Release Notes
Release Notes
Jul 24 2019
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* [2]Key Information
* [3]Release Announcements in 2019.3
* [4]Base Product Specifications in 2019.3
* [5]Compatibility Issues with Release 2019.3
* [6]SystemVerilog Defects Repaired in 2019.3
* [7]VHDL Defects Repaired in 2019.3
* [8]SystemC Defects Repaired in 2019.3
* [9]User Interface Enhancements in 2019.3
* [10]Document Revision History in 2019.3
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Key Information
* There is no licensing change between 10.7 and 2019.1 or 2019.2 or
2019.3. However, if you are migrating to 2019.3 from a release like
10.6 and older, please note that release 2019.3 uses FLEXnet
v11.14.1.3.
For floating licenses, it will be necessary to verify that the
vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd)
have FLEXnet versions equal to or greater than 11.14.1.3. If the
current FLEXnet version of your vendor daemon and lmgrd are less
than 11.14.1.3 then it will be necessary to stop your license
server and restart it using the vendor daemon and lmgrd contained
in this release.
If you use node locked licenses you don't need to do anything. This
release will update licensing to MSL v2017_1_patch2 with MGLS
v9.17_10.2.4 and PCLS v9.17.10.2.0
In summary, this release uses the following license versions:
+ FLEXnet v11.14.1.3
+ MSL v2017_1_patch2
+ MGLS v9.17_10.2.4
+ PCLS v9.17.10.2.0
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VHDL Compatibility
* QSIM-56691 - (source, results) Following execution of
uninstantiated procedures with OUT mode parameters not associated
with a type generic, and evaluation of generic procedures with OUT
mode parameters not associated with a type generic, actual
variables associated with the OUT parameters could be left
unchanged despite changes within the procedures. The compiler is
now generating code to correctly set the value of OUT mode
parameters in the above cases.
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