An introductory adder problem

a. Show that the expression for S in Eq. 11.6 is equivalent to the one in Eq. 11.1

S  ABCi  AB  BC i  ACi A  B  C i  

 
 ABCi  AB C i A  BA  B  C i   ABCi  A  B  C i  A B A  B  C i  
 
 ABCi  A C i  A B  B C i  A B A  B  C i  
 ABCi  ABC i  A BC i  A BC i  A BC i 
 ABCi  ABC i  A BC i  A BC i
 b. Convince yourself that the circuit in Fig. 11.4 implements Eq. 11.6. Size the
transistors such that each stage (carry and sum) has the same pull-up/pull-down
strength as a minimum-sized 2/1 inverter. Find the logical effort for each input
(consider the carry and sum stages separately).

8 8 8
6 6
8
6 8/3
3 8
6
8 2
2 2
2 3 1
2 2 2
2 2 2 3
2
3
1

Logical effort:

Carry Sum
A 16/3 A 21/3
B 16/3 B 21/3
Ci 5/3 Ci 21/3
Co 14/9
 c. Now consider the mirror adder in Fig. 11.6. Make sure that you understand what
it does. Size the transistors such that each stage (carry and sum) has the same
pull-up/pull-down strength as a minimum-sized 2/1 inverter. Find the logical
effort for each input (consider the carry and sum stages separately). How does it
compare to the architecture in Fig. 11.4?

4 4 4 4 4 6
4
4 4 4 6

2 2 2 3

2 2 2 2 2 2 3

Logical effort:

Carry Sum
A 12/3 A 15/3
B 12/3 B 15/3
Ci 6/3 Ci 15/3
Co 6/3

We can see that the mirror adder has lower logical effort for all inputs except Co.
However we should not forget the extra loading and delay of the additional inverters in
the complementary architecture. When those are included the mirror adder wins overall.
Complementary CMOS logic, Euler paths and logical effort
Given the CMOS gate below find the Euler paths and poly gates order so that diffusion is
uninterrupted:

Let’s draw the Euler graph, we can see that DABC is a consistent path in BOTH NMOS
and PMOS
In the sticks diagram below we can see the uninterrupted diffusions and the poly gates
order. Well and contacts are not shown.
For this problem we will use the following function: F  (a * b)  c * (d  e).
(Note:  stands for an XOR operation).
All signals and their complements are available as inputs.

a) Find a PDN configuration, which implements the function Y  A  B with four

transistors.

VDD
A B=AB+AB

B B A B

A A B A

PDN PUN
Note that for the given arrangement of the signals in the PUN circuit the connection
between the two branches can be omitted as shown in the figure above. We will not use
this feature in the solution.
b) Using the result from a), draw the complementary CMOS circuit that implements
the function F. Size it such that it has the same pull-up/pull-down strength as a
minimum sized 2/1 inverter.

A=ab
B=c(d+e)
VDD

8 d
c 4 a 4 4 b
8 e

a 8 d 8 8 e

b 8 c 8

a 4
a 3 3 b
b 4

d 4 4 e 3 d
c 1.5
c 4 3 e
 c) Determine the order of the input signals, which allows the largest number of
diffusions to be shared. Show the signal graphs used to arrive at your solution.

d a
e
b

VDD F
c
d

b c
e

GND

There is no path, which is consistent for both networks.

The path e d b a c a b c d e is consistent for the PDN and gives one discontinuity ( between
e and a) for the PUN. Therefore the layout will have three separate diffusion regions.
 d) For the sizing used in part b), find the logical efforts (g) for all of the inputs.

A (4+4)/3=8/3
B (4+4)/3=8/3
C (4+4)/3=8/3
D (4+8)/3=12/3
E (4+8)/3=12/3
A (8+3)/3=11/3
B (8+3)/3=11/3
C (8+1.5)/3=19/6
D (8+3)/3=11/3
E (8+3)/3=11/3