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DevOps Build Systems

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15 views7 pages

DevOps Build Systems

Uploaded by

tvinay22072005
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© © All Rights Reserved
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4th CHAPTER

1.paging

Paging is a memory-management scheme that permits the physical address


space of a process to be non contiguous. Paging avoids the considerable
problem of fitting memory chunks of varying sizes onto the backing store; most
memory-management schemes used before the introduction of paging suffered
from this problem. The problem arises because, when some code fragments or
data residing in main memory need to be swapped out, space must be found on
the backing store. The backing store also has the fragmentation problems.
Because of its advantages over earlier methods, paging in its various forms is
commonly used in most operating systems.

Basic Method:

The basic method for implementing paging involves breaking physical


memory into fixed-sized blocks called frames and breaking logical memory
into blocks of the same size called pages.

When a process is to be executed, its pages are loaded into any available
memory frames from the backing store. The backing store is divided into fixed-
sized blocks that are of the same size as the memory frames.
The hardware support for paging is illustrated in Figure

Every address generated by the CPU is divided into two parts: a page number
(p) and a page offset (d)

The page number is used as an index into a page table.

The page table contains the base address of each page in physical memory. This

base address is combined with the page offset to define the physical memory

address that is sent to the memory unit.


The page size (like the frame size) is defined by the hardware. The size of a
page is typically a power of 2, varying between 512 bytes and 16 MB per page,
depending on the computer architecture. The selection of a power of 2 as a page
size makes the translation of a logical address into a page number and page
offset particularly easy. If the size of logical address space is 2mand

a page size is 2n addressing units (bytes or ·words), then the high-order m - n

bits of a logical address designate the page number and then n low-order bits

designate the page offset. Thus the logical address is as follows:


An important aspect of paging is the clear separation between the user's view of
memory and the actual physical memory. The user program views memory as
one single space, containing only this one program The difference between the
user's view of memory and the actual physical memory is reconciled by the
address-translation hardware. The logical addresses are translated into physical
addresses. This mapping is hidden from the user and is controlled by the
operating system.

Since the operating system is managing physical memory, it must be aware of


the allocation details of physical memory-which frames are allocated, which
frames are available, how many total frames there are, and so on. This
information is generally kept in a data structure called a frame table. The frame
table has one entry for each physical page frame, indicating whether the latter is
free or allocated and, if it is allocated, to which page of which process or
processes. The operating system maintains a copy of the page table for each
process, just as it maintains a copy of the instruction counter and register
contents. This copy is used to translate logical addresses to physical addresses
whenever the operating system must map a logical address to a physical address
manually. It is also used by the CPU dispatcher to define the hardware page
table when a process is to be allocated the CPU. Paging therefore increases the
context-switch time.
2.Segmentation:
Segmentation is a memory-management scheme that supports this user view of
memory. A logical address space is a collection of segments. Each segment has
a name and a length. The addresses specify both the segment name and the
offset within the segment. The user therefore specifies each address by two
quantities: a segment name and an offset.

For simplicity of implementation, segments are numbered and are referred to by


a segment number, rather than by a segment name. Thus, a logical address
consists of a two tuple:

Segmentation -Hardware

Although the user can now refer to objects in the program by a two-dimensional
address, the actual physical memory is still, of course, a one-dimensional
sequence of bytes. Thus, we must define an implementation to map two
dimensional user-defined addresses into one-dimensional physical addresses.
This mapping is effected by a segment table. Each entry in the segment table
has a segment base and a segment limit. The segment base contains the starting
physical address where the segment resides in memory, whereas the segment
limit specifies the length of the segment. A logical address consists of two parts:
a segment number, s, and an offset into that segment, d. The segment number is
used as an index to the segment table. The offset d of the logical address must
be between 0 and the segment limit. If it is not, we trap to the operating system
(logical addressing attempt beyond end of segment). When an offset is legal, it
is added to the segment base to produce the address in physical memory of the
desired byte.
As an example, consider the situation We have five segments numbered from 0
through 4. The segments are stored in physical memory as shown. The segment
table has a separate entry for each segment, giving the beginning address of the
segment in physical memory (or base) and the length of that segment (or limit).
For example, segment 2 is 400 bytes long and begins at location 4300. Thus, a
reference to byte 53 of segment 2 is mapped onto location 4300 + 53 = 4353. A
reference to segment 3, byte 852, is mapped to 3200 (the base of segment 3) +
852 = 4052. A reference to byte 1222 of segment would result in a trap to the
operating system, as this segment is only 1,000 bytes long.

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