Arquitetura de Computadores I

Exercı́cios: Processador MIPS Single-Cycled

1. Para cada uma das instruções abaixo, mostre o valor de cada sinal (de dados e de controle) durante
a execução da instrução no processador MIPS single-cycled. Utilize as figuras em anexo.

(a) add $15, $20, $21

(b) sw $4, 40 ($10)
(c) lw $16, 100 ($19)
(d) beq $10, $11, 5
(e) j 25

2. Suponha que, no processador MIPS single-cycled, uma falha no hardware faz com que o sinal de
controle MemtoReg fique fixo em 0. Para cada instrução abaixo, indique se ela continua executando
corretamente neste processador ou não e justifique.

(a) add

Funciona, pois com MemtoReg em 0 pega o resultado da

ALU que é necessário para uma instrução do formato R

(b) slt

Funciona, pois com MemtoReg em 0 pega o resultado da

ALU que é necessário para uma instrução do formato R

(c) lw
Não funciona, pois para essa instrução a MemtoReg precisa
estar em 1 para ler da memória o que ocorre nessa instrução

(d) sw
Funciona, pois o sinal de MemtoReg não é importante para
essa instrução

(e) beq
Funciona, pois o sinal de MemtoReg não é importante para
essa instrução

(f) j

Funciona, pois o sinal de MemtoReg não é importante para

essa instrução
3. Para cada instrução abaixo, implemente-a no processador MIPS single-cycled.

• Mostre as alterações necessárias (se houver) no datapath, nas figuras em anexo.

• Mostre os valores dos sinais de controle para a execução da instrução, na tabela em anexo.
• Se você criar algum sinal de controle novo, mostre na tabela, o valor dele para todas as
instruções.

(a) Instrução: subi rt, rs, immediate

Significado: Reg[rt] = Reg[rs] - sign extend(immediate)
Formato: I
(b) Instrução: bne
(da forma definida no conjunto de instruções MIPS)
(c) Instrução: jr rs
Significado: PC = Reg[rs]
Formato: I (não usar formato R)

4. A instrução swinc (store word com incremento) é definida abaixo.

Instrução Formato Significado

swinc rt, (rs +) I Mem[ Reg[rs] ] = Reg[rt] ; Reg[rs] = Reg[rs] + 4

Implemente esta instrução no processador MIPS single-cycled.

• Mostre as alterações necessárias (se houver) no datapath, na figura em anexo.

• Mostre os valores dos sinais de controle para a execução da instrução, na tabela em anexo.
• Se você criar algum sinal de controle novo, mostre na tabela, o valor dele para todas as
instruções.
Exercı́cio 1(a)
Instruction [25-0] Shift Jump address [31-0] endereço alvo do j
PC address 26 left 2 32 32
28 0 1
PC + 4 [31-28] PC + 4
M M
Add PC + 4 4 u u
32 32 endereço x x novo
alvo do beq PC
4 Add 1 0

RegDst Shift PCSrc

Jump left 2
32
Branch
MemRead
Instruction [31-26] MemtoReg
Control
op ALUOp 2
MemWrite
ALUSrc
RegWrite

Instruction [25-21] Read

Read register1
PC address
rs Read
Instruction [20-16] data 1
Read
register2 Equal
Instruction rt 0
[31-0] ALU Read
M Read 0 Address 1
u Write Result data
Instruction register data 2 M M
Instruction [15-11] x u u
Memory 1 Data x
rd Register x
Write 1 Memory 0
data File
Write
data
Instruction [15-0] 16 32
Sign
4
immediate extend ALU
Control ALUOperation
Instruction [5-0]
funct

Exercı́cio 1(b)
Instruction [25-0] Shift Jump address [31-0] endereço alvo do j
PC address 26 left 2 32 32
28 0 1
PC + 4 [31-28] PC + 4
M M
Add PC + 4 4 u u
32 32 endereço x x novo
alvo do beq PC
4 Add 1 0

RegDst Shift PCSrc

Jump left 2
32
Branch
MemRead
Instruction [31-26] MemtoReg
Control
op ALUOp 2
MemWrite
ALUSrc
RegWrite

Instruction [25-21] Read

Read register1
PC address
rs Read
Instruction [20-16] data 1
Read
register2 Equal
Instruction rt 0
[31-0] ALU Read
M Read 0 Address 1
u Write Result data
Instruction register data 2 M M
Instruction [15-11] x u u
Memory 1 Data x
rd Register x
Write 1 Memory 0
data File
Write
data
Instruction [15-0] 16 32
Sign
4
immediate extend ALU
Control ALUOperation
Instruction [5-0]
funct
Exercı́cio 1(c)
Instruction [25-0] Shift Jump address [31-0] endereço alvo do j
PC address 26 left 2 32 32
28 0 1
PC + 4 [31-28] PC + 4
M M
Add PC + 4 4 u u
32 32 endereço x x novo
alvo do beq PC
4 Add 1 0

RegDst Shift PCSrc

Jump left 2
32
Branch
MemRead
Instruction [31-26] MemtoReg
Control
op ALUOp 2
MemWrite
ALUSrc
RegWrite

Instruction [25-21] Read

Read register1
PC address
rs Read
Instruction [20-16] data 1
Read
register2 Equal
Instruction rt 0
[31-0] ALU Read
M Read 0 Address 1
u Write Result data
Instruction register data 2 M M
Instruction [15-11] x u u
Memory 1 Data x
rd Register x
Write 1 Memory 0
data File
Write
data
Instruction [15-0] 16 32
Sign
4
immediate extend ALU
Control ALUOperation
Instruction [5-0]
funct

Exercı́cio 1(d)
Instruction [25-0] Shift Jump address [31-0] endereço alvo do j
PC address 26 left 2 32 32
28 0 1
PC + 4 [31-28] PC + 4
M M
Add PC + 4 4 u u
32 32 endereço x x novo
alvo do beq PC
4 Add 1 0

RegDst Shift PCSrc

Jump left 2
32
Branch
MemRead
Instruction [31-26] MemtoReg
Control
op ALUOp 2
MemWrite
ALUSrc
RegWrite

Instruction [25-21] Read

Read register1
PC address
rs Read
Instruction [20-16] data 1
Read
register2 Equal
Instruction rt 0
[31-0] ALU Read
M Read 0 Address 1
u Write Result data
Instruction register data 2 M M
Instruction [15-11] x u u
Memory 1 Data x
rd Register x
Write 1 Memory 0
data File
Write
data
Instruction [15-0] 16 32
Sign
4
immediate extend ALU
Control ALUOperation
Instruction [5-0]
funct
Exercı́cio 1(e)
Instruction [25-0] Shift Jump address [31-0] endereço alvo do j
PC address 26 left 2 32 32
28 0 1
PC + 4 [31-28] PC + 4
M M
Add PC + 4 4 u u
32 32 endereço x x novo
alvo do beq PC
4 Add 1 0

RegDst Shift PCSrc

Jump left 2
32
Branch
MemRead
Instruction [31-26] MemtoReg
Control
op ALUOp 2
MemWrite
ALUSrc
RegWrite

Instruction [25-21] Read

Read register1
PC address
rs Read
Instruction [20-16] data 1
Read
register2 Equal
Instruction rt 0
[31-0] ALU Read
M Read 0 Address 1
u Write Result data
Instruction register data 2 M M
Instruction [15-11] x u u
Memory 1 Data x
rd Register x
Write 1 Memory 0
data File
Write
data
Instruction [15-0] 16 32
Sign
4
immediate extend ALU
Control ALUOperation
Instruction [5-0]
funct
 Instruction [25-0] Shift Jump address [31-0] endereço alvo do j
PC left 2 32 32
address 26 28 0 1
PC + 4 [31-28] PC + 4
Exercı́cio 3(a)

4 M M
Add PC + 4 u u
32 32 endereço x x novo
alvo do beq PC
4 Add 1 0

RegDst Shift PCSrc

Jump left 2
32
Branch
MemRead
Instruction [31-26] MemtoReg
Control
op ALUOp 2
MemWrite
ALUSrc
RegWrite

Instruction [25-21] Read

Read register1
PC address
rs Read
Instruction [20-16] data 1
Read
register2 Equal
Instruction rt 0
[31-0] ALU Read
M Read 0 Address 1
u Write Result data
Instruction register data 2 M M
Instruction [15-11] x u u
Memory 1 Data x
rd Register x
Write 1 Memory 0
data File
Write
data
Instruction [15-0] 16 32
Sign
extend 4
immediate ALU
Control ALUOperation
Instruction [5-0]
funct
 Instruction [25-0] Shift Jump address [31-0] endereço alvo do j
PC left 2 32 32
address 26 28 0 1
PC + 4 [31-28] PC + 4
M M
Exercı́cio 3(b)

Add PC + 4 4 u u
32 32 endereço x x novo
alvo do beq PC
4 Add 1 0

RegDst Shift PCSrc

Jump left 2
32
Branch
MemRead
Instruction [31-26] MemtoReg
Control
op ALUOp 2
MemWrite
ALUSrc
RegWrite

Instruction [25-21] Read

Read register1
PC address
rs Read
Instruction [20-16] data 1
Read
register2 Equal
Instruction rt 0
[31-0] ALU Read
M Read 0 Address 1
u Write Result data
Instruction register data 2 M M
Instruction [15-11] x u u
Memory 1 Data x
rd Register x
Write 1 Memory 0
data File
Write
data
Instruction [15-0] 16 32
Sign
extend 4
immediate ALU
Control ALUOperation
Instruction [5-0]
funct
 Instruction [25-0] Shift Jump address [31-0] endereço alvo do j
PC left 2 32 32
address 26 28 0 1
PC + 4 [31-28] PC + 4
Exercı́cio 3(c)

4 M M
Add PC + 4 u u
32 32 endereço x x novo
alvo do beq PC
4 Add 1 0

RegDst Shift PCSrc

Jump left 2
32
Branch
MemRead
Instruction [31-26] MemtoReg
Control
op ALUOp 2
MemWrite
ALUSrc
RegWrite

Instruction [25-21] Read

Read register1
PC address
rs Read
Instruction [20-16] data 1
Read
register2 Equal
Instruction rt 0
[31-0] ALU Read
M Read 0 Address 1
u Write Result data
Instruction register data 2 M M
Instruction [15-11] x u u
Memory 1 Data x
rd Register x
Write 1 Memory 0
data File
Write
data
Instruction [15-0] 16 32
Sign
extend 4
immediate ALU
Control ALUOperation
Instruction [5-0]
funct
 Instruction [25-0] Shift Jump address [31-0] endereço alvo do j
PC left 2 32 32
address 26 28 0 1
Exercı́cio 4

PC + 4 [31-28] PC + 4
4 M M
Add PC + 4 u u
32 32 endereço x x novo
alvo do beq PC
4 Add 1 0

RegDst Shift PCSrc

Jump left 2
32
Branch
MemRead
Instruction [31-26] MemtoReg
Control
op ALUOp 2
MemWrite
ALUSrc
RegWrite

Instruction [25-21] Read

Read register1
PC address
rs Read
Instruction [20-16] data 1
Read
register2 Equal
Instruction rt 0
[31-0] ALU Read
M Read 0 Address 1
u Write Result data
Instruction register data 2 M M
Instruction [15-11] x u u
Memory 1 Data x
rd Register x
Write 1 Memory 0
data File
Write
data
Instruction [15-0] 16 32
Sign
extend 4
immediate ALU
Control ALUOperation
Instruction [5-0]
funct
 Exercı́cios 3 (a,b,c) e 4

Instrução Sinais de Controle gerados pela Unidade de Controle Principal

RegDst ALUSrc MemToReg RegWrite MemRead MemWrite Branch Jump ALUOp

Formato R 1 0 0 1 0 0 0 0 10

lw 0 1 1 1 1 0 0 0 00

sw X 1 X 0 0 1 0 0 00

beq X 0 X 0 0 0 1 0 01

j X X X 0 0 0 0 1 XX
Exercı́cios 3 (a,b,c) e 4

Unidade de Controle da ALU

Sinais de entrada Sinal de saı́da Operação que
Instrução
ALUOp funct ALUOperation ALU realiza
lw 00 – 0010 soma
sw 00 – 0010 soma
beq 01 – 0110 subtração
add 10 100000 0010 soma
sub 10 100010 0110 subtração
and 10 100100 0000 AND
or 10 100101 0001 OR
slt 10 101010 0111 set on less than