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UBC Lecture 03 MOS PartII

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10 views13 pages

UBC Lecture 03 MOS PartII

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gemg.tian
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© © All Rights Reserved
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EECE 481

MOS Basics – part 2


Lecture 3

Reza Molavi
Dept. of ECE
University of British Columbia
[email protected]

Slides Courtesy : Dr. Res Saleh (UBC), Dr. D. Sengupta (AMD), Dr. B. Razavi (UCLA)
EECE 481 Lecture 3 1
MOS Current - Review

In general, the saturation region is


entered when either the channel is
pinched-off or the carriers achieved
velocity saturation.

Note that in extreme case (EcL >> VGS, VDS) both equations translate to those of long channel
devices
EECE 481 Lecture 3 2
MOS Current – Short Channel Effects

The mobility of electrons is 4X higher than that of holes, i.e. in long channel
regime the current of 1X NMOS is 4times a 1X PMOS
However, early velocity saturation of electrons makes this ratio smaller in short channel devices

Current ratio of two 1X devices

Roughly 2.4 for short channel devices

EECE 481 Lecture 3 3


MOS Current - Sub threshold

Transistor turn-on/turn-off switching is a continuous process. At around Vth


(and even below it) there is still significant leakage current.

(Board Notes)

What is an ideal slope n and slope factor?


EECE 481 Lecture 3 4
MOS Capacitances

- Each MOS device possess several junction and oxide capacitances (depends on dielectric
and geometry) specified in units of fF/µm
- The charge/discharge of internal capacitances limits the switching speed

EECE 481 Lecture 3 5


Gate (Oxide) Capacitance and DSM Evolution

Gate Capacitance

5µm CMOS

0.35µm CMOS

0.18µm CMOS

The unit capacitance has remained constant over two decades! (part of constant field scaling
plan introduced in 1970)

EECE 481 Lecture 3 6


Gate Capacitance in different regions of
operation
The total capacitace (Cg) is broken into three
components Cgb, Cgs and Cgd

Why Does Cgs and Cds change as we


move from one region of operation
to another?

(Board Notes)

EECE 481 Lecture 3 7


Junction Capacitance

A pn junction when forward biased shows the following I-V characteristics

A pn junction when reverse-biased has a leakage current


and a wider depletion region resulting in a voltage-
dependant junction capacitor

Capacitance of a pn junction
(in case of abrupt junction m=1/2)

(Board Notes)
Diode (junction) built-in potential Junction capacitance vs junction potentiai

EECE 481 Lecture 3 8


Junction Capacitance

Bottom plate area Sidewall area

If this is a voltage-dependant capacitance, how do


model it as the device switches between different
voltages?
1) Standard average (arithmetic mean)
2) Calculate the effective capacitance from Ceff = ΔQ / ΔV

(Board Notes)
EECE 481 Lecture 3 9
Junction Capacitance - Example

EECE 481 Lecture 3 10


Junction Capacitance – Example cont’d

Exercise: Use the integral (effective capacitance technique) and compare against the average
here

EECE 481 Lecture 3 11


Overlap Capacitance

-The lateral diffusion creates an overlap between gate and drain (source areas) creating a parasitic
capacitance called overlap capacitance
- The proximity of drain (source) regions to the sidewall of gate in DSM contact creates another
parasitic cap called fringe capacitance

EECE 481 Lecture 3 12


Summary

• The current capability ratio of NMOS and PMOS decreases (due


to velocity saturation) as we move further into short channel
regime.
• There is an exponential dependence of leakage current on VGS
in sub threshold region.
• A MOS device has three main physical types of capacitance
• The gate-oxide capacitance is re-distributed between source
and drain, i.e. CGS and CDS vary, as device moves from linear to
saturation region.
• The junction capacitance is voltage-dependant; we need to find
an effective (average) capacitance for switching devices.
• The overlap/fringe capacitance becomes more important in
DSM technologies.

EECE 481 Lecture 3 13

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