IJSART - Volume 2 Issue 10 –OCTOBER 2016 ISSN [ONLINE]: 2395-1052

FPGA Implementation of I2C and SPI Protocols

using VHDL
Satish M Ghuse1, Prof. Surendra K. Waghmare2
1, 2
Department of ENTC
1, 2
SPPU/G.H.Raisoni College of Engineering and Management, Pune, Maharashtra/Zone, India

Abstract- I2C and SPI are the serial communication protocols digital electronics systems, and they might probably will
that are commonly used for both intra-chip and inter-chip continue to compete in the future, I2C and SPI both are
low/medium bandwidth data transfer. It can support bi- actually complementary for this kind of communication. The
directional data transfers at up to 100 Kbit/s in the standard- I2C and SPI protocol specifications are well defined.
mode, up to 400 Kbit/s in the Fast-mode, up to 1 M bit/s in the Consequently, they will not be discussed here. But, a quick
Fast-mode plus, or up to 3.4 M bit/s in the High-speed mode. overview is provided in table 1.
These protocols have a preferable speed and power Although the literature of I2C and SPI is old (early 1980), to
consumption capability when implemented with different the best of the writers knowledge there is no comprehensive
devices but their speed is low, when used with BIST or comparison of I2C and SPI problem. By comprehensive
checksums. comparison we mean a treatment that start from Philips and
Motorola specifications and goes down to the actual ASIC or
In the earlier systems speed and delay was not taken FPGA implementation, linguistics the two designs and then
into the consideration and the protocol was implemented as it considering similarities of the obtained results based on
is in the standard mode. We are about to implement the I2C included protocol features.
and SPI protocols efficiently so that the speed of the data
transfer increases and there delay is reduced. In order to do
so we have proposed a design in which we are using pipelined
buffer in between Master and Slave so that it will reduce the
delay and there would be synchronization and increase in the
speed of data transfer as the delay in data transfer decreases.
The pipelined buffer results in the speed enhancement for the
critical paths. Using this pipelined buffer the data transferred
from master is first stored in buffer and then transferred to the
slave and vice-versa. The delay is in the form of nanoseconds
in which when used pipelined buffer in the system route delay
is neglected and only logic delay is considered. The speed is
calculated using the delay of the system in the form of Mbps or
Gbps depending on the delay. The delay report for both the
protocols are taken from synthesis report generated in the
Xilinx software and the simulation of the system is done in the
model-sim software.

Keywords- Xilinx Software 14.5, Model Sim Software, I2C Serial

communication Protocol, SPI Serial Communication Protocol,
Pipelined Buffer

I. INTRODUCTION
There are many software applications developed in
Today, at the low end of the communication
the implementation of the communication protocols SPI and
protocols we can find two worldwide standards: Inter
I2C. In general, these researches are focused on the
integrated circuits (I2C) and serial peripheral interface (SPI).
comparisons and implementations of different architectures in
Both protocols are well specified for communication between
order to meet characteristics required by current technologies.
integrated circuits for low or medium data transfer speed with
onboard peripherals. The two protocols co-exist in modern

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IJSART - Volume 2 Issue 10 –OCTOBER 2016 ISSN [ONLINE]: 2395-1052

In 2006, Oudjida et al. developed a code to As required higher performance of TD-LTE

implement to medium or low speed a transmitter slave I2C in communication system, the hardware requirements are getting
a VLSI-architecture that allowed meeting some specific terms higher and higher. TD-LTE system of base and signal includes
that were not implemented in other designs such as drive noise the decoding operations and FFT transform complex
filtering, a data unit, a unit equipment side interface, a control algorithms, bringing in a huge amount of computation. As far
unit, etc. as the current processing rate of hardware is concerned, it is
difficult to use Digital Signal Processing or FPGA to finish the
More recently, in 2009 Oudjida et al., present an task separately. Based on the systematic evaluation, we
implementation of the SPI and I2C protocols in different propose a new hardware processing platform based on
FPGA devices, help designers to choose the right architecture DSP,FPGA and ARM. In this way, the DSP, FPGA and ARM
for their systems. To do this, they designed the code in Verilog can play to their strengths, work together and achieve great
HDL (according to each protocol) for the slave SPI and I2C to efficiency. The TD-LTE Comprehensive Test Instrument is
the different FPGA devices, considering similarities their just based on the hardware platform[6].
functionality in response times and clock settings, concluding
that logic can predict certain behaviors for master devices SPI or Serial-Peripheral Interface is a worldwide
from the results of the slaves[2]. accepted standard communication protocol. SPI protocol was
invented by Motorola. SPI protocol is considered as one of the
Then in 2011 Lazaro et al.[1], presented a new design very best among the systems that are connected to a number of
in Verilog I2C protocol, focusing on the security of the devices and make the communication smooth and fast. SPI as
electronic communication devices, integrating AES-GCM well as others serial protocols such as I2C and 1-wire for
authentication and encryption algorithms. To do this, author urgency are well fitted for data communications from
adapted the features of the I2C protocol with verification integrated circuits for low or medium data transfer speed to
techniques and secret data, comparing with the final design peripherals which are on chip board.
with original protocol, and they concluded that their work
reduces the memory of data flow and it is easily implemented Several works have been done using VHDL in
in FPGA[3]. designing SPI. A comparison between SPI and I2C
Implementation over FPGA is shown in TABLE 1. On that
Zhou et al., developed a verification environment paper, a comparative study of those two protocols on FPGA
considering many different and connected parts of electronic platform is presented and the entire design has been coded in
systems from the master SPI interface, and integrate Verilog VHDL. For various controlling purposes SPI is implemented.
with object-oriented programming (OOP). To achieve this, This is new approach of designing SPI with embedded BIST
they started with the functional description of the requirements capability using Field Programmable Gate Array (FPGA)
for the master SPI and environment design, and they technology. Testing of a circuit has become increasingly tough
implemented the APB controller in OOP classes[4]. The SPI as the scale of integration grows.
Master interface was developed and implemented in FPGA
Verilog. Finally, it is important to take into account that in the SPI with the BIST capability provides the specified
above mentioned works, the design makers have used the testability requisites and lowest-price with the highest
method of hardware description (Verilog HDL), which helps performance implementation. Much lesser blocks and modules
to implement and to model the concurrent behavior of the are used to design this SPI so that the testing complexity can
electronic embedded devices, especially when it is a new be reduced. This system can be fabricated into a single chip.
architecture design.
II. PROPOSED SYSTEM OF I2C PROTOCOL
Software Radio technique is mainly based on recent
communication theory, a wireless device with configurable The proposed system of I2C protocol consist of the
hardware platform, which can go across a variety of master and slave in whom we have introduced a pipelined
communication standards[5]. The basic principle is to make buffer in the bus SDA and SCL. The 8 bit address is used as
sure the bandwidth close to the antenna as much as possible, an input to the system. The buffer stores the data transferred
to use the software instead of hardware for signal processing. from the master or from slave to master. Due to which there is
As lower cost, greater susceptible of modification or no data lose in between the data transfer. As the delay of the
adaptation and higher performance, it was been widely used in system gates reduced the speed of the data transfer or Transfer
many areas.TD-LTE communication system also uses the rate of the system increase.
software radio technology.

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IJSART - Volume 2 Issue 10 –OCTOBER 2016 ISSN [ONLINE]: 2395-1052

Below is the proposed design for I2C Protocol. TABLE 2: Signal Description

Fig 1. Proposed design for I2C Protocol.

III. PROPOSED SYSTEM OF SPI PROTOCOL

The proposed system of SPI protocol consist of the Fig 4.Simulation Result of Standard I2C Protocol.
master and slave in whom we have introduced a pipelined
buffer in the bus MOSI and MISO. The 1 bit address is used 4.1 Simulation Result for I2C Protocol with Pipelined
as an input to the system. The buffer stores the data transferred Buffer
from the master .Due to which there is no data lose in between
the data transfer. As the delay of the system gates reduced the The below is the simulation result of the I2C protocol
speed of the data transfer or Transfer rate of the system which comprises of the pipelined buffer. In this result will are
increase. able to see the transmitted address getting fully received and
also some data stored in buffer.
Below is the proposed design for SPI Protocol.
Table 3: Signal Description for I2C Protocol with Pipelined
Buffer

Fig 3.Proposed design for SPI Protocol.

IV. SIMULATION RESULT FOR STANDARD I2C

PROTOCOL

Below is the Simulation result of the standard I2C

Protocol it comprise of Start cycle, Read cycle, write cycle
and reset. Fig:4.1. Simulation Result for I2C Protocol with Pipelined
Buffer
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IJSART - Volume 2 Issue 10 –OCTOBER 2016 ISSN [ONLINE]: 2395-1052

4.2 Comparison

Below table shows the comparison between standard

I2C Protocol Delay and Speed with the proposed Design of
the system containing Pipelined buffer.

Table 4: Comparison

Fig 5 Simulation Result FOR Standard SPI Protocol

5.1 Simulation Result for SPI Protocol with Pipelined

Buffer

Below is the Simulation result of the SPI Protocol

with Pipelined Buffer.

TABLE 6: Signal Description for SPI with Pipelined Buffer

Fig4.2 Graphical Representation I2C Delay and Speed of

System Containing Pipelined Buffer.

V. SIMULATION RESULT FOR STANDARD SPI

PROTOCOL

Below is the Simulation result of the standard SPI Protocol.

TABLE 5: Signal Description for SPI

Fig 6

5.2 Comparison

Below table shows the comparison between standard

SPI Protocol Delay and Speed with the proposed Design of the
system containing Pipelined buffer.

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IJSART - Volume 2 Issue 10 –OCTOBER 2016 ISSN [ONLINE]: 2395-1052

Table 8: Comparison I am equally indebted to Prof. Vijay Kumar Joshi, M.

E. Coordinator Electronics and Telecommunication
Department, for necessary help, providing, facilities and time
to time valuable guidance. No word be good enough to
express my deep gratitude to our respected principal Dr. R. S.
Bichkar for his kind blessings, inspiration and necessary
support whenever needed.

REFERENCES

[1] Chen Fatang, YangLinyu “The Design of I2C Bus in the

TD-LTE Comprehensive test Instrument” 978-0-765-
4464-9/11 2011 IEEE DOI10.1109/BCG-In.2011.165
662.

[2] A.K Oudjida, M.L Berrandjia, R. Tiar, A. Liacha, K.

Tahraui “FPGA Implementation of I2C and SPI
Protocols:A Comparative Study” 978-1-4244-5091-
6/092009 IEEE

Fig 8.Graphical Representation of Delay and Speed with the [3] Zheng-Wei HU in “I2C Protocol Design for Reusability”
proposed Design of the system containing Pipelined buffer. 978-0-7695-4261-4/10 2010 IEEE.

VI. CONCLUSIONS [4] Wasim Hussain, YvonSavaria, Yves Blaqui`ere in” An

Interface for the I2C Protocol in theWaferBoardTM” 978-
The results of the simulations and from the 1-4673-5762-3/13/$31.00 ©2013 IEEE.
comparison tables we can conclude that the above system
works as per the requirement. The decrease delays and [5] Sindhu, Dr. Vijaya Prakash A M and Ankit K v, Proposed
increase in transfer rate can be seen from comparison and as “ASIC Implementation of I2C Master Bus Controller
well as the synthesis report illustrates the systems Firm IP Core” International Journal of VLSI design and
requirements more clearly. The design of both the protocols Communication Systems (VLSICS) Vol.6 No. 4, August
using VHDL simplifies the design process. If a new 2015.
technology emerges, designers do not need to redesign the
circuit. He simply input the design program to the logic [6] Tatiana Leal-Del Rio, Gustavo Juarez-Gracia, L.Noe
synthesis tool and creates a new gate level netlist using the olive Moreno, “Implementation of communication
new fabrication technology. The logic synthesis tool will protocols SPI and I2C using a FPGA by the HDL-Verilog
optimize the circuit in area and timing for the new technology. Language” pp.31-41; rec. 2014-06-19; 2014-07-21.
Through this implementation we can conclude that the system Research in computer Science 75 (2014)
can be used for serial communication for faster transfer of
data. This also takes less delay because of which the speed of
Satish M. Ghuse received the B.E degree in Electronics
the I2C and SPI protocols has been increased.
Engineering from Om College of Engineering, Wardha in
2013 and pursuing M.E in Electronics and Telecommunication
ACKNOWLEDGMENTS
with Specialization in VLSI and Embedded Systems from G.H
Raisoni College of Engineering and Management, Pune
I would like to take this opportunity to thank my
University.
guide Prof. SurendraK. Waghmare GHRCEM, Pune for his
valuable guidance for this project. This project could not be
completed in time but due to the sincere hard work of the
teaching staff. Special Thanks to our Teaching, non-teaching
staff, friends and parents who helped us all the time and in
every way for this successful attempt and completion of this
project.

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