D SUDHAKR

Asst. Professor
MGIT.
ARM-Cortex Processors/controllers
 The ARM-Cortex microcontroller is a most popular
microcontroller in the digital embedded system world
and most of the industries prefer only ARM
microcontrollers since it consists of enormous features
to implement products with an advanced appearance.

 The ARM microcontrollers are cost sensitive and high

performance devices which are used in a wide range of
application such as industrial instrument control
systems, wireless networking and sensors and
automotive body system etc.
Introduction to ARM Microcontroller
 The ARM stands for Advanced RISC machine and it is a 32-
bit reduced instructions set computer (RISC) microcontroller.

 It was first introduced by the Acron computers’ organization in

1987.

 The ARM is a family of the microcontroller developed by the

different manufacturers such as ST microelectronics, Motorola
and so on.

 The ARM microcontroller architecture come with a few different

versions such as ARMv1, ARMv2 , ARMv3, ARMv4 ARMv5,
ARMv6 , ARMv7, ARMv8 and each one has its own advantage
and disadvantages.
 The ARM cortex microcontroller is an advanced
microcontroller in the ARM family, which is developed
by the ARMv7 architecture. The ARM cortex family
divided into three sub-families such as;
 ARM-Cortex A-series
 ARM-Cortex R-series
 ARM-Cortex M-series
ARM-Cortex A-series

 The Application profile defines an architecture aimed

at high performance processors, supporting a virtual
memory system using a Memory Management Unit
(MMU) and therefore capable of running fully featured
operating systems.

 Support for the ARM and Thumb instruction sets is

provided.
ARM-Cortex R-series
 The Real-time profile defines an architecture aimed at
systems that require deterministic timing and low
interrupt latency.

 There is no support for a virtual memory system, but

memory regions can be protected using a simple
Memory Protection Unit (MPU).
ARM-Cortex M-series
 The Microcontroller profile defines an architecture
aimed at low cost systems, where low-latency interrupt
processing is vital.

 It uses a different exception handling model to the

other profiles and supports only a variant of the
Thumb instruction set.
Three architecture profiles:
A, R and M.
The ARM Cortex-A
 The ARM Cortex-A is a group of 32-bit and 64-bit RISC
ARM processor cores licensed by Arm Holdings.

 32-bit cores:
ARM Cortex-A5, A7, A8, A9,A12, A15, A17 ,A32

64-bit cores:
ARM Cortex-A35, A53,A55,A57, A72, A73,75, A76 and A77.
 The main distinguishing feature of the ARM-A core
compared to ARM Cortex-R cores and ARM Cortex-M
cores, is
 only the ARM-A core includes a memory management
unit (MMU).

 Many modern operating systems require a MMU to

run.
The ARM Cortex-A
ARMv7-A architecture:
 The Cortex-A5 / A7 / A8 / A9 / A12 / A15 / A17 cores
implement the ARMv7-A architecture.

ARMv8-A architecture:
 The Cortex-A32 /A34 / A35 / A53 / A57 / A72 / A73 cores
implement the ARMv8-A architecture.

ARMv8.2-A architecture:
 The Cortex-A55 / A65 / A75 / A76 /A77 cores implement
the ARMv8.2-A architecture.
The Cortex-A5 processor
 The Cortex-A5 processor is the smallest ARM multi-
core applications processor.

 Devices based on this processor are typically low-cost,

capable of delivering the internet to the widest possible
range of devices from low-cost entry-level smart phones
and smart mobile devices, to embedded, consumer and
industrial devices.
The Cortex-A5 processor
The Cortex-A5 processor
SCU
 Snoop Control Unit (SCU) The SCU maintains coherency between all the data
caches in the cluster. The SCU contains buffers that can handle direct cache-to-
cache transfers between cores without having to read or write data to the L3
cache.
ACP
 Accelerator Coherency Port The Accelerator Coherency Port (ACP) is an
optional slave interface. The ACP provides direct memory access to cacheable
memory. The SCU maintains cache coherency by checking ACP accesses for
allocation in the core and L3 caches.
AMBA
 The ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-
standard, on-chip interconnect specification for the connection and
management of functional blocks in system-on-a-chip (SoC) designs. It
facilitates development of multi-processor designs with large numbers of
controllers and components with a bus architecture.
Cortex-A5 processor features:
 Full application compatibility with other Cortex-A series
processors.

 Multiprocessing capability for scalable, energy efficient

performance.

 Optional Floating-point or NEON units for media and

signal processing.

 High-performance memory system including caches and

memory management unit.

 High value migration path from older ARM processors.

ARM-Cortex A-series
 The ARM Cortex-A Series is a family of applications processors for
complex OS and user applications. The Cortex-A family processors
support the ARM and Thumb instruction sets, incorporating Thumb 2-
technology.

 The ARM Cortex-A5 processor is a high-performance, low-power,

ARM macrocell with an L1 cache subsystem that provides full virtual
memory capabilities. The Cortex-A5 processor implements the
ARMv7-A architecture profile and can execute 32-bit ARM instructions
and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the
smallest member of the Cortex-A processor family.

 The ARM Cortex-A7 MPCore processor is fully compatible with

other Cortex-A family of processors and incorporates all of the features
of the high-performance Cortex-A15 MPCore processor including
virtualization, Large Physical Address Extension (LPAE), NEON Media
Processing Engine (MPE) Advanced SIMD, and AMBA 4 ACE
coherency support. The Cortex-A7 MPCore processor implements the
ARMv7-A architecture profile.
ARM-Cortex A-series
 The ARM Cortex-A8 processor is a high-performance, low-power,
cached application processor that implements the ARMv7-A
architecture profile and provides full virtual memory capabilities.
 The ARM Cortex-A9 processor is a very high-performance, low-
power, ARM macrocell with an L1 cache subsystem that provides full
virtual memory capabilities. The Cortex-A9 processor implements the
ARMv7-A architecture profile and can execute 32-bit ARM instructions,
16-bit and 32-bit Thumb instructions, and 8-bit Java bytecodes in
Jazelle state.
 The ARM Cortex-A15 MPCore processor has an out-of-order
superscalar pipeline with a tightly-coupled low-latency level-2 cache
that can be up to 4MB in size. The Cortex-A15 MPCore processor
implements the ARMv7-A architecture profile.
Key features of the Cortex-A family:
 Scalable clusters supporting single and multi-core configurations
 RISC cores with support for Armv7-A and Armv8-A architecture
 Full backward compatibility with code from previous Arm
processors
 VFP and Neon units to execute floating-point and Advanced
SIMD instruction sets
 Optional Cryptographic accelerator engines supporting
algorithms like AES, SHA1 and SHA2-256
 Memory Management Support (MMU) supporting virtual
address and physical address spaces with various page sizes
 Hardware translation table walking for virtual to physical
address translation
 Big-endian and little-endian data access support
 Unaligned access support for basic load/store instructions
Key architectural points of ARM
Cortex-A series processors
A number of key points are common to the Cortex-A family of devices:
• 32-bit RISC core, with 16 × 32-bit visible registers with mode-based register banking.
• Modified Harvard Architecture (separate, concurrent access to instructions and data).
• Load/Store Architecture.
• Thumb-2 technology as standard.
• VFP and NEON options.
• Backward compatibility with code from previous ARM processors.
• 4GB of virtual address space and a minimum of 4GB of physical address space.
• Hardware translation table walking for virtual to physical address translation.
• Virtual page sizes of 4KB, 64KB, 1MB and 16MB. Cacheability attributes and access
permissions can be set on a per-page basis.
• Big-endian and little-endian data access support.
• Unaligned access support for basic load/store instructions.
• Symmetric Multi-processing (SMP) support on MPCore™ variants, that is, multi-core
versions of the Cortex-A series processors, with full data coherency at the L1 cache level.
Automatic cache and Translation Lookaside Buffer (TLB) maintenance propagation
provides high efficiency SMP operation.
ARM Cortex processors details

https://www.arm.com/products/silicon-ip-cpu
ARM-Cortex R-series
ARM-Cortex R4-Processor
ARM-Cortex R4-Processor
ARM-Cortex R-series
 The ARM Cortex-R Series is a family of embedded processors for real-time
systems. The Cortex-R family processors support the ARM and Thumb
instruction sets.

 The ARM Cortex-R5 processor is a high-performance real-time processor for

use in embedded systems.
 The ARM Cortex-R5F processor is a Cortex-R5 processor with a floating
point unit (FPU).

 The ARM Cortex-R4 processor is a mid-range real-time processor for use in

deeply embedded systems.
 The ARM Cortex-R4F processor is a Cortex-R4 processor with a floating
point unit (FPU).

 The ARM Cortex-R7 MPCore processor is a high performance real-time

multiprocessor for use in a vast range of deeply embedded applications.
Cortex-M0 processor
Cortex-M0 processor
Cortex-M series processors
 ARM documentation set for the ARM Cortex-M series of processors, including the ARM Cortex-M0,
ARM Cortex-M0+, ARM Cortex-M1, ARM Cortex-M3, and ARM Cortex-M4 processors.
 The ARM Cortex-M Series is a family of deeply embedded processors optimized for cost sensitive
applications. These processors support the Thumb instruction set only.
 The Cortex-M System Design Kit contains a collection of AMBA infrastructure components,
baseline peripherals and example system designs to help accelerate the development of Cortex-M
based systems.

 The ARM Cortex-M4 processor is a low-power processor that features low gate count, low interrupt
latency, and low-cost debug. The Cortex-M4F is a processor with the same capability as the Cortex-
M4 processor, and includes floating point arithmetic functionality. These processors are intended for
applications requiring digital signal processing functionality.

 The ARM Cortex-M3 processor is a low-power processor that features low gate count, low interrupt
latency, and low-cost debug. It is intended for deeply embedded applications that require fast
interrupt response, including microcontrollers and automotive and industrial control systems.

 The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a
small processor integrated into an FPGA.

 The ARM Cortex-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area and power
consumption optimized processor, with a rich set of configuration options.
 The ARM Cortex-M0 processor is a very low gate count, energy efficient processor that is intended
for microcontroller and deeply embedded applications that require an area optimized processor.
 ARM Architecture and Processors

2.3 Processor properties

In this section, we consider some ARM processors and identify which processor implements
which architecture version. In Cortex-A series processors on page 2-10 we take a slightly more
detailed look at some of the individual processors that implement architecture version v7-A.
Some terminology will be used in this chapter that might be unfamiliar to the first-time user of
ARM processors and will not be explained until later in the book.

Table 2-1 lists the architecture version implemented by a number of older ARM processors.

Table 2-1 Older ARM processors and architectures

Architecture version Applications processor Embedded processor

v4T ARM720T™ ARM7TDMI™

ARM920T™
ARM922T™

v5TE - ARM946E-S™
ARM966E-S™
ARM968E-S

v5TEJ ARM926EJ-S™ -

v6K ARM1136J(F)-S™ -
ARM11™ MPCore™

v6T2 - ARM1156T2-S™

v6K + security extensions ARM1176JZ(F)-S™ -

Table 2-2 lists the architecture version implemented by the Cortex family of processors.

Table 2-2 Cortex processors and architecture versions

v7-A (Applications) v7-R (Real Time) v6-M/v7-M (Microcontroller)

Cortex-A5 (Single/MP) Cortex-R4 Cortex-M0+ (ARMv6-M)

Cortex-A7 (MP) Cortex-R5 Cortex-M0 (ARMv6-M)

Cortex-A8 (Single) Cortex-R7 Cortex-M1™ (ARMv6-M)

Cortex-A9 (Single/MP) Cortex-M3™ (ARMv7-M)

Cortex-A12 (MP) Cortex-M4(F) (ARMv7E-M)

Cortex-A15 (MP)

Table 2-3 on page 2-9 compares the properties of Cortex-A series processors. For processor
cache information, see Table 8-1 on page 8-11.

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 ARM Architecture and Processors

Table 2-3 Some properties of Cortex-A series processors

Processor

Cortex-A5 Cortex-A7 Cortex-A8 Cortex-A9 Cortex-A12 Cortex-A15

Release date Dec 2009 Oct 2011 July 2006 March 2008 June 2013 April 2011

Typical clock ~1GHz ~1GHz on ~1GHz on ~2GHz on ~2GHz on ~2.5GHz on

speed 28nm 65nm 40nm 28nm 28nm

Execution order In-order In-order In-order Out of order Out of order Out of order

Cores 1 to 4 1 to 4 1 1 to 4 1 to 4 1 to 4

Peak integer 1.6DMIPS/ 1.9DMIPS/ 2DMIPS/MHz 2.5DMIPS/M 3.0DMIPS/ 3.5DMIPS/

throughput MHz MHz Hz MHz MHz

VFP VFPv4 VFPv4 VFPv3 VFPv3 VFPv4 VFPv4

architecture

NEON NEON NEONv2 NEON NEON NEONv2 NEONv2

architecture

Half precision Yes Yes No Yes Yes Yes

extension

Hardware No Yes No No Yes Yes

Divide

Fused Multiply Yes Yes No No Yes Yes

Accumulate

Pipeline stages 8 8 13 9 to 12 11 15+

Instructions 1 Partial dual 2 2 2 3

decoded per issue (Superscalar) (Superscalar) (Superscalar) (Superscalar)
cycle

Return stack 4 8 8 8 8 48
entries

LPAE No Yes No No Yes Yes

Floating Point Optional Yes Yes Optional Yes Optional

Unit

AMBA 64-bit 128-bit 64 or 128-bit 2× 64-bit 128-bit 128-bit

interface AMBA 3 AMBA 4 AMBA 3 AMBA 3 AMBA 4 AMBA 4

Generic Included Optional Not included Included External Optional

Interrupt
Controller
(GIC)

Trace Optional Optional Integrated Integrated Integrated Integrated

ETM ETM ETM PTM PTM PTM
separate
macrocell

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 ARM Architecture and Processors

2.4 Cortex-A series processors

In this section, we take a closer look at each of the processors that implement the ARMv7-A
architecture. Only a general description is given in each case, for more specific information on
each processor, see Table 2-3 on page 2-9 and Table 8-1 on page 8-11.

2.4.1 The Cortex-A5 processor

The Cortex-A5 processor is the smallest ARM multi-core applications processor. Devices based
on this processor are typically low-cost, capable of delivering the internet to the widest possible
range of devices from low-cost entry-level smartphones and smart mobile devices, to
embedded, consumer and industrial devices.

ARM CoreSight Multicore Debug and Trace

Generic Interrupt Controller

NEON
Data Engine

Cortex-A5 processor

Floating-point
unit
4
3
Instruction
Data Cache 2
Cache
Core 1

SCU ACP

Dual 64-bit AMBA3 AXI

Figure 2-3 Cortex-A5 processor

The Cortex-A5 processor has the following features:

• Full application compatibility with other Cortex-A series processors.

• Multiprocessing capability for scalable, energy efficient performance.

• Optional Floating-point or NEON units for media and signal processing.

• High-performance memory system including caches and memory management unit.

• High value migration path from older ARM processors.

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 ARM Architecture and Processors

2.4.2 The Cortex-A7 processor

The ARM Cortex-A7 processor is the most energy efficient application processor developed by
ARM and extends ARM’s low-power leadership in entry level smart phones, tablets and other
advanced mobile devices.

ARM CoreSight Multicore Debug and Trace

Generic Interrupt Controller

NEON
Data Engine

Cortex-A7 processor

Floating-point
unit
4
3
Instruction
Data Cache 2
Cache
Core 1

SCU L2 Cache W/ECC

128-bit AMBA ACE Coherent Bus Interface

Figure 2-4 Cortex-A7 processor

The Cortex-A7 processor has the following features:

• Architecture and feature set identical to the Cortex-A15 processor, enabling big.LITTLE
configuration.

• Less than 0.5mm2, using 28nm process technology.

• Full application compatibility with all Cortex-A series processors.

• Tightly-coupled low latency level 2 cache (up to 4MB).

• Floating-point unit.

• NEON technology for multimedia and SIMD processing.

2.4.3 The Cortex-A8 processor

The ARM Cortex-A8 processor, has the ability to scale in speed from 600MHz to greater than
1GHz. The Cortex-A8 processor can meet the requirements for power-optimized mobile
devices needing operation in less than 300mW; and performance-optimized consumer
applications requiring 2000 Dhrystone MIPS. It is available in a number of different devices,
including the S5PC100 from Samsung, the OMAP3530 from Texas Instruments and the

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 ARM Architecture and Processors

i.MX515 from Freescale. From high-end feature phones to netbooks, DTVs, printers and
automotive-infotainment, the Cortex-A8 processor offers a proven high-performance solution
with millions of units shipped annually

ARM CoreSight Multicore Debug and Trace

NEON
Data Engine

Cortex-A8 processor
Dynamic branch
prediction

L1 Instruction Floating-point
L1 Data Cache unit
Cache

Integrated L2 Cache

64- or 128-bit AMBA3 Bus Interface

Figure 2-5 Cortex-A8 processor

The Cortex-A8 processor has the following features:

• Frequency from 600MHz to more than 1GHz.

• High performance superscalar architecture.

• NEON technology for multi-media and SIMD processing.

• Compatibility with older ARM processors.

2.4.4 The Cortex-A9 processor

The ARM Cortex-A9 processor is a power-efficient and popular high performance choice in low
power or thermally constrained cost-sensitive devices.

It is currently shipping in large volumes for smartphones, digital TV, consumer and enterprise
applications. The Cortex-A9 processor provides an increase in performance of greater than 50%
compared to the Cortex-A8 processor. The Cortex-A9 processor can be configured with up to
four cores delivering peak performance when required. Configurability and flexibility makes
the Cortex-A9 processor suitable for wide variety of markets and applications.

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 ARM Architecture and Processors

ARM CoreSight Multicore Debug and Trace

Generic Interrupt Controller

NEON
Data Engine

Cortex-A9 processor

Floating-point
unit
4
3
L1 Instruction
L1 Data Cache 2
Cache
Core 1

SCU ACP

Dual 64-bit AMBA3 AXI

Figure 2-6 Cortex-A9 processor

Devices containing the Cortex-A9 processor include nVidia’s dual-core Tegra-2, the
SPEAr1300 from ST and TI’s OMAP4 platform.

The Cortex-A9 processor has the following features:

• Out-of-order speculating pipeline.

• 16, 32 or 64KB four way associative L1 caches.

• Floating-point unit.

• NEON technology for multi-media and SIMD processing.

• Available as a speed or power optimized hard macro implementation.

2.4.5 The Cortex-A12 processor

The Cortex-A12 processor is a high performance mid-range mobile processing solution

designed for mobile applications, for example, use in smartphones and tablet devices. The
Cortex-A12 processor is a successor to the highly successful Cortex-A9 processor and is
optimized for highest performance in the mainstream mobile power envelope leading to
best-in-class efficiency.

The high performance and high-end feature set of the Cortex-A12 processor is suitable for many
use cases. Mid-range devices can build on the success of high-end devices and continue driving
the fastest growing market segment in mobile.

Architecturally, the Cortex-A12 processor is based on the latest ARMv7-A architecture and
features extensions that are aligned with processors such as the Cortex-A15 processor.

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 ARM Architecture and Processors

ARM CoreSight Multicore Debug and Trace

NEON
Data Engine

Cortex-A12 processor

Floating-point
unit
4
3
L1 Instruction
L1 Data Cache 2
Cache
Core 1

SCU ACP Integrated L2 cache w/ECC Peripheral Port

Dual 64-bit AMBA3 AXI

Figure 2-7 Cortex-A12 processor

The Cortex-A12 processor has the following features:

• 40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM.

• Full application compatibility with all Cortex-A series processors.

• NEON technology for multi-media and SIMD processing.

• Virtualization and TrustZone security technology

2.4.6 The Cortex-A15 processor

The ARM Cortex-A15 processor is designed to deliver unprecedented flexibility and processing
capability. This processor is designed with advanced power reduction techniques, and enables
products in a wide range of markets ranging from mobile computing, high-end digital home,
servers and wireless infrastructure.

The Cortex-A15 MPCore processor has full application compatibility with all other Cortex-A
series processors.

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 ARM Architecture and Processors

ARM CoreSight Multicore Debug and Trace

Generic Interrupt Controller

NEON
Data Engine

Cortex-A15 processor

Floating-point
unit
4
3
L1 Instruction
L1 Data Cache 2
Cache
Core 1

SCU ACP Integrated L2 cache w/ECC

128-bit AMBA ACE Coherent Bus Interface

Figure 2-8 Cortex-A15 processor

The Cortex-A15 processor has the following features:

• Highly scalable, up to 2.5GHz performance.

• Full application compatibility with all Cortex-A series processors.

• Out-of-order superscalar processor.

• Tightly coupled low-latency level 2 cache (up to 4MB).

• Floating-point unit.

• NEON technology for multi-media and SIMD processing.

• Available as a quad-core hard macro implementation.

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 ARM Architecture and Processors

2.5 Key architectural points of ARM Cortex-A series processors

A number of key points are common to the Cortex-A family of devices:

• 32-bit RISC core, with 16 × 32-bit visible registers with mode-based register banking.

• Modified Harvard Architecture (separate, concurrent access to instructions and data).

• Load/Store Architecture.

• Thumb-2 technology as standard.

• VFP and NEON options.

• Backward compatibility with code from previous ARM processors.

• 4GB of virtual address space and a minimum of 4GB of physical address space.

• Hardware translation table walking for virtual to physical address translation.

• Virtual page sizes of 4KB, 64KB, 1MB and 16MB. Cacheability attributes and access
permissions can be set on a per-page basis.

• Big-endian and little-endian data access support.

• Unaligned access support for basic load/store instructions.

• Symmetric Multi-processing (SMP) support on MPCore™ variants, that is, multi-core

versions of the Cortex-A series processors, with full data coherency at the L1 cache level.
Automatic cache and Translation Lookaside Buffer (TLB) maintenance propagation
provides high efficiency SMP operation.

• Physically indexed, physically tagged (PIPT) data caches. See Virtual and physical tags
and indexes on page 8-11.

All of these architectural points are described in the chapters which follow.

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 ARMv8-A Architecture and Processors

2.2 ARMv8-A Processor properties

Table 2-1 compares the properties of the processor implementations from ARM that support the
ARMv8-A architecture.

Table 2-1 Comparison of ARMv8-A processors

Processor

Cortex-A53 Cortex-A57

Release date July 2014 January 2015

Typical clock speed 2GHz on 28nm 1.5 to 2.5 GHz on 20nm

Execution order In-order Out of order, speculative

issue, superscalar

Cores 1 to 4 1 to 4

Integer Peak throughput 2.3MIPS/MHz 4.1 to 4.76MIPS/MHza

Floating-point Unit Yes Yes

Half-precision Yes Yes

Hardware Divide Yes Yes

Fused Multiply Accumulate Yes Yes

Pipeline stages 8 15+

Return stack entries 4 8

Generic Interrupt Controller External External

AMBA interface 64-bit I/F AMBA 4 128-bit I/F AMBA 4

(Supports AMBA 4 (Supports AMBA 4 and
and AMBA 5) AMBA 5)

L1 Cache size (Instruction) 8KB to 64 KB 48KB

L1 Cache structure (Instruction) 2-way set associative 3-way set associative

L1 Cache size (Data) 8KB to 64KB 32KB

L1 Cache structure (Data) 4-way set associative 2-way set associative

L2 Cache Optional Integrated

L2 Cache size 128KB to 2MB 512KB to 2MB

L2 Cache structure 16-way set associative 16-way set associative

Main TLB entries 512 1024

uTLB entries 10 48 I-side

32 D-side

A. IMPLEMENTATION DEFINED

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 ARMv8-A Architecture and Processors

2.2.1 ARMv8 processors

This section describes each of the processors that implement the ARMv8-A architecture. It only
gives a general description in each case. For more specific information on each processor, see
Table 2-1 on page 2-5.

The Cortex-A53 processor

The Cortex-A53 processor is a mid-range, low-power processor with between one and four
cores in a single cluster, each with an L1 cache subsystem, an optional integrated GICv3/4
interface, and an optional L2 cache controller.

The Cortex-A53 processor is an extremely power efficient processor capable of supporting

32-bit and 64-bit code. It delivers significantly higher performance than the highly successful
Cortex-A7 processor. It is capable of deployment as a standalone applications processor, or
paired with the Cortex-A57 processor in a big.LITTLE configuration for optimum performance,
scalability, and energy efficiency.

ARM CoreSight Multicore Debug and Trace

Generic Interrupt Controller

NEON
Data Engine
with crypto ext
Cortex-A53 processor

Floating-point
unit

Level 1 Memory
Level 1 Data
Instruction Management 3
Cache w/ECC
Cache Unit
2
Performance Monitor Data Processing Core 1
Unit Unit
0

SCU ACP Integrated Level 2 Cache w/ECC

AMBA 4 ACE or AMBA 5 CHI Coherent Bus Interface

Figure 2-2 Cortex-A53 processor

The Cortex-A53 processor has the following features:

• In-order, eight stage pipeline.

• Lower power consumption from the use of hierarchical clock gating, power domains, and
advanced retention modes.

• Increased dual-issue capability from duplication of execution resources and dual

instruction decoders.

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 ARMv8-A Architecture and Processors

• Power-optimized L2 cache design delivers lower latency and balances performance with
efficiency.

The Cortex-A57 processor

The Cortex-A57 processor is targeted at mobile and enterprise computing applications

including compute intensive 64-bit applications such as high end computer, tablet, and server
products. It can be used with the Cortex-A53 processor into an ARM big.LITTLE configuration,
for scalable performance and more efficient energy use.

The Cortex-A57 processor features cache coherent interoperability with other processors,
including the ARM Mali™ family of Graphics Processing Units (GPUs) for GPU compute and
provides optional reliability and scalability features for high-performance enterprise
applications. It provides significantly more performance than the ARMv7 Cortex-A15
processor, at a higher level of power efficiency. The inclusion of cryptography extensions
improves performance on cryptography algorithms by 10 times over the previous generation of
processors.

ARM CoreSight Multicore Debug and Trace

Generic Interrupt Controller

NEON
Data Engine
with crypto ext
Cortex-A57 processor

Floating-point
unit

Level 1
Level 1 Data Memory
Instruction 3
Cache w/ECC Protection Unit
Cache
2
Performance Monitor Unit Core 1
0

SCU ACP Integrated Level 2 Cache w/ECC

AMBA 4 ACE or AMBA5 CHI Coherent Bus Interface

Figure 2-3 Cortex-A57 processor core

The Cortex-A57 processor fully implements the ARMv8-A architecture. It enables multi-core
operation with between one and four cores multi-processing within a single cluster. Multiple
coherent SMP clusters are possible, through AMBA5 CHI or AMBA 4 ACE technology. Debug
and trace are available through CoreSight technology.

The Cortex-A57 processor has the following features:

• Out-of-order, 15+ stage pipeline.

ARM DEN0024A Copyright © 2015 ARM. All rights reserved. 2-7

ID050815 Non-Confidential
Hercules™ ARM® Cortex®-R4
System Architecture
Processor Overview
What is Hercules™?
TI’s 32-bit ARM® Cortex™-R4/R5 MCU family for Industrial, Automotive, and Transportation Safety

Hardware Safety Features Hercules™ Scalable Memory

• ARM Cortex-R4F and R5F CPUs & Peripherals
• Lockstep CPU Architecture • Up to 330MHz • 128KB to 4MB of Embedded
• CPU & RAM Built in Self Test • IEC 61508 & ISO 26262 Safety Flash Memory
• RAM & Flash ECC • Automotive AEC Q100 Qualification • 10-Bit & 12-Bit ADCs
• Clock & Voltage Monitoring • Development kits starting under $20 • Ethernet, USB, FR, CAN, LIN,
• SPI, I2C, UART, NHET

• Broad Safety MCU Portfolio • Reduce Systematic and Random Faults

– CPU performance from 80MHz to 330MHz – Development flow certified to IEC61508 & ISO26262
– Flash memory options ranging from 128KB to 4MB – Integrated diagnostics protect against random faults

• High Reliability • Time To Market

– Proven hardware based on 20+ years of TI safety-critical – Hardware safety features reduce software development
system expertise – Tools, software and safety documentation
– Development flow refined for high quality & low DPPM

2
 Hercules™ MCUs RM57L
330 MHz
4MB Flash
Scalable platform for functional safety applications RM48L9
220 MHz
512kB RAM

3MB Flash
256kB RAM
RM48L7 337p BGA
200 MHz
2MB Flash
256kB RAM 144p QFP
RM46L8 337p BGA 570LC43
220 MHz 300 MHz
1.2MB Flash 144p QFP 4MB Flash
512kB RAM
RM44L9 192kB RAM
337p BGA
570LS31
180 MHz
1MB Flash 180 MHz
128kB RAM
144p QFP
3MB Flash
256kB RAM
337p BGA
RM44L5 337p BGA 570LS12
180 MHz 180 MHz
1.2MB Flash
768K Flash
128kB RAM
100p QFP 192kB RAM 144p QFP
144p QFP 570LS09 337p BGA
160 MHz
RM42L4 1MB Flash
100 MHz 144p QFP
100p QFP 128kB RAM
384kB Flash
570LS07 337p BGA
32kB RAM 144p QFP 160 MHz
768kB Flash
128kB RAM
100p QFP
570LS04 144p QFP
RM41L2 100p QFP 80 MHz
80MHz
128kB Flash
384kB Flash 100p QFP
32kB RAM
32kB RAM 144p QFP External certification: ISO 26262, IEC 61508
570LS03
80 MHz 100p QFP
100p QFP 256kB Flash
32kB RAM
Documentation: Safety Manual, FMEDA reports

Software: Drivers, libraries, RTOS, Autosar, tools, debug

570LS02 100p QFP
80 MHz
128kB Flash Development Kits: LaunchPad, HDK, SafeTI CSP, SafeTI CQK
32kB RAM

Production
100p QFP
 Cortex-R: Ideal for safety-critical applications
Lockstep implementation
Safety features
Compare
• Supports Lockstep Error
Output + Control
• Memory Protection Unit (MPU)
CCM
• Error-Correcting Code (ECC) Cycle Delay
Self
Test

Higher performance
• 8-stage processor pipeline
• Dual issue – two instructions can
execute in parallel
• Load store unit reduces stalling
• Pre-fetch and Branch Prediction Units
• Cached*
Cycle Delay

Real-time / determinism
• Tightly Coupled Memory (TCM)
• Fast interrupt response Input + Control

• Deterministic interrupt response

Cortex-R4 features
• ARMv7-R architecture, supports ARM and Thumb2 instruction sets
• 8-stage processor pipeline
• Pre-fetch and Branch Prediction Units
• Floating-Point Unit
• Fast interrupt response
• Tightly Coupled Memory (TCM) with ECC
• Memory Protection Unit (MPU)
• Performance Monitoring Unit (PMU)
Cortex-R4 Hercules Processor Cortex-R4 processor structure
Prefetch unit
• Fetches instructions from the TCMs, or external
memory
• Predicts the outcome of branches in the instruction
stream
Data Processing Unit (DPU)
• Decodes and executes instructions
• Interfaces with LSU to transfer data to or from the
memory system
• Holds general-purpose registers, status registers and
control registers (CP15, CP14, etc.)
Load/store unit
• Manages all load & store operations, interfacing with
the DPU, TCMs, and memory
AXI master interface
• Provides a high-bandwidth interface to on-chip RAM,
peripherals, and interfaces to external memory
• Consists of a single AXI port with a 64-bit read/write
DMA
channel for instruction & data fetches
• Can run at the same frequency as the processor
 Pipeline
The following stages make up the pipeline:
• Fetch stages (Fe1, Fe2)
• Pre-Decode and Decode stages (Pd, De)
• Issue stage (Iss)
• Execution stages (Ex1, Ex2, etc.)

64-bit
Floating Point Unit (FPU)
• FPU is compliant to IEEE754

• 16 double-word (64 bits) registers

• 32 single-word (32 bits) registers

• Supports features:

– Single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate,
and square root operations

– Conversions between fixed-point and floating-point data formats, etc

– Comparisons

– Underflow

– Exceptions
 Processor modes
Mode Description • ARM has 7 basic operating modes.
Supervisor Entered on reset and when a • Modes other than user mode have
(SVC) Software Interrupt instruction privileged access rights.
(SWI) is executed
Undef Used to handle undefined • Usually the initial setup is done in SVC
instructions Privileged mode after reset, then switch to
Abort Used to handle memory modes system or user mode afterwards.
Exception modes

access violations • Privileged access rights are needed to

FIQ Entered when a high priority access certain configuration registers in
(fast) interrupt is raised the processor and peripherals. For
IRQ Entered when a low priority example, CP15, flash control registers.
(normal) interrupt is raised
System Privileged mode using the • Cortex-R MCU has MPU, which can be
same registers as User mode used to set the memory access rights
User Mode under which most Unprivileged for certain regions.
Applications / OS tasks run mode
 Processor registers
User/System FIQ mode IRQ mode Supervisor Abort Undefined
mode mode Exception Instruction
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7
R8 R8 FIQ R8 R8 R8 R8
R9 R9 FIQ R9 R9 R9 R9
R10 R10 FIQ R10 R10 R10 R10
R11 R11 FIQ R11 R11 R11 R11
R12 R12 FIQ R12 R12 R12 R12
Stack Pointer (SP) R13 SP R13 FIQ R13 IRQ R13 SVC R13 ABORT R13 UNDEF
Link Register (LR) R14 LR R14 FIQ R14 IRQ R14 SVC R14 ABORT R14 UNDEF
Program Counter (PC) R15 PC R15 PC R15 PC R15 PC R15 PC R15 PC

Current Program
Status Register (CPSR) CPSR CPSR CPSR CPSR CPSR CPSR
Saved Program SPSR FIQ SPSR IRQ SPSR SVC SPSR ABORT SPSR UNDEF
Status Register (SPSR)
Current Processor Status Register (CPSR)
31 30 29 28 27 26 25 24 23 20 19 16 15 10 9 8 7 6 5 4 0

N Z C V Q IT J DNM GE[3:0] IT[7:2] E A I F T MODE[4:0]

• Condition Code Flags • A = Imprecise Abort Disable

N = ALU Negative result • Interrupt Disable bits
Z = ALU Zero result I = 1, disables the IRQ
C = ALU Carry out F = 1, disables the FIQ
V = ALU arithmetic overflow
Q = ALU sticky overflow • State bit
T = 0, 32-bit instruction set
• J = Java state bit (always reads 0) T = 1, 16-bit instruction set
• IT[7:0] = If-Then • Mode (defines processor mode)
• DNM (Do Not Modify) M[4:0] = 10000 User mode
• GE[3:0] = Greater Than or Equal To M[4:0] = 10001 FIQ mode
M[4:0] = 10010 IRQ mode
• E = Endianism of Data M[4:0] = 10011 Supervisor mode
M[4:0] = 10111 Abort mode
M[4:0] = 11011 Undefined mode
M[4:0] = 11111 System mode
Supported data types
• The processor supports the following data types:
– Double Word (64 bit)
– Word (32 bit)
– Half Word (16 bit)
– Byte (8 bit)
• Although the processor supports unaligned accesses, TI does not recommend
using unaligned accesses for bus performance.
– Above data types should be aligned at their respective size boundary.
– Most unaligned accesses are converted into multiple aligned accesses.
• The TMS570 devices are storing their data in big endian format (BE32), and
RM4/5x stores data in little endian format.
Exception handling and the vector table

• Reset Highest Priority

• DABT
• FIQ
• IRQ
• UNDEF
• PABT
• SVC Lowest Priority

• The FIQ is implemented as a non-maskable interrupt in the Hercules MCU.

• nFIQ and nIRQ inputs are connected to VIM.
Exception handling
When an exception occurs, the CPU does the following:
• Copies CPSR into SPSR_<mode>
• Sets appropriate CPSR bits
• Change to ARM state
• Change to exception mode
• When an IRQ interrupt is received, the CPU disables other IRQ interrupts
• When an FIQ interrupt is received, the CPU disables both IRQ and FIQ interrupts
• Stores the return address in LR_<mode>
• Sets PC to vector address or ISR address
• Swaps banked registers

To return, the exception handler needs to:

• Restore CPSR from SPSR_<mode>
• Restore PC from LR_<mode>
Interrupt handling
The Hercules MCU supports three different modes to handle peripheral interrupts in hardware
and software:

• Index interrupts mode (legacy mode): The interrupt dispatching has to be done completely in
software (software dispatcher).

• Register-vectored interrupt mode: This mode allows the interrupt dispatching to be done in
hardware, the software has only to load the interrupt vector of the ISR from the VIM module
and branch to the vector.

• Hardware-vectored interrupt mode (IRQ only): This mode has the advantage that the vector
of the ISR has not been loaded by software. Instead, the vector is directly supplied to the MCU
core via the VIC port, and saves some CPU cycles for lower interrupt latency compared to the
second mode.
Index interrupts mode
1. Events occur within peripherals
2. Peripherals make FIQ/IRQ requests
to the VIM
3. VIM prioritizes the requests &
provides the highest ISR to CPU
4. CPU fetch from 0x18/0x1C.
5. Branch to ISR dispatcher.
6. Load Interrupt offset .(IRQINDEX,
FIQINDEX)
7. Decide which ISR to execute.
8. Branch to ISR

VIM:
Prioritizing and
signaling IRQ/FIQ
to ARM Cortex-R4
 Register-vectored interrupts
1. Events occur within peripherals
2. Peripherals make FIQ/IRQ requests
to the VIM
3. VIM prioritizes the requests &
provides the addr of the highest ISR
to CPU
4. CPU fetches from 0x18/0x1C
5. Branch to ISR (LDR PC, [PC, #-
0x1B0]), (IRQVECREG/FIQVECREG.)
6. Branch to ISR

VIM:
Prioritizing and signaling
IRQ/FIQ to ARM Cortex-R4
 Hardware-vectored interrupts (only IRQ)
1. Events occur within
peripherals
2. Peripherals make FIQ/IRQ
requests to the VIM
3. VIM prioritizes the requests
4. VIM provides address of
highest pending request
directly to the processors VIC
port.
5. CPU branches directly to ISR.

VIM:
Prioritizing and signaling
IRQ/FIQ to
ARM Cortex-R4/5
Abort: Prefetch and Data
Prefetch Abort (PABT)
• CPU tries to execute an instruction from a protected or faulty memory location, such as:
– The memory location is not implemented in the system.
– The memory region is protected by the MPU.
– An error is detected in the data by the ECC checking logic.
• All prefetch aborts are precise.

Data Abort (DABT)

• The CPU takes the data abort if data is read from or written to a protected or faulty memory location.
This could be because of the following conditions:
– The memory location is not implemented.
– The memory location is read- or write-only in privileged mode (when processor is in User mode).
– The memory location is read- or write-protected by the MPU.
– If an error is detected in the data by the ECC checking logic.
• Data aborts can be precise or imprecise.
Abort type: Precise (synchronous), Imprecise (asynchronous)
Precise or Synchronous Aborts
• The abort is taken at the instruction that caused the exception.
• The abort handler could use the SPSR_abt and R14_abt (LR_abt) registers to determine the
instruction that generated the abort and the CPU state when the abort occurred.
• Prefetch abort is always a precise abort.

Imprecise or Asynchronous Aborts

• If the exception is taken on an instruction later than the instruction that caused the exception.
• It is not possible to determine the exact instruction that caused the abort.
• This could be the case on writes to normal-type memory, where the write is stored in a buffer until
the memory system is ready to perform it. In such cases, the exception will be generated and the
abort will be taken after the appropriate store instruction was executed by the processor.
How to determine the cause of an abort
• The Cortex-R4/5 processor has a system control coprocessor implemented: The
CP15. The CP15 offers the possibility to readout additional information about an
abort.
• Four registers in the CP15 hold information about the cause of an abort:
– Data Fault Status Register
– Auxiliary Fault Status Registers
– Data Fault Address Register
– Instruction Fault Address Register
For more information
• SafeTI Web Page: www.ti.com/safeti
• Hercules Web Page: www.ti.com/hercules
– Data sheets
– Technical Reference Manual
– Application notes
– Software & tools downloads and updates
– Order evaluation and development kits
• Hercules Safety Microcontrollers Training Series
training.ti.com/hercules
– Cortex-R Processor Architecture
– Peripherals
– Software
– Functional Safety
• For questions about this training, refer to the
Engineer-2-Engineer Support Forum www.ti.com/hercules-support
– News and announcements
– Ask technical questions
– Search for technical content
TI Information – Selective
Disclosure
15/04/2020 List of ARM microarchitectures - Wikipedia

List of ARM microarchitectures

This is a list of microarchitectures based on the ARM family of instruction sets designed by ARM Holdings and 3rd parties, sorted by
version of the ARM instruction set, release and name. ARM provides a summary of the numerous vendors who implement ARM cores
in their design.[1] Keil also provides a somewhat newer summary of vendors of ARM based processors.[2] ARM further provides a
chart[3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent
ARM core families.

Contents
ARM cores
Designed by ARM
Designed by third parties
ARM core timeline
See also
References
Further reading

ARM cores

Designed by ARM

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ARM ARM Cache (I / D),

ARM core Feature Typical MIPS @ MHz Reference
family architecture MMU
ARM1 ARMv1 ARM1 First implementation None
4 MIPS @ 8 MHz
ARMv2 ARM2 ARMv2 added the MUL (multiply) instruction None
0.33 DMIPS/MHz
ARM2 Integrated MEMC (MMU), graphics and I/O
ARMv2a ARM250 processor. ARMv2a added the SWP and None, MEMC1a 7 MIPS @ 12 MHz
SWPB (swap) instructions
12 MIPS @ 25 MHz
ARM3 ARMv2a ARM3 First integrated memory cache 4 KB unified
0.50 DMIPS/MHz
ARMv3 first to support 32-bit memory
address space (previously 26-bit).
ARM60 None 10 MIPS @ 12 MHz
ARMv3M first added long multiply
instructions (32x32=64).
ARM6 ARMv3
As ARM60, cache and coprocessor bus (for
ARM600 4 KB unified 28 MIPS @ 33 MHz
FPA10 floating-point unit)
17 MIPS @ 20 MHz [4]
ARM610 As ARM60, cache, no coprocessor bus 4 KB unified
0.65 DMIPS/MHz
ARM700 8 KB unified 40 MHz
ARM710 As ARM700, no coprocessor bus 8 KB unified 40 MHz [5]
ARM7 ARMv3
40 MHz
ARM710a As ARM710 8 KB unified
0.68 DMIPS/MHz
3-stage pipeline, Thumb, ARMv4 first to drop 15 MIPS @ 16.8 MHz
ARM7TDMI(-S) None
legacy ARM 26-bit addressing 63 DMIPS @ 70 MHz
8 KB unified,
ARM710T As ARM7TDMI, cache 36 MIPS @ 40 MHz
MMU
ARM7T ARMv4T 8 KB unified,
MMU with FCSE
ARM720T As ARM7TDMI, cache 60 MIPS @ 59.8 MHz
(Fast Context
Switch Extension)
ARM740T As ARM7TDMI, cache MPU
5-stage pipeline, Thumb, Jazelle DBX,
ARM7EJ ARMv5TEJ ARM7EJ-S None
enhanced DSP instructions
5-stage pipeline, static branch prediction, 8 KB unified, 84 MIPS @ 72 MHz [6][7]
ARM8 ARMv4 ARM810
double-bandwidth memory MMU 1.16 DMIPS/MHz
ARM9TDMI 5-stage pipeline, Thumb None
16 KB / 16 KB,
MMU with FCSE 200 MIPS @ [8]
ARM920T As ARM9TDMI, cache
(Fast Context 180 MHz
ARM9T ARMv4T Switch Extension)
8 KB / 8 KB,
ARM922T As ARM9TDMI, caches
MMU
ARM940T As ARM9TDMI, caches 4 KB / 4 KB, MPU
Variable, tightly
ARM946E-S Thumb, enhanced DSP instructions, caches coupled
memories, MPU
ARMv5TE
ARM966E-S Thumb, enhanced DSP instructions No cache, TCMs
ARM9E ARM968E-S As ARM966E-S No cache, TCMs
Thumb, Jazelle DBX, enhanced DSP Variable, TCMs, 220 MIPS @
ARMv5TEJ ARM926EJ-S
instructions MMU 200 MHz
No caches,
ARMv5TE ARM996HS Clockless processor, as ARM966E-S
TCMs, MPU
6-stage pipeline, Thumb, enhanced DSP 32 KB / 32 KB,
ARM1020E
instructions, (VFP) MMU
ARMv5TE
16 KB / 16 KB,
ARM10E ARM1022E As ARM1020E
MMU
Thumb, Jazelle DBX, enhanced DSP Variable, MMU or
ARMv5TEJ ARM1026EJ-S
instructions, (VFP) MPU
ARM11 740 @ 532–665 MHz
8-stage pipeline, SIMD, Thumb, Jazelle DBX, [9]
ARMv6 ARM1136J(F)-S (i.MX31 SoC), 400–
(VFP), enhanced DSP instructions, unaligned Variable, MMU
528 MHz
memory access

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ARMv6T2 ARM1156T2(F)- 9-stage pipeline, SIMD, Thumb-2, (VFP), Variable, MPU [10]
S enhanced DSP instructions
965 DMIPS @
ARM1176JZ(F)- Variable, MMU + 772 MHz, up to [11]
ARMv6Z As ARM1136EJ(F)-S
S TrustZone 2,600 DMIPS with
four processors
ARMv6K ARM11MPCore As ARM1136EJ(F)-S, 1–4 core SMP Variable, MMU
ARMv6-M SC000 0.9 DMIPS/MHz
SecurCore ARMv4T SC100
ARMv7-M SC300 1.25 DMIPS/MHz
Microcontroller profile, most Thumb + some
Thumb-2,[13] hardware multiply instruction Optional cache,
Cortex-M0[12] 0.84 DMIPS/MHz
(optional small), optional system timer, no TCM, no MPU
optional bit-banding memory
Microcontroller profile, most Thumb + some Optional cache,
Thumb-2,[13] hardware multiply instruction no TCM, optional
Cortex-M0+[14] 0.93 DMIPS/MHz
ARMv6-M (optional small), optional system timer, MPU with 8
optional bit-banding memory regions
Microcontroller profile, most Thumb + some 136 DMIPS @
Optional cache,
Thumb-2,[13] hardware multiply instruction 0–1024 KB I- 170 MHz,[16]
Cortex-M1[15] (optional small), OS option adds SVC / TCM, 0–1024 KB (0.8 DMIPS/MHz
banked stack pointer, optional system timer, D-TCM, no MPU FPGA-dependent)[17]
no bit-banding memory
Optional cache,
Microcontroller profile, Thumb / Thumb-2,
no TCM, optional
ARMv7-M Cortex-M3[18] hardware multiply and divide instructions, 1.25 DMIPS/MHz
MPU with 8
optional bit-banding memory
regions
Microcontroller profile, Thumb / Thumb-2 / Optional cache,
DSP / optional VFPv4-SP single-precision no TCM, optional 1.25 DMIPS/MHz
Cortex-M4[19]
FPU, hardware multiply and divide MPU with 8 (1.27 w/FPU)
instructions, optional bit-banding memory regions
Cortex-M
0−64 KB I-cache,
ARMv7E-M 0−64 KB D-
Microcontroller profile, Thumb / Thumb-2 / cache, 0–16 MB
DSP / optional VFPv5 single and double I-TCM, 0–16 MB
Cortex-M7[20] 2.14 DMIPS/MHz
precision FPU, hardware multiply and divide D-TCM (all these
instructions w/optional ECC),
optional MPU with
8 or 16 regions
Optional cache,
Microcontroller profile, Thumb-1 (most), no TCM, optional
Cortex-M23[21] 0.99 DMIPS/MHz
Thumb-2 (some), Divide, TrustZone MPU with 16
regions
Optional cache,
Microcontroller profile, Thumb-1, Thumb-2,
no TCM, optional
Cortex-M33[22] Saturated, DSP, Divide, FPU (SP), 1.50 DMIPS/MHz
MPU with 16
ARMv8-M TrustZone, Co-processor
regions
Built-in cache
(with option 2–
Microcontroller profile, Thumb-1, Thumb-2,
Cortex- 16 KB), I-cache,
Saturated, DSP, Divide, FPU (SP), 1.50 DMIPS/MHz
M35P[23] TrustZone, Co-processor
no TCM, optional
MPU with 16
regions
Cortex-R ARMv7-R Real-time profile, Thumb / Thumb-2 / DSP /
0–64 KB / 0–
optional VFPv3 FPU, hardware multiply and
64 KB, 0–2 of 0–
optional divide instructions, optional parity &
Cortex-R4[24] 8 MB TCM, opt. 1.67 DMIPS/MHz[25]
ECC for internal buses / cache / TCM, 8-
MPU with 8/12
stage pipeline dual-core running lockstep
regions
with fault logic
Real-time profile, Thumb / Thumb-2 / DSP /
optional VFPv3 FPU and precision, hardware
multiply and optional divide instructions, 0–64 KB / 0–
optional parity & ECC for internal buses / 64 KB, 0–2 of 0–
Cortex-R5[26] cache / TCM, 8-stage pipeline dual-core 8 MB TCM, opt. 1.67 DMIPS/MHz[25]
running lock-step with fault logic / optional as MPU with 12/16
2 independent cores, low-latency peripheral regions
port (LLPP), accelerator coherency port
(ACP)[27]

Cortex-R7[28] Real-time profile, Thumb / Thumb-2 / DSP / 0–64 KB / 0– 2.50 DMIPS/MHz[25]

optional VFPv3 FPU and precision, hardware 64 KB, ? of 0–

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multiply and optional divide instructions, 128 KB TCM, opt.
optional parity & ECC for internal buses / MPU with 16
cache / TCM, 11-stage pipeline dual-core regions
running lock-step with fault logic / out-of-
order execution / dynamic register renaming /
optional as 2 independent cores, low-latency
peripheral port (LLPP), ACP[27]

Cortex-R8[29] TBD TBD 2.50 DMIPS/MHz[25]

ARMv8-R Cortex-R52[30] TBD TBD 2.16 DMIPS/MHz[31]
Application profile, ARM / Thumb / Thumb-2 /
DSP / SIMD / Optional VFPv4-D16 FPU /
4−64 KB /
Optional NEON / Jazelle RCT and DBX, 1–4 1.57 DMIPS/MHz per
Cortex-A5[32] 4−64 KB L1,
cores / optional MPCore, snoop control unit core
MMU + TrustZone
(SCU), generic interrupt controller (GIC),
accelerator coherence port (ACP)
Application profile, ARM / Thumb / Thumb-2 /
DSP / VFPv4 FPU / NEON / Jazelle RCT and
DBX / Hardware virtualization, in-order
8−64 KB /
execution, superscalar, 1–4 SMP cores,
8−64 KB L1, 0– 1.9 DMIPS/MHz per
Cortex-A7[33] MPCore, Large Physical Address Extensions
1 MB L2, MMU + core
(LPAE), snoop control unit (SCU), generic
TrustZone
interrupt controller (GIC), architecture and
feature set are identical to A15, 8–10 stage
pipeline, low-power design[34]
16–32 KB / 16– Up to 2000
Application profile, ARM / Thumb / Thumb-2 / 32 KB L1, 0– (2.0 DMIPS/MHz in
Cortex-A8[35] VFPv3 FPU / NEON / Jazelle RCT and DAC, 1 MB L2 opt. speed from 600 MHz
13-stage superscalar pipeline ECC, MMU + to greater than
TrustZone 1 GHz)
Application profile, ARM / Thumb / Thumb-2 /
2.5 DMIPS/MHz per
DSP / Optional VFPv3 FPU / Optional NEON 16–64 KB / 16–
core, 10,000 DMIPS
/ Jazelle RCT and DBX, out-of-order 64 KB L1, 0–
@ 2 GHz on
Cortex-A9[36] speculative issue superscalar, 1–4 SMP 8 MB L2 opt.
Performance
cores, MPCore, snoop control unit (SCU), parity, MMU +
ARMv7-A Optimized TSMC 40G
generic interrupt controller (GIC), accelerator TrustZone
(dual-core)
coherence port (ACP)
Application profile, ARM / Thumb-2 / DSP /
Cortex-A VFPv4 FPU / NEON / Hardware
(32-bit) virtualization, out-of-order speculative issue
3.0 DMIPS/MHz per
Cortex-A12[37] superscalar, 1–4 SMP cores, Large Physical 32−64 KB
core
Address Extensions (LPAE), snoop control
unit (SCU), generic interrupt controller (GIC),
accelerator coherence port (ACP)
Application profile, ARM / Thumb / Thumb-2 /
DSP / VFPv4 FPU / NEON / integer divide / At least
32 KB w/parity /
fused MAC / Jazelle RCT / hardware 3.5 DMIPS/MHz per
32 KB w/ECC L1,
virtualization, out-of-order speculative issue core (up to
Cortex-A15[38] superscalar, 1–4 SMP cores, MPCore, Large
0–4 MB L2, L2
4.01 DMIPS/MHz
has ECC, MMU +
Physical Address Extensions (LPAE), snoop depending on
TrustZone
control unit (SCU), generic interrupt controller implementation)[39]
(GIC), ACP, 15-24 stage pipeline[34]
Application profile, ARM / Thumb / Thumb-2 /
DSP / VFPv4 FPU / NEON / integer divide /
fused MAC / Jazelle RCT / hardware
32 KB L1,
virtualization, out-of-order speculative issue
Cortex-A17[40] 256 KB–8 MB L2 2.8 DMIPS/MHz
superscalar, 1–4 SMP cores, MPCore, Large
w/optional ECC
Physical Address Extensions (LPAE), snoop
control unit (SCU), generic interrupt controller
(GIC), ACP
8–64 KB
w/optional parity /
Application profile, AArch32, 1–4 SMP cores, 8−64 KB
TrustZone, NEON advanced SIMD, VFPv4, w/optional ECC
ARMv8-A Cortex-A32[41]
hardware virtualization, dual issue, in-order L1 per core,
pipeline 128 KB–1 MB L2
w/optional ECC
shared
Cortex-A ARMv8-A 8−64 KB w/parity
(64-bit) / 8−64 KB w/ECC
Application profile, AArch64, 1–4 SMP cores,
ARM Cortex- L1 per core,
TrustZone, NEON advanced SIMD, VFPv4,
128 KB–1 MB
A34[42] hardware virtualization, 2-width decode, in-
L2 shared, 40-bit
order pipeline
physical
addresses

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Cortex-A35[43] Application profile, AArch32 and AArch64, 1– 8−64 KB w/parity 1.78 DMIPS/MHz
4 SMP cores, TrustZone, NEON advanced / 8−64 KB w/ECC
SIMD, VFPv4, hardware virtualization, 2- L1 per core,
width decode, in-order pipeline 128 KB–1 MB
L2 shared, 40-bit
physical
addresses
8−64 KB w/parity
/ 8−64 KB w/ECC
Application profile, AArch32 and AArch64, 1–
L1 per core,
4 SMP cores, TrustZone, NEON advanced
Cortex-A53[44] SIMD, VFPv4, hardware virtualization, 2-
128 KB–2 MB 2.3 DMIPS/MHz
L2 shared, 40-bit
width decode, in-order pipeline
physical
addresses
48 KB w/DED
parity / 32 KB
Application profile, AArch32 and AArch64, 1–
w/ECC L1 per
4 SMP cores, TrustZone, NEON advanced
core; 512 KB– 4.1–
Cortex-A57[45] SIMD, VFPv4, hardware virtualization, 3-
width decode superscalar, deeply out-of-
2 MB L2 shared 4.5 DMIPS/MHz[46][47]
w/ECC; 44-bit
order pipeline
physical
addresses
48 KB w/DED
parity / 32 KB
Application profile, AArch32 and AArch64, 1–
w/ECC L1 per
4 SMP cores, TrustZone, NEON advanced
core; 512 KB–
Cortex-A72[48] SIMD, VFPv4, hardware virtualization, 3- 4.7 DMIPS/MHz
2 MB L2 shared
width superscalar, deeply out-of-order
w/ECC; 44-bit
pipeline
physical
addresses
64 KB / 32−64 KB
Application profile, AArch32 and AArch64, 1– L1 per core,
4 SMP cores, TrustZone, NEON advanced 256 KB–8 MB
Cortex-A73[49] SIMD, VFPv4, hardware virtualization, 2- L2 shared w/ 4.8 DMIPS/MHz[50]
width superscalar, deeply out-of-order optional ECC, 44-
pipeline bit physical
addresses
ARMv8.2-A Application profile, AArch32 and AArch64, 1– 16−64 KB /
8 SMP cores, TrustZone, NEON advanced 16−64 KB L1,
Cortex-A55[51] SIMD, VFPv4, hardware virtualization, 2- 256 KB L2 per
core, 4 MB L3
width decode, in-order pipeline[52]
shared
Application profile, AArch64, 1–8 SMP cores,
64 / 64 KB L1,
Arm Cortex- TrustZone, NEON advanced SIMD, VFPv4,
256 KB L2 per
hardware virtualization, 2-wide decode
A65AE[53] core, 4 MB L3
superscalar, 3-width issue, out-of-order
shared
pipeline, SMT
Application profile, AArch32 and AArch64, 1–
64 / 64 KB L1,
8 SMP cores, TrustZone, NEON advanced
512 KB L2 per
Cortex-A75[54] SIMD, VFPv4, hardware virtualization, 3-
core, 4 MB L3
width decode superscalar, deeply out-of-
shared
order pipeline[55]
Application profile, AArch32 (non-privileged
64 / 64 KB L1,
level or EL0 only) and AArch64, 1–4 SMP
256−512 KB L2
cores, TrustZone, NEON advanced SIMD,
Cortex-A76[56] VFPv4, hardware virtualization, 4-width
per core,
512 KB−4 MB L3
decode superscalar, 8-way issue, 13 stage
shared
pipeline, deeply out-of-order pipeline[57]
Application profile, AArch32 (non-privileged
1.5K L0 MOPs
level or EL0 only) and AArch64, 1–4 SMP
cache, 64 / 64 KB
cores, TrustZone, NEON advanced SIMD,
L1, 256−512 KB
Cortex-A77[58] VFPv4, hardware virtualization, 4-width
L2 per core,
decode superscalar, 6-width instruction fetch,
512 KB−4 MB L3
12-way issue, 13 stage pipeline, deeply out-
shared
of-order pipeline[57]
Neoverse Application profile, AArch32 (non-privileged 64 / 64 KB L1,
level or EL0 only) and AArch64, 1–4 SMP 512−1024 KB L2
cores, TrustZone, NEON advanced SIMD, per core,
Neoverse N1[59] VFPv4, hardware virtualization, 4-width 2−128 MB L3
decode superscalar, 8-way dispatch/issue, 13 shared, 128 MB
stage pipeline, deeply out-of-order system level
pipeline[57] cache
Neoverse E1 Application profile, AArch64, 1–8 SMP cores, 32−64 KB /
TrustZone, NEON advanced SIMD, VFPv4, 32−64 KB L1,
hardware virtualization, 2-wide decode 256 KB L2 per

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superscalar, 3-width issue, 10 stage pipeline, core, 4 MB L3
out-of-order pipeline, SMT shared
ARM ARM Cache (I / D),
ARM core Feature Typical MIPS @ MHz Reference
family architecture MMU

As Dhrystone is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

Designed by third parties

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from
ARM.

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Instruction
Core Family Microarchitecture Feature Cache (I / D), MMU Typical MIPS @ MHz
set
100–233 MHz
StrongARM SA-110 5-stage pipeline 16 KB / 16 KB, MMU
ARMv4 1.0 DMIPS/MHz
(Digital)
SA-1100 derivative of the SA-110 16 KB / 8 KB, MMU
Up to 32 KB / 32 KB cache, 1.26 DMIPS/MHz
FA510
MPU 100–200 MHz
6-stage pipeline
Up to 32 KB / 32 KB cache, 1.26 MIPS/MHz
ARMv4 FA526
MMU 166–300 MHz
1.35 DMIPS/MHz
FA626 8-stage pipeline 32 KB / 32 KB cache, MMU
500 MHz
Faraday[60]
1.22 DMIPS/MHz
(Faraday FA606TE 5-stage pipeline No cache, no MMU
200 MHz
Technology)
1.43 MIPS/MHz
FA626TE 8-stage pipeline
800 MHz
ARMv5TE
1.43 MIPS/MHz
FMP626TE 8-stage pipeline, SMP 32 KB / 32 KB cache, MMU
500 MHz
2.4 DMIPS/MHz
FA726TE 13 stage pipeline, dual issue
1000 MHz
7-stage pipeline, Thumb, enhanced
XScale 32 KB / 32 KB, MMU 133–400 MHz
DSP instructions
XScale
Wireless MMX, wireless SpeedStep
(Intel / ARMv5TE Bulverde 32 KB / 32 KB, MMU 312–624 MHz
added
Marvell)
32 KB / 32 KB L1, optional
Monahans[61] Wireless MMX2 added Up to 1.25 GHz
L2 cache up to 512 KB, MMU
Feroceon 5–8 stage pipeline, single-issue 16 KB / 16 KB, MMU
600–2000 MHz
Jolteon 5–8 stage pipeline, dual-issue 32 KB / 32 KB, MMU
ARMv5
Sheeva 5–8 stage pipeline, single-issue, 1.46 DMIPS/MHz
(Marvell) PJ1 (Mohawk) 32 KB / 32 KB, MMU
Wireless MMX2 1.06 GHz
ARMv6 / 6–9 stage pipeline, dual-issue, 2.41 DMIPS/MHz
PJ4 32 KB / 32 KB, MMU
ARMv7-A Wireless MMX2, SMP 1.6 GHz
1 or 2 cores. ARM / Thumb / Thumb-
Scorpion[62] 2 / DSP / SIMD / VFPv3 FPU / NEON 256 KB L2 per core 2.1 DMIPS/MHz per core
(128-bit wide)
ARMv7-A
1, 2, or 4 cores. ARM / Thumb /
4 KB / 4 KB L0, 16 KB /
Snapdragon Krait[62] Thumb-2 / DSP / SIMD / VFPv4 FPU
16 KB L1, 512 KB L2 per core
3.3 DMIPS/MHz per core
(Qualcomm) / NEON (128-bit wide)
Up to 2.2 GHz
ARMv8-A Kryo[63] 4 cores. ?
(6.3 DMIPS/MHz)

2 cores. ARM / Thumb / Thumb-2 /

ARMv7-A Swift[64] L1: 32 KB / 32 KB, L2: 1 MB 3.5 DMIPS/MHz per core
DSP / SIMD / VFPv4 FPU / NEON
2 cores. ARM / Thumb / Thumb-2 /
L1: 64 KB / 64 KB, L2: 1 MB,
ARMv8-A Cyclone[65] DSP / SIMD / VFPv4 FPU / NEON /
L3: 4 MB
1.3 or 1.4 GHz
TrustZone / AArch64
2 or 3 cores. ARM / Thumb / Thumb-
L1: 64 KB / 64 KB, L2: 1 MB
ARMv8-A Typhoon[65][66] 2 / DSP / SIMD / VFPv4 FPU / NEON
or 2 MB, L3: 4 MB
1.4 or 1.5 GHz
/ TrustZone / AArch64
2 cores. ARM / Thumb / Thumb-2 /
L1: 64 KB / 64 KB, L2: 2 MB,
ARMv8-A Twister[67] DSP / SIMD / VFPv4 FPU / NEON /
L3: 4 MB or 0 MB
1.85 or 2.26 GHz
Ax TrustZone / AArch64
(Apple)
2 or 3 cores. AArch64, 6-decode, 6-
L1: 64 KB / 64 KB, L2: 3 MB
ARMv8.1-A Hurricane[68] issue, 9-wide, superscalar, out-of-
or 8 MB, L3: 4 MB or 0 MB
2.34 or 2.38 GHz
order
2 cores. AArch64, 7-decode, ?-issue, L1I: 128 KB, L1D: 64 KB, L2:
ARMv8.2-A Monsoon[69] 2.39 GHz
11-wide, superscalar, out-of-order 8 MB, L3: 4 MB
2 or 4 cores. AArch64, 7-decode, ?-
L1: 128 KB / 128 KB, L2:
ARMv8.3-A Vortex[70] issue, 11-wide, superscalar, out-of-
8 MB, L3: 8 MB
2.5 GHz
order
2 cores. AArch64, 7-decode, ?-issue, L1: 128 KB / 128 KB, L2:
ARMv8.4-A Lightning[71] 2.66 GHz
11-wide, superscalar, out-of-order 8 MB, L3: 16 MB

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X-Gene ARMv8-A X-Gene 64-bit, quad issue, SMP, 64 cores[72] Cache, MMU, virtualization 3 GHz (4.2 DMIPS/MHz
(Applied per core)
Micro)
2 cores. AArch64, 7-wide
superscalar, in-order, dynamic code
Denver 128 KB I-cache / 64 KB D-
(Nvidia)
ARMv8-A Denver[73][74] optimization, 128 MB optimization
cache
Up to 2.5 GHz
cache,
Denver1: 28nm, Denver2:16nm
2 cores. AArch64, 10-wide
superscalar, in-order, dynamic code
Carmel optimization, ? MB optimization
ARMv8(t.b.d.) Carmel[75][76] ? KB I-cache / ? KB D-cache Up to ? GHz
(Nvidia) cache,
functional safety, dual execution,
parity & ECC
ThunderX 64-bit, with two models with 8–16 or
ARMv8-A ThunderX ? Up to 2.2 GHz
(Cavium) 24–48 cores (×2 w/two chips)
K12
ARMv8-A K12[77] ? ? ?
(AMD)
5.1 DMIPS/MHz
64 KB I-cache / 32 KB D-
M1/M2 4 cores. AArch64, 4-wide, quad-
ARMv8-A cache, L2: 16-way shared
("Mongoose")[78] issue, superscalar, out-of-order
2 MB (2.6 GHz)

64 KB I-cache / 32 KB D-
Exynos 4 cores, AArch64, 6-decode, 6-issue, cache, L2: 8-way private
(Samsung) ARMv8-A M3 ("Meerkat")[79] ?
6-wide. superscalar, out-of-order 512 KB, L3: 16-way shared
4 MB
64 KB I-cache / 32 KB D-
2 cores, AArch64, 6-decode, 6-issue, cache, L2: 8-way private
ARMv8.2-A M4 ("Cheetah") ?
6-wide. superscalar, out-of-order 512 KB, L3: 16-way shared
4 MB

ARM core timeline

The following table lists each core by the year it was announced.[80][81] Cores before ARM7 aren't included in this table.

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Neoverse
Classic cores Cortex cores
cores
Year
Real- Application Application Application
ARM7 ARM8 ARM9 ARM10 ARM11 Microcontroller
time (32-bit) (64-bit) (64-bit)
1993 ARM700
ARM710
1994 ARM7DI
ARM7TDMI
1995 ARM710a
1996 ARM810
ARM710T
1997 ARM720T
ARM740T
ARM9TDMI
1998
ARM940T
ARM9E-S
1999 ARM966E-
S
ARM920T
ARM922T
2000 ARM1020T
ARM946E-
S
ARM7TDMI- ARM9EJ-S
ARM1020E
2001 S ARM926EJ-
ARM1022E
ARM7EJ-S S
ARM1026EJ-
2002 ARM1136J(F)-S
S
ARM1156T2(F)-
ARM968E- S
2003
S ARM1176JZ(F)-
S
2004 Cortex-M3
2005 ARM11MPCore Cortex-A8
2006 ARM996HS
2007 Cortex-M1 Cortex-A9
2008
2009 Cortex-M0 Cortex-A5
2010 Cortex-M4(F) Cortex-A15
Cortex-
R4
Cortex-
2011 Cortex-A7
R5
Cortex-
R7
Cortex-A53
2012 Cortex-M0+
Cortex-A57
2013 Cortex-A12
2014 Cortex-M7(F) Cortex-A17
Cortex-A35
2015
Cortex-A72
Cortex-
Cortex-M23 R8
2016 Cortex-A32 Cortex-A73
Cortex-M33(F) Cortex-
R52
Cortex-A55
2017
Cortex-A75
Cortex-
A65AE
2018 Cortex-M35P(F) Cortex-A76
Cortex-
A76AE
2019 Cortex-A77 Neoverse
E1
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Neoverse
N1

See also
Comparison of ARMv7-A cores
Comparison of ARMv8-A cores
List of applications of ARM cores
ARM architecture

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0140328171411/http://www.arm.com/about/company-profile/milestones.php) from the original on 28 March 2014. Retrieved 6 April
2014.
81. "ARM Press Releases" (http://www.arm.com/about/newsroom/index.php). Archived (https://web.archive.org/web/20140409172237/
http://arm.com/about/newsroom/index.php) from the original on 9 April 2014. Retrieved 6 April 2014.

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 D SUDHAKR
Asst. Professor
MGIT.
 Technical White Paper
SWPA001 – December 2000

OMAP™: Enabling Multimedia Applications

in Third Generation (3G) Wireless Terminals
Jamil Chaoui, Ken Cyr, Jean-Pierre Giacalone, OMAP Architecture Team
Sebastien de Gregorio, Yves Masse, Yeshwant Muthusamy,
Tiemen Spits, Madhukar Budagavi, Jennifer Webb

ABSTRACT

This paper describes how the Open Multimedia Applications Platform™ software and
hardware architecture enables multimedia applications in third-generation (3G) wireless
appliances. It provides an overview of OMAP™ strategy, concepts, main milestones, and
achievements. It also describes OMAP hardware architecture, explains how multimedia
applications can benefit from this advanced architecture, and why a RISC/DSP approach
is superior to RISC-only architecture. This paper outlines OMAP software concepts to
show how an architecture that combines two heterogeneous processors (RISC and DSP),
several operating system (OS) combinations, and applications running on both DSP and
RISC can be made accessible seamlessly to third parties. The final parts of the paper
outline how key multimedia applications such as speech and video can be integrated in an
OMAP solution.

Contents
1 Introduction .........................................................................................................................................2
2 OMAP Hardware Architecture ...........................................................................................................3
2.1 Advantages of a Combined RISC/DSP Architecture.....................................................................3
2.2 How the Architecture Works ..........................................................................................................4
2.3 C55x DSP and Multimedia Extensions .........................................................................................5
3 OMAP Software Architecture ............................................................................................................7
4 OMAP Multimedia Applications.........................................................................................................9
4.1 Video...............................................................................................................................................9
4.2 Speech Applications .....................................................................................................................10
5 Conclusion.........................................................................................................................................11

Figures
Figure 1. OMAP Hardware Architecture ................................................................................................ 4
Figure 2. How the OMAP Architecture Works ...................................................................................... 8
Figure 3. Hierarchical Organization of Speech APIs.......................................................................... 10

Tables
Table 1. Comparative Algorithm Execution......................................................................................... 3
Table 2. Description of the « copr » Opcodes .................................................................................... 5
Table 3. Data Flow Modes ..................................................................................................................... 6
Table 4. Characteristics of Video Hardware Accelerators ................................................................ 6
Table 5. MPEG4 Video Codec Power ................................................................................................... 7

1
SWPA001

1 Introduction
Every wireless handset contains two fundamental components: a modem and an applications
processing and delivery system. The modem communicates with a network to send and receive
data via an air interface. The applications component provides the functions that the user wants
in a multimedia appliance. These may include speech, audio playback, image reproduction and
streaming video, fax transmission and reception, e-mail, Internet connections, games, personal
organizer functions, and a host of other possibilities. The applications component also handles
user interface functions such as speech recognition (voice commands), keyboard, and written
character recognition. Except for user interface functions, all of these applications depend on the
air interface, which provides only limited bandwidth.
Managing the volume of data required for applications involving speech, audio, image, and video
within the available bandwidth requires heavy signal compression before transmission and
decoding or expansion within the receiver, which, for purposes of this paper, is a handheld
wireless appliance. Wireless appliances need additional signal processing capabilities for the
concurrent noise suppression and echo cancellation algorithms essential for even the most basic
functionality, i.e., voice telephony.
In many of today’s second generation (2G) wireless handsets, the modem component employs a
DSP, which provides the air interface and takes care of such essentials as noise suppression
and echo cancellation. The applications component, however, relies on a general purpose
processor (GPP), usually a RISC processor, which attempts to provide the signal processing
needed at the application level, user interfaces, and overall command and control functions.
In 2G appliances, which are, essentially, wireless telephones with extremely limited data
features, this processing dichotomy has generally proved to be satisfactory. However, for 2.5G
and 3G appliances, which offer such capabilities as full-motion video and high-fidelity audio
playback, the currently popular division of tasks between the two processors does not provide
reliably robust performance and still maintain the useful battery life that is acceptable to
consumers.
Next generation appliances, which include numerous applications enabled by high data rates
and real-time signal processing, continue to require both a DSP and a GPP. However, the
functional wall between the two basic appliance components breaks down as the demand for
signal processing within the applications component increases. The DSP, which is optimized for
intensive signal processing in real time with extremely low power consumption, becomes the
primary processor for both the modem and the applications component. The GPP plays a
secondary role, taking care of system management, command, control, and certain user
interface activities. The OMAP architecture provides a means to coordinate dual processors
across the two basic components of the wireless appliance and to seamlessly take advantage of
the unique capabilities of each. Nokia, Ericsson, Sony, Handspring, and others already have
selected the OMAP hardware and software architecture as the development platform for their
wireless appliances. The first samples of an OMAP-based chipset will be available in 4Q00.
In addition to enabling the numerous, media-rich applications made possible by 2.5G and 3G
data rates, the OMAP architecture also provides a new capability—the capability to dynamically
download applications and application upgrades from the web in the same way that PC users
download applications from the Internet today. This dynamic environment requires the
programmability offered by DSPs and the application programming interface (API) features built
into the OMAP architecture.

2 OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals

 SWPA001

2 OMAP Hardware Architecture

2.1 Advantages of a Combined RISC/DSP Architecture

The OMAP architecture is based on a combination of TI’s state-of-the-art TMS320C55x™ DSP
core and high performance ARM925T CPU. A RISC architecture, like ARM925T, is well suited
for control type code (Operating System (OS), User Interface, OS applications). A DSP is best
suited for signal processing applications, such as MPEG4 video, speech recognition, and audio
playback. The OMAP architecture combines two processors to gain maximum benefits from
each.
TI conducted a comparative benchmarking study, based on published data, which shows that a
typical signal processing task executed on the latest RISC machine (StrongARM™, ARM9E™)
requires three times as many cycles as the same task requires on a C55x™ DSP. See Table 1.
In terms of power consumption, tests show that a given signal-processing task executed on such
a RISC engine consumes more than twice the power required to execute the same task on a
C55x DSP architecture. Battery life, critical for mobile applications, therefore, is much greater
when such tasks are executed on a DSP. The OMAP architecture’s use of two processors
provides this kind of power consumption benefits. At the same time, it allows the DSP to gain
support from the RISC processor.
For instance, a single C55x DSP can process, in real-time, a full videoconferencing application
(audio and video at 15 images/sec.), using only 40 percent of the available computational
capability. Therefore, 60 percent of the capacity can be employed to run other applications
concurrently. At the same time, in the OMAP dual-core architecture, the ARM processor stands
ready to handle any other application requirements or can be suspended, thus saving battery
life. As a result, the mobile user can enjoy access to popular OS applications (Word™, Excel™,
etc.) while also engaging a videoconferencing application.
With a RISC processor alone, all of the available computing capacity would be needed to
execute only the videoconferencing application, and power consumption would be twice as great
as would be the case when the C55x DSP handles that application. The mobile user would not
be able to execute other applications simultaneously. And battery life would suffer dramatically.

Table 1. Comparative Algorithm Execution

ARM9E StrongARM 1100 TMS320C5510 Units
Echo cancellation 16 bits 24 39 4 Mcycles/s
(32 ms – 8 kHz)
Echo cancellation 32 bits 37 41 15 Mcycles/s
(32 ms – 8 kHz)
MPEG4/H263 decoding 33 34 17 Mcycles/s
QCIF @ 15 fps
MPEG4/H263 encoding 179 153 41 Mcycles/s
QCIF @ 15 fps
JPEG decoding (QCIF) 2.1 2.06 1.2 Mcycles/s
MP3 decoding 19 20 17 Mcycles/s
Average cycle ratio with 3.1 3 1
C5510™

Information based on published data.

OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals 3

SWPA001

2.2 How the Architecture Works

The OMAP hardware architecture, shown in Figure 1, is designed to maximize the overall
system performance of a 3G terminal while minimizing power consumption. This is achieved
through the use of a C55x DSP core and an ARM925T CPU. Both processors utilize an
instruction cache to reduce the average access time to instruction memory and eliminate power-
hungry external accesses. In addition, both cores have a memory management unit (MMU) for
virtual-to-physical memory translation and task-to-task memory protection.
ROM
RAM
SDRAM FLASH

SRAM

MEM IF MEM IF MEM IF

LEAD3 Core DSP INTH
Loc I-Cache
al M WD Timer DSP
Bu MU ME Periph. Bridge
Local s DSP MMU MO Rhea
Bus RY SARAM
I/F
I/F DSP DMA
DARAM Controller 3 Timers
MEMORY I/F
HS M
MU Multiport / UART
HSA A PDROM
Bus I/F Multichannel
DMA controller API
C5510 megacell 16 GPIO

DPLL

Per CLKM
ARM925T Bri
dg
e
I-MMU D-MMU
ARM
Rhea
I-Cache D-Cache

ARM9TDMI ARM INTH WD Timer 3 Timers

LCD Controller
Int
Te egr
st atio JTAG
& n

OMAP

Figure 1. OMAP Hardware Architecture

The OMAP core contains two external memory interfaces and one internal memory port. The
external memory interfaces support direct connection to synchronous DRAMs at up to 100 MHz
and to standard asynchronous memories, such as SRAM, FLASH, or burst FLASH devices. The
latter interface is typically used for program storage. It can be configured as 16 or 32 bits wide.
The internal memory port allows direct connection to on-chip memory, such as SRAM, and can
be used for frequently-accessed data, such as critical OS routines or the liquid crystal display
(LCD) frame buffer. This reduces the access time and eliminates costly external accesses. All
three interfaces are completely independent and allow concurrent access from either processor
or direct memory access (DMA) unit.

4 OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals

 SWPA001

The OMAP core also contains numerous interfaces to connect to peripherals or external devices
from either the DSP or GPP. To improve system efficiency, these interfaces also support DMA
from each respective processor’s DMA unit. The local bus interface is a high-speed,
bidirectional, multimaster bus that can be used to connect to external peripherals or additional
OMAP-based devices in a multicore product. Additionally, a high-speed access bus is available
to allow an external device to share the main OMAP system memory (SDRAM, FLASH, internal
memory). This interface provides an efficient mechanism for data communication and also
allows the designer to reduce system cost by reducing the number of external memories
required in the system.
To support common operating system requirements, the OMAP architecture includes several
peripherals—timers, general purpose input/output interfaces (I/Os), a UART, and watchdog
timers. These are the minimum peripherals required in the system; other peripherals can be
added on the TI peripheral bus (TIPB) interfaces. A color LCD controller is also included to
support a direct connection to the LCD panel. The ARM DMA engine contains a dedicated
channel that is used to transfer data from the frame buffer to the LCD controller, where the frame
buffer can be allocated in the SDRAM or internal SRAM.

2.3 C55x DSP and Multimedia Extensions

The C55x DSP offers a highly optimized architecture for wireless modem and vocoding
applications execution. Corresponding code size and power consumption are also optimized at
system level. These features also provide advantages to a wider range of applications, though
there may be some trade-offs in performance or power consumption.
The flexible architecture of the TI DSP hardware core allows extension of the core functions for
multimedia-specific operations. The C55x DSP family are the first DSPs with such core level
multimedia-specific extensions, which facilitate the demands of the multimedia market for real-
time, low-power processing of streaming video and audio. The software developer has access to
the multimedia extensions using the copr() instruction as described in Table 2, using
combinations of C55x arithmetic instructions to create the desired data flow.

Table 2. Description of the « copr » Opcodes

Function of « Copr » Opcodes

copr () Qualify instruction

Copr(k6) Qualify instruction, pass k6
constant to MME control interface
Smem=ACx, Qualify instruction, write
copr() accumulator to memory (16-bit)
Lmem=ACy, Qualify instruction, write
copr() accumulator to memory (32-bit)

OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals 5

SWPA001

Table 3 indicates all data flow modes that can be built using the combination of arithmetic
instructions and the opcodes in Table 2.

Table 3. Data Flow Modes

DSP Multimedia Extension Data Flow Modes

Available
ACy = copr(k8, ACx, ACy)
ACy = copr(k8, ACx, ACy), Smem=ACz
ACy = copr(k8, ACx, ACy), dbl(Lmem)=ACz
ACy = copr(k8, ACx, Smem)
ACy = copr(k8, ACx, Xmem), Ymem=ACz
ACy = copr(k8, ACx, dbl(Lmem))
ACy = copr(k8, ACx, dbl(Xmem)), dbl(Ymem)=ACz
ACy = copr(k8, ACx, Xmem, Ymem)
ACx,ACy = copr(k8, ACx, ACy, Xmem, Ymem)
ACx = copr(k8, Ymem, Coef), mar(Xmem)
ACx = copr(k8, ACx, Ymem, Coef), mar(Xmem)
ACx,ACy = copr(k8, Xmem, Ymem, Coef)
ACx,ACy = copr(k8, ACy, Xmem, Ymem, Coef)
ACx,ACy = copr(k8, ACx, ACy, Xmem, Ymem, Coef)

One of the first application domains that will extend the functionality of wireless terminals is
video processing. Motion estimation, discrete cosine transform (DCT) and its inverse function
(IDCT), and pixel interpolation require the greatest number of cycles for a pure software
implementation using the C55x DSP processor. Consequently, these three application domains
are the first multimedia programming extensions that the C55x DSP supports. Table 4
summarizes the characteristics of the extensions.

Table 4. Characteristics of Video Hardware Accelerators

Multimedia (MM) Speed-up Factor
Extension Type
Motion estimation x5.2
DCT/IDCT x4.1
Pixel interpolation x7.3

Using the extensions, the overall video-codec application mentioned earlier is twice as fast as a
classic software implementation. By reducing cycle count, the DSP real-time operating
frequency and, thus, the power consumption are also reduced.

6 OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals

 SWPA001

Table 5 summarizes current consumption (at maximum and lowest possible supply voltage) of a
C55x DSP video MPEG4 Coder/Decoder using multimedia extensions, for various image rates
and formats.

Table 5. MPEG4 Video Codec Power

Formats mA @1.5 V mA @ 0.9 V
and Rates (15C035) (15C035)
QCIF, 10 fps 12 7
QCIF, 15 fps 19 11
QCIF, 30 fps 37 22
CIF, 10 fps 49 29
CIF, 15 fps 74 44

3 OMAP Software Architecture

The OMAP architecture includes an open software infrastructure that supports application
development and provides a dynamic upgrade capability for heterogeneous multiprocessor
system design. This infrastructure includes a framework for developing software that targets the
system design and APIs for executing software on the target system.
The 2.5G and 3G wireless systems merge the classic voice-centric telephone phone model with
the data functionality of the personal digital assistant (PDA). Non-voice multimedia applications
(MPEG video, MP-3 audio, etc.) also will be downloaded to future phone platforms. These
systems will also have to accommodate a variety of popular operating systems, such as
WinCE™, EPOC™, and others. The dynamic, multitasking nature of these applications will
require the use of operating systems on the DSP as well.
As a result, the OMAP architecture requires software that is sufficiently generic to allow easy
adaptation and expansion for future technology. At the same time it must provide I/O and
processing performance that approach the performance of a specific targeted architecture.
It is important to be able to abstract the implementation of the DSP software architecture from
the GPP environment. The OMAP architecture accomplishes this by defining an interface
scheme that allows the GPP to be the system master. This interface scheme is called the
DSP/BIOS™ Bridge and consists of a set of APIs that includes device driver interfaces. See
DSP API in Figure 2.

OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals 7

SWPA001

Figure 2. How the OMAP Architecture Works

The most important function of the DSP/BIOS Bridge is providing communications between GPP
applications and DSP tasks. The DSP/BIOS Bridge API is abstracted from the high-level
application developers by a set of DLL and drivers that is provided in the development toolkit for
the platform. This allows application developers to develop on the OMAP platform in the same
manner as if they were developing on a single RISC processor. The environment provided for
development allows the application developer to call the localized functions for video, audio,
speech, etc. and to develop in the traditional manner on platforms such as the PC. The high-
level application developer does not require any awareness of the DSP or DSP/BIOS Bridge
API.
The DLL and driver developers actively use the DSP/BIOS Bridge API to:

• Initiate and control tasks on the DSP

• Exchange messages with the DSP

• Stream data to and from the DSP

• Perform status queries

8 OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals

 SWPA001

Although the design initially targets a limited set of OSs, the underlying architecture facilitates
expansion of this list in the future. Standardization and reuse of existing API and application
software are the main goals for the open platform architecture, thus allowing extensive reuse of
previously developed software and a faster time to market of new software products.

4 OMAP Multimedia Applications

4.1 Video
Video applications include two-way videophone communication and one-way decoding or
encoding, which may be used for entertainment, surveillance, or video messaging. While
second-generation communicators support speech only, coded at 8 to 13 kbps, even low-motion
video on a small display requires at least 20 kbps. 3G wireless standards will make possible the
higher bit rates required for more sophisticated video-related applications.
Compressed video is particularly sensitive to errors that can occur with wireless transmission.
To achieve high compression ratios, variable-length code words are used, and motion is
modeled by copying blocks from one frame to the next. When errors occur, the decoder loses
synchronization, and errors propagate from frame to frame. The new MPEG-4 standard supports
wireless video with special error resilience features, such as added resynchronization markers
and redundant header information. The MPEG-4 data-partitioning tool, originally proposed by TI,
puts the most important data in the first partition of a video packet, which makes partial
reconstruction possible for better error concealment.
TI’s MPEG-4 video software for OMAP architecture is based on reference C software, which is
converted to use ETSI C libraries and then ported to C55x DSP assembly code. The ETSI C
libraries consist of routines representing all common DSP instructions. The ETSI routines
perform the desired function and also evaluate processing cycles and check for saturation, etc.
Thus, the ETSI C, commonly used for testing speech codecs, provides a tool for benchmarking
and facilitates porting the C code to assembly.
As shown in Section 2.2, the video software runs efficiently on the OMAP architecture. The
architecture is able to encode and decode in the same time QCIF (176 ×144 pixels) images at
15 frames per second. The CPU loading for simultaneous encoding and decoding represents
only 15 percent of the total DSP capability. Therefore, 85 percent of the CPU is still available to
other tasks, such as graphic enhancements, audio playback (MP3), or speech recognition.
The assembly encoder is under development and typically requires about three times as much
processing as the decoder. The main processing bottlenecks are motion estimation, DCT, and
IDCT. However, through tight coupling of hardware and software, the OMAP architecture
improves the video encoding execution by a factor of two.
The OMAP architecture provides not only the computational resources, but also the data-
transfer capability needed for video applications. One QCIF frame requires 38016 bytes, for
chrominance components downsampled in 4:2:0 format, when transferring uncompressed data
from a camera or to a display. The video decoder and encoder must access both the current
frame and the previously decoded frame in order to perform the motion compensation and
estimation, respectively. Frame rates of 10- to 15-frames per second must be supported for
wireless applications.

OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals 9

SWPA001

Third-generation standards for wireless communication, along with the new MPEG-4 video
standard, and new low-power platforms like the OMAP architecture will make possible many
new video applications. It is quite probable that video applications will differentiate 2G and 3G
devices, creating new markets and higher demand for wireless communicators.

4.2 Speech Applications

A typical embedded system has constraints of low power, small memory size, and little or no
disk storage. Therefore, speech recognition algorithms designed for embedded systems, such
as wireless phones, must minimize resource usage while providing acceptable recognition
performance.
TI proposes a dynamic vocabulary speech recognizer that is split between the C55x DSP and
the ARM processor. The computationally intensive, small-footprint speech recognition engine
runs on the DSP, while the computationally non-intensive, larger footprint grammar, dictionary,
and acoustic model generation components reside on the ARM processor. The interaction
between the model generation and recognition modules is minimized and conducted via a
hierarchy of APIs, as shown in Figure 3. The advantage of this architecture is that the application
can handle new vocabularies in several (potentially unlimited) recognition contexts without pre-
compilation or storage of the grammars and models.

Speech-enabled
Application

Standard Speech API

(e.g. JSAPI or SAPI)

Speech Primitives
[e.g. load_grmrs(), start_rec(),
stop_rec(), get_result(), start_tts(),
tts_speak(), pause_tts(),
ARM
set_spkr()…]
OMAP DIRECT DSP API
DSP

Figure 3. Hierarchical Organization of Speech APIs

Note that only the unit selection and waveform generation modules of the Text-to-Speech (TTS)
are on the DSP.

10 OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals

 SWPA001

For each new recognition context, the grammars and acoustic models are generated
dynamically on the ARM processor and transferred to the recognizer on the DSP. This dynamic
vocabulary capability of the speech recognizer is crucial on resource-constrained wireless
devices. For example, a voice-enabled web browser on the phone can now handle several
different web sites, each with its own different vocabulary, without compiling or storing
vocabularies and speech grammars beforehand. Similarly, for a voice-enabled stock quote
retrieval application, company names can be dynamically added to or removed from the stock
portfolio. At any given time, the size of the active vocabulary is limited by the resource
constraints on the DSP (e.g., size of the RAM available for the recognition search). However,
given that different vocabularies can be swapped in and out depending on the recognition
context, the application can be designed to give the perception of an unlimited speech
recognition vocabulary.
Similarly, the text-to-speech (TTS) system on the wireless device can be split between the ARM
processor and the DSP. The text analysis and linguistic processing modules of the TTS reside
on the ARM processor along with the phonetic databases. The unit selection and waveform
generation modules reside on the DSP. As with the speech recognizer, the interaction between
the ARM processor and DSP modules is minimized and conducted via a hierarchy of APIs.

5 Conclusion

This paper has described how the OMAP hardware and software architecture will enable
multimedia applications in 3G wireless terminals. The OMAP multiprocessor architecture has
been optimized to support heavy multimedia applications, such as video and speech in 3G
terminals. Such a complex architecture, combining two heterogeneous processors (RISC and
DSP), several OS combinations, and applications running on both the DSP and ARM can be
made accessible seamlessly to application developers because of the DSP/BIOS Bridge feature.
Moreover, this dual processor architecture is more cost efficient and power efficient than a single
processor solution.

Open Multimedia Applications Platform, OMAP, TMS320C5510, TMS320C55x, C55x, DSP/BIOS are trademarks of
Texas Instruments.

ARM, StrongARM, ARM9E, ARM10 are trademarks of Advanced RISC Machines, Ltd.

Word, Excel and WinCE are trademarks of Microsoft.

EPOC is a trademark of Symbian, Ltd.

All other trademarks are the property of their respective companies .

OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals 11

SWPA001

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their
products or to discontinue any product or service without notice, and advise customers to
obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current and complete. All products are sold subject to the
terms and conditions of sale supplied at the time of order acknowledgement, including
those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at
the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer's applications, adequate design
and operating safeguards must be provided by the customer to minimize inherent or
procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does
not warrant or represent that any license, either express or implied, is granted under any
patent right, copyright, mask work right, or other intellectual property right of TI covering
or relating to any combination, machine, or process in which such semiconductor
products or services might be or are used. TI's publication of information regarding any
third party's products or services does not constitute TI's approval, warranty or
endorsement thereof.
Copyright  2000 Texas Instruments Incorporated

12 OMAP: Enabling Multimedia Applications in Third Generation (3G) Wireless Terminals

 T H E W O R L D L E A D E R I N D S P A N D A N A L O G

Product Bulletin
Key Features

OMAP1510 • Dual-core architecture optimized for

efficient operating system and multimedia
Application Processor for 2.5 and 3G code execution
• TMS320C55x™ DSP core provides
Wireless Devices superior multimedia performance while
delivering the lowest system-level
power consumption
• TI-enhanced ARM™ 925 core with an
added LCD frame buffer to run command
and control functions and user interface
applications
• Rich set of peripherals including USB
Client; USB Host; and camera, audio
and memory interfaces allow
developers to customize their products
to their customers’ needs
• Small, 289-pin MicroStar™ BGA
package (12 x 12 mm) eases design in
space-constrained devices
• DSP/BIOS™ Bridge allows easy-to-
integrate DSP multimedia algorithms
• Open platform enables a large network
of independent developers providing a
broad range of OMAP™ architecture
compatible software solutions
• Code Composer Studio™ Integrated
Development Environment (IDE) is part
of TI’s award winning eXpressDSP™
Real-Time Software Technology that
The OMAP1510 processor is a unique dual-core architecture that combines the slashes development and integration
command and control capabilities of the TI-enhanced ARM™ 925 time by up to 50%
processor with the high-performance and low power capabilities of the
TMS320C55x™ DSP core.

As the wireless market continues sumer expects this rich functionali- The OMAP processor is the ideal
to grow, the OMAP™ platform ty while continuing to demand engine for wireless multimedia
from Texas Instruments (TI) will longer battery life and smaller, applications processing. TI DSP
help meet wireless devices sleeker products. The OMAP technology is the key to providing
increasing consumer expectations. architecture features open hard- both the high performance and
Next-generation wireless multime- ware and software that drives the low-power consumption required
dia appliances will include more quick introduction of differentiated in these next generation mobile
than just voice communications. products for next-generation wire- products. In addition, OMAP archi-
As full-motion video, video confer- less appliances. The OMAP archi- tecture is open, providing flexibility
encing, voice recognition, real-time tecture has a high-performance, and a programmable platform for
Internet and high-fidelity audio are ultra-low-power TMS320C55x™ developers. The OMAP processor
integrated into these wireless digital signal processor (DSP) core supports advanced operating sys-
appliances, a general-purpose for efficient execution of real-time tems (OS) such as Microsoft
processor alone will not be able to multimedia applications as well as a Windows® CE and Symbian
handle the processing perform- TI-enhanced ARM™ 925 processor EPOC™ as well as standard multi-
ance needed while meeting bat- to run command and control function media application programming
tery life expectations. The con- and user interface applications. interfaces (APIs). Developers can
leverage a wide range of software decode and encode, MP3 decode OMAP Architecture
developer’s networks, including and encode, JPEG decode and The OMAP1510 processor is
TI DSP third parties, ARM third encode and advanced speech based on the unique dual-core
parties, TI OMAP developers and applications such as text-to- architecture that combines the
OS third parties. The OMAP speech, speech recognition and command and control capabilities
processor enables real-time Adaptive Multi-Rate (AMR). This of the TI-enhanced ARM 925 core
communications with the extended combination of cores and periph- with the benchmark performance/
battery life that consumers demand. erals provides the best-in-class power capabilities of the C55x
The OMAP1510 is the first power and performance ratio for DSP engine. The TI-enhanced
applications processor specifically both standard and custom ARM 925 core is an industry lead-
targeted for 2.5 and 3G wireless processors for wireless devices. As ing implementation of the ARM
devices. The OMAP1510 proces- an example, the OMAP1510 pro- RISC architecture that operates
sor combines a TI-enhanced ARM vides the same processing power up to 175 MHz. The TI-enhanced
925 core with a C55x™ DSP core of a standalone RISC processor ARM 925 includes a memory man-
along with a wide range of gener- but uses just 1/4th the power. agement unit (MMU) for virtual-
al-purpose peripherals and The OMAP1510 is initially to-physical memory translation
dedicated multimedia application targeted at PDA and smart phone and task-to-task memory protec-
peripherals. The OMAP1510 has applications although it is sched- tion as well as a 16KB instruction
been optimized for power efficient uled to be offered for a wider cache, an 8KB data cache and a
execution of the key multimedia range of applications in the sec- 17 word write buffer. There is
applications including MPEG-4 ond half of 2001. 1.5 Mb of internal SRAM provid-

OMAP1510 Application Processor for 2.5 and 3G Wireless Devices

Program
Memory SDRAM

Uart (x3)
1.5 Mb USB Client
I SRAM
USB Host
Microwire™
I Cache
Interface to Applications

Traffic I2C Host

Controller D Cache
MMU

GPIO
Peripherals

+DMA TI-Enhanced PWT

ARM™ 925
Core PWL
McBSP x3
I Cache
PCM Audio I2S
Interface
Power uLaw SPI x2
MMU

Management TMS320C55x™
LCD Keyboard
for External Control DSP Core
Modem Controller Camera Interface
Interface SD/MMC
RTC
Clock JTAG/ETM9 Modem Interface
Bluetooth™ Interface

Clocks LCD MPU System Test/Real-Time

Interface SW Debug

2
ing a large memory space for space as well as between periph- peripherals can occur in the
power efficient on-chip data and erals without Microprocessor Unit background of MPU operation.
code storage for applications such (MPU) intervention.
Camera Interface
as liquid crystal display (LCD)
LCD Controller Video applications will be an
frame buffering. A two level inter-
The LCD controller allows a important part of next-generation
rupt handler provides 32 inter-
direct connection to a black and wireless appliances. A camera
rupt lines including 13 internal
white or color LCD panel, either interface allows the OMAP1510
and 19 external interrupts. Also
super twist nematic (STN) or thin to connect directly with a camera
included in the core is the ARM
film transistor (TFT), reducing module for video conferencing
CP15 coprocessor and protection
the system component count and and other video applications.
module.
power consumption. The frame The interface uses 8-bit parallel
DSP Advantage buffer can be allocated in external image data, pixel clock and
The 200 MHz C55x DSP core sets SDRAM or internal 1.5Mb SRAM horizontal/vertical sync signals for
the DSP industry’s benchmark for improved power efficiency. A the interface. Additionally, a clock
power and performance ratio. dedicated channel on the DMA can be provided to the external
Three key innovations enable unit is used to transfer data from camera at various configurable
this: increased idle domains, the frame buffer to the LCD con- frequencies. The pixel clock can
variable length instructions and troller. The LCD controller can be synchronous or asynchronous
increased parallelism. The C55x support 2/4/8/12/16-bits per pixel depending on the requirements
DSP core has a highly optimized and a 1024x1024 display. of the external camera module.
architecture for multimedia A DMA port allows camera data
Memory Interfaces
applications, including core level to be transferred without the
The OMAP1510 processor con-
extensions that facilitate the need for MPU intervention.
tains three memory interfaces–
demands of the multimedia mar-
two external and one internal. Air Interface
ket for real-time, low-power pro-
The external memory interfaces An external modem device
cessing of streaming video and
support direct connection to can be connected directly to the
audio. The C55x DSP core con-
64MB of addressable SDRAM up OMAP1510 through a modem
tains three multimedia extensions
to 100 MHz and to 32MB of interface, allowing both data and
to further improve the power
addressable Flash (asynchronous voice communications. The inter-
efficiency. These are motion esti-
or burst), random access memory face has been designed to work
mation, discrete cosine transform
(RAM) or read only memory with any air interface standard,
(DCT), inverse discrete cosine
(ROM) devices. Both of these making it easy to use in any
transform (IDCT) and 1/2- pixel
external memory interfaces are system. The data is transferred on
interpolation. The addition of
16-bits data wide and support the TI standard Multi-channel
this hardware accelerator enables
external devices having 2.75-V or Buffered Serial Port (McBSP) at
video applications to run up to
1.8-V (typical) interfaces. The configurable rates up to 6 Mbps
twice as fast while also reducing
internal memory port connects to while the control is done through
the power consumption.
the 1.5 Mb of on-chip SRAM. All a UART along with control signal
The C55x DSP core includes
three memory interfaces are lines for the clock and power. The
32 kwords of internal dual-access
accessible and can be shared by 8-kHz voice data can be trans-
SRAM, 48 kwords of internal
the TI-enhanced ARM 925 MPU, ferred by the Multi-Channel Serial
single access SRAM and a
C55x DSP core and system DMA. Interface (MCSI). The McBSP
12 kword instruction cache. The
The system DMA is included to and universal asynchronous
C55x DSP core also includes an
allow transfers of data between receiver transmitter (UART) have
MMU as well as a dual layer inter-
points in the memory space DMA support, reducing the MPU
rupt handler and a direct memory
without MPU intervention. Data loading.
access (DMA) unit. The DMA
movements to and from internal
allows the transfer of data
memory, external memory and
between points in the memory

3
OMAP1510 2.5 and 3G Wireless System Diagram

Touch Flash SDRAM

Screen 16-64MB 8-64MB
32 kHz IrDA
Bluetooth™
12 MHz
6 16 16 5
8 JTAG
Data McBSP UART
Voice 2 I2C
McBSP TMS320C55x™ TI-Enhanced
6 ARM™ 925
DSP Core Core 32 GPIO
Serial
OMAP1510
Traffic Controller/DMA Buzzer
UART 1
4
LED
1
Program/data
USB Host USB SRAM Reset
Client
5 Hub Frame
Air Buffer
Interface Data 5
Keypad
McBSP USB Mux McBSP 16
Voice 6

5 6 16 5 13
External USB
Host/Client USB LCD SD/MMC Camera
Connector Display
Audio
Codec
48 kHz
Audio
In/Out

Bluetooth™ Interface can be used for 8-kHz voice data serial communication up to
The Bluetooth™ standard will and has a four-wire interface with 115.2 kbps. The three UARTs
allow short distance wireless bi-directional data, a serial clock have 64 word receive and trans-
connectivity so that wireless and frame sync. mit FIFOs with programmable
multimedia appliances can be trigger levels and offer even, odd
Universal Asynchronous
connected with other appliances, or none transmit parity along with
Receiver Transmitter (UART)
a home computer or local area 1, 1.5 or 2 stop bits.
Three 16C750 compatible UARTs
network. A Bluetooth interface,
are included in the OMAP1510. I2C Host
provided by a high-speed UART
All are controllable through a The OMAP1510 includes an I2C
and MCSI serial port on the
software interface or through host port compliant with Philips
OMAP1510 processor allows
hardware flow control signals. I2C standard. The interface is a
developers to easily incorporate
Two of the UARTs, as mentioned single master only, half-duplex
this feature in their next-
above, are intended for modem serial port using two lines (data
generation wireless devices. The
and Bluetooth interfaces but are and clock) for data transmit with
Host Control Interface is done
not limited to those applications. software addressable external
through a standard UART with
The third UART includes optional devices. Both standard 100-kHz
extended baud rate options up to
infrared data adapter (IrDA) 1.0 and fast 400-kHz transmit modes
1.625 Mbps by using an externally
serial infrared (SIR) support for are supported. Burst write, single
supplied baud clock. The MCSI

4
read and combined read modes computer or other master device. Loop (PLL) and power manage-
are all supported. A transmit The OMAP1510 also has a USB ment. The MPU and DSP each
burst buffer of 16 words allows host controller, with up to three have three 32-bit timers and a
for continuous transmission down stream ports, allowing watchdog timer.
of data. connection to high-speed modem
Space Saving Package
devices or USB peripherals such
PWT Generator The OMAP1510 comes in a
as a mouse, keyboard or camera.
A pulse width tone (PWT) space-saving 289-pin MicroStar™
Both the host and client con-
generator generates a modulated ball-grid array (BGA) package
trollers are compliant with the
frequency signal for the external with 0.5-mm ball pitch. The
USB specification version 1.1.
buzzer. The frequency is 12 x 12-mm package is ideal for
programmable between 349 Hz SD/MMC Interface ultra-small, ultra-light designs.
and 5276 Hz with 12 half-tone A Secure Digital (SD)/MultiMedia
Tools and Support
frequencies per octave. In addition, Card Controller (MMC) interface
TI will offer a wide range of sup-
the PWT is volume programma- allows connection of industry
port for OMAP platform products
ble, allowing the user to select standard flash storage cards and
including PC-based application
how loud their phone rings. To I/O peripherals for storage of large
development tools and an evalua-
control the backlight of the LCD multimedia data like digital audio,
tion module (EVM) with a User’s
and keypad, a pseudo-noise pulse digital video, maps and digital still
Guide and Technical Reference
width light (PWL) modulator is photos. The I/O peripheral mode
Manual to help speed designs to
also included. allows for the addition of future
market.
peripherals. The SD/MMC inter-
Serial Ports Application software developers
face is compliant with the MMC
The OMAP1510 processor can use the same PC-based
standard specification version
includes many different types of emulation tools currently provid-
2.2 and the SD Physical Layer
serial ports. Two McBSPs can be ed by the OS manufacturers with
specification version 1.0.
used for interface to an audio added TI OMAP extensions. This
codec for digital audio input and Additional Features allows application developers to
output (using I2S interface The OMAP1510 processor also develop in the same environment
protocol for example) or can be offers support for licensees of they are used to and tap into the
configured to connect to an MemoryStick™ or OpenMG™ OMAP processor capabilities by
external optical audio interface technology. This allows the simply calling into the software
device. A Microwire™ standard consumer to add flash cards to extensions that represent the
compatible interface is included their wireless appliance that extensive base of DSP algorithms.
for connecting external devices contain programs, games, The application developers can
such as a serial EEPROM or LCD. personal information, music or quickly develop software, using
The 14-bit general-purpose other data important to them. available DSP algorithms, without
input/output (GPIO) can be A real-time clock (RTC) having to use either the EVM
dedicated to either the DSP or keeps track of the current time hardware or learn the internal
the microcontroller unit (MCU). in seconds, minutes and hours complexities of the DSP algorithm.
A 5-bit GPIO dedicated to the and allows for devices to include For development of DSP
MCU is also provided. A general alarm clock functionality. algorithms and the DSP gateway
serial port interface (SPI) is Calendar information like day, components on the TI-enhanced
included and can be used as a month, year and day of the week ARM 925, the programmer can
voice communication interface. up to the year 2099 is also use the TI Code Composer
provided. Studio™ Integrated Development
USB Client and Host
Other features of the OMAP1510 Environment (IDE), a component
The OMAP1510 processor
include a keyboard interface that of TI’s award winning eXpressDSP™
includes a universal serial bus
allows a direct connection of Real-Time Software Technology,
(USB) client controller for
a 6x5 or 8x8 matrix keyboard, and EVM. Code Composer Studio
high-speed plug-and-play syn-
a JTAG and emulation interface, is a fully integrated development
chronization with a personal
a clock generator with Phase Lock environment that improves time-

5
OMAP™ Software Architecture

Applications

MM API Real-Time Tasks

Protocol
DSP Gateway Video Web Speech Video Audio Speech
Media
Framework

DSP/BIOS Bridge API DSP/BIOS Bridge API

DSP/BIOS™ Bridge

DSP Manager
Host OS DSP Manager Data Streams DSP/OS
Server
(EPOC/ (BIOSII/
Windows® OSE)
CE)
Link Driver Link Driver

TI-Enhanced ARM™ 925 Core TMS320C55x™ DSP Core

to-market and covers all phases of mation are included to get prod- tion developer calls localized DSP
development, from editing and ucts to the market faster. OMAP gateway components to perform
building to debugging, code profil- supports multiple OSs on the DSP different functions like video,
ing and project management. including TI’s DSP/BIOS and audio and speech. Thus, high-
Code Composer Studio includes a OSE™, from Enea OSE systems. level application developers do
full compiler, simulator and not need to be knowledgeable
OMAP1510 Software Applications
debugger for the OMAP1510. The about using the DSP or DSP/BIOS
Platform
Visual Project Management sys- Bridge API to successfully intro-
The OMAP1510 includes an
tem allows visualization, access duce new applications. Once an
open software architecture that
and manipulation of all project application has been developed
supports fast application develop-
files from the same window. Code using this standard API, it will be
ment and provides the ability
Composer Studio also supports compatible with future wireless
to dynamically download applica-
the development of systems appliances based on the OMAP
tions and application upgrades.
with multiple processors using platform.
The DSP/BIOS™ Bridge provides
the Parallel Debug Manager The OMAP platform currently
the communications between the
(PDM). DSP/BIOS™, also part supports Microsoft Windows CE
applications on the TI-enhanced
of eXpressDSP, is a scalable, and Symbian EPOC operating
ARM 925 and algorithms on the
real-time kernel for the C55x DSP systems. Other operating systems
C55x DSP core. The DSP/BIOS
core that provides a standard are planned for the OMAP plat-
Bridge API allows developers to
software base that reduces cost, form in the near future. TI is also
initiate and control tasks on the
risk and development time. investing in technologies, such as
DSP, exchange messages with the
Common run-time objects and JAVA™, which will allow a larger
DSP, stream data to and from the
utilities such as I/O modules, a software developer base.
DSP and perform status queries.
fast preemptive scheduler and
In this environment, the applica-
APIs for capturing real-time infor-

6
OMAP Developers Network The OMAP Developer Network Availability
The OMAP software infrastructure will benefit the wireless device The OMAP1510 processor is ini-
is optimized for use by manufacturer in many different tially targeted at PDAs and smart
software developers. Software ways. The manufacturer can now phone manufacturers. TI is ship-
developed using the standard rely on expert outside developers ping production samples of the
DSP/BIOS will be OMAP proces- to deliver specialized program- OMAP processor today, and the
sor compatible. TI is working with ming specifically for their plat- OMAP1510 is scheduled to be
software developers to develop form. Since the software develop- available in volume production
application software, DSP algo- ers have already invested the quantities in third quarter 2001.
rithms, and gateway components time and resources building
For More Information
for the OMAP platform. expertise in their particular area,
To find out more about how the
There are a number of applica- these applications will add value
OMAP1510 processor is the ideal
tion areas for OMAP developers to any platform. To provide the
engine for 2.5 and 3G wireless
to focus on for 2.5 and 3G wire- highest performance possible, the
devices, call your local sales office
less appliances. Some promising software developer has already
or visit the TI web site. Find out
areas include: optimized their code between
how TI products can help make
the DSP and microprocessor, this
• Multimedia: streaming your next-generation systems
allows faster time-to-market for
audio/video, broadcast, players easier to design with higher
manufacturers.
• Games: 2D, 3D performance and lower power
TI has an existing DSP Third
• Location-based services: GPS, consumption.
Party Program with the most
network-assisted solutions Please visit us at:
extensive collection of DSP devel-
• Security (user interface): www.omap.com
opment support in the industry.
biometrics, user authentication
With access to TI’s DSP Third
• Security (infrastructure):
Party Network, the list of potential
encryption/decryption,
applications leveraging the per-
firewall, user verification,
formance of the DSP is ever-
anti-virus
expanding. Given the wide variety
• Business applications: database
of application software being
management, spreadsheet,
developed, a hardware manufac-
synchronization, application
turer can put together software
navigation via speech
from many different developers
to get the right mix for their
customers.

7
TI Worldwide Technical Support

Internet
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Home Page
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TI Semiconductor KnowledgeBase Home Page

www.ti.com/sc/knowledgebase

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Phone International +81-3-3344-5311 Important Notice: The products and services of Texas Instruments and
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A030101

The red/black banner, OMAP, TMS320C55x, DSP/BIOS, eXpressDSP and Code Composer Studio are trademarks of Texas Instruments.
Bluetooth is a trademark of Telefonakiebolaget L M Ericsson and licensed to Texas Instruments.
All other trademarks are the property of their respective owners.

© 2001 Texas Instruments Incorporated

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