2017 International Conference on Advanced Computing and Communication Systems (ICACCS -2017), Jan.

06 – 07, 2017, Coimbatore, INDIA

Scaling Effect of Cylindrical Surrounding

Double-Gate MOSFET: A Device Beyond
22 nm Technology
Viranjay M. Srivastava
Department of Electronic Engineering,
Howard College, University of KwaZulu-Natal,
Durban - 4041, South Africa.
[email protected]

Abstract – The scaling of the device, for the vertical surrounding-gate MOSFET [5, 6]. The cylindrical
application of VLSI and ULSI technology, is device fabrication on a cylindrical pillar of silicon (may
necessary. For this purpose a novel model of DG be horizontal or vertical) has the properties of reduced
MOSFET has already been designed, after that SCEs and improved subthreshold slope with higher
FinFET and nanowire techniques introduced. But to packing densities [7]. The double-gate (DG) MOSFETs
further improvement for the latest technologies, the fabricated on SOI substrates is also a device which can be
CDSG MOSFET, a novel model has an advantage of used for the short channel applications [8].
the scaling. Using this CSDG MOSFET beyond 22 nm
technology, the effect on the parameters like threshold The detailed scaling theory has been introduced by
voltage, switching speed, drain current and power etc. Suzuki et al. [9] for double-gate SOI MOSFETs which
has been discussed in this research work. was based on the minimum potential at the center part of
channel. The proposed hypothesis don’t precisely
Keywords – CSDG MOSFET, Double-gate modeled the surrounding gate MOSFETs as the gate has
MOSFET, Scaling of device, nanotechnology, VLSI. larger control on the channel potential due to the
cylindrical structure. But the cylindrical MOSFET is one
I. INTRODUCTION of the emerging members of gate all around (GAA) family
for the CMOS technology [10]. The GAA architectures
Latest communication systems requires high are easier to integrate and with less parasitic on SOI, thin
frequency, integrated systems, multi-standards, and low SOI, and substrates. In this present research work, a
power consumption for better performance also under comparable scaling theory has been established regarding
adverse environment as high temperature, radiation and cylindrical surrounding double-gate (CSDG) MOSFET as
congestion [1]. In some applications this performance shown in fig. 1. The analysis proves the enhanced
depends on the RF switches. These switches require a characteristics of CSDG MOSFET devices over the DG
high performance technology that can easily accomplish MOSFET devices. In this work an attempt to check the
operating frequencies in the GHz range. These switches effect of the parameters by the scaling of CSDG
can be made up of the MOSFETs. Multiple-gate devices MOSFET has been done [11].
such as double-gate (DG) MOSFET, OmegaFET,
FinFETs have developed as a favorable device to For the designing perspective the threshold voltage
substitute the planar MOS technology for very large scale and process parameters can not be controlled. In the
integrated (VLSI) circuits beyond 22 nm. It is due to its designing only the width, length, and connection scheme
higher integration property [2]. The main advantages of of the transistors of a particular process can be controlled
these devices are lower short channel effects (SCE), which refers to scaling of device. Mainly the scaling
steeper sub-threshold slope, and reduced variability means to the decrease in extent of the MOSFETs used for
impact [3]. There is still a discussion about the most the purpose of VLSI and ULSI technology. It allows to
reliable and adequate nonplaner multigate device use less power and less area hence drives the latest
substrate, SOI or bulk is going on [4]. electronic revolution. By this technique operational
characteristics of MOSFETs and parasitic elements can be
As the semiconductor devices scaled into the sub- affected. But physical limits restrict degree of scaling that
micron system, the SCE and poor sub-threshold can be achieved. So in this work the work related to the
characteristics starts to plague traditional planar CSDG MOSFET has been extended [12].
transistors. Silicon dioxide has been used as the dielectric
material from decades, and the latest device scaling trend This paper is organized as follows. The design of
requires the film thickness (tox) of approximately 1.5 nm CSDG MOSFET has been structured in the Section II. It’s
to 5 nm. Due to this, the higher packing density is feasible scaling constant and effect on various parameters have
in communication devices and switches. One of the been discussed in the Section III. A procedure to apply the
promising structures of the higher packing density is the voltage duality has been given in the Section IV. The

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2017 International Conference on Advanced Computing and Communication Systems (ICACCS -2017), Jan. 06 – 07, 2017, Coimbatore, INDIA

effect on capacitance for this model has been done in the TABLE I. TECHNOLOGY NODE AND INTERCONNECTS
Section V. Finally, the Section VI concludes the work and [18, 19].
recommends the future works. Year Technology (nm) No. of interconnects
2008 29 7
II.STRUCTURE OF CSDG MOSFET 2011 22 8
2014 16 10
Devices scaling below 50 nm technology has made 2017 7 11
the planer traditional MOSFET to suitable for SCEs like 2020 4 12
drain induced barrier leakage (DIBL), gate induced drain
leakage (GIDL), and reduced gate control [13]. To III.SCALING CONSTANT AND EFFECT ON
overcome these issues, cylindrical surrounding gates
MOSFETs are the better suitable replacement of DG
VARIOUS PARAMETERS
MOSFET etc. due to their excellent electrostatic control
In this scaling design the VDD and VT has been kept
over the channel from both sides. The fabrication
unchanged means the present analysis is for the constant
processes of these cylindrical surrounding gate MOSFETs
voltage scaling [19]. This threshold voltage is a critical
has been reported in [14, 15]. The circuits using Si
part to determine the functionality of MOSFET. So the
nanowire (CGNW) FETs having diameters as small to 3
power supply and terminal voltages are kept constant,
nm have been reported in [16]. In this present work, the
while all the process dimensions are scaled down be a
cylindrical structure has been extended to the CSDG
factor SCSDG, means the device lengths are reduced by the
MOSFET as shown in fig. 1.
factor SCSDG. As the device size reduced and the number
of charges are fixed, so the doping densities will increased
By scaling, increased current of device, packing
by a factor of SCSDG2 to keep constant the charge and field
density, functionality of chip, performance and
relationship.
complexity and speed can be achieved with lower cost of
production. But the trade-offs are short channel effect,
As the device size reduces, the power dissipation and
higher leakage current and sub-threshold swing [17]. The
power density will higher. To define the scaling for
short channel devices exhibit higher sub-threshold leakage
CSDG MOSFET, a scaling factor SCSDG is introduced. For
current and more sub-threshold swing. These trades-off
the perfect scaling this SCSDG should be greater than 1. As
can be minimized with the help of CSDG MOSEFT
the threshold voltage and leakage currents are playing the
devices. Scaling is getting more difficult with the
critical role in determining the functionality of the
limitations in interconnects.
MOSFET devices, so these values should be kept as low
as possible which increases the switching speed of the
device. It is due to shortening the time to accumulate the
charge into the channel for a MOSFET to be turn ON. The
CSDG MOSFET can be scaled down using the rules as
suggested in ref. [19].

If the scaling factor S for traditional MOSFET is

related to the channel length L, means S D L , so the
W
aspect ratio of the MOSFET k that is channel
L
length:
(a) W
L (1)
k

where W is the width of the device for the traditional

MOSFET which is less than the 2b as in the model of fig.
1(a). Since the maximum diameter is 2b where b is the
maximum radius of the CSDG MOSFET.

For the CSDG MSOEFT this scaling factor will be

SCSDG D LCSDG , so the channel length for this CSDG
(b)
MOSFET:
Fig. 1. Schematic of (a) CSDG MOSFET and (b) its 2S r
LCSDG (2)
cross-section [11]. k

where radius r varies between a < r < b, which

concludes that the LCSDG ! L , so the SCSDG ! S .
With the use of this scaling ratio, the device
2017 International Conference on Advanced Computing and Communication Systems (ICACCS -2017), Jan. 06 – 07, 2017, Coimbatore, INDIA

dimensions are scaled down and other parameter also voltage. These parameters are source/drain implant,
changes. It is directly corresponds to the channel length or compensation implantation etc. But these considerations
device length. To achieve the optimal value the have not been taken care in the present work.
researchers in [1, 19] has measured some parameters that
can be attuned in order to achieve the optimum threshold

Table II. Scaling Effect on Various Parameters of CSDG MOSFET

CSDG
Parameter MOSFET Discussion
scaling
Voltage (VDD) -- This has been kept constant and specific for the particular application.
Threshold
-- This has been kept constant and specific for the technology nodes.
voltage (Vth)
The oxide thickness is scaled down by SCSDG and the channel
Oxide tox / resistance (internal and external channel) does not change, whereas the
thickness (tox) SCSDG gate capacitance is reduces with the same factor so the RC delay will still
be the same as previous.
As the number of charges / concentration is constant and device side
Doping density SCSDG2. reduces do the doping density increases, and for CSDG MOSFET S CSDG
(NA, Nd) Nd >S, So, doping density for the CSDG MOSFET is higher than the
traditional MOSFET.
Channel length L/ Due to the circular structure, the length can be reduced for the
(L) SCSDG specific drain current.
Width of channel is reduced as the drain and source are of cylindrical
Channel width W/ structure and correlate with the gate and channel forms accordingly. So,
(W) SCSDG the overall width of the channel decreases as compare to the traditional
MOSFET.
Channel Lx / As the presented device has two gates (internally and externally),
thickness (Lx) SCSDG keeping the device size (substrate) fix, so the channel thickness reduces.
Due to the cylindrical structure, it has less are in contact with the
Contact area on
-- board on which it will be placed. So less heat will produced. This reduces
board
the heat sink size.
ID = μn.Cox (W/L)[(Vgs-Vth)Vds- Vds2]
According to this equation as the drain current is dependent on the
Drain current
SCSDG.ID CoxW/L, and due to the circular structure and area these parameters overall
(ID)
increases due to increase in the oxide capacitance, so the drain current
increases in the proposed model.
Oxide area in the CSDG MOSFET increases as the oxide area
Oxide SCSDG.C
increases with (πr2) and the radius r is varies between a to b means
capacitance (Cox) ox
a<r<b
As the channel is controlled by the both side of gates so this leakage
Leakage
-- current (OFF-current) minimizes as both the gates are effectively
current
controlled the channel current.

In this design the oxide thickness tox has been application, this can be changed means external gate and
reduced. Due to this reduction, the oxide capacitance internal gates can have two different threshold voltages as
increases which increases the switch-ON current. Also, voltage duality. It can be beneficial for the application of
the reduced tox controls the Vth roll-off which reduces the two devices on the same chip. To obtain the different
subthreshold leakage in the device. The various effect of threshold voltages in fully-depleted devices, appropriate
scaling on the parameters has been discussed in the table gate work-function is recommended for both the gates (G1
II. and G2). So in a particular application, if two different
current (or any voltage / current related parameters) are
On the basis of this effects it can be worth to say that required, then using both gates of CSDG MOSFET, it can
the proposed model of CSDG MOSFET is comparable [2, be achieved.
6, 19] with the other small scale device even better.
V.EFFECTS OF CAPACITANCES
IV.VOLTAGE DUALITY
The modeling of parasitic copacitances of the CSDG
In this work there are two gates with same threshold MOSFETs is required to describe the high frequency
voltage. But for the specific requirement of the behavior of the devices. The capacitive model is shown in
2017 International Conference on Advanced Computing and Communication Systems (ICACCS -2017), Jan. 06 – 07, 2017, Coimbatore, INDIA

the fig. 2. The oxide capacitance will be Cox,CSDG = εox Also, the reduction in junction concentration and
(SCSDG/ tox). It means the oxide capacitance for the CSDG achieving dopant redistribution is an area for the future
MOSFET will increases by a factor of scaling. recommendation. The voltage duality can be achieved
easily in CSDG MOSFET, so it can be discussed in the
Due to the cylindrical structure, the drain and source future work.
can be overlapped and produces the overlap capacitance
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