UNIT III

COMPUTER FUNDAMENTALS
Functional Units of a Digital Computer: Von Neumann Architecture – Operation and
Operands of Computer Hardware Instruction – Instruction Set Architecture (ISA): Memory
Location, Address and Operation – Instruction and Instruction Sequencing – Addressing
Modes, Encoding of Machine Instruction – Interaction between Assembly and High Level
Language

FUNCTIONAL UNITS OF A DIGITAL COMPUTER

Digital Computer
A digital computer can be defined as a programmable machine which reads the binary data
passed as instructions, processes this binary data, and displays a calculated digital output.
Therefore, Digital computers are those that work on the digital data
Main functional units of a computer system
The basic functional units of computer systems are,
 Input unit
 Output unit
 Central Processing unit(CPU)
o Arithmethic and Logical Unit(ALU)
o Control unit
 Memory unit

Input Unit
 The input unit consists of input devices that are attached to the computer.
 These devices take input from the user and feed that in to the computer understands.
 Input devices are keyboard, mouse, joystick, scanner
Central Processing Unit (CPU)
 Once the information is entered into the computer by the input device, the processor
processes it.
 The CPU is the control center of the computer. It first fetches instructions from memory
and then interprets them to know what is to be done. If required, data is fetched from
memory or input device.
 CPU executes or performs the required computation and then either stores the output
or displays on the output device.
 The CPU has three main components which are responsible for different functions
1. Arithmetic Logic Unit (ALU): This unit performs mathematical calculations and
takes logical decisions. Arithmetic calculations include addition, subtraction,
multiplication and division
2. Logical decisions involve comparison of two data items to see which one is larger
or smaller or equal
Control Unit (CU)
 The Control unit coordinates and controls the data flow in and out of CPU and also
controls all the operations of ALU, memory registers and also input/output units.
 It is also responsible for carrying out all the instructions stored in the program.
 It decodes the fetched instruction, interprets it and sends control signals to
input/output devices until the required operation is done properly by ALU and
memory.
Memory registers
 A register is a temporary unit of memory in the CPU. These are used to store the data
which is directly used by the processor.
 Registers can be of different sizes(16 bit, 32 bit, 64 bit ) and each register inside the
CPU has a specific function like storing data, storing an instruction, storing address of a
location in memory etc.
 The user registers can be used by an assembly language programmer for storing
operands, intermediate results etc.
 Accumulator (ACC) is the main register in the ALU and contains one of the operands of
an operation to be performed in the ALU.
Memory
 Memory attached to the CPU is used for storage of data and instructions and is called
internal memory, it is divided into many storage locations, each of which can store data
or instructions.
 Each memory location is of the same size and has an address.
  With the address, the computer can read any memory location easily without having to
search the entire memory.
 when a program is executed, it’s data is copied to the internal memory and is stored in
the memory till the end of the execution.
 The internal memory is also called the Primary memory or Main memory.
 This memory is also called as RAM, i.e. Random Access Memory. The time of access of
data is independent of its location in memory, therefore this memory is also called
Random Access memory (RAM).
 Smallest form of memory is cache and they are inbuilt within CPU and are faster to
access
 The Secondary memory is used to store large volume of information. They are magnetic
disks, optical disks.
Output Unit
 The output unit consists of output devices that are attached with the computer. It
converts the binary data coming from CPU to human understandable form. The
common output devices are monitor, printer, plotter etc
Interconnection between Functional Components
 A computer consists of input unit that takes input, a CPU that processes the input and
an output unit that produces output. All these devices communicate with each other
through a common bus.
 A bus is a transmission path, made of a set of conducting wires over which data or
information in the form of electric signals, is passed from one component to another in
a computer. The bus can be of three types – Address bus, Data bus and Control Bus.

 The address bus carries the address location of the data or instruction.
 The data bus carries data from one component to another
 the control bus carries the control signals.
 The system bus is the common communication path that carries signals to/from CPU,
main memory and input/output devices.
 The input/output devices communicate with the system bus through the controller
circuit which helps in managing various input/output devices attached to the computer.
2 types of Computers:
1. Fixed Program Computers – Their function is very specific and they couldn’t be re-
programmed, e.g. Calculators.
2. Stored Program Computers – These can be programmed to carry out many different tasks,
In this stored-program concept, programs and data are stored in a separate storage unit
called memories. A computer built with this architecture would be much easier to reprogram.
The modern computers are based on a stored-program concept introduced by John Von
Neumann.

VON NEUMANN ARCHITECTURE

 The modern computers are based on a stored-program concept introduced by John
Von Neumann.
 This architecture consisted of a CPU, memory and I/O devices.
 The von Neumann architecture is a design model for a stored-program digital computer
that uses a processing unit and a single separate storage structure to hold both
instructions and
 The CPU fetches an instruction from the memory at a time and executes it.
 Thus, the instructions are executed sequentially which is a slow process.
 Neumann machines are called as control flow computer because instruction are
executed sequentially as controlled by a program counter.
Basic structure

It is also known as ISA (Instruction set architecture) computer and is having three basic units:
1. The Central Processing Unit (CPU)
2. The Main Memory Unit
3. The Input/Output Device
Control Unit
 A control unit (CU) handles all processor control signals. It directs all input and output
flow, fetches code for instructions, and controls how data moves around the system.
Arithmetic and Logic Unit (ALU)
 The arithmetic logic unit is that part of the CPU that handles all the calculations the CPU
may need, e.g. Addition, Subtraction, Comparisons.
 It performs Logical Operations, Bit Shifting Operations, and Arithmetic operations.
Main Memory Unit (Registers)
1. Accumulator: Stores the results of calculations made by ALU.
2. Program Counter (PC): Keeps track of the memory location of the next instructions
to be dealt with. The PC then passes this next address to Memory Address Register
(MAR).
3. Memory Address Register (MAR): It stores the memory locations of instructions that
need to be fetched from memory or stored into memory.
4. Memory Data Register (MDR): It stores instructions fetched from memory or any
data that is to be transferred to, and stored in, memory.
5. Current Instruction Register (CIR): It stores the opcode of the instructions that is
currently being executed.
6. Instruction Buffer Register (IBR): The instruction that is not to be executed
immediately is placed in the instruction buffer register IBR.
Input/Output Devices
 Program or data is read into main memory from the input device or secondary storage
under the control of CPU input instruction.
 Output devices are used to output the information from a computer. If some results
are evaluated by computer and it is stored in the computer, then with the help of
output devices, we can present them to the user.
Buses
 Data is transmitted from one part of a computer to another, connecting all major
internal components to the CPU and memory, by the means of Buses.
 Types:
o Data Bus: It carries data among the memory unit, the I/O devices, and the
processor.
o Address Bus: It carries the address of data (not the actual data) between memory
and processor.
o Control Bus: It carries control commands from the CPU (and status signals from
other devices) in order to control and coordinate all the activities within the
computer.
Von Neumann bottleneck –
 Instruction are executed only one at a time and can be carried out sequentially.
Uniprocessor :
 A type of architecture that is based on a single computing unit.
 All operations (additions, multiplications, etc ) are done sequentially on the unit.
Multiprocessor :
 A type of architecture that is based on multiple computing units.
 Some of the operations are done in parallel and the results are joined afterwards.
Flynn Taxonomy.

MIPS (Microprocessor without Interlocked Pipelined Stages

MIPS is a load/store architecture (also known as a register-register architecture); except for
the load/store instructions used to access memory, all instructions operate on the registers.
RISC VS CISC
OPERATION AND OPERANDS OF COMPUTER HARDWARE INSTRUCTION
Instruction-An instruction is a binary code which specifies the operation that has to be
executed by the computer. Each computer has its specific group of instructions called
Instruction Set.
Opcodes-specify the operation for specific instructions
address determines the registers or the areas used for that operation.
Operands are definite elements of computer instruction that show what information is to be
operated on.
Format of an Instruction
An Instruction contains two fields Operation code (Opcode) and Operands
Instructions in a computer can be of multiple lengths with a variable number of addresses.
The various address fields in the instruction format of a computer vary as per the organization
of its registers. It depends on the multiple address fields

Operation of Computer Hardware Instruction

 Instruction Set Operations
1. Data Transfer Operation
2. Arithmetic Operation
3. Logical Operation
4. I/O Transfer Operation
5. Program sequencing operation
6. Control operation
 Every computer must be able to perform arithmetic.
 The MIPS assembly language notation
Ex add a, b, c
 Instructs a computer to add the two variables b and c and to put their sum in a.
 This notation is rigid in that each MIPS arithmetic instruction performs only one
operation and must always have exactly three variables.
 The following code shows an equivalent MIPS code:
ADD $s1, $s2, $s3 the sum of b and c is placed in a.
 Here, the variables a,b and c are assumed to be stored in the register $s1, $s2 and $s3
all arithmetic immediate value are signed extended.
 MIPS Assembly Language

MIPS Operands
Operands of the Computer Hardware Instruction
 Register operand
 Memory operand
 Constant or immediate operands

Register Operand
 In MIPS instruction set architecture, operand can either in register or memory. Most of the
arithmetic and logical instructions use register operands.
 Registers are limited number of special location built directly in hardware and they are visible to
the programmer
 The size of a register in the MIPS architecture is 32 bits;
 groups of 32 bits are given the name word in the MIPS architecture.
 The number of registers is limited to 32

Design Principle 1: Simplicity favors regularity.

Example :Compiling Two C Assignment Statements into MIPS

• This segment of a C program contains the five variables a, b, c, d, and e

• The translation from C to MIPS assembly language ins tructions are performed by the compiler.
Show the MIPS code produced by a compiler.
• A MIPS instruction operates on two source operands and places the result in one destination
operand.
• Hence, the two simple statements above compile directly into these two MIPS assembly language
instructions:

Design Principle 2: Smaller is faster.

 A very large number of registers may increase the clock cycle time simply because it takes
electronic signals longer when they must travel farther.
 Use fewer register to conserve energy.

Example: Compiling a C Assignment Using Registers

 It is the compiler‘s job to associate program variables with registers. Take, for instance,
the assignment statement from our earlier example:
 The variables f, g, h, i, and j are assigned to the registers $s0, $s1, $s2, $s3, and $s4, respectively.

Answer
 The compiled program is very similar to the prior example, except we replace the variables with
the register names mentioned above plus two temporary registers, $t0 and $t1, which
correspond to the temporary variables above:
Memory Operands
 Programming languages have simple variables that contain single data elements, as in these
 examples, but they also have more complex data structures —arrays and structures.
 These complex data structures can contain many more data elements than there are registers in
a computer.The processor can keep only a small amount of data in registers, but computer
memory contains billions of data elements.
 Hence, data structures (arrays and structures) are kept in memory.
 As explained above, arithmetic operations occur only on registers in MIPS instructions; thus,
MIPS must include instructions that transfer data between memory and registers. Such
instructions are called data transfer instructions.
 To access a word in memory, the instruction must supply the memory address.
 Memory is just a large, single-dimensional array, with the address acting as the index to that
array, starting at 0. For example, in the followingFigure, the address of the third data element is
2, and the value of Memory[2] is 10
Fig: Memory addresses and contents of memory at those locations

 The data transfer instruction that copies data from memory to a register is traditionally called
load.
 The format of the load instruction is the name of the operation followed by the register to be
loaded, then a constant and register used to access memory.
 The sum of the constant portion of the instruction and the contents of the second register forms
the memory address. The actual MIPS name for this instruction is lw, standing for l oad word.

Fig: Actual MIPS memory addresses and contents of memory for those words.
Alignment restriction
 In MIPS, words must start at addresses that are multiples of 4. This requirement is called an
alignment restriction
 alignment restriction A requirement that data be aligned in memory on natural boundaries
.many architecture have alignment restriction
Big endian and little Endian
 8 bit bytes are divided into two parts:
 Address of the left most byte is called ―big endian‖ and right most byte is called ―little endian ―
Compiling an Assignment When an Operand Is in Memory
Example 1:
  Let‘s assume that A is an array of 100 words and that the compiler has associated the variables g
and h with the registers $s1 and $s2 as before.
 Let‘s also assume that the starting address, or base address, of the array is in $s3. Compile this C
assignment statement:
MIPS Code

 In the given statement, there is a single operation. Whereas, one of the operands is in memory,
so we must carry this operation in two steps:
Step 1: load the temporary register($s3) + 8
Step 2: perform addition with h(($s2)), and store result in g($s1)

 The constant in a data transfer instruction (8) is called the offset, and the register added to form
the address ($s3) is called thebase register.
Example 2:
Compiling Using Load and Store
 What is the MIPS assembly code for the C assignment statement below?

 Assume variable h is associated with register $s2 and the base address of the array A is in $s3.
MIPS code

 The final instruction stores the sum into A[12], using 48 (4 × 12) as the offset and register $s3
as the base register

 Load word and store word are the instructions that copy words between memory and registers
in the MIPS architecture. Other brands of computers use other instructions along with load and
store to transfer data.
Constant or Immediate Operands
 Constant variables are used as one of the operand for many arithmetic operation in MIPS
architecture
 The constants would have been placed in memory whenthe program was loaded.
 To avoid load instruction used in arithmetic instruction we can use one operand a constant
 This quick add instruction with one constant operand is called add immediate or addi. To add 4
to register $s3, we just write
Design Principle 3: Make the common case fast.

Advantage of constant operands

 It uses less energy
 It performs operation in more fast
Index register
 The register in the data transfer instructions was originally invented to hold an index of an
array with the offset used for the starting address of an array. Thus, the base register is also
called the index register.
INSTRUCTION SET ARCHITECTURE (ISA)
 An ISA is defined as the design of a computer from the Programmer’s Perspective. An ISA describes
the design of a Computer in terms of the basic operations it must support. The ISA is not concerned
with the implementation-specific details of a computer. It is only concerned with the set or collection
of basic operations the computer must support.
 For example, the AMD Athlon and the Core 2 Duo processors have entirely different implementations
but they support more or less the same set of basic operations as defined in the x86 Instruction Set. .
MIPS is one of the most widely used ISAs in education due to its simplicity.
 ISA includes an Instruction set, rules for using instructions, mnemonics functionality, addressing
modes and instruction encoding
 The addressing modes that are commonly used for accessing operands in memory locations and
processor registers
 A sufficient number of instructions and addressing methods are introduced to enable us to present
complete, realistic programs for simple tasks.
 These generic programs are specified at the assembly-language level, where machine instructions
and operand addressing information are represented by symbolic names.
 A complete instruction set, including operand addressing methods, is often referred to as the
instruction set architecture (ISA) of a processor.
 The vast majority of programs are written in high-level languages such as C, C++, or Java.
 To execute a high-level language program on a processor, the program must be translated into the
machine language for that processor, which is done by a compiler program.
 Assembly language is a readable symbolic representation of machine language.
 An ISA must have sufficient number of registers and compilers must use registers efficiently
 MIPS ISA
• RISC architecture
• ISA has small set of instructions and addressing modes designed to use with high-level
programming language
• It supports parallel execution
• Large register set with minimizing main memory access
• Fixed instruction width 32 bits
• Three instruction encoding types R-type, I-type and J-type
 ISA defines
• Types of instructions
• Length of instruction
• Instruction fomat
3.1 Memory Locations and Addresses
• The memory consists of many millions of storage cells, each of which can store a bit of
information having the value 0 or 1.
• Because a single bit represents a very small amount of information, bits are seldom handled
individually.
• The usual approach is to deal with them in groups of fixed size. For this purpose, the memory is
organized so that a group of n bits can be stored or retrieved in a single, basic operation.
• Each group of n bits is referred to as a word of information, and n is called the word length. The
memory of a computer can be schematically represented as a collection of words, Modern
computers have word lengths that typically range from 16 to 64 bits.
• The memory is an array of M number of n-bit words. Each word of memory has an unique
address. The address is used to identify a particular word in the memory. If the processor has 16
memory capacity it can address upto 216 address lines
 •
• If the word length of a computer is 32 bits, a single word can store a 32-bit number
• A unit of 8 bits is called a byte. Machine instructions may require one or more words for their
representation.
• Accessing the memory to store or retrieve a single item of information, either a word or a byte,
requires distinct names or addresses for each location.
• It is customary to use numbers from 0 to 2k − 1, for some suitable value of k, as the addresses of
successive locations in the memory.
• Thus, the memory can have up to 2k addressable locations. The 2k addresses constitute the
address space of the computer. For example, a 24-bit address generates an address space of 224
(16,777,216) locations.
• This number is usually written as 16M (16 mega), where 1M is the number 220 (1,048,576). A
32-bit address creates an address space of 232 or 4G (4 giga) locations, where 1G is 230.

Fig 3.1 Memory words

Figure 3.2 Examples of encoded information in a 32-bit word

3.1.1 Byte Addressability
• A byte is always 8 bits, but the word length typically ranges from 16 to 64 bits. It is imprac tical to
assign distinct addresses to individual bit locations in the memory.
• The most practical assignment is to have successive addresses refer to successive byte locations
in the memory. This is the assignment used in most modern computers. The term byte-
addressable memory is used for this assignment. Byte locations have addresses 0, 1, 2,....
• Thus, if the word length of the machine is 32 bits, successive words are located at addresses 0,
4, 8, , with each word consisting of four bytes.
3.1.2 Big-Endian and Little-Endian Assignments
 The name big-endian is used when lower byte addresses are used for the more significant bytes
(the leftmost bytes) of the word.
 The name little-endian is used for the opposite ordering, where the lower byte addresses are
used for the less significant bytes (the rightmost bytes) of the word.
 The words ―more significant‖ and ―less significant‖ are used in relation to the weights (powers of
2) assigned to bits when the word represents a number.
 Both little-endian and big-endian assignments are used in commercial machines. In both cases,
byte addresses 0, 4, 8,..., are taken as the addresses of successive words in the memory of a
computer with a 32-bit word length.
 These are the addresses used when accessing the memory to store or retrieve a word.

3.1.3 Word Alignment

 Common Processor word length being 8,16,32 and 64 bits
 In the case of a 32-bit word length, natural word boundaries occur at addresses 0, 4, 8,..., as
shown in Figure 2.3. We say that the word locations have aligned addresses if they begin at a
byte address that is a multiple of the number of bytes in a word.
 For practical reasons associated with manipulating binary-coded addresses, the number of bytes
in a word is a power of 2. Hence, if the word length is 16 (2 bytes), aligned words begin at byte
addresses 0, 2, 4,..., foe a word length 0f 32(4 bytes) allignes words begin at byte address
0.4,8,12---- for a word length of 64 (23 bytes), aligned words begin at byte addresses 0, 8, 16,....
 If the words begin at an arbitrary byte address. then words are said to have unaligned
addresses.
 But, the most common case is to use aligned addresses, which makes accessing of memory
operands more efficient.
 3.1.4 Accessing Numbers and Character strings
• A number usually occupies one word, and can be accessed in the memory by specifying its word
address.
• characters can be stored in the memory as bytes and accessed by their byte address.

3.2 Memory Operations

• Both program instructions and data operands are stored in the memory. To execute an
instruction, the processor has to fetch instruction and read operand from memory .
• After execution processor store the result and modified operands if any in the memory. Thus,
two basic operations involving the memory are needed, namely, Read and Write.
• Load( Read operation)
• The Read operation transfers a copy of the contents of a specific memory location to the
processor. The memory contents remain unchanged.
• To start a Read operation, the processor sends the address of the desired location to the
memory and requests that its contents be read. The memory reads the data stored at that
address and sends them to the processor.
• Store(Write operation)
• The Write operation transfers an item of information from the processor to a specific memory
location, overwriting the former contents of that location.
• To initiate a Write operation, the processor sends the address of the desired location to the
memory, together with the data to be written into that location.
• The memory then uses the address and data to perform the write.

INSTRUCTION AND INSTRUCTION SEQUENCING.

 The tasks carried out by a computer program consist of a sequence of small steps, such as
adding two numbers, testing for a particular condition, reading a character from the keyboard,
or sending a character to be displayed on a display screen.
 A computer must have instructions capable of performing 4 types of operations:
1. Data transfers between the memory and the registers (MOV,PUSH,POP, XCHG).
2. Arithmetic and logic operations on data (ADD, SUB, MUL, DIV, AND, OR, NOT).
3. Program sequencing and control(CALL.RET,LOOP, INT).
4. I/0 transfers (IN, OUT).

REGISTER TRANSFER NOTATION (RTN)

• Here the transfer of information from one location in a computer to another.
• Possible locations that may be involved in such transfers are memory locations, processor
registers, or registers in the I/O subsystem.
• Most of the time, we identify such locations symbolically with convenient names.
• The possible locations in which transfer of information occurs are:
1) Memory-location
2) Processor register &
3) Registers in I/O device.
ASSEMBLY LANGUAGE NOTATION
• To represent machine instructions and programs, assembly language format is used.

BASIC INSTRUCTION TYPES

INSTRUCTION EXECUTION & STRAIGHT LINE SEQUENCING

• An instruction consists of operation and operands. To perform an specific task, A programmer must
select, write appropriate instructions one after another in proper sequence, and this is called as
instruction sequencing and sequence of instructions is called a program
• A program is executed as follows:
1) Initially, the address of the first instruction is loaded into PC.
2) Then, the processor control circuits use the information in the PC to fetch and execute instructions,
one at a time, in the order of increasing addresses. This is called Straight-Line sequencing.
3) During the execution of each instruction, PC is incremented by the length of the current instruction in
execution
• There are 2 phases for Instruction Execution:
1) Fetch Phase: The instruction is fetched from the memory-location and placed in the IR.
2) Execute Phase: The contents of IR is examined to determine which operation is to be
performed. The specified-operation is then performed by the processor.
 [B]
Program Explanation
• Consider the program for adding a list of n numbers
• The Address of the memory-locations containing the n numbers are symbolically given as NUM1,
NUM2…..NUMn.
• Separate Add instruction is used to add each number to the contents of register R0.
• After all the numbers have been added, the result is placed in memory-location SUM.

•
ADDRESSING MODES
 The different ways in which the location of an operand is specified in instructions are referred to
as addressing modes.
 Different types of addresses involve tradeoffs between instruction length, addressing
flexibility and complexity of address calculation.
 The different types of addressing modes are:
1. Immediate addressing mode
2. Direct or absolute addressing mode
3. Indirect addressing mode
4. Register addressing mode
5. Indexed addressing mode(Displacement)
6. Relative addressing mode
7. Auto increment
8. Auto decrement
9. Implied (Stack, and a few others)
1. Immediate Addressing and Small Operands
 The operand is given explicitly in the instruction.
Example: MOVE #200, R0
 The above statement places the value 200 in the register R0. A common convention is to use the
sharp sign (#) in front of the value to indicate that this value is to be used as an immediate
operand.
2. Direct Addressing (Absolute addressing mode)
 The operand is in a memory location; the address of this location is given explicitly in the
instruction. (In some assembly languages, this mode is called Direct Mode.
Example: MOVE LOC, R2
 This instruction copies the contents of memory location of LOC to register R2.
 Address field contains address of operand.
 Look in memory at address for operand.
 Single memory reference to access data.

3. Memory-Indirect Addressing
 The effective address of the operand is the contents of a register or memory location whose
address appears in the instruction.
Ex 1 Add (R2),R0 here Register R2 is used as a pointer to the address of the operand .
Ex 2 MOV [A], R0
  The initialization section of the program loads the counter value n from memory location N into
Rl and uses the immediate addressing mode to place the address value NUM 1, which is the
address of the first number in the list, into R2.

4. Register Direct Addressing

a.
b. The operand is the contents of a processor register; the name (address) of the register is
given in the instruction.
Example: MOV R1,R2
c. This instruction copies the contents of register R2 to R1.
d. Operand(s) is(are) registers EA = R.
e. There are a limited number of registers.
f. Therefore a very small address field is needed.
g. Shorter instructions are used.
h. Instruction fetch is faster when compared to other.

5. Register Indirect Addressing

a. Similar to memory-indirect addressing; much more common, EA = (R).
b. Operand is in memory cell pointed to by contents of register R.
c. Large address space (2n).
d. One fewer memory access than indirect Addressing.

Register Indirect Addressing

6.Displacement Addressing(Index addressing mode)
e. The effective address of the operand is generated by adding a constant value to the contents
of
a register. The register used may be either a special register provided for this purpose, or, more
commonly; it may be anyone of a set of general-purpose registers in the processor.
f. In either case, it is referred to as an index register. We indicate the index mode symbolically
as X(Ri).
g. Where X denotes the constant value contained in the instruction and Ri is the name of the
register involved. The effective address of the operand is given by EA = X + [Ri].
h. The contents of the index registers are not changed in the process of generating
the effectiveaddress.
i. EA = A + (R)
ii. Combines register indirect addressing with direct addressing
iii. Address field hold two values
iv. A = base value
v. R = register that holds displacement
vi. or vice versa

Types of Displacement Addressing

i. Relative Addressing
j. Base-register addressing
k. Indexing
7.Relative Addressing
l. We have defined the Index mode using general-purpose processor registers. A useful version
of this mode is obtained if the program counter, PC, is used instead of a general purpose
register.
m. Then, X(PC) can be used to address a memory location that is X bytes away from the
location presently pointed to by the program counter.
n. Since the addressed location is identified ''relative'' to the program counter, which always
identifies the current execution point in a program, the name Relative mode is associated
with this type of addressing.
o. EA = X + (PC)
8.Base-Register Addressing
p. A holds displacement.
q. R holds pointer to base address.
r. R may be explicit or implicit.
s. e.g. segment registers in 80x86 are base registers and are involved in all EA computations.
t. x86 processors have a wide variety of base addressing formats.
9. Auto- increment mode
u. The effective address of the operand is the contents of a register specified in the instruction.
After accessing the operand, the contents of this registers are automatically incremented to
point to the next item in a list.
 v. We denote the Auto increment mode by putting the specified register in parentheses, to
show that the contents of the registers are used as the effective address, followed by a plus
sign to indicate that these contents are to be incremented after the operand is accessed.
w. Thus, the Auto increment mode is written as,
(Ri) +
x. As a companion for the Autoincrement mode, another useful mode accesses the items of a
list in the reverse order:
10.Auto- decrement mode
y. The contents of a register specified in the instructions are first automatically decremented
and is then used as the effective address of the operand.
z. We denote the Autodecrement mode by putting the specified register in parentheses,
preceded by a minus sign to indicate that the contents of the registers are to be
decremented before being used as the effective address. Thus, we write

- (Ri)
11.Stack Addressing
• A stack ia linear array of reserved memory locations,It is associated with a pointer called Stack
Pointer(SP)
• In this mode, the SP always contains the address of TOP of stack, where the operand is to be
stored or located.
• This is a special case of register indirect addressing where referenced registeri is a stack pointer
• Operand is (implicitly) on top of stack.
e.g. PUSH, POP
• PUSH R – This instruction decrements SP and copies the cntents register R on to the top of stack
pointer by SP

Ex Consider the computer with three instruction classes and CPI measurements as given below
and instruction counts for each instruction class for the same program from two different
compilers are given. Assume that the computer’s clock rate is 4 GHZ. Which code sequence
will execute faster according to execution time? (6) (NOV/DEC2014)
Code from CPI for the instruction class A
B C
 CPI 1 2 3
Code from Instruction count for each class

A B C
Compiler 1 2 1 2
Compiler 2 4 1 1
ANSWER
aa. Sequence 1 executes 2 + 1 + 2 = 5 instructions. Sequence 2 executes 4 + 1 + 1 = 6
instructions. Therefore, sequence 1 executes fewer instructions. We can use the equation
for CPU clock cycles based on instruction count and CPI to find the total number of clock
cycles for each sequence:

bb. This yields,

cc. CPU clock cycles1 = (2 × 1) + (1 × 2) + (2 × 3) = 2 + 2 + 6 = 10 cycles
dd. CPU clock cycles2 = (4 × 1) + (1 × 2) + (1 × 3) = 4 + 2 + 3 = 9 cycles
ee. So code sequence 2 is faster, even though it executes one extra instruction. Since code
sequence 2 takes fewer overall clock cycles but has more instructions, it must have a lower
CPI. The CPI values can be computed by,

ENCODING OF MACHINE INSTRUCTION

• We have introduced a variety of useful instructions and addressing modes. These instructions
specify the actions that must be performed by the proces sor circuitry to carry out the desired
tasks.
• We have often referred to them as machine instructions. Actually, the form in which we have
presented the instructions is indicative of the form used in assembly lang uages, except that we
tried to avoid using acronyms for the various operations, which are awkward to memorize and
are likely to be specific to a particular commercial processor.
• To be executed in a processor, an instruction must be encoded in a compact binary pattern.
Such encoded instructions are properly referred to as machine instructions.
• The instructions that use symbolic names and acronyms are called assembly language
instructions, which are converted into the machine instructions using the assembler program.
• We have seen instructions that perform operations such as add, subtract, move, shift, rotate,
and branch. These instructions may use operands of different sizes, such as 32-bit and 8-bit
numbers or 8-bit ASCII-encoded characters.
• The type of operation that is to be performed and the type of operands used may be specified
 using an encoded binary pattern referred to as the OP code for the given instruction.
• Suppose that 8 bits are allocated for this purpose, giving 256 possibilities for specifying different
instructions. This leaves 24 bits to specify the rest of the required information.
• The instruction Add R1, R2 has to specify the registers R1 and R2, in addition to the OP code.
If the processor has 16 registers, then four bits are needed to identify each register. Additional
bits are needed to indicate that the Register addressing mode is used for each operand.
• The instruction Move 24(R0), R5 requires 16 bits to denote the OP code and the two registers,
and some bits to express that the source operand uses the Index addressing mode and that the
index value is 24.
• The shift instruction LShiftR #2, R0
• And the move instruction Move #$3A, R1 have to indicate the immediate values 2 and #$3A,
respectively, in addition to the 18 bits used to specify the OP code, the addressing modes, and
the register.
• This limits the size of the immediate operand to what is expressible in 14 bits
• Consider next the branch instruction Branch >0 LOOP
• Again, 8 bits are used for the OP code, leaving 24 bits to specify the branch offset.
• Since the offset is a 2‘s-complement number, the branch target address must be within 223
bytes of the location of the branch instruction.
• To branch to an instruction outside this range, a different addressing mode has to be used, such
as Absolute or Register Indirect. Branch instructions that use these modes are usually called
Jump instructions.
• In all these examples, the instructions can be encoded in a 32-bit word. Depicts a possible format.
• There is an 8-bit Op-code field and two 7-bit fields for specifying the source and destination
operands. The 7-bit field identifies the addressing mode and the register involved (if any).
• The ―Other info‖ field allows us to specify the additional information that may be needed, such as
an index value or an immediate operand.
• But, what happens if we want to specify a memory operand using the Absolute addressing mode?
• The instruction Move R2, LOC

• Requires 18 bits to denote the OP code, the addressing modes, and the register.
• This leaves 14 bits to express the address that corresponds to LOC, which is clearly insufficient.
And #$FF000000. R2
• In which case the second word gives a full 32-bit immediate operand. If we want to allow an
instruction in which two operands can be specified using the Absolute addressing mode, for
example
o Move LOC1, LOC2
• Then it becomes necessary to use an additional words for the 32-bit addresses of the operands. This
 approach results in instructions of variable length, dependent on the number of operands and the
type of addressing modes used.
• Using multiple words, we can implement quite complex instructions, closely resembling operations
in high-level programming languages.
• The term complex instruction set computer (CISC) has been used to refer to processors that use
instruction sets of this type.
• The restriction that an instruction must occupy only one word has led to a style of computers that
have become known as reduced instruction set computer (RISC).
• The RISC approach introduced other restrictions, such as that all manipulation of data must be done
on operands that are already in processor registers.
• This restriction means that the above addition would need a two-instruction sequence
Move (R3), R1 Add R1, R2
• If the Add instruction only has to specify the two registers, it will need just a portion of a 32-bit
word. So, we may provide a more powerful instruction that uses three operands
o Add R1, R2, R3
• Which performs the operation R3 -> [R1] + [R2]
• A possible format for such an instruction in shown in fig c. Of course, the processor has to be able
to deal with such three-operand instructions.
• In an instruction set where all arithmetic and logical operations use only register operands, the only
memory references are made to load/store the operands into/from the processor registers.
• RISC-type instruction sets typically have fewer and less complex instructions than CISC -type sets.

INTERACTION BETWEEN ASSEMBLY AND HIGH LEVEL LANGUAGE

• Three Language Levels that can be used to write a program
• Machine Level Language
• Assembly Level Language
• High Level Language
• Machine Level Programs:
• A program which has simply a sequence of the binary codes for the instructions is called
machine level language program.
• This binary form of the program is referred to as machine language because it is the form
required by the machine.
• However to write a program in machine language, programmer has to memorize the
thousands of binary instruction codes for a processor.
• This task is difficult and error prone

• Assembly level languages:

• It is easier to write program in assembly language b programmers than in machine
language
• Single line of command is the instruction which defines the operation carried out by the
instruction with the operands
• High Level Languages:
• High level languages are called “high-level‘ because they are closer to human languages
• There is no one-to-one relationship between the instructions in a high level language and
machine language as there is with assembly language.
• Examples of a high level language. Basic, C, Fortran, Python, Ada etc.
• Advantages of assembly language over a high level language.
• It requires less memory and execution time.
 • It allows hardware-specific complex jobs in an easier way.
• It is suitable for time-critical jobs.
• It is most suitable for writing interrupt service routines and other memory resident programs.
• Advantages of using a high level language over assembly language.
• Faster program development – it is less time consuming to write and then test the program.
• It is not necessary to remember the registers of the CPU and mnemonic instructions.
• Portability of a program from one machine to other.
• Each assembly language is specific to a particular type of CPU, but most high-level
programming languages are generally portable across multiple architectures.
• Compiler
• A compiler reads the whole high level code and translates it into a complete machine code
program which is output as a new file and can be saved.
• The biggest advantage of this is that the translation is done once only and as a separate
process. The program that is run is already translated into machine code so is much faster in
execution.
• The disadvantage is that you cannot change the program without going back to the original
source code, editing that and recompiling.
• Interpreter
• An interpreter reads the source code one instruction or line at a time, converts this line into
machine code and executes it.
• The machine code is then discarded and the next line is read. The advantage of this is it‘s
simple and you can interrupt it while it is running, change the program and either continue or
start again.
• The disadvantage is that every line has to be translated every time it is executed, even if it is
executed many times as the program runs. And because of this interpreters tend to be slow.
• Assembler
• An assembler reads the code written in assembly language format and converts it into the
machine level code

Difference between assembly language and high level language

 TWO MARKS

1. What is cache memory?

The small and fast RAM units are called as caches.
When the execution of an instruction calls for data located in the main memory, the data are
fetched and a copy is placed in the cache. Later if the same data are required it reads directly
from the cache.
2 What is the function of ALU?
 Most of the computer operations (arithmetic & logic) are performed in ALU. The data required
for the operation is brought by the processor and the operation is performed by the ALU.
4. What is the function of control unit?
 The Control unit is the main part of the computer that coordinates the entire computer
operations. Data transfers between the processor and memory controlled by the control unit
through timing signal.
5. What are basic operations of a computer memory?
 The basic operations of the memory are READ and WRITE.
 READ – read the data from input device to memory.
 WRITE – writes data to the output device.
6. List out the operations of the computer.
 The computer accepts the information in the form of programs and data through an input unit and
stores it in the memory.
1. Information stored in the memory is fetched under program control into an arithmetic and logic
unit where it is processed.
2. Processed information leaves the computer through an output unit.
3. All activities inside the machines are directed by the control unit.
7. What are the main elements of a computer?
 Processor: To interpret and execute programs.
 Memory: For storing programs and data.
 Input-output equipment: Fortransferring information between the computer and outside world.
8. Define Computer design.
 It is concerned with the hardware design of the computer. Once the computer specifications are
formulated, it is the task of the designer to develop hardware for the system.
 Computer design is concerned with the determination of what hardware should be used and
how the parts should be connected. This aspect of computer hardware is sometimes referred to
as computer implementation.
9. What is instruction set architecture?
 An abstract interface between the hardware and the lowest level software that encompasses all
the information necessary to write a machine language program that will run correctly.
 Including instructions, registers, memory access, I/O and so on.
10. State Amdahl’s law. Nov / Dec 2014
 Amdahl‘s Law is used to find the execution time of a program after making the improvement. It
can be represented in an equation as follows:
 Hence, Amdahl‘s Law can be used to estimate performance improvements.

11. Define Stored Programmed Concept.

 Storing program and their data in the same high-speed memory.
 It enables a program to modify its own instructions (such self-modifying Programs have
undesirable aspects, however and are rarely used).
12. What are the registers generally contained in the processor?(Nov/Dec-2019)
 MAR – Memory Address Register.
 MDR – Memory Data Register.
 IR – Instruction Register.
 R0 – Rn – General purpose Register.
 PC – Program Counter.
13. What do you mean by Memory address register (MAR) and Memory dataregister (MDR)?
 The MAR holds the address of the location to be accessed.
 The MDR contains the data to be written into or read out of the addressed location.
14. What is Data path?
 The component of the processor that performs arithmetic operations is called data path.
15. What is elapsed time of computer system?
 The total time to execute the total program is called elapsed time.
 It is affected by the speed of the processor, the disk and the printer.
16. What is processor time of a program?
 The period during which the processor is active is called processor time of a program.
 It depends on the hardware involved in the execution of individual machine instructions.
 17. Define clock rate.
 The clock rate is given by,
R=1/P,
 Where P is the length of one clock. It can be measure as cycles per second (Hertz).
18. What is meant by clock cycle?
 Processor circuit is controlled by a timing signal called a clock.
 The clock defines regular time intervals, called clock cycle.
 To execute the machine instruction the processor divides the action to be performed into
sequence of basic steps. Each step can be completed in one clock cycle.
19. Write down the basic performance equation. (Apr/May-2014)(Nov/Dec 2019)
T=N*S/R
Where
T-Processor time
N-Number of machine instructions
S-Number of basic steps needed to execute one machine
instruction R-Clock rate
20. What is meant by addressing mode? List its types. (May/June 2013) Nov/ Dec 2013
The addressing mode is defined as the different ways in which the location or of an operand is
specified in an instruction.
The different types of addressing modes are:
1. Immediate addressing mode
2. Register addressing mode
3. Direct or absolute addressing mode
4. Indirect addressing mode
5. Indexed addressing mode
6. Relative addressing mode
7. Auto increment
8. Auto decrement

21. Define Register addressing mode with an example.

 In register addressing mode, the operand is the content of a processor register. The name
(address) of the register is given in the instruction.
Effective address (EA) = Ri, Where Ri is a processor register.
22. Define absolute addressing mode with an example.
 In absolute addressing mode, the operand is in a memory location. The addresses of this
location are given explicitly in the instruction. This is also called as direct addressing mode.
EA = Loc Where loc is the memory address.
23. What is relative addressing mode with an example? (N/D 2014)
 The Effective address is determined by the index mode using the program counter in place of
general purpose register. This mode is used to access the data operands.
EA = X + [PC]
24. What is indirect addressing mode?
 The Effective address of the operand is the contents of a register or memory location whose
address appears in the instruction.
EA = [Ri] or EA = [Loc]
25. What is indexed addressing mode?
 The Effective address of the operand is generated by adding a constant value to the contents of
a register.
EA = X + [Ri].
 26. Define auto increment mode of addressing.
The Effective address of the operand is the contents of a register specified in the instruction. After
accessing the operand, the contents of this registers are automatically incremented to point to the next
item in the list.
EA = (Ri) +
27. Define auto decrement mode of addressing.
The contents of a register specified in the instructions are first automatically decremented and are then
used as the effective address of the operand.
EA = - (Ri)
28. List the basic instruction types. May / June 2013
The various instruction types are,
 Three address instructions
 Two-address instructions
 Single-address instructions
 Zero-address instructions
29. What is register?
 A small set of high-speed storage devices called registers, which serve as implicit storage
locations for operands and results.
30. List the phases, which are included in the each instruction cycle?
 Fetch:Fetches instruction from main memory (M).
 Decode: Decodes the instruction‘s opcode.
 Load: Loads (read) from M any operands needed unless they are already in CPU Registers.
 Execute: Executes the instruction via a register-to-register operation using an appropriate
functional unit of the CPU such as a fixed–point adder.
 Store: Stores (write) the results in M unless they are to be retained in CPU register.
31. What are the types of computer?
 Mini computer
 Micro computers
 Mainframe computers
 Super computers
32. What are the two major steps in processing an instruction? (Or) Write the two steps that are
common to implement any type of instruction. Nov. / Dec. 2018
 Fetch step: During this step a new instruction is read from the external memory M by the CPU.
 Execute step: During this step operations specified by the instructions are executed
by the CPU.
33. What are the speedup techniques available to increase the performance of a computer?
 Cache: It is a fast accessible memory often placed on the same chip as the CPU. It is used to
reduce the average time required to access an instruction or data to a single clock cycle.
 Pipelining: Allows the processing of several instructions to be partially overlapped.
 Super scalar: Allows processing of several instructions in parallel (full overlapping).
34. What are Timing signals?
 Timing signals are signals that determine when a given action is to take place.
 Data transfers between the processor and the memory are also controlled by the control unit
through timing signals.
35. Distinguish between auto increment and auto decrement addressing mode. (May/June 2016)

Auto Auto decrement

increment
1.The effective address of the operand is the 1.The contents of a register specified in the
contents of the register specified in the instruction are decremented and then are
instruction. After accessing the operand, the used as effective address to access a memory
contents of the register are incremented to location.
address the next location.

2.Auto increment is symbolically represented as 2.Auto decrement mode is symbolically

(Ri)+.Example:move(R2), R0+ represented as -(Ri).Example: Move R1, -(R0)
36. What is an opcode? How many bits are needed to specify 32 distinct operations? (Apr/May
2011)
 An opcode is the first byte of an instruction in machine language which tells the hardware what
operation needs to be performed with this instruction.
 Every processor/controller has its own set of opcodes defined in its architecture. Opcode is the
operation to be performed on data. An opcode is followed by data like address, values etc if
needed.
 5 bits are needed to specify 32 distinct operations.
37. Define word length. (Nov/Dec 2011)
 In computer architecture, a word is a unit of data of a defined bit length that can be addressed
and moved between storage and the computer processor.
 Address that is divided by 4 is called word.
 The number of bits in the word is called word length.
 In longer architected word length,the computer processor can do more in a single operation.
38. What are the merits and demerits of single address instructions? (Nov/Dec 2011)
Single address instruction,
Eg: Add A
Store A
Add the contents of memory location A to the contents of the accumulator register and place the sum
back into accumulator.
39. Explain the disadvantages of using a single type of instruction.
In practice the codes in an instruction (opcode and condition) may be fairly small e.g. 2. to .8
bits. However, if the instruction is to be able to reference large quantities of data then the addresses
must be large e.g. 16..32 bits. If the above instruction were to use 6 bits for the opcode, 4 bits for the
condition code and 16 bits for each address then it would have to be 90 bits long.
40. What is relative addressing mode? When is it used? (May/June 2012)
 The effective address is determined by the index mode using program counter in place of the
general purpose registers.
 This address is commonly used to specify the target address in branch instruction.
 Example: JNZ BACK
o This instruction causes program executive to go to the branch target location identified
by the name BACK, if the branch condition is satisfied.
41. Suppose you wish to run a program P with 8.5 * 109 instructions on a 5 Ghz machine with CPI
of 0.8. What is the expected CPU time? (Nov/Dec 2010)
Percentage of elapsed time=(User CPU Time + System CPU Time)/Elapsed Time
Expected CPU time =0.8-0.2*8.5*109=1.36
42. What does the term hertz refer to? (Nov/Dec 2010)
 The hertz abbreviated as Hz.
 It is a unit of frequency.
 It is equal to 1 cycle per second.
 43. Mention the registers used for communications between processor and main memory.
(May/June 2010)
1) MAR( Memory Address Register): The Memory Address Register (MAR) is a CPU register that
either stores the memory address from which data will be fetched to the CPU or the address to
which data will be sent and stored.
2) MDR (Memory Data Register):It is the register of a computer's control unit that contains the
data to be stored in the computer storage (e.g. RAM), or the data after a fetch from the
computer storage. It acts like a buffer and holds anything that is copied from the memory ready
for the processor to use it.
44. What is SPEC? Specify the formula for SPEC rating. (May/June 2012)(Apr/May 2014)
 SPEC is a nonprofit consortium of 22 major computer vendors whose common goals are ―to
provide the industry with a realistic yardstick to measure the performance of advanced
computer systems‖ and to educate consumers about the performance of vendors‘ products.
 SPEC creates, maintains, distributes, and endorses a standardized set of application-oriented
programs to be used as benchmarks.
The formula for SPEC rating is as follows:
SPEC rating (ratio) = TR / TC;
where,
TR = Running time of the Reference Computer;
TC = Running time of the Computer under test;
If the SPEC rating = 50 means that the computer under test is 50 times as fast as the ultra sparc 10. This
is repeated for all the programs in the SPEC suit, and the geometric mean of the result is computed.
45. Give an example each of zero-address, one-address, two-address and three-address
instructions. (Or) Classify the instructions based on the operations they perform and give one
example to each category. Apr. / May 2018, Nov. / Dec. 2018
 Zero address- push (Push the value as top of stock)
 One address- INC CL (If carry set, increment CL by one)
 Two address- Add A,B (A→ A+B)
 Three address- Add A,B,C (A→ B+C)
46. Which data structures can be best supported using (a) indirect addressing mode (b) indexed
addressing mode?
(a) Indirect addressing mode – Pointer data structure
(b) Indexed addressing mode- Array data structure
47. What are the four basic types of operations that need to be supported by an instructor set?
(i) Data transfer between memory and the processor register.
(ii) Arithmetic and logic operations on Data.
(iii) Program sequencing and control.
(iv) I/O transfer.
48. What are the address-sequencing capabilities required in a control memory?
(i) Incrementing of the control address register.
(ii) Unconditional branch as specified by address field of the micro
instruction. (iii)Conditional branch depending on status bits in registers of
computer.
(iv)A facility for sub-routines calls and returns.
49. What are the limitations of assembly language? (M/J 2007)
(i) Assembly language is converted to Machine language using assembler which is time consuming
when compared with machine language.
(ii) It is difficult to solve the complex problems.
(iii) A set of symbolic names (mnemonics) and rules has to be followed.
 50. A memory byte location contains the pattern 00101100. What does this pattern rep resent
when interpreted as a number? What does it represent as an ASCII Code? (Nov/Dec 2007)
 Interpreted number is 44.
 ASCII code is NULL/idle.
51. What is the information conveyed by addressing modes? (Nov/Dec 2007)
 The information conveyed by addressing mode is to specify the location of an operand in an
instruction.
52. Why is the data bus in most microprocessors bi-directional while the address bus is
unidirectional? (Apr/May 2008)
 The data bus is bi-directional bus and is used to fetch instruction from memory and to send a
command to an I/O device or port. Address is unidirectional to carry memory address while
reading from or writing into memory.
53. What is meant by the stored program concept? Discuss. (May/June 2007)
 A set of instruction that performs a task is called a program. Usually the program is stored in the
memory. The processor fetches the instructions that take up the program from the memory,
one at a time and perform the desired operation.
54. What are the two techniques used to increase the clock rate R?
The two techniques used to increase the clock rate R are:
 The Integrated Circuit (IC) technology can be increased which reduces the time needed to
complete a basic step.
 We can reduce the amount of processing done in one basic step.
55. What is Big-Endian and Little-Endian representations? (Nov/Dec 2014)
 The big-endian is used when lower byte addresses are used for the more significant bytes(The
leftmost bytes) of the word.
 The little-endian is used for the opposite ordering, where the lower byte addresses are used for
the less significant bytes (the rightmost bytes) of the word.
56. What is meant by instructions? (May/June 2016)
 Instructions are command that is governed by the transfer of information within the computer
as well as between the computers and its input and output device.
57. What is the use of Instruction register?
 It holds the instructions that are currently being executed.
58. What is the use of MAR?
 It holds the address of the location to be accessed.
59. What is the use of MDR?
 It holds the data to be written into or read out of the addressed location.
60. State the basic performance equation of a computer. (Apr/May 2014)
T= (NxS)/R
Where,
N- Number of instructions
S- Average numbers of steps needed to execute one
instruction. R- Clock rate.
61. What are the two basic operations involving in the memory?
1. Load (Read or fetch)
2. Store (Write)
62. How to measure the performance of the system?
1. Response time
2. Throughput.
63. What is register indirect addressing mode? When is it used? (Nov/Dec 2013)
The effective address of the operand is the contents of a register or memorylocation whose address
appears in the instruction. Example Add (R2),R0
Register R2 is used as a pointer to the numbers in the list, and the operands are accessed indirectly
through R2. The initialization section of the program loads the counter value n from memory location N
into Rl and uses the Immediate addressing mode to place the address value NUM 1, which is the
address of the first number in the list, into R2.
64. List the eight great ideas invented by computer architects. (Nov/Dec-2015)
 Design for Moore‘s Law
 Use abstraction to simplify design
 Make the common case fast
 Performance viaparallelism
 Performance viapipelining
 Performance viaprediction
 Hierarchy of memories
 Dependabilityvia redundancy
65. Distinguish pipelining from parallelism. (N/D2015)
 Parallelism means we are using more hardware for the executing the desired task. In parallel
computing more than one processor are running in parallel. There may be some dedicated
hardware running in parallel for doing the specific task.
 Parallelism increases the performance but the area also increases.
 The pipelining is an implementation technique in which multiple instructions are overlapped
in execution.
 In case of pipelining the performance and throughput increases at the cost of pipelining
registers area.
 In pipelining there are different hazards like data hazards, control hazards etc.

66. Give the formula for CPU execution time for a program.(Nov/Dec 2016)
 A simple formula relates the most basic metrics (clock cycles and clock cycle time) to CPU time:

 Alternatively, because clock rate and clock cycle time are inverses,

 This formula makes it clear that the hardware designer can improve performance by reducing
the number of clock cycles required for a program or the length of the clock cycle.
67. What is an instruction register? (Nov/Dec 2016)
In computing, an instruction register (IR) is the part of a CPU's control unit that holds the instruction
currently being executed or decoded.
68. State the need for indirect addressing mode. Give an example. Apr/May 2017
The register or memory location that contains theaddress of the operand is a pointer. When an
execution takes place in such mode, instruction may be told to go to a specific address. Once it's there,
instead of finding an operand, it finds an address where the operand is located.
In this case the number is usually enclosed with square brackets.
LD Acc, [5];Load the value stored in the memory location pointed to by the operand into the
accumulator Memory location 5 is accessed which contains 3. Memory location 3 is accessed which is
 17.
Ax becomes 17.
69. Specify the CPU performance equation. Nov/ Dec 2012
The performance equation analyzes execution time as a product of three factors that are relatively
independent of each other. The three factors are, in order, known as the instruction count (IC), clocks
per instruction (CPI), and clock time (CT). CPI is computed as an effective value.
f represents the frequency of energy-consuming transition s (0→1)
70. Give the MIPS code for the statement f=(g+h)-(i+j). May 2019
Simple arithmetic expression,assignment
int f, g, h, i, j;
f = (g + h) - (i + j);

Assume variables are assigned to $s0, $s1, $s2, $s3, $s4 respectively add
$s0, $s1, $s2 # $s0 = g + h
add $s1, $s3, $s4 # $s1 = i + j
sub $s0, $s0, $s1 # f = (g + h) - (i + j)

71. Define Word Length. Nov/Dec-2019

A word is a unit of data of a defined bit length that can be addressed and moved between storage and
the computer processor. ... Typically, an instruction is a word in length, but some architectures support
halfword and doubleword-length instructions
72. What is Zero address instruction format? Nov/Dec 2020
A zero-address instruction implies that the absolute address of the operand is held in a special
register that is automatically incremented (or decremented) to point to the location of the top of the
stack.

Part B
1.Explain the functional units of a digital computer in detail(16)
2.Explain the Von-Neumann Architecture in details(8 or 10)
3.Write about Operation and Operands of a Computer Hardware instruction(16)
4.Explain ISA in detail(8)
5.Explain the different types of addressing modes in detail(16)
6.Explain the single instruction execution in detail(8)
7.Explain about the encoding of instructions(8)
8.Write about Assembly language and High Level Language(8)