Module 2

Chapter

Logic Families
Syllabus
Difference between analog and digital signals, Logic levels, TTL and CMOS logic families and their
characteristics.

Chapter Contents
2.1 Signals 2.7 Tristate (Three State) TTL Devices

2.2 Binary Logic and Logic Levels 2.8 Standard TTL Characteristics

2.3 Logic Families 2.9 CMOS Logic

2.4 Classification of Logic Families 2.10 CMOS Characteristics
2.5 Digital IC Parameters (Characteristics) 2.11 Interfacing
2.6 Transistor Transistor Logic (TTL) 2.12 Comparisons
 LOgi

DSD (Sem. III /E&Tc/ MU) 2-2

2.1 Signals :
1
Definition: 1

We can define "signal" as a physical quantity, which 1

signal(Digitalsignal)
contains some information and which is a function of 2.1.2:Binary distin
(B-2163)Fig. having eight
one or more independent variables. digital signal
Octal signal : A an octalsignal.
values is called
as sixteen
2.1.1 Types of Signals : digital signal having
Hexadecimal signal:Athe hexadecimal number
The signals can be of two types : calledas
distinct values is distinct values
of
1. Analog signals 2. Digital signals. digitalsignal Number
Type of 2
2.1.2 Analog Signals : Binary
8
Definition: Octal
16
having
An analog signal is defined as the signal Hexadecimal
continuous values. They can have infinite number of Digital Signal :
different values. 2.1.4 Sources of the
analog. can be obtained directly from
Most of the quantities observed in nature are The digital signals computers is
data used by the
The examples of analog signal are as follows : computers. All the
1. Temperature 2. Pressure digital. (Analog to
4. Sound can also use an A to D converter
3 Distance We signals
convert analog
5 Brightness 6. Voltage digital converter) in order to
7 Current 8. Power into digital signals.
Signals:
All the analog signals are continuous signals as 2.1.5 Advantages of Digital
shown in Fig. 2.1.1. transmitted
Temperature Pressure 1. Digital signals can be processed and
A
more efficiently and reliably than analog signals.
2. It is possible to store the digital data.
Time Distance 3 Play back or further processing of the digital
Brightness data is possible.
Voltage
4 The effect of "noise" (unwanted voltage
fluctuations) is less. So digital data does not get
Time Distance corrupt.

(C-1) Fig. 2.1.1 :Graphical representation of analog signals

2.1.6 Comparison of Digital and Analog
Signals :
2.1.3 Digital Signals :
Sr.
Definition : No.
Parameter Analog signals Digital signals
A digital signal is defined as the signal which has 1. Number of Infinite Finite (2, 8, 16
only afinite number of distinct values values
etc.)
Digital signals are not continuous signal. They are 2. Nature
Continuous Discrete
discrete signals as shown in Fig. 2.1.2. 3. Sources Signal Computers, Ato
Binary signal :If adigital signal has only two distinct
values, i.e. 0 and 1 then it is called as a binary signal.
generators, Dconverters
transducers etc.
Tech Knouwledgë
PubI ationS
 DSD (Sem. III /E&Tc / MU) 2-3
Logic Families
Sr. 2.3 Logic Families :
Parameter Analog signals Digital signals
No.
Examples
Definition:
4
Sinewave, Binary signal
triangular wave Logic families are defined as the type of logic circuit
5 Applications Operational Television, used in an IC. Various digital ICs available in market
amplifiers, Military belong to various types. Each type is known as a
telephones systems, logic family.
Microprocessors Various digital ICs available in market belong to
2.2 Binary Logic and Logic Levels : various types. These types are known as "families".
Based on the components and devices internally
A logic statement, is defined as a statement which is
used, the digital IC families are named as RTL
true if some condition is satisfied and false if that
(Resistor transistor logic), TTL (Transistor Transistor
condition is not satisfied. For example, a bulb turns
ON, if we close the switch, othenwise it is OFF.
Logic), DTL (Diode Transistor Logic), CMOS etc.
Features of logic families :
2.2.1 Positive Logic: Table 2.3.1 gives the comparison of some of the
A"LOW" voltage level represents "logic 0" state and outstanding features of these logic families.
a comparatively "HIGH" output voltage level Table 2.3.1 :Comparison of important
features of logic families
represents "logic 1" state, as shown in Fig. 2.2.1(a).
Sr. Characteristics TTL CMOS ECL
For example, 0 Volt represent a logic 0 state and
No.
+5 V represent logic . This is called as "positive Moderate
1. Power input Moderate Low'
logic". to high
Positive Logic : Logic0 (LOW) =o v,) 2. Frequency limit |High Moderate Very high
Logic 1 (HIGH) = + 5 V. 3. Circuit density Moderate High to Moderate
|to high very high
2.2.2 Negative Logic : Moderate
4. Circuit ty pes per High High
A "LOW" voltage level represents "logic 1" state and family
a "HIGH" output voltage level represents "logic 0" Thus TTL family has a great versatility. It has high
state, as shown in Fig. 2.2.1(b). speed as well (delay less than 1 nS for some TTL
For example, 0 Volts represent a "logic 1" state and subfamilies).
+ 5 V represent "logic 0" state. This is calld as The CMOs family is popular because of its low input
"negative logic". power and very high circuit density i.e. more circuits
Negative Logic : Logic 0(LOW) =5V) can be placed in the same volume of IC.
Logic 1 (HIGH) =0 V. ) ECL is used for very high speed digital circuits. But it
+5V
+5V
........Logic 1 . . .Loglc 0
Output T Output needs more input power and less types of logic
voltage voltage
circuits are available in ECL than those available in
-Logic O OV Logic 1
TTL and CMOS.
(a) Positive logic (b) Negative logic
(B-439) Fig. 2.2.1 2.4 Classification of Logic Fanmilies :
Note: In thís chapter, we are going to consider only
The classification of logic families is shown in
the positive logiC, Also we will assume the logic Fig. 2.4.1.
0 level corresponds to 0 Volts and logic 1 level
Corresponds to +5 V.
The two basic techniques for manufacturing ICs are:
1 Bipolar technology.
Teshknouledge
Pubiiratlons
 LOd es

DSD (Sem. III / E&Tc / MU) 2-4

Families : MOS Field Effect
2. Unipolar devices-Metal Oxide Semiconductor 2.4.2 MOS fabricates So s.
family
use
on the chip.
(MOS) technology. The Mos (MOSFETS) fabricated family use the
Digital ICs Iransistors the MOS
belonging to
the gates
MOSFET based'circuits.
Bipolar Unipolar are three logic families
categorythere family, NMOe
MOSFETS)
In the MOS (p-channel and CMOS
namely PMOSMOSFETS)
Unsaturated PMOS NMOS CMOS
Saturated family
(P-channel (N-channel (Complementarý
" Resistor transistor MOSFET) MOSFET) MOSFET) (complementary
(n-channel MOSFETS) family.
logic (RTL) type. VMOS is used
and slowest for the
" Diode transistor
PMOS is the
oldest Integration) field i.e.
logic(DTL) Schottky Emitter coupled logic (Large Scale
" Direct coupled TTL (ECL) for the LSI
microprocessors and memories.
transistor arrangement of n.
logic (DCTL) push pull
CMOS which
uses a extensively uSed
"Integrated injection logic (I´L) p-channel MOSFETS, is
channel and such as in
" High threshold logic (HTL) consumptionis needed
Transistor transistorr logid(rTL) where low power
pocket calculators.
(C-205) Fig. 2.4.1 :Classification of logic families Circuit
Classification Based on
2.4.1 Bipolar Families : 2.4.3
Complexity :
available in
The bipolar families of logic circuits use
the bipolar circuits of different types are
all the The logical Depending on the level
of
transistors fabricated on the chip. That means circuits.
use the the integrated circuit are classified
into
gates belonging to the bipolar family complexity the integrated
transistorised circuits.
follows :
basic families four categories as
In the bipolar category there are three
called, Diode Transistor Logic (DTL), Transistor 1 SSI : SmallScale Integration.
Medium Scale Integration.
Transistor Logic (TTL) and Emitter Coupled Logic 2. MSI :

(ECL). 3 LSI : Large Scale Integration.

DTL uses diodes and transistors, TTL uses transistors 4 : Very Large Scale Integration.
VLSI
as the main elements. TTL has become the most transistors,
The number of components (diodes,
popular family in SSI (Small Scale Integration) and gates etc.) in SSI will be the lowest
and that in VLSI
MSI (Medium Scale Integration) chips, while ECL is
will be the highest.
the fastest logic family which is used for high speed
applications. 1 Small Scale Integration (SSI) < 10 components.
(MSD < 100
In the "Bipolar saturated" logic families, the bipolar 2. Medium Scale Integration
transistors are used as the main device. It is used as a components.
switch and operated in the saturation or cutoff 3. Large Scale Integration (LSI) > 100 components.
regions. 4. Very Large Scale Integration (VLSI) > 1000
TTL is an example of saturated bipolar logic. components.
In the unsaturated bipolar logic, the bipolar 2.5 Digital lCParamneters
transistors are not driven into hard saturation. This
(Characteristics) :
increases the speed of operation. So the unsaturated
bipolar ICs such as Schottky TTL and ECL (emitter MU : May 03, May 10, May 12
coupled logic) are much faster as compared to TTL. University Questions
Q. 1 What are the
All these ICs are fabricated on silicon chips using characteristics of logic family ?
different fabrication technologies. (May 03, 8 Marks)
SE Tech Knouledgë
E DSD (Sem. III /E&Tc/ MU) 2-5
Logic Families
o 2 Explain parameters of logic families. 1.
t
VL (max) - Worst case low level input voltage:
(May 10, 8Marks)
o3 List various characteristics of digital ICs and This is the maximum value of input voltage which is
explain their significance in brief. to be considered as a logic 0 level. If the
input
(May 12, 8 Marks) voltage is higher than L (maxy then it will not be
Eventhough there are various logic families, the treated as a low (0) input level.
general
characteristics, their definitions, and 2. VIH (min) - Worst case high level input voltage:
terminologies used for all of them have been This the
standardized. minimum value of the input voltage which
is to be considered as a logic 1 level. If the input
So let us discusS Some of the most
important general voltage is lower than VH (minly then it will not be
characteristics that are applicable to all the digital ICs treated as a High (1) input.
first and then discuss them for some
particular 3.
families. VOH(min) Worst case high level output voltage:
The important characteristics of all the digital IC This is the minimum value of the output voltage
families are as follows: which will be considered as a logic HIGH (1) level. If
the output voltage is lower than this level then it
1. Voltage and current parameters.
won't be treated as a HIGH (1) output.
2 Fan-in and fan-out.
4. VoL (max) - Worst case low level output voltage :
3 Noise margin.
This is the maximum value of the output voltage
4 Propagation delay (speed). which will be considered as a logic LOW (0) level. If
5 Power dissipation. the output voltage is higher than this value then it
6. Operating temperature. won't be treated as a LOW (0) output.
All the voltage parameters are shown in Fig. 2.5.1.
7. Invalid voltage levels. Input Output
voltage voltage
8. Figure of merit (SPP).
VGc
2.5.1 Voltage and Current Parameters: Logic
1

MU : May 10, May 11, Dec. 11,Dec. 12 VIH(nin) VOH(min)

Undefined Undefined
University Questions
Logie NL(max VoL(mav)
Q.1 Explain parameters of logic families. 0.

(May 10, 8 Marks) (a) Input voltage parameters (b) Output voltage
a. 2 Explain characteristics of logic families with parameters
(C-7584) Fig. 2.5.1: Voltage parameters
examples : Voltage parameters. (May 11, 2Marks)
The voltage parameters can be shown on the digital
Q.3 Explain characteristics of logic families Current
parameters (Dec, 11, Dec.12, 2Marks) circuit consisting of gates as shown in Fig. 2.5.2.
Note that, the NAND and NOT gates shown, can be
Voltage parameters (Threshold levels) : of TTL, ECL, CMOS or any other type.
Ideally the input voltage levels of 0 V and + 5 V (for 1
HIGH LOW
TTL) are called as logic 0 and 1 levels respectively. LOW HIGH
HIGH LOW
However practically we won't always observe or
obtain the voltage levels matching exactly to these VOH VIH HIGH
VoL ViL
values.
Therefore it is necessary to define the worst case
input voltages. (C-207) Fig. 2.5.2: Voltage parameters on a logic circuit
TechKnouwledge
Pub cations
 DSD (Sem. II /E&Tc / MU) 2-6 Fan-out: May1
and 09, May10,
2.5.2 Fan-in 08,May 14,May
18
Current parameters : Mav 06. Dec. Dec.
MU: May14,
11.Dec. 12,
(a) I -Low level input current: Dec.
fan in.
It is the current that flowS into the input terminals UniversityQuestions Fanoutand 12
terms: 11, Dec.
following
when a low level input voltage in the specified range Definethe 11,Dec.
Marks)
09, May
Q. 1
Dec. 08, May Dec. 14, May15, 4
is applied. (May06, May14, families.
logic Marks)
(b) IH High level input current : parameters of (May 10, 8
Explain
input terminals 2
It is the current that flows into the
when a high level input voltage in the specified range gate hac
Fan-in: number of inputs a
as the fan-in egual
is applied. Fan-in is defined input gate will have a
a two
(c) loL - Low level output current: For example
output when to 2.
This is the current that flows out of the of inpute
in the specified Fan-out: maximum number
the output voltage happens to be as the drive without
applied.
load is Fan-out is defined a gate can
low (0) voltage range and a specified family that limits
of the same IC specified output voltage
(d) loH - High level output current: the
falling outside indicates supplying
higher the current
This is the current flowing from the
output when the Higher fan out
output voltage happens to be in
the specified HIGH capacity of a gate. indicates that the gate
fan out of 5
(1) voltage range and a specified
load is applied. For example, a to) at the most5
inputs of
current
output terminal can drive (supply
If the output current flows into the
and if the the same IC family.
then it is called as a sinking current
terminal then 2.5.3 Noise Margin :
output current flows out of the output May 10, May 11, Dec.
11.
it is called as a sourcing current. MU : May 06, May 09,
May 15, Dec. 16
logic Dec. 12, May 14, Dec. 14,
The current parameters are displayed on the
circuit shown in Fig. 2.5.3. University Questions.
Q.1 Define the term: Noise margin.
(May 06, May 09, May 11, Dec. 11,
DeG 14, May 15, 2 Marks)
Dec. 12, May 14, Dec.
LOW
Q.2 Explain parameters of logic families.
HIGH HIGH {May 10, 8 Marks)
LOW
Q.3 Define noise margin, propagation delay, power
(a)
dissipation, (Dec. 16, 5 Marks)
+ 5V
HIGH loL
To understand the meaning of the term "Noise
Margin" or "Noise Immunity", refer to the input and
LOW LOW output voltage profiles shown in Fig. 2.5.4.
HIGH
Voltage
(b) Valid logic "1
(C-208) Fig. 2.5.3 : Current parameters
Valid logic "1" VOH(min)
Note that the actual current directions can be

opposite to those shown in Fig. 2.5.3; depending on Invalid VIH(min) Invalid

the logic family.

Note that current flowing into a node or deviçe is Valld logic VL(nax) VN.J VoL(mal Valid logic "0"
considered positive and current flowing out of node
(a) Input profile
or device is considered negative. (b) Output profile
(C-210) Fig. 2.5.4
TechKnowledge
Pub|atinns
 pSD (Sem. III / E&Tc /MU) 2-7 Logic Families
Noise is an unwanted electrical disturbance which There is a time delay between these two time
may induce some voltage in the connecting wires
Used betwen two gates or from a gate output to instants, which is called as the propagation delay.
load. Thus propagation delay is defined as time delay
Noise immunity is defined as the ability of a logic between the instant of application of an input pulse
circuit to tolerate the noise without causing the and the instant of occurrence of the
corresponding
Öutput to change undesirably. output pulse. This is shown in Fig. 2.5.5.
Aquantitative measure of noise immunity of a logic Input Output
family is known as noise margin.
In order to avoid the effects of noise
voltage, the
designers adjust the voltage levels VoH (min) and L 50%

VH (min) to different levels with some difference Input

between them as shown in Fig. 2.5.4, H
Output
The difference between V,OH (min) and V (min) iS known 50%

as the high level noise margiH VyH:

Similarly the difference between V (maw and oL (max iS PHL tPLH
called as the low level noise margin Vi. (a) Propagation delays for an inverter
High level noise margin, VNH = VoH (min) -VH (min) 4+Vcc
Output
Low level noise margin, VNL =V max Vo tmen Input.

When a high logic output is driving a logic circuit

H
input, any negative noise spike greater than VNH can ..... 50%
force the voltage to reduce into the invalid range. Input

H
Similarly when a low logic output is driving a logic 50%
circuit input, any positive noise spikes greater than Output
V can force the voltage to go into the invalid state.
tpLH -fPHL
2.5.4 Propagation Delay (Speed of (b) Propagation delays for an AND gate
Operation): (C-211) Fig. 2.5.5
From Fig. 2.5.5 it is observed that there are two
MU : May 06, Dec. 08, May 09, May 10, May 11, Dec. 11
Dec. 12, Dec. 14, May 15, Dec. 16
propagation delays.
tpHL It is the propagation delay measured when the
University Questions output is making a transition from HIGH (1) to LOW
a.1 Definethefollowing term: Propagation delay (0) state.
(May 06, Dec. 08, May 09, May 11, Dec, 11, Dec. 12, 2. tpH: This is the propagation delay measured when
Dec. 14, May 15,2 Marks) the output makes a transition from LOW (0) to HIGH
Q. 2 Explain parameters of logic families. (1) state.
(May 10, 8Marks) (a) The values of to and tp are not always equal. If
Q.3 Define noise margin, propagation delay, power they are not equal then the one which is higher is
dissipation. (Dec. 16, 5Marks) considered as the propagation delay time of the
Definition : gate.
The output of a logic gate does not change its state (b) The propagation delays are measured between the
instantaneously when the state of its input is points corresponding to 50% levels as shown in
Fig. 2.5.5.
changed.
Tech Knowledge
ubcatlons
 LOgiCramlies

DSD (Sem. II / E&Tc/ MU) 2-8 Temperature:

Dec. 1
2.5.6 Operating Te MU : May 10,
Ideally propagation delay should be zero and

practically it should be as short as possible.

University Questions families.
The values of propagation delays are used to logic Marks)
parameters of (May 10, 8
measure how fast a logic circuits is. Explain families
Q.1 of logic
(Dec. 12, 2 Marks)
characteristics
For example, a logic circuit with a propagation time Explain
of 5 nS will be a faster logic circuit than the one with Q. 2 Temperature range. the Consumer
load acceptable for
10 nS propagation time, under the specified temperature range 70° C and
that s.
The applications is 0° to
conditions. C.
and
industrial 55°Cto 125°
2.5.5 Power Dissipation : applications is -
specified
the military will be in the
MU : May 06, May 09, May 10, Dec. 14, May 15, Dec.
16 performance of gates ranges.
The temperature is in these
University Questions limits only if the
($peed Power Product
Q.1 Define the term : Power dissipation.
2.5.7 Figure ofMerit
Marks)
(May 06, May 09, Dec. 14, May 15,2 SPP) : Dec. 1
May 11, Dec. 11,
Q. 2 Explain parameters of logic families. MU: May 10,
(May 10, 8 Marks).
power University Questions families.
Define noise margin, propagation delay, parameters oflogic
Q.3
(Dec.16, 5Marks) Q. 1 EXplain (May 10, 8 Marks)
dissipation. with
characteristics of logic families
Definition : Q.2 Explain
flowing through examples figure ofmerit. Marks)
Due to applied voltage and currents (May 11, Dec. 11, Dec. 14, 2
dissipated in it, in
the logic ICs, _ome power will be
the form of heat. Definition :
family is the product
The figure of merit of a logical
be taken to
This power is in milliwatts. Care should
reduce the power dissipation taking place in the propagation delay. It is
of power dissipation and
logic IC in order to protect the IC against damage product. The speed is
called as the speed power
due to excessive temperature, to reduce the loading
specified in seconds and power is specified in W.
on power supplies etc.
Figure of merit = Propagation delay time x Power dissipation.
Another importance of power dissipation is that the
product of power dissipation and propagation time is Ideally the value of figure of merit is zero and
always constant. practically, it should be as low as possible.
Therefore if we reduce the power dissipation may Figure of merit is always a compromise between
lead then the propagation delay will increase in order speed and power dissipation. That means if we try to
to keep their product constant. reduce the propagation delay then the power
Usually there is only one power supply terminal on dissipation will increase and vice-versa.
any IC. t is denoted by Ve for the TTL ICs and Von
2.5.8 Invalid Voltage Levels :
for the CMOS ICs.

The power drawn by an IC from the power supply is The operation of a logic circuit will be proper if and
given by, only if its input voltage levels are kept outside the
P= Vcc x lcc invalid voltage range.
where Ir is the current-drawn from the power That means the input voltage should be
than V (max) Or higher than VH
either lower
supply. (min.)"
TechKnowledge
Pubca t ions
 DSD (Sem. III/E&Tc / MU) 2-9
Logic Families
invalid input produce
The voltage will an
The long form of TTL is transistor logic. The digital
unpredictable output response. Therefore it should ICs in the TTL family use only transistors as their
be avoided.
basic building block.
When the output is overloaded, there is a possibility
of output voltage going into the invalid range. TTL ICs were first developed in 1965 and they were
known as "standard TTL". This version of TTL circuits
o69 Current Sourcing and Current Sinking : is not practically used now due to availability of
Current sourcing: advanced versions.
The current sourcing action is illustrated in The standard TTL has been improved to a great
Eia. 2.5.6(a). Gate-1 acts as a source and Gate-2 acts
extent over the years.
as load.
TTL devices are still used as "glue" logíc which
The output of Gate-1 is high. It supplies a current I,
to the input of Gate-2. This is called as the connects more complex devices in digital systems.
current
sourcing action.
The bipolar TTL family as a whole is now becoming
Current sinking : obsolete, but we can study it in order to understand
The current sinking action has been demonstrated in basic important concepts in general about the logic
Eia. 2.5.6(b). Gate-2 which is the load gate acts as a families.
load.
As SOOn as the output of Gate-1 goes low, the 2.6.1 The Multiple Emitter Transistor:
current starts flowing into the output terminal of In the TTL circuits that we are going to discuss, use a
Gate-1 as shown in Fig. 2.5.6(b).
very special type of transistor.
Thus when gate-1 is accepting the current through
The normal transistor has only three terminals
its output terminal, it is said that the current sinking
is taking place. namely collector, base and emitter.
+Voc
But this special transistor has more than one
Gate-1 Load gate
emitters, as shown in Fig. 2.6.1(a) and its equivalent
1 H Gate - 1sources
Curent to circuit is shown in Fig. 2.6.1(b). The number of

Driving
VoH Gate-2
Gate - 2
emitters equal tothe number of inputs of the gate.
gate
(a) Current sourcing The multiple emitter input transistor can have upto
eight emitters, for an eight input NAND gate.
+Vo +Vcc
Gate-1
In the equivalent circuit of Fig. 2.6.1(b), diodes D, and
Gate - 1 receives (Sinks) D, represent the two base to emitter junctions
VoL Current from
1 Gate -2 whereas D, represents the collector to base junction.
Driving Gate-2
gate In the forthcoming discussions, we are going to
(b) Current sinking replace the multiple emitter transistor by its
(C-1000) Fig. 2.5.6
equivalent circuit shown in Fig. 2.6.1(b).
2.6 Transistor Transistor Logic (TTL): This transistor can be turned ON by forward biasing
MU: Dec. 07, May 08 either (or both) the diodes D, and D,
University Questions This transistor will be in the OFF state if and only if
Q.1 Explain TTL, CMOS, ECL Logic Families. both the base-emitter junctions (D, and D,) are
(Dec, 07, May 08, 5 Marks)
reverse biased.
TechKnowledge
PubICot0ns
 LOy
dmlien
input
RF DSD (Sem. II/E&Tc / MU) 2-10
input
terminals. The
ideallv)
voltages
Base
A and B arethe LOW (zero volts HIGH
be either
1.
Base Emitter
1
D, and B can
(+ Vaeideally).
Emitter 1 Emitter
De bothLOW: ground, then bot
Colleotor 2. A andB connectedto forward
Emitter 2 Colleotor are
and Bboth transistor Q,
are biased.
If AB-Ejunctions of
(a) Multiple emitter transistor (b) Equivalent circuit 2.6.3 will conduct t
the in Fig.
(C-1011)Fig. 2.6.1 and D,
Hence diodes
D,
in Fig. 2.6.3 to 0.7V
C
Standard TTL: voltage at point
force the +Vcc
The 7400 TTL series is known as the standard TTL
series. The TTL gates that we are going to discuss
belong to this family.
2.6.2 Two Input TTL-NAND Gate
(Totem Pole Output):
Bo
MU: Dec. 02, Dec. 11, May 19 -Equivalentof Q
University Questions equivalen
Q,1 Draw a standard TTL NAND gate and explain its 2.6.3: Transistor Q, is replaced by its
(C-1012) Fig. base
working. (Dec. 02, 9 Marks)
is insufficient to forward bias
This voltage of D.
Q. 2 Draw standard TTL 2 input NAND gate circuit, due to the presence
emitter junction of Q
discuss its operation and draw its transfer OFF.
(Dec. 11, 10 Marks) Hence Q, will remain
characteristic.
rises to Ve:
Q.3 Draw and explain two input TTL NND gate. Therefore its collector voltage V,
in the emitter followe
(May 19, 5 Marks) As transistor Q, is operating
voltage.
Circuit diagram : mode, output Y willbe pulled up to high
B=0 (LOW)
Atwo input TTL-NAND gate is shownin Fig.2.6.2. A .:. Y =1 (HIGH) ...For A=
and B are the two inputs while Y is the output condition
terminal of this NAND gate.
The equivalent circuit for this input
+Vcc
shown in Fig. 2.6.4(a).
3 Either Aor B LOW:
R, R
Totempole If any one input (A or B) is connected to ground wit
Output stage
the other terminal left open or connected to + V,
AO
Inputs then the corresponding diode (D,or D,) will conduct
Q,

Y(output)
This will pull down the voltage at "C" to 0.7
Multiple
emitter transistor (Fig. 2.6.3)
This voltage is insufficient to turn ON D, and Q,. So
remains OFF.
So collector voltage V, of Q, will be equal to Vce. Thi
(C-1012) Fig. 2.6.2: Two input TTL NAND gate voltage acts as base voltage for Q,.
Operation: As Q, acts as an emitter
follower, output Y will b
In order to understand the operation of this circuit, pulled to Vcc
let us replace transistor Q, by its equivalent circuit as
.. Y =1 A = 0 and B 1
shown in Fig. 2.6.3. l if A= 1 and B
=0 (C-6373)
TechKnouledg=
PubIi c ation
 BE DSD (Sem. II / E&Tc / MU) 2-11 Logic Families

The equivalent circuit for this mode is shown in The equivalent circuit for this mode of operation is
Fig. 2.6.4(b). shown in Fig. 2.6.4(c).
p+Voo
q+Vcc
R,

Q, ON
D D +Vcc ag OFF
A Kit OFF OFF
D,
D2
Y HIGH
At K
B K o= 0.7V OFF ON ON
oY= LOW
BothON JQ4 OFF
diodes
B K JQ, ON
OFF

(a) Equivalent circuit for A= B =0

4
Aand B both HIGH:
(C-1014) Fig. 2.6.4(c): Equivalent circuit for A = B = 1
1f A and B both are connected to + V then both
This discussion reveals that the circuit operates as a
the diodes D, and D, will be reverse biased and do
NAND gate.
not conduct. Therefore voltage at point "C" i.e. at the
anode of D, increases to a sufficiently high value. Truth Table :

p+Vco The Truth Table of Two input standard NAND gate is

as follows.
(G-7538) Table 2.6.1: Truth Table of a 2-input NAND gate
R

Qg ON Inputs Status of varlous transistors

D D
D D2
output
OFF OFF OFF ON ON OFF ON OFF 1
D

1 ON OFF OFF ON OFF 1

ON

1 OFF ON OFF ON OFF 1

OFF

1 1 OFF OFF ON OFF ON

(b) Equivalent circuit for A = 1, B = 0 2.6.3 Totem-pole (Active Pullup) Output

(C-1013) Fig. 2.6.4 Stage:
Therefore diode D, is forward biased and base The arrangement of Q, and Q, on the output side of
current is supplied to transistor Q, via R, and D, as a TTL NAND gate is called as the totem-pole
shown in Fig. 2.6.4(c).
arrangement.
As Q, conducts, the voltage at X willdrop down and It is possible in TTL gates to speed up the charging of
Q, will be OFF, whereas voltage at Z (across R,) will
output capacitance without corresponding increase
increase to a sufficient leveltoturn ONQ
in the power dissipation with help of Totem-pole
As Q, goes into saturation, the output voltage Ywill
output stage.
be pulled down tO a low voltage.
The Totem-pole output is also known as active pull
...For A= B= 1 up.
TechKnowledge
Pub|cat on
 should
DSD (Sem. II / E&Tc / MU) 2-12 unused
inputs
or
eitherto Vbe
returned
input(s)
However, thhesome used ia
Advantages of totem-pole output stage: Connectedto resistor as
shOwnin 2.6.5(b).
suitable
The advantages of using the totem-pole output througha a
stage are as follows : Clamping
Diodes:
subjected to
1 It reduces the power dissipation taking place in the 2.6.5
should not be negative
inputs operating conditions
circuit. The TTL
voltages.
Under
normal tis
2. It has a very low output impedance (typically 10). getsmanagedeasily. applied at the
Disadvantages of Totem-pole output : transitions are input
voltage ringing (sinusoida
For a very short duration of few nanoseconds, both Butif fast possibility of
then there
is a
positive and
negative half cycles),
the transistors will be simultaneously ON. This is oscillations with
called as cross conduction and it will draw relatively the inputs will
be subjected to
Due to
ringing,
large current (30 to 40 mA) from the 5 Vsupply.
negative voltages.
clamping diodes are
Function of diode D: this ringing,
suppress in all the TTL circuits
Diode D connected between transistors Qand Q is
To connected externally
generally
used for successfully avoiding the cross conduction. Fig. 2.6.6(a).
as shown in forwar
Function of R,: recovery diodes. They are
used then These are fast the ringine
During the cross conduction, if R, is not negative half cycles of
series biased during the negative inpe
there will be no current limiting element in sinusoidal waveform. Hence the
drawn
with Q, and Q, and a heavy current will be
restricted (clamped) to - 0.7 Vol
voltage will be
from the source for a short duration. Fig. 2.6.6(b).
approximately as shown in D, is ON in the
This can be avoided by limiting the current by negative cycle of
inserting resistor R, in series with Q,. ringing and clamps
Ringing
VA to 0.7V
2.6.4 Unconnected Inputs : Qy (Input
transistor)
A
If any input of a TTL gate is left open, disconnected
or floating, then the corresponding base emitter B
junction of the input transistor Q, is not forward D, ZA A D, 0.7V AD,
ON
biased as shown in Fig. 2.6.5(a).
KClamping
diodes
This base-emitter Voc
junction is
réverse biased
Floating (a) Clamping diodes (b) Effect of clamping diodes
input
(C-1019) Fig. 2.6.6
A.
Bo 2.6.6 Device Numbers for TTL 7400 Series :
Unused input
Q is returned to Q4
Vcc through R Table 2.6.2gives some of the TTL 7400 series gates.
Table 2.6.2: Standard TTL gates

(a) Unused input (b) Standard connection Device number Description

(C-1018) Fig. 2.6.5
7400 Quad 2-input NAND gate
Therefore the open or floating input is equivalent to 7402 Quad 2- input NOR gate
a logical 1 is applied to that input.
7404 Hex inverter
Hence in TTL ICs all the unconnected inputs are
7408
treated as logical 1s. Quad 2 - input AND gate
TechKnouwledge
Publitation
 DSD (Sem. IIl / E&Tc /MU) 2-13
Logic Families
Device number Description Hence Qa is on andQ, is off. Hence output Y= 1.
7432 Quad 2 - input OR gate 2 A=0, B=1:
7486 Quad 2 - input XOR gate Transistor Q, conducts but Qremains off. Hence Q,
remains off but Qs conducts.
2.6.7 5400 Series:
Since Q, and Qare in parallel, the conducting Q will
The temperature range for the devices in 7400 series
bring the potential at "X" low and that at "Z" will go
is from 0 to 70°G, Over a supply voltage range of 4.75
to5.25 V. up.
Hence Q, will be off and Q, turns on. Hence output
So 7400 series used for the commercial Y = 0.
applications.
But 5400 TTL series is developed specially for the 3. A=1, B=0:
military applications. Q remains off but Q turns on. Hence Q, will
The devices of 5400 series operate over the conduct and Qremains off.
temperature range of - 55 to 125°C and over the The potential at X comes down and that at Z goes
supply voltage range of 4.5 to 5.5 Volts. up. So Q, will be off and Q, will be on. Hence Y=0.
2.6.8 TTL NOR Gate: 4 A=B=1:

Circuit diagram : Both Q, and Q are off. Hence Q, and Q: conduct.

In order to get the 2-input NOR operation, the Potential at X decreases and that at Z is increased.

manufacturers modify the 2-input NAND gate as So Q, is off and Q, turns on. Hence Y =0.
shown in Fig. 2.6.7. Function of diode D:
In this circuit, transistor Q, and Q, are newly added It important to avoid simultaneous conduction of
transistor. Rest of the circuit is same as that of the Q, and Q, because it will lead to cross conduction
TTL-NAND gate. and will increase power dissipation.
+Voo Thus D, is used for successfully avoiding the cross
conduction.
R4 RA
Truth Table :

Truth table of TTL NOR gate is as follows.

(C-7586)Table 2.6.3:Truth Table of a TTL NOR gate
Y evariosstransistors
Inputs Inputs Status of v
(Output) Outputs
Bo A B Q4 Q Q
Q4 ON OFF ON OFF ON OFF 1
Rs
1 ON OFF OFF ON OFF ON

(G-1021) Fig. 2.6.7 :TTL-NOR gate 1 OFF ON OFF ON ON ON

Operation : 1 OFF ON OFF ON OFF ON

1. A=B=0:
Refer to the inputs A, Band output Y columns in
Both transistors Q, and Qconduct. Hence Q, and Q
Table 2.6.3. This is indeed the truth table of a NOR
both remain off. Hence potential at point "X goes
high and that at point "Z" is low. gate.
Tech Knowledge
P u b t atlon s
 tri-state
DSD (Sem. II /E&Tc /MU) 2-14
block
diagramofa
signal OE inverte
2.7 Tristate (Three State) TTL Devices: The
outputstage (a). Theenable
2.7.1
shown inFig. transistors Q,
and Q,. decide
We have discussed the totem-pole and open IS operationof operates as a

collector output TTL configurations in chapters. Now

the
WhenOE =
1, then
the
inverter
output will
be norma
1(HIGH)
then will
let us study the third type of output circuitry used in
inverter. If
input is 0 pull up transistor Q,
2.7.1(a).The
TTL as well as CMOS logic families. It is called as the shownin Fig.
tristate configuration. (1),
It is called as tristate because it allows three possible
ON.
OE = 1
and input high
transistor
the outpu
Similarly with
because the
pull down
output states namely: will be
low
2.7.1(b).
1, HIGH shown in Fig.
be ON as
2. LOW 3. High Impedance (Hi - Z) state. impedance state :
High (zero), then irrespective
+Voc enable input OE = 0 transistors will
If the
input, both the remain
the status of
Internal
circuit Qg ON 2.7.1(c).
in Fig.
off as shown as high impedance
Input Output = HIGH operation is called
LOW This state of state the output
termips
state. In this anywhere
Q, OFF (Hi - Z) connected
i.e. not
OE =1 remains open circuit
(Enable)
of Tristate:
2.7.1 Advantages
(a) State 1: HIGH ICs can be Connected togethe
The outputs of tristate wire. But in
+Vcc they can make use of a Common
i.e.
reduction in switching speed
Internal
doing so there is no
circuit QaOFF
open collector ICs).
(this problem is faced for
because the tristate
-Output LOW
There is no reduction in speed
Input
HÊGH
totem-pole TTL
output when enabled, operates as a
Q ON totem-pole output
OE=1 So we get all the advantages of
such as low output impedance and high speed.
(Enable)

However note that when tristate outputs are

(b) State 2 : LOW
connected together, we should enable only one of
them at a time.
+Voo
Intemal Otherwise, two or more active outputs will fight to
drouit Qg OFF
take control of the common line. This will result in
Input Output HI-Z very high currents which can damage the ICs and
1 or 0
produce invalid output voltage levels.
Q, OFF
OE=0 2.7.2 Tristate Buffers: MU : Dec. 02
(Disabled)
(C) State 3: High Impedance state
University Questions
Q.1 What is a tristate gate ? Where is it used ?
(C-1032) Fig. 2.7.1
(Dec. 02, 2 Marks)
An additional input called Output Enable (OE) has A tristate buffer is a circuit which
either connects or
been introduced. Both the pull up and pull down isolates its input from its output., In other words It
transistors (Q, and Q,) are being used. controls the flow of signal from input to
output.
Tech Knowledge
P ub Cat on
 F DSD (Sem. III / E&Tc/ MU) 2-15 Logic Families
Tristate buffers are of two types, namely the non Three tristate buffers are used for connecting the
inverting buffers and inverting buffer. inputs A, B and C to the common bus.
The inverting tristate buffers will invert the input data As shown in Fig. 2.7.3(b), the enable signal E, is
while passing it to the output.
connected to +5 V. Therefore A gets connected to
Cia 2.7.2 shows the symbols and truth tables for a
the bus.
non-inverting buffer.
Since enable terminals E, and E, are connected to
Y A
(Output) (Input)
ground, the second and third buffer of Fig. 2.7.3(b)
(Input) (Output)
will go into the high impedance state. So B and C will
be isolated from the common bus.
Truth table
Truth table
Y 2.7.4 A TRI-STATE Inverter : MMU : May 11
A
EY
Hi -Z
1 Hi-Z A
University Questions
Q.1 Draw standard TTL inverter, discuss its operation
(C-1033) Fig. 2.7.2 : Tristate non-inverting buffers,
symbols and truth tables and draw its transfer characteristic.
(May 11,10 Marks)
27.3 Applications of Tristate Buffers
Circuit diagram :
(Bus Organization): MU: Dec. 02
University Questions Fig. 2.7.4 shows the circuit diagram of a Tri-State
O.1 What is a tristate gate ? Where is it used ? Logic (TSL) inverte.
(Dec. 02, 2 Marks) It has an enable input (OE) and a data input A and
Tristate buffers are used in those applications in óne output. The output stage is totempole type
which several signals are simultaneously connected which has been discussed earlier.
to a common bus. o+5V
The basicidea about the common bus and the use of
tristate buffers is illustrated in Fig. 2.7.3(a). R
Enable D;
input
OE
oK

Be Common oY
bus (Data input)
(Output)
E2
Q

(a) A, B, C are connected to a common (C-1035) Fig. 2.7.4: ATSL inverter

bus via tristate buffers
A gets connected
Operation :
to the common bus
1. When OE =LOW:
When OE = 0, diode D, is forward biased and is
+5V turned ON. Therefore the voltage at point X is equal
Be Band Care to 0.7 Volt, irrespective of the state of data input A.
isolated from
/the bus V, = 0.7 V is not sufficient to turn ON Qa, so it
remains OFF.
C
"OE" is also connected to one emitter of transistor
Q,. As OE = "0", transistor Q, is ON, hence Q, is OFF
(b) A is getting transmitted on the bus (as discussed for the NAND gate).
(C-1034) Fig. 2.7.3
TechKnowledge
Publicatlons
 Table2.8.1
DSD(Sem. III / E&Tc / MU) 2-16 Temperature
Voltage
Range|
0° C to 70°c
Range
As Q, is OFF, Current through R, is zero. So Q, is in Seriessupply
|TTL 5.25V
the OFF state. 4.75 Vto 55° Cto 125° n
74series V
Thus with OE = LOW (0), both the output transistors 4.5 Vto5.5
in the
Q, andQ, will be OFF and the inverter will be 54 series
output logic
High-Impedance state. Voltage levels :
shows the
input and voltag
2 When OE HIGH: Table 2.8.2 series.
74series
the TTL 74 for TTL
When OE = 1 (HIGH), the diode D. will be reverse levels for Voltage levels
Typical| Maximum
Table2,8.2:
biased. So it will be ineffective. Voltages Mínimum
junction of Q, 0.4 V
Also the corresponding emitter base 0.2 V

circuit of TSL inverter

will be reverse biased. So the VoL
2.4 V
3.4 V
only one input A.
now actsas aTTL NAND gate with
0.8 V
VoH
OFF, so V, = Vcc
If A = 0, then Q, is ON, so Q, is VL
1.
hence Q, turns ON and output Y = 2.0V
Q, is ON, So V, is low, but
VH family is o.4 V, Th
If A = 1, then Q, is OFF, so for the TTL
R, so Q goes into Thus noise
margin induced noise voltag
sufficient voltage appears across long as the
ICs wilI
saturation and Y = 0. means that as operation of the TTL
V, the
circuit operates as a less thsn 0.4
Thus with OE = 1, the given affected.
normal inverter.
Power dissipation : standard
operation of the TSL for the
Table 2.7.1 summarizes the average power dissipation
inverter.
The approximately 10 mW.
TSL inverter 74 series is parameters such as
tolerance
Table 2.7.1 : Operation of on the
Output It is dependent
Enable input Data input signal level etc.
OE = 1 A=0 Y=1
Propagation delay :
TTL gate
OE =1 A=1 Y= 0
propagation delay of a standard
The
Hi-Impedance (1 nanosecond = 10
approximately 10 nanoseconds
OE = 0 A=0 or 1

Logic symbol : seconds).

inverter is shown in Fan out:
The logic symbol of a TSL
of driving at the mo:
Fig. 2.7.5. Astandard TTL gate is capable
maintaining
Data input Data output 10 other TTL gates simultaneously,
limits. Hence fa
A output voltage within the specified
out of a TTL gate is 10.
Enable input All the important characteristics of TTL logic famil
OE are listed in Table 2.8.3.
inverter
(C-1036) Fig. 2.7.5: Logic symbol of TSL Table 2.8.3 : Important parameters of TTL logic family
2.8 Standard TTL Characteristics : Sr.
Parameter Values
two TTL series No.
The Texas instrument first introduced
1. Supply voltage 74 series: (4.75 to 5.25 V)
namely 54 series and 74 series.
54 series : (4.5 to 5.5 V)
Supply voltage and temperature ranges : 2. Temperature range 74 series: 0to 70° C
Table 2.8.1 gives the supply voltage and temperature 54 series: -55 to 125° C
ranges for two TTL families.
TechKnowledg=
PubcatI on
 DSD (Sem. II /E&Tc / MU) 2-17
Logic Families
Sr. Parameter The p and n channel MOSFETS are connected in
Values
No. series, with their drains connected together and
Voltage levels = 0.8 V.
3
Vumax)
VoL (max=0.4 V
output taken from common drain point.
Input is applied at the common gate terminal formed
ViH min) 2 V, by connecting two gates together.
VoH (min) 2.4 V
Noise margin
The 74CÌ0 CMOS series is a group of CMOS circuits
4. 0.4 V
which are pin-for-pin and function for function
5 Power dissipation 10 mW
compatible with the TTL 7400 devices.
6. Propagation delay 10 nanosec.
For example 74C32 is a quad 2-input OR gate in the
7 Fan out 10 CMOS family whereas 7402 is a quad 2 input TTL
8 Figure of merit 100 gate in the 7400 TTL family.

2.8.1 Advantages of TTL: 2.9.1 CMOS Inverter: MU: Dec. 12

TTL circuits are fast.

University Questions
1
Q.1 Draw CMOS inverter circuit, discuss its operation
2 Lowpropagation delay. and draw its transter characterístic.
(Dec.12, 10 Marks)
3 Power dissipation is not dependent on
Circuit diagram:
frequency.
Compatible to all the other families. CMOS inverter with positive input and output
4.
voltages is shown in Fig. 2.9.1(a).
5 Latch ups do not take place. p+Vbo
6 These are not susceptible to the damage due to
static charges. Q(PMOS)

7. Higher current sourcing and sinking capabilities.

+ Output
D
2.8.2 Disadvantages of TTL:
G
Q, (NMOS)
1. Large power dissipation.
2. Fan out is lower than that of CMOS.
3 Less component density. (C-1053) Fig. 2.9.1(a):CMOS inverter with positive voltages
4 Can operate only on + 5 Vpower supply. Operation :
5 Poor noise immunity. 1. With V, = 0 Volt (logic 0) :
2.9 CMOS Logic : With V, = 0 Volt, the gate to source voltage V of Q,
(NMOS) will be OVolt, hence it will be OFF. But Vee of
MU: Dec. 10, Dec. 11
Q, (PMOS) willbe equal to - Von- So Q, will be ON.
University Questions
Q. 1 Explain MOS logic farmilies. Hence the output voltage will be equal to + Von i.e.
(Dec. 10,10 Marks) logic 1.
Q.2 Write short noteon CMOS 1ogic family 2. With V, = Vop (logic 1) :
(Dec. 11, 5 Marks)
With V, = + Von the gate to source voltages of the
Definition:
two MOSFETs are as follows :
CMOS stands for complementary MOSFET. It is Q, (NMOS) : VGs1 = p.,
obtained by using a p-channel MOSFET and n
channel MOSFET simultaneously. Q, (PMOS): Ves = 0Volt
TechKnowledge
Pubicat Ions
 DSD (Sem. II / E&Tc / MU) 2-18 p+Voo
Q,(PMOS)
+VpD
Hence Q, will be turned ON and Q, will be OFF. So
Inputs G
a, (PMOS)
output gets connected to ground i.e. it will be "0".
S
Thus the inversion will take place. Q,(PMOS)
a (PMOs)
B
The operation of this inverter has been summarized Output
got y=Å+B
in Fig. 2.9.1(b).
G
V Output
OFF ON Von (logic 1) (NMOS) NMOS)
OV (logic 0)
Vop (logic 1) ON OFF 0(logic 0)
CMOS NORgate
Fig. 2.9.1(b): Summary of operation Fig.2.9.3:
(C-1055) ON and Q,
Waveforms and equivalent circuits : =1 if Q, and , both both
Output Y= Vonoutput Y = 0 if , or Q, or are
for the inverter
The input output voltage waveforms both OFF. And
both are ON.
or Q,
are shown in Fig. 2.9.2. OFFand Q,
1
VpD Operation:
Input 1 With A B =0: Hence and Q, will be
Vasy = - Von

ande, will be OFF.

1 ON.
So Q,
Vasa = 0, Vss =0,
VpD
shown in
Output
for this mode is
The equivalent circuit
OV
2.9,4(a) which shows that output Y :
Fig.
To,OFF! (logical 1).
=1.
.:. For A= 0,B = 0, output Y
9+VoD
Q, (PMOS)
+VpDo
Q, (PMOS)

V,=0 oOutput =Vpp V=VoD ’Output = 0 A= B=0 A=0, B=19 A=1, B=0

Q, (NMOS) Q, (NMOS) +Y=Vpp(1) +Y=0 Y=0

(C-1054) Fig. 2.9.2 : Input output voltage waveforms and

equivalent circuits for a CMOS inverter
2.9.2 CMOS NOR Gate:
(a) For A = B=0 (b) For A= 0, B =1 (c) For A= 1, B
Circuit diagram : =0
(C-1056) Fig. 2.9.4: Equivalent circuits
Fig. 2.9.3 shows the CMOS 2-input NOR gate. It is
2, With A=0, B=1:
obtained by modifying the CMOS inverter circuit.
If A =0 and B = 1, then Q.
Q, and Q, are p-channel MOSFETs connected in will remain ON, but Q,
will turn OFF.
series and Q, Q, are n-channel MOSFETs connected
Q, willremain OFF but Q,
in parallelwith each other. will be ON.
Input A is connected to the gates of Q, and Q, while The equivalent circuit for this
input Bis connected to the gates of Q, and Q.
Fig. 2.9.4(b) which shows that mode is shown in
(logical 0). output Y = 0 Voits

TechKnowledge
PubiIeations
 DSD (Sem. II /E&Tc/ MU) 2-19 Logic Families

Thus Y = 0for A=0 andB= 1, 2.9.3 CMOS NAND Gate :

3
With A=1, B= 0: Circuit diagram :
If A =1 and B = 0 then Q, will be OFF and Q, will The two input CMOS NAND gate is shown in
turn ON. Fig. 2.9.5(a) and its equivalent circuit by replacing
each MOSFET by a switch is shown in Fig. 2.9.5(b).
o will be turned ON but O, will turn OFF.

Fquivalent circuit of this mode is shown in

Fia. 2.9.4(C) which shows that Y= 0 volts (logical 0).
Ao
Thus Y= 0for A = 1, B= 0. (PMOS) (PMOS)
D

4. For A=B=1:
+Output
TD
f A and B both are high (1), then Q, and Q, both will
Qg (NMOS)
be OFF.
D
0. and Q, both will be ON. Hence output Y = 0.
Bo )Q,(NMOS)
The equivalent circuit for this mode is shown in
ig. 2.9.4(d) and Table 2.9.1 summarizes the
operation. (a) 2-input CMOS NAND gate
+VoD
A=1 s*
Q, (PMOS)

A-. Q.
B=1.. a, (PMOS) (PMOS) (PMOS) ?

+Output Y=0
Output

Q, (NMOS)
a,NMOS) i , (NMOS)
B-.. ä,(NMOS)

(C-1057) Fig. 2.9.4(d) : Equivalent circuit for A = B = 1 (C-1058) Fig. 2.9.5(b): Equivalent circuit
Truth Table : Q, and Q, are p-channel MOSFETs. They are
connected in parallel with each other.
Table 2.9.1 shows the truth table of the two input
NOR gate. Qa and Q, are n-channel MOSFETs. They are
connected in series with each other.
Table 2.9.1:Truth Table
Input A is connected to gates of Q, and Q. So A
Inputs Transistors Output controls the status of MOSFETs Q, and Q
A B Input B is connected to gates of Q, and Q. So B
controls the status of MOSFETs Q, and Q
ON ON OFF OFF Vop (1)
Operation :
1 ON OFF OFF ON 0
1. A=B=0:
1 OFF ON ON OFF With A= 0and B= 0, both the PMOSFETS i.e. Q, and
Q, will be ON. But both the N-MOSFETS 0.e. Q, and
1 1 OFF OFF ON ON
Qa willbe OFF.
TechKnowledge
Pubcatlons
 +VoD
2-20
DSD (Sem. III /E&Tc /MU

As seen from the equivalent circuit of Fig. 2.9.6(a), A=1-o,(P)

the output Y= + Von (logic 1).
OutputY=1
SoY = 1 if A =B = 0

A= 0 a,(P) (P) B0

B= 0
2.9.6(c):A = 1,
Output = Von = 1 (C-1060)Fig.

Q, (N) B=1: P-MOSFETSi.e. , and Q, wil be

With A= 1,
4.
B= 1 both and Q, will
B=0 *****.. With A= N-MOSFETS i.e. Q
Q, (N) boththe
OFF and
ON. of this mode
is shown in
(C-1059) Fig. 2.9.6(a) : A= B= 0 equivalent circuit
The
With A=0and B=1: Fig.2.9.6(d). +VDD
2
continue to be ON and
With A= 0and B = 1,Q, will and
But O, will now turn OFF
Q, continues to be OFF.
Q, willbe turned ON. A=1 0-Q,(P)
this mode is shown in
The equivalent circuit of output Y= + Von i.e.
Fig. 2.9.6(b) which shows that Output Y=0

logic 1.
So Y= 1 ifA = 0and B = 1.
otVoD
B=1 0
Q, (P)
A=0:
{a,(P)
(d) A = 1, B = 1
+Output Y = 1 Equivalent circuit
(G-1060) Fig. 2.9.6:
(LOW).
Q, (N)
It shows that output Y= 0
So Y =0ifA = B= 1.
the two input
Table 2.9.2 shows the truth table of
B=1
Qy (N)

NAND gate.
(b) A = , B = 1 Truth Table :
(C-1059) Fig. 2.9.6: Equivalent circuits Table 2.9.2: Truth Table of aCMOS NAND gate

3 With A= 1 and B=0: nputs Transistors

With A = 1, Q, will be turned OFF and Q, will turn Output Y
ON.
be
And with B = 0, Q, will be turned ON and Q, will ON
0 ON OFF OFF 1

turned OFF. 0 ON OFF OFF ON 1

2.9.6(c), the
As seen from the equivalent circuit of Fig. 1 OFF ON ON OFF
output Y= + Von (logic 1).
1 1 OFF OFF ON ON
So Y=1 ifA =1 and B= 0.
Tech Knowledge
PubIicatiDns
 DSD (Sem. III / E&Tc / MU) 2-21 Logic Families
2.9.4 CMOS Series : 2 High fan out (typically 50).
The popular CMOS series are 4000/14000 series, 74C
3 High noise margin for higher values of Vn
ceries, 74 HC/HCT (High speed CMOS), 74 AC/ACT 4. Capable of working over a wide range of supply
(Advanced CMOS). voltage.
5 Switching speeds comparable to those of TTL.
2.10 CMOS Characteristics:
6. High packaging density since (more devices can
MU: May 12 be accommodated in the same space) MOS
University Questions devices need less space.
Q.1 What are the salient features of CMOS logic 2.10.2 Disadvantages of CMOS:
family ? MU: Dec. 14
(May 12, 5 Marks)
Althe important University Questions
characteristics of CMOS logic family
are listed in Table 2.10.1,
Q.1 Give the advantage and disadvantage of CMOS
Table 2.10.1 :Important parameters of CMOS logic family family. (Dec. 14, 5 Marks)
1 Propagation delays longer than those of TTL
Sr. Parameter (25 to 100 nS).
CMOS
No.
2 Slower than TTL.
VIH (min) 3.5 V (Vnn = 5 V)
1 3. . CMOS ICs can get damaged due to static
2 VIL (max) 1.5 V charge.
4 Latch ups can take place which can damage the
3 VOH (min) 4.95 V
device.
4 VoL (max) 0.05 V Need protection circuitry.
5.

5 High level noise VNH=1.45 V 2.11 Interfacing:

margin
VaI =1.45 V The meaning of word interfacingis to connect one or
6 Low level noise margin
more outputs of one system to the one or more
7 Noise immunity Better than TTL
inputs of another system or circuits which have
different electrical characteristics.
8 Propagation delay 105 nS
(Metal gate CMOS) If the electrical characteristics of the twO circuits or
systems are different then we cannot have a direct
9 Switching speed Less than TTL.
connection between them.
10. Power dissipation per P, = 0.1 mN. Hence So an "interface" circuit is required to be inserted
gate. used for battery backup between the "driver" circuit and the "load" circuit as
applications
shown in Fig. 2.11.1.
11. Speed power product. 10.5 pJ Driver Load
Syster InterfaCe system
12. Fan out Typically 50.
Flexible from 3 V to 15 V (C-1067) Fig. 2.11.1: Interfacing between two different
13. Power supply voltage
systems

2.10.1 Advantages of CMOS: MU: Dec. 14 The task of the interface circuit is to accept the
output of the driver circuit and "condition" it so that
|UniversityQuestions it becomes compatible with the load circuit.
Q.1 Give the advantage and disadvantage of CMOS ICs from the same family are designed in such a way
family (Dec. 14, 5 Marks) that they can be connected together without any
1 Low power dissipation. special considerations.
TechKnouledge
 Logic Fami
requiredif
SF DSD (Sem. II/E&Tc /MU) resistance is
not
ACT
the CMO
2-22 family,
dirbeectcaluys.e h
74
up HCT or
Such apull to 74
But when we connect the output of one type of IC to belongs accept the TTL outputs
gate Compatible CMOS
the input of another type of IC, we have to be
concerned about the differences related to the
these
families can

other
are TTL
wordsthey Externalpullup
families,
resistor
voltage and current levels of both the ICs. + 5V
The pull up resst
2.11.1 TTL to CMOS Interfacing : raises the output
level of
MU:Dec. 08, May 10
S10k2 TTL Ingalth e.
about +5V,
HÊGH state
University Questions A

Q.1 Explain interfacing of TTL and CMOS logic. CMOS

TTL
families. (Dec. 08, 6 Marks, May 10, 8 Marks)
TTLdriving CMos
2.11.2:
When we interface different types of ICs, it is (C-1068)Fig. Interface :
to TTL
necessary to check whether the driving IC is capable 2.11.2 CMOS MU: Dec. 08, May 10
of meeting the current and voltage requirements of
interfacing of TTL May CMOS
University Questions and 1ogic
the load IC or not. Explain 10, 8 Markei
O.1
families. (Dec.08, 6 Marks,
For example Table 2.11.1 reveals that the output of CMOS
current capability of TTL ICs is much higher than the Before we
considerthe problem
output characteristice
interfacing
us review the
input current values of CMOS ICs. Therefore there is with TTL, let
different states.
no problem for a TTL IC to drive CMOS as
far as CMOS in two
the equivalent output circuit of.
current is concerned. Fig. 2.11.3(a) shows HIGH state output,
whereae
CMOS inverter in the
But there is a problem when we compare the voltage equivalent in the LOW state
levels of TTL and CMOS. Because VOH (minl of a TTL Fig. 2.11.3(b) shows its
output.
series is very low as compared with V,H (mioh required +Vpp
HIGH STATE
for the CMOS series like 400B, 74 HC or 74 AC.
In such situations, something has to done to increase LOH
the level of TTL Output voltage to an acceptable
voltage level for CMOS. VoH
(C-6353) Table 2.11,1:Input output currents for standard
devices with a supply voltage of 5 V
CMOS TTL PMOS Q, ON
Parameter NMOS Q, OFF
4000 B4HCIHCT 7 4 4 LS 74AS
(a) Equivalent circuit of a CMOS inverter for HIGH state
IH(ma) 1pA 1 pA 40 uA 20 uA 20 A

IL(max) 1pA 1.6 mA 0.4 mA 0.5 mA

LOH(max) 0.4 mA 4 mA 0.4 mA 0.4 mA 2 mA

LOW STATE
IoL(max) 0.4 mA 4 mA 16 mA 8 mA 20 mA
+Vpo
The situation in which a TTL IC is driving CMOS is A IoL
shown in Fig. 2.11.2.
Note the presence of pullup resistor at the output of VoL
the TTL gate. Due to this resistor the TTL output will
riseto approximately + 5 Vin its HIGH state.
PMOS Q, OFF
This will provide the sufficient voltage level at the NMOS Q, ON
input of the CMOS gate. (b) Equivalent circuit of a
CMOS inverter for low state
(C-1071) Fig. 2.11.3
 Logic Families
DSD (Sem. III /E&Tc/MU) 2-23

Equivalent circuit in HIGH state : Table 2.12.1 : Comparison of CMOS and TTL
Sr.
In the HIGH state of output, the P-channel MOSFET Parameter CMOS TTL
No.
o will be ON, so it has been replaced by the ON 1. Device used N-channel Bipolar
ctate resistance RON: Whereas the N-channel MOSFET MOSFET and junction
will be OFF. So it has been replaced by an open P-channel transistor
MOSFET
Switch as shown in Fig. 2.11.3(a). 2 ViH (min) 3.5 V 2V

Therefore the CMOS output is equivalent to a V,DD (Vop =5 )

sOurce with asOurce resistance of R.ON 3 VL (max) 1.5 V 0.8 V

4 NoH (min) 4.95 V) 2.7 V

Equivalent circuitin LOW state :
0.05 V' 0.4 V

The eguivalent circuit of a CMOS inverter in its low

5.

6
VoL(max)
High level noise VMH =1.45 V 0.4 V

ctate of output is shown in Fig. 2.11.3(b). In this state, margin

7. Low level noise VNI =1.45 V 0.4 V
theP-MOSFET Q, 0S OFF and represented by an open
margin
switch. Better than Less than
8. Noise immunity
TTL CMOS
Whereas the N-channel MOSFET i ON. So it has
105 nS (Metal 10 nS.
been replaced by resistance Ro: So the CMOS Propagation
delay gate CMOS) (Standard
inverter now acts as a low resistance connected to TTL)
ground and sinks current. Switching Less than Faster than
10.
TTL. CMOS
speed
Table 2.11.2 presents the various voltage and current P, =0.1 mW. 10mW
11. Power
levels for the standard CMOS (4000B) and TTL (74) dissipation per Hence used

series for comparison. gate. for battery

backup
(C-6259) Table 2,11.2
applications
Speed power 10.5 pJ 100 pJ
Parameters for drvingparemeters for the oad 12.
Sr. gate (CMOS) of 4o00 gate TTL)of 74 8erles product.
No B serles P, does not
Dependence of P, increases
VOH(min) = 4.95V 13.
1. VIH(min) =2V Po on frequency with increase depend on
2. VOL(max) =0.05V VL (max) = 0.8V in frequency. frequency.
3. 'OH(max) = 0.4mA VIH(ma) =40uA 14. Fan out Typically 50. 10

4. 'OL(max) = 0.4mA IL(max) = 1.6mA 15. Unconnected Unused inputs Inputs can
should be remain
inputs
For low For high returned to floating. The
state output
state output GND or Vop floating inputs
They should are treated as
2.12 Comparisons : never be left logic 1s.
4

floating.
2.12.1 Comparison of CMOS and TTL: Less than
16. Component More than TTL
CMOS since
MU: Dec. 13, Dec. 15, Dec. 17, May 18 density since
MOSFETS BJT needs
University Questions need smaller more space.
space while
Q.1Compare TTL with CMOSlogic famílles.
fabricating an
(Dec. 13, Dec. 15, Dec. 17, May 18, 5 Marks) IC.

TechKaouledg
 CMOSlogicinverter.
DSD (Sem. II /E&Tc / MU) 2-24 application of
the while using
Sr.
Parameter CMOS TTL
Q. 7
State
the
precautionstaken CMOS
No.
Q. 8
What are
17. Operating areas MOSFETS are Transistors ICs ? disadvantages of
operated as are operated advantages and TTL
switches. i.e. in saturation or Mention the families.
Q.9 ECL IC
in the ohmic cut off regions. CMOSand gates,
region or cut characteristicsoflogic
off region. Q. 10 Listanyfour CMOS logic.
and
Flexible from Fixed equal to between TTL
18. Power supply Compare
Q. 11 scale of integration,
voltage 3V to 15 V. 5 V. accordingtotheir
ClassifytheIC
Q. 12 LSI,VLSI.
Review Questions terms SSI, MS,
Q. 13 Explain
the
TTL.
Explain what is meant by
Q. 1 Which are the different logic families ? Write their Q. 14 input TTL NAND
circuit diagram of two
characteristics. Q. 15 Draw the function of each component
explain the
gate and
Q. 2 What is passive pull-up load and active pull-up
it.
load ?
High-Threshole
Explain with diagram the working of
Q.3 Give the advantages of active pull-up over passive Q. 16 advantage of HTL over DTL
Logic (HTL). State the
pull-up.
NAND gate in tr.
Q. 4 Explain the use of multi-emitter inputs. Explain briefly the operation of TTL
Q.17
state output configurations.
Q. 5 Define the following terms regarding a logic family :
families
Q. 18 Give the important characteristics of logic
1. Noise margin
and explain their importance.
2. Propagation delay
Q.6 Explain the features of complementary symmetry
logic (CMOS).