ADS1113-Q1, ADS1114-Q1, ADS1115-Q1

SBAS563E – DECEMBER 2011 – REVISED DECEMBER 2022

ADS111x-Q1 Automotive, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs

With Internal Reference, Oscillator, and Programmable Comparator

1 Features 3 Description
• AEC-Q100 qualified for automotive applications: The ADS1113-Q1, ADS1114-Q1, and ADS1115-Q1
– Temperature grade 1: –40°C to +125°C, TA devices (ADS111x-Q1) are precision, low-power,
• Functional Safety-Capable 16-bit, I2C-compatible, analog-to-digital converters
– Documentation available to aid functional safety (ADCs) offered in VSSOP-10 and UQFN-10
system design packages. The ADS111x-Q1 devices incorporate a
• Wide supply range: 2.0 V to 5.5 V low-drift voltage reference and an oscillator. The
• Low current consumption: ADS1114-Q1 and ADS1115-Q1 also incorporate a
– 150 μA (continuous-conversion mode) programmable gain amplifier (PGA) and a digital
• Programmable data rate: comparator. These features, along with a wide
operating supply range, make the ADS111x-Q1 well
– 8 SPS to 860 SPS
suited for power- and space-constrained, sensor
• Single-cycle settling
measurement applications.
• Internal low-drift voltage reference
• Internal oscillator The ADS111x-Q1 perform conversions at data rates
• I2C interface: Four pin-selectable addresses up to 860 samples per second (SPS). The PGA offers
• Family of devices: input ranges from ±256 mV to ±6.144 V, allowing
– ADS1113-Q1: 1 single-ended or differential precise large- and small-signal measurements. The
input ADS1115-Q1 features an input multiplexer (MUX)
– ADS1114-Q1: 1 single-ended or differential that allows two differential or four single-ended
input with comparator and PGA input measurements. Use the digital comparator in
– ADS1115-Q1: 4 single-ended or 2 differential the ADS1114-Q1 and ADS1115-Q1 for under- and
inputs with comparator and PGA overvoltage detection.

2 Applications Package Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Camera modules without processing
DGS (VSSOP, 10) 3.00 mm × 3.00 mm
• Automotive center information displays ADS111x-Q1
• Automotive cluster displays NKS (UQFN, 10) 1.60 mm × 2.00 mm
• General-purpose voltage and current monitoring (1) For all available packages, see the package option
addendum at the end of the data sheet.

Table 3-1. Device Information

PART NUMBER INPUT CHANNELS FEATURES(1)
ADS1113-Q1 1 DE (1 SE) —
ADS1114-Q1 1 DE (1 SE) PGA, comparator
ADS1115-Q1 2 DE (4 SE) PGA, comparator

(1) See the Device Comparison Table for details.

VDD VDD VDD

Comparator Comparator
Voltage Voltage ALERT/ Voltage ALERT/
Reference Reference RDY Reference RDY

ADDR ADDR AIN0 ADDR

AIN0 16-Bit AIN0 16-Bit 16-Bit

I2C PGA  I2C AIN1 PGA  I2C
Interface SCL Interface SCL MUX Interface SCL
AIN1 ADC AIN1 ADC AIN2 ADC
SDA SDA SDA
AIN3
Oscillator Oscillator Oscillator
ADS1113-Q1 ADS1114-Q1 ADS1115-Q1

GND GND GND

Simplified Block Diagrams

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS1113-Q1, ADS1114-Q1, ADS1115-Q1
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Table of Contents
1 Features............................................................................1 8.3 Feature Description...................................................15
2 Applications..................................................................... 1 8.4 Device Functional Modes..........................................20
3 Description.......................................................................1 8.5 Programming............................................................ 21
4 Revision History.............................................................. 2 8.6 Register Map.............................................................26
5 Pin Configuration and Functions...................................4 9 Application and Implementation.................................. 30
6 Specifications.................................................................. 5 9.1 Application Information............................................. 30
6.1 Absolute Maximum Ratings........................................ 5 9.2 Typical Application.................................................... 35
6.2 ESD Ratings............................................................... 5 9.3 Power Supply Recommendations.............................39
6.3 Recommended Operating Conditions.........................5 9.4 Layout....................................................................... 40
6.4 Thermal Information....................................................6 10 Device and Documentation Support..........................42
6.5 Electrical Characteristics.............................................7 10.1 Documentation Support.......................................... 42
6.6 Timing Requirements: I2C...........................................8 10.2 Receiving Notification of Documentation Updates..42
6.7 Timing Diagram...........................................................8 10.3 Support Resources................................................. 42
6.8 Typical Characteristics................................................ 9 10.4 Trademarks............................................................. 42
7 Parameter Measurement Information.......................... 13 10.5 Electrostatic Discharge Caution..............................42
7.1 Noise Performance................................................... 13 10.6 Glossary..................................................................42
8 Detailed Description......................................................14 11 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 14 Information.................................................................... 42
8.2 Functional Block Diagrams....................................... 14

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2018) to Revision E (December 2022) Page
• Changed all instances of legacy terminology to controller and target where I2C is mentioned.......................... 1
• Added Functional Safety-Capable bullets and device family information to Features section, moved ESD
classification information from Features section to ESD Ratings table.............................................................. 1
• Changed applications in Application section...................................................................................................... 1
• Added NKS (UQFN) package and Device Information table and deleted last paragraph from Description
section................................................................................................................................................................ 1
• Added NKS package to Pin Configuration and Functions section and changed Pin Functions table................ 4
• Changed free-air to ambient in condition statement of Absolute Maximum Ratings table................................. 5
• Added ESD classification levels and NKS package to ESD Ratings table......................................................... 5
• Added NKS package to Thermal Information table............................................................................................ 6
• Changed unit of common-mode input impedance (FSR = ±0.512 V, FSR = ±0.256 V) parameter from MΩ to
kΩ in Electrical Characteristics table.................................................................................................................. 7
• Changed Y-axis unit of Total Error vs Input Signal figure from μV to mV in Typical Characteristics section...... 9
• Added additional information to last paragraph in Multiplexer section..............................................................15
• Added additional information to Voltage Reference section............................................................................. 17
• Moved Figure 8-7 from Conversion Ready Pin section to Digital Comparator section.....................................18
• Changed bit setting notation from hexadecimal to binary where beneficial for clarity throughout Register Map
section.............................................................................................................................................................. 26
• Added Config Register - ADS1113-Q1, Config Register - ADS1114-Q1, and Config Register - ADS1115-Q1
and changed bit descriptions in Config Register Field Descriptions table in Config Register section.............. 27
• Changed first paragraph in Lo-threh and Hi_thresh Registers section.............................................................29
• Changed Unused Inputs and Outputs section.................................................................................................. 31
• Added layout example for NKS package in Layout Example section............................................................... 41

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Changes from Revision C (December 2016) to Revision D (January 2018) Page

• Changed Digital input voltage max value from VDD + 0.3 V to 5.5 V in Absolute Maximum Ratings table....... 5
• Deleted values for ADS111xB-Q1 device in Thermal Information table; thermal values now same for all
devices................................................................................................................................................................6
• Added "over temperature" to Offset drift parameter for clarity............................................................................ 7
• Added Long-term Offset drift parameter in Electrical Characteristics table........................................................ 7
• Added "over temperature" to Gain drift parameter for clarity..............................................................................7
• Added Long-term gain drift parameter in Electrical Characteristics table...........................................................7
• Changed VIH parameter max value from VDD to 5.5 V in Electrical Characteristics table................................. 7
• Added Output Data Rate and Conversion Time section for clarity....................................................................17
• Changed Conversion Ready Pin section for clarity.......................................................................................... 19
• Changed Figure 28, ALERT Pin Timing Diagram for clarity............................................................................. 19
• Changed Typical Connections of the ADS1115-Q1 figure for clarity.................................................................30
• Changed the resistor values in Figure 43, Basic Hardware Configuration, from 10 Ω to 10 kΩ.......................34

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Device Comparison Table

MAXIMUM SAMPLE INPUT CHANNELS
RESOLUTION SPECIAL
DEVICE RATE Differential PGA INTERFACE
(Bits) FEATURES
(SPS) (Single-Ended)
ADS1115-Q1 16 860 2 (4) Yes I2C Comparator
ADS1114-Q1 16 860 1 (1) Yes I2C Comparator
ADS1113-Q1 16 860 1 (1) No I2C None
ADS1015-Q1 12 3300 2 (4) Yes I2C Comparator
ADS1014-Q1 12 3300 1 (1) Yes I2C Comparator
ADS1013-Q1 12 3300 1 (1) No I2C None
ADS1118-Q1 16 860 2 (4) Yes SPI Temperature sensor
ADS1018-Q1 12 3300 2 (4) Yes SPI Temperature sensor

5 Pin Configuration and Functions

SCL
10

ADDR 1 9 SDA
ADDR 1 10 SCL

ALERT/RDY 2 9 SDA
ALERT/RDY 2 8 VDD
GND 3 8 VDD

GND 3 7 AIN3
AIN0 4 7 AIN3

AIN1 5 6 AIN2
AIN0 4 6 AIN2
5

Not to scale Not to scale

AIN1

Figure 5-1. NKS Package, Figure 5-2. DGS Package,

10-Pin UQFN (Top View) 10-Pin VSSOP (Top View)

Table 5-1. Pin Functions

PIN(1)
NAME ADS1113-Q1 ADS1114-Q1 ADS1115-Q1 TYPE DESCRIPTION
ADDR 1 1 1 Digital input I2C target address select
AIN0 4 4 4 Analog input Analog input 0
AIN1 5 5 5 Analog input Analog input 1
AIN2 — — 6 Analog input Analog input 2 (ADS1115-Q1 only)
AIN3 — — 7 Analog input Analog input 3 (ADS1115-Q1 only)
Comparator output or conversion ready (ADS1114-Q1 and ADS1115-Q1 only).
ALERT/RDY — 2 2 Digital output
Open-drain output. Connect to VDD using a pullup resistor.
GND 3 3 3 Analog Ground
NC 2, 6, 7 6, 7 — — No connect. Leave pin floating or connect to GND.
SCL 10 10 10 Digital input Serial clock input. Connect to VDD using a pullup resistor.
SDA 9 9 9 Digital I/O Serial data input and output. Connect to VDD using a pullup resistor.
VDD 8 8 8 Analog Power supply. Connect a 0.1-μF, power-supply decoupling capacitor to GND.

(1) See the Unused Inputs and Outputs section for unused pin connections.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power-supply voltage VDD to GND –0.3 7 V
Analog input voltage AIN0, AIN1, AIN2, AIN3 GND – 0.3 VDD + 0.3 V
Digital input voltage SDA, SCL, ADDR, ALERT/RDY GND – 0.3 5.5 V
Input current, continuous Any pin except power supply pins –10 10 mA
Operating ambient, TA –40 125
Temperature Junction, TJ –40 150 °C
Storage, Tstg –60 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1)
±2000
HBM ESD classification level 2
Electrostatic Corner pins
V(ESD) Charged-device model (CDM), V
discharge (DGS package: Pins 1, 5, 6, and 10) ±750
per AEC Q100-011 (NKS package: Pins 1, 4, 5, 6, 9, and 10)
CDM ESD classification level C4B
All other pins ±500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
POWER SUPPLY
Power supply (VDD to GND) 2 5.5 V
ANALOG INPUTS(1)
FSR Full-scale input voltage range(2) (VIN = V(AINP) – V(AINN)) ±0.256 ±6.144 V
V(AINx) Absolute input voltage GND VDD V
DIGITAL INPUTS
VDIG Digital input voltage GND 5.5 V
TEMPERATURE
TA Operating ambient temperature –40 125 °C

(1) AINP and AINN denote the selected positive and negative inputs. AINx denotes one of the four available analog inputs.
(2) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to the analog inputs of
the device. See Table 8-1 for more information.

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6.4 Thermal Information

DGS (VSSOP) NKS (UQFN)
THERMAL METRIC(1) UNIT
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 170.9 126.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.0 52.0 °C/W
RθJB Junction-to-board thermal resistance 91.2 60.6 °C/W
ψJT Junction-to-top characterization parameter 8.5 1.1 °C/W
ψJB Junction-to-board characterization parameter 89.8 60.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.

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6.5 Electrical Characteristics

at VDD = 3.3 V, data rate = 8 SPS, and full-scale input voltage range (FSR) = ±2.048 V (unless otherwise noted); maximum
and minimum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
FSR = ±6.144 V(1) 10
FSR = ±4.096 V(1), FSR = ±2.048 V 6 MΩ
Common-mode input impedance
FSR = ±1.024 V 3
FSR = ±0.512 V, FSR = ±0.256 V 100 kΩ
FSR = ±6.144 V(1) 22
FSR = ±4.096 V(1) 15
MΩ
Differential input impedance FSR = ±2.048 V 4.9
FSR = ±1.024 V 2.4
FSR = ±0.512 V, ±0.256 V 710 kΩ
SYSTEM PERFORMANCE
Resolution (no missing codes) 16 Bits
DR Data rate 8, 16, 32, 64, 128, 250, 475, 860 SPS
Data rate variation All data rates –10% 10%
Output noise See Noise Performance section
INL Integral nonlinearity DR = 8 SPS, FSR = ±2.048 V(2) 1 LSB
FSR = ±2.048 V, differential inputs –3 ±1 3
Offset error LSB
FSR = ±2.048 V, single-ended inputs ±3
Offset drift over temperature FSR = ±2.048 V 0.005 LSB/°C
FSR = ±2.048 V, TA = 125°C,
Long-term Offset drift ±1 LSB
1000 hrs
Offset power-supply rejection FSR = ±2.048 V, DC supply variation 1 LSB/V
Offset channel match Match between any two inputs 3 LSB
Gain error(3) FSR = ±2.048 V, TA = 25°C 0.01% 0.15%
FSR = ±0.256 V 7
Gain drift over temperature(3) FSR = ±2.048 V 5 40 ppm/°C
FSR = ±6.144 V(1) 5
FSR = ±2.048 V, TA = 125°C,
Long-term gain drift(3) ±0.05 %
1000 hrs
Gain power-supply rejection 80 ppm/V
Gain match(3) Match between any two gains 0.02% 0.1%
Gain channel match Match between any two inputs 0.05% 0.1%
At DC, FSR = ±0.256 V 105
At DC, FSR = ±2.048 V 100
CMRR Common-mode rejection ratio At DC, FSR = ±6.144 V(1) 90 dB
fCM = 60 Hz, DR = 8 SPS 105
fCM = 50 Hz, DR = 8 SPS 105
DIGITAL INPUT/OUTPUT
VIH High-level input voltage 0.7 VDD 5.5 V
VIL Low-level input voltage GND 0.3 VDD V
VOL Low-level output voltage IOL = 3 mA GND 0.15 0.4 V
Input leakage current GND < VDIG < VDD –10 10 µA

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6.5 Electrical Characteristics (continued)

at VDD = 3.3 V, data rate = 8 SPS, and full-scale input voltage range (FSR) = ±2.048 V (unless otherwise noted); maximum
and minimum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER-SUPPLY
TA = 25°C 0.5 2
Power-down
5
IVDD Supply current µA
TA = 25°C 150 200
Operating
300
VDD = 5.0 V 0.9
PD Power dissipation VDD = 3.3 V 0.5 mW
VDD = 2.0 V 0.3

(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to the analog inputs of
the device. See Table 8-1 for more information.
(2) Best-fit INL; covers 99% of full-scale.
(3) Includes all errors from onboard PGA and voltage reference.

6.6 Timing Requirements: I2C

over operating ambient temperature range and VDD = 2.0 V to 5.5 V (unless otherwise noted)
FAST MODE HIGH-SPEED MODE
MIN MAX MIN MAX UNIT
fSCL SCL clock frequency 0.01 0.4 0.01 3.4 MHz
Bus free time between START and STOP
tBUF 600 160 ns
condition
Hold time after repeated START condition.
tHDSTA 600 160 ns
After this period, the first clock is generated.
tSUSTA Setup time for a repeated START condition 600 160 ns
tSUSTO Setup time for STOP condition 600 160 ns
tHDDAT Data hold time 0 0 ns
tSUDAT Data setup time 100 10 ns
tLOW Low period of the SCL clock pin 1300 160 ns
tHIGH High period for the SCL clock pin 600 60 ns
tF Rise time for both SDA and SCL signals(1) 300 160 ns
tR Fall time for both SDA and SCL signals(1) 300 160 ns

(1) For high-speed mode maximum values, the capacitive load on the bus line must not exceed 400 pF.

6.7 Timing Diagram

t LOW
tR tF t HDSTA

SCL

t HDSTA t HIGH t SUSTA t SUSTO

t HDDAT t SUDAT

SDA
t BUF

P S S P

Figure 6-1. I2C Interface Timing

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6.8 Typical Characteristics

at TA = 25°C, VDD = 3.3 V, FSR = ±2.048 V, DR = 8 SPS (unless otherwise noted)

300 5.0
4.5
250
4.0

Power-down Current (µA)

Operating Current (µA)

VDD = 5 V
3.5
200
3.0
150 2.5
VDD = 3.3 V
VDD = 2 V 2.0
100 VDD = 5 V
1.5
VDD = 3.3 V
50 1.0
0.5
VDD = 2 V
0 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

Figure 6-2. Operating Current vs Temperature Figure 6-3. Power-Down Current vs Temperature
150 60
FSR = ±4.096 V FSR = ±1.024 V
100 50
FSR = ±2.048 V FSR = ±0.512 V
50 VDD = 5 V
VDD = 2 V 40
Offset Voltage (µV)
Offset Error (µV)

0
30
-50 VDD = 4 V
20
-100 VDD = 3 V
10
-150
0
-200 VDD = 2 V
VDD = 5 V
-250 -10

-300 -20
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

Figure 6-4. Single-Ended Offset Error vs Temperature Figure 6-5. Differential Offset vs Temperature
0.05 0.15
FSR = ±0.256 V
0.04
0.10
0.03
FSR = ±0.512 V
0.02 0.05
Gain Error (%)

Gain Error (%)

FSR = ±256 mV
0.01
FSR = ±1.024 V, ±2.048 V, 0
0 FSR = ±2.048 V
±4.096 V, and ±6.144 V
-0.01 -0.05

-0.02
-0.10
-0.03

-0.04 -0.15
-40 -20 0 20 40 60 80 100 120 140 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature (°C) Supply Voltage (V)

Figure 6-6. Gain Error vs Temperature Figure 6-7. Gain Error vs Supply Voltage

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6.8 Typical Characteristics (continued)

at TA = 25°C, VDD = 3.3 V, FSR = ±2.048 V, DR = 8 SPS (unless otherwise noted)

60 60

50 40
Integral Nonlinearity (µV)

Integral Nonlinearity (µV)

+125°C
40 20
-40°C
FSR = ±6.144 V
30 0
FSR = ±0.512 V, ±0.256 V
FSR = ±2.048 V
20 -20
+25°C
10 -40

0 -60
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0
Supply Voltage (V) Input Signal (V)
VDD = 3.3 V, FSR = ±2.048 V, DR = 8 SPS, best fit
Figure 6-8. INL vs Supply Voltage Figure 6-9. INL vs Input Signal
60 60

40 40
Integral Nonlinearity (µV)

Integral Nonlinearity (µV)

+125°C
20 20
-40°C TA = -40°C

0 0
+25°C TA = +125°C TA = +25°C
-20 -20

-40 -40

-60 -60
-0.5 -0.375 -0.250 -0.125 0 0.125 0.250 0.375 0.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0
Input Signal (V) Input Voltage (V)
VDD = 3.3 V, FSR = ±0.512 V, DR = 8 SPS, best fit VDD = 5 V, FSR = ±2.048 V, DR = 8 SPS, best fit
Figure 6-10. INL vs Input Signal Figure 6-11. INL vs Input Signal
60 140

40 120
Integral Nonlinearity (µV)

Integral Nonlinearity (µV)

TA = +25°C 100
20
TA = -40°C
80
0 VDD = 2 V
60
TA = +125°C
-20 VDD = 5 V
40

-40 20
VDD = 3.3 V
-60 0
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -60 -40 -20 0 20 40 60 80 100 120 140
Input Voltage (V) Temperature (°C)
VDD = 5 V, FSR = ±0.512 V, DR = 8 SPS, best fit
Figure 6-12. INL vs Input Signal Figure 6-13. INL vs Temperature

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6.8 Typical Characteristics (continued)

at TA = 25°C, VDD = 3.3 V, FSR = ±2.048 V, DR = 8 SPS (unless otherwise noted)

12 35
FSR = ±2.048 V
10 30
860 SPS
25
RMS Noise (µV)

RMS Noise (µV)

8
DR = 860 SPS
20
6
DR = 128 SPS 15
4 128 SPS
DR = 8 SPS 10

2 5
8 SPS
0 0
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V) Supply Voltage (V)
FSR = ±0.512 V FSR = ±2.048 V
Figure 6-14. Noise vs Input Signal Figure 6-15. Noise vs Supply Voltage
10 30
9
25
8
Number of Occurrences

7
RMS Noise (µV)

20
6
5 15
4
10
3
2 5
1
0 0
-40 -20 0 20 40 60 80 100 120 140
0

0.020

0.040
-0.010
-0.005

0.005
0.010
0.015

0.025
0.030
0.035

0.045
0.050
0.055
0.060
0.065
0.070
0.075
0.080
0.085
0.090
Temperature (°C)
FSR = ±2.048 V, DR = 8 SPS Gain Error (%)
FSR = ±2.048 V, 185 units
Figure 6-16. Noise vs Temperature Figure 6-17. Gain Error Histogram
160 4
140 3
Number of Occurrences

120 2
Total Error (mV)

100 1
80 0
60 -1
40 -2

20 -3

0 -4
-3 -2 -1 0 1 2 3 -2.048 -1.024 0 1.024 2.048
Offset (LSBs) Input Signal (V)
FSR = ±2.048 V, 185 units
Differential inputs; includes noise, offset and gain error
Figure 6-18. Offset Histogram
Figure 6-19. Total Error vs Input Signal

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6.8 Typical Characteristics (continued)

at TA = 25°C, VDD = 3.3 V, FSR = ±2.048 V, DR = 8 SPS (unless otherwise noted)

4 0

3 -10
VDD = 5 V
2 -20
Data Rate Error (%)

1 -30

Gain (dB)
VDD = 3.3 V
0 -40

-1 -50

-2 -60
VDD = 2 V
-3 -70

-4 -80
-40 -20 0 20 40 60 80 100 120 140 1 10 100 1k 10k
Temperature (°C) Input Frequency (Hz)
DR = 8 SPS
Figure 6-20. Data Rate vs Temperature Figure 6-21. Digital Filter Frequency Response

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7 Parameter Measurement Information

7.1 Noise Performance
Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input
signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and
decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between
modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and
thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the
input-referred noise drops when reducing the output data rate because more samples of the internal modulator
are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is
particularly useful when measuring low-level signals.
Table 7-1 and Table 7-2 summarize the ADS111x-Q1 noise performance. Data are representative of typical noise
performance at TA = 25°C with the inputs shorted together externally. Table 7-1 shows the input-referred noise
in units of μVRMS for the conditions shown. The µVPP values are shown in parenthesis. Table 7-2 shows the
effective resolution calculated from μVRMS values using Equation 1. The noise-free resolution calculated from
peak-to-peak noise values using Equation 2 are shown in parenthesis.

Effective Resolution = ln (FSR / VRMS-Noise) / ln(2) (1)

Noise-Free Resolution = ln (FSR / VPP-Noise) / ln(2) (2)

Table 7-1. Noise in μVRMS (μVPP) at VDD = 3.3 V
FSR (Full-Scale Range)
DATA RATE
(SPS) ±6.144 V ±4.096 V ±2.048 V ±1.024 V ±0.512 V ±0.256 V
8 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
16 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
32 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
64 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
128 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (12.35)
250 187.5 (252.09) 125 (148.28) 62.5 (84.03) 31.25 (39.54) 15.62 (16.06) 7.81 (18.53)
475 187.5 (266.92) 125 (227.38) 62.5 (79.08) 31.25 (56.84) 15.62 (32.13) 7.81 (25.95)
860 187.5 (430.06) 125 (266.93) 62.5 (118.63) 31.25 (64.26) 15.62 (40.78) 7.81 (35.83)

Table 7-2. Effective Resolution from RMS Noise (Noise-Free Resolution from Peak-to-Peak Noise) at
VDD = 3.3 V
FSR (Full-Scale Range)
DATA RATE
(SPS) ±6.144 V ±4.096 V ±2.048 V ±1.024 V ±0.512 V ±0.256 V
8 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
16 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
32 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
64 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
128 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.33)
250 16 (15.57) 16 (15.75) 16 (15.57) 16 (15.66) 16 (15.96) 16 (14.75)
475 16 (15.49) 16 (15.13) 16 (15.66) 16 (15.13) 16 (14.95) 16 (14.26)
860 16 (14.8) 16 (14.9) 16 (15.07) 16 (14.95) 16 (14.61) 16 (13.8)

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8 Detailed Description
8.1 Overview
The ADS111x-Q1 are very small, low-power, 16-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The
ADS111x-Q1 consist of a ΔΣ ADC core with an internal voltage reference, a clock oscillator, and an I2C interface.
The ADS1114-Q1 and ADS1115-Q1 also integrate a programmable gain amplifier (PGA) and a programmable
digital comparator. Figure 8-1, Figure 8-2, and Figure 8-3 show the functional block diagrams of the ADS1115-
Q1, ADS1114-Q1, and ADS1113-Q1, respectively.
The ADS111x-Q1 ADC core measures a differential signal, VIN, that is the difference of V(AINP) and V(AINN).
The converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This
architecture results in a very strong attenuation of any common-mode signals. Input signals are compared to the
internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a
code proportional to the input voltage.
The ADS111x-Q1 have two available conversion modes: single-shot and continuous-conversion. In single-shot
mode, the ADC performs one conversion of the input signal upon request, stores the conversion value to an
internal conversion register, and then enters a power-down state. This mode is intended to provide significant
power savings in systems that only require periodic conversions or when there are long idle periods between
conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as
soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed
data rate. Data can be read at any time and always reflect the most recent completed conversion.
8.2 Functional Block Diagrams
VDD

ADS1115-Q1 Comparator

Voltage ALERT/RDY
MUX Reference

AIN0
ADDR

AIN1 16-Bit
I2C

PGA SCL
ADC Interface
SDA
AIN2

Oscillator
AIN3

GND

Figure 8-1. ADS1115-Q1 Block Diagram

VDD VDD

ADS1114-Q1 Comparator ADS1113-Q1

Voltage ALERT/RDY Voltage

Reference Reference

ADDR ADDR
AIN0 AIN0
16-Bit
I2C 16-Bit
I2C
PGA SCL SCL
ADC Interface ADC Interface
AIN1 AIN1
SDA SDA

Oscillator Oscillator

GND GND

Figure 8-2. ADS1114-Q1 Block Diagram Figure 8-3. ADS1113-Q1 Block Diagram

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8.3 Feature Description

8.3.1 Multiplexer
The ADS1115-Q1 contains an input multiplexer (MUX), as shown in Figure 8-4. Either four single-ended or two
differential signals can be measured. Additionally, AIN0 and AIN1 can be measured differentially to AIN3. The
multiplexer is configured by bits MUX[2:0] in the Config register. When single-ended signals are measured, the
negative input of the ADC is internally connected to GND by a switch within the multiplexer.

VDD ADS1115-Q1

AIN0
VDD

GND
AINP
AIN1 AINN
VDD

GND
AIN2
VDD

GND
AIN3

GND

GND

Figure 8-4. Input Multiplexer

The ADS1113-Q1 and ADS1114-Q1 do not have an input multiplexer and can measure either one differential
signal or one single-ended signal. For single-ended measurements, connect the AIN1 pin to GND externally. In
subsequent sections of this data sheet, AINP refers to AIN0 and AINN refers to AIN1 for the ADS1113-Q1 and
ADS1114-Q1.
Electrostatic discharge (ESD) diodes connected to VDD and GND protect the ADS111x-Q1 analog inputs. Keep
the absolute voltage of any input within the range shown in Equation 3 to prevent the ESD diodes from turning
on.

GND – 0.3 V < V(AINX) < VDD + 0.3 V (3)

If the voltages on the input pins can potentially violate these conditions, use external Schottky diodes and series
resistors to limit the input current to safe values (see the Absolute Maximum Ratings table). Overdriving an input
on the ADS1115-Q1 can affect conversions taking place on other inputs. If overdriving an input is possible, clamp
the signal with external Schottky diodes.

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8.3.2 Analog Inputs

The ADS111x-Q1 use a switched-capacitor input stage where capacitors are continuously charged and then
discharged to measure the voltage between AINP and AINN. The frequency at which the input signal is sampled
is called the sampling frequency or the modulator frequency (fMOD). The ADS111x-Q1 has a 1-MHz internal
oscillator that is further divided by a factor of 4 to generate fMOD at 250 kHz. The capacitors used in this input
stage are small, and to external circuitry, the average loading appears resistive. Figure 8-5 shows this structure.
The capacitor values set the resistance and switching rate. Figure 8-6 shows the timing for the switches in
Figure 8-5. During the sampling phase, switches S1 are closed. This event charges CA1 to V(AINP), CA2 to V(AINN),
and CB to (V(AINP) – V(AINN)). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1 and
CA2 then discharge to approximately 0.7 V and CB discharges to 0 V. This charging draws a very small transient
current from the source driving the ADS111x-Q1 analog inputs. The average value of this current can be used to
calculate the effective impedance (Zeff), where Zeff = VIN / IAVERAGE.
0.7 V

CA1 ZCM
AINP 0.7 V Equivalent
S1 S2 Circuit AINP
CB
ZDIFF
S1 S2
AINN 0.7 V AINN

fMOD = 250 kHz ZCM

CA2

0.7 V

Figure 8-5. Simplified Analog Input Circuit

tSAMPLE
ON
S1
OFF

ON
S2
OFF

Figure 8-6. S1 and S2 Switch Timing

The common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and
AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance
changes depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In Figure
8-5, the common-mode input impedance is ZCM.
The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one
input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and
scales with the full-scale range. In Figure 8-5, the differential input impedance is ZDIFF.
Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance,
the ADS111x-Q1 input impedance can affect the measurement accuracy. For sources with high-output
impedance, buffering can be necessary. Active buffers introduce noise, and also introduce offset and gain errors.
Consider all of these factors in high-accuracy applications.
The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most
applications, this input impedance drift is negligible, and can be ignored.

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8.3.3 Full-Scale Range (FSR) and LSB Size

A programmable gain amplifier (PGA) is implemented before the ΔΣ ADC of the ADS1114-Q1 and ADS1115-Q1.
The full-scale range is configured by bits PGA[2:0] in the Config register and can be set to ±6.144 V, ±4.096 V,
±2.048 V, ±1.024 V, ±0.512 V, ±0.256 V. Table 8-1 shows the FSR together with the corresponding LSB size.
Equation 4 shows how to calculate the LSB size from the selected full-scale range.

LSB = FSR / 216 (4)

Table 8-1. Full-Scale Range and Corresponding LSB
Size
FSR LSB SIZE
±6.144 V(1) 187.5 μV
±4.096 V(1) 125 μV
±2.048 V 62.5 μV
±1.024 V 31.25 μV
±0.512 V 15.625 μV
±0.256 V 7.8125 μV

(1) This parameter expresses the full-scale range of the ADC

scaling. Do not apply more than VDD + 0.3 V to the analog
inputs of the device.

The FSR of the ADS1113-Q1 is fixed at ±2.048 V.

Analog input voltages must never exceed the analog input voltage limits given in the Absolute Maximum Ratings.
If a VDD supply voltage greater than 4 V is used, the ±6.144 V full-scale range allows input voltages to extend
up to the supply. Although in this case (or whenever the supply voltage is less than the full-scale range; for
example, VDD = 3.3 V and full-scale range = ±4.096 V), a full-scale ADC output code cannot be obtained. For
example, with VDD = 3.3 V and FSR = ±4.096 V, only signals up to VIN = ±3.3 V can be measured. The code
range that represents voltages |VIN| > 3.3 V is not used in this case.
8.3.4 Voltage Reference
The ADS111x-Q1 have an integrated voltage reference. An external reference cannot be used with these
devices.
The ADS111x-Q1 does not use a traditional band-gap reference to generate the internal voltage reference.
For that reason, the reference does not have an actual specified voltage value. Instead of using the reference
voltage value and the gain setting to derive the full-scale range of the ADC, use the FSR values provided in
Table 8-1 directly.
Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included
in the gain error and gain drift specifications in the Electrical Characteristics table.
8.3.5 Oscillator
The ADS111x-Q1 have an integrated oscillator running at 1 MHz. No external clock can be applied to operate
these devices. The internal oscillator drifts over temperature and time. The output data rate scales proportionally
with the oscillator frequency.
8.3.6 Output Data Rate and Conversion Time
The ADS111x-Q1 offer programmable output data rates. Use the DR[2:0] bits in the Config register to select
output data rates of 8 SPS, 16 SPS, 32 SPS, 64 SPS, 128 SPS, 250 SPS, 475 SPS, or 860 SPS.
Conversions in the ADS111x-Q1 settle within a single cycle; thus, the conversion time is equal to 1 / DR.

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8.3.7 Digital Comparator (ADS1114-Q1 and ADS1115-Q1 Only)

The ADS1115-Q1 and ADS1114-Q1 feature a programmable digital comparator that can issue an alert on the
ALERT/RDY pin. The COMP_MODE bit in the Config register configures the comparator as either a traditional
comparator or a window comparator. In traditional comparator mode, the ALERT/RDY pin asserts (active low by
default) when conversion data exceeds the limit set in the high-threshold register (Hi_thresh). The comparator
then deasserts only when the conversion data falls below the limit set in the low-threshold register (Lo_thresh).
In window comparator mode, the ALERT/RDY pin asserts when the conversion data exceed the Hi_thresh
register or fall below the Lo_thresh register value.
In either window or traditional comparator mode, the comparator can be configured to latch after being asserted
by the COMP_LAT bit in the Config register. This setting causes the assertion to remain even if the input signal
is not beyond the bounds of the threshold registers. This latched assertion can only be cleared by issuing an
SMBus alert response or by reading the Conversion register. The ALERT/RDY pin can be configured as active
high or active low by the COMP_POL bit in the Config register. Operational diagrams for both the comparator
modes are shown in Figure 8-7.
The comparator can also be configured to activate the ALERT/RDY pin only after a set number of
successive readings exceed the threshold values set in the threshold registers (Hi_thresh and Lo_thresh). The
COMP_QUE[1:0] bits in the Config register configures the comparator to wait for one, two, or four readings
beyond the threshold before activating the ALERT/RDY pin. The COMP_QUE[1:0] bits can also disable the
comparator function, and put the ALERT/RDY pin into a high state.

TH_H TH_H

Input Signal Input Signal

TH_L TH_L

Time Time

Latching
Latching Successful Comparator Successful Successful
Comparator SMBus Alert Output SMBus Alert SMBus Alert
Output Response Response Response

Time Time

Non-Latching
Non-Latching Comparator
Comparator Output
Output

Time Time

TRADITIONAL COMPARATOR MODE WINDOW COMPARATOR MODE

Figure 8-7. ALERT Pin Timing Diagram

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8.3.8 Conversion Ready Pin (ADS1114-Q1 and ADS1115-Q1 Only)

The ALERT/RDY pin can also be configured as a conversion ready pin. Set the most-significant bit of the
Hi_thresh register to 1b and the most-significant bit of Lo_thresh register to 0b to enable the pin as a conversion
ready pin. The COMP_POL bit continues to function as expected. Set the COMP_QUE[1:0] bits to any 2-bit
value other than 11b to keep the ALERT/RDY pin enabled, and allow the conversion ready signal to appear
at the ALERT/RDY pin output. The COMP_MODE and COMP_LAT bits no longer control any function. When
configured as a conversion ready pin, ALERT/RDY continues to require a pullup resistor. The ADS111x-Q1
provide an approximately 8-µs conversion ready pulse on the ALERT/RDY pin at the end of each conversion in
continuous-conversion mode, as shown in Figure 8-8. In single-shot mode, the ALERT/RDY pin asserts low at
the end of a conversion if the COMP_POL bit is set to 0b.
ADS1114/5-Q1
Converting Converting Converting Converting
Status

Conversion Ready Conversion Ready Conversion Ready

8 µs
ALERT/RDY
(active high)

Figure 8-8. Conversion Ready Pulse in Continuous-Conversion Mode

8.3.9 SMbus Alert Response

In latching comparator mode (COMP_LAT = 1b), the ALERT/RDY pin asserts when the comparator detects a
conversion that exceeds the upper or lower threshold value. This assertion is latched and can be cleared only by
reading conversion data, or by issuing a successful SMBus alert response and reading the asserting device I2C
address. If conversion data exceed the upper or lower threshold values after being cleared, the pin reasserts.
This assertion does not affect conversions that are already in progress. The ALERT/RDY pin is an open-drain
output. This architecture allows several devices to share the same interface bus. When disabled, the pin holds a
high state so that the pin does not interfere with other devices on the same bus line.
When the controller senses that the ALERT/RDY pin has latched, the controller issues an SMBus alert command
(00011001b) to the I2C bus. Any ADS1114-Q1 and ADS1115-Q1 data converters on the I2C bus with the
ALERT/RDY pins asserted respond to the command with the target address. If more than one ADS111x-Q1 on
the I2C bus assert the latched ALERT/RDY pin, arbitration during the address response portion of the SMBus
alert determines which device clears assertion. The device with the lowest I2C address always wins arbitration.
If a device loses arbitration, the device does not clear the comparator output pin assertion. The controller then
repeats the SMBus alert response until all devices have the respective assertions cleared. In window comparator
mode, the SMBus alert status bit indicates a 1b if signals exceed the high threshold, and a 0b if signals exceed
the low threshold.

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8.4 Device Functional Modes

8.4.1 Reset and Power-Up
The ADS111x-Q1 reset on power-up and set all the bits in the Config register to the respective default settings.
The ADS111x-Q1 enter a power-down state after completion of the reset process. The device interface and
digital blocks are active, but no data conversions are performed. The initial power-down state of the ADS111x-
Q1 relieves systems with tight power-supply requirements from encountering a surge during power-up.
The ADS111x-Q1 respond to the I2C general-call reset commands. When the ADS111x-Q1 receive a general call
reset command (06h), an internal reset is performed as if the device is powered-up.
8.4.2 Operating Modes
The ADS111x-Q1 operate in one of two modes: continuous-conversion or single-shot. The MODE bit in the
Config register selects the respective operating mode.
8.4.2.1 Single-Shot Mode
When the MODE bit in the Config register is set to 1b, the ADS111x-Q1 enter a power-down state, and operate
in single-shot mode. This power-down state is the default state for the ADS111x-Q1 when power is first applied.
Although powered down, the devices still respond to commands. The ADS111x-Q1 remain in this power-down
state until a 1b is written to the operational status (OS) bit in the Config register. When the OS bit is asserted,
the device powers up in approximately 25 μs, resets the OS bit to 0b, and starts a single conversion. When
conversion data are ready for retrieval, the device powers down again. Writing a 1b to the OS bit while a
conversion is ongoing has no effect. To switch to continuous-conversion mode, write a 0b to the MODE bit in the
Config register.
8.4.2.2 Continuous-Conversion Mode
In continuous-conversion mode (MODE bit set to 0b), the ADS111x-Q1 perform conversions continuously. When
a conversion is complete, the ADS111x-Q1 place the result in the Conversion register and immediately begin
another conversion. When writing new configuration settings, the currently ongoing conversion completes with
the previous configuration settings. Thereafter, continuous conversions with the new configuration settings start.
To switch to single-shot conversion mode, write a 1b to the MODE bit in the configuration register or reset the
device.
8.4.3 Duty Cycling For Low Power
The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more
samples of the internal modulator are averaged to yield one conversion result. In applications where power
consumption is critical, the improved noise performance at low data rates is not always required. For these
applications, the ADS111x-Q1 support duty cycling that yield significant power savings by periodically requesting
high data rate readings at an effectively lower data rate. For example, an ADS111x-Q1 in power-down state with
a data rate set to 860 SPS can be operated by a microcontroller that instructs a single-shot conversion every
125 ms (8 SPS). A conversion at 860 SPS only requires approximately 1.2 ms, so the ADS111x-Q1 enter power-
down state for the remaining 123.8 ms. In this configuration, the ADS111x-Q1 consume approximately 1/100th
the power that is otherwise consumed in continuous-conversion mode. The duty cycling rate is completely
arbitrary and is defined by the controller. The ADS111x-Q1 offer lower data rates that do not implement duty
cycling and also offer improved noise performance if required.

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8.5 Programming
8.5.1 I2C Interface
The ADS111x-Q1 communicate through an I2C interface. I2C is a two-wire open-drain interface that supports
multiple devices and controllers on a single bus. Devices on the I2C bus only drive the bus lines low by
connecting them to ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high
by pullup resistors, so the bus wires are always high when no device is driving them low. As a result of
this configuration, two devices cannot conflict. If two devices drive the bus simultaneously, there is no driver
contention.
Communication on the I2C bus always takes place between two devices, one acting as the controller and the
other as the target. Both the controller and target can read and write, but the target can only do so under the
direction of the controller. Some I2C devices can act as a controller or target, but the ADS111x-Q1 can only act
as a target device.
An I2C bus consists of two lines: SDA and SCL. SDA carries data; SCL provides the clock. All data are
transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, drive the SDA line to the
appropriate level while SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). After
the SDA line settles, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the
receiver shift register. If the I2C bus is held idle for more than 25 ms, the bus times out.
The I2C bus is bidirectional; that is, the SDA line is used for both transmitting and receiving data. When the
controller reads from a target, the target drives the data line; when the controller writes to a target, the controller
drives the data line. The controller always drives the clock line. The ADS111x-Q1 cannot act as a controller, and
therefore can never drive SCL.
Most of the time the bus is idle; no communication occurs, and both lines are high. When communication takes
place, the bus is active. Only a controller device can start a communication and initiate a START condition
on the bus. Normally, the data line is only allowed to change state when the clock line is low. If the data line
changes state when the clock line is high, this change is either a START condition or a STOP condition. A
START condition occurs when the clock line is high, and the data line goes from high to low. A STOP condition
occurs when the clock line is high, and the data line goes from low to high.
After the controller issues a START condition, the controller sends a byte that indicates which target device to
communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address
that the device responds to. The controller sends an address in the address byte, together with a bit that
indicates whether the controller wishes to read from or write to the target device.
Every byte (address and data) transmitted on the I2C bus is acknowledged with an acknowledge bit. When the
controller finishes sending a byte (eight data bits) to a target, the controller stops driving SDA and waits for the
target to acknowledge the byte. The target acknowledges the byte by pulling SDA low. The controller then sends
a clock pulse to clock the acknowledge bit. Similarly, when the controller completes reading a byte, the controller
pulls SDA low to acknowledge this completion to the target. The controller then sends a clock pulse to clock the
bit. The controller always drives the clock line.
If a device is not present on the bus, and the controller attempts to address the device, the controller receives
a not-acknowledge because no device is present at that address to pull the line low. A not-acknowledge is
performed by simply leaving SDA high during an acknowledge cycle.
When the controller has finished communicating with a target, the controller can issue a STOP condition. When
a STOP condition is issued, the bus becomes idle again. The controller can also issue another START condition.
When a START condition is issued while the bus is active, this condition is called a repeated start condition.
The Timing Requirements section shows a timing diagram for the ADS111x-Q1 I2C communication.

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8.5.1.1 I2C Address Selection

The ADS111x-Q1 have one address pin, ADDR, that configures the I2C address of the device. This pin can
be connected to GND, VDD, SDA, or SCL, allowing for four different addresses to be selected with one pin,
as shown in Table 8-2. The state of address pin ADDR is sampled continuously. Use the GND, VDD and SCL
addresses first. If SDA is used as the device address, hold the SDA line low for at least 100 ns after the SCL line
goes low to make sure the device decodes the address correctly during I2C communication.
Table 8-2. ADDR Pin Connection and Corresponding Target Address
ADDR PIN CONNECTION TARGET ADDRESS
GND 1001000b
VDD 1001001b
SDA 1001010b
SCL 1001011b

8.5.1.2 I2C General Call

The ADS111x-Q1 respond to the I2C general call address (0000000b) if the eighth bit is 0b. The devices
acknowledge the general call address and respond to commands in the second byte. If the second byte is
00000110b (06h), the ADS111x-Q1 reset the internal registers and enter a power-down state.
8.5.1.3 I2C Speed Modes
The I2C bus operates at one of three speeds. Standard mode allows a clock frequency of up to 100 kHz; fast
mode permits a clock frequency of up to 400 kHz; and high-speed mode (also called Hs mode) allows a clock
frequency of up to 3.4 MHz. The ADS111x-Q1 are fully compatible with all three modes.
No special action is required to use the ADS111x-Q1 in standard or fast mode, but high-speed mode must
be activated. To activate high-speed mode, send a special address byte of 00001xxxb following the START
condition, where xxx are bits unique to the Hs-capable controller. This byte is called the Hs controller code,
and is different from normal address bytes; the eighth bit does not indicate read/write status. The ADS111x-Q1
do not acknowledge this byte; the I2C specification prohibits acknowledgment of the Hs controller code. Upon
receiving a controller code, the ADS111x-Q1 switch on Hs mode filters, and communicate at up to 3.4 MHz. The
ADS111x-Q1 switch out of Hs mode with the next STOP condition.
For more information on high-speed mode, consult the I2C specification.
8.5.2 Target Mode Operations
The ADS111x-Q1 act as target receivers or target transmitters. The ADS111x-Q1 cannot drive the SCL line as
target devices.
8.5.2.1 Receive Mode
In target receive mode, the first byte transmitted from the controller to the target consists of the 7-bit device
address followed by a low R/W bit. The next byte transmitted by the controller is the Address Pointer register.
The ADS111x-Q1 then acknowledge receipt of the Address Pointer register byte. The next two bytes are written
to the address given by the register address pointer bits, P[1:0]. The ADS111x-Q1 acknowledge each byte sent.
Register bytes are sent with the most significant byte first, followed by the least significant byte.
8.5.2.2 Transmit Mode
In target transmit mode, the first byte transmitted by the controller is the 7-bit target address followed by the
high R/W bit. This byte places the target into transmit mode and indicates that the ADS111x-Q1 are being
read from. The next byte transmitted by the target is the most significant byte of the register that is indicated
by the register address pointer bits, P[1:0]. This byte is followed by an acknowledgment from the controller.
The remaining least significant byte is then sent by the target and is followed by an acknowledgment from the
controller. The controller can terminate transmission after any byte by not acknowledging or issuing a START or
STOP condition.

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8.5.3 Writing To and Reading From the Registers

To access a specific register from the ADS111x-Q1, the controller must first write an appropriate value to register
address pointer bits P[1:0] in the Address Pointer register. The Address Pointer register is written to directly after
the target address byte, low R/W bit, and a successful target acknowledgment. After the Address Pointer register
is written, the target acknowledges, and the controller issues a STOP or a repeated START condition.
When reading from the ADS111x-Q1, the previous value written to bits P[1:0] determines the register that is
read. To change which register is read, a new value must be written to P[1:0]. To write a new value to P[1:0], the
controller issues a target address byte with the R/W bit low, followed by the Address Pointer register byte. No
additional data has to be transmitted, and a STOP condition can be issued by the controller. The controller can
now issue a START condition and send the target address byte with the R/W bit high to begin the read. Figure
8-9 details this sequence. If repeated reads from the same register are desired, there is no need to continually
send the Address Pointer register, because the ADS111x-Q1 store the value of P[1:0] until modified by a write
operation. However, for every write operation, the Address Pointer register must be written with the appropriate
values.
1 9 1 9

SCL ¼

(1) (1)
SDA 1 0 0 1 0 A1 A0 R/W 0 0 0 0 0 0 P1 P0

Start By ACK By ACK By Stop By

Controller ADS1113/4/5-Q1 ADS1113/4/5-Q1Controller

Frame 1: Target Address Byte Frame 2: Address Pointer Register

1 9 1 9
SCL
(Continued)
¼

SDA
1 0 0 1 0 A1
(1)
A0
(1)
R/W D15 D14 D13 D12 D11 D10 D9 D8 ¼
(Continued)
Start By ACK By From ACK By
(2)
Controller ADS1113/4/5-Q1 ADS1113/4/5-Q1 Controller
Frame 3: Target Address Byte Frame 4: Data Byte 1 Read Register

1 9
SCL
(Continued)

SDA
D7 D6 D5 D4 D3 D2 D1 D0
(Continued)
From ACK By Stop By
(3)
ADS1113/4/5-Q1 Controller Controller
Frame 5: Data Byte 2 Read Register

A. The values of A0 and A1 are determined by the ADDR pin.

B. The controller can leave SDA high to terminate a single-byte read operation.
C. The controller can leave SDA high to terminate a two-byte read operation.

Figure 8-9. Timing Diagram for Reading From the ADS111x-Q1

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1 9 1 9

SCL ¼

SDA 1 0 0 1 0 A1
(1)
A0
(1)
R/W 0 0 0 0 0 0 P1 P0 ¼
Start By ACK By ACK By
Controller ADS1113/4/5-Q1 ADS1113/4/5-Q1

Frame 1: Target Address Byte Frame 2: Address Pointer Register

1 9 1 9
SCL
(Continued)

SDA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(Continued)
ACK By ACK By Stop By
ADS1113/4/5-Q1 ADS1113/4/5-Q1 Controller

Frame 3: Data Byte 1 Frame 4: Data Byte 2

A. The values of A0 and A1 are determined by the ADDR pin.

Figure 8-10. Timing Diagram for Writing to the ADS111x-Q1

ALERT

1 9 1 9

SCL

SDA 0 0 0 1 1 0 0 R/W 1 0 0 1 A1 A0 Status

Start By ACK By From NACK By Stop By

Controller ADS1113/4/5-Q1 ADS1113/4/5-Q1 Controller Controller
Frame 1: SMBus ALERT Response Address Byte Frame 2: Target Address

A. The values of A0 and A1 are determined by the ADDR pin.

Figure 8-11. Timing Diagram for SMBus Alert Response

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8.5.4 Data Format

The ADS111x-Q1 provide 16 bits of data in binary 2's-complement format. A positive full-scale (+FS) input
produces an output code of 7FFFh and a negative full-scale (–FS) input produces an output code of 8000h. The
output clips at these codes for signals that exceed full-scale. Table 8-3 summarizes the ideal output codes for
different input signals. Figure 8-12 shows code transitions versus input voltage.
Table 8-3. Input Signal Versus Ideal Output Code
INPUT SIGNAL
VIN = (VAINP – VAINN) IDEAL OUTPUT CODE(1) (1)
≥ +FS (215 – 1)/215 7FFFh
+FS/215 0001h
0 0000h
–FS/215 FFFFh
≤ –FS 8000h

(1) Excludes the effects of noise, INL, offset, and gain errors.

7FFFh
7FFEh
...

0001h
Output Code

0000h
FFFFh
...

8001h
8000h

-FS ... 0 ... +FS

Input Voltage VIN
15 15
2 -1 2 -1
-FS +FS
15 15
2 2

Figure 8-12. Code Transition Diagram

Note
Single-ended signal measurements, where VAINN = 0 V and VAINP = 0 V to +FS, only use the positive
code range from 0000h to 7FFFh. However, because of device offset, the ADS111x-Q1 can still output
negative codes in case VAINP is close to 0 V.

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8.6 Register Map

The ADS111x-Q1 have four registers that are accessible through the I2C interface using the Address Pointer
register. The Conversion register contains the result of the last conversion. The Config register is used to change
the ADS111x-Q1 operating modes and query the status of the device. The other two registers, Lo_thresh and
Hi_thresh, set the threshold values used for the comparator function, and are not available in the ADS1113-Q1.
8.6.1 Address Pointer Register (address = N/A) [reset = N/A]
All four registers are accessed by writing to the Address Pointer register; see Figure 8-9.
Figure 8-13. Address Pointer Register
7 6 5 4 3 2 1 0
RESERVED P[1:0]
W-000000b W-00b

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 8-4. Address Pointer Register Field Descriptions

Bit Field Type Reset Description
7:2 Reserved W 000000b Always write 000000b
1:0 P[1:0] W 00b Register address pointer
00b : Conversion register
01b : Config register
10b : Lo_thresh register
11b : Hi_thresh register

8.6.2 Conversion Register (P[1:0] = 00b) [reset = 0000h]

The 16-bit Conversion register contains the result of the last conversion in binary 2's-complement format.
Following power-up, the Conversion register is cleared to 0000h, and remains 0000h until the first conversion
completes.
Figure 8-14. Conversion Register
15 14 13 12 11 10 9 8
D[15:8]
R-00h
7 6 5 4 3 2 1 0
D[7:0]
R-00h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8-5. Conversion Register Field Descriptions

Bit Field Type Reset Description
15:0 D[15:0] R 0000h 16-bit conversion result

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8.6.3 Config Register (P[1:0] = 01b) [reset = 8583h]

The 16-bit Config register is used to control the operating mode, input selection, data rate, full-scale range, and
comparator modes.
Figure 8-15. Config Register - ADS1113-Q1
15 14 13 12 11 10 9 8
OS RESERVED MODE
R/W-1b R/W-000010b R/W-1b
7 6 5 4 3 2 1 0
DR[2:0] RESERVED
R/W-100b R/W-00011b

Figure 8-16. Config Register - ADS1114-Q1

15 14 13 12 11 10 9 8
OS RESERVED PGA[2:0] MODE
R/W-1b R/W-000b R/W-010b R/W-1b
7 6 5 4 3 2 1 0
DR[2:0] COMP_MODE COMP_POL COMP_LAT COMP_QUE[1:0]
R/W-100b R/W-0b R/W-0b R/W-0b R/W-11b

Figure 8-17. Config Register - ADS1115-Q1

15 14 13 12 11 10 9 8
OS MUX[2:0] PGA[2:0] MODE
R/W-1b R/W-000b R/W-010b R/W-1b
7 6 5 4 3 2 1 0
DR[2:0] COMP_MODE COMP_POL COMP_LAT COMP_QUE[1:0]
R/W-100b R/W-0b R/W-0b R/W-0b R/W-11b

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8-6. Config Register Field Descriptions

Bit Field Type Reset Description
Operational status or single-shot conversion start
This bit determines the operational status of the device. OS can only be written
when in power-down state and has no effect when a conversion is ongoing.
When writing:
15 OS R/W 1b 0b : No effect
1b : Start a single conversion (when in power-down state)
When reading:
0b : Device is currently performing a conversion
1b : Device is not currently performing a conversion
Input multiplexer configuration (ADS1115-Q1 only)
These bits configure the input multiplexer.
These bits serve no function on the ADS1113-Q1 and ADS1114-Q1. ADS1113-Q1
and ADS1114-Q1 always use inputs AINP = AIN0 and AINN = AIN1.
000b : AINP = AIN0 and AINN = AIN1 (default)
001b : AINP = AIN0 and AINN = AIN3
14:12 MUX[2:0] R/W 000b
010b : AINP = AIN1 and AINN = AIN3
011b : AINP = AIN2 and AINN = AIN3
100b : AINP = AIN0 and AINN = GND
101b : AINP = AIN1 and AINN = GND
110b : AINP = AIN2 and AINN = GND
111b : AINP = AIN3 and AINN = GND

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Table 8-6. Config Register Field Descriptions (continued)

Bit Field Type Reset Description
Programmable gain amplifier configuration
These bits set the FSR of the programmable gain amplifier.
These bits serve no function on the ADS1113-Q1. ADS1113-Q1 always uses FSR
= ±2.048 V.
000b : FSR = ±6.144 V(1)
001b : FSR = ±4.096 V(1)
11:9 PGA[2:0] R/W 010b
010b : FSR = ±2.048 V (default)
011b : FSR = ±1.024 V
100b : FSR = ±0.512 V
101b : FSR = ±0.256 V
110b : FSR = ±0.256 V
111b : FSR = ±0.256 V
Device operating mode
This bit controls the operating mode.
8 MODE R/W 1b
0b : Continuous-conversion mode
1b : Single-shot mode or power-down state (default)
Data rate
These bits control the data rate setting.
000b : 8 SPS
001b : 16 SPS
010b : 32 SPS
7:5 DR[2:0] R/W 100b
011b : 64 SPS
100b : 128 SPS (default)
101b : 250 SPS
110b : 475 SPS
111b : 860 SPS
Comparator mode (ADS1114-Q1 and ADS1115-Q1 only)
This bit configures the comparator operating mode.
4 COMP_MODE R/W 0b This bit serves no function on the ADS1113-Q1.
0b : Traditional comparator (default)
1b : Window comparator
Comparator polarity (ADS1114-Q1 and ADS1115-Q1 only)
This bit controls the polarity of the ALERT/RDY pin.
3 COMP_POL R/W 0b This bit serves no function on the ADS1113-Q1.
0b : Active low (default)
1b : Active high
Latching comparator (ADS1114-Q1 and ADS1115-Q1 only)
This bit controls whether the ALERT/RDY pin latches after being asserted or
clears after conversions are within the margin of the upper and lower threshold
values.
This bit serves no function on the ADS1113-Q1.
2 COMP_LAT R/W 0b 0b : Nonlatching comparator . The ALERT/RDY pin does not latch when asserted
(default).
1b : Latching comparator. The asserted ALERT/RDY pin remains latched until
conversion data are read by the controller or an appropriate SMBus alert
response is sent by the controller. The device responds with an address, and
is the lowest address currently asserting the ALERT/RDY bus line.
Comparator queue and disable (ADS1114-Q1 and ADS1115-Q1 only)
These bits perform two functions. When set to 11, the comparator is disabled
and the ALERT/RDY pin is set to a high-impedance state. When set to any other
value, the ALERT/RDY pin and the comparator function are enabled, and the set
value determines the number of successive conversions exceeding the upper or
1:0 COMP_QUE[1:0] R/W 11b lower threshold required before asserting the ALERT/RDY pin.
These bits serve no function on the ADS1113-Q1.
00b : Assert after one conversion
01b : Assert after two conversions
10b : Assert after four conversions
11b : Disable comparator and set ALERT/RDY pin to high-impedance (default)

(1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to the analog inputs of the
device.

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8.6.4 Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers
These two registers are applicable to the ADS1115-Q1 and ADS1114-Q1. These registers serve no purpose
in the ADS1113-Q1. The upper and lower threshold values used by the comparator are stored in two 16-bit
registers in 2's complement format. The comparator is implemented as a digital comparator; therefore, the
values in these registers must be updated whenever the PGA settings are changed.
The conversion-ready function of the ALERT/RDY pin is enabled by setting the Hi_thresh register MSB to 1b and
the Lo_thresh register MSB to 0b. To use the comparator function of the ALERT/RDY pin, the Hi_thresh register
value must always be greater than the Lo_thresh register value. The threshold register formats are shown in
Figure 8-18. When set to RDY mode, the ALERT/RDY pin outputs the OS bit when in single-shot mode, and
provides a continuous-conversion ready pulse when in continuous-conversion mode.
Figure 8-18. Lo_thresh Register
15 14 13 12 11 10 9 8
Lo_thresh[15:8]
R/W-80h
7 6 5 4 3 2 1 0
Lo_thresh[7:0]
R/W-00h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8-7. Hi_thresh Register

15 14 13 12 11 10 9 8
Hi_thresh[15:8]
R/W-7Fh
7 6 5 4 3 2 1 0
Hi_thresh[7:0]
R/W-FFh

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8-8. Lo_thresh and Hi_thresh Register Field Descriptions

Bit Field Type Reset Description
15:0 Lo_thresh[15:0] R/W 8000h Low threshold value
15:0 Hi_thresh[15:0] R/W 7FFFh High threshold value

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The following sections give example circuits and suggestions for using the ADS111x-Q1 in various situations.
9.1.1 Basic Connections
The principle I2C connections for the ADS1115-Q1 are shown in Figure 9-1.

10
ADS1115-Q1 VDD
SCL

1-k
to 10-k (typ)

VDD 1 ADDR SDA 9
Pullup Resistors
2 ALERT/RDY VDD 8

3 GND AIN3 7 0.1 μF (typ)

Microcontroller or
Microprocessor
4 AIN0 AIN2 6
with I2C Port
AIN1
5
SCL

SDA

GPIO

Inputs Selected
from Configuration
Register

Figure 9-1. Typical Connections of the ADS1115-Q1

The fully-differential voltage input of the ADS111x-Q1 is ideal for connection to differential sources with
moderately low source impedance, such as thermocouples and thermistors. Although the ADS111x-Q1 can
read bipolar differential signals, these devices cannot accept negative voltages on either input.
The ADS111x-Q1 draw transient currents during conversion. A 0.1-μF power-supply bypass capacitor supplies
the momentary bursts of extra current required from the supply.
The ADS111x-Q1 interface directly to standard mode, fast mode, and high-speed mode I2C controllers. Any
microcontroller I2C peripheral, including controller-only and single-controller I2C peripherals, operates with the
ADS111x-Q1. The ADS111x-Q1 does not perform clock-stretching (that is, the device never pulls the clock line
low), so this function does not need to be provided for unless other clock-stretching devices are on the same I2C
bus.
Pullup resistors are required on both the SDA and SCL lines because I2C bus drivers are open drain. The size
of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors
consume less power, but increase the transition times on the bus, thus limiting the bus speed. Lower-value
resistors allow higher speed, but at the expense of higher power consumption. Long bus lines have higher
capacitance and require smaller pullup resistors to compensate. Do not use resistors that are too small to avoid
bus drivers being unable to pull the bus lines low.

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9.1.2 Single-Ended Inputs

The ADS1113-Q1 and ADS1114-Q1 can measure one, and the ADS1115-Q1 up to four, single-ended signals.
The ADS1113-Q1 and ADS1114-Q1 can measure single-ended signals by connecting AIN1 to GND externally.
The ADS1115-Q1 measures single-ended signals by appropriate configuration of the MUX[2:0] bits in the Config
register. Figure 9-2 shows a single-ended connection scheme for ADS1115-Q1. The single-ended signal ranges
from 0 V up to positive supply or +FS, whichever is lower. Negative voltages cannot be applied to these devices
because the ADS111x-Q1 can only accept positive voltages with respect to ground. The ADS111x-Q1 do not
lose linearity within the input range.
The ADS111x-Q1 offer a differential input voltage range of ±FSR. Single-ended configurations use only one-half
of the full-scale input voltage range. Differential configurations maximize the dynamic range of the ADC, and
provide better common-mode noise rejection than single-ended configurations.
VDD

10 Output Codes
ADS1115-Q1 SCL 0-32767

1 ADDR SDA 9

2 ALERT/RDY VDD 8

3 GND AIN3 7 0.1
F (typ)

4 AIN0 AIN2 6

AIN1
5

Inputs Selected
from Configuration
Register

NOTE: Digital pin connections omitted for clarity.

Figure 9-2. Measuring Single-Ended Inputs

The ADS1115-Q1 also allows AIN3 to serve as a common point for measurements by appropriate setting of
the MUX[2:0] bits. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration, the
ADS1115-Q1 operates with inputs, where AIN3 serves as the common point. This ability improves the usable
range over the single-ended configuration because negative differential voltages are allowed when
GND < V(AIN3) < VDD; however, common-mode noise attenuation is not offered.
9.1.3 Input Protection
The ADS111x-Q1 are fabricated in a small-geometry, low-voltage process. The analog inputs feature protection
diodes to the supply rails. However, the current-handling ability of these diodes is limited, and the ADS111x-Q1
can be permanently damaged by analog input voltages that exceed approximately 300 mV beyond the rails for
extended periods. One way to protect against overvoltage is to place current-limiting resistors on the input lines.
The ADS111x-Q1 analog inputs can withstand continuous currents as large as 10 mA.
9.1.4 Unused Inputs and Outputs
Follow the guidelines below for the connection of unused device pins:
• Either float unused analog inputs, or tie unused analog inputs to GND
• Either float NC (not connected) pins, or tie the NC pins to GND
• If the ALERT/RDY output pin is not used, leave the pin unconnected or tie the pin to VDD using a weak
pullup resistor

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9.1.5 Analog Input Filtering

Analog input filtering serves two purposes:
1. Limits the effect of aliasing during the sampling process
2. Reduces external noise from being a part of the measurement
Aliasing occurs when frequency components are present in the input signal that are higher than half the
sampling frequency of the ADC (also known as the Nyquist frequency). These frequency components fold back
and show up in the actual frequency band of interest below half the sampling frequency. The filter response of
the digital filter repeats at multiples of the sampling frequency, also known as the modulator frequency (fMOD),
as shown in Figure 9-3. Signals or noise up to a frequency where the filter response repeats are attenuated to
a certain amount by the digital filter depending on the filter architecture. Any frequency components present in
the input signal around the modulator frequency, or multiples thereof, are not attenuated and alias back into the
band of interest, unless attenuated by an external analog filter.
Magnitude

Sensor Unwanted
Signal Unwanted Signals
Signals

Output fMOD / 2 fMOD Frequency

Data Rate

Magnitude
Digital Filter

Aliasing of
Unwanted Signals

Output fMOD / 2 fMOD Frequency

Data Rate

Magnitude External
Antialiasing Filter
Roll-Off

Output fMOD / 2 fMOD Frequency

Data Rate

Figure 9-3. Effect of Aliasing

Many sensor signals are inherently band-limited; for example, the output of a thermocouple has a limited rate of
change. In this case, the sensor signal does not alias back into the pass-band when using a ΔΣ ADC. However,
any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass-band.
Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated
from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors
and cellular phones. Another noise source typically exists on the printed-circuit-board (PCB) in the form of clocks
and other digital signals. Analog input filtering helps remove unwanted signals from affecting the measurement
result.
A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to
reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond fMOD / 2 is
attenuated to a level below the noise floor of the ADC. The digital filter of the ADS111x-Q1 attenuate signals to
a certain degree, as shown in Figure 6-21. In addition, noise components are usually smaller in magnitude than
the actual sensor signal. Therefore, use a first-order RC filter with a cutoff frequency set at the output data rate
or 10x higher as a generally good starting point for a system design.

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9.1.6 Connecting Multiple Devices

Up to four ADS111x-Q1 devices can be connected to a single I2C bus using different address pin configurations
for each device. Use the address pin to set the ADS111x-Q1 to one of four different I2C addresses. Use the
GND, VDD, and SCL addresses first. If SDA is used as the device address, hold the SDA line low for at
least 100 ns after the SCL line goes low to make sure the device decodes the address correctly during I2C
communication. An example showing four ADS111x-Q1 devices on the same I2C bus is shown in Figure 9-4.
One set of pullup resistors is required per bus. If needed, lower the pullup resistor values to compensate for the
additional bus capacitance presented by multiple devices and increased line length.
VDD
GND

10
ADS1115-Q1
SCL

1 ADDR SDA 9
1-k
to 10-k (typ) 2 ALERT/RDY VDD 8
I2C Pullup Resistors VDD
3 GND AIN3 7

4 AIN0 AIN2 6
Microcontroller or
Microprocessor AIN1
With I2C Port
5

SCL

SDA

10
ADS1115-Q1
SCL

1 ADDR SDA 9
2 ALERT/RDY VDD 8

3 GND AIN3 7

4 AIN0 AIN2 6
AIN1
5

10
ADS1115-Q1
SCL

1 ADDR SDA 9
2 ALERT/RDY VDD 8

3 GND AIN3 7

4 AIN0 AIN2 6
AIN1
5

10
ADS1115-Q1
SCL

1 ADDR SDA 9
2 ALERT/RDY VDD 8

3 GND AIN3 7

4 AIN0 AIN2 6
AIN1
5

NOTE: The ADS111x-Q1 power and input connections are omitted for clarity. The ADDR pin selects the I2C address.

Figure 9-4. Connecting Multiple ADS111x-Q1 Devices

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9.1.7 Quick-Start Guide

This section provides a brief example of ADS111x-Q1 communications. Hardware for this design includes: one
ADS111x-Q1 configured with an I2C address of 1001000b; a microcontroller with an I2C interface; discrete
components such as resistors, capacitors, and serial connectors; and a 2-V to 5-V power supply. Figure 9-5
shows the basic hardware configuration.
The ADS111x-Q1 communicate with the controller (microcontroller) through an I2C interface. The controller
provides a clock signal on the SCL pin and data are transferred using the SDA pin. The ADS111x-Q1 never
drive the SCL pin. For information on programming and debugging the microcontroller being used, see the
device-specific product data sheet.
The first byte sent by the controller is the ADS111x-Q1 address, followed by the R/W bit that instructs the
ADS111x-Q1 to listen for a subsequent byte. The second byte is the Address Pointer register byte. The third and
fourth bytes sent from the controller are written to the register indicated in register address pointer bits P[1:0].
See Figure 8-9 and Figure 8-10 for read and write operation timing diagrams, respectively. All read and write
transactions with the ADS111x-Q1 must be preceded by a START condition, and followed by a STOP condition.
For example, to write to the configuration register to set the ADS111x-Q1 to continuous-conversion mode and
then read the conversion result, send the following bytes in this order:
1. Write to Config register:
• First byte: 10010000b (first 7-bit I2C address followed by a low R/W bit)
• Second byte: 00000001b (points to Config register)
• Third byte: 10000100b (MSB of the Config register to be written)
• Fourth byte: 10000011b (LSB of the Config register to be written)
2. Write to Address Pointer register:
• First byte: 10010000b (first 7-bit I2C address followed by a low R/W bit)
• Second byte: 00000000b (points to Conversion register)
3. Read Conversion register:
• First byte: 10010001b (first 7-bit I2C address followed by a high R/W bit)
• Second byte: the ADS111x-Q1 response with the MSB of the Conversion register
• Third byte: the ADS111x-Q1 response with the LSB of the Conversion register
3.3 V
ADS111x-Q1
VDD
0.1 µF 2
GND 3.3 V I C-Capable Controller
AIN0 (MSP430F2002)

AIN1 3.3 V
ADDR 10 k 10 k

AIN2 (ADS1115-Q1 Only)
SCL SCL (P1.6) VDD
AIN3 (ADS1115-Q1 Only) 0.1 µF
SDA SDA (P1.7)
GND
ALERT
(ADS1114/5-Q1 Only)

JTAG Serial/UART

Figure 9-5. Basic Hardware Configuration

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9.2 Typical Application

Shunt-based, current-measurement solutions are widely used to monitor load currents. Low-side, current-shunt
measurements are independent of the bus voltage because the shunt common-mode voltage is near ground.
Figure 9-6 shows an example circuit for a bidirectional, low-side, current-shunt measurement system. The load
current is determined by measuring the voltage across the shunt resistor that is amplified and level-shifted by
a low-drift operational amplifier, OPA333-Q1. The OPA333-Q1 output voltage is digitized with ADS1115-Q1 and
sent to the microcontroller using the I2C interface. This circuit is capable of measuring bidirectional currents
flowing through the shunt resistor with great accuracy and precision.
High-Voltage Bus
VDD
VCM VDD
CCM2
LOAD R6
AINN
ILOAD R4 I2C
R3 OPA333-Q1 CDIFF ADS1115-Q1
+ R5
4-Wire Kelvin

VINX
Connection

AINP
VOUT
RSHUNT

±
VSHUNT CCM1

R1 R2

Figure 9-6. Low-Side Current Shunt Monitoring

9.2.1 Design Requirements

Table 9-1 shows the design parameters for this application.
Table 9-1. Design Parameters
DESIGN PARAMETER VALUE
Supply voltage (VDD) 5V
Voltage across shunt resistor (VSHUNT) ±50 mV
Output data rate (DR) ≥200 readings per second
Typical measurement accuracy at TA = 25°C(1) ±0.2%

(1) Does not account for inaccuracy of shunt resistor and the precision resistors used in the
application.

9.2.2 Detailed Design Procedure

The first stage of the application circuit consists of an OPA333-Q1 in a noninverting summing amplifier
configuration and serves two purposes:
1. To level-shift the ground-referenced signal to allow bidirectional current measurements while running off a
unipolar supply. The voltage across the shunt resistor, VSHUNT, is level-shifted by a common-mode voltage,
VCM, as shown in Figure 9-6. The level-shifted voltage, VINX, at the noninverting input is given by Equation 5.
VINX = (VCM · R3 + VSHUNT · R4) / (R3 + R4) (5)
2. To amplify the level-shifted voltage (VINX). The OPA333-Q1 is configured in a noninverting gain configuration
with the output voltage, VOUT, given by Equation 6.
VOUT = VINX · (1 + R2 / R1) (6)

Using Equation 5 and Equation 6, VOUT is given as a function of VSHUNT and VCM by Equation 7.

VOUT = (VCM · R3 + VSHUNT · R4) / (R3 + R4) · (1 + R2 / R1) (7)

Using Equation 7 the ADC differential input voltage, before the first-order RC filter, is given by Equation 8.

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VOUT – VCM = VSHUNT · (1 + R2 / R1) / (1 + R4 / R3) + VCM · (R2 / R1 – R3 / R4) / (1 + R3 / R4) (8)

If R1 = R4 and R2 = R3, Equation 8 is simplified to Equation 9.

VOUT – VCM = VSHUNT · (1 + R2 / R1) / (1 + R4 / R3) (9)

9.2.2.1 Shunt Resistor Considerations

A shunt resistor (RSHUNT) is an accurate resistance inserted in series with the load as shown in Figure 9-6. If the
absolute voltage drop across the shunt, |VSHUNT|, is a larger percentage of the bus voltage, the voltage drop can
reduce the overall efficiency and system performance. If |VSHUNT| is too low, measuring the small voltage drop
requires careful design attention and proper selection of the ADC, operation amplifier, and precision resistors.
Make sure that the absolute voltage at the shunt terminals does not result in violation of the input common-mode
voltage range requirements of the operational amplifier. The power dissipation on the shunt resistor increases
the temperature because of the current flowing through the resistor. To minimize the measurement errors
resulting from variation in temperature, select a low-drift shunt resistor. To minimize the measurement gain error,
select a shunt resistor with low tolerance value. To remove the errors caused by stray ground resistance, use a
four-wire Kelvin-connected shunt resistor, as shown in Figure 9-6.
9.2.2.2 Operational Amplifier Considerations
The operational amplifier used for this design example requires the following features:
• Unipolar supply operation (5 V)
• Low input offset voltage (< 10 µV) and input offset voltage drift (< 0.5 µV/°C)
• Rail-to-rail input and output capability
• Low thermal and flicker noise
• High common-mode rejection (> 100 dB)
The OPA333-Q1 offers all these benefits and is selected for this application.
9.2.2.3 ADC Input Common-Mode Considerations
VCM sets the VOUT common-mode voltage by appropriate selection of precision resistors R1, R2, R3, and R4.
If R1 = R3, R2 = R4, and VSHUNT = 0 V, VOUT is given by Equation 10.

VOUT = VCM (10)

If VOUT is connected to the ADC positive input (AINP) and VCM is connected to the ADC negative input
(AINN), VCM appears as a common-mode voltage to the ADC. This configuration allows pseudo-differential
measurements and uses the maximum dynamic range of the ADC if VCM is set at midsupply (VDD / 2). A resistor
divider from VDD to GND followed by a buffer amplifier can be used to generate VCM.
9.2.2.4 Resistor (R1, R2, R3, R4) Considerations
Proper selection of resistors R1, R2, R3, and R4 is critical for meeting the overall accuracy requirements.
Using Equation 8, the offset term, VOUT-OS, and the gain term, AOUT, of the differential ADC input are
represented by Equation 11 and Equation 12 respectively. The error contributions from the first-order RC filters
are ignored.

VOUT-OS = VCM · (R2 / R1 – R3 / R4) / (1 + R3 / R4) (11)

AOUT = (1 + R2 / R1) / (1 + R4 / R3) (12)

The tolerance, drift, and linearity performance of these resistors is critical to meeting the overall accuracy
requirements. In Equation 11, if R1 = R3 and R2 = R4, VOUT-OS = 0 V and therefore, the common-mode voltage,
VCM, only contributes to level-shift VSHUNT and does not introduce any error at the differential ADC inputs.
High-precision resistors provide better common-mode rejection from VCM.

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9.2.2.5 Noise and Input Impedance Considerations

If vn_res represents the input-referred rms noise from all the resistors, vn_op represents the input-referred rms
noise of OPA333-Q1, and vn_ADC represents the input-referred rms noise of ADS1115-Q1, the total input-referred
noise of the entire system, vN, can be approximated by Equation 13.

vN 2 = vn_res 2 + vn_op 2 + vn_ADC/ (1 + R2 / R1)2 (13)

The ADC noise contribution, vn_ADC, is attenuated by the noninverting gain stage.
If the gain of the noninverting gain stage is high (≥ 5), a good approximation for vn_res 2 is given by Equation 14.
The noise contribution from resistors R2, R4, R5, and R6 when referred to the input is smaller in comparison to R1
and R3 and can be neglected for approximation purposes.

vn_res 2 = 4 · k · T · (R1 + R3) · Δf (14)

where:
• where k = Boltzmann constant
• T = temperature (in kelvins)
• Δf = noise bandwidth
An approximation for the input impedance, RIN, of the application circuit is given by Equation 15. RIN can be
modeled as a resistor in parallel with the shunt resistor, and can contribute to additional gain error.

RIN = R3 + R4 (15)

From Equation 14 and Equation 15, a trade-off exists between vN and R IN. If R3 increases, v n_res increases, and
therefore, the total input-referred rms system noise, vN, increases. If R3 decreases, the input impedance, RIN,
drops, and causes additional gain error.
9.2.2.6 First-Order RC Filter Considerations
Although the device digital filter attenuates high-frequency noise, use a first-order, low-pass RC filter at the ADC
inputs to further reject out-of-bandwidth noise and avoid aliasing. A differential low-pass RC filter formed by R5,
R6, and the differential capacitor CDIFF sets the –3-dB cutoff frequency, fC, given by Equation 16. These filter
resistors produce a voltage drop because of the input currents flowing into and out of the ADC. This voltage drop
can contribute to an additional gain error. Limit the filter resistor values to below 1 kΩ.

fC = 1 / [2π · (R5 + R6) · CDIFF] (16)

Two common-mode filter capacitors (CCM1 and CCM2) are also added to offer attenuation of high-frequency,
common-mode noise components. Select a differential capacitor, CDIFF, that is at least an order of magnitude
(10x) larger than these common-mode capacitors because mismatches in these common-mode capacitors can
convert common-mode noise into differential noise.

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9.2.2.7 Circuit Implementation

Table 9-2 shows the chosen values for this design.
Table 9-2. Parameters
PARAMETER VALUE
VCM 2.5 V
FSR of ADC ±0.256 V
Output data rate 250 SPS
R1, R3 1 kΩ(1)
R2, R4 5 kΩ(1)
R5, R6 100 Ω(1)
CDIFF 0.22 µF
CCM1, CCM2 0.022 µF

(1) 1% precision resistors used.

Using Equation 7, if VSHUNT ranges from –50 mV to +50 mV, the application circuit produces a differential voltage
ranging from –0.250 V to +0.250 V across the ADC inputs. The ADC is therefore configured at a FSR of ±0.256
V to maximize the dynamic range of the ADC.
The –3 dB cutoff frequencies of the differential low-pass filter and the common-mode low-pass filters are set at
3.6 kHz and 0.36 kHz, respectively.
RSHUNT typically ranges from 0.01 mΩ to 100 mΩ. Therefore, if R1 = R3 = 1 kΩ, a good trade-off exists between
the circuit input impedance and input referred resistor noise as explained in the Noise and Input Impedance
Considerations section.
A simple resistor divider followed by a buffer amplifier is used to generate VCM of 2.5 V from a 5-V supply.
9.2.2.8 Results Summary
A precision voltage source is used to sweep VSHUNT from –50 mV to +50 mV. The application circuit produces
a differential voltage of –250 mV to +250 mV across the ADC inputs. Figure 9-7 and Figure 9-8 show the
measurement results. The measurements are taken at TA = 25°C. Although 1% tolerance resistors are used,
the exact value of these resistors are measured with a Fluke 4.5 digit multimeter to exclude the errors resulting
from inaccuracy of these resistors. In Figure 9-7, the x-axis represents VSHUNT and the black line represents the
measured digital output voltage in mV. In Figure 9-8, the x-axis represents VSHUNT, the black line represents
the total measurement error in %, the blue line represents the total measurement error in % after excluding the
errors from precision resistors, and the green line represents the total measurement error in % after excluding
the errors from precision resistors and performing a system offset calibration with VSHUNT = 0 V. Table 9-3 shows
a results summary.
Table 9-3. Results Summary(1)
PARAMETER VALUE
Total error, including errors from 1% precision resistors 1.89%
Total error, excluding errors from 1% precision resistors 0.17%
Total error, after offset calibration, excluding errors from 1% precision resistors 0.11%

(1) TA = 25°C, not accounting for inaccuracy of shunt resistor.

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9.2.3 Application Curves

2
250
1.75
200 1.5
1.25
150
Measured Output (mV)

Measurement Error ( )
100 0.75
0.5
50 0.25
0 0
-0.25
-50 -0.5
-100 -0.75
-1
-150 -1.25 Including all errors
-200 -1.5 Excluding resistor errors
-1.75 Excluding resistor errors, after offset calibration
-250 -2
-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 -50 -40 -30 -20 -10 0 10 20 30 40 50
Shunt Voltage (mV) D004 Shunt Voltage (mV) D005
Figure 9-7. Measured Output vs Shunt Voltage Figure 9-8. Measurement Error vs Shunt Voltage
(VSHUNT) (VSHUNT)

9.3 Power Supply Recommendations

The device requires a single unipolar supply, VDD, to power both the analog and digital circuitry of the device.
9.3.1 Power-Supply Sequencing
Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up
reset process to complete.
9.3.2 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. VDD must be decoupled with at
least a 0.1-µF capacitor, as shown in Figure 9-9. The 0.1-μF bypass capacitor supplies the momentary bursts
of extra current required from the supply when the device is converting. Place the bypass capacitor as close to
the power-supply pin of the device as possible using low-impedance connections. Use multilayer ceramic chip
capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for
power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments,
avoid the use of vias for connecting the capacitors to the device pins for better noise immunity. Using multiple
vias in parallel lowers the overall inductance, and is beneficial for connections to ground planes.
VDD
10
TI Device DIN

1 ADDR SDA 9

2 ALERT/RDY VDD 8

3 GND AIN3 7 0.1 µF

4 AIN0 AIN2 6

AIN1
5

Figure 9-9. ADS1115-Q1 Power-Supply Decoupling

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9.4 Layout
9.4.1 Layout Guidelines
Employ best design practices when laying out a printed-circuit board (PCB) for both analog and digital
components. For optimal performance, separate the analog components [such as ADCs, amplifiers, references,
digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers,
complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF)
transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component
placement is shown in Figure 9-10. Although Figure 9-10 provides a good example of component placement, the
best placement for each application is unique to the geometries, components, and PCB fabrication capabilities
employed. That is, there is no single layout that is perfect for every design and careful consideration must always
be used when designing with any analog component.

Ground Fill or Ground Fill or

Optional: Split
Ground Cut
Ground Plane Ground Plane
Supply
Generation
Signal
Conditioning
(RC Filters
Interface
Device Microcontroller
and Transceiver
Optional: Split
Ground Cut
Amplifiers) Connector
or Antenna
Ground Fill or Ground Fill or
Ground Plane Ground Plane

Figure 9-10. System Component Placement

The following outlines some basic recommendations for the layout of the ADS111x-Q1 to get the best possible
performance of the ADC. A good design can be ruined with a bad circuit layout.
• Separate analog and digital signals. To start, partition the board into analog and digital sections where
the layout permits. Route digital lines away from analog lines. This architecture prevents digital noise from
coupling back into analog signals.
• Fill void areas on signal layers with ground fill.
• Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground
plane is cut or has other traces that block the current from flowing right next to the signal trace, the current
must find another path to return to the source and complete the circuit. If the current is forced into a larger
path, longer route increases the chance that the signal radiates. Sensitive signals are more susceptible to
EMI interference.
• Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass
capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active
device yields the best results.
• Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react
with the input bias current and cause an added error voltage. Reduce the loop area enclosed by the source
signal and the return current in order to reduce the inductance in the path. Reduce the inductance to reduce
the EMI pickup, and reduce the high frequency impedance observed by the device.
• Differential inputs must be matched for both the inputs going to the measurement source.
• Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best
input combinations for differential measurements use adjacent analog input lines such as AIN0, AIN1 and
AIN2, AIN3. The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G
(NPO), which have stable properties and low-noise characteristics.

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9.4.2 Layout Example

ADDR

ALERT/RDY

SDA

SCL
VDD

1 ADDR SCL 10

2 ALERT/RDY SDA 9
AIN0 AIN3
3 GND TI Device VDD 8

4 AIN0 AIN3 7

5 AIN1 AIN2 6

AIN2
AIN1

Vias connect to either bottom layer or

an internal plane. The bottom layer or
internal plane are dedicated GND planes

Figure 9-11. ADS1115-Q1 VSSOP Package

ALERT/RDY

ADDR

SDA
SCL

VDD

AIN0 AIN3
10
1 9
2 8
3 7
4 6
5

AIN1 AIN2

Vias connect to either bottom layer or

an internal plane. The bottom layer or
internal plane are dedicated GND planes

Figure 9-12. ADS1115-Q1 UQFN Package

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10 Device and Documentation Support

10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA333-Q1 Automotive, 1.8-V, Micropower, CMOS, Zero-Drift Operational Amplifier data
sheet
• Texas Instruments, MSP430F20x3, MSP430F20x2, MSP430F20x1 Mixed-Signal Microcontrollers data sheet
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: ADS1113-Q1 ADS1114-Q1 ADS1115-Q1

 PACKAGE OPTION ADDENDUM

www.ti.com 30-Apr-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ADS1113BQDGSRQ1 ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 19L6 Samples

ADS1114BQDGSRQ1 ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 19K6 Samples

ADS1115BQDGSRQ1 ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 19J6 Samples

ADS1115QNKSRQ1 ACTIVE UQFN NKS 10 5000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 N4J Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Apr-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS1113-Q1, ADS1114-Q1, ADS1115-Q1 :

• Catalog : ADS1113, ADS1114, ADS1115

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-May-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1113BQDGSRQ1 VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADS1114BQDGSRQ1 VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADS1115BQDGSRQ1 VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADS1115QNKSRQ1 UQFN NKS 10 5000 180.0 8.4 1.8 2.35 0.7 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-May-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1113BQDGSRQ1 VSSOP DGS 10 2500 366.0 364.0 50.0
ADS1114BQDGSRQ1 VSSOP DGS 10 2500 366.0 364.0 50.0
ADS1115BQDGSRQ1 VSSOP DGS 10 2500 366.0 364.0 50.0
ADS1115QNKSRQ1 UQFN NKS 10 5000 213.0 191.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP SEATING PLANE
4.75

A PIN 1 ID 0.1 C
AREA

8X 0.5
10
1

3.1
2.9 2X
NOTE 3 2

5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4

0.23
TYP
SEE DETAIL A 0.13

0.25
GAGE PLANE

0.7 0.15
0 -8 0.05
0.4

DETAIL A
TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10

SYMM

8X (0.5) 5 6

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10

SYMM
8X (0.5)

5 6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221984/A 05/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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