LOGIC GATES

Digital Signals
 A digital signal has two discrete levels or values. Two representations
of digital signals are as shown below.

5V 5V

High Low
3.5V 3.5V

1V 1V
Low High
0V 0V
(a) (b)
 In each case there are two discrete levels and the levels can be
represented using the terms LOW and HIGH. Fig (a), the lower of the
two levels has been designated as LOW and higher level as HIGH level.
In Fig. (b), the designation has been reversed.
 Digital systems using the representation in Fig. (a) are said to employ
positive logic system and those using the other representation of Fig.
(b) are said to employ negative logic system.

Truth Tables
 A truth table is means of describing how a logic circuit’s output
depends on the logic levels present at the circuit’s inputs e.g.
Inputs Outputs
A B X
0 0 0
0 1 1
1 0 1
1 1 0
 Truth table for three or four inputs can also been drawn depending on
the inputs present at circuit.

Boolean Expression
 It’s a simple mathematical tool allows the description of the
relationship between logic circuit output (s) and its inputs as an
algebraic equation e.g.
A B B  A  B

BASIC LOGIC GATES

 Logic gates are the basic building blocks for forming digital electronic
circuitry. It has one output terminal and one or more input terminals.
 Some of these gates include:-
a) INVERTER (or NOT gate)

1
b) AND gate
c) OR gate
d) NAND gate
e) NOR gate
f) Exclusive-OR gate (EXOR)
g) Exclusive-NOR gate

 The INVERTER, AND and OR gate are the basic gates. The NAND,
NOR, Exclusive-OR and Exclusive-NOR gates are derived gates.

(i) The INVERTER or NOT gate

 Its gate that performs inversion (or complementation) operation. It has
one input (A) and one output (B).
 Its logic symbols are as shown.

1
A Y A Y

(a) (b)
 The truth table of a NOT gate is

Input Output
A Y
0 1
1 0

 The operation of a NOT gate can be expressed in the Boolean

expression as
XA
It states that the output X is complement or opposite of the input
A i.e. X = 0 if
A = 1, and X = 1 if A = 0.
 AN electronic implementation this gate is as shown.
5V(VCC )

Vo
Vi
Inverter electronic circuit

 When Vi is low (0 V) transistor is cut off and is unable to conduct,

thus full voltage of Vcc is available at the output. Whereas when

2
 Vi is high (+5 V), it will make the transistor to conduct and thus
giving a low Vo

(ii) The AND gate

 It’s composed of 2 or more inputs and a single output. Its logic
symbol for 2-input AND gate is as shown.

A
Y
B

 The truth table of a 2-input AND gate is

Inputs outputs
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

Logic operation: An AND gate produces a HIGH (1) output only when
all of the inputs are HIGH (1) else the output is LOW (1).
Example 1 Determine the total number of possible input combinations
of a 3-input AND gate. Sketch a logic symbol and develop a truth table
for this logic gate.
Solution
 
A 3-input AND gate has eight possible combination i.e. 2 3  8 . The
symbol and truth table of a 3-input AND gate is as shown.

A
B Y
C

Inputs Outputs
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

3
Exercise: Determine the total number of possible input combinations of a
4-input AND gate. Sketch a logic symbol and develop a truth table for this
logic gate.

Pulse operation of an AND gate

Example 2 Consider the two waveforms below:-

A
A Y
B
B

t1 t2 t3 t4 t5 t6
 Hence, applying the rules of AND gate as shown in the truth
table, the output Y as shown in obtained.
Example 3 The Fig. below shows two input waveforms, A and B applied
to an AND
gate.

1
A 0
A Y
1
B B
0

1
Y
0
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

Boolean Expression for an AND gate

 The operation of an AND gate can be expressed in the Boolean
expression

Y  AB
 The AND operation can be extended to more than two variables. For
example, the three and four input AND operation Boolean expressions
are expressed as:-

Y  ABC and Y  ABCD

 The electronic implementation this gate is as shown below.

4
 5V
D1
A
D2 Y
B
AND electronic circuit
 When inputs A and B are low, both diodes are connected to +5 V and
thus they are forward biased and conduct pulling down the output to
low value. If one input is low, the diode with low input conducts
pulling down the output to low. If both inputs are high, both diodes
being reversed biased get cut-off and supply voltage, high appears at
the output, hence it’s through table.

(iii) The OR gate

 OR gate is also basic logic gate from which all logic functions are
constructed. It composed of two or more input and one output. The
symbol of a 2-input OR gate and its truth table is shown.

A
Y
B

 The truth table of a 2-input OR gate is

Inputs outputs
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

Logic operation: An OR gate produces a HIGH (1) output when any of

the inputs are HIGH (1) else the output is LOW (1).

Example 4 Determine the total number of possible input combinations

of a 3-input OR gate. Also draw a logic symbol and develop a truth
table for this logic gate.

Solution
 
 A 3-input OR gate has eight possible combination i.e. 2 3  8 . The
symbol and truth table of a 3-input OR gate is as shown.

5
 A
B Y
C

Inputs Outputs
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Exercise: Determine the total number of possible input combinations of a

4-input OR gate. Sketch a logic symbol and develop a truth table for this
logic gate

Pulse operation of an OR gate

Example 5

A Y
B B

t1 t2 t3 t4 t5
Example 6 The Fig. below shows the two input waveforms A and B
applied to an OR gate. The resulting output is as shown in waveform Y.

A
A Y
B B

t1 t2 t3 t4 t5 t6 t7 t8
Exercise: The Fig. below shows the three input waveforms, A, B, and C
applied to an OR gate. Sketch the resulting output waveform at Y.

6
 A

A
B B Y
C

Boolean expression for an OR Gate

 OR gate operate on the Boolean expression
Y  AB
 For a three or four input OR gates, the Boolean expressions
becomes

Y  A  B  C and Y  A  B  C  D
 The electronic implementation this gate is as shown below
D1
A
D2 Y
B
OR electronic circuit
 If both inputs are low (0), then both diodes do not conduct, giving
low (0) output at Y.If any input is is high, the diode with that high
input conducts, giving high (1) output. If both inputs are high,
both diodes conduct, giving high (1) output.

UNIVERSAL LOGIC GATES

 They are referred to as universal logic gates because they can be used
to realize any logic expression. They are derived from the basic logic
gates. These are NAND and NOR gates.

The NAND gate

 The term NAND is a contraction of NOT-AND. It implies an AND

function with a complemented (or inverted) output. The standard logic
symbol for a 2-input NAND gate is as shown.

A
Y
B

 The small circle (or a bubble) on its output denotes the inversion
operation. Thus a NAND gate operates like an AND gate followed by a
NOT as show below.

7
 A
Y
B

 It truth table a 2-input NAND is

Inputs outputs
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

Logical operation of the NAND gate

 NAND gate produces a LOW (0) output only when all the inputs are
HIGH (1). When any of the inputs is LOW (0), the output will be HIGH
(1).

Pulsed Operation of a NAND Gate

 In order to determine the output level of an NAND gate, we look at the

inputs with respect to each other with reference to the truth table.
Some examples are given below

Example 7

A
A Y
B
B

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

Example 8 The figure below shows the two waveforms applied to the
NAND gate inputs. Determine the resulting output waveform.

8
 1
A 0
A Y
1
B
B 0
1
Y 0
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

Exercise Sketch the output waveform for the 3-input NAND gate shown
in the figure below showing its proper time relationships to the inputs

1
A 0

1 A
B B Y
0
C
1
C
0

Boolean Expression for the NAND Gate

 The Boolean expression representing NAND function is
Y  AB
 This expression means that the two input variables, A and B are
first ANDed and then inverted (or complemented) as indicated by
the bar over the AND expression.
 For a three and four input OR gates, the Boolean expressions
becomes
Y  ABC and Y  ABCD

The NOR gate

 The term NOR is a contraction of NOT-OR. It implies an OR

function with a complemented (or inverted) output. The standard
logic symbol for a 2-input NOR gate is as shown.

A
Y
B

 The small circle (or a bubble) on its output denotes the inversion
operation. Thus a NOR gate operates like an OR gate followed by a
NOT as show below.
9
 A
Y
B

 It truth table a 2-input NOR is

Inputs outputs
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

Logical operation of the NAND gate

 The NOR gate produces a LOW (0) output when any of the inputs is
HIGH (1). The output is HIGH (1) only when all of the inputs are LOW
(0).

Pulsed Operation of a NOR Gate

Example 10 Consider waveforms A and B applied at the inputs of a 2-

input NOR gate as shown.

A
A Y
B B

t0 t1 t2 t3 t4 t5 t6

Exercise Sketch the output waveform for a 3-input NOR gate shown
below, showing the proper time relationships to the inputs.

1
A
0
1 A
B 0 Y
B
C
1
C 0

t0 t1 t2 t3 t4 t5 t6

10
Boolean Expression for a NOR gate
 The Boolean expression representing NAND function is
Y  AB
 This expression means that the two input variables, A and B are first
ORed and then inverted (or complemented) as indicated by the bar
over the OR expression.
 For a three and four input OR gates, the Boolean expressions
becomes
Y  A  B  C and Y  A  B  C  D

The Exclusive-OR and Exclusive-NOR gates

 Both these gates are formed by combination of the basic gates i.e.
Inverter, AND and OR gates. But because of their fundamental
importance in many applications, they are treated as basic logic gates
with their unique symbols.

The Exclusive- OR (XOR) gate

 Unlike other gates, this gate has only two inputs and one output. Its
logic symbol is as shown.

A
Y
B

 The truth table of a 2-input XOR gate is

Inputs output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Logic Operation
 The output is HIGH (1) only when the two inputs are at opposite logic
levels. The output is LOW (0) when the two inputs are at the same
logic levels.

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Pulsed Operation of a XOR Gate

Example 11 Consider the two waveforms, A and B being the inputs of an

XOR gate shown. The output waveform is as shown in Y.

1
A
0
1 A Y
B 0 B

1
Y 0

t1 t2 t3 t4 t5

Exercise Sketch the output waveform for an XOR gate with the input
waveforms as shown in the figure below.

1
A
0
A
Y
1 B
B 0

t1 t2 t3 t4 t5 t6 t7 t8

Boolean Expression for a XOR gate

 The Boolean expression representing XOR function is

Y  A  B  AB  AB

The Exclusive-NOR (XNOR) gate

 It has only two inputs and one output. Its logic symbol is as shown.
A
Y
B

 The truth table of a 2-input XNOR gate is

Inputs output
A B Y
0 0 1
0 1 0
1 0 0
1 1 1

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Logic Operation
 The output of this gate is HIGH (1) only when the two inputs are at
the same logic level. The output is LOW (0) when the two inputs are at
opposite logic levels.

Pulsed Operation of a XNOR Gate

 To determine the output waveform, we look at the inputs with respect

to each other with reference to the truth table. Some examples are
given below:-

Example 12 Consider the two waveforms, A and B being the inputs of an

XOR gate shown. The output waveform is as shown in Y.

1
A
0
A Y
1
B 0 B

1
Y 0

t1 t2 t3 t4 t5 t6 t7

Exercise Sketch an output waveform for an exclusive-NOR gate with the

input waveforms as shown below.

1
A 0
A
Y
1 B
B
0

Boolean Expression for a XNOR gate

 The Boolean expression for an XNOR gate is given by the equation

Y  A  B  A B  AB

Determination of Boolean Expression for a Logic Circuit

 Irrespective of how complex a logic circuit is, it can completely be

described using the Boolean expressions.
 Consider the circuit below

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 A
B
Y = (A.B) + C
C

 Also consider the circuit below

A A+B
B
Y = (A + B).C
C

Example 13 Write the Boolean expression for output Y for logic circuit
shown the figure below.

A A
A B  C
B
C Y  A  B C A D
AD

D AD

Example 14 Write the Boolean expression for output Y for logic circuit
shown the figure below.

A A B (A B) C
B (A B) C
C
(A B) C  D
D
Y
E

 Thus, the Boolean expression for the final output is


Y  ( A  B)C  D E
Exercise Determine the Boolean expression for the output X for the logic
circuit shown in the figure below.

14
 A
B
C

D
Y
E

Evaluating the Boolean Expression for the Logic Circuit Output

 After obtaining the Boolean expression as shown above, the output
logic can be determine for any set of input levels. The following
general rules are followed.
(i) First, perform all inversions of single terms; i.e. 0  1 or 1  0
(ii) Then perform all operations within parentheses.
(iii) Perform an AND operation before an OR operation unless
parentheses indicates otherwise
(iv) If an expression has a bar over it, perform the operation of the
expression first then invert the result.

Example 15 Suppose we want to know the logic level Y for the circuit
below for the case where A  0, B  1, C  1and D  1 .
A A A B
B A B
B
Y  (A B) BC
C

Substituting the values of the variables A, B, and C into the output

expression have
Y  ( A  B )BC
Y  ( 0  1)1.1
Y  (1  0)1.1
Y  (1)1.1
Y  0.1.1
0

Determination of a Truth table for a Logic Circuit

 Once the Boolean expression for all the possible combination of the
inputs variables have evaluated as shown above, the result can be
summarized in a truth table.
 To illustrate this concept, consider the circuit below.

15
 A A B
B
Y (A B)(B C )

C C B C

 We can then evaluate all the possible combination of the input

variables and determine the logic level of the final output. The results
are as shown in the table below.

Inputs output
A B C Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

Implementing Logic Circuits from Boolean Expression

 A logic circuit can be implemented directly from Boolean expression.

For example, a circuit defined by Y  ABC , can be implemented using a
3-input AND gate. If on the other hand a circuit is defined by Y  A B ,
then a two-input OR with an NOT gate on one of the input terminal is
used to implement it. This can be extended to more complex logic
circuits.

Example 16 Construct a circuit whose output is Y  AC BC ABC

Solution
 The expression has three terms (AC, BC, ABC) which are ORed together.
Hence it shows that a 3-input OR gate is required with inputs equal
to AC, BC, and ABC , respectively i.e.

AC Y  AC BC ABC

BC
A BC

 Since each OR gate input is an AND product term, then it means that
an AND gate with appropriate inputs can be used to generate each of
these terms i.e.

16
 A AC

B BC Y  AC BC ABC

C

A BC

Example 17 Sketch the logic circuit for the Boolean expressions:

a) (A B) C
b) AB C

Solution
(a) A A B
A
B
B (A B) C
C

(b) A AB
A
B AB C
C C

Exercise Construct the logic circuits that can implement the Boolean
expressions:
a) Y  AB AB
b) Y  W PQ
c) Y  AB(C D)
d) Y  (A B CDE)  BCD

The Universality of NAND and NOR Gates

 These gates can be used to implement the basic gates as well as each
other.

The NAND gate as a universal logic gate

 An INVERTER can be made from a NAND gate by connecting all of its
inputs together i.e.
A Y  A.A  A

17
  It can be used as an AND gate as
A AB Y  AB
B

 It can also be implemented as an OR gate as

A A

Y  A B  A B

B B

The NOR gate as a universal logic gate

 Like NAND, NOR gate can be used to implement the INVERTER i.e.
A Y  A A  A

 An OR can be performed by connecting a 2-input gates as shown

A A B Y  A B  A B
B

 An AND gate operation can be performed by connecting 3 NOR gates

as show.
A A
Y  A B  AB

B B

ASSINGMENT 2

1. Realize the following logic operations using only NOR gates

a) NAND (b) XOR (c) XNOR [10 marks]

2. Realize the following logic operations using only NAND gates

a) NAND (b) XOR (c) XNOR [10 marks]

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COMBINATIONAL LOGIC DESIGN
Introduction
 Boolean algebra theorems are used for the manipulations of logic
expressions. The number of gates and the number of input terminals
for the gates required for the realization of a logical expression, in
general, get reduced considerably if the expression can be simplified.
 Basically, digital circuits are divided into two broad categories:
(i) Combinational circuits, and
(ii) Sequential circuits
 In combinational circuits, the outputs at any instant of time depend
upon the inputs present at that instant of time. Thus, these circuits
have no memory.
 There are other types of circuits in which the outputs at any instant of
time depend upon the present inputs as well as the past
inputs/outputs. This implies that they have memory. Such circuits
are known as sequential circuits.
 The design requirements of combinational circuits may be specified in
any of the following ways:
(i) A set of statements
(ii) Boolean expression, and
(iii) Truth table

Boolean algebra and logic simplification

Boolean algebra is a convenient and systematic way of expressing and

analyzing the operation of logic circuits. It’s named after George Boole
who invented it.

Laws and rules of Boolean algebra

1) OR Rules
(i) A 0  A
(ii) A 1  1
(iii) A A  A
(iv) A A  1
2) AND Rules
(i) A .0  0
(ii) A .1  A
(iii) A . A  A
(iv) A . A  0

3) Laws of Complementation
(i) 0  1
(ii) 1  0
(iii)If A  1, then A  0

19
 (iv) If A  0, then A  1
(v) A  A

4) Commutative laws
These laws allow changes of position of variables in OR and AND
expressions
(i) A B  B A
(ii) A . B  B. A

5) Associative laws
These laws allow removal of brackets from logic expressions and
regrouping of variables.
(i) A (B C)  (A B)  C
(ii) (A B)  (C D)  A B C D
(iii) A.(B.C)  (A.B).C

6) Distributive laws
These laws permit factoring or multiplying out of an expression
(i) A(B C)  AB AC
(ii) A BC  (A B)(A C)
(iii) A AB  A B

7) Absorptive laws
These laws are used in reduction of a complex expression to a simpler
form by absorbing some of the terms into existing terms
(i) A AB  A
(ii) A(A B)  A
(iii) A(A B)  AB

Example 1: Prove the following Boolean identity AC ABC  AC

Solution
AC ABC  AC(1  B) (But 1  B  1)
Then
AC(1  B)  AC.1  AC
 AC ABC  AC

Example 2 Prove that the following Boolean identity

(A B)(A C)  A BC
Solution
Let y  (A B)(A C)
 AA AC BA BC
 A AC BA BC
 A(1 B)  AC BC

20
  A AC BC
 A(1  C)  BC
 A BC

Example 3 Prove the following Boolean identity A AB  A B

Solution
Let y  A AB
 A .1  AB
 A(1  B)  AB
 A AB AB
 A B(A A)
 A B
Example 4 Using the truth table, show that the Boolean expression
A AB  A

A B AB A+AB
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1

Hence, from the table, the columns of A and A+AB are the same and
hence A AB  A

Example 5 Using the truth table, show that the Boolean, A AB  A B

A B A AB A AB A+B
0 0 1 0 0 0
0 1 1 1 1 1
1 0 0 0 1 1
1 1 0 0 1 1

 An inspection of the fifth and sixth columns indicates that they are
the same. This verifies that A AB  A B

Example 6 Using the truth table, show that the Boolean expression,
( A  B)( A  C )  A  BC

A B C A+B A+C (A+B)(A+C) BC A+BC

0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 1 1 1 1

21
 1 0 0 1 1 1 0 1
1 0 1 1 1 1 0 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1

The sixth and the eighth columns are the same. This verifies that
( A  B)( A  C )  A  BC

Example 7 Using the Boolean laws and rules simplify the expression and
implement the minimized expression using logic gates: y  ABD ABD
Solution
y  ABD ABD
 AB(D D) (Using distributive law)
 AB(1) (Using the rule A A  1 )
 AB
B
Y  AB
A

Example 8 Using the Boolean laws and rules, simplify the following
expression and implement the minimized expression using logic gates:
x  ACD ABCD
Solution
x  ACD ABCD
 (A AB) CD (Using distributive law)
 (A B) CD (Since A AB  A B )
A A B
B
Y  (A B) CD
C CD
D

Example 9 Using Boolean algebra techniques, simply the expression:

z  AB A(B C)  B(B C)
Solution
z  AB A(B C)  B(B C)
 AB AB AC BB BC (Using distributive law)
 AB AB AC B BC (Since BB  B )
 AB AC B BC (Since AB AB  AB )
 AB AC B (Since B B C  B )
 AC B (Since AB B  B )

22
 B z  B AC
A
C AC

Example 10 Using laws and rules of Boolean algebra simplify the Boolean
the following expression and implement the simplified expression.
z  [AB(C BD)  AB] C
Solution
z  [AB(C BD)  AB] C
 (ABC ABBD AB) C (Using distributive laws)
 (ABC A .0. D AB) C (Since BB  0 )
 (ABC 0  AB) C (Since A .0. D  0 )
 ABC C ABC (Using distributive laws)
 ABC ABC (Since CC  C )
 (A A) BC (Factoring out BC )
 1. BC (Since A A )
 BC

B
z  BC
C

Exercise
(i) Simplify the following Boolean expression and draw the logic
circuits for the simplified expressions.
a) y  ABC ABC ABC BC (ans: AC B )
b) y  B(A C)  C(A B)  AC (ans: AB C )
c) z  ABC ABC ABC ABC ABC (ans: AB BC BC )

De Morgan’s Theorem

 De Morgan proposed the following theorems that are an important

part of Boolean algebra:
Theorem 1: The complement of a product of variables is equal to the
sum of the complements of the variables i.e.
AB  A B
Theorem 2: The complement of a sum of variables is equal to the
product of the complements of the variables i.e.
A B  A . B
 In terms of logic circuits, theorem 1 can be illustrated as

23
 A A
AB A B
B B

 In terms of logic circuits, theorem 2 can be illustrated as

A A
A B A.B
B B

Example 11 Apply De Morgan’s theorems to the following Boolean

expressions with 3
variables:
a) XYZ and
b) X  Y  Z
Solution
a) XYZ , applying De Morgan’s theorem 1
XYZ = X Y Z
b) X  Y  Z applying De Morgan’s theorem 2
X  Y  Z = X.Y. Z

Example 12 Using Boolean algebra simplify the following expression.

Z  AB AC  ABC
Solution
Z  (AB).(AC)  A B C
 (A B).(A C)  ABC
 AA AC AB BC ABC
 A  AC  AB  BC
 A  AB  BC
 A  BC

Example 13 Simplify the Boolean expression

T ( x, y, z)  ( x  y)[ x ( y  z )]  xy  xz
Solution
Given the Boolean expression
T ( x, y, z)  ( x  y)[ x ( y  z )]  xy  xz
 ( x  y)[ x  ( y  z )]  xy  xz
 ( x  y)[ x  ( y.z )]  xy  xz
 ( x  y)( x  yz )  xy  xz
 xx  xyz  xy  yyz  xy  xz
 x  xyz  xy  yz  xy  xz
 x(1  yz  y)  yz  xy  xz
 x  yz  xy  xz

24
  ( x  xy )  yz  xz
 x  y  yz  xz
 ( x  xz )  ( y  yz )
 xz  yz
 x  y  ( z  z)
 x  y 1
1

Exercise
(i) Simplify the following expression using De Morgan’s theorem and
Boolean algebra laws and rules
a) Y  ( B  C )( B  C )  A  B  C
b) Z  (C  D)  A CD  ABC  ABCD  ACD
c) ABCD

ASSINGMENT 3

(i) Prove the following Boolean identity (A B)(A B)(A C)  AC

(ii) Prove the following Boolean identity A  B  A  B  A B
(iii) Prove the following identity ABC ABC ABC  A(B C)
(iv) Simplify the following Boolean expression
ABC  AB C  A BC  ABC  AB C
(v) Simplify the following expression and show the minimum gate
implementation. y  ABC D ABC D BCD
(vi) Simplify the following expression using De Morgan’s theorem
and Boolean algebra laws and rules
a) W  RST .( R  S  T )
b) X  ABC  ABC  ABC  ABC  AB C
c) A( B  C ) D

SIMPLIFICATION OF LOGIC CIRCUITS

Broadly there are two methods to simplify Boolean algebra:

(i) Simplification using Boolean algebra and
(ii) Simplification using Karnaugh maps.

(i) Simplification using Boolean algebra

This method is as had been explained earlier. Such a simplification leads

to the simplification of logic circuit.

25
Example 14 Determine the Boolean expression for the output of the logic
circuit shown below.
Solution
The Boolean expression for the output of the logic circuit is,
Y  BC ( AB  C )
Simplifying the expression, have
Y  BC ( AB  C )
 BC ( AB.C )
 BC ( AB.C )
 BC[ A  B ]C
A
B

C
Y

 BC[ A C  B C ]
 A BCC  BCB C
 A BC  0
 A BC
The simplified expression can be implemented as

A
Y ABC
B

C
Example 15 Figure (a) below shows a logic circuit with the inputs A and
B. The waveforms at the inputs are also shown in figure (b). Determine the
minimized circuit and then sketch the waveform at the output.
10 ms

A
A 10 ms
B Y

(a) B

5 ms 5 ms
(b)
Solution
The output of the logic circuit is Y  ( A  B ).B
Applying the De Morgan’s theorem 1 to the terms on the right, have

26
 Y  A B  B
 A B  B
 A B
B
Y
A

The resulting waveform at Y is obtained by adding the waveforms at A

and B and is as shown.

10ms

5ms

Y  A B

Example 16 Using Boolean algebra minimize the logic circuit shown

below.

A Y
B

Solution
The output of the logic circuit is Y  A  ( A  B )
Applying De Morgan’s theorem 2 to the right side, have,
Y  A .( A  B )
 A( A  B )
 AA  AB )
 A  AB )
 A(1  B )
A
Hence, a minimized logic circuit has no logic gate. The output is equal to
the value of A itself. In other words the given logic circuit is redundant.

Example 17 The circuit shown below is used to implement the function

Z  f ( A, B)  A  B . What values should be selected for I and J.

27
 J
I
A Y

Solution
The above circuit is redrawn as shown below.
J
I A I Y  A B
1
A 4

3
2 A J
A
Y  ( A  J )( A  I )
 A A  AI  AJ  JI
 0  AI  AJ  JI
 AI  AJ  JI
Since the output Y is given to be equal to A  B , therefore,
A  B  AI  AJ  JI
Comparing the terms on the left and right on the above equation, have
that,
A  AJ …………………….……………(i) and
B  A I  JI ……………………………...(ii)
From equation (i), if J  1 then A  A.1 . Hence J  1
From equation (ii), B  ( A  J ) I  ( A  1) I  1.I  I ,
Thus, J  1 and B  I

STANDARD FORMS OF BOOLEAN EXPRESSIONS

Each Boolean expression can be converted into either of two forms:

(i) Sum-of-Product (SOP) form or
(ii) Product-of-Sum (POS) form

(i) Sum-of-Product (SOP) Form

In Boolean algebra, a product term (also called min-term) is the product
of literals (or Boolean variables). In logic circuit circuits, a product term
is produced by AND operation with no OR operation
e.g. AB , AB , ABC , AB CD .
A product term is equal to 1 if and only if each of the literals in the term
is 1. Its equal to 0 when one or more of the literals are 0.

28
When two or more product terms are ORed, the resulting expression is
called a Sum-of-Product (SOP) e.g. AB  BCD ,
ABC  CDE  B CD , AB  A BE  B D .
SOP expression can contain a single variable term but a single overbar
cannot extend over more than one variable, although more than one
variable in a term can have an overbar e.g. A BC can be a term in SOP
expression but not ABC .

Domain of a Boolean expression

The domain of a Boolean expression is the set of variables contained in
the expression in either complemented or uncomplemented form e.g. the
domain of the expression AB  A BC is the set of variables, A, B and C. D.

Implementation of Sum-of-Products (SOP) Expression

SOP expressions can be implemented by AND-OR logic. For example,

implement the SOP expression AB  A BC  AC .

A
B

A Y  AB ABC AC
B
C

A
C

NB: The no. of AND gates is equal to the number of terms in the sum-
of-products expression.

Conversion of a General Expression to Sum-to-Products (SOP) Form

Any logic expression can be converted to SOP using Boolean laws e.g.
A( BC  D)  ABC  AD

Example 19: Convert the following Boolean expressions to SOP form.

a) ( A  B)(C  B )
b) ( A  B C )C

Solution
a) ( A  B)(C  B )  AC  AB  BC  BB
 AC  AB  BC  0

29
  AC  AB  BC
b) ( A  B C )C  AC  B CC
 AC  B C

d) Standard Sum-of-Product Form

A standard SOP expression is one in which all the variables in the

domain appear in each product term of the expression e.g.
ABC D  A BCD  ABCD . If in any product term one of the literals is
missing, then the expression is a non-standard SOP expression e.g.
AB C  ABD  AC
Standard SOP expressions are very important in constructing the truth
table or the K-map.

Conversion of Product term to a Standard Sum-of-Product (SOP)

Form

The procedure is as follows:-

(i) Identify the non-standard product terms in the given expression.
Multiply each such product term by a term made up of the sum of a
missing variable and its complement
(ii) Repeat step (i) until all resulting product terms contain all variables in
the domain in either complemented or uncomplemented form.

Example 20 Convert the Boolean expression AB C  A B  ABC D to

standard SOP form.
Solution
AB C  A B  ABC D  AB C[ D  D]  A B[C  C ][ D  D ]  ABC D
 AB CD  AB CD  [ A BC  ABC ][ D  D ]  ABC D
 AB CD  AB CD  A BCD  A BCD  ABC D  ABC D  ABC D

Example 21 Convert AB C  B CD  AC D to a standard SOP form.

Solution
AB C  B CD  AC D  AB C[ D  D ]  B CD[ A  A ]  AC D[ B  B ]
 AB CD  AB CD  AB CD  A B CD  ABC D  AB C D

(ii) The Product-of-Sums (POS) Form

In the Boolean algebra, a sum term (or max-term) is the sum of literals or
variables e.g. A  B , A  B  C , A  D etc.
A sum term is equal to 1 when one or more of the literals in the term are
1 and equal to 0 iff each of the literal is 0 e.g
( A  B )( A  B  D )( A  B  C  D) or ( A  B  C )( A )( A  B )

30
The Standard form of POS

A standard POS expression is one in which all the variables in the

domain appear in each sum term of the expression e.g.
( A  B  C  D)( A  B  C  D )( A  B  C  D )
If one of the literals is missing in any max-term, then the expression is
non-standard e.g. ( A  D )( A  B  D )( A  B  C  D)

Converting a Sum Term to a Standard Product-of-Sums (SOP) Form

The procedure is as follows:-
(i) Identity the non-standard sum term in the given expression. To each
non-standard sum term, add a product term consisting of a missing
variable and its compliment
(ii) Apply the following rule of algebra : A  BC  ( A  B)( A  C )
(iii)Repeat step (i) until all sum terms contain all variables in the domain
in either complemented or uncomplemented form.

Example 22 Convert the following Boolean expression to its standard form

( A  B  C )( B  C  D)( A  B  C  D)
Solution
Given ( A  B  C )( B  C  D)( A  B  C  D)
( A  B  C  DD )( AA  B  C  D)( A  B  C  D)
( A  B  C  D)( A  B  C  D )( A  B  C  D)( A  B  C  D)( A  B  C  D)

Exercise Convert the Boolean expression ( A  B )( B  C )

Converting Standard Sum-of-Product (SOP) to Standard Product-of-

Sum (POS)

The procedure is as follows:-

(i) Evaluate each product term in the SOP expression i.e. determine the
binary number which represents the product terms.
(ii) Determine all the binary numbers not included in the evaluation in
step (i)
(iii)Write the equivalent sum term for each binary number from step (ii)
and express in POS form.

NB: A similar procedure is used for the reverse.

Example 23 Convert the following Sum-of-Product (SOP) expression toan

equivalent Product-of-Sums (POS) expression.
A B C  A B C  A BC  AB C  ABC

31
Solution
On evaluating each term have
A B C  A B C  A BC  AB C  ABC
000  001  011  101  111
Since the possible combination is 2 3  8 , then the remaining terms are
those for POS i.e. 010, 100 and 110. Since these are binary values that
make the sum term 0, therefore the equivalent POS expression is,
( A  B  C )( A  B  C )( A  B  C )

Convert SOP Expression to Truth Table Format

The procedure is as follows:-
(i) List all the possible combinations of binary values of the variables in
the given expression.
(ii) Convert the SOP expression to standard form if it is not already so
(iii)Place a 1 in the output column (Y) for each binary value that makes
the standard SOP expression a 1 and place a 0 for all the remaining
values.

Example 24 Construct a truth table for the following expression:

A B C  AB C  ABC
Solution
On evaluating each term have
A B C  AB C  ABC
001  100  111 , hence the truth table becomes,

INPUTS OUTPUTS
A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Example 25 Develop a truth table for the following Boolean expressions:

A B  ABC  AC  AB C
Solution
A B  ABC  AC  AB C  A B  ABC  A  C  AB C
Standardizing the expression we have,

32
 A B  ABC  A  C  AB C  A B(C  C )  ABC  A ( B  B )(C  C ) 
C ( A  A )( B  B )  AB C
 A BC  A BC  ABC  A BC  A BC  A B C  A B C  ABC  AB C 
A BC  A B C  AB C
(Some product terms are repeated and one of the repeated terms is
retained while the rest are discarded). Thus, the required expression is,
 A BC  A BC  ABC  A B C  A B C  AB C  AB C
Its truth table is

INPUTS OUTPUTS
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Converting Product-of-Sums (POS) Expression to a Truth Table

Form

Since a POS expression is equal to 0 only if at least one of the sum

terms is equal to 0,
then the procedure is:
(i) List all the possible combinations of binary values of the
variables
(ii) Convert the POS expression to standard form if it is not already
so.
(iii) Place a 0 in the output (Y) for each binary value that makes the
expression a 0 and place a 1 for all the remaining binary values.
Example 26 Construct a truth table for a standard POS expression
( A  B  C )( A  B  C )( A  B  C )
Solution
Given the expression ( A  B  C )( A  B  C )( A  B  C ) , converting to
binary equivalent have (1  1  0)(0  1  1)(0  0  0) . Hence the truth table
becomes,

INPUTS OUTPUTS
A B C Y
0 0 0 0
0 0 1 1

33
 0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1

Example 27 Develop the truth table for the following standard POS
expression
( A  B )( A  B  C )( A  B  D )( A  B  C  D)

Exercise
(i) Find the canonical Sum-of-Products form for the expression
given below
f ( A, B, C )  AB  A B  ABC  AC  A C
(ii) Also find POS expression for the expression in (i).
(iii) Determine the canonical POS form and canonical SOP form of
the Boolean expression f ( A, B, C )  B C
(iv) Find the min terms or canonical SOP form and max terms or
canonical POS form for the function f ( A, B, C )  A C  AC .
(v) Find the max terms or canonical POS form of the function
f ( A, B, C ) , which is represented by the truth table

Decimal value A B C f(A,B,C)

0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 0
6 1 1 0 0
7 1 1 1 1

(vi) Express f ( A, B, C, D)  AB  A BC  C D as the sum of min terms

and as the product of max terms.

The Karnaugh Map (K-Map)

 Another method of minimizing expression is using a K-map. It

provides a simple set procedure for minimizing the Boolean
functions.

34
 K-map is similar to a truth table in that it presents all the possible
values of input variables and the resulting output of each value.
But instead of being organized into columns and rows like a truth
table, the K-map is an array of squares or cells in which each
square represents a binary value of the input variables.
 Each square is denoted by a binary number or its decimal
equivalent e.g. if the function consists of three-variables, then the
K-map has 8(23) squares and for four is 16 (24) squares. These
maps are as shown below:-

a) 2-variable K-map
A
0 1
B

0 AB AB
1 AB AB

b) 3-variable K-map

AB
C 00 01 11 10
0 ABC ABC ABC ABC

1 A BC A BC A BC A BC

c) 4-variable K-map
AB D
C

00 01 11 10
00 A B C D A B C D A BC D A B C D

01 A B C D A B C D A B C D A B C D

11 A BC D A BC D A BC D ABC D

10 A BC D A BC D ABC D ABC D

Minimizing SOP Expression Using K-Map

 Any function to be minimized or to be reduced is first written in
standard Sum-of- Product form and its min-terms are then
written. Each min-term is then converted to its equivalent binary
number and a marking ‘1’ is made in the corresponding square in

35
 the map. This is referred to as mapping a SOP expression on the K-
map.

Example 28 Map the following SOP expression on the K-map:

A B C  A BC  A BC  ABC
Solution

AB
C 00 01 11 10
0 1

1 1 1 1

A B C  A BC  A BC  A BC
Example 29 Map the following standard sum-of-products (SOP)
expression on a K-
map:
A BCD  ABCD  ABC D  A B C D  ABC D  A B C D  AB CD  ABCD
Solution
AB D
C

ABCD 00 01 11 10
00 1 1 A BC D

01 1 1 A BC D

A BC D 11 1 A BC D

10 1 1 1

A BC D ABC D ABC D
Example 30 Map the following non-standard sum-of-products (SOP)
expression on a
K-map: A  A B  ABC
Solution
First the given expression is standardized as follows:-
A ( B  B )(C  C )  A B (C  C )  ABC
 A BC  A BC  A B C  A B C  A B C  A B C  ABC or
 011  010  001  000  001  000  110 or
 011  010  001  000  110

36
 ABC ABC
AB
C 00 01 11 10
0 1 1 1

1 1 1

A BC A BC ABC
 After the Boolean expression has been mapped on the K-map,
there are three steps in the process of obtaining a minimum SOP
expression.
(i) Grouping the 1s – the adjacent 1s are grouped with the objective
of maximizing the size of the groups and to minimize the number
of groups using the following rules:-
a) A group must contain either 1,2,4,8 or 16 squares
b) Each square in the group must be adjacent to one or more
squares in that same group but all squares in the same group
do not have to be adjacent to each other.
c) Always include the largest possible number of 1s in
accordance to rule (a).
d) Each 1 on the K-map must be included in at least one group.
The 1s already in a group can be included in another group as
long as the overlapping groups included non-common 1s.
(ii) Determining the Product term for each group – the minimum
product term and hence the minimum sum-of-products expression
is obtained using the following rule:
a) Each group of squares containing 1s creates one product term
composed of all variables that occur in only one form within the
group are eliminated. These are called contradictory variables.
(iii)
Summing the resulting product terms – all the derived minimum
product terms
are summed together to form the minimum sum-of-product
expression.

Example 31 Simplify the following expression using a K-map:

Y  A B  A B C  ABC  AB C
Solution
 First the given is standardized i.e.
Y  A B(C  C )  A B C  ABC  AB C
 A BC  A BC  A B C  ABC  AB C
 Next the standard SOP expression in mapped on to a K-map i.e.

37
 AB
C 00 01 11 10
0 1 1 1 AC

1 1 1

AC AB
Hence the simplified expression is,
Y  A C  A B  AC

Example 32 Simplify the following SOP expression using the K-map:

Y  A BC D  AB C D  A B C D  ABC D  ABC D  ABCD
Solution
 The expression is already in standard form and therefore its mapped
directly to the K-map.
AB D
C

00 01 11 10
00 1 AB C

01 1 1 1 1 CD

11 1

10

ABD
 Hence the simplified expression is,
Y  ABD  ABC  C D

Example 33 Simplify the following SOP expression using the K-map:

Y  BC D  A BC D  ABC D  A BCD  ABCD
Solution
 First the given is standardized i.e.
Y  1. BC D  A BC D  ABC D  A BCD  ABCD
 ( A  A ) BC D  A BC D  ABC D  A BCD  ABCD
 ABC D  A BC D  A BC D  ABC D  A BCD  ABCD
 Next the standard SOP expression in mapped on to a K-map i.e.

38
 A
CD B
00 01 11 10

00 1 1
BC

01 1 1

BD
11 1 1

10

 Hence the simplified expression is,

Y  BC  BD

Mapping directly on K-map from a Truth Table

 A truth table representing an output of a Boolean expression can be
mapped directly on a K-map. To illustrate this, consider the truth
table below.

INPUTS OUTPUTS
A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

 On mapping it becomes,
AB

00 01 11 10
C

0 1

1 1 1 1 1

Example 34 Implement the following Boolean expression using

minimum number of 3-input NAND gates.

f ( A, B, C, D)   (1, 2, 3,4, 7, 9,10,12)

Solution

39
 The expression above can be represented in form a truth table as,

Decimal INPUTS OUTPUTS

number
A B C D F
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0

 Then the variables in the truth are mapped on a K-map as

A
CD B
00 01 11 10

00 1 1 BC D
BCD
01 1 1

11 1 1
BCD
ACD
10 1 1

 Hence the resulting simplified expression is’

f ( A, B, C, D)  B C D  B C D  A C D  B C D
 This can be implemented using 3-input NAND gates as shown below.

40
 A B C D

BC D

BCD
ACD f

BCD

IMPLICANTS
 When a Boolean expression of four or less variables is represented on
a K-map, then the set of adjacent minterms or the simplified SOP
term are called the implicants of the expression.
(i) Prime-implicant – An implicant is called prime-implicant of the
expression if it is not a subset of any other implicant of the
expression. Each product term individually is a prime-implicant.
(ii) Essential prime-implicant – a prime-implicant which includes a ‘1’
cell, which is not included in any other prime-implicant, on the K-
map, is known as an essential prime-implicant of the function.
AB D
C

00 01 11 10
00 I VI

01 II V

11 III 1 IV

10

 From the above K-map, there are six prime-implicants I, II, III, IV, V
and VI each formed by a pair of two adjacent minterms. Prime-
implicant I and VI are essential prime-implicants because one of their
minterms is not included in any other prime-implicant.

41
 AB
C 00 01 11 10
0 1 1 1

1 1 1 1

 From above K-map, no prime-implicant is essential thus it is called a

cyclic-prime-implicant map. This is because each minterm is
included in at least two implicants.

Example 34 (b): Find the set of prime-implicants and the minimum

expressions of the expression below using s a K-map.
f ( A, B, C, D)    0,1, 2,3, 4,6,8,9,10,11
Solution:
AB D
C

00 01 11 10
00 1 1 1

01 1 1

11 1 1

10 1 1 1

 From the group of 8 cell pairs  0,1, 2,3,8,9,10,11 have a minterm of B

 From the group of 4 cell pairs  0, 2, 4, 6  have a minterm of AD .
 Thus, the two mintems above are prime-implicants. Both are essential
prime-implicants because prime-implicant B contains some mintems
i.e. 1,3,8,9,10,11 which are not included in any other prime-implicant.
Similarly the prime-implicant AD contains some minterms i.e.
4, 6 which are not included in any other prime-implicant.
 The minimum expression is f ( A, B, C, D)  B  AD

‘Don’t Care’ conditions

 In digital design sometimes a situation arises in which some input
variable conditions
are not allowed e.g. in BCD code, there are six invalid combinations.
Since these are unallowed states in BCD code, they can be taken as
either 1 or 0. This is what is called don’t care condition.
 These don’t care terms can be used to advantage on the K-map for
simplification of logic equations. Consider a combinational circuit

42
 which produces a 1 output corresponding to a BCD input equal and
greater than six. The output is 0 if the input is less than six. In form a
truth table, it is as shown.

INPUTS OUTPUTS
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 x
1 0 1 1 x
1 1 0 0 x
1 1 0 1 x
1 1 1 0 x
1 1 1 1 x

 Then this can be mapped on a K-map as,

A
CD B
00 01 11 10
A
00 x 1

01 1 x 1

11 x x x

10 1 x x

BC
 Hence the simplified expression is,

Y  A  BC
Example 35 Consider the K-map shown below. Determine the logic
function represented by the map and simplify it in the minimal form.

43
 A
CD B
00 01 11 10

00 1 x x

01 1 x 1

11 x 1

10 1 x x

Solution

A
CD B
00 01 11 10

00 1 x x

AC
01 1 x 1

BD
11 x 1

10 1 x x BD

The resulting simplified function is,

Y  AC  BD  B D

Minimizing POS expression using a K-map

 The POS expression is obtained from a K-map in the same manner as

it is found from the truth table.

Example 36 Consider a Boolean function f ( A, B, C, D)   (0, 3,12,15) .

 The above SOP expression can be written in POS as,
f ( A, B, C, D)   (0, 3,12,15)  (1, 2, 4, 5, 6, 7, 8, 9,10,11,13,14)
 Thus mapping it to a K-map, we obtained

44
 A
CD B (A B)
00 01 11 10

00 0 0

01 0 0 0 0
(C D)

11 0 0 (A  B)

10 0 0 0 0

(C  D)
 Hence
f ( A, B, C, D)  ( A  B)( A  B )(C  D )(C  D)

Example 37 Obtain the minimal POS expression for the Boolean function
given below using a four variable K-map.
f ( A, B, C, D)  (3, 4, 6, 7,11,12,13,14,15)
Solution

A
CD B (B  D)
00 01 11 10

00 0 0

(A  B)
01 0

11 0 0 0 0 ( C  D)

10 0 0

Hence
f ( A, B, C, D)  ( A  B )( B  D)(C  D )

Example 38 Minimize the multiple-output Boolean function given

below, using four-variable K-map.
f ( A, B, C, D)   (1, 2, 6, 7, 8,13,14,15)   (3, 5,12)
x
Where the min-terms with x are don’t care conditions.
Solution

45
 A
CD B
00 01 11 10

00 x 1 ACD

AB
01 1 x 1
AD

11 x 1 1

10 1 1 1

AC
Hence
f ( A, B, C, D)  AB  A C  AC D  A D

ASSIGNMENT 5

(i) Obtain the minimal SOP expression for the Boolean function
given below using the K-map.
f ( A, B, C, D)   (0, 3, 4, 7, 8)   (10,11,12,13,14,15)
x

(ii) Express the Boolean function, f  A  B C in sum-of min-terms

(iii) Find the set of prime-implicants from the function given below
and obtain the minimum expression/expressions using a K-
map.
f ( A, B, C, D)   (0,1, 2,5,7,8,9,10,13,15)
(iv) Express the Boolean function f  AB  A C in product-of max-
terms.
(v) Express the Boolean function :
f ( A, B, C, D)   (0,1, 2, 5, 8, 9,10) in product-of-sums form
(vi) Simplify the following Boolean functions using K-map:
a) f ( A, B, C )   (0, 2, 3, 4, 6)
b) f ( A, B, C, D)   (0,1, 2, 4,5, 7,11,15)
(vii) Given the logical function f ( A, B, C )  ( A  B  C )( A  B  C ) . Express
it in the standard sum-of-products form.

46
PRACTICAL DESIGNS OF COMBINATIONAL CIRCUIT

 All arithmetic operations can be implemented using adders from basic logic gates.
Some of these logic circuits are discussed below.

The Half-Adder
 The logic symbol of a half adder is as shown

A S

Half - adder

B Cout

 Thus it accepts two inputs and produces two digits on the output: a sum bit (S) and a
carry bit (Cout).
 The truth table of a half-adder is

Inputs outputs
A B S Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

 The Boolean expression for the sum output (S) can be expressed as
S  AB  A B
 A  B ……………………………………………………….…………(1)
 And the Boolean expression for the carry output is
C  AB …………………………………………………………………..(2)
 The two equations can be implemented using logic circuits as
A
S
B

Cout

The Full-Adder
 The logic symbol of a full-adder is as shown

A S

B Full - adder

Cin Cout

47
 A full-adder accepts three inputs (two-input A and B, and a carry input (Cin)) and two
outputs: a sum output (S) and a carry-output (Cout).
 The truth table of a full-adder is

Inputs Outputs
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0` 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

 The Boolean expression for the sum output as obtained from the truth table is
S  A B Cin  A BCin  AB Cin  ABC in ………………………………….…………(3)
 A ( B Cin  BCin )  A( B Cin  BCin )
 A ( B  Cin )  A( B  Cin ) ……………………………..………………………..(4)
 Let Y  B  Cin , then equation (4) can be written as,
S  A.Y  A.Y
 A  Y ……………………………………..……………………………………(5)
 Replacing Y with B  Cin , equation (5) can be written as
S  A  ( B  Cin )
 A  B  Cin ……………………………………………..……………………..(6)

 The Boolean expression for the carry-output is as shown with three ABC in terms
added since it has common factors with each of the other terms.
Cout  A BCin  AB Cin  ABCin  ABC in
 BCin ( A  A)  AB Cin  ABCin
 BCin  AB Cin  ABCin
 Cin ( B  AB )  ABCin
 BCin  ACin  ABCin
 BCin  A(Cin  BCin )
 BCin  AC in  AB ……………………………….…………………………..(7)
 Equation (6) and (7) can be implemented by using logic gates as

48
 A
B
S
Cin

Cout

Full-adder

 A full-adder can also be implemented using two half-adders.

 For a full-adder, the two output equations are,
S  A  B  Cin
and
Cout  A BCin  AB Cin  ABCin  ABC in
 ( A B  AB )Cin  AB(Cin  Cin )
 ( A  B)Cin  AB
 Hence the full-adder logic circuit using two half-adder is

A B Sum
A A S A S
A B C
Half- Half-
adder adder
B B Cout B Cout
(A B) C in
Cin
Carry output

(A B) C in  AB

Parallel Adders
 As shown above, a single full-adder can add two 1-bit numbers and an input carry.
Thus, to add binary numbers with more than one bit, parallel adders are used. To add
two binary numbers, a full adder is required for each bit in the number. Thus, for two-
bit numbers, two full-adders are used. Similarly, four full adders are required to add
four-bit numbers.
 A block diagram of a basic 2-bit parallel adder using two full-adders is as shown.

49
 A1 B1 A0 B0

Cin Cin
A B A B
Full- Full-
adder adder
Cout S Cout S

S2 S1 S0
(MSB) (LSB)
 Similarly, a 4-bit parallel adder can be constructed using four full adders in parallel as
shown.

A3 B3 A2 B2 A1 B1 A0 B0

Cin Cin Cin Cin

A B A B A B A B
Full- Full- Full- Full-
adder adder adder adder
Cout S Cout S Cout S Cout S

S2 S3 S2 S1 S0
(MSB) (LSB)

DECODERS
 A decoder is used to decode the binary information in a digital system by changing it
into some other type of number system, preferably decimal or hexadecimal number
system. It converts an n-bit binary input code into a maximum of 2n unique output
lines.
 A 3 to 8 line decoder is as shown.
 A practical application of this decoder is binary to octal conversion. The input
variables will represent three binary digit number and output will represent the eight
digits in the octal number systems.

ENCODERS
This is just the reverse of decoding. It has 2n or less input lines and n output lines. For
example an octal to binary encoder is as shown below.

50
 D0  CBA

A  LSB  D1  CBA

D 2  CBA

D3  CBA

D 4  CBA
C  MSB 

D5  CBA

D6  CBA

D7  CBA

A 3 to 8 line decoder

A
D0

D1

D2

D3 B

D4

D5

D6 C

D7
Octal to binary encoder

51
MULTIPLEXERS (MUX)
 It is also known as data selector. It accepts several data inputs and selects only one of
them at a time and directs it to a single output line. A 4 line to 1 multiplexer is as
shown below.

S1 S0

I0

I1

Y
I2

I3

4 to 1 line multiplexer
 The logic symbol and truth table of this MUX are

4 1MUX Y Output

S1 S0

Block diagram of MUX

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Exercise:
With the aid of truth tables, draw the logic circuits of the following Multiplexers
a) 2 to 1 MUX
b) 8 to 1 MUX

52
 DEMULTIPLEXER [DEMUX]
 It is also known as data distributor. It does the reverse of the multiplexer i.e. it takes in
a single input and distributes over several outputs. The select inputs will determine or
decide, to which output the data input will be transmitted.
 For example, a 1 to 4 line demultiplexer with it truth table is as shown below.

Inputs Outputs
Data S1 S0 Y3 Y2 Y1 Y0
inputs
I 0 0 0 0 0 1
I 0 1 0 0 1 0
I 1 0 0 1 0 0
I 1 1 1 0 0 0

Exercise:
With the aid of truth tables, draw the logic circuits of the following Multiplexers
c) 1 to 2 DEMUX
d) 1 to 8 DEMUX

I S1 S0

Y0   S2 ,S1  I

Y1   S2 ,S1  I

Y2   S2 ,S1  I

Y3   S2 ,S1  I

1 to 4 line demultiplexer

53
ELEMENTS OF SEQUENTIAL LOGIC CIRCUITS

Introduction
 Unlike combinational logic circuits, sequential logic circuits have memory elements
which store the previous output information of the circuit to be used as feedback.
 A block diagram of a sequential logic circuit is as shown.

Inputs Output
Combinational
circuit Memory
elements

Block diagram of Sequential circuit

 The storage elements are devices capable of storing binary information. The binary
information stored in these elements at any given time defines the state of the
sequential circuit at that time.
 The sequential circuits receive binary information from external inputs. These inputs,
together with the present state of the storage elements, determine the binary of value
of outputs. They also determine the condition for changing the state in the storage
elements. Thus a sequential circuit is specified by a time sequence of inputs, outputs,
and internal states.
 The differences between combinational and sequential circuits are as shown in the
table.

Combinational Circuit Sequential Circuit

Its output at any instant of time depends Its output depends on the present inputs
on input applied simultaneously at that and previous history of inputs
time.
It contains no memory elements It contains at least one memory
elements.
It can be totally described by the set of It s performance is totally described by
output values only. the set of subsequent state values as well
as set of output values.
It is easy to design, due to absence of It is difficult to design due to presence of
memory memory.
Faster in speed because all inputs are Comparatively slower in speed because it
primary inputs applied simultaneously. has secondary inputs also, which are
applied after a delay.
It needs more hardware for its realization. It needs less hardware for its realization
It is expensive in cost. It is cheaper in cost.

54
FLIP-FLOP (FF)
 A general symbol for a flip-flop is as shown.

Q Normal
Flip-flop output
Inputs
Q Inverted
output
Flip-flop Symbol
 It has two outputs labeled as Q and Q that are inverse (or complement) of each
other. When a reference of the state of the flip-flop is made, its usually referring
to the state of its normal (Q) output. There are two operating states of the flip-
flop. One is when Q  1, Q  0 which is called HIGH state or 1 state or SET state.
The other is when Q  0, Q  1 which is called LOW state or 0 state or RESET
state.
 The flip-flop can have one or more inputs as shown in the block diagram. A flip-
flop is also called a latch or bistable multivibrator.

Latch
 It’s the most basic type of flip-flop circuit. When a flip-flop operated without the
clock, it’s referred to as a latch.
 There are two types of latches depending on whether a NAND or a NOR gate is
used to construct it.

NAND gate Latch

 Its construction is as shown

SET
1 Q

2 Q
CLEAR

NAND gate latch

Operation:
 Normally, the SET and CLEAR inputs of the latch are resting in the HIGH state.
 If the output needs to be changed, one of the inputs is changed to LOW.
 For example, when SET = CLEAR = 1, there are two possible output states. If
Q  0 and Q  1 , the inputs of NAND-2 are 0 and 1, which produces Q  1 . The
1 from Q causes NAND-1 to have 1 at both inputs to produce a 0 at Q .The

55
 second case is when Q  1 and Q  0 . This shows that the HIGH from NAND-1
produces a LOW at the NAND-2 output, which in turn keeps the NAND-1 output
HIGH.
 Thus, as long as SET = CLEAR = 1, the output Q  1 and Q  0 .
 If CLEAR=0 AND SET= 1 and the outputs are Q  0 and Q  1 , then Q  0
keeps NAND-2 output HIGH with the LOW at CLEAR having no effect. If
CLEAR = 1, the latch outputs still remains Q  0 and Q  1 .
 This can be summarized in a truth table below:

Inputs Outputs
SET CLEAR
1 1 No change
0 1 Q 1
1 0 Q0
0 0 Q  Q  1 (invalid)

NOR gate Latch

 Its construction is as shown.

SET
1 Q

2 Q
CLEAR

NOR Gate Latch

Operation
 It operation is similar to the NAND gate latch but the SET and CLEAR inputs are
active-HIGH rather than active-LOW. The results are given in the truth table
below.

Inputs Outputs
SET CLEAR
0 0 No change
1 0 Q 1
0 1 Q0
1 1 invalid

56
 (i) SET = CLEAR = 0: This condition is the normal resting state for the
NOR latch. It has no effect on the output state. In other words, Q
and Q will remain in the same state in which they were prior to this input
condition.
(ii) SET = 1, CLEAR = 0: This condition always causes the output to go to
Q  1 state where it will remain even after SET returns to 0.
(iii) SET = 0, CLEAR = 1: This condition will always causes the output to go
to Q  0 state where it will remain even after CLEAR returns to 0.
(iv) SET = 1, CLEAR = 1: This condition tries to set and clear the latch
simultaneously. It produces invalid results and should not be used.

CLOCKED SIGNALS
Digital systems are of two types:
(i) Asynchronous systems: in these systems, the outputs of logic circuits can
change state any time one or more of the inputs change. They are
generally more difficult to design and troubleshoot than a synchronous.
(ii) Synchronous systems: In these systems, the exact time at which the
output can change states are determined by a signal commonly called a
clock.
 Clocked signal is generally a rectangular pulse train as shown in the figure below.

Rising edge Falling edge

1

0
Time
(a) Rectangular pulse train
 A square wave can also be used as clock signal as shown.

Rising edge Falling edge

1

0
(b) Square Wave
 The synchronization in a digital system is accomplished through the use of
clocked flip-flops that are designed to change states on one or the other of the
clock’s transitions
 Clocked flip-flops have a clock input that is labeled as CLK, CK or CP. But CLK
is commonly used. The CLK can either be edge triggered or level-triggered. Edge
triggered means the CLK is activated by a signal transition and is indicated by the
presence of a small triangle on the CLK input. The triggering transition can either

57
 be the rising or the falling edge. The two cases are represented in a block diagram
form as shown.

SET SET
S Q S Q
CLK CLK

R CLR Q R CLR Q

(a) rising edge triggering (b)Falling edge triggering

CLOCKED S-R FLIP-FLOP

 The logic symbol and truth table of an S-R flip-flop are as shown below:

SET
S Q
CLK

R CLR Q

(a) Symbol

INPUTS OUTPUT
S R Q
0 0 Q0 (no change)
1 0 1
0 1 0
1 1 Invalid

(b) Truth table

 Figure (b) shows the truth table for a clocked S-R flip that is triggered by the
rising edge of the clock signal. Its operation can easily understood with the help
of input and output waveforms as shown.
 Note that the flip-flop is not affected by the falling edge of the clock pulses. It
may also be noted that S and R input levels have no affect on the flip-flop except
upon the occurrence of a rising edge of the clock signal.

58
 1
S
0

1
R
0

CLK
0

1
Q
0
No Set Reset Set Set
change

Typical input and output waveforms for a S-R flip-flop

S-R Logic gate implementation

 Below is a simplified version of a internal circuitry of an edge-triggered S-R flip-
flop. The circuit contains three sections:
(i) A basic NOR latch
(ii) A pulse steering circuit and
(iii) An edge-detector circuit

S
1
3 Q

Edge
detector
CLK

4 Q
R 2

Pulse-steering NOR Latch

circuit

Edge-triggered S-R flip-flop

CLOCKED J-K FLIP-FLOP

 The logic symbol and truth table of J-K flip-flop are as shown below:

59
 SET
J Q
CLK

K CLR Q

(a) Symbol

INPUTS OUTPUT
J K Q
0 0 Q0 (no change)
1 0 1
0 1 0
1 1 Q0 (toggles)

(b) Truth table

 Its operation can easily understood with the help of input and output waveforms
as shown

J 1
0

1
K
0

CLK
0

1
Q
0
No Toggle Reset Set No Toggle Reset
change change

Typical input and output waveforms for a J-K flip-flop

 Initially all the inputs are 0, and the Q output is also assumed to be 0, i.e. Q0  0
 When the rising edge of the first clock pulse occurs, J  K  0 condition exists.
Thus the flip-flop does not change its output state, i.e. Q  Q0  0 .
 When the rising edge of the second clock pulse occurs, J  K  1 condition exists.
Thus the flip-flop toggles to its opposite state i.e. Q  Q0  0  1 .

60
 When the rising edge of the third clock pulse occurs, J  0 and K  1 condition
exists. Thus the flip-flop is cleared to the Q  0 state.
 When the rising edge of the fourth clock pulse occurs, J  1 and K  0 condition
exists. This condition sets the output Q to 1 state.
 When the rising edge of fifth pulse occurs, J  1 and K  0 condition exists. This
is the condition that sets the output Q to 1. However since Q is already 1, so it
will remain there. Hence no change in the output state.
 When the rising edge of sixth pulse occurs, J  K  1 condition exists. This is the
condition causes the flip-flop to toggle to its opposite state.
 When the rising edge of seventh pulse occurs, J  0 and K  1 condition exists.
This is the condition causes the clear to Q  0 state.

J-K Logic gate implementation

 Below is a simplified version of an internal circuitry of an edge-triggered S-R
flip-flop. The circuit contains three sections:
(i) A basic NOR latch
(ii) A pulse steering circuit and
(iii) An edge-detector circuit

J
1 Q

Edge
CLK detector

2 Q
K

Internal circuitry of an edge-triggered J-K flip-flop

(iv) The only difference between the internal circuitry of edge-triggered J-K flip-
flop and S-R flip-flop is that in J-K, Q and Q outputs are fed back to the pulse
–steering NOR gates.
(v) It is because of this feedback connection that J-K flip-flop gives the toggle
operation for J  K  1 condition.

THE J-K MASTER-SLAVE FLIP-FLOP

 All the sequential circuits that we have been covered so far have problem (All the
level sensitive sequential circuits have this problem). Before the enable input
changes state from HIGH to LOW, if inputs changes, then another state transition

61
 occurs for the same enable pulse. This sort of multiple transition problem is called
racing. We can overcome this problem using a two stage J-K flip-flop as shown in
the block diagram below.

SET SET
J J Q J Q Q

K K CLR Q K CLR Q Q

CLK
 In the figure above there are two latches, the first latch on RHS is called master
latch and the one on LHS is called slave latch. Master latch is positively clocked
and slave latch is negatively clock.
 The internal logic circuit of the master-slave J-K flip-flop is as shown below.
 During the posive edge of the clock signal, the inputs are first passed on to the
master flip-flop while the the slave flip-flop is disabled. During the the negative
edge of the clock siganal, the master flip-flop is disabled while the slave is
enabled. Hence the output of the master flip-flop becomes the inputs of the slave
flip-flop and are passed as the output Q and Q .

K
Q

CLK

Q
J

CLOCKED D FLIP-FLOP
 The logic symbol and truth table of J-K flip-flop are as shown below:

SET
D Q
CLK

CLR Q

(a) Symbol

62
 Inputs output
D Q
0 Q
1 1

(b) Truth table

 The output Q will go to the same logic level as the present logic level of D input
when the rising edge occurs at the CLK. In other words, the level present at D will
be stored in the flip-flop at the instant the rising edge occurs.
 Consider the waveforms below:

1
D
0

1
CLK
0

1
Q
0

Input and output waveforms to illustrate the operation of clocked D flip-flop

 An implementation of D flip-flop using J-K flip-flop is as shown below.

D J
Q

CLK

Q
K

D-LATCH

 The logic symbol of a D-latch is as shown below:

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 D Q

D-Latch Symbol
 Its logic gate implementation is also as shown below. It consists of two NOR gates
connected as shown with complement inputs. Its truth table is similar to that of a D
flip-flop with the exception that in the later, the inputs are controlled by a clock signal
while in this case the input are not controlled. As the inputs are fed to the gates, they
are manipulated by the gates based on the present levels of the outputs and a next
output is produced. For such a logic circuit, its sometimes difficult to predict the
output of latch.

D Q

T FLIP-FLOP

 This flip-flop is also called a Toggle flip-flop since its outputs toggles
continuously based on the clocked changes its value. It based on the characteristic
of a J-K flip-flop when both its inputs are at logic level 1.
 It logic symbol is as shown:

SET
T=1 J Q
CLK

K CLR Q

Logic symbol for T flip-flop

 The logic gate implementation of this flip-flop look like this:-

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 T=1
Q

Logic circuit of a T flip-flop

 The output of the circuit toggles or changes its state from low to high or from high
to low depending on the previous state of the output at very instant of positive
going edge of the clock signal. Hence it truth table is as shown below

Inputs output
T Q
0 Q
1 1

 Consider the waves below:-

1
T
0
1
CLK
0
1
Q
0

 Based on the truth table of a T flip-flop, its Q output is as shown.

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