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Lecture 9

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3 views33 pages

Lecture 9

Uploaded by

kareemhero755
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We take content rights seriously. If you suspect this is your content, claim it here.
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COMPUTER

ORGANIZATION
Dr. Zahraa Salaheldin Ismail
Lecture 9:
1. Input-Output Configuration
2. Interrupt Program
3. Complete Computer Description
4. Control Signals
Input-Output Configuration
INPUT-OUTPUT CONFIGURATION
INPUT-OUTPUT AND INTERRUPT
INPUT-OUTPUT CONFIGURATION
▪FGI = 1 if there is an input character (INPR is full) (CPU can read the input)
(User can’t enter another character in the keyboard))
▪FGO = 1 if the output Register (OUTR) is empty (CPU can out data) (No data to be
printed)
INPUT-OUTPUT INSTRUCTIONS
INPUT-OUTPUT CONFIGURATION
INPUT-OUTPUT CONFIGURATION
PROGRAM CONTROLLED PROCEDURE
PROGRAM CONTROLLED PROCEDURE
PROGRAM CONTROLLED DATA TRANSFER
INTERRUPT PROGRAM

❑Using the programmed controlled procedure, CPU slowed down due to I/O low speed.
o If there is an instruction wait for the input data. Or there is an instruction to wait for the OUTR to be
empty to write output data.
o The computer is wasting time while checking the flag instead of doing some other useful processing
task.
▪ An alternative is Interrupt.

▪ While the computer is running a program, it does not check the flags. However, when a flag is set, the computer is
momentarily interrupted from proceeding with the current program and is informed of the fact that a flag has been set.
The computer deviates momentarily from what it is doing to take care of the input or output transfer. It then returns to
the current program to continue what it was doing before the interrupt.
INTERRUPT PROGRAM

▪ IEN: (Interrupt-enable flip-flop)


o Can be set and cleared by instructions
o When cleared (with the IOF instruction), the flags cannot interrupt the computer.
o When set to 1 (with the ION instruction), the computer can be interrupted.
 These two instructions provide the programmer with the capability of making a decision as to whether or not to use
the interrupt facility.
FLOWCHART FOR THE INTERRUPT CYCLE
REGISTER TRANSFER STATEMENTS FOR INTERRUPT CYCLE
 The interrupt cycle is equivalent to the execution of the branch and saves return address (BSA) operation.

▪The interrupt cycle :


RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
REGISTER TRANSFER OPERATIONS IN THE INTERRUPT CYCLE
Complete Computer Description
Flowchart for
Computer Operations
COMPLETE COMPUTERDESCRIPTIONMICROOPERATIONS
DESIGN OF BASIC COMPUTER (BC)
CONTROL OF REGISTERS AND MEMORY
CONTROL OF FLAGS
CONTROL OF FLAGS
 J-k flip-flop
CONTROL OF COMMON BUS
DESIGN OF ACCUMULATOR LOGIC
CONTROL OF AC REGISTER
ALU (ADDER AND LOGIC CIRCUITS)

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