Module-1

Introduction to
Digital Design
 Syllabus
• Binary Logic,
• Basic Theorems And Properties Of Boolean Algebra,
• Boolean Functions,
• Digital Logic Gates,
• Introduction, The Map Method,
• Four-Variable Map,
• Don’t-Care Conditions,
• NAND and NOR Implementation,
• Other Hardware Description Language [HDL] – Verilog Model of a
simple circuit.

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 Fundamentals

Introduction to digital 1s and 0s

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Digital Signals
The transition between the two states is called an edge.
When the signal proceeds from HIGH to LOW, it is considered a falling edge,
or negative edge.

Need for Timing Digital

To show the relationship between changes at the input and output in order
to demonstrate the operation of the system. This means the logic states
must be observed over time.
Timing diagrams show the relationship, over time, between many digital
“signals.”

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Analog and Digital Representations
Analog representation a quantity is represented by a
continuously variable, proportional indicator.
E.g.
• Speedometer
• Thermometers
Digital representation the quantities are represented not by
continuously variable indicators but by symbols called digits.
E.g.
• Digital Speedometer
• Digital indoor/outdoor thermometer

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Digital Number Systems [Decimal System]
The decimal system is composed of 10 numerals or symbols. These 10 symbols are 0,
1, 2, 3, 4, 5, 6, 7, 8, 9. The decimal system, also called the base-10. Decimal position
values as powers of 10.

Binary System
Unfortunately, the decimal number system does not lend itself to convenient
implementation in digital systems.
For example, it is very difficult to design electronic equipment so that it can work with 10
different voltage levels.
It is very easy to design simple, accurate electronic circuits that operate with only
two voltage levels.
For this reason, almost every digital system uses the binary (base-2) number system
as the basic number system of its operations. Binary position values as powers of
2.
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Binary Counting

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Parallel and Serial Transmission
Parallel transmission uses one connecting line per bit, and all bits are
transmitted simultaneously.
Serial transmission uses only one signal line, and the individual bits are
transmitted serially (one at a time).

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Digital Computers
Major Parts of a Computer
A sequence of instructions, called a
Input unit program, that operates on given data.
Output unit
Memory unit
Arithmetic/logic unit
Control unit

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• The signals in most present‐day electronic digital systems use
just two discrete values and are therefore said to be binary. A
binary digit, called a bit, has two values: 0 and 1.
• Discrete elements of information are represented with groups
of bits called binary codes.
• The general‐purpose digital computer is the best‐known
example of a digital system.
• Digital systems can be made to operate with extreme
reliability by using error‐correcting codes.
• An example of this strategy is the DVD, in which digital
information representing video, audio, and other data is
recorded without the loss of a single item.
• Computer capacity is usually given in bytes. A byte is equal to
eight bits and can accommodate one keyboard character

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 Binary logic

• Binary logic deals with variables that take on two discrete

values and with operations that assume logical meaning.
• The two values the variables assume may be called by different
names (true and false, yes and no, etc.), in terms of bits and
assign the values 1 and 0.
• The binary logic is equivalent to an algebra called Boolean
algebra.
• Binary logic consists of binary variables and a set of logical
operations. The variables are designated by letters of the
alphabet, such as A, B, C, x, y, z, etc., with each variable having
only two distinct possible values: 1 and 0.
• There are three basic logical operations: AND, OR, and NOT.
Each operation produces a binary result, denoted by z.

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 Binary logic
1. AND: This operation is represented by a dot. For example, x.y = z or xy = z is read
“x AND y is equal to z.” The logical operation AND is interpreted to mean that z = 1
if and only if x = 1 and y = 1; otherwise z = 0.
2. OR: This operation is represented by a plus sign. For example, x + y = z is read “x
OR y is equal to z,” meaning that z = 1 if x = 1 or if y = 1 or if both x = 1 and y = 1. If
both x = 0 and y = 0, then z = 0.
3. NOT: This operation is represented by a prime(sometimes by an overbar). For
example, x` = z (or 𝑥ҧ = z ) is read “not x is equal to z,” meaning that z is what x is
not. In other words, if x = 1, then z = 0, but if x = 0, then z = 1. The NOT operation is
also referred to as the complement operation, since it changes a 1 to 0 and a 0 to 1,
i.e., the result of complementing 1 is 0, and vice versa.

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 Binary logic
• Binary logic should not be confused with binary arithmetic.
• One should realize that an arithmetic variable designates a
number that may consist of many digits. A logic variable is
always either 1 or 0.
• For example, in binary arithmetic, we have 1 + 1 = 10 (read
“one plus one is equal to 2”), whereas in binary logic, we have
1 + 1 = 1 (read “one OR one is equal to one”).
• For each combination of the values of x and y, there is a value
of z specified by the definition of the logical operation.
Definitions of logical operations may be listed in a compact
form called truth tables.
• A truth table is a table of all possible combinations of the
variables, showing the relation between the values that the
variables may take and the result of the operation.

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 Logic Gates
• A logic gate is a digital circuit with 1 or more input voltages
but only 1 output voltage.
• Logic gates are the fundamental building blocks of digital
systems.
• By connecting the different gates in different ways, we can
build circuits that perform arithmetic and other functions
associated with the human brain. Because the circuits
simulate mental processes, gates are often called logic circuits.
• NOT, OR & AND gates are the basic types of gates.
• The inter-connection of gates to perform a variety of logical
operations is called logic design.
• The operation of a logic gate can be easily understood with
the help of "truth table".
• A truth table lists all possible combinations of inputs and the
corresponding outputs.

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• The input signals x and y in the AND and OR gates may exist in one of four possible
states: 00, 10, 11, or 01.

• The timing diagrams illustrate the idealized response of each gate to the four input
signal combinations.
• The horizontal axis of the timing diagram represents the time, and the vertical axis
shows the signal as it changes between the two possible logic values.
• The NOT gate is commonly referred to as an inverter.

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 Basic Gates
• NOT GATE (INVERTER)
• It is a gate with only 1 input and a complemented output.

• AND GATE
• This is a gate with 2 or more inputs. The output is HIGH only
when all inputs are HIGH.

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 Basic Gates
• OR GATE
• This is a gate with 2 or more inputs. The output is HIGH
when any input is HIGH.

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Logic Gates
• NOR GATE
• This represents an OR gate followed by an inverter.

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Logic Gates
• NAND GATE
• This represents an AND gate followed by an
inverter.

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EXCLUSIVE-OR (XOR) GATES
• The exclusive-OR gate has a high output only when
an odd number of inputs is high.

• Y = A⨁B

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EXCLUSIVE-NOR (XNOR) GATES-2
• EX-NOR Gate
• Truth Table
A B Y
0 0 1 A
Y
0 1 0 B
1 0 0
1 1 1

• Y = A⨀B
ഥB
• Y = AB + A ഥ or Y = A⨁B

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 Boolean Algebra
• In 1854, George Boole developed an algebraic system now called
Boolean algebra.
• In 1938, Claude E. Shannon introduced a two‐valued Boolean
algebra called switching algebra.
• For the formal definition of Boolean algebra, we shall employ the
postulates formulated by E. V. Huntington in 1904.
• Each gate input is labelled with a variable.
• Each appearance of a variable or its complement in an
expression will be referred to as a literal.
• The following expression, which has three variables, has 10 literals
• ab′c + a′b + a′bc′ + b′c′
• A truth table (also called a table of combinations) specifies
the values of a Boolean expression for every possible
combination of values of the variables in the expression.

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27-09-2024 Module-1 23
• Redundant Terms: The Term not or no longer needed or useful.
(A + BC)(A + D + E) = A + AD + AE + ABC + BCD + BCE
= A(1 + D + E + BC) + BCD + BCE
= A + BCD + BCE
• The Consensus Theorem
• Useful in simplifying Boolean expressions.
• The consensus theorem can be used to eliminate redundant
terms from Boolean expressions.
• E.g. XY + X′Z + YZ,
• the term YZ is redundant and can be eliminated to form the equivalent
expression XY + X′Z. The term that was eliminated is referred to as the
consensus term.
• Given a pair of terms for which a variable appears in one term
and the complement of that variable in another, the consensus
term is formed by multiplying the two original terms together,
leaving out the selected variable and its complement.
• E.g. The consensus of ab and a′c is bc;
• The consensus of abd and b′de′ is (ad)(de′) = ade′.
• The consensus of terms ab′d and a′bd′ is 0.

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• F= a’b’c+a’bc+ab’
• DeMorgan’s theorem for three variables: (x + y + z)’ = x’y’z’ and (xyz)’ = x’ + y’ + z’
• Determine whether the following Boolean equation is true or false.
x’y’ + x’z + x’z’ = x’z’ + y’z’ + x’z
• For the Boolean function F = xy’z + x’y’z + xy + x’y
(a) Obtain the truth table of F.
(b) Draw the logic diagram, using the original Boolean expression.
(c) Use Boolean algebra to simplify the function to a minimum number of literals.
(d) Obtain the truth table of the function from the simplified expression and show that it is
the same as the one in part (a).
• Write the Boolean equations and draw the logic diagram of the circuit whose
outputs are defined by the following truth table:

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• Find the complement of the functions F1 = x’yz’ + x’y’z and
F2 = x(y’z’ + yz).

• A simpler procedure for deriving the complement of a

function is to take the dual of the function and complement
each literal.

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• Solve
1. (x+y)(x+y’)
2. 𝐴 + 𝐵 (𝐴ҧ + 𝐵)
ത
• Prove that, A(A' + C) (A'B + C) (A'BC + C') = 0
• Simplify, Y= (A+ B) (A'(B' + C'))' + A'(B + C)
• Reduce the given Boolean expressions to three number of literals;
(x’y’+z)’+z+xy+wz
• We can perform logical on strings of bits by considering each pair of
corresponding bits separately (called bitwise operation). Given two
eight‐bit strings A = 10110001 and B = 10101100, evaluate the eight‐bit
result after the following logical operations: (a) AND (b) OR (c) XOR
• A digital system has a 4-bit input from 0000 to 1111. Design a logic circuit
that produces a high output whenever the equivalent decimal input is
greater than 13.
• We need a circuit with 2 inputs and 1 output. The output is to be high only
when 1 input is high. If both inputs are high, the output is to be low. Draw
a sum-of-products circuit for this.
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 Boolean Algebra
• An expression is said to be in sum-of-products (SOP)
form when all products are the products of single
variables.
• E.g. AB′ + CD′E + AC′E′
• A sum-of-products expression can be realized using one or
more AND gates feeding a single OR gate at the circuit
output.
• An expression is in product-of-sums (POS) form when
all sums are the sums of single variables.
• E.g. (A + B′)(C + D′ + E)(A + C′ + E′)
• A product-of-sums expression can be realized using one or
more OR gates feeding a single AND gate at the circuit
output.

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• A prime implicant is a product term obtained by combining the
maximum possible number of adjacent squares in the map.
• If a minterm in a square is covered by only one prime implicant, that
prime implicant is said to be essential.
Find the minterms of the following Boolean expressions by first plotting
each function in a map:
(a)xy + yz + xy’z (b) C’D + ABC’ + ABD’ + A’B’D
Find all the prime implicants for the following Boolean functions, and
determine which are essential;
F (A, B, C, D) = (0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
Simplify the following Boolean expressions, using four-variable maps:
Y= A’B’C’D’ + AC’D’ + B’CD’ + A’BCD + BC’D
Simplify the Boolean function
F (w, x, y, z) = (1, 3, 7, 11, 15)
which has the don’t-care conditions, d (w, x, y, z) = (0, 2, 5)

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1. Simplify the Boolean function, using K-Map
F (w, x, y, z) = (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
2. Simplify the Boolean function,
F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’
3. For the Boolean function
F = AC + AB + ABC + BC
(a) Express this function as a sum of minterms.
(b) Find the minimal sum-of-products expression.
4. Simplify the following Boolean function F, with the don’t-care
conditions d;
F(A, B, C, D) = Σm(5, 6, 7, 12, 14, 15)
d(A, B, C, D) = Σd( 3, 9, 11, 13)

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• F = AB + CD Implement using NAND gate only
• Implement the following Boolean function with NAND gates:
F (x, y, z) = (1, 2, 3, 4, 5, 7)
• F = (A + B)(C + D)E Implement using NOR gate only
• Draw a NAND logic diagram that implements the complement
of the following function:
F(A, B, C, D) = Σm (0, 1, 2, 3, 6, 10, 11, 14)
• Draw a logic diagram using only two-input NOR gates to
implement the following function:
F(A, B, C, D) = (A B)’(C D)
• Implement the following Boolean function F, together with the
don’t-care conditions d, using no more than 2 input NOR gates:
F(A, B, C, D) = Σm (2, 4, 10, 12, 14),
d(A, B, C, D) = Σd (0, 1, 5, 8)
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 Hardware Description Language [HDL]
• Manual methods for designing logic circuits are feasible only when the circuit is
small.
• Practically designers use computer-based design tools. Computer-based design
tools leverage the creativity and the effort of a designer and reduce the risk of
producing a flawed design.
• Prototype integrated circuits are too expensive and time consuming to build, so
all modern design tools rely on a hardware description language to describe,
design, and test a circuit in software before it is ever manufactured.
• A HDL is a computer-based language that describes the hardware of digital
systems in a textual form.
• It resembles as C, but is specifically oriented to describing hardware structures
and the behavior of logic circuits.
• It can be used to represent logic diagrams, truth tables, Boolean expressions, and
complex abstractions of the behavior of a digital system.
• It describes a relationship between signals that are the inputs to a circuit and the
signals that are the outputs of the circuit.
• HDLs are used in several major steps in the design flow of an integrated circuit:
design entry, functional simulation or verification, logic synthesis, timing
verification, and fault simulation.
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• Design entry: The description can be in a variety of forms:
Boolean logic equations, truth tables, a netlist of
interconnected gates, or an abstract behavioral model.
• Logic simulation: Simulation detects functional errors in a
design without having to physically create and operate the
circuit. Errors that are detected during a simulation can be
corrected by modifying the appropriate HDL statements.
• Logic synthesis: The process of deriving a list of physical
components and their interconnections (called a netlist ) from
the model of a digital system described in an HDL. It is similar
to compiling a program in a conventional high-level language.
• Timing verification confirms that the fabricated, integrated
circuit will operate at a specified speed.
• Fault simulation compares the behavior of an ideal circuit with
the behavior of a circuit that contains a process-induced flaw.

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A Verilog code can be written in the following styles:
1.Dataflow style: In this modeling, logic blocks are realized
by writing their Boolean expressions.
2.Behavioral style: In this modeling instead of writing
Boolean expressions, the behavior of the logic block is
described.
3.Structural style: This is a hierarchical design style in
which a logic block is realized in terms of its basic sub-
blocks. A sub-block can be a logic gate or any complex
logic block. In two ways it can be described which are;
1.Gate Level Modeling
2.Module Instantiation
4.Mixed style

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 HDL
• A Verilog model is composed of text using keywords, of which there
are about 100.
• Keywords are predefined lowercase identifiers that define the
language constructs. Examples of keywords are module,
endmodule, input, output, wire, and, or, and not. For clarity,
keywords will be displayed in boldface.
• Any text between two forward slashes ( // ) and the end of the line is
interpreted as a comment and will have no effect on a simulation
using the model.
• Multiline comments begin with / * and terminate with * /.
• Blank spaces are ignored, but they may not appear within the text of
a keyword, a user-specified identifier, an operator, or the
representation of a number.
• Verilog is case sensitive, which means that uppercase and lowercase
letters are distinguishable (e.g., not is not the same as NOT).
• A module is the fundamental descriptive unit in the Verilog
language. The term module refers to the text enclosed by the
keyword pair module . . . endmodule.

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Combinational Logic
Modeled with
Primitives

//Starts the declaration (description) of the module

module name (list of ports)
//Specify which of the ports are inputs and which are outputs
//Internal connections

//List of primitive gates with instantiations of a gate

The name (Simple_Circuit) is an identifier. Identifiers are names

given to modules, variables (e.g., a signal), and other elements of
the language so that they can be referenced in the design.
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• In general, we choose meaningful names for modules. Identifiers are composed of
alphanumeric characters and the underscore (_), and are case sensitive.
• Identifiers must start with an alphabetic character or an underscore, but they
cannot start with a number.
• The port list of a module is the interface between the module and its environment.
The port list is enclosed in parentheses, and commas are used to separate elements
of the list. The statement is terminated with a semicolon (;). In this example, the
ports are the inputs and outputs of the circuit.
• The circuit in this example has one internal connection, at terminal w1, and is
declared with the keyword wire.
• The structure of the circuit is specified by a list of (predefined) primitive gates,
each identified by a descriptive keyword (and, not, or).
• The elements of the list are referred to as instantiations of a gate, each of which is
referred to as a gate instance. Each gate instantiation consists of an optional name
(G1, G2, etc.) followed by the gate output and inputs separated by commas and
enclosed within parentheses. The output of a primitive gate is always listed first,
followed by the inputs. For example, the OR gate is represented by the or
primitive, is named G3, and has output D and inputs w1 and E.
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• The module description ends with the keyword endmodule. Each
statement must be terminated with a semicolon, but there is no
semicolon after endmodule.
• It is important to understand the distinction between the terms
declaration and instantiation.
• A Verilog module is declared. Its declaration specifies the input–
output behavior of the hardware that it represents.
• Predefined primitives are not declared, because their definition is
specified by the language and is not subject to change by the user.
• A Verilog model is a descriptive model. Simple_Circuit describes
what primitives form a circuit and how they are connected. The
input–output behavior of the circuit is implicitly specified by the
description because the behavior of each logic gate is defined.
• Thus, an HDL-based model can be used to simulate the circuit that it
represents.
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 Gate-Level Model with Propagation Delays
• All physical circuits exhibit a propagation delay between the transition of an
input and a resulting transition of an output.
• The association of a time unit with physical time is made with the ‘timescale
compiler directive.
‘timescale 1ns/100ps
• The first number specifies the unit of measurement for time delays. The
second number specifies the precision for which the delays are rounded off, in
this case to 0.1 ns.
• If no timescale is specified, a simulator may display dimensionless values or
default to a certain time unit, usually 1ns.

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 Test Bench
• In order to simulate a circuit with an HDL, it is necessary to apply
inputs to the circuit so that the simulator will generate an output
response. An HDL description that provides the stimulus to a design is
called a test bench.
• In its simplest form, a test bench is a module containing a signal
generator and an instantiation of the model that is to be verified. Note
that the test bench has no input or output ports, because it does not
interact with its environment.
• Within the test bench, the inputs to the circuit are declared with
keyword reg and the outputs are declared with the keyword wire.
• The module Simple_Circuit_prop_delay is instantiated with the instance
name M1. Note that using a test bench is similar to testing actual
hardware by attaching signal generators to the inputs of a circuit and
attaching probes (wires) to the outputs of the circuit.
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 A test bench for simulating the circuit with delay,
shown below

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27-09-2024 Module-1 42
• The initial keyword is used with a set of statements that begin
executing when the simulation is initialized; the signal activity
associated with initial terminates execution when the last
statement has finished executing.
• The initial statements are commonly used to describe
waveforms in a test bench.
• The set of statements to be executed is called a block statement
and consists of several statements enclosed by the keywords
begin and end.
• A second initial statement uses the $finish system task to
specify termination of the simulation.

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• Boolean equations describing combinational logic are specified in Verilog
with a continuous assignment statement consisting of the keyword assign
followed by a Boolean expression.
• To distinguish arithmetic operators from logical operators, Verilog uses the
symbols (&), (|), and (~) for AND, OR, and NOT (complement), respectively.
For example circuit; assign D = (A && B) || (!C);
• A circuit that is specified with the following two Boolean expressions:
E = A + BC + B’D
F = B’C + BC’D’
• The simulator detects when the test bench changes a value of one or more of
the inputs. When this happens, the simulator updates the values of E and F.

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Draw the logic diagram of the digital circuit specified
by the following Verilog description:

module Circuit_1 (A, B, C, D, F);

Input A, B, C, D;
output F;
wire w, x, y, z, a, d;
or (x, B, C, d);
and (y, a ,C);
and (w, z ,B);
and (z, y, A);
or (F, x, w);
not (a, A);
not (d, D);
endmodule
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 User-Defined Primitives
• The logic gates used in Verilog descriptions with keywords and, or, etc., are
defined by the system and are referred to as system primitives.
• The user can create additional primitives by defining them in tabular form.
These types of circuits are referred to as user-defined primitives (UDPs).
• It proceeds according to the following general rules:
• It is declared with the keyword primitive , followed by a name and port
list.
• There can be only one output, and it must be listed fi rst in the port list and
declared with keyword output.
• There can be any number of inputs. The order in which they are listed in
the input declaration must conform to the order in which they are given
values in the table that follows.
• The truth table is enclosed within the keywords table and endtable.
• The values of the inputs are listed in order, ending with a colon (:). The
output is always the last entry in a row and is followed by a semicolon (;).
• The declaration of a UDP ends with the keyword endprimitive.
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primitive UDP_02467 (D, A, B, C);
output D;
input A, B, C;
table //Truth table for D = f (A, B, C) = Σm(0, 2, 4, 6, 7);
0 0 0 : 1; // A B C : D;
0 0 1 : 0;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive

module Circuit_with_UDP_02467 (e, f, a, b, c, d);

output e, f;
input a, b, c, d
UDP_02467 (e, a, b, c);
and (f, e, d); // Option gate instance name omitted
endmodule
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