Comparative experimental study of junctionless and inversion-

mode nanowire transistors for analog applications

D. Bosch1,2, J.P. Colinge1, J. Lugo1, A. Tataridou2, C. Theodorou2, X. Garros1, S. Barraud1, J. Lacord1, B. Sklenard1, M. Casse1,
L. Brunet1, P. Batude1, C. Fenouillet-Béranger1, D. Lattard1, J. Cluzel1, F. Allain1, R. Nait Youcef1, J.M. Hartmann1, C. Vizioz1,
G. Audoit1, F. Balestra2, F. Andrieu1
1
CEA-LETI, Univ. Grenoble Alpes, 17 rue des Martyrs, 38054 Grenoble, France ; email: [email protected]
2
Univ. Grenoble Alpes, IMEP-LAHC, 38000 Grenoble, France

Abstract— We fabricated junctionless and inversion-mode lower performance due to higher access resistance (R0) and non-
monocrystalline nanowire nMOSFETs down to L=18nm gate length optimized junctions (Fig. 3).
and W=20nm width. We demonstrate record performance of nanowire Local variability: matching coefficient AVT is higher for JL/JAM
junctionless transistors for analog applications: AVT=1.4mV.μm devices than IM (1.7/1.4 vs. 1.0 mV.μm, Fig. 6). This degradation with
matching, Av0=62dB gain (L=200nm), fT=126GHz cut-off frequency the channel doping is attributed to Random Dopant Fluctuation [9].
and fMAX=182GHz maximum operating frequency (L=35nm). Analog: we consider a nominal analog transistor width of
Junctionless transistor performances even exceed those of inversion- W=0.24μm, (planar SOI configuration instead of a trigate nanowire
mode ones in terms of back-bias capability, low-frequency noise, hot- structure). The JL/JAM subthreshold slope (SS) is SS=64mV/dec vs.
carrier degradation and fMAX. This is explained by junctionless physics: 61mV/dec for the IM device (Fig. 7). However, back-bias can be
channel length modulation, bulk conduction and high channel-depth leveraged in order to adjust the threshold voltage and tune performance
sensitivity to back bias. [10]. Indeed, back-bias is more effective for wider than for narrower
I. INTRODUCTION devices and it is more effective on JL/JAM than on IM transistors
(Fig.8). Markedly, a negative back-bias applied on JAM moves the bulk
Recent years have seen renewed interest for junctionless CMOS
conduction channel upwards towards the gate, which results in an
transistors because of the relative simplicity of its process integration
improvement of the electrostatic control (SS, gd) and, therefore,
and its potential fabrication at low temperature as a Back-End-Of-Line
improving gm/Id and gm/gd (Figs 9-10). As a result, JAM FETs reach
transistor for a 3D-sequential integration [1]. On the one hand, poly-
analog performances that are slightly better than IM devices, up to an
crystalline silicon or germanium junctionless channels, whose doping is
Av0=20 log(gm/gd)=68dB gain.
activated by a laser anneal, are a promising solution for low-cost and
extremely-low-temperature fabrication [2, 3]. On the other hand, Reliability: we have performed Positive Bias Temperature
monocrystalline Si junctionless channels have already been Instability (PBTI) and Hot Carrier Injection (HCI) (Figs. 11-12). We
demonstrated on either planar Silicon-On-Insulator (SOI) [4], FinFET demonstrate similar PBTI (88 years lifetime at VDD=0.8V) for JL and
[5] or nanowire architectures [6,7]. JAM devices, demonstrating a negligible impact of the channel doping.
However the JL threshold voltage shift is not sufficient for Time-To-
II. DEVICE PROCESS FLOW Failure extrapolation. We speculate it may be due to the thermal budget
We fabricated Inversion-Mode (IM) and JunctionLess nanowire difference, mainly due to the 1050°C spike annealing absence. Better
nMOSFETs down to W=20nm channel width and L=18nm gate length. HCI is measured for JL as compared to IM. It can be explain by a lower
The channel thickness is 11nm. The junctionless devices are made by and shifted to the drain (not underneath the gate dielectric as for
epitaxially growing a 7nm thick in-situ phosphorous (P) doped Si film IM/JAM) peak electric field.
on a 4nm undoped SOI layer. Excellent crystalline quality is obtained Low-frequency drain current noise measurements (Fig.13) show
(Fig.1). After full process integration the final channel doping level is a 31-die average 1/f signature and a slightly lower input-referred gate
uniform and equal to 8.1018 at/cm3. Such channel doping and thickness voltage noise level (SVg) for JAM. Using the Carrier number
are suitable even for the largest devices. The fabrication process is fluctuations with Correlated Mobility Fluctuations model [11] and
outlined in Fig.2. All the devices feature the same gate stack with HfO2 taking into account the series resistance noise (SRsd), we fitted the
dielectrics (equivalent oxide thickness EOT=1nm), TiN + poly-Si and normalized drain current noise at f =10 Hz (Fig.28) to extract the
identical 8nm thick spacer. volumetric oxide effective trap density NT, and the remote Coulomb
Junctionless transistors (named JL) have been fabricated. In order to scattering coefficient αsc for all wafers. We extracted a value of NT ≈
optimize their Source/Drain resistance and to dope only the JL-RSD, a 7.5 1017 eV/cm3 for all cases, reflecting a similar interface quality,
5keV P implantation was carried out in the 17nm thick Raised independently of the conduction mode. This value is also very close to
Source/Drain (RSD) followed by a Solid Phase Epitaxy Regrowth state-of-the-art NT values of high-k-metal-gate CMOS technologies
(SPER) annealing at 525°C 30 min (see Kinetic Monte-Carlo profile on [12]. Concerning αsc, a very similar value (≈ 4×103 Vs/C) is extracted
Fig.2). Note that no lateral dopant diffusion occurs, leading to a small for all wafers, showing that the remote Coulomb scattering is not
doping concentration under the spacer. This process module is suitable affected by the different conduction modes. Finally, SRsd has a
for a 525°C 3D-sequential integration process [8]. Moreover, in order significant impact only for JL, which can be linked to non-optimized
to decorrelate the impact of the channel doping and the source/drain source/drain doping [13].
resistance, we also fabricated so-called Junctionless Accumulation Mobility differences, due to channel doping (see gmMAX in Fig.7),
Mode (JAM) transistors with the same channel doping and RSD are also translated into a cut-off frequency shift, measured at FT=130
thickness as the JL devices but with HDD+LDD implantation + 1050°C GHz for JAM vs. 136 GHz for IM. But JAM exceeds IM devices in
anneal, as for IM MOSFETs. terms of FMAX because of lower gate capacitances CGDS. We
demonstrate a record Fmax=182GHz for JAM nMOS (Fig. 15).
III. DEVICE ELECTRICAL CHARACTERIZATION
IV. CONCLUSION
The Digital ION-IOFF figure of merit (Fig. 3) shows no significant
difference between JAM and IM FET for L=35nm. Also, the parasitic Finally, our Junctionless Accumulation Mode devices feature
gate to SD capacitance CGDS suggests a similar direct overlap controlled record performance among previously published junctionless
by the SD implant (Fig. 4). On the other hand, the JL FET has a nMOSFETs (Fig.16). Thanks to process technology variants, electrical
0.06fF/μm lower CGDS vs. JAM/IM, which cannot be explained by the characterizations and TCAD simulations, we demonstrated that such a
fringe components but rather by a depletion region extending below the technology offers a good tradeoff for mixed analog/digital applications.
spacers in JL transistors (Fig.5). Nevertheless JL devices suffers from

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 tSI:P=7nm Si:P @1e19 at/cm3
CCOV (fF/μm):
GDS(fF/µm):
JAM VDD=0.8V L=35nm
tSI=11nm
tSI=4nm 8
BOX BOX
-6
FDSOI FDSOI W=20nm JAM: 0.48
Spaceur 0
JAM VG=-0.5V
IM: 0.49

IOFF (A/µm)
Active Zone definition + Gate stack (high-k dielectric)+ Spacer+ Raised SD IM L=35nm
KMC JL: 0.42

C (fF)
-8 JL
Phosphorus
profile (at/cm3)
P SD implant (KMC)+ P SD implant (HDD+LDD) 4
525°C anneal (SPER) +1050°C anneal

0
1E+19 5E+20
-10 R0 (Ω.μm):
Raised Silicides + Back-End-of-Line
Depth (nm)

18nm 28nm IM
IM: 250
10

SD JL JAM JAM: 260

S G D S G D S G D JL: 6000 0
11nm 1e20
at/cm3
2e20
at/cm3
2e20
at/cm3 -12 0 4 8 12
20

CHANNEL N HDD+LDD N N+ HDD+LDD i N+ 0 100 200 300 400 500 600 700 800
BOX
FDSOI
BOX
FDSOI
BOX
FDSOI
W (µm)
ION (µA/µm)
Fig.1: TEM cross section of JAM Fig.2: Detailed Process flow for IM Fig.3: ION-IOFF for L=35nm and Fig.4: C(W) and CGDS extraction at
device. Excellent crystalline quality (N+-i-N+), JAM (N+-N-N+) and JL W=20nm. L=35nm. Inset: Schematic with
is observed. (N) devices. parasitic capacitance contributions.
(TCAD) JL
100
JAM AVT=1.7mV.µm W=0.24µm IM VB=10V
VG <VTH: Depletion IM NDIE=28 JAM
80 200
G in Drain region

GmMAX (µS/µm)
300

SS (mV/dec)
JL JL
1021
VT (mV)

VT (mV)
AVT=1.4mV.µm
VTH< VG <VFB: 1017 50 60 IM
Solid: W=0,24µm
150
1010 100 JL Dot: W=0,02µm
JAM
Bulk conduction
107 AVT=1mV.µm
VTH< VFB<VG: 101 VD=0.8V 0
40

0
e- density 0 25 50 0,1 1
0
1
Accumulation layer
(cm-3) 1/sqrt(W.L) (µm-1) L (µm) L (µm)
Fig. 5 : Electron density (SD cut) Fig.6: Pelgrom plot (local Fig.7: gmMAX and SS as a function of Fig.8: Back bias efficiency for
highlighting three operation regimes. variability). L for W=0.24μm. W=0.02μm and W=0.24μm.
solid VB=0 V JAM 0.92 V HCI, T=125°C
300
IM Gain VB L=100 L=200 L=400 T=125°C
IM
109 VG-5y~0.8V
open VB=-10V JAM
AV0 (dB) (V) nm nm nm
-5
10
JL 1E9 JL JL
5 years
TTF(s)

--- model
IM
VT (mV)

0 1 60 50 TTF(s) 104
gd (A/V)

200
VDS=0.8V
IM

L=0.1µm
10 -6
-10 18 65 53 tstress=300s
W=10µm JAM
0.1 10-1 model
0 1 12 51 AC and IM:
JAM

100
VG-5y=0.92V
10-7 -10 64.5 68.8 55 W=240nm
88y @ VDD=0.8V 10-6
0 59 47 38 0 1E-11 L=40nm
JL

1.5 2.0 0 1 2 3
W=0.24µm -10 61.5 65 41 VG(V) VG (V) 10-11
10-8 1 2 3
0.1
L (µm) 1 (a) (b) VD(V)
Fig.9: gd vs. L for VB=0 and VB=- Fig.10: Gain Av0 for different Gate Fig.11: (a) ΔVT as a function of VG Fig.12: Time-To-Failure for HCI.
10V. VB<0 improves electrostatics. length. VB<0 improves Av0. (b) Time-To-Failure for PBTI. The The 5-year criterion is met.
5-year criterion is met.
1E-9 200 This
F=10Hz JAM Ref. [14] [6]
JAM FMAX JAM Work
IM 10-7 IM IM Low-Temp NW/FDS
1E-10 JL Techno NW
FDSOI OI
SID/ID² (/Hz)

JL
SVG (V²/Hz)

NT (x10 ) 17
160 LG (nm) 80 48 35
F (GHz)

8 W=120nm
VG-VT=0V AVT
1E-11
10 -8 6  SC (x10 ) NFINGER=120
3
(mV.μm)
- 4.4 1.4
NDIES=31 4 55 for 45 for 68 for
120 AV0 (dB)
W= 240nm 2
L=40nm L=80nm L=0.2μm
1E-12 FT fT (GHz) 80 >70 126
L= 110nm 0 CNF+CMF
/eV.cm3 V*s/C
10 -9 fmax (GHz) 117 ~90 169
35 45 55 65
-9 -8 -7 -6 -5
100010 10
100 10 10 10 10 30 40 50 60
f (Hz) I (A) L (nm)
D
Fig.13: Input-referred gate voltage Fig.14: Normalized drain current Fig.15: fMAX and fT comparison Fig.16: nMOS junctionless
power spectral density versus power spectral density versus ID. for different L. benchmark for analog FOM.
frequency. Inset: Extracted values of Nt and αsc.
ACKNOWLEDGMENTS: This work was funded by French Public Authorities through the NANO2022, LabEx Minos ANR-10-LABX-55-01& by
the European Research Council (ERC) through My-CUBE project.
REFERENCES: [1]A. Vandooren et al., TED, 2018. [2]J. Lin et al., EDL, 39, 9, p. 1326‑29, 2018. [3]D. Bosch et al., S3S, 2019. [4]C. Lee et al., TED, 2010. [5]T. K.
Kim et al., EDL, 2013. [6]A. Veloso et al., VLSI, 2016. [7]S. Barraud et al, EDL, 2012 [8]J. Micout et al., S3S, 2017. [9]A. Kranti et al., ESSDERC, 2010 [10]R. Trevisoli
et al., EUROSOI, 2015. [11]G. Ghibaudo et al., PSS,91. [12]E.G. Ioannidis et al., SSE, 2014. [13]C. Diaz-Llorente et al., S3S, 2018 [14]A. Vandooren et al., VLSI, 2018.

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978-1-7281-4232-6/20/$31.00 ©2020 IEEE 127 2020 VLSI-TSA