23AID102

ELEMENTS OF
SCHOOL OF ARTIFICIAL COMPUTING- 1
INTELLIGENCE
DESIGN AND
IMPLEMENT PROJECT A

BATCH A - 17 FACULTY INCHARGE

16-BIT HACK CPUVIPIN
A.R.NIRMAL CB.AI.U4AID24001 DR
MANNAVA DAASARADHI CB.AI.U4AID24030
VENUGOPAL
PRAJITH S CB.AI.U4AID24039
SAKTHI CHARUKESH S CB.AI.U4AID24049
Introduction

• The HACK CPU is the central

processing unit for the HACK
computer system.
• It processes instructions written
in the HACK machine language.
• Combines arithmetic, logic
operations, memory, and control
functions.
• This report describes the step-
by-step design and implementation
of a 16-bit HACK CPU using the
NAND2Tetris HDL framework.
Objectives

The project aims to:

Design and implement a 16-bit HACK

CPU capable of executing A-
instructions
Build modularand C-instructions.
components like
registers, an ALU, and a Program
Counter
Test the(PC).
CPU with predefined machine
language programs to ensure
correctness and efficiency.
Methodology

• Integrate functional
components: ALU, registers,
control logic, and memory
access units.
• Implement each component in
HDL.
• Test thoroughly before
integrating into the complete
CPU.
ALU (Arithmetic Logic Unit)

•Performs arithmetic and logical

operations.
•Controlled by six inputs (zx, nx, zy, ny,
f, no).
•Operations include addition,
subtraction, and bitwise AND.
Registers

• Store temporary data during

computation.
• A Register: Holds addresses
or constant values.
• D Register: General-purpose
register for computations.
Program Counter
(PC)

• Keeps track of the next

instruction's address.
• Can:
• Increment by 1 to
fetch the next
instruction.
• Load a new address
for jumps.
• Reset to 0.
16-bit HACK CPU

•Integrates ALU, registers, and

PC.
•Includes control logic for
instruction decoding and
execution.
•Uses instruction memory for
programs and data memory for
intermediate results.
 PROJECT B-6

16-BIT CARRY-SELECT ADDER

WITH VARIABLE BLOCK SIZES
(2-2-3-4-5)
Introduction

Carry-Select Adder (CSA)

is one of the high-speed
In a CSA, several sum and This project introduces a
adders. The most
carry values are 16-bit Carry-Select Adder
significant issues
precomputed, using mux, in Nand2Tetris HDL with
concerning achieving
to produce the final block sizes varied from
acceleration for general
addition operations on outcome for different 2-2-3-4-5 bits to
values of carry in, 0 and optimize performance and
digital systems are
1. minimize the carry delay.
related to carry
propagation delay.
Objectives
• Design and Build a 16-bit Carry-Select Adder: The goal
is to design a 16-bit Carry-Select Adder with block
sizes of 2-2-3-4-5 bits. The design will calculate two
possible sum and carry outputs (for carry-in = 0 and 1)
using carry-select logic, and select the right one using
multiplexers.
• Performance Optimization: By breaking the adder into
blocks of different sizes (2-2-3-4-5), the design aims
to minimize the delay due to carry propagation,
optimizing the adder’s performance.
• Test and Verify the Design: Test the design with a set
of test cases using the Nand2Tetris simulator to ensure
accuracy in computing sum and carry values.
 Full Adder

Multiplexer (1-bit Mux)

Ripple Carry Adders

Approach Multiplexer (n-bit Mux)

Carry Select Blocks

16-bit Carry Select

Adder
Full Adder
• The Full Adder is the basic building block for addition in this project.

• CHIP FullAdder {

• IN a, b, cin;

• OUT sum, cout;

• PARTS:

• Xor(a=a, b=b, out=xor1);

• Xor(a=xor1, b=cin, out=sum);

• And(a=a, b=b, out=and1);

• And(a=b, b=cin, out=and2);

• And(a=a, b=cin, out=and3);

• Or(a=and1, b=and2, out=or1);

• Or(a=or1, b=and3, out=cout);

• }
Multiplexer(1
Bit)
The 1-bit multiplexer selects one of two inputs based on a selector signal.

CHIP Mux {

IN a, b, sel;

OUT out;

PARTS:

And(a=b, b=sel, out=selAndB);

Not(in=sel, out=notSel);

And(a=a, b=notSel, out=notSelAndA);

Or(a=selAndB, b=notSelAndA, out=out);

}
MUX(2 bits)
• CHIP Mux2 {
• IN a[2], b[2], sel;
• OUT out[2];

• PARTS:
• Mux(a=a[0], b=b[0], sel=sel, out=out[0]);
• Mux(a=a[1], b=b[1], sel=sel, out=out[1]);
•}
MUX(3 Bits)
• CHIP Mux3 {
• IN a[3], b[3], sel;
• OUT out[3];

• PARTS:
• Mux(a=a[0], b=b[0], sel=sel, out=out[0]);
• Mux(a=a[1], b=b[1], sel=sel, out=out[1]);
• Mux(a=a[2], b=b[2], sel=sel, out=out[2]);
•}
MUX(4 Bits)
• CHIP Mux4 {
• IN a[4], b[4], sel;
• OUT out[4];

• PARTS:
• Mux(a=a[0], b=b[0], sel=sel, out=out[0]);
• Mux(a=a[1], b=b[1], sel=sel, out=out[1]);
• Mux(a=a[2], b=b[2], sel=sel, out=out[2]);
• Mux(a=a[3], b=b[3], sel=sel, out=out[3]);
•}
MUX(5 Bits)
• CHIP Mux5 {
• IN a[5], b[5], sel;
• OUT out[5];

• PARTS:
• Mux(a=a[0], b=b[0], sel=sel, out=out[0]);
• Mux(a=a[1], b=b[1], sel=sel, out=out[1]);
• Mux(a=a[2], b=b[2], sel=sel, out=out[2]);
• Mux(a=a[3], b=b[3], sel=sel, out=out[3]);
• Mux(a=a[4], b=b[4], sel=sel, out=out[4]);
• }
Ripple Carry Adder(2 Bits)
• CHIP RippleCarryAdder2 {
• IN a[2], b[2], cin; // Two 2-bit input buses and a carry-in
• OUT sum[2], carry; // 2-bit sum output and carry-out

• PARTS:
• // First Full Adder: Adds the least significant bits (LSBs)
• FullAdder(a=a[0], b=b[0], cin=cin, sum=sum[0], carry=carry0);

• // Second Full Adder: Adds the most significant bits (MSBs)

• FullAdder(a=a[1], b=b[1], cin=carry0, sum=sum[1], carry=carry);
• }
Ripple Carry Adder(3 Bits)
• CHIP RippleCarryAdder3 {
• IN a[3], b[3], cin;
• OUT sum[3], cout;

• PARTS:
• FullAdder(a=a[0], b=b[0], cin=cin, sum=sum[0],
cout=carry1);
• FullAdder(a=a[1], b=b[1], cin=carry1, sum=sum[1],
cout=carry2);
• FullAdder(a=a[2], b=b[2], cin=carry2, sum=sum[2],
cout=cout);
• }
Ripple Carry Adder(4 Bits)
• CHIP RippleCarryAdder4 {
• IN a[4], b[4], cin;
• OUT sum[4], cout;

• PARTS:
• FullAdder(a=a[0], b=b[0], cin=cin, sum=sum[0], cout=carry1);
• FullAdder(a=a[1], b=b[1], cin=carry1, sum=sum[1],
cout=carry2);
• FullAdder(a=a[2], b=b[2], cin=carry2, sum=sum[2],
cout=carry3);
• FullAdder(a=a[3], b=b[3], cin=carry3, sum=sum[3], cout=cout);
• }
Ripple Carry Adder(5 Bits)
• CHIP RippleCarryAdder5 {
• IN a[5], b[5], cin;
• OUT sum[5], cout;

• PARTS:
• FullAdder(a=a[0], b=b[0], cin=cin, sum=sum[0], cout=carry1);
• FullAdder(a=a[1], b=b[1], cin=carry1, sum=sum[1], cout=carry2);
• FullAdder(a=a[2], b=b[2], cin=carry2, sum=sum[2], cout=carry3);
• FullAdder(a=a[3], b=b[3], cin=carry3, sum=sum[3], cout=carry4);
• FullAdder(a=a[4], b=b[4], cin=carry4, sum=sum[4], cout=cout);
• }
Carry Select Block (2 bits)
• CHIP CarrySelectBlock2 {
• IN a[2], b[2], cin;
• OUT sum[2], cout;

• PARTS:
• RippleCarryAdder2(a=a, b=b, cin=false, sum=sum0, cout=carry0);
• RippleCarryAdder2(a=a, b=b, cin=true, sum=sum1, cout=carry1);
• Mux2(a=sum0, b=sum1, sel=cin, out=sum);
• Mux(a=carry0, b=carry1, sel=cin, out=cout);
• }
Carry Select Block (4 bits)
• CHIP CarrySelectBlock4 {
• IN a[4], b[4], cin;
• OUT sum[4], cout;

• PARTS:
• RippleCarryAdder4(a=a, b=b, cin=false, sum=sum0, cout=carry0);
• RippleCarryAdder4(a=a, b=b, cin=true, sum=sum1, cout=carry1);
• Mux4(a=sum0, b=sum1, sel=cin, out=sum);
• Mux(a=carry0, b=carry1, sel=cin, out=cout);
• }
Carry Select Block (16 bits)
• CHIP CarrySelectAdder16 {
• IN a[16], b[16], cin;
• OUT sum[16], cout;

• PARTS:
• CarrySelectBlock2(a=a[0..1], b=b[0..1], cin=cin, sum=sum[0..1],
cout=carry1);
• CarrySelectBlock2(a=a[2..3], b=b[2..3], cin=carry1, sum=sum[2..3],
cout=carry2);
• CarrySelectBlock3(a=a[4..6], b=b[4..6], cin=carry2, sum=sum[4..6],
cout=carry3);
• CarrySelectBlock4(a=a[7..10], b=b[7..10], cin=carry3, sum=sum[7..10],
cout=carry4);
• CarrySelectBlock5(a=a[11..15], b=b[11..15], cin=carry4, sum=sum[11..15],
cout=cout);
• }
Testing and Results
Conclusion
•
The 16-bit HACK CPU was successfully implemented,
adhering to the HACK architecture. The modular design
ensured easy debugging and integration of components. The
CPU demonstrated its ability to execute a sequence of
instructions accurately, paving the way for further
advancements in computer design.
• This project successfully designed and implemented
a 16-bit Carry-Select Adder using Nand2Tetris HDL.
The use of modular blocks (2-2-3-4-5 bits) reduced
carry propagation delay, optimizing performance.
The carry-select logic coupled with modularity
provided an efficient solution.
THANK YOU