UNIT 4

8086 MICROPROCESSOR

Dr.V.Sumitra
Pin diagram
Architecture
Internal registers
Interrupts
Addressing modes
Instruction sets
 8086 Microprocessor

Addressing Modes
• Every instruction of a program has to operate on a data.
• The different ways in which a source operand is denoted
in an instruction are known as addressing modes.
1. Register Addressing
Group I : Addressing modes for register and
2. Immediate Addressing immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for memory data
6. Indexed Addressing

7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for I/O ports
10. Indirect I/O port Addressing

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode 40

 8086 Microprocessor Group I : Addressing modes for register and

Addressing Modes immediate data

1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL) ← (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

41
 8086 Microprocessor Group I : Addressing modes for register and
immediate data

Addressing Modes
1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL) ← 08H

8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX) ← 0A9FH
12. Implied Addressing

42
 8086 Microprocessor

Addressing Modes : Memory Access

Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

43
 8086 Microprocessor

Addressing Modes : Memory Access

• 20 Address lines ⇒ 8086 can address up to 220 = 1M bytes
of memory

• However, the largest register is only 16 bits

• Physical Address will have to be calculated Physical Address :

Actual address of a byte in memory. i.e. the value which goes out
onto the address bus.

• Memory Address represented in the form – Seg : Offset (Eg

- 89AB:F012)

• Each time the processor wants to access memory, it takes the

contents of a segment register, shifts it one hexadecimal place to
the left (same as multiplying by 1610), then add the required
offset to form the 20- bit address
16 bytes of contiguous
memory

89AB : F012 → 89AB → 89AB0 (Paragraph to byte → 89AB x 10 = 89AB0)

F012 → 0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
44
 8086 Microprocessor

Addressing Modes : Memory Access

• To access memory we use these four registers: BX, SI, DI, BP

• Combining these registers inside [ ] symbols, we can get different

memory locations (Effective Address, EA)

• Supported combinations:

[BX + SI] [BX + SI + d8]

[SI]
[BX + DI] [BX + DI + d8]
[DI]
[BP + SI] [BP + SI + d8]
d16 (variable offset only)
[BP + DI] [BP + DI + d8]
[BX]

[SI + d8] [BX + SI + d16] [SI + d16]

[DI + d8] [BX + DI + d16] [DI + d16]
[BP + d8] [BP + SI + d16] [BP + d16]
[BX + d8] [BP + DI + d16] [BX + d16]

BX SI
+ disp
BP DI 45
 8086 Microprocessor Group II : Addressing modes for memory
data

Addressing Modes
1. Register Addressing

2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
9. Direct I/O port Addressing
The square brackets around the 1354H denotes
the contents of the memory location. When
10. Indirect I/O port Addressing
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

46
 8086 Microprocessor Group II : Addressing modes for memory
data

Addressing Modes
1. Register Addressing In Register indirect addressing, name of the
register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
7. Based Index Addressing
Example:
8. String Addressing Note : Register/ memory
MOV CX, [BX] enclosed in brackets refer to
9. Direct I/O port Addressing content of register/ memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX) ← (MA) or,

(CL) ← (MA)
(CH) ← (MA +1)
47
 8086 Microprocessor Group II : Addressing modes for memory
data

Addressing Modes
1. Register Addressing In Based Addressing, BX or BP is used to hold the
base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS is
7. Based Index Addressing
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing
0008H ← 08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX) ← (MA) or,

(AL) ← (MA)
48
(AH) ← (MA + 1)
 8086 Microprocessor Group II : Addressing modes for memory
data
Addressing Modes SI or DI register is used to hold an index value for
1. Register Addressing
memory data and a signed 8-bit or unsigned
2. Immediate Addressing 16-bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String Addressing
MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
FFA2H ← A2H (Sign extended)
11. Relative Addressing
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA

(CX) ← (MA) or,

(CL) ← (MA)
(CH) ← (MA + 1)
49
 8086 Microprocessor Group II : Addressing modes for memory
data

Addressing Modes
1. Register Addressing In Based Index Addressing, the effective address
is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH ← 0AH (Sign extended)
7. Based Index Addressing

8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA

10. Indirect I/O port Addressing (DX) ← (MA) or,

11. Relative Addressing (DL) ← (MA)

(DH) ← (MA + 1)
12. Implied Addressing

50
 8086 Microprocessor Group II : Addressing modes for memory
data

Addressing Modes
1. Register Addressing Employed in string operations to operate on string
data.
2. Immediate Addressing
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored in
DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
12. Implied Addressing

Note : Effective address of the (MAE) ← (MA)

Extra segment register
If DF = 1, then (SI) ← (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI) ← (SI) +1 and (DI) = (DI) + 1 51
 8086 Microprocessor Group III : Addressing modes for I/O
ports

Addressing Modes
1. Register Addressing These addressing modes are used to access data
from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL) ← (PORT)
6. Indexed Addressing
Content of port with address 09H is
7. Based Index Addressing
moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.

11. Relative Addressing Example: OUT [DX], AX

12. Implied Addressing Operations: PORTaddr = (DX)

(PORT) ← (AX)

Content of AX is moved to port

whose address is specified by DX
register. 52
 8086 Microprocessor Group IV : Relative Addressing
mode

Addressing Modes
1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing 000AH ← 0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing MA = BA + EA

12. Implied Addressing If ZF = 1, then the program control jumps to

new address calculated above.

If ZF = 0, then next instruction of the

program is executed.
53
 8086 Microprocessor Group IV : Implied Addressing
mode

Addressing Modes
1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

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INSTRUCTION SET
 8086 Microprocessor

Instruction Set
8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

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 8086 Microprocessor

Instruction Set1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to registers, memory
locations and I/O ports.

Generally involve two operands: Source operand and Destination operand of the
same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit data can be
moved to 16-bit register/ memory.

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 8086 Microprocessor

Instruction Set1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2) ← (reg1)

MOV mem, reg1 (mem) ← (reg1)
MOV reg2, mem (reg2) ← (mem)

MOV reg/ mem, data

MOV reg, data (reg) ← data

MOV mem, data (mem) ← data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2) ↔ (reg1)

XCHG mem, reg1 (mem) ↔ (reg1)

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 8086 Microprocessor

Instruction Set1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP) ← (SP) – 2

MA S = (SS) x 16 10 + SP
(MA S ; MA S + 1) ← (reg16)

PUSH mem (SP) ← (SP) – 2

MA S = (SS) x 16 10 + SP
(MA S ; MA S + 1) ← (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 16 10 + SP

(reg16) ← (MA S ; MA S + 1)
(SP) ← (SP) + 2

POP mem MA S = (SS) x 16 10 + SP

(mem) ← (MA S ; MA S + 1)
(SP) ← (SP) + 2
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 8086 Microprocessor

Instruction Set1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORT addr = (DX) OUT [DX], AL PORT addr = (DX)
(AL) ← (PORT) (PORT) ← (AL)

IN AX, [DX] PORT addr = (DX) OUT [DX], AX PORT addr = (DX)
(AX) ← (PORT) (PORT) ← (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL) ← (addr8) OUT addr8, AL (addr8) ← (AL)

IN AX, addr8 (AX) ← (addr8) OUT addr8, AX (addr8) ← (AX)

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 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADD reg2, reg1 (reg2) ← (reg1) + (reg2)

ADD reg2, mem (reg2) ← (reg2) + (mem)
ADD mem, reg1 (mem) ← (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg) ← (reg)+ data

ADD mem, data (mem) ← (mem)+data

ADD A, data

ADD AL, data8 (AL) ← (AL) + data8

ADD AX, data16 (AX) ← (AX) +data16

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 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2) ← (reg1) + (reg2)+CF

ADC reg2, mem (reg2) ← (reg2) + (mem)+CF
ADC mem, reg1 (mem) ← (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg) ← (reg)+ data+CF

ADC mem, data (mem) ← (mem)+data+CF

ADDC A, data

ADD AL, data8 (AL) ← (AL) + data8+CF

ADD AX, data16 (AX) ← (AX) +data16+CF

62
 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2) ← (reg1) - (reg2)

SUB reg2, mem (reg2) ← (reg2) - (mem)
SUB mem, reg1 (mem) ← (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg) ← (reg) - data

SUB mem, data (mem) ← (mem) - data

SUB A, data

SUB AL, data8 (AL) ← (AL) - data8

SUB AX, data16 (AX) ← (AX) - data16

63
 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2) ← (reg1) - (reg2) - CF

SBB reg2, mem (reg2) ← (reg2) - (mem)- CF
SBB mem, reg1 (mem) ← (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg) ← (reg) – data - CF

SBB mem, data (mem) ← (mem) - data - CF

SBB A, data

SBB AL, data8 (AL) ← (AL) - data8 - CF

SBB AX, data16 (AX) ← (AX) - data16 - CF

64
 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8) ← (reg8) + 1

INC reg16 (reg16) ← (reg16) + 1

INC mem (mem) ← (mem) + 1

DEC reg/ mem

DEC reg8 (reg8) ← (reg8) - 1

DEC reg16 (reg16) ← (reg16) - 1

DEC mem (mem) ← (mem) - 1

65
 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX) ← (AL) x (reg8)

For word : (DX)(AX) ← (AX) x (reg16)

MUL mem For byte : (AX) ← (AL) x (mem8)

For word : (DX)(AX) ← (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX) ← (AL) x (reg8)

For word : (DX)(AX) ← (AX) x (reg16)

IMUL mem For byte : (AX) ← (AX) x (mem8)

For word : (DX)(AX) ← (AX) x (mem16)

66
 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL) ← (AX) :- (reg8) Quotient
(AH) ← (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX) ← (DX)(AX) :- (reg16) Quotient
(DX) ← (DX)(AX) MOD(reg16) Remainder

DIV mem For 16-bit :- 8-bit :

(AL) ← (AX) :- (mem8) Quotient
(AH) ← (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX) ← (DX)(AX) :- (mem16) Quotient
(DX) ← (DX)(AX) MOD(mem16) Remainder

67
 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL) ← (AX) :- (reg8) Quotient
(AH) ← (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX) ← (DX)(AX) :- (reg16) Quotient
(DX) ← (DX)(AX) MOD(reg16) Remainder

IDIV mem For 16-bit :- 8-bit :

(AL) ← (AX) :- (mem8) Quotient
(AH) ← (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX) ← (DX)(AX) :- (mem16) Quotient
(DX) ← (DX)(AX) MOD(mem16) Remainder

68
 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags ← (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags ← (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags ← (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

69
 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags ← (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags ← (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

70
 8086 Microprocessor

Instruction Set 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags ← (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags ← (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

71
 8086 Microprocessor

Instruction Set 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

72
 8086 Microprocessor

Instruction Set 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

73
 8086 Microprocessor

Instruction Set 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

74
 8086 Microprocessor

Instruction Set 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

75
 8086 Microprocessor

Instruction Set 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

76
 8086 Microprocessor

Instruction Set 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

77
 8086 Microprocessor

Instruction Set 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

78
 8086 Microprocessor

Instruction Set 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

79
 8086 Microprocessor

Instruction Set
4. String Manipulation Instructions

❑ String : Sequence of bytes or words

❑ 8086 instruction set includes instruction for string movement, comparison, scan, load and store.

❑ REP instruction prefix : used to repeat execution of string instructions

❑ String instructions end with S or SB or SW.

❑ S represents string, SB string byte and SW string word.

❑ Offset or effective address of the source operand is stored in SI register and that of the destination
operand is stored in DI register.

❑ Depending on the status of DF, SI and DI registers are automatically updated.

❑ DF = 0 ⇒ SI and DI are incremented by 1 for byte and 2 for word.

❑ DF = 1 ⇒ SI and DI are decremented by 1 for byte and 2 for word.

80
 8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP

REPZ/ REPE While CX ≠ 0 and ZF = 1, repeat execution of string instruction

and
(Repeat CMPS or SCAS until ZF = 0) (CX) ← (CX) – 1

REPNZ/ REPNE
While CX ≠ 0 and ZF = 0, repeat execution of string instruction
(Repeat CMPS or SCAS until ZF = 1) and
(CX) ← (CX) - 1

81
 8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 16 10 + (SI)

MAE = (ES) x 16 10 + (DI)

(MA E) ← (MA)

If DF = 0, then (DI) ← (DI) + 1; (SI) ← (SI) + 1

If DF = 1, then (DI) ← (DI) - 1; (SI) ← (SI) - 1

MOVSW MA = (DS) x 16 10 + (SI)

MAE = (ES) x 16 10 + (DI)

(MA E ; MA E + 1) ← (MA; MA + 1)

If DF = 0, then (DI) ← (DI) + 2; (SI) ← (SI) + 2

If DF = 1, then (DI) ← (DI) - 2; (SI) ← (SI) - 2

82
 8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string

word
CMPS

CMPSB MA = (DS) x 16 10 + (SI)

MAE = (ES) x 16 10 + (DI)

Modify flags ← (MA) - (MA E)

If (MA) > (MA E), then CF = 0; ZF = 0; SF = 0

If (MA) < (MA E), then CF = 1; ZF = 0; SF = 1
CMPSW If (MA) = (MA E), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI) ← (DI) + 1; (SI) ← (SI) + 1
If DF = 1, then (DI) ← (DI) - 1; (SI) ← (SI) - 1

For word operation

If DF = 0, then (DI) ← (DI) + 2; (SI) ← (SI) + 2
If DF = 1, then (DI) ← (DI) - 2; (SI) ← (SI) - 2

83
 8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with
accumulator
SCAS

SCASB MAE = (ES) x 16 10 + (DI)

Modify flags ← (AL) - (MA E)

If (AL) > (MA E), then CF = 0; ZF = 0; SF = 0

If (AL) < (MA E), then CF = 1; ZF = 0; SF = 1
If (AL) = (MA E), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI) ← (DI) + 1

If DF = 1, then (DI) ← (DI) – 1

SCASW MAE = (ES) x 16 10 + (DI)

Modify flags ← (AL) - (MA E)

If (AX) > (MA E ; MA E + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MA E ; MA E + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MA E ; MA E + 1), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI) ← (DI) + 2

84
If DF = 1, then (DI) ← (DI) – 2
 8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to

AX

LODS

LODSB MA = (DS) x 16 10 + (SI)

(AL) ← (MA)

If DF = 0, then (SI) ← (SI) + 1

If DF = 1, then (SI) ← (SI) – 1

LODSW MA = (DS) x 16 10 + (SI)

(AX) ← (MA ; MA + 1)

If DF = 0, then (SI) ← (SI) + 2

If DF = 1, then (SI) ← (SI) – 2

85
 8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to

string

STOS

STOSB MAE = (ES) x 16 10 + (DI)

(MA E) ← (AL)

If DF = 0, then (DI) ← (DI) + 1

If DF = 1, then (DI) ← (DI) – 1

STOSW MAE = (ES) x 16 10 + (DI)

(MA E ; MA E + 1 ) ← (AX)

If DF = 0, then (DI) ← (DI) + 2

If DF = 1, then (DI) ← (DI) – 2

86
 8086 Microprocessor

Instruction Set
5. Processor Control Instructions
Mnemonics Explanation
STC Set CF ← 1

CLC Clear CF ← 0

CMC Complement carry CF ← CF /

STD Set direction flag DF ← 1

CLD Clear direction flag DF ← 0

STI Set interrupt enable flag IF ← 1

CLI Clear interrupt enable flag IF ← 0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor which shares the
address and data bus with the 8086

LOCK Lock bus during next instruction 87

 8086 Microprocessor

Instruction Set6. Control Transfer Instructions

• Transfer the control to a specific destination or target instruction
• Do not affect flags

❑ 8086 Unconditional
transfers
Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

88
 8086 Microprocessor

Instruction Set6. Control Transfer Instructions

❑ 8086 signed conditional branch ❑ 8086 unsigned conditional branch
instructions instructions

• Checks flags

• If conditions are true, the program control is transferred to the new

memory location in the same segment by modifying the content of IP

89
 8086 Microprocessor

Instruction Set6. Control Transfer Instructions

❑ 8086 signed conditional branch ❑ 8086 unsigned conditional branch
instructions instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or equal Jump if above Jump if not below or
equal
JGE disp8 JNL disp8
Jump if greater than or Jump if not less JAE disp8 JNB disp8
equal Jump if above or equal Jump if not below
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not greater than Jump if below Jump if not above or
or equal equal
JLE disp8 JNG disp8
Jump if less than or Jump if not greater JBE disp8 JNA disp8
equal Jump if below or equal Jump if not above

90
 8086 Microprocessor

Instruction Set6. Control Transfer Instructions

❑ 8086 conditional branch instructions affecting individual flags

Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

91
 Data Transfer Instructions
• LEA: Load Effective Address
• The general format of LEA instruction is
• LEA register, source
• This instruction determines the offset address of the variable or memory location
named as the source and puts this offset address in the indicated 16 bit register.
• Examples:
• LEA BX, COST; Load BX with offset address of COST in data segment where
• COST is the name assigned to a memory location in data segment.
• LEA CX, [BX][SI]; Load CX with the value equal to (BX)+(SI) where (BX) and
• (SI) represents content of BX and SI respectively.

92
 Data Transfer Instructions
• LDS: Load register and DS with words from memory
• The general form of this instruction is
• LDS register, memory address of first word
• The LDS instruction copies a word from the memory location specified in the
instruction into the register and then copies a word from the next memory location
into the DS register.
• LDS is useful for initializing SI and DS registers at the start of a string before using
one of the String instructions.
• Example:
• LDS SI,[2000H]; Copy content of memory at offset address 2000H in data segment
to lower byte of SI, content of 2001H to higher byte of SI. Copy content at offset
address 2002H in data segment to lower byte of DS and 2003H to higher byte of
DS.

93
 Data Transfer Instructions
• LES, LSS: LES and LSS instructions are similar to LDS
instruction except that instead of DS register, ES and SS
registers are loaded respectively along with the register
specified in the instruction.
• LAHF: This instruction copies the low byte of flag
register into AH.
• SAHF: Store content of AH in the low byte of flag
register.
• Except SAHF and POPF instructions, all other data
transfer instructions do not affect flag register.

94
 Arithmetic Instructions
•DAA: Decimal Adjust AL after BCD addition
•This instruction is used to get the result of adding two packed BCD numbers (two
decimal digits are represented in 8 bits) to be a BCD number. The result of addition
must be in AL for DAA to work correctly. If the lower nibble (4 bits) in AL is greater
than 9 after addition or AF flag is set by the addition then the DAA will add 6 to the
lower nibble in AL. If the result in the upper nibble of AL is now greater than 9 or if
the carry flag is set by the addition, then the DAA will add 60H to AL.
•Examples:
•Let AL=0101 1000=58 BCD
• CL=0011 0101=35 BCD
•Consider the execution of the following instructions:
•ADD AL, CL; AL=10001101=8DH and AF=0 after execution
•DAA - Add 0110 (decimal 6) to AL since lower nibble in AL is greater than 9
• AL=10010011= 93 BCD and CF=0
•Therefore the result of addition is 93 BCD.

95
 Arithmetic Instructions
•DAS: Decimal Adjust after BCD subtraction
•DAS is used to get the result is in correct packed BCD form after subtracting two
packed BCD numbers. The result of the subtraction must be in AL for DAS to work
correctly. If the lower nibble in AL after a subtraction is greater than 9 or the AF was
set by subtraction then the DAS will subtract 6 from the lower nibble of AL. If the
result in the upper nibble is now greater than 9 or if the carry flag was set, the DAS
will subtract 60H from AL.
•Examples:
•Let AL=86 BCD=1000 0110
•CH=57 BCD=0101 0111
•Consider the execution of the following instructions:
•SUB AL, CH; AL=0010 1111=2FH and CF=0 after execution
•DAS; Lower nibble of result is 1111, so DAS subtracts 06H from AL to make
•AL=0010 1001=29 BCD and CF=0 to indicate there is no borrow.
•The result is 29 BCD.

96
AAA: ASCII AFTER ADDITION
Stack Structure

Picture Courtesy :Google

Stack is a set of memory locations in the Read/Write memory which is used for
temporary storage of binary information during the execution of a program.
It is implemented in the Last-in-first-out (LIFO) manner. i.e., the data written first can
be accessed last, One can put the data on the top of the stack by a special operation
known as PUSH.
Data can be read or taken out from the top of the stack by another special instruction
known as POP.
102
 Stack Structure
• Stack is implemented in two ways. In the first case, a set of registers is arranged
in a shift register organization.
• One can PUSH or POP data from the top register. The whole block of data
moves up or down as a result of push and pop operations respectively.
• In the second case, a block of RAM area is allocated to the stack. A special
purpose register known as stack pointer (SP) points to the top of the stack.
• Whenever the stack is empty, it points to the bottom address. If a PUSH
operation is performed, the data are stored at the location pointed to by SP and it
is decremented by one. Similarly if the POP operation is performed, the data are
taken out of the location pointed at by SP and SP is incremented by one. In this
case the data do not move but SP is incremented or decremented as a result of
push or pop operations respectively

103
 Stack Structure
• Application of Stack: Stack provides a powerful data structure
which has applications in many situations. The main
advantage of the stack is that, We can store data (PUSH) in it
with out destroying previously stored data.
• This is not true in the case of other registers and memory
locations. stack operations are also very fast The stack may
also be used for storing local variables of subroutine and for
the transfer of parameter addresses to a subroutine.
• This facilitates the implementation of re-entrant subroutines
which is a very important software property. The
disadvantage is, as the stack has no fixed address, it is
difficult to debug and document a program that uses stack.

104
 Stack Operation
• Stack operation: Operations on stack are performed using
the two instructions namely PUSH and POP. The
contents of the stack are moved to certain memory
locations after PUSH instruction.
• Similarly, the contents of the memory are transferred
back to registers by POP instruction.

105
The PUSH operation of the Stack
• Let us consider two registers (register pair) B & C whose
contents are 25 & 62.

Picture Courtesy :Google

106
The POP operation of the Stack

107 Picture Courtesy :Google

 Example program
• Write a program to initialize the stack pointer (SP) and store the contents of the register
pair HL on stack by using PUSH instruction. Use the contents of the register pair for
delay counter and at the end of the delay retrieve the contents of H-L using POP.

Picture Courtesy :Google 108

 Interrupts
• The meaning of ‘interrupts’ is to break the sequence
of operation
• While the CPU is executing a program, an interrupt
breaks the normal sequence of execution of instructions,
diverts its execution to some other program called
Interrupt Service Routine (ISR)
• After executing ISR , the control is transferred back again
to the main program 8086 Interrupts and Interrupt
Response

109
 Types of Interrupt
An 8086 interrupt can come from any one of the three
sources
• One source is an external signal applied to the Non
Maskable Interrupt (NMI) input pin or to the Interrupt
(INTR) input pin
• An interrupt caused by a signal applied to one of these
inputs is referred to as a hardware interrupt
A second source of an interrupt is execution of
the Interrupt instruction, INT, This is referred to as
Software Interrupt
The third source of an interrupt is some error condition
produced in the 8086 by the execution of an instruction
An example of this is the divide
110
by zero error
Types of Interrupt

Picture
111 Courtesy :Google
Types of Interrupt

112 Picture Courtesy :Google

Hardware Interrupt

Picture Courtesy :Google

113
 Software Interrupts
• The interrupt vector table contains 256 four byte entries,
contains the CS:IP
• Interrupt vectors for each of the 256 possible interrupts. The
table is used to locate the interrupt service routine addresses
for each of those interrupts.
• The Interrupt vector table is located in the first 1024 bytes of
memory at addresses 000000H-0003FFH.It contains the
address(segment and offset)of the interrupt service provider

114
 Software Interrupts
• The first five interrupt vectors are
identical in all Intel processors
• Intel reserves the first 32 interrupt
vectors
• The last 224 vectors are user
available
• Each is four bytes long in real mode
and contains the starting address of
the interrupt service procedure.
• The first two bytes contain the offset
address The last two contain the
segment address

Picture Courtesy :Google 115

Types of Interrupts
• TYPE 0 The divide error : whenever the results
from a division overflows or an attempt is made to
divide by zero.
• Type 2 The non-maskable interrupt occurs when a
logic 1 is placed on the NMI input pin to the
microprocessor. non- maskable—it cannot be
disabled
• Type 3 A special one-byte instruction (INT 3) that
uses this vector to access its interrupt-service
procedure. often used to store a breakpoint in a
program for debugging
• TYPE 4 Overflow is a special vector used with the
TYPE 2
INTO instruction. The INTO instruction interrupts
the program if an overflow condition exists.

TYPE 4 116 Picture Courtesy :Google