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Lab 11-DLD

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Rizwan Latif
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16 views4 pages

Lab 11-DLD

Uploaded by

Rizwan Latif
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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International Islamic University Islamabad

Faculty of Engineering and Technology


Department of Electrical and Computer Engineering

DIGITAL LOGIC DESIGN LAB

Experiment No. 11: S-R Latch and S-R Flip-Flop

Name of Student: ……………………………………

Registration No.: ……………………………………

Date of Experiment: ………………………………..

Submitted To: ………………………………………

Experiment No. 11: S-R Latch and S-R Flip-Flop Page 1


Objectives:
✓ The objective of this experiment is to understand, construct and verify the truth tables of
S-R latch and S-R flip-flop.
Equipment Required:
✓ Digital Lab Trainer (IDL-800) or equivalent
✓ Logic Probe [Qty=1];
✓ ICs: 7400 (NAND Gate) [Qty=1]; 7402 (NOR Gate) [Qty=1];
✓ Connecting wires
Theory:
Logic circuits that incorporate memory cells are called sequential logic circuits; their
output depends not only upon the present value of the input but also upon the previous
values. Sequential logic circuits often require a clock signal for their operation. The latch
and flip-flop are a basic bi-stable memory elements widely used in sequential logic
circuits. Usually there are two outputs, Q and its complementary value (Q‫)׳‬. The S-R
latch consists of two cross-coupled NOR gates whereas S-R flip-flop requires an
additional clock input (CLK) so that the S and R inputs are active only when the CLK is
high. When the CLK goes low, the state of flip-flop is latched and can’t change until the
CLK goes high again. That’s why, flip-flops are also known as synchronous devices.
The term synchronous means that the output changes state only at leading or trailing
edge of the CLK. Flip-flops are edge-triggered or edge-sensitive whereas gated latches
are level-sensitive.
Procedure:
Part 1: Construction of S-R Latch
a. Connect the IC-7402 as shown in Figure 21.1. The pin configuration of IC-7402 is given
in Figure 21.3 whereas Figure 21.2 represents the logical symbol of an S-R latch.
b. Connect the inputs (R and S) to logic switches whereas the outputs (Q and Q‫ )׳‬to LED’s.

Figure 21.1: Logical Diagram of S-R Latch Figure 21.2: Logical Symbol of S-R Latch

Experiment No. 11: S-R Latch and S-R Flip-Flop Page 2


Figure 21.3: Pin Configuration of IC-7402 (NOR Gates)
c. Apply various input combinations as per Table 21.1 and verify the working of S-R latch.
Table 21.1: Truth Table of S-R Latch
Sr. Verification Status
S R Q Ǭ Mode
No. YES/NO
1 0 0 NC NC No Change
2 1 0 1 0 Set
3 0 1 0 1 Reset
4 1 1 0 0 Invalid Condition

d. Is the truth table of S-R latch verified or not?


_______________________________________________________________________
_______________________________________________________________________

Part 2: Construction of clocked S-R Flip-Flop


a. Connect the IC-7400 as shown in Figure 21.4. The pin configuration of IC-7400 is given
in Figure 21.6 whereas Figure 21.5 represents the logical symbol of a clocked S-R flip-
flop.
b. Connect the inputs (R and S) to logic switches whereas the outputs (Q and Q‫ )׳‬to LED’s.
The clock signal can be applied from the function generator available on the digital
trainer.

Figure 21.4: Logical Diagram of clocked S-R Flip-Flop

Experiment No. 11: S-R Latch and S-R Flip-Flop Page 3


Figure 21.5: Logical Symbol of clocked S-R Flip-Flop

Figure 21.6: Pin Configuration of IC-7400 (NAND Gates)

c. Apply various input combinations as per Table 21.2 and verify the working of S-R flip-
flop.
Table 21.2: Truth Table of S-R Flip-Flop
Sr. Verification Status
CLK S R Q Ǭ Mode
No. YES/NO
1 ↑ 0 0 NC NC No Change
2 ↑ 1 0 1 0 Set
3 ↑ 0 1 0 1 Reset
4 ↑ 1 1 0 0 Invalid Condition

d. Is the truth table of S-R flip-flop verified or not?


_______________________________________________________________________
_______________________________________________________________________

Experiment No. 11: S-R Latch and S-R Flip-Flop Page 4

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