J.P.

COLLEGE OF ENGINEERING
COLLEGE ROAD, AYIKUDI, TENKASI – 627852
Approved by AICTE – New Delhi & Affiliated to Anna University, Chennai

DEPARTMENT OF ECE

NM1038 - IC CHIP DESIGN & VERIFICATION LABORATORY

NAME :

REGISTER NUMBER :

DEGREE & DEPARTMENT : B.E. - ECE

REGULATION : 2021

YEAR & SEMESTER : IV Year & VII Semester

BATCH : 2021 - 2025

 J.P. COLLEGE OF ENGINEERING
COLLEGE ROAD, AYIKUDI, TENKASI – 627852
Approved by AICTE – New Delhi & Affiliated to Anna University, Chennai

DEPARTMENT OF ECE
2024-2025

Certified that this is a bonafide record of practical work done by

Mr/Ms...................................................Reg.No...........................................of Third

year, VII Semester B.E ECE in the NM1038 - IC CHIP DESIGN & VERIFICATION

LABORATORY during the academic year 2024-2025.

STAFF IN-CHARGE HEAD OF THE DEPARTMENT

Submitted for the Anna University Practical Examination held on _____________at J.P. College of
Engineering, Ayikudi, Tenkasi-627 852.

INTERNAL EXAMINER EXTERNAL EXAMINER

 INTRODUCTION
IC CHIP DESIGN:

IC chip design involves the creation of complex circuits on a semiconductor wafer.

It includes several phases:
1. Specification and Conceptual Design:
o Define the chip's functionality, performance, and power consumption
requirements.
o Decide on the architecture, whether it's a processor, memory, analog
circuit, or a mixed-signal design.

2. RTL (Register Transfer Level) Design:

o Use hardware description languages (HDL) like VHDL or Verilog to
describe the functionality of the chip.
o This phase abstracts the logical operations and data flow between
registers.

3. Synthesis:
o Convert the RTL design into a gate-level netlist using a synthesis tool.
This involves mapping high-level descriptions to specific logic gates
and flip-flops.

4. Physical Design:
o Translate the netlist into a physical layout, specifying where
transistors, wires, and other elements will go on the chip.
o Key steps include placement, clock tree synthesis, routing, and
ensuring timing constraints are met (Timing Closure).
o The result is a GDSII file used for fabrication.

5. Design for Manufacturability (DFM):

o Ensure that the design can be reliably produced with the desired yield.
This includes analyzing factors like mask generation, lithography, and
variability in the manufacturing process.
6. Tapeout:
o This is the final stage where the design is sent to a foundry for
manufacturing.
IC Chip Verification

Verification ensures that the design meets the specifications and works as intended before
fabrication. This process is crucial because any error found aftertapeout can be extremely costly.
Verification can be divided into various categories:
1. Functional Verification:
o Verify that the design behaves according to the specification. This isoften the
most time-consuming process.
o Simulation is the most common approach, where the design istested with
various input vectors to ensure correctness.
o Formal Verification: Uses mathematical proofs to verify that the design
matches the specification. It’s particularly useful for checkingcorner cases.
o Assertion-Based Verification: Uses specific properties orassertions
within the RTL code that must always hold true.
o Equivalence Checking: Ensures that the RTL design matches thegate-level
implementation after synthesis.
2. Timing Verification:
o Static Timing Analysis (STA): Verifies that all signal paths meet the timing
constraints, such as setup and hold times.
o Dynamic Timing Analysis: Simulates actual signal propagationthrough the
design, considering delays and variability in the fabrication process.

3. Power Verification:
o Ensures the design meets power consumption targets, both fordynamic
and static power.
o Power-Aware Simulation: Verifies that the design's power management
mechanisms work correctly.
4. Physical Verification:
o Ensures the physical layout meets the foundry’s manufacturing
requirements.
o This includes:
 Design Rule Checking (DRC): Ensures the layout adheresto the
manufacturing process rules.
 Layout vs. Schematic (LVS): Verifies that the physicallayout
matches the original circuit schematic.
 Antenna Rule Checking: Ensures that long metal routes donot
accumulate too much charge during fabrication, which can damage the
chip.

5. Pre-Silicon Validation:
o Before tapeout, hardware emulation platforms or FPGA prototyping may be
used to validate the design in a near-real environment, allowing the testing of
software alongside the hardware.
6. Post-Silicon Validation:
o Once the chip is fabricated, it’s tested in real-world conditions to ensure it
functions correctly. This can reveal manufacturing defects orunforeseen issues in
the design.
Tools and Methodologies

 EDA Tools (Electronic Design Automation):

o Tools from companies like Cadence, Synopsys, and Mentor Graphics(Siemens)
dominate the industry. These tools automate and assist in everything from
synthesis to verification.
o Common tools include:
 Cadence Virtuoso (for analog/mixed-signal design)
 Synopsys Design Compiler (for RTL synthesis)
 Cadence Innovus/Genus (for physical design and timingclosure)
 Synopsys VCS or Mentor Questa (for functional verification)
 Verification Methodologies:
o UVM (Universal Verification Methodology) is widely usedfor functional
verification. It provides a structured framework for creating reusable
testbenches.
o Random Testing: Involves generating random stimuli and checking if
the design works as expected under all conditions.

Challenges

 Complexity: Modern ICs, especially system-on-chip (SoC) designs, can consist of

billions of transistors, making verification extremely challenging.
 Power and Performance Trade-offs: Designers need to balance performance
requirements with power consumption, particularly in mobileand IoT devices.
 Shorter Design Cycles: The demand for new products with faster time-to-market
increases pressure on design and verification teams.
Evolution of IC Design and Verification

 Early IC Design:
o Briefly describe the early days of IC design (1970s–1980s) and simple microchips
(e.g., the Intel 4004).
o Mention early verification techniques, which were manual and verytime-
consuming.

 Advancements in Tools and Automation:

o EDA Tools: The rise of Electronic Design Automation (EDA) tools and their
impact on IC design.
o How automation reduced manual labor and allowed designers tohandle
increasingly complex designs.

 Introduction of Formal Methods:

o When and how formal verification methods (e.g., static timinganalysis,
equivalence checking) became crucial.

 The Move to System-on-Chip (SoC) and Mixed-Signal Designs:

o How designs have grown to include more components (processors, memory,
I/O, etc.) on a single chip, increasing verification complexity.

IC Chip Design Workflow

 Specification to Architecture Design:

o Describe the early stages of defining chip specifications, functionality, and
architecture.
  RTL Design:
o The role of hardware description languages (HDLs) like Verilog andVHDL.
o Example: How a CPU architecture is described in RTL.
 Synthesis and Optimization:
o How RTL designs are synthesized into gate-level netlists, includingthe role of
synthesis tools and power/performance trade-offs.
 Physical Design:
o Transitioning from logical design to physical layout.
o Challenges like timing closure and signal integrity.

IC Verification Process

 Functional Verification:
o Describe how functional verification ensures the design meets
specifications.
o Example: How UVM (Universal Verification Methodology) and
SystemVerilog enable reusable test environments.
 Static and Dynamic Timing Analysis:
o Explain the significance of timing verification to ensure the chipoperates
within speed and power constraints.
 Power Verification:
o Discuss the growing importance of power-aware verification inmobile
and IoT devices.
 Physical Verification (DRC, LVS):
o Importance of physical verification before tapeout to avoid
manufacturing issues.

Challenges in Modern IC Design and Verification

 Increasing Complexity:
o Discuss how modern SoCs consist of billions of transistors, makingdesign and
verification extremely challenging.
o Example: The verification of a high-end SoC with multiple cores,GPUs, and
accelerators.
  Power vs. Performance Trade-offs:
o How designers must optimize for performance, while managing
heatand power consumption, particularly in mobile and edge
devices.
 Design Cycles and Time-to-Market Pressure:
o The impact of shortened product development cycles on the
designand verification process.
 Verification Bottlenecks:
o Functional verification often takes up to 70% of the entire
designcycle. Mention why this is a critical bottleneck.
Emerging Trends in IC Design and Verification

AI and Machine Learning in EDA Tools:

o How AI is being integrated into verification processes to
automateparts of functional verification and timing closure.
 Shift-Left Verification:
o Discuss the trend of starting verification earlier in the design
process,with continuous verification alongside design.
 3D ICs and Heterogeneous Integration:
o The challenges posed by emerging packaging technologies, such
as3D ICs, chiplets, and heterogeneous integration.
 Post-Silicon Validation:
o How post-silicon validation is evolving to complement pre-
siliconverification with real-world testing.

1
 TABLE OF CONTENTS

S. No Date Laboratory Experiment Name Page Marks Signature

No
Design and implementation of a
1 12.09.24 3
4:2 Encoder
Design and implementation of a
2 19.09.24 6
2:4 Decoder
Design and implementation of a
3 27.09.24 9
1-bit Half-Adder
Design and implementation of a
4 03.10.24 12
1-bit Full-Adder

Design and implementation of a

5 17.10.24 15
4:1 Multiplexer

Design and implementation of a

6 24.10.24 18
Rise edge detector
Design and implementation of a
7 24.10.24 21
Fall edge detector
Design and implementation of a
8 07.11.24 24
16-bit Adder
Verification of a 16-bit Adder
9 14.11.24 27
design
Verification of a MIN-MAX
10 21.11.24 32
Calculator design

2
PIN DIAGRAM:

TRUTH TABLE:

y3 y2 y1 y0 out [1] out [0]

0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

3
EX.NO: 01 DESIGN AND IMPLEMENTATION OF A
DATE: 12.09.24
4:2 ENCODER

AIM:
To design and implement a 4:2 Encoder.

THEORY:
An encoder is a device or algorithm that converts information from one format
or representation to another. In the context of electronics, computer science, and
communication, encoders are used to transform data into a format suitable for
transmission, storage, or further processing.

1. Digital Encoder (Mechanical Encoder): These are used in machines like motors,
robotics, and industrial equipment. They convert mechanical position or movement
into a digital signal (e.g., rotary or linear encoders). and typically output binary
signals that represent the position or direction of motion.

2. Data Encoder (Signal Encoder): It is used in communication systems to transform

data into a format suitable for transmission over a medium (e.g., radio waves, optical
fibers). It Involves converting analog or digital data into a code (such as a binary
code or a more complex encoding scheme like Huffman coding or Manchester
encoding). It helps reduce errors and optimize the efficiency of data transfer.

3. Audio/Video Encoder: It converts raw audio or video data into compressed

formats for easier storage or streaming (e.g., MP3, H.264, or AAC). Compression
algorithms (like lossy or lossless compression) are used to reduce the size of the file,
making it easier to send or store while maintaining quality.

4. Software Encoder (for Data Processing): In computing, it could refer to a software

program that performs encoding tasks, such as encoding data for web applications
(e.g., base64 encoding to handle binary data as text in web forms).

The primary role of an encoder is to facilitate efficient, reliable, or secure

handling of information, often by converting it into a format that fits the
requirements of the system in which it will be used.

(4 to 2) line Encoder: The 4 to 2 Encoder consists of four inputs y0 y1 y2 y3, and

two outputs 0 and 1. (4 to 2) Encoder encodes the information from 4 inputs into a
2-bit code.

4
PROGRAM:

DESIGN CODE:
module encoder(
input y0,
input y1,
input y2,
input y3,
output[1:0] out
);
assign out[0] = y3|y1;
assign out[1] = y3|y2;

endmodule : encoder

RESULT:
Thus the 4:2 Encoder circuit was designed, implemented and the output was
verified.

5
PIN DIAGRAM:

TRUTH TABLE:
y1 y0 out [3] out [2] out [1] out [0]
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

6
EX.NO: 02 DESIGN AND IMPLEMENTATION OF A
DATE: 19.09.24
2:4 DECODER

AIM:
To design and implement a 2:4 Decoder.

THEORY:
A decoder is an electronic or computational device used to translate coded or
encoded information back into its original form. It works in reverse of an encoder,
which transforms data into a coded format for transmission or storage. The decoder
essentially "decodes" the encoded signal to retrieve the original data.

1. Digital Decoders (Binary Decoders): These are used in digital electronics to

convert binary input values (such as a combination of 1s and 0s) into a
corresponding output. For example, a 3-to-8 binary decoder converts a 3-bit input to
one of 8 possible outputs. It's used in applications like memory addressing, where
the decoder helps to select specific memory locations.

2. Data Communication Decoders: In communications, a decoder receives a coded

signal, such as a modulated radio wave, and converts it into readable data, like text,
audio, or video. For example, a DVD decoder decodes compressed video and audio
files back into high-quality media that can be displayed on a screen.

3. Error-Correction Decoders: In digital communications, data is often transmitted

with error-correcting codes (ECC). The decoder will not only retrieve the original
data but also detect and correct any errors that occurred during transmission. An
example of this is a Reed-Solomon decoder, used in CD/DVD players and other
devices to ensure accurate data retrieval.

4. Speech/Audio Decoders: In the context of audio, a decoder (such as an MP3

decoder) is used to convert compressed audio data (like an MP3 file) into an
uncompressed audio format (like PCM) that can be played on speakers or
headphones.

Decoders are essential in many fields where data needs to be transferred,

stored, or displayed in an intelligible format, and they work by reversing or undoing
the encoding process.

(2 to 4) Decoder: The (2 to 4) decoder consists of two inputs y1and y0, and four
outputs 0 1 2 3. (4 to 2) decoder decodes the information from 2 inputs into a 4-bit
code.

7
PROGRAM:
DESIGN CODE:
module decoder(
input y0,
input y1,
output[3:0] out
);

assign out[0] = !y0 & !y1;

assign out[1] = y0 & !y1;
assign out[2] = !y0 & y1;
assign out[3] = y0 & y1;
endmodule : decoder

RESULT:
Thus, the 2:4 Decoder circuit was designed, implemented and the output was
verified.

8
PIN DIAGRAM:

TRUTH TABLE:

A B sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

9
EX.NO: 03 DESIGN AND IMPLEMENTATION OF A
DATE: 27.09.24
1-BIT HALF-ADDER

AIM:
To design and implement a 1-Bit half-adder.

THEORY:
A half adder is a basic digital circuit used in binary arithmetic to add
two single-bit binary numbers. It produces two outputs:

1. Sum (S): The XOR (exclusive OR) of the two input bits.
S=A⊕B
2. Carry (C): The AND of the two input bits, which represents the
carry-out to the next higher bit position.
C=A⋅B

If both inputs are 0, the sum is 0, and there is no carry. If one input is
1 and the other is 0, the sum is 1, and there is no carry. If both inputs are
1, the sum is 0 (since 1 + 1 = 10 in binary), and there is a carry of 1 to the
next bit.

A half adder is typically used in binary addition

circuits as part of more complex arithmetic circuits like full
adders and multi-bit adders.

10
 PROGRAM:

DESIGN CODE:
module half_adder(
input A,
input B,
output sum,
output carry
);

always @(*)begin
sum = A^B;
carry = A & B;
end
endmodule : half_adder

RESULT:
Thus the 1-Bit half- adder circuit was designed, implemented and the
output was verified.

11
PIN DIAGRAM:

TRUTH TABLE:

A B C sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

12
EX.NO: 04 DESIGN AND IMPLEMENTATION OF A
DATE: 03.10.24
1-BIT FULL-ADDER

AIM:
To design and implement a1-Bit full-adder.

THEORY:
A full adder is a digital circuit used in computing and electronics to
perform the addition of three binary bits: two significant bits A and B and
a carry-in bit Cin. The full adder produces two outputs:

1. Sum (S): The binary sum of A, B and Cin.

S = A⊕B⊕ Cin
(⊕ represents the XOR operation.)
2. Carry-out (Cout): A bit that indicates if there is an overflow from the
addition.
Cou t= (A⋅B) + (Cin ⋅ (A⊕B))
(⋅ represents the AND operation, and + represents the OR operation.)

A full adder can be implemented using logic gates such as XOR,

AND, and OR.

It is a building block in larger circuits like arithmetic logic units

(ALUs) and ripple-carry adders, which handle multi-bit binary addition.

13
PROGRAM:

DESIGN CODE:
module full_adder(
input A,
input B,
input C,
output sum,
output carry
);
always @(*)begin
sum = (A^B)^C;
carry = (A & B) | (A ^ B);
end
endmodule : full_adder

RESULT:
Thus the 1-Bit full adder circuit was designed, implemented and
the output was verified.

14
PIN DIAGRAM:

TRUTH TABLE:

sel[1] sel[0] Out

0 0 y0
0 1 y1
1 0 y2
1 1 y3

15
EX.NO: 05 DESIGN AND IMPLEMENTATION OF A 4:1
DATE: 17.06.24 MULTIPLEXER

AIM:
To design and implement a 4:1 Multiplexer.

THEORY:
A multiplexer is a combinational circuit that has 2n inputs, n select
lines, and one output. Multiplexer selects one of the inputs and passes the
input through the output pin based on the select line.

4:1 Multiplexer has four data inputs y3, y2, y1 &y0, two selection
lines sel 0 &sel1 and one output out. One of these 4 inputs will be
connected to the output based on the combination of inputs present at
these two selection lines.

It acts as a data selector. It uses control signals. These control

signals decide which input is connected to the output. There are two types
of multiplexers namely analog and digital multiplexers.

MUXes are used in systems to route data from multiple sources to

a single destination, like in communication networks.Inside processors,
multiplexers are used to select different data inputs for various operations
(e.g., selecting operands for arithmetic operations).

They can be used to select memory addresses or data from

different locations. Multiplexers are commonly used in communication
systems, data routing, signal processing, and microprocessors.

PROGRAM:

DESIGN CODE:

module mux(
input y0,
input y1,
input y2,
input y3,
input [1:0] sel,
output out
);

16
 reg out_s;
always @(y0 or y1 or y2 or y3 or sel) begin
case(sel)
'b00 : begin
out_s = y0;
end
'b01 : begin
out_s = y1;
end
'b10 : begin
out_s = y2;
end
'b11 : begin
out_s = y3;
end
endcase
end

assign out = out_s;

endmodule : mux

RESULT:
Thus the 4:1 Multiplexer circuit was designed, implemented and the
output was verified.

17
PIN DIAGRAM:

18
EX.NO: 06 DESIGN AND IMPLEMENTATION OF A RISE
DATE: 24.10.24 EDGE DETECTOR

AIM:
To design and implement a rise edge detector.

THEORY:
A rise edge detector is a digital circuit or logic function used to
detect the transition from a low voltage level (logic 0) to a high voltage
level (logic 1) on a signal. It responds specifically to the rising edge of a
signal.

1. Input Signal: The signal being monitored (e.g., a clock or any other
waveform).
2. Detection: The edge detector monitors the state of the input signal and
detects when it changes from 0 to 1, which is referred to as the rising
edge.
3. Output: The circuit produces an output pulse when a rising edge is
detected. This pulse is typically very brief and occurs at the moment the
input signal transitions from low to high.

A rise edge detector can be implemented using basic logic gates

(such as AND, NOT, or D flip-flops). One common implementation is to
use a D flip-flop with the input signal connected to the clock and a
delayed version of the input connected to the D input. The output of the D
flip-flop will produce a pulse when the input signal rises from low to high.

The clock input of the flip-flop is connected to the signal you are
monitoring. The D input is connected to the delayed version of the signal,
usually with a slight delay (using a simple inverter or buffer). The flip-
flop will output a logic high only for one clock cycle when the input
signal rises from 0 to 1.

Rise edge detectors are used in timing applications where it's

important to detect the start of a clock cycle. They are also used to
generate a single pulse in response to a rising edge, for example, in pulse
width modulation (PWM) or synchronization of signals.

A rise edge detector specifically identifies when a signal moves

from low to high, creating a transient pulse that can be used for further
logic or timing purposes.

19
PROGRAM:

DESIGN CODE:
module rise_edge_detector(
reg a_r;
input clk,
input rst_n,
input a,
output rise_edge_o
);
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
a_r <=0;
end
else begin
a_r <= a;
end
end
assign rise_edge_o = !a_r & a;
endmodule : rise_edge_detector

RESULT:

Thus the rise edge detector circuit was designed, implemented and
the ouput was verified.

20
PIN DIAGRAM:

21
EX.NO: 07 DESIGN AND IMPLEMENTATION OF A FALL
DATE: 24.10.24 EDGE DETECTOR

AIM:
To design and implement a fall edge detector.

THEORY:
A fall edge detector is a type of circuit or algorithm designed to
detect the falling edge of a signal. The falling edge occurs when a signal
transitions from a high state (logic 1) to a low state (logic 0). In digital
electronics, this can be important for timing or triggering specific actions
when a signal's state drops.

1. Signal Input: The circuit or algorithm monitors the input signal, which
is usually a square wave or a digital signal that oscillates between high
and low states.
2. Edge Detection: The detector identifies a transition in the signal from a
high to a low state. This falling edge can be detected by examining the
signal's changes over time.
3. Triggering: Once the falling edge is detected, the circuit can trigger an
event, such as sending a pulse or activating another process.

The input signal can be fed to a D flip-flop clocked by the signal.

The output of the flip-flop will reflect the previous state of the signal. By
comparing the current state of the signal with the previous state (which is
stored in the flip-flop), you can detect a falling edge when the current
state is low (0) and the previous state was high (1).
A more basic approach could involve an AND gate that checks for
a high-to-low transition between two consecutive samples of the signal.

In digital timing circuits, detecting the falling edge is often

essential for synchronization. Falling edge detection is used to generate
pulses in response to the falling edge of a signal. In sequential logic
systems, operations often occur on the falling edge of a clock signal.

A falling edge detector is designed to recognize and react to the

transition from high to low in a digital signal, and it is widely used in
timing and synchronization applications.

22
PROGRAM:

DESIGN CODE:
module fall_edge_detector(
input clk,
input rst_n,
input a,
output fall_edge_o
);
reg a_r;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
a_r <=0;
end
else begin
a_r <= a;
end
end
assign fall_edge_o = a_r & !a;
endmodule : fall_edge_detector

RESULT:

Thus the fall edge detector circuit was designed, implemented and
the output was verified.

23
PIN DIAGRAM:

PINDESCRIPTION:

SignalName I/O Width Description

clk input 1 100MHzclock.
rst_n input 1 Asynchronousnegativereset.
Inputvalid.Thesignalmustbeasserted
valid_i input 1
foreachvaliddata transfertothedesign.
data_1 input 16 data_1for16-bitadditionoperation
data_2 input 16 data_2for16-bitadditionoperation
valid_o output 1 Outputvalid.Indicatesvalidoutputdata.
data_out output 17 Addedoutputdata.

24
EX.NO: 08 DESIGN AND IMPLEMENTATION OF A 16-BIT
DATE:07.11.2024 ADDER

AIM:
To Designandimplementationofa16-bit adder.

THEORY:
A 16-bit adder is a digital circuit that performs the addition of two
16-bit binary numbers. It is an extension of smaller adders, such as 4-bit
or 8-bit adders, to accommodate larger binary values.

Full Adder Units: Each bit of the binary number is added using a full
adder. A full adder takes three inputs: two bits (from the numbers being
added) and a carry bit (from the previous stage). It produces two outputs:
a sum bit and a carry bit.

Carry Propagation: The carry output from one bit’s addition is passed
to the next higher bit. This process is repeated until the most significant
bit (MSB).

Ripple Carry Adder (RCA): The simplest implementation, where carry

bits ripple through all stages sequentially.

Carry Look-Ahead Adder (CLA): Faster than RCA because it

calculates carry bits in parallel, reducing delay.

To add two 16-bit numbers A and B:

A = 1101001100111010
B = 0110010101100101

Each corresponding bit is processed along with any carry,

producing a 16-bit sum and a final carry-out. These circuits are used in
processors, ALUs, and other digital systems requiring multi-bit addition.

PROGRAM:

DESIGN CODE:
module my_adder (
input valid_i,
input [15:0] data_1,
input [15:0] data_2,
output [16:0] data_out,
output valid_o,

25
 input clk,
input rst_n
);
reg [15:0] data_1_r, data_2_r;
reg valid_1d, valid_2d;
reg [16:0] out_s, out_r;
always @ (posedge clk or negedge rst_n) begin
if (! rst_n) begin
data_1_r <= 0;
data_2_r <= 0;
valid_1d <= 0;
end
else begin
valid_1d <= valid_i;
if(valid_i) begin
data_1_r <= data_1;
data_2_r <= data_2;
end end
end
always @(data_1_r or data_2_r) begin
out_s = {1'b0,data_2_r} + {1'b0,data_1_r};
end

26
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
out_r <= 0;
valid_2d <= 0;
end
else begin
valid_2d <= valid_1d;
if(valid_1d) begin
out_r <= out_s;
end
end end
assign valid_o = valid_2d;
assign data_out = out_r;
end module : my_adder

RESULT:

Thus, the 16-Bit adder circuit was designed, implemented and the
output was verified.

27
EX.NO: 09 VERIFICATION OF A 16-BIT ADDER DESIGN
DATE: 14.11.24

AIM:
To verify a 16-bit adder design.

THEORY:
A 16-bit adder is a digital circuit that performs the addition of two
16-bit binary numbers. It is an extension of smaller adders, such as 4-bit
or 8-bit adders, to accommodate larger binary values.

Full Adder Units: Each bit of the binary number is added using a full
adder. A full adder takes three inputs: two bits (from the numbers being
added) and a carry bit (from the previous stage). It produces two outputs:
a sum bit and a carry bit.

Carry Propagation: The carry output from one bit’s addition is passed
to the next higher bit. This process is repeated until the most significant
bit (MSB).

Ripple Carry Adder (RCA): The simplest implementation, where carry

bits ripple through all stages sequentially.

Carry Look-Ahead Adder (CLA): Faster than RCA because it

calculates carry bits in parallel, reducing delay.

To add two 16-bit numbers A and B:

A = 1101001100111010
B = 0110010101100101

Each corresponding bit is processed along with any carry,

producing a 16-bit sum and a final carry-out. These circuits are used in
processors, ALUs, and other digital systems requiring multi-bit addition.

PROGRAM:

TEST BENCH CODE:

module tb_top(); // parameter
parameter RESET_PERIOD = 2;
parameter CLOCK_PERIOD = 10;
parameter DATAIN_WIDTH = 16;
parameter DATAOUT_WIDTH = 17;

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// local variable logic clk;
logic rst_n;
logic valid_i;
logic [DATAIN_WIDTH-1:0] data_1;
logic [DATAIN_WIDTH-1:0] data_2;
logic [DATAOUT_WIDTH-1:0] data_out;
logic valid_o;
bit [DATAOUT_WIDTH-1:0] exp_data_q[$];
bit [DATAOUT_WIDTH-1:0] act_data_q[$];

// DUT instantiation my_adder i_my_adder(

.clk(clk),.rst_n(rst_n),
.valid_i(valid_i),.data_1(data_1),
.data_2(data_2),.data_out(data_out),
.valid_o(valid_o));
initial begin
rst_n=1;
reset_input_signals();
reset_generation();
drive_input_signal(10);
end

initial begin fork

input_monitor();
output_monitor();
check_exp_act();
join end
initial begin clock_generation();
end
initial begin
#200;
$finish;
end
// drive inputs into DUT
task drive_input_signal(int trans_count);
for(int i=0; i<trans_count; i++) begin
#1;
valid_i = 1;
data_1 = $urandom_range(0,65535);
data_2 = $urandom_range(0,65535);
@(posedge clk)
#1;
end reset_input_signals();

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endtask : drive_input_signal
// input monitor
task input_monitor();
bit[DATAOUT_WIDTH-1:0] dataout;
forever begin
if(valid_i==1) begin
dataout = data_1 + data_2;
exp_data_q.push_back(dataout);
end
@(posedge clk);
end
endtask : input_monitor

// output monitor
task output_monitor();
forever begin
if(valid_o==1) begin
act_data_q.push_back(data_out);
end
@(posedge clk);
end
endtask : output_monitor
// check the expect and actual data t
ask check_exp_act();
bit[DATAOUT_WIDTH-1:0] act,exp;
forever begin
if(act_data_q.size>=1) begin
if(exp_data_q.size==0)
$error("DUT generates output without provided any input");
else begin
act = act_data_q.pop_front ;
exp = exp_data_q.pop_front ;
if(act == exp)
$display("expect data %0d == actual data%0d ",exp,act);
else
$error("expect data %0d != actual data %0d",exp,act);
end
end
@(posedge clk);
end
endtask : check_exp_act

// reset input signals

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function void reset_input_signals();
valid_i = 'b0;
data_1 = 'bx;
data_2 = 'bx;
endfunction : reset_input_signals

// reset generation
task reset_generation();
@(posedge clk);
rst_n = 0;
repeat(RESET_PERIOD) begin
@(posedge clk);
end
rst_n=1;
endtask : reset_generation

// clock generation
task clock_generation();
clk=0;
forever begin
#(CLOCK_PERIOD/2)
clk=~clk;
end
endtask : clock_generation endmodule: tb_top

RESULT:

Thus the 16-Bit adder circuit design was verified.

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PIN DIAGRAM:

PIN DESCRIPTION:

Signal Name I/O Width Description

clk input 1 100 MHz clock.
rst_n input 1 Asynchronous negative reset.
The opcode signal indicates the min
opcode input 1 or max operation.
0– min.
1– max.
input_valid input 1 Input valid. The signal must be
asserted
for each valid data transfer to the
design.
data_in input 8 Input data.
count input 4 Count indicates the number of inputs.
0
is not a valid data.
output_valid output 1 Output valid. Indicates valid output
data.
data_out output 8 Output data.

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EX.NO: 10 VERIFICATION OF A MIN-MAX
DATE: 21.11.24 CALCULATOR DESIGN

AIM:
To verify a MIN-MAX calculator design.

THEORY:
A min-max calculator is a tool used to determine the
minimum and maximum values within a set of data or a range. It is often
used in various contexts, such as statistics, programming, and
optimization problems. It is a simple yet powerful tool for extracting
insights from numerical data.

1. Input: You provide a series of numbers or a range of values. This

could be an array of data points (like test scores, temperatures, stock
prices, etc.) or a specific numerical range (like from 1 to 100).

2. Process: The calculator compares all the values in the dataset or range.
It identifies the smallest (minimum) and largest (maximum) numbers.

3. Output: Minimum value is the lowest number in the set or range and
the maximum value is the highest number in the set or range.

Array of Numbers:
If you have the following set of numbers: `[7, 5, 2, 9, 4]`, the min-max
calculator would:
- Find the minimum value: `2`
- Find the maximum value: `9`

Range of Values:
If you have a range from 1 to 100, the min-max calculator would:
- Minimum value: `1`
- Maximum value: `100`

Applications:
Data Analysis: To find the range of values in a dataset.
Normalization: In machine learning, min-max normalization is used to
scale data to a specific range (e.g., 0 to 1).
Optimization: In mathematical problems where you need to find the best
possible outcomes (maximum) or the worst (minimum).

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TIMING DIAGRAM:

MIN timing diagram (hexadecimal values):

MAX timing diagram (hexadecimal values):

MIN-MAX timing diagram (hexadecimal values):

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PROGRAM:

TEST BENCH CODE:

module tb_top(); // parameter parameter

RESET_PERIOD = 2; parameter
CLOCK_PERIOD = 10; parameter
WIDTH = 8; // local variable logic clk;
logic rst_n; logic input_valid; logic
[WIDTH-1:0] data_in; logic [3:0] count;
logic opcode; logic output_valid; logic
[WIDTH-1:0] data_out; bit [WIDTH-1:0]
exp_data_q[$]; bit [WIDTH-1:0]
act_data_q[$]; P a g e | 28 // DUT
instantiation min_max_cal
i_my_adder( .clk(clk), .rst_n(rst_n), .inpu
t_valid(input_valid), .data_in(data_in),
count(count), .opcode(opcode),
.output_valid(output_valid),
.data_out(data_out) );
initial begin rst_n=1;
reset_input_signals(); reset_generation();
drive_input_signal(3); end initial begin
fork input_monitor(); output_monitor();
check_exp_act(); join end initial begin
clock_generation(); end initial begin
#300; $finish; end P a g e | 29 // drive
inputs into DUT task
drive_input_signal(int trans_count); bit
[3:0] cnt,j; bit op_code; for(int i=0;
i=data_in || cnt==0)
begin
dataout=data_in; end cnt++;
end else if(opcode==1) begin
if(dataout<=data_in || cnt==0)
begin dataout=data_in; end

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cnt++; P a g e | 30 end
if(cnt==count) begin
exp_data_q.push_back(dataou
t); cnt = 0; dataout = 0; end
end @(posedge clk); end
endtask : input_monitor //
output monitor task
output_monitor(); forever
begin if(output_valid==1)
begin
act_data_q.push_back(data_o
ut); end @(posedge clk); end
endtask : output_monitor //
check the expect and actual
data task check_exp_act();
bit[WIDTH-1:0] act,exp;
forever begin
if(act_data_q.size>=1) begin
if(exp_data_q.size==0)
$error("DUT genearates
output without provided any
input"); else begin act =
act_data_q.pop_front ; exp =
exp_data_q.pop_front ; if(act
== exp ) $display("expect
data %0d == actual data %0d
",exp,act); else $error("expect
data %0d != actual data %0d
",exp,act); end end P a g e | 31
@(posedge clk); end endtask :
check_exp_act // reset input
signals function void
reset_input_signals();
input_valid = 'b0; data_in =
'bx; count = 'bx; opcode = 'bx;
endfunction:

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reset_input_signals // reset
generation task
reset_generation();
@(posedge clk); rst_n = 0;
repeat(RESET_PERIOD)
begin @(posedge clk); end
rst_n=1; endtask :
reset_generation // clock
generation task
clock_generation(); clk=0;
forever begin
#(CLOCK_PERIOD/2);
clk=~clk; end endtask :
clock_generation endmodule :
tb_top

RESULT:

Thus the MIN - MAX calculator circuit design was verified.

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