11/8/2024

Part Two

CSE 491

82C55
Computer Interfacing and Peripherals
programmable peripheral interface
(PPI)

THE PROGRAMMABLE PERIPHERAL INTERFACE

• 82C55 programmable peripheral interface (PPI) is

a popular, low-cost interface component found in
Basic Input/Output Interface many applications.
• The PPI has 24 pins for I/O, programmable in groups
of 12 pins and groups that operate in three distinct
modes of operation.
• 82C55 can interface any TTL-compatible
I/O device to the microprocessor.

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• The 82C55 (CMOS version) requires wait states if Basic Description of the 82C55
operated with a processor using higher than an 8
MHz clock. • Fig 1 shows pin-outs of the 82C55 in
DIP and surface mount (flat pack) format.
– also provides at least 2.5 mA of sink (logic 0)
current at each output, a maximum of 4.0 mA • The three I/O ports (labeled A, B, and C) are
programmed as groups.
• Because I/O devices are inherently slow, wait states
used during I/O transfers do not impact significantly – group A connections consist of port A (PA7–PA0)
upon the speed of the system. and the upper half of port C (PC7–PC4)
• The 82C55 still finds application even in the latest – group B consists of port B (PB7–PB0) and the
Core2-based computer system. lower half of port C (PC3–PC0)
• 82C55 is selected by its CS pin for programming and
reading/writing to a port.

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Figure 1 The pin-out of the 82C55 peripheral interface adapter (PPI).

• 82C55 is used for interface to the keyboard and
parallel printer port in many PCs.
– found as a function within an interfacing chip set
– also controls the timer and reads data from the
keyboard interface
• An experimentation board is available that plugs into
the parallel port of a PC, to allow access to an 8255 Table 1 shows I/O port assignments
used for programming and access to
located on the board. the I/O ports

• The 8255 is programmed in either assembly

language or Visual C++ through drivers available
with the board.

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Figure 2 The 82C55 interfaced to the low bank of the 80386SX microprocessor.
• Table 1 shows I/O port assignments used for
programming and access to the I/O ports.
• In the PC, a pair of 82C55s, or equivalents, are
decoded at I/O ports 60H–63H and also
at ports 378H–37BH.
• The 82C55 is a fairly simple device to interface to
the microprocessor and program.
• For 82C55 to be read or written, the CS input must
be logic 0 and the correct I/O address must be
applied to the A1 and A0 pins.
• Remaining port address pins are don’t cares.

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• Fig 2 shows an 82C55 connected to the 80386SX • After a RESET, no other commands are needed, as
so it functions at 8-bit addresses C0H (port A), C2H long as it is used as an input device for all three
(port B), C4H (port C), ports.
and C6H (command register). • 82C55 is interfaced to the PC at port addresses
– this interface uses the low bank of the I/O map 60H–63H for keyboard control.
• All 82C55 pins are direct connections to the – also for controlling the speaker, timer, and other
80386SX, except the CS pin. The pin is internal devices such as memory expansion
decoded/selected by a 74ALS138 decoder. • It is also used for the parallel printer port at I/O ports
• A RESET to 82C55 sets up all ports as 378H–37BH.
simple input ports using mode 0 operation.
– initializes the device when the processor is reset

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Programming the 82C55 • Group A (port A and the upper part of port C) are
programmed as input or output pins.
• 82C55 is programmed through two internal
command registers shown in Figure 3. • Group A can operate in modes 0, 1, and 2.
• Bit position 7 selects either command byte A or – mode 2 operation is a bidirectional mode of
command byte B. operation for port A
– command byte A programs functions of group • If a 0 is placed in bit position 7 of the command byte,
A and B command byte B is selected
– byte B sets (1) or resets (0) bits of port C only • This allows any bit of port C to be set (1) or reset
if the 82C55 is programmed in mode 1 or 2 (0), if the 82C55 is operated in either mode 1 or 2.
– otherwise, this byte is not used for programming
• Group B (port B and the lower part of port C) are
programmed as input or output pins.

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Figure 3 The command byte of the command register in the 82C55. (a) Programs
ports A, B, and C. (b) Sets or resets the bit indicated in the select a bit field.
Mode 0 Operation

– group B operates in mode 0 or • Mode 0 operation causes 82C55 to function:

mode 1 – as a buffered input device
– mode 0 is basic input/output mode – as a latched output device
that allows the pins of group B to
be programmed as simple input • Fig 4 shows 82C55 connected to a
and latched output connections set of eight seven-segment LED displays.
– Mode 1 operation is the strobed • These are standard LEDs.
operation for group B connections – the interface can be modified with a change
– data are transferred through port B in resistor values for an organic LED (OLED)
– handshaking signals are provided display or high-brightness LEDs
by port C

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Figure 4 An 8-digit LED display interfaced to the 8088 microprocessor through an

82C55 PIA. • In this display, the segment load resistor passes 80
– ports A & B are programmed as mA current and has approximately 3.0 V across it.
(mode 0) simple latched output ports • The value of the resistor is 3.0 V ÷ 180 mA = 37.5
– port A provides segment data inputs Ohm. The closest standard resistor
port B provides a means of selecting value of 39 Ohm is used in Fig 4.
one display position at a time for • Programming the 82C55 is accomplished by the
multiplexing the displays short sequence of instructions listed in Example 11.9.
– the 82C55 is interfaced to an 8088 • Ports A and B are programmed as outputs.
through a PLD so it functions at
I/O port numbers 0700H–0703H
– PLD decodes the I/O address and
develops the write strobe for the WR
pin of the 82C55
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• Resistor values in Fig 4 are chosen so the segment An LCD Display Interfaced to the 82C55
current is 80 mA.
– required to produce average 10 mA current
per segment as the displays are multiplexed • LCDs (liquid crystal displays) have replaced LED
• A six-digit display uses a segment current of 60 mA displays in many applications.
for an average of 10 mA per segment. • Fig 5 shows an Optrex DMC-20481 LCD display
• Peak anode current in an eight-digit display interfaced to an 82C55.
is 560 mA (seven segments  80 mA). – DMC-20481 is a 4-line by 20-characters-per-line
– average anode current is 80 mA display that accepts ASCII code as input data
• In a six-digit display, peak current would be 420 mA • It also accepts commands that initialize it and control
(seven segments  60 mA). its application.

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Figure 5 The DMC-20481 LCD display interfaced to the 82C55.

• To program DMC-20481 it must first be initialized.
• This applies to any display using the HD44780
(Hitachi) display driver IC.
• The entire line of small display panels from Optrex
and most other manufacturers is programmed in the
same manner.
• To program DMC-20481 it must first be initialized.
– this applies to any display using the HD44780
(Hitachi) display driver integrated circuit

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• The data connections, which are attached to the • Initialization is accomplished via the following:
82C55 port A, are used to input display data and to – 1. Wait at least 15 ms after VCC rises to 5.0 V
read information from the display. – 2. Output the function set command (30H), and
• For a 4-bit interface, D4–D7 pins are used where the wait at least 4.1 ms
data must be formatted with the high nibble first, – 3. Output the function set command (30H) a
followed by the low nibble. second time, and wait at least 100 µs
• A few newer OLED devices contain a serial interface – 4. Output the function set command (30H) a
that uses a single pin for the data. third time, and wait at least 40 µs
– 5. Output the function set command (38H) a
fourth time, and wait at least 40 µs
– 6. Output 08H to disable the display, and wait
at least 40 µs

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– 7. Output a 01H to home the cursor and clear • Once the BUSY procedure is available, data can be
the display, and wait at least 1.64 ms sent to the display by writing another procedure
– 8. Output the enable display cursor off (0CH), called WRITE.
and wait at least 40 µs • The WRITE procedure uses BUSY to test before
– 9. Output 06H to select auto-increment, shift trying to write new data to the display.
the cursor, and wait at least 40 µs • Example 11–14 shows the WRITE procedure, which
transfers the ASCII character from the BL register to
• Software to accomplish the initialization of
the current cursor position of the display.
the LCD display is listed in Example 11–12.
• The time delays can also be obtained by using a
timer in C++.

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• After initialization, time delays are no longer needed • The only other procedure needed for a basic display
when sending data or many commands to the is the clear & home cursor procedure, called CLS,
display. shown in Example 11–15.
• The clear display command still needs a time delay • This procedure uses the SEND macro from the
as the busy flag is not used . initialization software to send the clear command to
• Instead of a time delay, the busy flag is tested to see the display.
whether the display has completed an operation. • With CLS and the procedures presented thus far,
• The BUSY procedure tests the LCD display and only you can display any message on the display, clear
returns when the display has completed a prior it, display another message, and basically operate
instruction. the display.

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Figure 6 The stepper motor showing full-step operation: (a) 45° (b) 135° (c) 225°
A Stepper Motor Interfaced to the 82C55. (d) 315°.

• Another device often interfaced to a computer

system is the stepper motor.
– a digital motor because it is moved in discrete
steps as it traverses through 360°
• An inexpensive stepper motor is geared to move
perhaps 15° per step
• A more costly, high-precision stepper motor can be
geared to 1° per step.

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• In all cases, these steps are gained through many • The motor is driven by NPN Darlington amp pairs to
magnetic poles and/or gearing. provide a large current to each coil.
• Figure 6 shows a four-coil stepper motor that uses • A circuit that can drive this stepper motor is
an armature with a single pole. illustrated in Fig 7.
– two coils are energized – with the four coils shown in place
• If less power is required, one coil may be energized • This circuit uses the 82C55 to provide drive signals
at a time, causing the motor to used to rotate the motor armature in either the right-
step at 45°, 135°, 225°, and 315°. or left-hand direction.
• The motor is shown with the armature rotated to four • A simple procedure that drives the motor is listed in
discrete places, called full stepping. Example 11–16 in both assembly language and as a
– accomplished by energizing the coils, as shown function in C++.

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Figure 7 A stepper motor interfaced to the 82C55. This illustration does not show the Figure 8 A 4  4 keyboard matrix connected to an 8088 microprocessor through the
decoder. 82C55 PIA.

– the 82C55 is decoded at I/O

ports 50H–53H for an 8088
– port A is programmed as an
input port to read the rows
– port B is programmed as an
output port to select a column
– a flowchart of the software
required to read a key from the
keyboard matrix and debounce
the key is illustrated in Fig 9

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Figure 9 The flowchart of a keyboard-scanning procedure.

Key Matrix Interface
– keys must be debounced, normally
• Keyboards come in a variety of sizes, from standard with a time delay of 10–20 ms
101-key QWERTY keyboards to special keyboards – the software uses a procedure
that contain 4 to 16 keys. called SCAN to scan the keys and
• Fig 8 is a key matrix with 16 switches interfaced to another called DELAY10 to waste
ports A and B of an 82C55. 10 ms of time for debouncing
– the switches are formed into a 4  4 matrix, – the main keyboard procedure is
but any matrix could be used, such as a 2  8 called KEY and appears in Example
• The keys are organized into four rows and columns: 11–17
(ROW0–ROW3) (COL0–COL3) – the KEY procedure is generic, and
can handle any configuration from a
1  1 matrix to an 8  8 matrix.

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Figure 10 Strobed input operation (mode 1) of the 82C55. (a) Internal structure and
• The ShortDelay procedure is needed as the (b) timing diagram.
computer changes port B at a very high rate .
– the time delay allows the data sent to port B to
settle to their final state
• This is not needed if scan rate (time between output
instructions) does not exceed 30 KHz.
– if the scanning frequency is higher, the device
generates radio interference
• If so, the FCC will not approve application
in any accepted system
– without certification the system cannot be sold

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Mode 1 Strobed Input Signal Definitions for Mode 1 Strobed Input

• Causes port A and/or port B to function as latching

input devices.
– allows external data to be stored to the port STB
until the microprocessor is ready to retrieve it • The strobe input loads data to the port latch, which
• Port C is used in mode 1 operation—not for data, but holds the information until it is input to the
for control or handshaking signals. microprocessor via the IN instruction.
– to help operate either or both port A and B as
strobed input ports IBF
• Fig 10 shows how both ports are structured for mode • Input buffer full is an output indicating that the input
1 strobed input operation. latch contains information.

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INTR Strobed Input Example

• Interrupt request is an output that requests an • An example of a strobed input device is a keyboard.
interrupt. The INTR pin becomes a logic 1 when STB • The keyboard encoder debounces the key switches
returns to a logic 1. Cleared when data are input and provides a strobe signal whenever a key is
from the port by the processor. depressed.
– the data output contains ASCII-coded key code
INTE • Figure 11 illustrates a keyboard connected to
• Interrupt enable signal is neither input nor output; it strobed input port A.
is an internal bit programmed via
port PC4 (port A) or PC2 (port B) bit position.

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Figure 11 Using the 82C55 for strobed input operation of a keyboard.

PC7, PC6
• The port C pins 7 and 6 are general-purpose I/O pins
that are available for any purpose.

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Mode 1 Strobed Output Signal Definitions for Mode 1 Strobed Output

• Fig 12 shows the internal configuration and timing

diagram of 82C55 when operated as a strobed
output device under mode 1. OBF
• Strobed output operation is similar to mode 0 output • Output buffer full goes low whenever data are
operation. output (OUT) to the port A or B latch. The signal is
– except control signals are included to provide set to logic 1 when the ACK pulse returns from the
handshaking external device.
• When data are written to a strobed output port, the
output buffer full signal becomes logic 0 to indicate
data are present in the port latch.

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Figure 12 Strobed output operation (mode 1) of the 82C55. (a) Internal structure and
(b) timing diagram. ACK
• The acknowledge signal causes the OBF
pin to return to logic 1. The ACK signal is a response
from an external device, indicating that it has
received data from the 82C55 port.

INTR
• Interrupt request often interrupts the processor
when the external device receives the data via the
ACK signal. Qualified by the internal INTE (interrupt
enable) bit.

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Figure 13 The 82C55 connected to a parallel printer interface that illustrates the
INTE strobed output mode of operation for the 82C55.

• Interrupt enable is neither input nor output;

it is an internal bit programmed to enable or disable
the INTR pin. INTE A is programmed using PC6 bit.
INTE B is programmed using the PC2 bit.

PC4, PC5
• Port C pins PC4 and PC5 are general-purpose I/O
pins. The bit set and reset command is used to set or
reset these two pins.

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Strobed Output Example Mode 2 Bidirectional Operation

• The printer interface demonstrates how to achieve • Mode 2 is allowed with group A only.
strobed output synchronization between the printer • Port A becomes bidirectional, allowing data
and the 82C55. transmit/receive over the same eight wires.
• Figure 13 illustrates port B connected to – useful when interfacing two computers
a parallel printer, with eight data inputs for receiving • Also used for IEEE-488 parallel high-speed GPIB
ASCII-coded data, a DS (data strobe) input to (general- purpose instrumentation bus) interface
strobe data into the printer, and an ACK output to standard.
acknowledge the receipt of the ASCII character.
• Figure 14 shows internal structure and timing for
mode 2 bidirectional operation.

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Figure 14 Mode 2 operation of the 82C55. (a) Internal structure and (b) timing
diagram. ACK
• Acknowledge is an input that enables the three-
state buffers so that data can appear on port A. If
ACK is logic 1, the output buffers of port A are at
their high-impedance state.

STB
• The strobe input loads the port A input latch with
external data from the bidirectional port A bus.

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Signal Definitions for Bidirectional Mode 2 PC0, PC1, and PC2

• These pins are general-purpose I/O pins in mode 2
controlled by the bit set and reset command.
INTR
• Interrupt request is an output used to interrupt the
microprocessor for input and output conditions.

OBF
• Output buffer full is an output indicating the output
buffer contains data for the bidirectional bus.

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IBF • To receive data through the bidirectional port A bus,

IBF is tested with software to decide whether data
• Input buffer full is an output used to signal that the have been strobed into the port.
input buffer contains data for the external bidirectional
bus. – if IBF = 1, data is input using IN
• The external interface sends data to the port by
using the STB signal.
INTE
– the IBF signal becomes logic 1 and data at
• Interrupt enable are internal bits (INTE1 & INTE2) port A are held inside the port in a latch
that enable the INTR pin. The state of the INTR pin is
• When the IN executes, the IBF bit is cleared and
controlled through port C bits PC6 (INTE1) and PC4
data in the port are moved into AL.
(INTE2).
• See Example 11–21 for a procedure.

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The Bidirectional Bus • The INTR (interrupt request) pin can be activated
from both directions of data flow through the bus.
• The bidirectional bus is used by referencing port A
with the IN and OUT instructions. • If INTR is enabled by both INTE bits, the output and
input buffers both cause interrupt requests.
• To transmit data through the bidirectional bus, the
program first tests to determine whether the output • This occurs when data are strobed into the buffer
buffer is empty. using STB or when data are written using OUT.
– if so, data are sent to the output buffer via OUT
• The external circuitry also monitors the signal to
decide whether the microprocessor has sent data to
the bus.

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82C55 Mode Summary SUMMARY

• Figure 15 shows a graphical summary of the three • The 82C55 is a programmable peripheral
modes of operation for the 82C55.
• Mode 0 provides simple I/O. interface (PIA) that has 24 I/O pins that are
• Mode 1 provides strobed I/O. programmable in two groups of 12 pins each
• Mode 2 provides bidirectional I/O.
• These modes are selected through the command (group A and group B).
register of the 82C55. • The 82C55 operates in three modes: simple I/O
(mode 0), strobed I/O (mode 1), and bidirectional
I/O (mode 2).

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Figure 15 A summary of the port connections for the 82C55 PIA.

SUMMARY (cont.)

• When the 82C55 is interfaced to the 8086

operating at 8 MHz, we insert two wait states
because the speed of is faster than the 82C55 can
handle.
• The LCD display device requires a fair amount of
software, but it displays AS‐CII‐coded
information.

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