AND9202/D

A System Designer's Guide

for Building a PCIe® Clock
Tree while Addressing
Timing Challenges
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APPLICATION NOTE

Abstract Evolution of PCIe Standard

PCIe standard has become a popular choice for high speed Earlier, parallel bus model was preferred over serial
serial communication in networking, computing, industrial model for higher throughput. However practical speed
and embedded systems. With increasing data rates limitation due to clock skew, signal data skew and flight
requirements, the reference clock performance is critical time, and high pin count motivated the transition away from
and its specifications are more aggressive for good timing the parallel bus model, and advanced serial communication
margins in these systems. Clocking signals have to protocols gained prominence for their superior performance
overcome difficult system challenges for maintaining the and their compact footprint. Peripheral Component
timing budget requirements and to provide a reliable Interconnect − Special Interest Group (PCI−SIG) introduced
reference clock. a serial local computer bus protocol − Peripheral Component
This application note focuses on the PCIe timing solutions Interconnect (PCI) for higher throughput, and it was later
from ON Semiconductor catering to different clocking enhanced to PCI Extended (PCI−X). Further enhancements
architectures and various system clock trees used in the in the development led to PCI Express (PCIe), which is a
industry. The portfolio includes crystal oscillators, clock point−to−point full duplex serial computer expansion bus
generators, spread spectrum (for EMI reduction) clock standard developed by PCI−SIG. PCIe was designed to
generators, fanout buffers, zero delay (ZDB) buffers and replace PCI, PCI−X and AGP standards for a faster and
PCIe switches for Networking, Computing, Consumer and flexible solution.
Industrial markets. This application note also elaborates on PCIe protocol has evolved over a period of time through
the best in class timing products offered by generations, accommodating the needs of higher speeds and
ON Semiconductor which are suitable for systems with throughput – each generation of the protocol, Gen I, Gen II
stringent timing margins, thereby enabling system designers and Gen III, progressively required stringent reference clock
to realize a complete clock tree with high performance performance. Originally intended for desktop computers,
silicon solutions. PCIe is now a popular choice in applications like servers,
network attached storage, network switches/ routers, set top
Introduction
boxes and other embedded applications for its advantages of
The next generation technologies bring in the need for scalable bandwidth and flexibility. This makes the PCIe
faster and efficient communication with robust signal reference clock requirements more stringent as it needs to
integrity and shrinking form factors. Catering to transceiver adhere to timing budgets of these applications while
applications for high baud rates, many communication overcoming the system challenges.
protocols such as ISA, ATA, XT−IDE, PCMCIA, USB, PCI,
PCI−X, AGP, PCIe, etc. are further being developed and
adapted to meet the bandwidth demands of the next
generation technologies.

© Semiconductor Components Industries, LLC, 2015 1 Publication Order Number:

March, 2015 - Rev. 1 AND9202/D
 AND9202/D

PCIe CLOCKING ARCHITECTURES

PCI−SIG defines three clock distribution methods for In systems using spread spectrum clocking (SSC) for EMI
PCIe standards – Common Clock, Data clock and Separate suppression, the Tx and the Rx PLLs are edge aligned and
clock architectures. Irrespective of clocking methodology, much of the jitter propagates equally to both PLLs. The
the accuracy requirement of PCIe standard is the same i.e. drawback of this clocking architecture is the clock needs to
± 300 ppm. be distributed to each PCIe endpoint in the system, which
increases the PCB real estate and sets tighter limits on clock
Common Clock Architecture jitter, clock skew requirement, and the number of signals
In this architecture, same clock reference is sourced to the routed on hardware.
transmitter (Tx) and the receiver (Rx). This clocking method This is the preferred and simple clock distribution scheme
is most common in commercially used devices for its when the design consists of single card with multiple PCIe
simplicity in implementation. It also supports end points and the same clock source needs to be transmitted
spread−spectrum clocking used for EMI (emission) with other signals through the distribution channel.
reduction.

Transmitter Receiver

Data In TX Latch RX Latch Data Out

TX PLL CDR

RX PLL

Refclk

Figure 1. Common Clock Architecture

Data Clock Architecture stream at the receiver. Additional clock recovery circuitry is
In this architecture, the clock signal is embedded into the used to extract the clock from signal stream at the receiver
transmitted data stream and is recovered from the data end. SSC can be implemented in this architecture.

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Transmitter Receiver

Clock Out
Data In TX Latch RX CDR and Data
Out

TX PLL

Refclk

Figure 2. Data Clock Architecture

Separate Clock Architecture / SRIS (Separate Refclk effective jitter at the Rx is the RSS (Root Sum Square) sum
Independent Spread) of the Tx and Rx PLLs, thus the jitter requirement for
This architecture avoids transmitting the clock to all separate reference clocks is substantially tighter than for
channels by using separate clock sources at each PCIe common clock architecture. The PCIe SRIS clocking specs
endpoint, however it substantially increases the design are still in their infancy. However, as per preliminary results,
complexity since the frequency accuracy limit of ±300 ppm the PCIe Generator clocks from ON Semiconductor
without SSC still holds. This clocking method supports two conforms to the current SRIS refclk requirements (as per
types of clocking – Tx and Rx with same data rates, and Tx PCI−SIG: Separate Refclk Independent SSC Architecture
and Rx at different data rates. The later tolerates 5600 ppm draft).
difference for separate refclks utilizing the SSC (SRIS). The

Transmitter Receiver

Data In TX Latch RX Latch Data Out

TX PLL CDR

RX PLL

Refclk

Refclk

Figure 3. Separate Reference Clock with Independent Spread Architecture

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PCIe STANDARD CLOCK SPECIFICATION

The PCIe Serializer De−serializer (SerDes) system uses a The Refclk contains jitter over wide range of frequencies.
reference clock (Refclk) to generate higher frequency clock A specific frequency band of interest will be tracked by the
from internal PLL which delivers higher bit rates. Typically receiver which is meaningful for a PCIe system – mainly the
the reference clock is multiplied by 4 to 25 times to generate jitter component tracked (not filtered) by the transfer
the bit rate frequency. Jitter on reference clock degrades the function of the CDR. Thus, PCIe systems are concerned
communication both at the Tx and Rx thereby prejudicing about this band of period jitter that is extracted and
the system performance. Thus, a precise low jitter reference calculated by mathematical functions, which differ for each
clock is essential for a good operational system. of the PCIe Gen I, II and III models. The maximum limits of
Furthermore, the Refclk jitter performance specifications the jitter values are listed in Table 1.
are stringent for higher bitrates.

Table 1. PCIe SPECIFICATION JITTER LIMITS

PCIe Data Transfer Rate Jitter Evaluation Band Total Jitter Units
Gen I 2.5Gb/s Input Evaluation Band: 86 ps
0 Hz − Nyquist (clock frequency/2)
Gen II (High Band) 5Gb/s Input High Band: 3.1 ps
1.5 MHz − Nyquist (clock frequency/2)
Gen II (Low Band) 5Gb/s Input Low Band: 3.0 ps
10 kHz − 1.5 MHz
Gen III 8Gb/s Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) 1.0 ps

The jitter on the signal is comprised of Deterministic (Dj) below shows the results on the clock output from
and a Random (Rj) component. The Dj is the non−Gaussian NB3N51034, a 25 MHz Crystal to 100 MHz/ 200 MHz Quad
probability density function bounded in amplitude and HCSL/LVDS Clock Generator after PCIe Gen I, II and III
appears due to specific causes like interference, data transfer functions or filters are applied to the cycle trend
dependence, Duty Cycle Distortion and is predictable. For data.
clocks, the Dj appears as spurs of definite amplitude in the
phase noise plot. The Rj is the Gaussian distribution
component of jitter which is unbounded and present due to
random phenomena such as thermal noise, process
variation, etc. In clocks, the Rj component appears as the
integrated phase noise over a specified frequency offset
range. Total jitter (TJ) is calculated from Dj and Rj by −
Tj = Djpeak−to−peak + 2 × n × Rjrms, ; n is based on BER of
the link (10−12 for Ethernet)
Table 1 represents the Tj value acceptable for PCIe Gen
I, II and III systems in specified frequency bands (based on
CDR transfer function).
Jitter Evaluation Method Figure 4. PCIe Jitter Level Post PCIe Jitter
In order to evaluate the PCIe jitter values from clock, a Extraction on NB3H51034 Clock
cycle trend period jitter data of 1.6 ms (approx. 200,000
cycles) is fed to the PCIe Jitter analyzer tool (A tool The red vertical line is the maximum jitter limit for each
developed by ON Semiconductor which is similar to Intel® of the PCIe generation standards. The green color indicates
Clock Jitter Tool). This extraction can also be done on the the conformance to the spec and the green bar length
clock cycles data by applying the respective transfer indicates how far the measured jitter is from the maximum
functions for each of the PCIe generations. The Figure 4 limit.

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Table 2. ON PCIe CLOCK PERFORMANCE MARGIN AGAINST PCIe SPECIFICATION

Leading Competitor Part
ON PCIe Family Clock Typical Performance Performance (IDT5V41236
PCIe Standard Specification (NB3N51034 at 100 MHz and SS off) at 100 MHz and SS off) Units
Gen I 86 10 28 ps
Gen II (High Band) 3.1 1 1.8 ps
Gen II (Low Band) 3.0 0.1 0.7 ps
Gen III 1.0 0.35 0.48 ps

The jitter results of the ON PCIe clocks meet the protocol other PCIe parts in market. These margins are useful to
specification with ample margins and performs superior to overcome system challenges explained in next section.

SYSTEM CHALLENGES

To overcome the performance limitations and voltage Serializer De−serializer (SerDes) is used to transmit and
scaling problem posed by parallel bus communication receive data over the serial link. The reference clock is
systems, the industry is moving towards point−to−point sourced to the SerDes block of a system.
serial communication. In a serial bus communication, a

Transmitter Block
TXDP
TX

Serializer TX Data
TXDN

TX Clk Timing Block

TX PLL

Refclk

RX CDR PLL Refclk

stable
RX Clk

RXDP Receiver Block

RX

RXDN Deserializer RX Data

Act Activity
Detect Detect

Figure 5. Serial System SerDes Block Diagram

As system bandwidth requirements continue to increase, design and sound circuit design techniques, SerDes can be
SerDes are moving large amount of data between systems. virtually immune to supply noise.
The success of SerDes serial link poses a challenge for Jitter Signal integrity issues like ISI, crosstalk, impedance
performance. Power supply noise, Reference clock quality mismatch can also be dealt with impedance matching, better
and signal integrity are the main system issues that are PCB material and routing techniques.
potential pitfalls affecting the performance of a SerDes Jitter on Reference clock is the most difficult to suppress.
system. It not only multiplies and propagates directly with the
Power supply noise introduces bounded and uncorrelated transmitted signal, but also corrupts the reference clock for
jitter DJ at Refclk input, PLL, clock distribution and serial the recovered signal at the receiver. The high performance
data distribution. However, with regulated power supply PLL architecture of ON Semiconductor PCIe clock

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generators ensures low jitter peaking and substantial margin The extremely low random jitter from ON Semiconductor
to the PCIe Gen I, II and III jitter specification limits as PCIe reference clock generator at both the transmitter and
shown in Table 2. The challenge is to create a system where the receiver is beneficial in avoiding SerDes system failure
jitter generation plus the system jitter is less than receiver due to jitter performance. Furthermore, SSC capability
tolerance. enables EMI suppression.

PCIe CLOCK TREE

In designing any future scalable system with PCIe industry. In the PCIe based systems, the CPU and memory
architecture, clock tree planning is a critical task. Based on exchange data through a hub consisting of multiple PCI
number of internal and external PCIe I/Os (including the Express lanes called a PCIe Root Complex. The clock tree
future scalability) in the system and speed/ bandwidth mainly consists of several components – clock generators,
requirements, appropriate PCIe clock sources, buffers, and clock buffers (Zero delay and non−zero delay buffers) and
switches are selected. Based on the PCIe data exchange, switches.
below are few of the commonly used clock trees in the

PCIe Root Complex

PCIe Endpoint PCIe Switch PCIe Endpoint

PCIe Endpoint
PCIe Endpoint

PCIe Endpoint
100 MHz HCSL
100 MHz HCSL
100 MHz HCSL
100 MHz HCSL
100 MHz HCSL NB3N106K 100 MHz HCSL

25 MHz 100 MHz HCSL

crystal
NB3N51034
100 MHz to HCSL/ LVDS

Figure 6. Typical Clock Tree in Computation Applications

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PCIe Clock

External Links

Advanced TCA Backplane

Extension slots PCIe Clock
Buffer

PCIe PCIe To Host A To Host B To

To Host A To Host B
PCIe PCIe To Host A
PCIe to
To Host B
Fabric 2
PCIe SwitchPCIe Switch
Switch Switch PCIePCIe
to to
PCIX
To
Switch Switch Fabric 2
PCIXPCIX To CPU
Fabric 1 Root
CPU
Root
CPURootRoot Root Complex
CPUCPU Complex
Complex Complex CPU
Complex
To Fabric 1 To Fabric 2 CPU
To Fabric 1 To Fabric 2 MEM
To Fabric 1 To Fabric 2 MEM MEM MEM
MEM
LineLine Card/
Card/ Server
Server Blades
Blades Host B
Fabric Card Line Card/ Server Blades
Host A

Figure 7. Typical Clock Tree in Embedded Applications

ON SEMICONDUCTOR PCIe CLOCK TREE SOLUTIONS

ON Semiconductor offers a range of high performance performance. Some of the clock generators offer SSC
solutions in Clock Generation, clock and data Distribution, Generation for EMI suppression. In this technique, the peak
and Multiplexing/ switching to construct a complete system energy of the carrier is re−distributed to nearby frequencies
clock tree and continuously expanding the portfolio. in the spectrum, in order to reduce the radiated power. Refer
to AND9015/D A Solution for Peak EMI Reduction with
Clock Generators Spread Spectrum Clock Generators for further details.
The range of clock generators from ON Semiconductor Table 3 lists several off the shelf PCIe clock generators
provide the best in class sub picosecond phase jitter available from ON Semiconductor.

Table 3. PCIe CLOCKS FROM ON SEMICONDUCTOR WITH PARAMETRICS AND PHASE NOISE
Phase Jitter Spread
No. of PCIe Noise Cycle− Spread Frequency
Part Clock RMS cycle Spectrum Deviation
Number Description Outputs (ps) (ps) Modulation (%) Package
NB3N3002 3.3 V, Crystal to single 1 0.35 3 No TSSOP−16
output HCSL clock
synthesizer
NB3N5573 3.3 V, Crystal to dual 2 0.4 No TSSOP−16
output HCSL clock
synthesizer
NB3N51032 3.3 V, Dual output HCSL 2 0.4 2 Yes 0% TSSOP−16
clock synthesizer (SS −0.5%
compatible)
−0.75%
NB3N51034 3.3 V, Crystal to quad 4 0.4 Yes 0% TSSOP−20
output HCSL clock −0.5%
synthesizer
−1.0%
(SS compatible)
−1.5%

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Table 3. PCIe CLOCKS FROM ON SEMICONDUCTOR WITH PARAMETRICS AND PHASE NOISE
Phase Jitter Spread
No. of PCIe Noise Cycle− Spread Frequency
Part Clock RMS cycle Spectrum Deviation
Number Description Outputs (ps) (ps) Modulation (%) Package
NB3N51044 3.3 V, Crystal to quad 4 0.4 No TSSOP−28
HCSL clock synthesizer
with individual OE
NB3N51054 3.3 V, Crystal to quad 4 0.4 Yes 0% TSSOP−24
HCSL clock −0.35%
synthesizer with I2C
−0.5%

Spread Aware Fanout and Zero Delay Buffers these high performance fanout buffers in PCIe generation I,
The differential fanout clock and data buffers provide a II and III compliant applications. Many of the devices can
choice of either 6, 8, 10 or 21 outputs and the zero delay accept single−ended or differential LVPECL, LVDS and
buffers are offered in 8, 12 and 19 outputs. These buffers are HCSL input clocks, providing flexibility by allowing
ideal for systems requiring multiple copies of high system designers to easily interface to multiple input
precision, low phase noise clocks. Typical additive phase signaling schemes. Moreover these fanout buffers are
jitter as low as 0.1 picoseconds (ps) rms (integrated over spread aware, meaning they replicate the reference clocks
12 kilohertz [kHz] to 20 megahertz [MHz]), and low with spread spectrum.
output−to−output skew of 100 ps (max) enables the use of

Table 4. PCIe FANOUT BUFFERS AND ZDBs FROM ON SEMICONDUCTOR WITH PARAMETRICS AND ADDITIVE
JITTER
Input/ Additive Output− Max
Part Output Jitter output Propagation Frequency
Number Description Ratio (ps) Skew (ps) Delay (ns) (MHz) Package
NB3N106K Clock Fanout Buffer, 1:6 1:6 0.1 100 0.8 400 QFN−24
Differential, 3.3 V, with HCSL
Outputs
NB3N108K Clock / Data Fanout Buffer, 1:8 0.1 100 0.8 400 QFN−32
1:8 Differential, 3.3 V, with
HCSL Outputs
NB3N111K Clock / Data Fanout Buffer, 1:10 0.1 100 0.8 400 QFN−32
1:10 Differential, 3.3 V, with
HCSL Outputs
NB3N121K Clock / Data Fanout Buffer, 1:21 0.1 100 0.8 400 QFN−52
1:21 Differential, 3.3 V, with
HCSL Outputs
NB3W1200L 3.3 V 100/133 Mhz 1:12 0.001 50 100, 133 QFN−64
Differential 1:12 Push−Pull
Clock ZDB/Fanout Buffer for
PCle
NB3N1200K 3.3 V 100/133 Mhz 1:12 0.001 50 100, 133 QFN−64
Differential 1:12 HCSL Clock
ZDB/Fanout Buffer for PCle
NB3W800L 3.3 V 100/133 Mhz 1:8 0.001 50 100, 133 QFN−48
Differential 1:8 Push−Pull
Clock ZDB/Fanout Buffer for
PCle
NB3W1900L 3.3 V 100/133 Mhz 1:19 0.001 50 100, 133 QFN−72
Differential 1:19 Push−Pull
Clock ZDB/Fanout Buffer for
PCle
NB3N1900K 3.3 V 100/133 Mhz 1:19 0.001 50 100, 133 QFN−72
Differential 1:19 HCSL Clock
ZDB/Fanout Buffer for PCle

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PCIe Switch The single−pole, double throw (SPDT) PCIe Switches offer
The differential switches are designed for use in PCIe 2.0 up to six differential channels allowing it to handle up to
and PCIe 3.0 applications and support data rates of up to 8.0 three PCIe lanes, thereby enabling a single controller to
gigabits per second (Gbps). The new devices have low manage three PCIe slots. The NCNx612B family is
supply current requirements of 200 microamperes (mA) and compatible with both Display Port 1.2 and PCIe.
250 mA respectively that also help reduce heat dissipation.

Table 5. PCIe DATA SWITCHES FROM ON SEMICONDUCTOR WITH PARAMETRIC AND GENERATION
APPROPRIATENESS
VCC Max Data PCIe
Part Number Description Channels Configuration min (V) Rate Compatible Package
NCN2411 4−Channel Differential 8 8PDT 1.5 5 Gbps Gen 2 WQFN−42
1:2 Mux/Demux Switch

NCN2612 Data Switch, 12 12PDT 3 5 Gbps Gen 2 WQFN−56

6−Differential Channel
1:2 Switch for PCIe 2.0
and Display Port 1.1
NCN2612B Data Switch, 12 12PDT 3 5 Gbps Gen 2 WQFN−56
6−Differential Channel
1:2 Switch for PCIe 2.0
and Display Port 1.1
NCN3411 Data Switch, 4−Channel 8 8PDT 1.5 8 Gbps Gen 3 WQFN−42
Differential,
1:2Mux/Demux, for PCI
Express Gen3
NCN3612B Data Switch, 12 12PDT 3 8 Gbps Gen 3 WQFN−56
6−Differential Channel
1:2 Switch for PCIe 3.0
and Display Port 1.2

CONCLUSION

ON Semiconductor, a premier supplier of high clock tree can be realized with the PCIe clock synthesizers
performance silicon solutions for energy efficient to provide a clock source to the fanout buffers, and
electronics has a range of components that significantly selectively expand the clock tree using PCIe switches. The
strengthens its portfolio of products to address Peripheral superior performance of each of the ON Semiconductor
Component Interconnect Express (PCIe) applications in components in the Clock Tree alleviate the system timing
communications systems such as routers, servers, problems and strengthen the SerDes system to meet
networking equipment and ATE. Furthermore, a complete stringent clock performance requirements.

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References Clock Jitter In A Serial Link: Theory and

1. PCI Express® Base Specification Revision 3.0, applications in PCI Express”, DesignCon 2005
PCI−SIG, November 10, 2010 InIntegration for PCI Express
2. Bent Hessen−Schmidt, “PCI Express 2.0 Electrical 7. Jeff Reynolds, “Holistic PHY Integration for PCI
specification”, PCI−SIG, 2007 Express”, PCI−SIG, 2006
3. PCI−SIG ENGINEERING CHANGE NOTICE: 8. Jasmin Ajanovic, “PCI Express Technology
Separate Refclk Independent SSC Architecture Overview”, PCI−SIG, 2005
(SRIS) 9. Mike Jackson, Ravi Budruk, “PCI Express
4. Texas Instruments, “SerDes Implementation Guide Technology”, MindShare, 2012
for KeyStone I Device”, 2012 10. Ravi Budruk, Don Anderson and Tom Shanley
5. Jerry C. Chen, “Multi−Gigabit SerDes: The “PCI Express System Architecture”, MindShare,
Cornerstone of High Speed Serial Interconnects”, 2008
Design & Reuse
6. Mike Li, Andy Martwick, Gerry Talbot and Jan
Wilstrup, “Transfer Functions For The Reference

PCI Express and PCIe are registered trademarks of PCI−SIG Corporation.

Intel is a registered trademark of Intel Corporation in the United States and/or other countries.

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