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DDTV

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12 views5 pages

DDTV

Uploaded by

Jagadish Banavath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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AAT-II

DDTV
D. CHAITANYA
22955A0407

1. Define the following terms relevant to Verilog HDL construct and Conventions. (a) Identifiers (b)
Strings (c) Data types.

A: (a) Identifiers: In Verilog, identifiers are names used to represent various constructs such as modules,
wires, registers, and variables. Identifiers must start with an alphabetic character or an underscore (_)
and can be followed by letters, digits, and underscores. Identifiers are case-sensitive (e.g., signal, Signal,
and SIGNAL are different). Reserved words cannot be used as identifiers.

(b) Strings: In Verilog, strings are sequences of characters enclosed in double quotes ("). They are used
for display and debugging purposes but cannot be used in expressions or assignments for data
operations. For example, string_name = "Hello, Verilog"; assigns a string to a variable.

(c) Data types: Verilog has various data types used for different purposes:

• wire: Used to represent a physical wire connecting two points.

• reg: Represents a register that can hold a value and retains it until it is assigned a new value.

• integer: Used for holding integer values (e.g., integer count;).

• real: Used for floating-point numbers.

• time: Represents time values for simulation purposes.

• bit: Represents a 1-bit value, often used in more recent Verilog standards for simplified code.

2. Write short notes on the following with examples. a) Conditional operator b) Concatenation
operator.

A: (a) Conditional Operator: The conditional operator (? :) is used to evaluate a condition and select one
of two values. Syntax: condition ? value_if_true : value_if_false.

• Example: assign result = (a > b) ? a : b; // Assigns 'result' the value of 'a' if 'a' > 'b', else 'b'.

(b) Concatenation Operator: The concatenation operator ({}) is used to join two or more expressions to
create a larger vector.

• Example: assign combined = {a, b}; // Concatenates 'a' and 'b' to form a larger vector.

3. Construct the verilog code for a 4 bit binary to gray code converter using gate level modeling.

A: module binary_to_gray (
input [3:0] binary,
output [3:0] gray
);
assign gray[3] = binary[3];
assign gray[2] = binary[3] ^ binary[2];
assign gray[1] = binary[2] ^ binary[1];
assign gray[0] = binary[1] ^ binary[0];
endmodule.

4. Design a module for addition of two 4-bit inputs. Write a verilog HDL code for 4-bit addition

A: module adder_4bit (
input [3:0] a, b,
output [4:0] sum
);
assign sum = a + b;
endmodule.

5. Differentiate between the case and case-x statement.

A: case Statement: Compares an expression against a set of case items. It is strict and does not allow for
'don't care' conditions.

casex Statement: Similar to case, but allows for 'X' and '?' as 'don't care' conditions. Useful when a
certain value can be ignored during matching.

Example:

case (input_signal)
2'b00: output_signal = 0;
2'b01: output_signal = 1;
2'b10: output_signal = 2;
2'b11: output_signal = 3;
endcase
casex (input_signal)
2'b0X: output_signal = 0; // Matches both 00 and 01.
2'b1X: output_signal = 1; // Matches both 10 and 11.
Endcasex.

6. Write the syntax of repeat loop and explain with example.

A: The repeat loop in Verilog is used for looping a block of statements a specified number of times.

• Syntax:

repeat (expression) begin


// statements to execute
end
• Example:

integer i;
initial begin
repeat (5) begin
i = i + 1;
$display("i = %d", i);
end
end

7. Write a verilog code and test bench for full adder in switch level modeling.

A: Full Adder Module:


module full_adder (
input A, B, Cin,
output Sum, Cout
);
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (B & Cin) | (A & Cin);
endmodule.

Test Bench:

module test_full_adder;
reg A, B, Cin;
wire Sum, Cout;

full_adder uut (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);

initial begin
// Test cases
A = 0; B = 0; Cin = 0; #10;
A = 0; B = 0; Cin = 1; #10;
A = 0; B = 1; Cin = 0; #10;
A = 0; B = 1; Cin = 1; #10;
A = 1; B = 0; Cin = 0; #10;
A = 1; B = 0; Cin = 1; #10;
A = 1; B = 1; Cin = 0; #10;
A = 1; B = 1; Cin = 1; #10;

$finish;
end
endmodule
8. Construct a two-input NOR gate in CMOS logic and write verilog code for NOR gate in switch
levelmodeling.

A: CMOS Logic: A NOR gate can be implemented using PMOS and NMOS transistors. The PMOS
transistors are connected in parallel for the pull-up network, and the NMOS transistors are connected in
series for the pull-down network.
Verilog Code (Switch-Level Modeling):
module nor_gate (
input A, B,
output Y
);
supply1 VDD;
supply0 GND;
wire nA, nB;

// Pull-up network (PMOS transistors)


pmos p1(Y, VDD, A);
pmos p2(Y, VDD, B);

// Pull-down network (NMOS transistors)


nmos n1(Y, GND, A);
nmos n2(Y, GND, B);
endmodule

9. What are the rules to be followed to declare and to use the bidirectional lines?

A: Declaration: To declare a bidirectional line, use the inout keyword.


SYNTAX: inout wire bidir_signal;
Usage: Bidirectional lines must be used with caution to prevent driving conflicts. Typically, one
component should control the line at a time, while others only receive or tri-state their drivers.

10. Write a test bench for moore detector which makes uses of buffer to hold the data.

A: Moore Detector Module:


module moore_detector (
input clk, reset, din,
output reg detected
);
reg [1:0] state, next_state;
reg buffer;

// State machine states


parameter IDLE = 2'b00, S1 = 2'b01, S2 = 2'b10, DETECTED = 2'b11;
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= IDLE;
buffer <= 0;
end else begin
state <= next_state;
buffer <= din;
end
end

always @(state or din) begin


case (state)
IDLE: if (din) next_state = S1; else next_state = IDLE;
S1: if (din) next_state = S2; else next_state = IDLE;
S2: if (din) next_state = DETECTED; else next_state = IDLE;
DETECTED: next_state = IDLE;
default: next_state = IDLE;
endcase
end

always @(state) begin


if (state == DETECTED)
detected = 1;
else
detected = 0;
end
endmodule

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