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Pipelining and ALU

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38 views23 pages

Pipelining and ALU

Uploaded by

Abhishek abhishek
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Pipelining and

ALU
Presented By
Abhishek
00811805220
M.Tech VLSI Design
Pipelining and ALU
Introduction Defining
Pipelining Pipelining
Instructions
Hazards
Structurals Hazards
hazards Data
Hazards Control

ALU
combination ALU
What is
Pipelining?
A mechanism for overlapped execution of several input
sets by partitioning some computation into set of k sub-
computations (or stages).
- Very nominal increase in cost of implementation.
- very significant speedup (ideally ,k).
The Laundry Analogy
● A, B, C, D each have one A B C D
load of clothes to wash, dry,
and fold
● Washer takes 30 minutes

● Dryer takes 30 minutes

● “Folder” takes 30 minutes

●
“Stasher” takes 30 minutes
to put clothes into drawers
If we do laundry
6 PM 7 8
sequentially...
10 11 12 1 2 AM
9
●

30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
●

Time
T A
a
s
k B
O
r C
d
e D
r
To Pipeline, We Overlap Tasks
6 PM 7 8 9 10 11 12 1 2 AM

Time
30 30 30 30 30 30 30
• Pipelining doesn’t help latency of single
T task, it helps throughput of entire
a A
workload
s
k B • Multiple tasks operating
simultaneously
O
r C
d
e D
r

12
Pipelining a Digital System
● Key idea: break big computation up into
pieces

1ns

● Separate each piece with a pipeline


register

200ps 200ps 200ps 200ps 200ps

Pipeline
Register
Pipelining a Digital System
Why do this? Because it's faster for repeated
computations
Non-pipelined:
1operationfinishes
every1ns

1ns

Pipelined:
1operationfinishes
every200ps

200ps 200ps 200ps 200ps 200ps


Comments about
pipelining
Pipelining increases throughput, but not latency
Answer available every 200ps, BUT
-A single computation still takes 1ns
Limitations:
-Computations must be divisible into stage size
-Pipeline registers add overhead
● Suppose we need to perform multiply
and add operation with a stream of
numbers
●

● Each subinstruction is implemented in a


segment within the pipeline. Each segment
has one or two regsiters and a
combinational circuitThe sub operations
●
performed in each segement are as follows

●
Example of Pipeline Processing
Content of Registers in
Pipeline
Space Time Diagram of Pipeline
Speedup
S p e e d u p f r o m pipeline

= Av e ra g e instruction t i m e u n p i p l i n e d/ Ave ra ge instruction t i me


pipelined
C on s i d e r a c a s e for k - s e g m e n t pipeline with a clock cycle t i me t p t o
execute n t a s k s . The first t a s k T1 requires a t i me e q u a l t o k *t p t o
comp l e t e its op e ra t i on s in ce there a r e k s e g m e n t s in pipeline. The
r e ma i n i n g n-1 t a s k s e m e r g e f r o m t he p i p e a t a rate of o n e t a s k p e r
clock cycle a n d t he y will b e comp l e t e d in k + n - 1 clock cycles.
Next, t o c o n c s i d e r a n unpipeline unit t ha t p e r f or ms t he s a m e
op e ra t i on a n d t a k e s a t i m e e q u a l t o t n t o c o m p l e t e t he t a s k . The total
t i me required fro n t a s k s i s n*tn. The s p e e d u p of a pipeline
p r o c e s s i n g o v e r a n e q u i v a l en t non-pipeline p r o c e s s i n g i s defined b y
t he ratio
Speedup
● As the number of tasks increase n becomes much larger
k+n-1 approaches the value of n. Under this condition,
the speed up becomes

●
Where,

●
The speedup then reduces to numer of stages of pipeline
Throughput
Comments about
Pipelining
The good news
- Multiple instructions are being processed at same time
- This works because stages are isolated by registers
- Best case speedup of N
The bad news
- Instructions interfere with each other - hazards
Example: different instructions may need the same piece of
hardware (e.g., memory) in same clock cycle
Example: instruction may require a result produced by an
earlier instruction that is not yet complete
Pipeline Hazards
Limits to pipelining: Hazards prevent next
instruction from executing during its designated
clock cycle
Structural hazards: two different instructions use same h/w in same cycle
Data hazards: Instruction depends on result of prior instruction still in the
pipeline
Control hazards: Pipelining of branches & other instructions that change the PC
ALU
• An arithmetic-logic unit (ALU) is the part of a
computer processor (CPU) that carries out arithmetic and logic
operations on the operands in computer instruction words. In some
processors, the ALU is divided into two units, an arithmetic unit (AU)
and a logic unit (LU). Some processors contain more than one AU -
for example, one for fixed-point operations and another for floating-
point operations.
Combinational ALU
Sub unit 2 i.e logic unit

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