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10:02 AM 10/6/2024 Chapter 2

Course
ME4162: Microprocessor AVR Microcontrollers
Semester 1, 2023 Arithmetic and Logic
Lecturer: Dr. Duong Van Lac Dr. Duong Van Lac
Department of Mechatronics, HUST
Email: [email protected]

9/17/2023 1 9/17/2023 ME4162: Microprocessor 2

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Objectives Some ideas

• The concept of signed numbers and • 100 – 34 = ? (10’s complement) = 66
2’complement • 99 – 34 = ? (9’s complement) = 65
• Addition and subtraction instructions
• Carry and overflow • 100 – 34 = (99-34) + 1
• Logical instruction and masking (10’s comp = 9’s comp +1)
• Compare instruction and branching 115
• Shift, Rotate and Data serialization • 34 – 19 = ? (15)
• BCD, Packed BCD and ASCII conversion. ≜ 34 +100 -19 – 100 = 34 + (99-19)+1 -100 = 15
10’s 9’s
complement complement
of 19 of 19

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Some ideas ADD instruction

• 100000000 – 00101101 = 11010011
• 011111111 – 00101101 + 1 = 11010011 = A
ADD Rd,Rr ;Rd = Rd + Rr ( Direct or immediate are not supported)

1’s complement 2’s complement without a signed bit

Show how the flag register is affected by the following instructions.
• 010110110 – 00101101 = 182-45 = 137 LDI R21,0xF5 ;R21 = F5H
≜ 010110110 + 11010011 - 100000000 =?= 1000 1001 LDI
ADD
R22,0x0B ;R22 = 0x0BH
R21,R22 ;R21 = R21+R22 = F5+0B = 00 and C = 1

2’s complement with a signed bit Solution:

F5H 1111 0101
+ 0BH + 0000 1011
Two's complement:
100H 0000 0000
Step 1: starting with the absolute binary representation of the number, with the
leading bit being a sign bit; After the addition, register R21 contains 00 and the flags are as follows:
Step 2: inverting (or flipping) all bits – changing every 0 to 1, and every 1 to 0, C = 1 because there is a carry out from D7.
which effectively subtracts the value from -1; Z = 1 because the result in destination register (R21) is zero.
Step 3: adding 1 to the entire inverted number, ignoring any overflow. Accounting H = 1 because there is a carry from D3 to D4.
for overflow will produce the wrong value for the result.
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ADD instruction ADC instructions

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ADD Rd,Rr ;Rd = Rd + Rr ( Direct or immediate are not supported)
3C E7
+ 3B 8D
78 74

Write a program to add two 16-bit numbers. The numbers are 3CE7H and 3B8DH.
Place the sum in R3 and R4; R3 should have the lower byte.
Assume that RAM location 400H has the value of 33H. Write a program to find the sum
of location 400H of RAM and 55H. At the end of the program, R21 should contain the sum.
Solution:
Solution:
;R2:R1 = 3B 8D
;R4:R3 = 3C E7
LDS R2,0x400 ;R2 = 33H (location 0x400 of RAM)
LDI R21,0x55 ;R21 = 55
ADD R3,R1 ;R3 = R3 + R1 = E7 + 8D = 74 and C = 1
ADD R21,R2 ;R21 = R21 + R2 = 55H + 33H = 88H, C = 0
ADC R4,R2 ;R4 = R4 + R2 + carry, adding the upper byte
;with carry from lower byte
;R4 = 3C + 3B + 1 = 78H (all in hex)

Notice the use of ADD for the lower byte and ADC for the higher byte.

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SUB instructions SBC instruction

SUB Rd,Rr ;Rd = Rd – Rr (immediate values are not supported) SBC Rd,Rr ;Rd = Rd – Rr – C (immediate are not supported)
SUBI Rd,K ; Rd = Rd – K SBCI Rd,Rr ;Rd = Rd – K – C

27 62 (H)
- 11 96 (H)
Show the steps involved in the following. ---------------
11 CC (H)
LDI R20, 0x23 ;load 23H (35) into R20 ;R26) = 62 (
LDI R21, 0x3F ;load 3FH (63) into R21
;R27) = 27(
SUB R21, R20 ;R21 <- R21-R20

Solution: LDI R28,0x96 ;load the low byte )R28 = 96H(

LDI R29,0x12 ;load the high byte )R29 = 12H(
R21 = 3F 0011 1111 0011 1111 SUB R26,R28 ;R26 = R26 - R28 = 62 - 96 = CCH
- R20 = 23 0010 0011 + 1101 1101 (2’s complement) ;C =borrow =1, N =1
1C 1 0001 1100 SBC R27,R29 ;R27 = R27 - R29 - C
C = 0, D7 = N = 0 (result is positive) ;R27 = 27 - 12 - 1 = 14H
The flags would be set as follows: N = 0, C = 0. (Notice that there is a carry but C = 0.
We will discuss this more in the next section.) The programmer must look at the N (or After the SUB, R26 has =62H -96H =CCH and the carry flag is set to 1, indicating
C) flag to determine if the result is positive or negative. there is a borrow )notice, N =1 .(Because C =1, when SBC is executed R27 has
27H -12H -1 = 14H .Therefore, we have 2762H -1296H =14CCH.

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Multiplication and Division Logic Instructions

Multiplication: AND Rd,Rr ;Rd = Rd AND Rr
MUL Rd,Rr ; R1:R0 = Rd × Rr (Multiply Unsigned) OR Rd,Rr ;Rd = Rd OR Rr
MULS Rd,Rr ; R1:R0 = Rd × Rr (Multiply signed) EOR Rd,Rr ;Rd = Rd XOR Rr ( immediate are not supported)
MULSU Rd,Rr ; R1:R0 = Rd × Rr (Multiply signed with unsigned) COM Rd,Rr ;Rd = 1’s Complement of Rd (11111111 – Rd)
Division: NEG Rd,Rr ;Rd = 2’s Complement of Rd (100000000 – Rd)

.DEF NUM =R20 • AND is used to clear an specific bit/s of a byte

.DEF DENOMINATOR =R21
• OR is used to set an specific bit/s of a byte
.DEF QUOTIENT =R22

LDI NUM,95 ;NUM =95 Show the results of the following.

LDI DENOMINATOR,10 ;DENOMINATOR =10
CLR QUOTIENT ;QUOTIENT =0 LDI R20,0x35 ;R20 = 35H
ANDI R20,0x0F ;R20 = R20 AND 0FH (now R20 = 05)
L1: INC QUOTIENT
SUB NUM, DENOMINATOR Solution:
BRCC L1 ;branch if C is zero
35H 0011 0101
DEC QUOTIENT ;once too many AND 0FH 0000 1111
ADD NUM, DENOMINATOR ;add back to it 05H 0000 0101 ;35H AND 0FH = 05H, Z = 0, N = 0

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Setting and Clearing bits Branch and CP Instructions

AND Rd,Rr ;Rd = Rd AND Rr

OR Rd,Rr ;Rd = Rd OR Rr
CP Rd,Rr ;Rd – Rr (only flags are set)
EOR Rd,Rr ;Rd = Rd XOR Rr ( immediate are not supported)
COM Rd,Rr ;Rd = 1’s Complement of Rd (11111111 – Rd)
NEG Rd,Rr ;Rd = 2’s Complement of Rd (100000000 – Rd)

• AND is used to clear an specific bit/s of a byte

• OR is used to set an specific bit/s of a byte

35H 0 0 1 1 0 1 0 1 04H 0 0 0 0 0 1 0 0
AND 0FH 0 0 1 1 0 1 0 1 OR 30H 0 0 1 1 0 0 0 0
05H 0 0 0 0 0 1 0 1 34H 0 0 1 1 0 1 0 0 • BRVC is used to branch when oVerflow is clear to zero
• BRVS is used to branch when oVerflow is set to one

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ROR instruction ROL instruction

ROR Rd ;Rotate Right ROL Rd ;Rotate Left

In ROR, as bits are rotated from left to right, the carry flag enters the MSB
In ROL, as bits are shifted from right to left, the carry flag enters the LSB and the
and the LSB exits to the carry flag. In other words, in ROR the C is moved to
MSB exits to the carry flag. In other words, in ROL the C is moved to the LSB,
the MSB, and the LSB is moved to the C.
and the MSB is moved to the C.

See what happens to 0010 0110 after running 3 ROR instructions:

SEC ;make C = 1
CLC ;make C = 0 (carry is 0 ) LDI R20,0x15 ;R20 = 0001 0101
LDI R20 , 0x26 ;R20 = 0010 0110 ROL R20 ;R20 = 0010 1011 C = 0
ROR R20 ;R20 = 0001 0011 C = 0 ROL R20 ;R20 = 0101 0110 C = 0
ROR R20 ;R20 = 0000 1001 C = 1 ROL R20 ;R20 = 1010 1100 C = 0
ROR R20 ;R20 = 1000 0100 C = 1 ROL R20 ;R20 = 0101 1000 C = 1

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LSL instruction LSR instruction

LSR Rd ;Logical Shift Right
LSL Rd ;Logical Shift Left
In LSR, as bits are shifted from left to
In LSL, as bits are shifted from right to left, right, 0 enters the MSB and the LSB exits
0 enters the LSB and the MSB exits to the to the carry flag. In other words, in LSR
carry flag. In other words, in LSL 0 is 0 is moved to the MSB, and
moved to the LSB, and the the LSB is moved to the C.
MSB is moved to the C.

this instruction multiplies content of the register by 2 assuming that after this instruction divides content of the register by 2 and carry flag contains
LSL the carry flag is not set. the remainder of division.

In the next code you can see what happens to 00100110 after running 3 LSL In the next code you can see what happens to 0010 0110 after running 3 LSR
instructions. instructions.
CLC ;make C = 0
LDI R20 , 0x26 ;R20 = 0010 0110(38) c = 0 LDI R20,0x26 ;R20 = 0010 0110 (38)
LSL R20 ;R20 = 0100 1100(74) C = 0 LSR R20 ;R20 = 0001 0011 (19) C = 0
LSL R20 ;R20 = 1001 1000(148) C = 0 LSR R20 ;R20 = 0000 1001 (9) C = 1
LSL R20 ;R20 = 0011 0000(98) C = 1; since C=1, content of R20 LSR R20 ;R20 = 0000 0100 (4) C = 1
;is not multiplied by 2

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ASR Instruction BCD, Packed BCD and ASCII conversion.

ASR Rd ;Arithmetic Shift Right
•ASCII
•BCD Codes
ASR means arithmetic shift right. ASR
instruction can divide signed number by 2.
In ASR, as bits are shifted from left to BCD Codes
right, MSB is held constant and the LSB Packed BCD
exits to the carry flag. In other words
MSB is not changed but is copied to D6, BCD1 BCD0
D6 is moved to D5, D5 is moved to D4
and so on.

In the next code you can see what happens to 0010 0110 after running 5 ASR
instructions.
LDI R20, 0xD0 ;R20 = 1101 0000(-48) C = 0
ASR R20 ;R20 = 1110 1000(-24) C = 0
ASR R20 ;R20 = 1111 0100(-12) C = 0
ASR R20 ;R20 = 1111 1010(-6) C = 0
ASR R20 ;R20 = 1111 1101(-3) C = 0 ASCII and BCD Codes for Digits 0–9
ASR R20 ;R20 = 1111 1110(-1) C = 1

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Packed BCD to ASCII conversion

To convert packed BCD to ASCII:
• you must first convert it to unpacked BCD.
• Then the unpacked BCD is tagged with 011 0000
(30H).

Packed BCD = 1001 0010

Unpacked BCD = 0000 1001 , 0000 0010

ACSII = 0011 1001 , 0011 0010

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