10/9/2023

7:00 AM 10/9/2023 Chapter 2

Course
ME4162: Microprocessor AVR Microcontrollers
Semester 1, 2023 Introduction to Assembly
Lecturer: Dr. Duong Van Lac Dr. Duong Van Lac
Department of Mechatronics, HUST
Email: [email protected]

9/17/2023 1 9/17/2023 ME4162: Microprocessor 2

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Prepared by Duong Van Lac. Email: [email protected]

Topics AVR’s CPU

◼ AVR’s CPU ◼ AVR’s CPU
◼ Its architecture ◼ ALU
◼ Some simple programs ◼ 32 General Purpose registers (R0 to R31)
◼ Data Memory access ◼ PC register R0

◼ Program memory ◼ Instruction decoder ALU R1

R2
◼ RISC architecture

…
RAM EEPROM Timers

PROGRAM
SREG: I T H S V N Z C
Flash ROM R15
Program
Bus
CPU
Data
Bus CPU R16
R17

…
PC
Interrupt Other
OSC Ports R30
Unit Peripherals
Instruction decoder
R31
I/O
PINS Instruction Register
registers

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Some simple instructions Some simple instructions

1. Loading values into the general purpose registers 2. Arithmetic calculation

LDI (Load Immediate) ◼ There are some instructions for doing Arithmetic
◼ LDI Rd, k and logic operations; such as:
◼ Its equivalent in high level languages: ADD, SUB, MUL, AND, etc.
Rd = k ◼ ADD Rd,Rs
◼ Example: R0 ◼ Rd = Rd + Rs R0
R1 R1
◼ LDI R16,53
ALU
R2 ◼ Example: ALU
R2

ADD R25, R9

…
◼ R16 = 53 SREG: I T H S V N Z C ◼ SREG: I T H S V N Z C

R25 = R25 + R9
R15 R15
◼ LDI R19,$27 CPU R16 ◼
CPU R16

◼ LDI R23,0x27
R17
◼ ADD R17,R30 R17

…
PC PC
◼ R23 = 0x27 R30
◼ R17 = R17 + R30 R30
Instruction decoder Instruction decoder
LDI R23,0b11101100
R31 R31
◼ Instruction Register Instruction Register
registers registers

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A simple program A simple program

◼ Write a program that calculates 19 + 95 ◼ Write a program that calculates 19 + 95 + 5

LDI R16, 19 ;R16 = 19

LDI R16, 19 ;R16 = 19
LDI R20, 95 ;R20 = 95
LDI R20, 95 ;R20 = 95
LDI R21, 5 ;R21 = 5
ADD R16, R20 ;R16 = R16 + R20
ADD R16, R20 ;R16 = R16 + R20
R0 ADD R16, R21 ;R16 = R16 + R21
ALU R1
R2
…

LDI R16, 19 ;R16 = 19

SREG: I T H S V N Z C
R15 LDI R20, 95 ;R20 = 95
CPU R16
R17 ADD R16, R20 ;R16 = R16 + R20
…

PC LDI R20, 5 ;R20 = 5

R30 ADD R16, R20 ;R16 = R16 + R20
Instruction decoder
R31
Instruction Register
registers

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Some simple instructions Some simple instructions

2. Arithmetic calculation 2. Arithmetic calculation

◼ SUB Rd,Rs ◼ INC Rd

◼ Rd = Rd - Rs ◼ Rd = Rd + 1
◼ Example: ◼ Example:
◼ SUB R25, R9 ◼ INC R25
◼ R25 = R25 - R9 R0 ◼ R25 = R25 + 1 R0
ALU R1 ALU R1
◼ SUB R17,R30 R2 R2

R17 = R17 - R30 DEC Rd

…
◼ SREG: I T H S V N Z C ◼ SREG: I T H S V N Z C
R15 R15

CPU R16 ◼ Rd = Rd - 1 CPU R16

R17 R17
◼ Example:

…
PC PC

Instruction decoder
R30 ◼ DEC R23 Instruction decoder
R30
R31 R31
Instruction Register
registers
◼ R23 = R23 - 1 Instruction Register
registers

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Prepared by Duong Van Lac. Email: [email protected]

Data Address Space Data Address Space

Address Name Address Name Address Name
Mem. I/O Mem. I/O Mem. I/O
$20 $00 - $36 $16 TIFR1 $4C $2C SPCR0
$21 $01 - $37 $17 TIFR2 $4D $2D SPSR0
$22 $02 - $38 $18 - $4E $2E SPDR0 RAM EEPROM Timers RAM EEPROM Timers
$23 $03 $39 $19 - $4F -
General General
PINB $2F
$24 $04 DDRB $3A $1A - $50 $30 ACSR Purpose Purpose
PROGRAM PROGRAM
$25 $05 PORTB $3B $1B PCIFR $51 $31 DWDR Registers Registers
$26 $06 $3C $1C EIFR ROM ROM
PINC $52 $32 -
$27 $07 DDRC $3D $1D EIMSK $53 $33 SMCR
$3E $1E GPIOR0
Program
CPU Data Program CPU Data
$28 $08 PORTC $54 $34 MCUSR
$29 $09 PIND $3F $1F EECR $55
Bus
$35 MCUCR Bus address bus Bus Bus address bus
$2A $0A DDRD $40 $20 EEDR $56 $36
data bus data bus
- control bus control bus
$2B $0B PORTD $41 $21 EEARL $57 $37 SPMCSR Data Data
$2C $0C - $42 $22 EEARH $58 $38 -
$2D $0D - $43 $23 GTCCR $59 $39 -
Bus Data Data Bus
R0
Data
$2E $0E - $44 $24 Data
TCCR0A $5A Address Address
R0 $3A - R1
Address Address R2
$2F $0F - R1
$45 $25 TCCR0B $5B $3B - $0000 General $0000 General

...
$0000 R2 $0000
$30 $10
General - $46 $26 TCNT0 $5C
General $3C - Other Purpose Purpose Other
Interrupt Interrupt

...
...
...

R31
$31 $11
Purpose - Purpose OSC Ports Example:
$001F Write
Registers a program
OSCthat adds the contents Portsof the PINC I/O
...

$47 $27 OCR0A $5D $3D Registers

...

SPL Peripherals $001F Peripherals

Registers -
R31
Registers Unit Unit
$32
$001F $12 $48 $28 OCR0B
$001F $5E $3E SPH
register to Registers
the contents of PIND IN (IN
Using
and fromthe
Names
stores IO I/O
of location)
registers
to I/Oresult in location 0x90
$0020 $0020 Standard I/O
$33 $13 - $49 $29 - $5F $3F SREG Standard I/O I/O Address
$0020
$34 Standard
$14 I/O I/O Address
$0020
Standard I/O Registers $00 OUT (OUT location)

...

...
- $4A $2A$00 GPIOR1 $01
Registers Registers I/O (SFRs) of the SRAM (SFRs) I/O
...

...

$35 $15
(SFRs) TIFR0 $4A
Example: $005F
$2A$01
Add contents of location
GPIOR2
Example:0x90
(SFRs)
Storeto0x53
contents of location
into the 0x95 and
SPH register.
PINS
The store
$005F $005F
PINS

...
$005F
IN Rd,IOaddress ;Rd = [addr]
...

$0060 $0060
$0060 Example: What
the result$0060 does the
in location following
0x313. LDS
STS instruction
(Load
(Storedirect
direct do?
from data0x80
to data space)
space)
$3E
Solution: Example:
$3E
Example: Write
Example: Write programaddress
aa program
Extended that
that of
stores
copiesSPH
55
the is 0x5E
into location
contents of 0x80
of location RAM.of RAM Extended SREG $3F Extended
OUT IOAddr,Rd ;[addr]=Rd

...
Extended SREG $3F
I/O Memory I/O Memory
...

I/O Memory I/O Memory

LDS R20,2
$00FF $01FF
$00FF
intoSolution:
$01FF
location 0x81. IN Internal
R20,PINC OUT =SPH,R12
;R20 PINC ;OUT 0x3E,R12
$0100 $0200 LDS Rd, addr ;[addr]=Rd
STS addr,Rd ;Rd = [addr] $0100
Internal
$0200

0x90 Solution:;R20 = [0x90]

Internal Internal
Example:
...

...
LDS R20, SRAM SRAM
...

...

SRAM
Solution:
Answer: $21FF
SRAM
IN R21,PIND
$21FF
IN
;R21 =R15,SREG
PIND
Example: ;IN R15,0x3F
$2200
LDS External
R21, 0x95 LDI ;R21R20,= 0x53
[0x95] ;R20 = 0x53
55 Example:
$2200
External Solution:
LDI R20, ;R20 = 55 External
SRAM
ADDSRAM
External
R20,R21 ;R20
IN R1, 0x3F
= R20 + R21 ;SREG = R12
;R1 = SREG
$FFFF
SRAM
It copies
ADD the
$FFFF
contents
SRAM
R20, R21 of STS
R2 into R20;= asR20
;R20
0x5E, 2 is+the
R20 R21address
;SPH of
= R2.
R20 $FFFF $FFFF OUT 0x3F,R12
STS 0x80,
LDS ATmega640/V
R20, 0x80 R20 LDS
;[0x80]
STS R1, = R20
0x60
;R20
0x60,R15 = 55
= [0x80] ; [0x60] = R15 ATmega328
ATmega640/V
IN R17,0x3E ;R17 = SPH
ATmega328 ATmega1280/V
STS ATmega1281/V
0x313, R20 ;[0x313] = R20
STS 0x90,R20
ATmega1280/V
;[0x90] = R20
ATmega64
ATmega128 STS ATmega2560/V
0x81, R20 ;[0x81] = R20 = [0x80]
ATmega64
ATmega128
ATmega1281/V
ATmega2560/V
OUT 0x3E,R15 ;SPH = R15
ATmega2561/V ATmega2561/V

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Machine Language Status Register (SREG)

ADD R0,R1 SREG: I T H S V N Z C

◼
Carry
Interrupt oVerflow Zero
Temporary Negative
000011 00 0000 0001 Sign Data Address
opcode operand Half carry N+V Space
Example: Show
Example:
Example:
Example: Show the
Show
Show thestatus
the
the statusof
status
status ofthe
of
of theC,
the
the C, H,
C,
C, H,$0000
H,
H, andZZ
and
and
and ZZ flagsafter
flags
flags
flags afterthe
after
after theaddition
the
the addition
$0001 General
subtraction
subtraction
of
of 0x9C of 0x23
0x38 and of 0x9C
0x73
0x64
0x2F from
in from
from
the 0x9Cin
0xA5
0x52
followinginthe
thefollowing
following
instructions: instructions:
instructions:
Purpose

...
◼ LDI R16, 2 LDI
LDI R20,
R20,
LDILDI R20, 0x9C
0xA5
0x52
R16, 0x9C
0x38 ;R16 = 0x38
R0
Registers
$001F IO Address
LDI
LDI R21,
R21, 0x9C
0x23
0x73R1
LDI R17, 3
$00
ALU
LDILDI R21,
R17, 0x64
0x2F ;R17 = $0020
0x2F $01
R2 Standard IO
SUB
SUB R20,
R20, R21
R21 ;subtract
;subtract R21
R21 from R20
from R20

...
ADD
ADD R20,
R16, R21
R17 ;add
;add R21
R17 toto R20
R16

...
Registers

…
ADD R16, R17 SREG: I T H S V N Z C
Solution:
Solution:
$005F
SPH
SREG
$3E
$3F
Solution:
Solution: R15 11

CPU
$0060
$52
$9C
$A5 0101 0010
10011100
1010 1100
0101R16
$38
$9C 0011
1001 1000
- $23
$73 0111
R17 0011

...
+-- +$64
$9C
$2F 10010100
0010
0110 1100
0011
1111
$DF 1101 1111 R20
R20 === $DF

…
1110 0000 0000 0010 PC
$00
$82 0000
1000
$67 0000
00100110 0111R20 $00
$82
R16is==a00
0x67
C = 1 because R21 is bigger0000
$100 1 0000 R20
than R20 and there borrow from D8 bit.
C===100because
C becausethere
because R21 is
R21 is not
isnot bigger
bigger than R20
than R20 andbit.
and there is
there is no
no borrow
borrow from
from D8
D8 bit.
bit.
1110 0000 0001 0011 Z
C
C
== 00 decoder
because
because the
thereR20
is has
no
a carry
R30
a value
carry
beyond the D7
otherthe
beyond than
D7zero after the subtraction.
Instruction
Z=
Z
H == 1
01 because
because there
because the R20
the R20 iscarry
is ahaszero after
a value
from the D3
other
the than 0 bit.
subtraction.
to theafter the subtraction.
D4 bit.
0000 1111 0000 0001 H = 1 because there isR31 a borrow
carry from
from D4D3
the toto
D3.
the D4 bit.
H===100because
ZH
Instruction
becausethe
because there
there
R20 is(the
is no borrow
no borrow fromaD4
result) from
has D4 to D3.
to
value D3.
0 in it after the addition.
Z = 0Register
because the R16 (the result) has a value other than 0 after the addition.
registers
$FFFF

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Assembler Assembler Directives

.EQU and .SET
Assembly
◼ .EQU name = value
EDITOR ◼ Example:
PROGRAM assembler
.EQU COUNT = 0x25
myfile.asm
LDI R21, COUNT ;R21 = 0x25
ASSEMBLER LDI R22, COUNT + 3 ;R22 = 0x28
PROGRAM Machine

.SET name = value

Language
◼

◼ Example:
myfile.eep myfile.hex myfile.map myfile.lst myfile.obj
.SET COUNT = 0x25
LDI R21, COUNT ;R21 = 0x25
DOWNLOAD TO DOWNLOAD TO LDI R22, COUNT + 3 ;R22 = 0x28
AVR’s EEPROM AVR ’s FLASH
.SET COUNT = 0x19
LDI R21, COUNT ;R21 = 0x19

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Assembler Directives Assembler Directives

.ORG .INCLUDE

◼ .ORG address ◼ .INCLUDE “filename.ext”

M328def.inc
.equ SREG = 0x3f
00 E205
.equ SPL = 0x3d
01 0000 .equ SPH = 0x3e
Program.asm 02 0000 ....
.ORG 0 03 0000
LDI R16, 0x25 04 0000
assembler
.ORG 0x7 05 0000
LDI R17, 0x34 06 0000
LDI R18, 0x31 Program.asm
07 E314
08 E321
LDI R20, 10
09 0000
OUT SPL, R20
0A 0000

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Flash memory and PC register Fetch and execute

00 E205
◼ Old Architectures 00 E205
LDI R16, 0x25 01 E314 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
02 E321 Instruct 4
03 0F01
ADD R16, R17 03 0F01 Instruct 3
ADD R16, R18 04 0F02 Instruct 2 04 0F02
LDI R17, 11 0516-bit
0516-bit
E01B Instruct 1 E01B
ADD R16, R17
06 0F01 06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300 07 9300
RAM EEPROM Timers 08 0300 RAM EEPROM Timers
08 0300 Fetch
09 940C 09PROGRAM
940C
PROGRAM
ALU Flash0009
ROM ALU
Flash0009
0A ROM 0A
PC: 3
0
9
1
5
2
A
7
4 PC: Data
16bit
8
B
6 Data
CPU Bus CPU Bus
14bit
Execute
Instruction dec. Instruction dec.
Program Program
Bus Bus

Interrupt Other Interrupt Other

OSC Ports OSC Ports
Unit Peripherals Unit Peripherals

I/O I/O
PINS PINS

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Pipelining How to speed up the CPU

◼ Pipelining 00 E205
◼ Increase the clock frequency
01 E314 ◼ More frequency ➔ More power consumption &
Instruct 4
02
03
E321
0F01
more heat
Instruct 3 04 0F02 ◼ Limitations
Instruct 2
Change the architecture
0516-bit
E01B
Instruct 1 06 0F01
◼
07 9300 ◼ Pipelining
RAM EEPROM Timers
RISC
08 0300
Fetch 09PROGRAM
940C
◼
Flash0009
ROM ALU
0A
PC: Data
CPU Bus
Execute Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

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Changing the architecture RISC architecture

RISC vs. CISC
◼ Feature 1
◼ CISC (Complex Instruction Set Computer) ◼ RISC processors have a fixed instruction size. It
◼ Put as many instruction as you can into the CPU makes the task of instruction decoder easier.
In AVR the instructions are 2 or 4 bytes.
RISC (Reduced Instruction Set Computer)
◼
◼
◼ In CISC processors instructions have different
◼ Reduce the number of instructions, and use your lengths
facilities in a more proper way.
◼ E.g. in 8051
◼ CLR C ; a 1-byte instruction
◼ ADD A, #20H ; a 2-byte instruction
◼ LJMP HERE ; a 3-byte instruction

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RISC architecture RISC architecture

◼ Feature 2: reduce the number of instructions ◼ Feature 3: limit the addressing mode
◼ Pros: Reduces the number of used transistors ◼ Advantage
◼ Cons: ◼ hardwiring
◼ Can make the assembly programming more difficult ◼ Disadvantage
◼ Can lead to using more memory ◼ Can make the assembly programming more difficult

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RISC architecture RISC architecture

◼ Feature 4: Load/Store ◼ Feature 5 (Harvard architecture): separate buses for
opcodes
LDS R20, and
0x100 operands
; R20 = [0x100]
ADD R20, R21
◼ Advantage:
ADD R20,R21opcodes and+operands
; R20 = R20 R21 can go in and out of the CPU
LDS R20, 0x100
LDS R20, 0x200 together.
LDS R21, 0x220
ADD R20, R21
◼ Disadvantage: leads to more cost in general purpose computers.
STS 0x230, R20 Fetch

RAM EEPROM Timers

PROGRAM
ALU
Flash ROM Execute
PC: Data
CPU Bus
Instruction dec.
Program
Bus
Control bus Control bus
Code Data
Interrupt
Ports
Other Memory Data bus CPU Data bus Memory
OSC Unit Peripherals
Address bus Address bus
I/O
PINS

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RISC architecture RISC architecture

◼ Feature 6: more than 95% of instructions are ◼ Feature 7
executed in 1 machine cycle ◼ RISC processors have at least 32 registers.
Decreases the need for stack and memory
usages.
◼ In AVR there are 32 general purpose registers (R0
to R31)

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