Simulation of DC-DC Buck Converter*

* Homework 1 for Power Electronics Converter (EE5416)

1st Andi Falih Maulandi Andika Putra

Electrical Engineering Department Master’s Program
National Sun Yat Sen University
Kaohsiung, Taiwan
Student ID M113010159
[email protected]

Abstract—A Buck Converter is a voltage step-down and cur- have zero voltage drop when on and zero current flow when
rent step-up converter. It is a DC-DC converter. Buck converter is off. Also, The inductor has zero series resistance. Further, it is
the most basic Switched-Mode Power Supply (SMPS) topology. assumed that the input and output voltages do not change over
It is widely used throughout the industry to convert a higher
input voltage into a lower output voltage. The Buck Converter the course of a cycle (this would imply the output capacitance
is used in SMPS circuits where the DC output voltage needs as being infinite). The ratio of output voltage, Vo to input
to be lower than the DC input voltage. Desired target is to voltage, Vi can be adjusted by varying the duty ratio of switch
design Buck Converter for 15 V input with output 5V @10W. using PWM Signal. In the PWM switching at a constant
In this report will including the design details, required wave switching frequency, the switch control signal Vtri , which
forms to verify the correctness of the circuit, the voltage gain,
inductor current/output voltage ripple, stray components and controls the state (on or off) of the switch, is generated by
their influences, efficiency charted from rated down to 10% comparing a signal-level control voltage Vref , with a repetitive
load, the switching loss, and performance comparison of different waveform as shown in Figure 2.
selections of devices.
Index Terms—buck converter, design, wave forms, gain, ripple,
efficiency, switching loss

I. I NTRODUCTION
A buck converter is a step-down converter. For a DC–DC
converter, input and output voltages are both DC. It uses a
power semiconductor device as a switch to turn on and off
the DC supply to the load. The basic operation of the buck
converter has the current in an inductor controlled by single
switches with a diode or two switches. The switching action Fig. 2. Switch control signal generation
can be implemented by a BJT, a MOSFET, or an IGBT. Figure
The frequency of each cycle is called switching period Ts . if
1 shows a diagram of a buck converter that accepts a DC
carrier signal voltage Vtrig is above Vref , switch will changing
input and uses pulse-width modulation (PWM) of switching
state to off and vice versa. To control the duration of on Ton
frequency to control the switch. An external diode, together
or 0 − DTs is by changing the voltage reference Vref . the
with external inductor and output capacitor, produces the
ratio between Vref and Vtrig known as duty ratio of switch
regulated dc output.
or called duty cycle. Duty cycle is always being presented in
percentage value. A 60% duty cycle means the power is on
60% of the time and off 40% of the time. The switch duty
ratio can be expressed as
Vref ton
= =D (1)
Vtrig Ts
Basic Switching, is have a very high ripple and not accept-
Fig. 1. Schematic of Buck Converter able for any use, thus we need to add low pass filter such as
inductor and capacitor to compensate the output ripple.
The buck converter can operate in two different modes;
II. L ITERATURE R EVIEW
continuous conduction mode (CCM) and discontinuous con-
A. Basic of Operation duction mode (DCM) shown by Figure 3. The difference
In an idealised buck converter, all the components are between the two is that in CCM the current in the inductor does
considered to be perfect. Specifically, the switch and the diode not fall to zero. A buck converter operates in continuous mode
if the current through the inductor never falls to zero during the initial value for the next cycle. but for the first cycle the value
commutation cycle. In DCM, the current through the inductor of imin is zero.
falls to zero during part of the period. Practically, converter As an ideal converter, total current flowing to inductor is
can operated in either operation modes. but, the design point or same as current flowing from the source and since diode is
component selection will be based on the heavy load and this reverse biased, the current flowing in diode is 0.
is mostly at CCM. So, in this design, we will be considering
I s = I L , ID = 0
to use a CCM operation.
From explation below we can plot the value of each signal
with its time period 0 − DTs shown in Figure 5.

Fig. 3. Operation Mode

The operation of a buck converter happens in two modes.

The first mode is when switch close or on, and the second is
when switch open or off.

Fig. 4. Switch is on

When switch closes shown in Figure 4, voltage in the gate

is high VGS and current Is flows from the supply voltage Vi
Fig. 5. 0 − DTs interval waveform
through the switch. Inductor current IL flow through inductor
L and into the load, thus charging the inductor by increasing its When the switch opens shown in Figure 6, the voltage on
magnetic field. Diode D will be on reverse bias, thus blocking the switch gate VGS is low, so power supply Vin is no longer
the path for current. Thus supply Voltage Vi will be same connected. The inductor acts as a source and maintains the
as diode Voltage Vd . Inductor current flows into load Io and current through the load resistor thus make the diode become
Capacitor ic thus store energy and smoothing the output ripple. forward bias and current may flow.
We can make circuit equation using Kirchoff Current Law.

Vs = 0, VD = Vin
−Vin + Vo + VL = 0
VL = Vin − Vo (2)
when current flow to an inductor, or charging, we can
calculate with this equation. Fig. 6. Switch is off
diL VL
= During this period, the energy stored in the inductor de-
dt L creases and its current VL falls . Current continues to flow
combine it from equation (2), then we can get the inductor in the inductor through the diode D as the magnetic field
current by integrate the equation. collapses and the inductor discharges. We can make circuit
Z equation using Kirchoff Current Law.
1 0
iL (t) = (Vin − Vo )dt + imin (3)
L DTs
Vs = Vin , VD = 0
It is important that there is continuous conduction through
VL = −Vo (4)
the load for this circuit. imin it is indicate that before the
inductor completely discharges, switch is closed and diode D when current flow to an inductor, or charging, we can
is open/reverse bias and the cycle repeats, so there is some calculate with this equation.
 Vo Vo
D= = (6)
diL VL Vin Vd
=
dt L
if we neglecting all losses in the circuit, then
combine it from equation (2), then we can get the inductor
current by integrate the equation. Pi = Po
Z
1 DTs
iL (t) = −Vo , dt + imax (5) Vi I i = Vo I o
L Ts
as an ideal converter, total current flowing to diode is same Io Vi 1
= = (7)
as current flowing from the inductor, the current flowing in Ii Vo D
switch is 0. Since it is a buck converter, the maximum voltage is same
Is = 0, ID = IL or less as input shown by this equation
From explation below we can plot the waveform shown in To n
Figure 7. D= ≤1
Ts
Vo ≤ Vin

III. D ESIGN O BJECTIVE

Buck Converter run in the CCM mode and have a specifi-
cation shown at table below

TABLE I
D ESIGN TARGET

No Variable Symbol Value

1 Input Voltage Vi 15 Volt
2 Output Voltage Vo 5 Volt
3 Output Power Po 10 Watt
4 Switching Frequency fs 100 kHz
5 Output Voltage Ripple ∆Vo % 1-2%
6 Inductor Current Ripple ∆IL % 10-15%

If we assume the input is an ideal and stable input. Then we

only need to determine suitable component such as Inductor
and Output Capacitor.
Fig. 7. Switch Q Opened
IV. C OMPONENT S ELECTION
when the cycle repeat, Average inductor voltage over a
switching time period (Ts) is equal to zero so the value on A. Load
the first period are the same with the second period, shown in Input voltage Vi is 15 Volt with target output Voltage Vo
figure below. is 5 Volt with rated power or the converter P is 10 Watt
with overall efficiency around 90%. The first step to calculate
the switch current is to determine the duty cycle, D, for the
maximum input voltage. The maximum input voltage is used
because this leads to the maximum switch current. The Duty
cycle need to charted from 10% (Pm in) load to 100% (Pm ax)
Vi 15
D= = = 0.333
Fig. 8. Balance Condition
Vo 5
Maximum current flow in the system, for ideal coverter
so we can make a balance condition in equation below from
Equation 2 and 4. Po 10
Ii = Io = = = 2A
Vin 5
(Vin − Vo )DTs = Vo (1 − D)Ts
Thus we can calculate the output resistor
Vin − Vo D = Vo − Vo D
P 10 4
Vo = Vin D R= 2
= = 2.5Ω
I 2
B. Inductor C. Capacitor
We know that for buck converter in steady state, the inductor Each cycle, when the inductor current exceeds the output
current is same as the output current. current, the output capacitor voltage increases. When the
inductor current is less than the output current, the output
IL = Io = 2A (8) capacitor voltage decreases. To achieve the correct average
output current and a constant DC output voltage, the amount
for max Inductor current ripple is known, ∆IL = 15% thus of the output capacitor charging must be equal to the amount of
output capacitor discharging. The steady avenge state current
∆IL , max = 0.1 ∗ IL = 0.15 ∗ 2 = 0.3A (9) through the capacitor is 0A. From the figure 9 we can estimate
Maximum and Minimum inductor current ripples are
∆IL 0.2
Imax = Io + =2+ = 2.1A (10)
2 2

∆IL 0.2
Imin = Io − =2− = 1.9A (11)
2 2
To find the inductor value. We need to analyze when switch
is closed. from Equation 3. We know that
(Vi − Vo )DTs
∆IL = (12)
L
if we subtitute Equation 6 we can get
V o(1 − D)Ts
∆IL = (13)
L
we know that the period is the reciprocal of the frequency.
Fig. 9. Output Voltage Ripple
1
Ts = (14)
fs voltage ripple.
Thus, equation for Inductor is ∆Q 1 1 ∆IL Ts ∆IL Ts
∆Vo = = =
C C2 2 2 8C
Vo (1 − D)
L= (15)
∆IL ∗ fs ∆IL
C= (18)
(∆Vo )(8)(fs )
if we subtitute variable with value then,
From Design target we know the Voltage ripple ∆Vo % is 1%.
5(1 − 0.333)
L= = 166.75uH thus
0.2 ∗ 100000
∆Vo , max = (∆Vo %)(Vo ) = (0.01)(5) = 0.05V (19)
Inductor value above is theoretical value and we need
to adjust with availability of the Inductor in market that if we substitute the value,
also capable with maximum current flowing in the inductor.
The suitable Inductor is Coilcraft Shielded Power Inductors 0.185
C= = 4.62uF (20)
MSS1210-184KED 180uH 2.4A. From Datasheet we found (0.05)(8)(100000)
that internal resistance of the inductor is rL = 0.173Ω. internal for capacitor voltage, is better more than with output voltage
resistance will be used to calculate power loss. max, thus
To measure if within inductor current ripple target ∆IL % < ∆Vo
15%, Then, we can use Equation 15. V c > Vo + = 5.025V
2
Vo (1 − D) 5(1 − 0.333) Capacitor value above is theoretical value, the common ca-
∆IL = = = 0.185A (16) pacitor value is 10uF 10V YAGEO SMD Multilayer Ceramic
L ∗ fs 0.00018 ∗ 100000
Capacitor CC0805ZKY5V6BB106. To measure if within out-
Inductor Current ripple is below limit, so it is suitable for use put voltage ripple ∆Vo % target <2%, we can use equation 17
in the design. The maximum inductor current with this device to find ∆Vo first.
is
∆IL 0.185 ∆IL
ILmax = Io + =2+ = 2.092A (17) ∆Vo = = 0.0231V (21)
2 2 (C)(8)(fs )
With this capacitor, the maximum voltage output is
∆Vo
Vomax = Vo + = 5.011V (22)
2
Output voltage ripple is below limit, so it is suitable for
use in the design. Next we need to calculate Equivalent Series
Resistance (ESR) of the capacitor. In converter design, ESR
of capacitor is chosen as
∆Vo , max
ESRlimit ≤ (23)
∆IL
0.05
ESRlimit ≤ = 0.270Ω
0.185
ESR is usually not explicitly exposed in datasheet, but given Fig. 10. Simulation Circuit Schematic
with tan δ. From Datasheet we found value of tanδ = 0.025
in room temperature (25◦ C). thus
tanδ = ESR ∗ 2π ∗ f ∗ C (24)
0.025
ESR = = 0.003Ω
2 ∗ 3.14 ∗ 100000 ∗ 0.00001
ESR is below the limit, so it is suitable for use as well.
D. Switch
When the switch and diode are in conducting state, ideally
the voltages across them are zero. However, when the switch
is off, and diode is reverse biased, the input voltage appears
across them. Thus the voltage rating of switch and diode is
the maximum input voltage.
VSmax = VDmax = Vin = 15V (25)
Fig. 11. Simulation Waveform
When the switch is off and diode is reverse biased, no
current flow through them. However, when the switch is ON,
IS and the current flow at diode ID its shown that the value
and diode is forward biased, they conduct the inductor current.
of the switch and the diode is opposite with each other, due to
Thus the current ratings of switch and diode are defined by
switching action. The last figure is the value of current flowing
the maximum inductor current.
in the inductor ILmax which is around 2.08A this is also close
∆IL with the analysis shown in Equation 17.
iSmax = iDmax = Imax = Io + = 2.089A (26)
2
VI. L OSSES
We can select an IRF540N Power MOSFET by INFINEON.
From Datasheet is known that breakdown voltage 100V with In a non ideal converter there are losses in the component
maximum current drain current 33.A, with rDS(on) = 0.044 such as switching losses PSloss , diode losses PDloss , inductor
Ω. For diode, we select SK54C Schottky diode by Taiwan losses PLloss
Semiconductor. From Datasheet we known the voltage rating A. Duty Ratio
is 40V and current rating 5A with forward voltage 0.55V at
There are conduction losses in components that are im-
room temperature (25◦ C).
portant in determining D, the duty factor. if we taking these
V. S IMULATION losses into account, for the ideal condition we can look from
Equation 6. We can now express the duty cycle of the buck
Simulation using PSIM, here we can verify our result via
converter as :
waveform analysis. The schematic used in PSIM is shown in
an image below. the condition of the circuit is ideal, thus not Vo + VDF
including losses and voltage drop. D= (27)
Vi − VQL + VDF
From figure above, at the firs waveform we see the output
VD = Forward Diode Voltage Drop VQ = Switching Voltage
voltage Io thus have maximum voltage at 5.005V which
Drop
according to the design target is below 1% ripple and close
we need to estimate the voltage drop of the MOSFET
with the analysis shown in Equation 22. The second waveform
switch, thus
is input and output voltage, also according to the design target
is 5V/15V. The third waveform is the current flow at switch VQL = ISmax rDS(on) = (2.089)(0.044) = 0.092V
 1
then PSLtrf = (70.10−9 ).(2.089).15.105 = 0.1096W
5 + 0.55 2
D = Dmax = = 0.359
15 − 0.097 + 0.55 Total Mosfett Switching Power Loss
Dmax for non ideal cicruit is 0.359, this slightly higher
PSSLoss = PSLgate + PSLcoss + PSLtrf = 0.1266W
than ideal duty ratio because of voltage drop on the system.
we need to calculate Inductor curent ripple by applying new For total power loss of MOSFET Switch is
duty cycle value using Equation 15.
PSloss = PSCLoss + PSSLoss = 0.3186W (32)
Vo (1 − D) 5(1 − 0.359) C. Diode Losses
∆ILa = = = 0.178A (28)
L ∗ fs 0.00018 ∗ 100000 for diode we simply calculate the power loss by knowing
thus for maximum and minimum current is current flow in the diode.
∆IL 0.178 If = Imax (1 − D) (33)
Imax = Io + =2+ = 2.089A
2 2
B. Switch Losses If = 2.089 ∗ (1 − 0.359) = 1.339A
For calcualting total power losses in the MOSFET switch, PDloss = VDF IF = (0.55)(1.339) = 0.736W
we have to know the power losses because of conduction loss
D. Inductor Losses
and Switching loss. For the MOSFET Conduction loss, we
can calculate the power flow into MOSFET affected by the For inductor power losses we simply calculate the power
internal resistance from Drain to Source. MOSFET Switching losses because of inductor internal resistance,
Power loss due to gate charge, Output Capacitance (COSS) 2
PLloss = rL Imax = (0.173)(2.089)2 = 0.757W
and rise and fall times. we need to know some value from
Datasheet. E. Total Losses
So total power losses in the system is
TABLE II
MOSFET VARIABLE Ploss = PSloss + PDloss + PLloss = 1.8116W (34)
No Variable Symbol Value F. Efficiency
1 Total Gate Charge Qg 71 nC
2 Output Capacitance Coss 250pF To found Overall efficiency is by calculate ratio between
3 Rise Time trise 35ns output power and output power subtracted by total power
4 Fall Time tf all 35ns
5 Gate Threshold Voltage VGS 4V
losses Ploss by the system.
6 Drain Voltage of MOSFET VF ET 15V
Pout
η= (35)
Pin + Ploss
For MOSFET Conduction Power loss 10
η= = 0.846 ≈ 85%
PSCLoss = VQL Imax ) = (0.092)(2.089) = 0.192W 10 + 1.8116
Using the same method above, we can plot converter
or by internal resistance,
efficiency from 10% load to maximum load.
2
PSCLoss = Imax rDS (on)) = (2.089)2 (0.044) = 0.192W
For MOSFET Switching Power loss due to gate charge, the
equation is
1
PSLgate = Qg .VGS .fs (29)
2
1
PSLgate = 71.10−9 .4.105 = 0.0142W
2
For MOSFET Switching Power loss due to Output Capacitance
(COSS), the equation is
1
PSLcoss = Coss.VF2ET .fs (30)
2
1
PSLcoss = 250.10−12 .152 .105 = 0.0028W Fig. 12. 0 − DTs interval waveform
2
For MOSFET Switching Power loss due to rise and fall times, by Converter have a very good efficiency when running low
the equation is voltage, but this is not close to real performance especially in
1 low voltage due to not considering inductor core stauration
PSLtrf = (trise + tf all ).Imax .VF ET .fs (31) and loss when ingniting magnetic core.
2
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