Error control coding
Error control coding
Notation
In digital communication message is usually represented by binary codes, which consists only of binary
symbols 0 and 1. In such a code, the encoding and decoding functions involve the binary arithmetic
operations of modulo-2 addition and multiplication. The ordinary plus sign (+) is used to denote modulo-
2 addition. The rules for modulo-2 addition and modulo-2 multiplication are as follows:
[C] = {c1 , c2 , . . . cn }
In a systematic linear block codes, the message bits of a codeword appears before the parity-check bits,
or vice versa. The remaining (n − k) parity-check bits in the codeword. By combining the message bits
and parity-check bits and expressed as a codeword which is as follows:
The remaining (n − k) parity-check bits ck+1 , ck+2 , . . . cn are generated from k message bits using a
predetermined rule
1 0 0 . . . 0 P11 P12 . . . P1,n−k
0 1 0 . . . 0 P21 P22 . . . P2,n−k
[c1 , c2 , . . . ck , ck+1 ck+2 . . . cn ] = [d1 , d2 , dk ] .. .. .. .
. . . ..
. . . ...
0 0 0 . . . 1 Pk1 Pk2 . . . Pk,n−k
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 1
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 1
0.1. Linear Block Codes
[C] = [D][G]
where [G] is called as generator matrix and is expressed as:
.
[G] = [Ik ..P ]k×n
d1 , d 2 ,...d k b1 , b2 ,...bn k
Message bits Parity-check bits
k bits n k bits
n bits
c1 , c2 ,........ ck ck 1ck 2 ......... cn
Let b0 , b1 , . . . bn−k−1 denote the (n − k) parity-check bits in the codeword. For the code to possess a
systematic structure, a codeword is divided into two parts, one of which is occupied by the message bits
and the other by the parity-check bits.
Clearly, we have the option of sending the message bits of a codeword before the parity-check bits, or
vice versa. The former option is illustrated in Figure 10.4, and its use is assumed in the following.
b0 , b1 ,...bn k 1 m0 , m1 ,...mk 1
Parity-check bits Message bits
or
m0 , m1 ,...mk 1 b0 , b1 ,...bn k 1
Message bits Parity-check bits
k bits n k bits
n bits
Figure 3: Structure of systematic codeword.
bi i = 0, 1, . . . n − k − 1
ci =
mi+k−n i=n−k,n−k+1,...n−1
this set of probabilities must satisfy the normalization property
m = [m0 , m1 , . . . mk−1 ]
b = [b0 , b1 , . . . bn−k−1 ]
c = [c0 , c1 , . . . cn−1 ]
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 2
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 2
0.1. Linear Block Codes
P00 P01 ... P0,n−k−1
P10 P11 ... P1,n−k−1
P = .. .. .. ..
. . . .
Pk−1,0 Pk−1,1 . . . Pk−1,n−k−1
where the element pij is 0 or 1.
The codeword c may be expressed as a partitioned row vector in terms of the vectors m and b as
follows:
..
c= b.m
or
.
c = m .. b
or
.
c = m Ik .. P
where
1 0 ··· 0
0 1 ··· 0
Ik = .. .. . . ..
. . . .
0 0 ··· 1
Define the k-by-n generator matrix
.
G = P .. Ik
or
.
G = Ik .. P
ci + cj = mi G + mj G
= (mi + mj )G
The modulo-2 sum of mi and mj represents a new message vector. Correspondingly, the modulo-2 sum of
ci and cj represents a new code vector.
The message bits and parity-check bits are expressed in another form which is a linear block code. Let
H denote an (n − k)-by-n matrix, defined as
.. T
H = In−k . P
or
.
H = P T .. In−k
where P T is an (n − k)-by-k matrix, representing the transpose of the coefficient matrix P , and In−k is
the (n − k)-by-(n − k) identity matrix.
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 3
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 3
0.1. Linear Block Codes
1 0 0 ... 0 P11 P12 . . . P1,n−k
. 0 1 0 ... 0 P21 P22 . . . P2,n−k
[G] = [Ik ..P ] .. .. .. .
. . . ..
. . . ...
0 0 0 ... 1 Pk1 Pk2 . . . Pk,n−k
..
H = PT . In−k
P11 P21 ... Pk1 1 0 0
... 0
P12 P22 ... Pk2 0 1 0
... 0
[H] = .. .. .. ..
. . ... . ... .
P1,n−k P2,n−k . . . Pk,n−k 0 0 0 ... 1
T
T
Ik
HG = P In−k
PT
= PT + PT
= 0
cH T = mGH T
= 0
The matrix H is called the parity-check matrix of the code and the above equation is mentioned as
parity-check equations.
s = rH T
The syndrome depends only on the error pattern and not on the transmitted codeword.
s = rH T
= (c + e)H T
= cH T + eH T
= eH T
dmin ≥ 2t + 1
2020 Jan 7 b. The parity check bits of a (7,4) Hamming code, are generated by
c 5 = d1 + d3 + d4
c 6 = d1 + d2 + d3
c 7 = d2 + d3 + d4
(iii) The (n,k) linear block code so obtained has a ’dual’ code. This dual code is a (n, n-k) code having
a generator matrix H and parity check matrix G. Determine the eight code vectors of the dual code
for the (7,4) Hamming code describe above.
(iv) Find the minimum distance of the dual code determined in part (c).
Solution:
n=7 and k=4
It is a 4 × 7 matrix in which 4 × 4 identity matrix
Message bits are d1 , d2 , d3 , d4 and code bits are arranged as c1 = d1 , c2 = d2 , c3 = d3 , c4 = d4 , c5 =
d1 + d3 + d4 c 6 = d1 + d2 + d3 , c 7 = d2 + d3 + d4 ,
[C] = [c1 , c2 , c3 , c4 , c5 , c6 , c7 ]
= [d1 , d2 , d3 , d4 , (d1 + d3 + d4 ), (d1 + d2 + d3 ), (d2 + d3 + d4 )]
1 0 0 0| 1 1 0
0 1 0 0| 0 1 1
= [d1 , d2 , d3 , d4 ]
0 0 1 0| 1 1 1
0 0 0 1| 1 0 1
= [D][G]
1 1 0
0 1 1
1 0 0 0 1 1 0 0 0 0
1 1 1
0 1 0 0 0 1 1 0 0 0
[G][H T ] =
0
1 0 1 =
0 1 0 1 1 1 0 0 0
1 0 0
0 0 0 1 1 0 1 0 0 0
0 1 0
0 0 1
′ ′ ′
The dual code is n, n − k = 7, 3 with message bits as d1 , d2 , d3
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 6
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 6
0.1. Linear Block Codes
1 0 1 1 1 0 0
′ ′ ′ ′ ′ ′
[c] = [d1 , d2 , d3 ][H] = [d1 , d2 , d3 ] 1 1 1 0 0 1 0
0 1 1 1 0 0 1
By observing the dual code vector the minimum distance minimum number of ones it is four Hence
dmin = Hmin = 4
Jan-2020-CBCS 8-a For a systematic (6,3) linear block code, the parity matrix P is given by
1 0 1
0 1 1
1 1 0
i) Find all possible code words. ii) Find error detecting and correcting capability.
(06 Marks)
Solution:
n=6 and k=3
There are 23 = 8 message vectors given by u=[000, 001, 010, 011, 100, 101, 110, 111]
The code vectors V are estimated using generator matrix G which is in the form of
[C] = [D][G]
where
[G] = [Ik |P ]
1 0 0| 1 0 1
= 0 1 0| 0 1 1
0 0 1| 1 1 0
[C] = [D][G]
= [d1 , d2 , d3 ][G]
1 0 0| 1 0 1
= [d1 , d2 , d3 ] 0 1 0| 0 1 1
0 0 1| 1 1 0
= [d1 , d2 , d3 , (d1 , +d3 ), (d2 + d3 ), (d1 + d2 )]
dmin = 2
(10 Marks)
Solution:
n=6 and k=3, n-k=6-3=3
There are 23 = 8 message vectors given by u=[000, 001, 010, 011, 100, 101, 110, 111]
The code vectors V are estimated using generator matrix G which is in the form of
[C] = [D][G]
where
[G] = [Ik |P ]
1 0 0| 1 1 1
= 0 1 0| 1 1 0
0 0 1| 1 0 1
[C] = [D][G]
= [d1 , d2 , d3 ][G]
1 0 0| 1 1 1
= [d1 , d2 , d3 ] 0 1 0| 1 1 0
0 0 1| 1 0 1
= [d1 , d2 , d3 , (d1 + d2 + d3 ), (d1 + d2 )(d1 + d3 )]
[G] = [Ik |P ]
1 0 0| 1 1 1
= 0 1 0| 1 1 0
0 0 1| 1 0 1
[H] = [P T |In−k ]
[H] = [P T |In−k ]
1 1 1| 1 0 0
= 1 1 0| 0 1 0
1 0 1| 0 0 1
d1
d2
Input
d1 d2 d3 d3
Message
Commutator
To Channel
+ + + (d1+d2+d3)
(d1+d2)
(d1+d3)
Jan-2019-CBCS 7-a For a (6,3) code find all possible code vectors, if the coefficient matrix P is given by
1 1 0
0 1 1
1 0 1
(08 Marks)
Solution:
n=6 and k=3
There are 23 = 8 message vectors given by u=[000, 001, 010, 011, 100, 101, 110, 111]
The code vectors V are estimated using generator matrix G which is in the form of
[C] = [D][G]
where
[G] = [Ik |P ]
1 0 0| 1 1 0
= 0 1 0| 0 1 1
0 0 1| 1 0 0
[C] = [D][G]
= [d1 , d2 , d3 ][G]
1 0 0| 1 1 0
= [d1 , d2 , d3 ] 0 1 0| 0 1 1
0 0 1| 1 0 1
= [d1 , d2 , d3 , (d1 + d3 ), (d1 + d2 )(d2 + d3 )]
d2
Input
d1 d2 d3 d3
Message
Commutator
To Channel
+ + + (d1+d3)
(d1+d2)
(d2+d3)
Figure 6: Encoder-LBC-2019-Jan
iii) Find the syndrome vector S
Parity check matrix H is expressed as
[H] = [P T |In−k ]
[H] = [P T |In−k ]
1 0 1| 1 0 0
= 1 1 0| 0 1 0
0 1 0| 0 0 1
S = RH T
P
HT = −
In−k
1 1 0
0 1 1
1 0 0
T
H = − − −
1 0 0
0 1 0
0 0 1
S = RH T
1 1 0
0 1 1
1 0 0
= [r1 r2 r3 r4 r5 r6 ]
1 0 0
0 1 0
0 0 1
= [s1 s2 s3 ]
= [(r1 + r3 + r4 ), (r1 + r2 + r5 ), (r2 + r6 )]
Received
r1 r2 r3 r4 r5 r6
Vector
+ + +
S0 S1 S2
(r1+r3+r4) (r2+r6)
(r1+r2+r5)
Figure 7: Syndrome-LBC-2019-Jan
Feb-2022-CBCS 7-a 2017 2010 scheme For a systematic (7,4) linear block code the parity matrix P is given
by
1 1 1
1 1 0
1 0 1
0 1 1
i) Find all possible code vectors.
ii) Draw the encoding circuit.
iii) A single error has occurred in the received vector R=[1011100]. Detect the error.
iii) Draw the syndrome calculation circuit.
(10 Marks)
Solution:
n = 7 and k = 4
The code vectors are estimated using generator matrix G which is in the form of
[C] = [D][G]
where
[G] = [Ik |P ]
1 0 0 0 | 1 1 1
0 1 0 0 | 1 1 0
=
0 0
1 0 | 1 0 1
0 0 0 1 | 0 1 1
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 12
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 12
0.1. Linear Block Codes
[C] = [D][G]
= [d1 , d2 , d3 , d4 ][G]
1 0 0 0 | 1 1 1
0 1 0 0 | 1 1 0
= [d1 , d2 , d3 , d4 ]
0 0 1 0 | 1 0 1
0 0 0 1 | 0 1 1
= [d1 , d2 , d3 , , d4 , (d1 + d2 + d3 ), (d1 + d2 + d4 )(d1 + d3 + d4 )]
c1
c2
c3
Input
d1 d2 d3 d4 c4
Message
Commutator
c5
To Channel
+ + + (d1+d2+d3)
(d1+d2+d4) c6
(d1+d3+d4)
c7
S = RH T
P
HT = −
In−k
1 1 1
1 1 0
1 0 1
T
0 1 1
H = − − −
1 0 0
0 1 0
0 0 1
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 13
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 13
0.1. Linear Block Codes
1 1 1
1 1 0
1 0 1
T
S = RH = [1 0 1 1 1 0 0]
0 1 1
1 0 0
0 1 0
0 0 1
[S] = [S1 , S2 , S3 ] = [1 0 1]
Syndrome bits are [1 0 1] which is presented in 3rd row of H T it indicates the error occurred in the 3rd
position of the vector counting from lest side of the received data. The received data is [1 0 1 1 1 0 0] in
which 3rd position bit is 1 which has to be changed as 0. The corrected vector is [1 0 0 1 1 0 0].
1 1 1
1 1 0
1 0 1
T
S = RH = [r1 , r2 , r3 , r4 , r5 , r6 , r7 ]
0 1 1
1 0 0
0 1 0
0 0 1
Received
r7 r6 r5 r4 r3 r2 r1
Vector
+ + +
S3 S2 S1
(r1+r3+r4+r7) (r1+r2+r3+r5)
(r1+r2+r4+r6)
A (6,3) linear block code with a parity matrix is as shown. The received code vector R = [1 1 0 0 1 0] is
given. Detect & correct the single error that has occurred due to noise
1 0 1
0 1 1
1 1 0
Solution:
H = [P T |In−k ]
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 14
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 14
0.1. Linear Block Codes
1 0 1 | 1 0 0
H= 0 1 1 | 0 1 0
1 1 0 | 0 0 1
S = RH T
P
HT = −
In−k
1 0 1
0 1 1
1 1 0
T
H = − − −
1 0 0
0 1 0
0 0 1
1 0 1
0 1 1
1 0 0
T
S = RH = [1 1 0 0 1 0]
− − −
1 0 0
0 1 0
0 0 1
S1 = 1 + 0 + 0 + 0 + 0 + 0 = 1
S2 = 0 + 0 + 0 + 0 + 0 + 0 = 0
S3 = 1 + 1 + 0 + 0 + 0 + 0 = 0
S = [S1 , S2 , S3 ] = [1 0 0] 6= 0
Compare this syndrome bits with the rows of H T . The syndrome bit S = [1 0 0] which is present in the
4th row of H T . Hence 4th bit of the received vector counting from left is having an error. The error bit
has been identified and has to be corrected. If it is 0 it has to be changed as 1 or if it is 1 it has to be
changed as 0.
The received code vector is R = [1 1 0 0 1 0] it has to changed as R = [1 1 0 1 1 0]
Jan-2019-CBCS 7-a The parity check bits of a (8,4) linear block code is given by
C 5 = d1 + d2 + d4
C 6 = d1 + d2 + d3
C 7 = d1 + d3 + d4
C 8 = d2 + d3 + d4
(08 Marks)
Solution:
n = 8 and k = 4
1 0 0 0 | 1 1 1 0
0 1 0 0 | 1 1 0 1
G=
0
0 1 0 | 0 1 1 1
0 0 0 1 | 1 0 1 1
H = [P T |In−k ]
1 1 0 1 | 1 0 0 0
1 1 1 0 | 0 1 0 0
H=
1
0 1 1 | 0 0 1 0
0 1 1 1 | 0 0 0 1
The minimum weight other than zero code vector is minimum weight. In this code vector minimum
weight is 4.
S 1 = r 1 + r2 + r 3 + r 5
S 2 = r 1 + r2 + r 4 + r 6
S 3 = r 1 + r3 + r 4 + r 7
(08 Marks)
Solution:
1 0 1
1 1 0
1 1 1
T
0 1 1
H =
− − −
1 0 0
0 1 0
0 0 1
1 1 1 0 | 1 0 0
H= 0 1 1 1 | 0 1 0
1 0 1 1 | 0 0 1
H = [P T | In−k ]
G = [Ik | P ]
1 0 0 0 | 1 0 1
0 1 0 0 | 1 1 0
G=
0
0 1 0 | 1 1 1
0 0 0 1 | 0 1 1
n = 7 and k = 4
0 0 0 1 | 0 1 1
= [d1 , d2 , d3 , , d4 , (d1 + d2 + d3 ), (d2 + d3 + d4 )(d1 + d3 + d4 )]
c1
c2
c3
Input
d1 d2 d3 d4 c4
Message
Commutator
c5
To Channel
+ + + (d1+d2+d3)
(d2+d3+d4) c6
(d1+d3+d4)
c7
1 0 1
1 1 0
1 1 1
T
0 1 1
S = RH = [r1 , r2 , r3 , r4 , r5 , r6 , r7 ]
− − −
1 0 0
0 1 0
0 0 1
1 0 1
1 1 0
1 1 1
T
0 1 1
S = RH = [1, 0, 1, 1, 0, 1, 1]
− − −
1 0 0
0 1 0
0 0 1
Jan-2020-CBCS 7-c Design a syndrome calculating circuit for a (7, 4) cyclic code g(X) = 1 + X + X 3 and
also calculate the syndrome of the received vector R=1110101
Solution:
Gate
g0= 1 g1 = 1 g2= 0
Input
Gate + S0 + S1 S2
Syndrome
Output
2019-DEC-CBCS 8-b A (7,4) cyclic code has the generator g(X) = 1 + X + X 3 . Find the code vector
both in systematic and non systematic form for the message bits (1101)
Solution:
Gate
g0=1 g1=1
g2=0
Code
word
P0 + P1 P2 +
When message bit is 1 the g0 and g1 are 1 After four shift, the contents of the register are (0 0 0) and
the codeword is (0 0 0 1 0 1 1)
2019-DEC-CBCS 8-b Draw the encoder circuit of a cycling code using (n-k) bit shift registers and explain
it.
Gate
g0 g1 gn-k-1
g2
Code
+ + word
R0 + R1 R2 +
R Registers
Parity Check digits
+ Modulo 2 adders
2019-DEC-CBCS 8-a Explain the syndrome calculation and error detection with help of neat diagram for
cyclic codes.
2019-DEC-CBCS 8-b Consider a (15,7) binary cyclic code with g(x) = 1 + X 4 + X 6 + X 7 + X 8
Solution:
Gate
g0=1 g4=1 g6=1 g7=1
R0 R1 R2 R3 + R4 R5 + R6 + R7 +
Shifts Input D R0 R1 R2 R3 R4 R5 R6 R7
0 0 0 0 0 0 0 0 0
1 1 1 0 0 0 1 0 1 1
2 1 0 1 0 0 0 1 0 1
3 1 0 0 1 0 0 0 1 0
4 0 0 0 0 1 0 0 0 1
5 0 1 0 0 0 1 0 1 1
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 20
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 20
0.1. Linear Block Codes
The code word is, the content of the register in the last shift is 10001011, hence code word is 10001011-
00111
iii) Draw the syndrome calculating circuit.
Gate
g0=1 g4=1 g6=1 g7=1
+ S0 S1 S2 S3 + S4 S5 + S6 + S7
Syndrome
Figure 15: Syndrome calculating circuit.
1. Linearity Property: The sum of any two codewords in the code is also a codeword.
2. Cyclic Property: Any cyclic shift of a codeword in the code is also a codeword.
c0 , c1 , c2 , . . . cn−2 , cn−1
cn−1 , c0 , c1 , . . . cn−3 , cn−2
cn−2 , cn−1 c0 , . . . cn−4 , cn−3
c0 , c1 , c2 , . . . cn−2 , cn−1
Code Polynomial
Let u = (1 0 1 0) be the message vector, then the corresponding message polynomial is u(X) = 1 + X 2 .
Let the generator polynomial is g(X) = 1 + X + X 3 .
Let c0 , c1 , , c2 . . . cn−1 , be the code C. The code polynomial of C is:
where the power of X corresponds to the bit position, and the coefficients are 0s and 1s
Multiplying u(X) by g(X) results in the following code polynomial :
x3 + x
x3 + x + 1)x6 + x3
6
x +x +x 4 3
.........................................................
x4
x4 + x2 + x
.........................................................
x2 + x
x + x2 011
• If the n-tuples corresponding to these k code polynomials are used as the rows of an k x n matrix,
then the generator matrix G is:
g0 g1 g2 . . . . gn−k 0 0 0 . . 0
0 g0 g1 g2 . . . . gn−k 0 0 . . 0
G = 0 0 g0 g1 g2 . . . . gn−k 0 . . 0
..
.
0 0 . . . 0 g0 g1 g2 . . . . gn−k
Note: g0 = gn−k = 1
1 1 0 1 0 0 0
0 1 1 0 1 0 0
G′ =
0
0 1 1 0 1 0
0 0 0 1 1 0 1
The generator matrix G′ constructed is not in systematic form. This can be changed into We into a
systematic form by adding the first row to the third row, and adding the sum of the first two rows
to the fourth row.
1 1 0 1 0 0 0
0 1 1 0 1 0 0
G= 1 1 1 0 0 1 0
1 0 1 0 0 0 1
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 23
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 23
0.2. Cyclic Codes
• All these three steps can be accomplished with a division circuit which is a linear (n-k)-stage shift
register with feedback connections based on the generator polynomial
Gate
Enable
g0=1 g1 g2 gn-k-1
R0 + R1 + R2 + Rn-k-1 +
Flip-flop
Parity
Modulo-2
adder
check digits
Message X n k u ( X ) To channel
• With the gate turned on, the k information digits u0 , u1 , . . . , uk−1 are shifted into the circuit and
simultaneously into the communication channel
• Shifting the message u(X) into the circuit from the front end is equivalent to premultiplying u(X)
by X n−k
• As soon as the complete message has entered the circuit, the n - k digits in the register form the
remainder and thus they are the parity-check digits.
Step 2
• Shift the parity-check digits out and send them into the channel
• These n-k parity-check digits b0 , b1 , . . . , bn−k−1 , together with the k information digits, form a
complete code vector
Example
• As the message digits are shifted into the register, the contents in the register are:
g(X) = 1 + X + X 3
= g0 + g1 X + g2 X 2 + g3 X 3
Enable
Gate
Code
word
R0 + R1 R2 +
g( X ) 1 X X 3
Message 1011
Parity Check
digits
Figure 17: Encoder for the (7,4) cyclic code generated by g(X) = 1 + X + X 3
1011 1 + X2 + X3 X 3 (1 + X 2 + X 3 ) = X 3 + X 5 + X 6
X3 + X2 + X + 1
X3 + X + 1)X 6 + X 5 + X 3
X6 + X4 + X3
.........................................................
X5 + X4
X5 + X3 + X2
.........................................................
X4 + X3 + X2
X4 + X2 + X
.........................................................
X3 + X
X3 + X + 1
.........................................................
1
100
After four shift, the contents of the register are (1 0 0) and the codeword is (1 0 0 1 0 1 1)
Register contents
Shifts Input
R0 R1 R2
Initial state 0 0 0
1 1 1 1 0
2 1 1 0 1
3 0 1 0 0
4 1 1 0 0
• In the decoding of a linear code, the first step is to compute the syndrome s = r.H T , where H is the
parity check matrix
• If the syndrome is zero, r is a code vector and decoder accepts r as the transmitted code vector
• If the syndrome 6= 0 r is not a code vector and the presence of errors has been detected
• s(X) is identical to zero if and only if the received polynomial r(X) is a code polynomial.
• The syndrome computation can be accomplished with a division circuit as shown in Figure 18
Gate
Enable
g0=1 g1 g2 g n k 1
r(x)
+ S0 + S1 + + Sn-k-1
Received Flip-flop Syndrome
vector Modulo-2
adder
Example
• A syndrome circuit for the (7, 4) cyclic code g(X) = 1 + X + X 3 is shown in Fig. 5.6
• As the received vector is shifted into the circuit, the contents in the register are given in Table 5.3
• At the end of the seventh shift, the register contains the syndrome s = (1 0 1)
• If the register is shifted once more with the input gate disabled, the new contents will be s(1) (X) =
(1 0 0), which is the syndrome of r(1) (X) = (0 0 0 1 0 1 1), a cyclic shift of r
1 1 0 1 0 0 0
0 1 1 0 1 0 0
G=
1
1 1 0 0 1 0
1 0 1 0 0 0 1
1 0 0 1 0 1 1
H= 0 1 0 1 1 1 0
0 0 1 0 1 1 1
1 0 0
0 1 0
0 0 1
T
1
S = r.H = [0 0 1 0 1 1 0] 1 0
= [1 0 1]
0 1 1
1 1 1
1 0 1
Gate
g0=1 g1=1
Received
bits
+ S0 + S1 S2
Syndrome
3
Modulo-2 Flip-flop output
g( X ) 1 X X adder
Figure 19: Syndrome calculator for the (7,4) cyclic code generated by g(X) = 1 + X + X 3
Register contents
Shifts Input
S0 S1 S2
Initial state 0 0 0
1 0 0 0 0
2 1 1 0 0
3 1 1 1 0
4 0 0 1 1
5 1 0 1 1
6 0 1 1 1
7 0 1 0 1
2022 FEB (18EC54) Jan 7 b. Design an encoder for a (7, 4) binary cyclic code generated by g(X) =
1 + X + X 3 and verify its operation using the message vectors (1001) and (1011)
Solution:
The encoder diagram as shown in Figure 20.
Enable
Gate
g0=1 g1=1
R0 + R1 R2 + Code
word
Message Xn-k u(X)
Parity Check
digits
Figure 20: Syndrome calculator for the (7,4) cyclic code generated by g(X) = 1 + X + X 3
2020 FEB (2017 scheme) Jan 7 c. Design a syndrome calculating circuit for a (7, 4) cyclic code with
g(X) = 1 + X + X 3 and also calculate the syndrome of the received vectors (1110101).
Solution:
The encoder diagram as shown in Figure 20.
Gate
Enable
Figure 21: Syndrome calculator for the (7,4) cyclic code generated by g(X) = 1 + X + X 3
g(X) = 1 + X + X 3
= g0 + g1 X + g2 X 2 + g3 X 3
Register contents
Shifts Input
S0 S1 S2
Initial state 0 0 0
1 1 1 0 0
2 0 0 1 0
3 1 1 0 1
4 0 1 0 0
5 1 1 1 0
6 1 1 1 1
7 1 0 0 1
(a) Draw the feedback register encoding circuit for this cyclic code. Find the code vector in systematic
form for the message D(X) = X 2 + X 3 + X 4 .
(b) Illustrate the encoding procedure with the message vector 0 1 1 0 1 0 0 1 0 1 1 by listing the states
of the register with each input.
Solution:
The encoder diagram as shown in Figure 22.
Gate
Enable
Figure 22: Syndrome calculator for the (7,4) cyclic code generated by g(X) = 1 + X + X 4
The content of the shift register is 1010 hence the message vector is 1010 0 1 1 0 1 0 0 1 0 1 1
X n−k D(X) = X 4 (X + X 2 + X 4 + X 7 + X 9 + X 10 ) = X 14 + X 13 + X 11 + X 8 + X 6 + X 5
X 4 + X + 1)X 14 + X 13 + X 11 + X 8 + X 6 + X 5 (X 10 + X 9 + X 5 + X 4 + X + 1
- X 14 + X 11 + X 10
- ———————————–
- X 13 + X 10 + X 8 + X 6 + X 5
- X 13 + X 10 + X 9
- ———————————–
- X9 + X8 + X6 + X5
- X9 + X6 + X5
- ———————————–
- X8
- X8 + X5 + X4
- ———————————–
- X5 + X4
- X5 + X2 + X
- ———————————–
- X4 + X2 + X
- X5 + X + 1
- ———————————–
- X2 + 1
- R(X) = 1 + X 2
R(X) = 1 + X 2 + X 5 + X 6 + X 8 + X 11 + X 13 + X 14
= [101001101001011]
(ii) Illustratge the encoder procedure with the message vector 1 1 0 0 1 1 0 1 0 1 1 by listing the states
of the register (the right most bit is the earliest bit ).
(iii) Verify the validity of the code vector so formed by using division method.
Solution:
i) The encoder circuit is.
The generator polynomial is g(X) = 1 + X + X 4 . The coefficients of g are:
g(X) = 1 + X + X 4
= g0 + g1 X + g2 X 2 + g3 X 3 + g4 X 4
Gate
Enable
g0=1 g1=1 g2=0 g3=0
R0 + R1 R2 R3 +
Flip-flop
Modulo-2
adder g(X ) 1 X X 4
Message 11001101011 To channel
Register contents
Shifts Input
R0 R 1 R2 R3
Initial state 0 0 0 0
1 1 1 1 0 0
2 1 1 0 1 0
3 0 0 1 0 1
4 1 0 0 1 0
5 0 0 0 0 1
6 1 0 0 0 0
7 1 1 1 0 0
8 0 0 1 1 0
9 0 0 0 1 1
10 1 0 0 0 1
11 1 0 0 0 0
(ii) Find the code polynomial for the message D(X) = 1 + X 3 + X 4 by listing the states of the register
with each binary message input.
(ii) Verify the validity of the code vector so formed by using division method.
Solution:
i) The encoder circuit is.
The generator polynomial is g(X) = 1 + X + X 2 + X 4 + X 6 + X 8 + X 10 . The coefficients of g are:
g0 = 1, g1 = 1, g2 = 1, g3 = 0, g4 = 1, g5 = 1, g6 = 0, g7 = 0, g8 = 1, g9 = 0
The syndrome calculation circuit is as shown in Figure 25.
Enable
Gate
g0=1 g1=1 g2=1 g4=1 g5=1 g8=1
R0 + R1 + R2 R3 + R4 + R5 R6 R7 + R8 R9 +
Flip-flop
Modulo-2
adder g ( X ) 1 X X 2 X 4 X 5 X 8 X 10
D( X ) 1 X 3 X 4
Message 10011 To
channel
Register contents
Shifts Input
R0 R1 R2 R3 R 4 R5 R6 R7 R8 R9
Initial state 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 1 1 0 0 1 0
2 1 1 0 0 1 1 0 1 0 1 1
3 0 1 0 1 0 0 0 0 1 1 1
4 0 1 0 1 1 1 1 0 0 0 1
5 1 0 1 0 1 1 1 1 0 0 0
X n−k D(X) = X 10 (1 + X 3 + X 4 ) = X 14 + X 13 + X 10
X 10 + X 8 + X 5 + X 4 + X 2 + X + 1)X 14 X 13 + X 10 + (X 4 + X 3 + X 2 + X
- X 14 + X 12 + X 9 + X 8 + X 6 + X 5 + X 4
- ———————————————
- X 13 + X 12 + X 10 + X 9 + X 8 + X 6 + X 5 + X 4
- X 13 + X 11 + X 8 + X 7 + X 5 + X 4 + X 3
- ———————————————
- X 12 + X 11 + X 10 + X 9 + X 7 + X 6 + X 5 + X 3
- X 12 + X 10 + X 7 + X 6 + X 4 + X 3 + X 2
- ———————————————
- X 11 + X 9 + X 4 + X 2
- X 11 + X 9 + X 6 + X 5 + X 3 + X 2 + X
- ———————————————
- X6 + X5 + X4 + X3 + X
- R(X) = X + X + X 4 + X 5 + X 6
3
= X + X 3 + X 4 + X 5 + X 6 + X 10 (1 + X 3 + X 4 )
= X + X 3 + X 4 + X 5 + X 6 + X 10 + X 13 + X 14
= [010111100010011]
010111100010011
2023 Jan 18EC54 8a 2001 FEB (2017 scheme) Jan 7 a.The generator polynomial of a (15,7) cyclic code is
g(X) = 1 + X 4 + X 6 + X 7 + X 8
(i) Draw the encoder circuit.
(ii) Obtain the codeword for the input (00111)
(iii) Find the code vector for the message D(X) = X 2 + X 3 + X 4 using encoder circuit.
(iv) Draw the syndrome calculation circuit.
(v) Find the syndrome of the received polynomial Z(X) = 1 + X + X 3 + X 6 + X 8 + X 9 + X 11 + X 14
(vi) Assume that the first and last bits of the code vector V (X) for D(X) = X 2 + X 3 + X 4 suffer
transmission errors. Find the syndrome of V (X).
Solution:
i) The encoder circuit is.
The generator polynomial is g(X) = 1 + X 4 + X 6 + X 7 + X 8 . The coefficients of g are:
g0 = 1, g1 = 0, g2 = 0, g3 = 0, g4 = 1, g5 = 0, g6 = 1, g7 = 1, g8 = 1
The encoder circuit is for the (15,7) cyclic code as shown in Figure 25.
Gate
Enable
g0=1 g4=1 g6=1 g7=1
R0 R1 R2 R3 + R4 R5 + R6 + R7 +
Flip-flop
Modulo-2
g(X ) 1 X 4 X 6 X 7 X 8
adder
Message 00111
To channel
Register contents
Shifts Input
R0 R1 R2 R 3 R4 R5 R6 R7
Initial state 0 0 0 0 0 0 0 0
1 1 1 0 0 0 1 0 1 1
2 1 0 1 0 0 0 1 0 1
3 1 0 0 1 0 0 0 1 0
4 0 0 0 0 1 0 0 0 1
5 0 1 0 0 0 0 0 1 1
X n−k D(X) = X 8 (X 2 + X 3 + X 4 ) = X 10 + X 11 + X 12
X 8 + X 7 + X 6 + X 4 + 1)X 12 + X 11 + X 10 (+X 4
- X 12 + X 11 + X 10 + X 8 + X 4
- ———————————–
- X8 + X4
- X8 + X7 + X6 + X4 + 1
- ———————————–
- R(X) = 1 + X 6 + X 7
[V ] = [R D] = [10000011 0011100]
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 35
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 35
0.2. Cyclic Codes
Gate
Enable
g0=1 g4=1 g6=1 g7=1
S0 S1 S2 S3 + S4 S5 + S6 + S7
Flip-flop Syndrome
g(X ) 1 X 4 X 6 X 7 X 8
ZX=110100101101001
Figure 26: Syndrome calculator for the (7,4) cyclic code generated by g(X) = 1 + X 4 + X 6 + X 7 + X 8
Register contents
Shifts Input
S0 S1 S 2 S3 S4 S 5 S6 S7
Initial state 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0
2 0 0 1 0 0 0 0 0 0
3 0 0 0 1 0 0 0 0 0
4 1 1 0 0 1 0 0 0 0
5 0 0 1 0 0 0 1 0 0
6 1 1 0 1 0 0 1 0 0
7 1 1 1 0 1 0 0 1 0
8 0 0 1 1 0 1 0 0 1
9 1 0 0 1 1 1 1 1 1
10 0 1 0 0 1 0 1 0 0
11 0 0 1 0 0 1 0 1 0
12 1 1 0 1 0 0 1 0 1
13 0 1 1 0 1 1 0 0 1
14 1 0 1 1 0 0 1 1 1
15 1 0 0 1 1 1 0 0 0
vi) When the first and last bits of the code vector V (X) for D(X) = X 2 + X 3 + X 4 suffer
transmission errors then the received code vector is.
The code vector is
[V ] = [100000110011100]
When the first and last bits of the code vector suffer transmission errors then
[Z] = [000000110011101]
Z(X) = X 6 + X 7 + X 10 + X 11 + X 12 + X 14
(ii) Find the code word in systematic form for the message (0 1 0 1 0 1 0) clearly explaining all the steps.
In particular list the state of the registers in each step of code computation.
Solution:
i) The encoder circuit is.
The generator polynomial is g(X) = 1 + X 4 + X 6 + X 7 + X 8 . The coefficients of g are:
g0 = 1, g1 = 0, g2 = 0, g3 = 0, g4 = 1, g5 = 0, g6 = 1, g7 = 1, g8 = 1
The encoder circuit is for the (15,7) cyclic code as shown in Figure 25.
From the above table the last row of the table is 0 1 0 1 1 0 0 0 and the vector is
V=[0 1 0 1 1 0 0 0 0 1 0 1 0 1 0]
(ii) Verify your answer by direct hand calculation.
Given data D is [ 0 1 0 1 0 1 0 ] D(X) = X + X 3 + X 5
Dr. J. Divya Lakshmi, Professor & HOD, Dept. of ECE, SKIT 37
Dr. Manjunatha P Prof., Dept of ECE, JNN College of Engg Shimoga [email protected] 37
0.2. Cyclic Codes
Gate
Enable
g0=1 g4=1 g6=1 g7=1
R0 R1 R2 R3 + R4 R5 + R6 + R7 +
Flip-flop
Modulo-2
g(X ) 1 X 4 X 6 X 7 X 8
adder
Message 010010
To channel
Register contents
Shifts Input
R0 R1 R2 R3 R4 R5 R6 R7
Initial state 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
2 1 1 0 0 0 1 0 1 1
3 0 1 1 0 0 1 1 1 0
4 1 1 1 1 0 1 1 0 0
5 0 0 1 1 1 0 1 1 0
6 1 1 0 1 1 0 0 0 0
7 0 0 1 0 1 1 0 0 0
g(X) = 1 + X 4 + X 6 + X 7 + X 8
X n−k D(X) = X 8 (X + X 3 + X 5 ) = X 13 + X 11 + X 9
X 8 + X 7 + X 6 + X 4 + 1)X 13 + X 11 + X 9 (X 5 + X 4 + X 3 + X
- X 13 + X 12 + X 11 + X 9 + X 5
- ———————————–
- X 12 + X 5
- X 12 + X 11 + X 10 + X 8 + X 4
- ———————————–
- X 11 + X 10 + X 8 + X 5 + X 4
- X 11 + X 10 + X 9 + X 7 + X 3
- ———————————–
- X9 + X8 + X7 + X5 + X4 + X3
- X9 + X8 + X7 + X5 + X
- ———————————–
- X4 + X3 + X
[V ] = [R D]
= [01011000 0101010]