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DWC Pcie CTL SW Databook

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1K views1,093 pages

DWC Pcie CTL SW Databook

Uploaded by

54wangzhigang
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DesignWare Cores

PCI Express Controller


Databook

DWC PCIe Switch -


Product Codes

Version 5.40a
March 2019
PCI Express SW Controller Databook

Copyright Notice and Proprietary Information


© 2019 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use,
reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals
of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and
to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
Trademarks
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https://www.synopsys.com/company/legal/trademarks-brands.html
All other product or company names may be trademarks of their respective owners.
Free and Open-Source Software Licensing Notices
If applicable, Free and Open-Source Software (FOSS) licensing notices are available in the product installation.
Third-Party Links
Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not
responsible for such websites and their practices, including privacy practices, availability, and content.

Synopsys, Inc.
www.synopsys.com

Synopsys, Inc.
2 SolvNet Version 5.40a
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PCI Express SW Controller Databook Contents

Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1 General Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.3 Features and Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4 Frequency, Speed, and Width Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.6 Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Chapter 2
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.2 RAM Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.3 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.4 Reset Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.5 Receive Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Chapter 3
Controller Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.2 Link Establishment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.3 Transmit TLP Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.4 Receive TLP Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.5 Register Module, LBC, and DBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.6 Reliability, Availability, and Serviceability (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.7 Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
3.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
3.9 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
3.10 Internal Address Translation Unit (iATU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
3.11 Gen2/3/4/5 Speed Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
3.12 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
3.13 Completion Timeout Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
3.14 Crosslink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
3.15 TLP Processing Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

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3.16 Atomic Operations (AtomicOps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257


3.17 TLP Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
3.18 Separate Refclk Independent SSC (SRIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
3.19 Readiness Notifications (RN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
3.20 Precision Time Measurement (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
3.21 Access Control Services (ACS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
3.22 Completion Queue Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Chapter 4
Signal Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
4.1 Transmit Interfaces (XALI0/1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
4.2 CCIX Transmit Interface (XALI_CCIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
4.3 Receive Bypass Interface (RBYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
4.4 Receive Request Interface (TRGT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
4.5 CCIX Receive Request Interface (TRGT1_CCIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
4.6 Data Bus Interface (DBI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
4.7 External Local Bus Interface (ELBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
4.8 Message Signaled Interrupt (MSI) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
4.9 MSI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
4.10 Vendor Message Interface (VMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
4.11 System Information Interface (SII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
4.12 PIPE Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
4.13 PHY Register Bus Interface (PRBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Chapter 5
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
5.1 Distributed Translation Interface AXI4-Stream Master Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
5.2 Distributed Translation Interface AXI4-Stream Slave Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
5.3 Distributed Translation Interface Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
5.4 Distributed Translation Interface Invalidate Request Timeout Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
5.5 CXS Rx Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
5.6 CXS Tx Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
5.7 XALI0 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
5.8 XALI1 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
5.9 XALI2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
5.10 XALI_CCIX Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
5.11 ADM adaptor Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
5.12 Bypass Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
5.13 RTRGT1 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5.14 TRGT1_CCIX Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
5.15 Clock and Reset (APM) Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
5.16 Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
5.17 DBI Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
5.18 ELBI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
5.19 CXS Rx FIFO RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
5.20 CXS Tx FIFO RAM Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
5.21 Receive Data Queue RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
5.22 Receive Formation Queue RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
5.23 Receive Header Queue RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

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5.24 Transmit Retry Buffer RAM Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429


5.25 Transmit Retry SOT Buffer RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
5.26 MSI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
5.27 MSI-X Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
5.28 VMI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
5.29 Power Budgeting Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
5.30 SII: AER Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
5.31 SII: CCIX Configuration/Control/Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
5.32 SII: Configuration Information Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
5.33 SII: Debug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
5.34 SII: Diagnostic Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
5.35 SII: Electromechanical Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
5.36 SII: FRS/DRS Messaging Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
5.37 SII: General Core Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
5.38 SII: General Messaging Reception Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
5.39 SII: Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
5.40 SII: Link Reset/Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
5.41 SII: LTR Message Generation Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
5.42 SII: LTR Message Reception Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
5.43 SII: Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
5.44 SII: OBFF Message Generation Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
5.45 SII: OBFF Message Reception Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
5.46 SII: PM, Unlock, and Error Messages Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
5.47 SII: Power Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
5.48 SII: Precision Time Management Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
5.49 SII: RAS Data Protection Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
5.50 SII: Receive Control/CPL Timeout Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
5.51 SII: Transmit Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
5.52 Common PIPE Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
5.53 Gen2/3-Only PIPE Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
5.54 Gen3-Only Equalization PIPE Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
5.55 Gen3-Only Equalization V7 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
5.56 Gen3-Only PIPE Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
5.57 Gen4-Only Margining Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
5.58 Gen4-Only PIPE Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
5.59 SerDes PIPE Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
5.60 Crosslink Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
5.61 Peer-to-Peer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
5.62 RAS D.E.S. Event Counter RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
5.63 RAS D.E.S. Event Counters Debug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
5.64 RAS D.E.S. Silicon Debug Internal Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
5.65 RAS D.E.S. Time-Based Analysis Debug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
5.66 RAS D.E.S. Time-Based Analysis RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
5.67 Configuration Intercept Interface (CII) Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
5.68 EXTSRIOV: PF Registers Value for VF Function Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
5.69 PHY Register Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
5.70 SII: ATS Capability Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
5.71 SII: BDF Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
5.72 SII: DPC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

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5.73 SII: TLP Bypass Internal Error Reporting Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

Chapter 6
Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
6.1 Main Features Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
6.2 Basic Features Config / PCIe Basic Features Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
6.3 Basic Features Config / Common Basic Features Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
6.4 DMA Configuration Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
6.5 Basic AXI Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
6.6 Basic AXI Config / PCIe TAGs and AXI IDs Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
6.7 Basic AXI Config / PCIe and AHB TAGs Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
6.8 Device-Wide Optional Non-PCIe Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
6.9 Advanced AXI Config / Advanced AHB Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
6.10 Advanced AXI Config / Advanced AXI Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
6.11 Device-Wide PCIe Features and Capabilities Config / MSI/MSI-X Capability Parameters. . . . . . . . . 703
6.12 Device-Wide PCIe Features and Capabilities Config / PCIe Capability Parameters . . . . . . . . . . . . . . . 705
6.13 Device-Wide PCIe Features and Capabilities Config / PF Extended Capabilities Parameters. . . . . . . 714
6.14 Device-Wide PCIe Features and Capabilities Config / VC Capability Parameters . . . . . . . . . . . . . . . . 718
6.15 Device-Wide PCIe Features and Capabilities Config / Slot ID Capability Parameters . . . . . . . . . . . . . 719
6.16 Device-Wide PCIe Features and Capabilities Config / AtomicOp Support Options Parameters . . . . 720
6.17 Device-Wide PCIe Features and Capabilities Config / Readiness Support Options Parameters. . . . . 722
6.18 Device-Wide PCIe Features and Capabilities Config / Lightweight Notification Support Options Pa-
rameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
6.19 Device-Wide PCIe Features and Capabilities Config / Other Optional PCIe Features Parameters. . . 726
6.20 Device-Wide PCIe Features and Capabilities Config / SR-IOV Related Features Parameters . . . . . . . 728
6.21 Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities Parameters . . . . . . 730
6.22 Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability Parameters. . .
738
6.23 Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability / L1 Substates
Capability Register Defaults Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
6.24 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support Parameters . . . . . . . . . . . . 741
6.25 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support / PASID Capability Register
Defaults Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
6.26 Device-Wide PCIe Features and Capabilities Config / Precision Time Management Support Options Pa-
rameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
6.27 Device-Wide PCIe Features and Capabilities Config / Secondary PCIe Extended Capability Parameters
744
6.28 Device-Wide PCIe Features and Capabilities Config / CCIX Transport DVSEC Parameters . . . . . . . 746
6.29 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Express Capability
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
6.30 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / MSI-X Register Configu-
ration (PF0) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
6.31 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Advanced Error Register
Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
6.32 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / TLP Processing Hints
Register Configuration (PF0) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
6.33 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ATS Register Configura-
tion (PF0) Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
6.34 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ACS Register Configura-

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tion (PF0) Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755


6.35 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Lightweight Notification
Configuration (PF0) Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
6.36 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Readiness Configuration
(PF0) Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
6.37 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Power Management Reg-
ister Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
6.38 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Register Configura-
tion Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
6.39 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Register Configura-
tion / PF0 PCI Register Defaults Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
6.40 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / BAR Setup For Physical
Function 0 (PF0) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
6.41 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / SR-IOV Register Config-
uration PF0 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
6.42 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Virtual Function BARs
for PF0 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
6.43 Advanced RAM Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
6.44 Advanced PHY Config / General Options Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
6.45 Advanced PHY Config / PHY Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
6.46 Advanced PHY Config / Gen3 PHY Equalization Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 816
6.47 Advanced PHY Config / Gen4 PHY Equalization Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 821
6.48 Advanced PHY Config / Gen5 PHY Equalization Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 825
6.49 Advanced PHY Config / PHY Lane Margining Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
6.50 Advanced PHY Config / PHY Message Bus Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
6.51 Advanced Transmit Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
6.52 Advanced Pipeline Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
6.53 Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters. . . . . . . . . . . . . . . . . . . . . . . . 847
6.54 Advanced Buffer Config / Segmented-Buffer Options Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
6.55 Advanced Buffer Config / Ordering Rules Configuration (Segmented-Buffer) Parameters . . . . . . . . 851
6.56 Advanced Buffer Config / Receive Serialization Queue Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
6.57 Advanced RX Queue Credit and Size Config / Cplq_Mng Calculator Parameters . . . . . . . . . . . . . . . . 853
6.58 Advanced RX Queue Credit and Size Config / VC 0 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
6.59 Advanced RX Queue Credit and Size Config / VC 1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
6.60 Advanced RAS Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
6.61 Memory Map Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
6.62 Automotive Features Selection Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
6.63 CXS Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

Chapter 7
Cache Coherent Interconnect for Accelerators (CCIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
7.1 CCIX PCIe Controller Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
7.2 CCIX PCIe Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884

Chapter 8
Embedded EndPoint (Switch DSP Integrated EndPoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
8.2 Advantages of Embedded EndPoint Solution Over Pipe Connected EndPoint . . . . . . . . . . . . . . . . . . . . 895
8.3 Embedded EndPoint Delivery Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896

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Contents PCI Express SW Controller Databook

Appendix A
Advanced Information: Gen3/4/5 Equalization Details and Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
A.1 Equalization Overview and Synopsys-Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
A.2 Detailed Equalization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
A.3 Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915

Appendix B
Advanced Information: Lane Reversal and Broken Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919

Appendix C
Advanced Information: Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
C.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
C.2 Local Digital Loopback (PIPE/RMMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
C.3 Local Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
C.4 Remote Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936

Appendix D
Advanced Information: Lane Deskew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
D.1 Conventional PCIe Deskew Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939

Appendix E
Advanced Information: Clock and Data Crossing (CDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
E.1 CDC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
E.2 Port Clocking and Input Synchonizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
E.3 CDC Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Appendix F
Advanced Information: Reset Domain Crossing (RDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946

Appendix G
Advanced Information: VC-Based Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
G.1 VC-Based Arbitration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
G.2 VC-Based WRR Arbitration Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Appendix H
Advanced Information: Advanced Filtering and Routing of TLPs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
H.1 Filtering Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
H.2 Filtering Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
H.3 Upstream Port Routing Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
H.4 Request TLP Routing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
H.5 Processing Illegal CFG TLPs and CFG1-CFG0 Conversion in Each PCI Express Port Type . . . . . . . . . 966

Appendix I
Advanced Information: Advanced Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
I.1 PCIe Ordering Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
I.2 Inbound (Receive) Order Enforcement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
I.3 Outbound (Transmit) Order Enforcement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973

Appendix J
Advanced Information: Advanced LBC and DBI Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
J.1 Programming Examples: CDM / ELBI Register Space Access Through DBI. . . . . . . . . . . . . . . . . . . . . . . 975
J.2 Configuration Intercept Controller (CIC) for USP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976

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Appendix K
Advanced Information: How to Tie Off Unused Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
K.1 Conventional PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979

Appendix L
Advanced Information: Advanced Error Handling for Received TLPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
L.1 Routing of Request TLPs with Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
L.2 Routing of Completions with Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
L.3 Application Error Reporting Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990

Appendix M
Advanced Information: Calculating Gen1 PCI Express Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
M.1 PCI Express Bandwidth and Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
M.2 Effective Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996

Appendix N
Advanced Information: Advanced Routing of Received Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
N.1 Routing of Received Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999

Appendix O
Advanced Information: Replay Buffer Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001

Appendix P
Advanced Information: Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003

Appendix Q
Introduction to PCIe Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
Q.1 Switch Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
Q.2 Digital IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
Q.3 Mixed Signal IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
Q.4 Switch Application Logic Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
Q.5 Advanced Switch Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Q.6 Non-Standard Switch Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
Appendix R
Advanced Information: Area, Power Estimates, and RAM Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
R.1 Area Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
R.2 Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
R.3 RAM Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029

Appendix S
Advanced Information: Flow Control Credit Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
S.1 Calculation of Flow Control Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
S.2 Calculation of Initial Flow Control Credits and Receive Buffer Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
Appendix T
Advanced Information: Serialization Queue Almost Full Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
T.1 Serialization Queue Almost Full Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
T.2 Serialization Queue Input and Output Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043

Appendix U
Internal Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046

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Revision History

Date March 2019

■ A full list of functional (RTL) changes is in the “Release Notes: PCI Express Cores” document.
■ A change-tracked version of this databook is available at
https://www.synopsys.com/dw/doc.php/iip/DWC_pcie/5.40a/doc/DWC_pcie_ctl_sw_databook_change.pdf
■ The change-tracked version does not indicate minor changes that has been made for readability, formatting, and
so on. It only indicates changes to functionality, new features, and major rewrites.

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Preface

A single coreKit is provided for DesignWare PCI Express DM, EP, RC, and SW controller ports. Using the
Device Type parameter (CC_DEVICE_TYPE) in coreConsultant GUI (as shown in Figure 1) you can configure
the controller as a:
■ 0 (EP): Endpoint port
■ 1 (RC): Root complex port
■ 2 (DM): Dual Mode port (pin-selectable EP/RC)
■ 3 (SW): Switch port (pin-selectable upstream/downstream)

■ The RC databook is not a description of the DM controller in RC mode.


Attention
■ Unlike the Registers and Signal Descriptions chapters, the Parameter Descriptions
chapter is common across all four databooks. The value of the CC_DEVICE_TYPE param-
eter in expressions should be interpreted according to the above list.
■ The parameter descriptions in Parameter Descriptions chapter include the Enabled: attri-
bute which indicates the values required to be set on other parameters before you can
change the value of the parameter in question.

Figure 1 Device Type Parameter in coreConsultant GUI

After the PCIe controller is configured as DM, EP, RC, or SW port, depending upon the features licensed,
the PCIe controller can be identified as:
■ Native PCIe controller (without AMBA bridge): Basic PCIe controller which has its own non-stan-
dard, proprietary dedicated bus interface to your application.
■ CCIX PCIe controller (without/with AMBA bridge): PCIe controller which has its own non-standard,
proprietary dedicated CCIX interface to your application (when not using the AMBA bridge) or CCIX

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compliant AMBA bridge interface to your application (when using the AMBA bridge). To enable CCIX
features, set the parameter CX_CCIX_ENABLE to 1.

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Product Codes
Table 1 lists the product codes and product names for DesignWare PCI Express controller ports.

Table 1 Product Codes

Product Code Product Name

Native PCIe (without AMBA bridge)

C902-0 DWC PCIe 1.0 Standard

C903-0 DWC PCIe 1.0 Plus

C904-0 DWC PCIe 1.0 Premium

C908-0 DWC PCIe 2.0 Standard

C909-0 DWC PCIe 2.0 Plus

C910-0 DWC PCIe 2.0 Premium

C914-0 DWC PCIe 3.0 Standard

C915-0 DWC PCIe 3.0 Plus

C921-0 DWC PCIe 4.0 Plus

C926-0 DWC PCIe 5.0 Standard

C927-0 DWC PCIe 5.0 Plus

C928-0 DWC PCIe 5.0 Premium

PCIe with AMBA bridge

C905-0 DWC PCIe 1.0 Standard AMBA

C906-0 DWC PCIe 1.0 Plus AMBA

C907-0 DWC PCIe 1.0 Premium AMBA

C911-0 DWC PCIe 2.0 Standard AMBA

C912-0 DWC PCIe 2.0 Plus AMBA

C913-0 DWC PCIe 2.0 Premium AMBA

C917-0 DWC PCIe 3.0 Standard AMBA

C918-0 DWC PCIe 3.0 Plus AMBA

C919-0 DWC PCIe 3.0 Premium AMBA

C923-0 DWC PCIe 4.0 Standard AMBA

C929-0 DWC PCIe 5.0 Standard AMBA

C930-0 DWC PCIe 5.0 Plus AMBA

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Product Code Product Name

C931-0 DWC PCIe 5.0 Premium AMBA

CCIX

C932-0 DWC CCIX 25G

C933-0 DWC CCIX 25G AMBA

Automotive

C934-0 DWC AP PCIe 1.0

C936-0 DWC AP PCIe 2.0

C937-0 DWC AP PCIe 2.0 AMBA

C938-0 DWC AP PCIe 3.0

C939-0 DWC AP PCIe 3.0 AMBA

C940-0 DWC AP PCIe 4.0

C941-0 DWC AP PCIe 4.0 AMBA

CCIX Automotive

C942-0 DWC AP CCIX 25G

C943-0 DWC AP CCIX 25G AMBA

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Reference Documentation
After installing the controller, the DWC PCI Express documents can be found under:
$DESIGNWARE_HOME/iip/DWC_pcie_ctl/latest/doc.
When you create a workspace in coreConsultant,
■ Pre-configuration, the DWC PCI Express documents for all four ports are available in <work-
space>/doc.
■ Post-configuration, only the documents corresponding to your configured controller port are avail-
able in <workspace>/doc.
When viewing documents from coreConsultant GUI (as shown in Figure 2),
■ Pre-configuration, the coreConsultant GUI points to the DM port documents.
■ Post-configuration, the coreConsultant GUI points to your configured controller port documents.

Figure 2 Viewing Documents from coreConsultant GUI

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Web Resources
■ DesignWare IP product information: https://www.synopsys.com/designware-ip.html
■ Your custom DesignWare IP page: https://www.synopsys.com/dw/mydesignware.php
■ Documentation through SolvNet: https://solvnet.synopsys.com (Synopsys password required)
■ Synopsys Common Licensing (SCL):https://www.synopsys.com/support/licensing-installa-
tion-computeplatforms/licensing.html

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PCI Express SW Controller Databook Preface

Terms and Abbreviations


The following terms are used throughout this document:

Table 2 Terms and Descriptions

Term Description

x1/x2/x4/x8/x16 1/2/4/8/16 lanes

BAR Base Address Register

Application software is a single program or a collection of small programs intended to


Application
perform certain tasks. In this document Application Software/Application logic is used to
Software/Application
identify customer specific application software/logic, for example customer implementation
Logic
to handle Rx/Tx/VDM TLPs.

CCIX Cache Coherent Interconnect for Accelerators

Configuration Dependent Module


CDM This is an internal block in the native controller that has the PCIe configuration registers and
some user-accessible registers.

Configuration Intercept Controller


Allows your application logic to detect the occurrence of; and to modify (using the CII) the
CIC
behavior of Rx CFG requests (from the remote link partner) that are accessing the
controller's internal registers.

Configuration Intercept Interface


CII
See “Configuration Intercept Controller (CIC) for USP” on page 976.

CPL Completion

C-PCIe Conventional PCI Express

Control Register Parallel Interface


CRPI The control registers in some Synopsys PHYs (for example, C8/C10/E12/E16) can be
accessed through this interface.

Common Xpress Port Logic


CXPL The internal controller module that implements the majority of the PCI Express protocol
layers.

CXS CCIX Stream Interface

Data Bus Interface


You can use this interface to locally access the controller’s internal registers in the CDM, or
DBI
your external application registers on the ELBI. You can optionally connect a local CPU or
controller to this port.

DLLP Data Link Layer Packet

DRS Device Readiness Status

Downstream port
DSP
Refers to root complex (RC) port and/or switch downstream port.

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Term Description

DWORD Double Word (32 bits)

External Local Bus Interface


Delivers an inbound register RD/WR received by the controller to external application
registers when the controller is expected to generate the PCIe completion of this register
ELBI RD/WR. For switch applications: the ELBI is intended for incoming requests that are
targeted to local switch application registers, while TRGT1 is intended for TLPs that are
passing through the switch. The controller automatically generates completions for
requests that are routed to the ELBI.

FRS Function Readiness Status

Host System System in which the host CPU resides

Host Software Software pertaining to the host system

iATU Internal Address Translation Unit

PCIe transactions that enter the controller from the wire side of the controller (PCIe wire).
Inbound traffic
These transactions are delivered to your application side.

Local Bus Controller


This is an internal block that allows the DBI interface (from your application side), or the
LBC
wire side interface (through the TRGT0 interface), to access the CDM or your external
application registers on the ELBI.

LTR Latency Tolerance Reporting

M-PCIe PCIe for M-PHY (not C-PCIe)

Maximum Transfer Unit


MTU Specifies the maximum packet payload size supported. This indicates the maximum
allowed transfer size for a write or completion.

Identifies the basic PCIe controller (without AXI Bridge) which has its own non-standard,
Native PCIe controller
proprietary dedicated bus interface to your application.

Number of Functions
NF
The value “1” represents one function.

Number of Double Words


NW
The value “1” represents a 32-bit DWORD.

NP Non-posted

Transactions that enter the controller from your application side of the controller. These
Outbound traffic
transactions are passed to the native controller, where they are sent out onto the PCIe wire.

P Posted

PCIe PCI Express

Standard PIPE interface between the PCI Express PHY and the controller. If you set
PIPE
PHY_TYPE to be the Synopsys PHY, then the PHY is included inside the controller.

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Term Description

PIPE Message Bus Controller


PMBC This module controls the PIPE Message Bus interface. It is enabled only when
CX_PIPE_VER >=3 or CX_MAX_PCIE_SPEED >=4.

PMC Power Management Controller

PRC PHY Register Controller

PHY Register Bus Interface


This interface facilitates direct access of PHY registers by your application through DBI or
PRBI CFG requests.
Note: Only Synopsys PHYs supporting Control Register Parallel Interface (CRPI), for
example Synopsys C8/C10/E12/E16 PHYs can be accessed through this interface.

Precision Time Measurement feature as defined in PCI Express Base Specification,


PTM
Revision 4.0, Version 1.0.

RADM Receive Application-Dependent Module

RAM Interface
RAMI Optional top-level interface to connect external RAMs for the retry buffer and receive
queues. If you do not select the optional top-level RAMI, the RAMs reside inside the
top-level hierarchy of the controller.

Reliability, Availability, and Serviceability


RAS
A collection of features aimed at error protection, error and event logging, and debug.

RAS-DP / RASDP Data Protection aspect of RAS.

RAS-DES / RASDES Debug, Error injection, and Statistics aspects of RAS.

System Information Interface


SII
Exchanges system information between the controller and your application.

Software Software is often divided into application software and system software.

SW PCI Express Switch (SW) controller

System software includes System Firmware (BIOS, UEFI), Operating System, VMM, power
management services, device drivers, user-mode services, kernel mode services, platform
vendor's add-on to the Operating System. It is also responsible for managing hardware
System Software
components and providing basic non-task-specific functions.
Configuration Software is an example of system software responsible for accessing
Configuration Space and configuring the PCI/PCIe bus.

TLP Transaction Layer Packet

Receive Target 0 Interface


TRGT0 This is an internal logical receive interface used to access registers in the CDM, or external
application registers on the ELBI.

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Term Description

Receive Target 1 and Bypass Interfaces


TRGT1 / RBYP These are the RX interfaces used to connect the native controller to your application .
RBYP is used by queues that are in bypass mode.

Receive Target 1 CCIX Interface.


TRGT1_CCIX
This RX interface is used to connect the native controller to your CCIX application.

Generic term for customer specific software (system as well as application, depending on
User Application
the context).

Upstream port
USP
Refers to endpoint port and/or switch upstream port.

VC Virtual Channel

Vendor Message Interface


VMI Allows your application to request a transmission of a vendor message independent from
the XALI client interfaces.

Vendor Specific Extended Capability


Most of the Synopsys implementation-specific registers (not defined by the PCI-SIG PCIe
VSEC specification) are located in the Port Logic space beginning at 0x700.
Going forward from release 4.40a, all new implementation-specific register groups are
implemented as VSEC’s in the PCIe Extended Capability Structure address space.

Transmit Client 0 Interface


XALI0
Transmit interface for outbound request or CPL TLPs.

Transmit Client 1 Interface


Additional application transmit interface, identical to XALI0. The usage of XALI0 and XALI1
XALI1
is up to your application. For example, an application might use XALI0 for requests and
XALI1 for completions.

Transmit Client 2 Interface


An optional transmit client interface, identical to XALI0 and XALI1. An example usage of the
XALI2
three transmit client interfaces is to use one for posted requests, one for non-posted
requests, and one for completions.

Transmit Client CCIX Interface


XALI_CCIX
Transmit interface for outbound CCIX TLPs.

XADM Transmit Application-Dependent Module

■ TRGT0/TRGT1 refer to the two logical Rx interfaces. RTRGT1 is a physical interface.


Hint
■ TRGT1 is mapped to RTRGT1 in native controller configurations.
■ TRGT0 can be mapped to the ELBI or CDM.

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Customer Support
To obtain support for your product:
■ First, prepare the following debug information, if applicable:
❑ For environment setup problems or failures with configuration, simulation, or synthesis that occur
within coreConsultant or coreAssembler, use the following menu entry:
File > Build Debug Tar-file
Check all the boxes in the dialog box that apply to your issue. This menu entry gathers all the
Synopsys product data needed to begin debugging an issue and writes it to the file <controller tool
startup directory>/debug.tar.gz.
❑ For simulation issues outside of coreConsultant or coreAssembler:
■ Create a waveforms file (such as VPD or VCD)
■ Identify the hierarchy path to the DesignWare instance
■ Identify the timestamp of any signals or locations in the waveforms that are not understood Then,
contact Support Center, with a description of your question and supplying the previous information,
using one of the following methods:
❑ For fastest response, use the SolvNet website. When you fill in your information as explained later,
your issue is automatically routed to a support engineer who is experienced with your product.
The Sub Product 1 entry is critical for correct routing.
Go to http://solvnet.synopsys.com/EnterACall and click on the link to enter a call. Provide the
requested information, including:
■ Customer Tracking Number: Enter your project name. Use the same name for cases related to
the same project.
■ Product: DesignWare Cores
■ Sub Product 1: PCI Express
■ Product Version: 5.10a (for example)
■ Problem Type:
■ Issue Severity:
■ Problem Title: Provide a brief summary of the issue or list the error message you have encoun-
tered
■ Problem Description: For simulation issues, include the timestamp of any signals or locations in
waveforms that are not understood
After creating the case, attach any debug files you created in the previous step.
❑ Or, send an e-mail message to [email protected] (your e-mail is queued and then, on
a first-come, first-served basis, is manually routed to the correct support engineer):
■ Include the Product name, Sub Product name
■ For simulation issues, include the timestamp of any signals or locations in waveforms that are
not understood
■ Attach any debug files you created in the previous step.
❑ Or, telephone your local support center:

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■ North America: Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific time, Monday through
Friday.
■ All other countries: https://www.synopsys.com/support/global-support-centers.html

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PCI Express SW Controller Databook Product Overview

1
Product Overview

This section gives an overview of the PCI Express controller. The topics in this section are:
■ “General Product Description” on page 24
■ “Applications” on page 26
■ “Features and Limitations” on page 27
■ “Frequency, Speed, and Width Support” on page 29
■ “Deliverables” on page 40
■ “Standards” on page 41

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General Product Description PCI Express SW Controller Databook

1.1 General Product Description


This DesignWare PCI Express controller provides a solution to implement a PCI Express port for a PCI
Express switch application. The SW port controller can operate as an upstream port or downstream port.
The operating mode of the controller is determined by the device_type input pin at power-up.

Attention The Synopsys PCI Express IP does not implement a full switch.

To implement a full switch, you must add your application routing logic (connected to the application client
interface ) and other support logic (including clock and reset generation). For more information, see
“Integrating with your Application RTL” section in the “Integrating the controller with the PHY, or
Application RTL, or Verification IP” chapter of the User Guide.
The PCIe controller implements the three PCI Express protocol layers (Transaction layer, Data Link layer,
and the MAC portion of the physical layer) in synthesizable RTL. It also implements the
application-dependent functionality of the PCI Express Transaction Layer for packet transmission, which is
located between your application logic and the PCI Express protocol layers.
A complete PCI Express port solution includes the controller, an analog PHY macro, and application logic to
source and sink data. The physical layer is split across the PIPE and controller such that the MAC
functionality (LTSSM, lane-to-lane deskew) is in the controller and the PHY functionality is implemented in
the PIPE-compliant PHY. The PHY is outside of the controller, interfacing through the standard PIPE
interface. For more information, see “Integrating the Controller with the PHY” section in the “Integrating
the Controller with the PHY, or Application RTL, or Verification IP” chapter of the User Guide.

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PCI Express SW Controller Databook General Product Description

Figure 1-1 Three Instances of Switch Port Controller in a Three-Port PCI Express Switch
PCI Express Link to Upstream Device

PIPE-Compliant PHY

PHY Interface (PIPE)

DWC PCIe Controller

Transaction Layer
Data Link Layer
Physical Layer(MAC)

Application Dependent
part of the
Transaction Layer

Switch Port 0
Application
Interfaces
Switch Application Logic

Application Application
Interfaces Interfaces

Switch Port 1 Switch Port 2

Application Dependent Application Dependent


part of the part of the
Transaction Layer Transaction Layer

Transaction Layer Transaction Layer

Data Link Layer Data Link Layer


Physical Layer(MAC) Physical Layer(MAC)

DWC PCIe Controller DWC PCIe Controller

PHY Interface (PIPE) PHY Interface (PIPE)

PIPE-Compliant PHY PIPE-Compliant PHY

PCI Express Link to Downstream Device PCI Express Link to Downstream Device

Customer Logic
PCIe Protocol
Synopsys Implementation

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Applications PCI Express SW Controller Databook

1.2 Applications
Typical applications for a PCI Express component built with the controller include:
■ Hyper-transport to PCI Express bridge
■ SATA to PCI Express bridge
■ Transparent PCI Express switch (For more information, see “Non-transparent Switches” on page 1025)
■ Non-Transparent PCI Express switch
The switch port controller is configurable as Upstream Switch or Downstream Switch port/device type but
is not configurable as a PCI Express to PCI/PCI-X bridge or PCI/PCI-X to Express bridge port/device type.
For more information on switches see “Introduction to PCIe Switches” on page 1006.

Note The switch port controller is not intended for use in a PCI Express endpoint or root complex.

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PCI Express SW Controller Databook Features and Limitations

1.3 Features and Limitations


1.3.1 Features
The Synopsys PCI Express controller supports:
■ All non-optional features of the PCI Express Base Specification, Revision 4.0, Version 1.0
■ The following optional features of the specification:
❑ Atomic Operations
❑ TLP Prefix
❑ L1 Substates (L1SS)
❑ Extended Tag Support
❑ Resizable BAR (RBAR) with Expanded RBAR and VF Resizable BAR support
❑ Optimized Buffer Fill and Flush (OBFF)
❑ Separate Refclk with Independent Spread Spectrum Clocking (SRIS)
❑ Gen3 Receiver Impedance
❑ Lightweight Notifications (LN)
❑ Readiness Notifications (RN)
❑ PCI Express Active State Power Management (ASPM)
❑ PCI Express Advanced Error Reporting (AER) with Multiple Header Logging
❑ PCI Express Advanced Error Reporting (AER)
❑ Vital Product Data (VPD)
❑ Precision Time Measurement (PTM)
❑ Access Control Services (ACS)
■ Up to x16 Gen1, Gen2, Gen3, Gen4, or Gen51 lanes (x1, x2, x4, x8, or x16)
■ 32, 64, 128, 256, or 512-bit Internal Datapath Operating at 62.5, 125, 250, 500, 625, 781.25, 1000, 1250, or
1562.5 MHz
■ 512-bit Internal Datapath Operating at 62.5, 125, 250, or 500 MHz
■ Automatic Integration with Most PHY types (8-bit, 16-bit, 32-bit, and 64-bit PIPE Width per Lane)
■ Power Gating (UPF) Support
■ Advanced Power and Clock Management
■ Internal Address Translation Unit
■ Internal MSI-X Generation Module
■ Automatic Lane Reversal
■ Upconfigure Support
■ RAS DES (Debug, Error Injection, and Statistics)
■ RAS DP (Data Protection) for Datapath and RAMs using ECC or Parity
■ ECRC Generation and Checking
1. Compliant with PCI Express Base Specification Revision 5.0, Version 0.9 with limitations. For more information, see the product
release notes.

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Features PCI Express SW Controller Databook

■ Configuration Intercept Controller to allow your application modify CFG access from wire
■ Multiple Virtual Channels (VCs), Traffic Classes (TCs), and Quality of Service (QOS)
■ Bypass, Cut-through, and Store-and-forward Queue Modes for Rx TLPs
■ Configurable Receive and Retry Buffer sizes
■ Configurable Max_Payload_Size size (128 bytes to 4 KB)
■ Configurable Filtering Rules for Posted, Non-posted, and Completion Traffic
■ Configurable BAR Filtering, I/O Filtering, Configuration Filtering and Completion Lookup/Timeout
■ Three Application Transmit Clients
■ Type 1 Configuration space
■ Application-initiated Manual Lane Reversal/flip for situations where controller does not detect Lane
0
■ MSI and MSI-X with Per-Vector Masking (PVM)
■ Configuration as Upstream Switch or Downstream Switch port/device type. It is NOT Configurable
as a PCI Express to PCI/PCI-X bridge or PCI/PCI-X to Express bridge port/device type
■ Prefetchable Memory Space
■ Transaction Filtering and Routing Look up
■ Configurable VC/TC Mapping
■ PHY Register access (Only for PHYs supporting Control Register Parallel Interface)
■ Automotive support
■ Transmit Interface Progression Detection
■ CDM Register Check
■ CCIX Support

Some features require an additional license. Licensing requirements are given in the
Attention
Installation Guide

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PCI Express SW Controller Databook Frequency, Speed, and Width Support

1.4 Frequency, Speed, and Width Support


To set the frequency, datapath width, and speed modes of the controller, use the following configuration
parameters in the coreConsultant GUI:
■ Max Link Speed (CX_MAX_PCIE_SPEED)
■ Controller Gen1, Gen2, Gen3, Gen4, and Gen5 Freq/Width (CX_MAC_SMODE_GEN1, CX_MAC_S-
MODE_GEN2, CX_MAC_SMODE_GEN3, CX_MAC_SMODE_GEN4, and CX_MAC_SMODE_GEN5)
■ PHY Gen1, Gen2, Gen3, Gen4, and Gen5 Freq/Width (CX_PHY_SMODE_GEN1, CX_PHY_SMODE_-
GEN2, CX_PHY_SMODE_GEN3, CX_PHY_SMODE_GEN4, and CX_PHY_SMODE_GEN5)
■ Maximum Link Width (CX_NL)

Figure 1-2 Conventional PCIe Frequency, Speed, and Width Configuration Parameters in coreConsultant GUI

After you have set these parameters, the coreConsultant tool cross-references your available licenses and
automatically calculates the following values:
■ Controller PIPE Lane Width (CX_PIPE_WIDTH_ bits or CX_NB bytes)
■ PHY PIPE Lane Width: (CX_PHY_PIPE_WIDTH_ bits or CX_PHY_NB bytes)
■ Datapath Width: (CX_NW/32 bits rounded up to multiple of 32 or CX_NL*CX_NB bytes)
■ CX_FREQ_STEP_DOWN_EN. This is the enable for the “Frequency Step Module (CX_FREQ_STEP_EN
=1)” on page 38

1.4.1 Gen2/Gen3/Gen4/Gen5 Modes


The controller supports Dynamic frequency, width, and pacing configurations for Gen2/Gen3/Gen4/Gen5
modes.
■ Dynamic Frequency (DF): For DF configurations, the number of active symbols on the PIPE is
constant; the frequency of the controller doubles each time as the controller transitions from Gen1 ->
Gen2 -> Gen3 -> Gen4 -> Gen5 rates.
■ Dynamic Width (DW): For DW configurations, the frequency of the controller is constant; the number
of active symbols on the PIPE doubles each time as the controller transitions from Gen1 -> Gen2 ->
Gen3 -> Gen4 rates.

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Synthesis for 1GHz Clock Frequency PCI Express SW Controller Databook

■ Dynamic Pacing (DP): DP is a rate reduction mode for the PIPE interface that allows for a higher clock
rate to be used at a slower data rate. It uses the mac_phy_txdatavalid and phy_mac_rxdatavalid
Gen3 signals to obtain the slower effective rate by toggling them every other clock (2:1 DP) or every
fourth clock (4:1 DP). This controls the number of valid symbols per one, two, or four clock cycles.
When DP is not used in a lower speed mode, these signals must be held high. At Gen3 rate these
signals are also used for regular de-assertion for 128b/130b encoding and decoding. The mac_-
phy_txdatavalid and phy_mac_rxdatavalid signals are present on all Gen3 and Gen4 configura-
tions. However, DP is only enabled for some controller/PHY combinations as indicated in Table 1-5.
For more information on the usage of the mac_phy_txdatavalid and phy_mac_rxdatavalid
signals, see “Signal Interfaces” on page 278.

■ The controller and PHY can have different Gen2 modes. For example, you can configure
Note the controller for Dynamic Frequency and the PHY for Dynamic Width. This is also true for
Gen3, Gen4, and Gen5.
■ For more information, see “Gen2/3/4/5 Speed Modes” on page 206, “Gen3 8.0 GT/s Oper-
ation” on page 206, and “Gen4 16.0 GT/s Operation” on page 207.

1.4.2 Synthesis for 1GHz Clock Frequency


1GHz operation is functionally supported as indicated in Table 1-2 on page 33. However, passing critical
timing is dependent on your configuration, process technology, operating conditions, and sign-off corner,
and may not be supported for all crosses of these variables. The default pipeline settings are configured to
allow timing closure without incurring unnecessary latency. However, it may be necessary to enable the
parameter CX_CUSTOM_PIPELINING to enable additional pipelines for your particular configuration. It is
recommended that you assess the feasibility of closing timing with your specific scenario setup by adjusting
your configuration parameters as suggested in Table 1-1.
You must follow the suggestions for configuration parameter settings marked as High severity in Table 1-1.
It is highly recommended that you follow the suggestion or/and use high speed library (that is, ULVT) for
configuration parameter settings marked as Medium severity in Table 1-1.

Table 1-1 Timing Critical Parameter Setting for 1Ghz Clock Frequency

Feature Parameter Value Severity Suggestions

3 or 4
RASDP
Data path Use Parity for Data path protection
Datapath CX_RASDP High
protection (CX_RASDP = 1 or 2)
Protection
with ECC

CX_INTERNAL_ATU_ENABLE
Address
CX_ATU_NUM_OUTBOUND_REGION >= 64
Translation High Reduce the number of regions
S Regions
Unit (ATU)
CX_ATU_NUM_INBOUND_REGIONS

Multiple
Virtual CX_NVC >= 3 High Reduce the number of VCs
Channels

Multiple
CX_NFUNC >= 16 High Reduce the number of functions
Functions

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PCI Express SW Controller Databook Synthesis for 1GHz Clock Frequency

Feature Parameter Value Severity Suggestions

Reduce the number of tags


Outbound
Contact Synopsys support if your
AXI CC_MAX_SLV_TAG (AXI) >= 128 High
system requires large number of
Transactions
TAGs.

Reduce the number of tags


Inbound AXI Contact Synopsys support if your
CC_MAX_MSTR_TAGS_AXI (AXI) >= 128 High
Transactions system requires large number of
TAGs.

■ Reduce the number of tags


(CC_MAX_SLV_TAG &
CC_MAX_MSTR_TAG_AXI)
■ Reduce number of DMA chan-
Embedded nels
CC_DMA_ENABLE 1 High
DMA ■ Disable Byte Alignment feature
(CC_DMA_BA_ENABLEa =0)
■ Change TAG remapping archi-
tecture (CC_MSTR_AXI_G-
M_EDMA_HTb =1)

Assess the feasibility of closing


timing with your specific setup to
select PIPE interface width at
CCIX ESM
CX_CCIX_ESM_SUPPORT 1 High 25GT/s speed either 2s
speed
(1562.5Mhz) or 4s (781.25Mhz).
Recommended option is 4s
(781.25Mhz).

Two or more medium severity configuration parameter settings High Follow the suggestions given

Simultaneous
Inbound Non
CX_REMOTE_MAX_TAG >= 127 Medium Reduce number of tags
Posted
Requests

Address
Translation CX_INTERNAL_ATU_ENABLE 1 Medium Reduce number of regions
Unit (ATU)

■ Reduce number of VFs


CX_SRIOV_ENABLE >= 128 Disable
SR-IOV Medium DYNAMIC_VF_ENABLE
CX_MAX_VF_X VFs
■ Enable CX_VF_STRIDE_AL-
WAYS_ONE

Multiple
CX_NFUNC >= 8 Medium Reduce number of functions
Functions

Outbound
AXI CC_MAX_SLV_TAG (AXI) >= 64 Medium Reduce number of tags
Transactions

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Supported Controller Configurations PCI Express SW Controller Databook

Feature Parameter Value Severity Suggestions

Inbound AXI
CC_MAX_MSTR_TAGS_AXI (AXI) >= 64 Medium Reduce number of tags
Transactions

a. This is a hidden parameter and is not visible in coreConsultant GUI. The default value of CC_DMA_BA_ENABLE is ‘1’. You can
change the value of this parameter through coreConsultant command line (using set_configuration_parameter command).
b. This is a hidden parameter and is not visible in coreConsultant GUI. The default value of CC_MSTR_AXI_GM_EDMA_HT is ‘0’.
You can change the value of this parameter through coreConsultant command line (using set_configuration_parameter
command).

To discuss trade-offs, or optimizations to your configuration, contact Synopsys support through Solvnet.
Floorplan Considerations for 1GHz Clock Frequency (Controller standalone)
The module and pin placement floorplan considerations for 1GHz clock frequency are as follows:
Module Placement
■ Place application interface modules close to your application logic
❑ Native Configuration
■ u_DWC_pcie_core/u_xadm
■ u_DWC_pcie_core/u_radm
■ Place physical layer modules close to PHY
❑ u_DWC_pcie_core/u_cx_pl/u_xmlh
❑ u_DWC_pcie_core/u_cx_pl/u_rmlh
❑ u_DWC_pcie_core/u_cx_pl/u_smlh
❑ u_DWC_pcie_core/gen_pipe_regif *
❑ u_DWC_pcie_core/gen_freq_step *
❑ u_DWC_pcie_core/u_lane_flip
❑ u_DWC_pcie_core/u_pipe *
PIN Placement
■ Place PIPE interface pins close to PHY
❑ PIPE Interface
❑ PHY Register Bus Interface
■ Place application interface pins close to your application logic
❑ Native Configuration
■ Receive Bypass / Request Interface (RBYP/TRGT1)
■ Transmit Interfaces (XALI0/1/2)

1.4.3 Supported Controller Configurations


Table 1-2 lists configurations supported by the controller.

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PCI Express SW Controller Databook Supported Controller Configurations

Table 1-2 Supported Controller Configurations

Maxa Link Width(for each controllerb


Datapath width)

core_clk @ Gen1 Gen2 Gen3 Gen4 Gen5


Gen{1,2,3,4,5} Speed Speed Speed Speed Speed
speed Modec Mode Mode Mode Mode 32-bit 64-bit 128-bit 256-bit 512-bit

250 g1_1s NA NA NA NA x4 x8 x16 NA NA


Gen1
Configu 125 g1_2s NA NA NA NA x2 x4 x8 x16 NA
rations
62.5 g1_4s NA NA NA NA x1 x2 x4 x8 NA

250, 250 g1_1s g2_2s_dw NA NA NA x2 x4 x8 x16 NA

125, 125 g1_2s g2_4s_dw NA NA NA x1 x2 x4 x8 x16


Gen2
Configu 250, 500 g1_1s g2_1s_df NA NA NA x4 x8 x16 NA NA
rations
125, 250 g1_2s g2_2s_df NA NA NA x2 x4 x8 x16 NA

62.5, 125 g1_4s g2_4s_df NA NA NA x1 x2 x4 x8 x16

250, 250,
g1_1s g2_2s_dw g3_4s_dw NA NA x1 x2 x4 x8 x16
250

125, 125,
g1_2s g2_4s_dw g3_8s_dw NA NA NA x1 x2 x4 x8
125
Gen3
250, 500,
Configu g1_1s g2_1s_df g3_1s_df NA NA x4 x8 x16 NA NA
1000d
rations
125, 250,
g1_2s g2_2s_df g3_2s_df NA NA x2 x4 x8 x16 NA
500

62.5, 125,
g1_4s g2_4s_df g3_4s_df NA NA x1 x2 x4 x8 x16
250

250, 250,
g1_1s g2_2s_dw g3_4s_dw g4_8s_dw NA NA x1 x2 x4 x8
250, 250

125, 250,
g1_2s g2_2s_df g3_2s_df g4_2s_df NA x2 x4 x8 x16 NA
Gen4 500, 1000d
Configu
rations 62.5, 125, g1_4s g2_4s g3_8s g4_8s NA NA x1 x2 x4 x8
125, 250

62.5, 125,
g1_4s g2_4s_df g3_4s_df g4_4s_df NA x1 x2 x4 x8 x16
250, 500

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Controller-PHY Compatibility PCI Express SW Controller Databook

Maxa Link Width(for each controllerb


Datapath width)

core_clk @ Gen1 Gen2 Gen3 Gen4 Gen5


Gen{1,2,3,4,5} Speed Speed Speed Speed Speed
speed Modec Mode Mode Mode Mode 32-bit 64-bit 128-bit 256-bit 512-bit

62.5, 125,
250, 500, g1_4s g2_4s_df g3_4s_df g4_4s_df g5_4s_df x1 x2 x4 x8 x16
1000d

Gen5 62.5, 125,


Configu 125, 250, g1_g4 g2_4s g3_8s g4_8s g5_8s NA x1 x2 x4 x8
rations 500

125, 250,
250, 500, g1_2s g2_2s g3_4s g4_4s g5_4s x1 x2 x4 x8 x16
1000d

a. The value in each cell indicates the maximum link width supported. You can configure the controller with a link width up to this value,
and coreConsultant automatically calculates the datapath width.
b. For license scheme , see the “Checking License Requirements” section in the DWC PCI Express Controller Installation Guide.
c. The g value indicates the speed mode. The s value indicates the number of 8-bit symbols processed per clock cycle per lane by the
controller PIPE interface, in the indicated speed mode. The dw/df value indicates how the speed change to that mode is achieved.
d. For more information, see “Synthesis for 1GHz Clock Frequency” on page 30.

1.4.4 Controller-PHY Compatibility


The following tables indicate which combinations of controller configurations from Table 1-2 and PHYs are
supported. In Table 1-3 to Table 1-6, the sets of values for each row indicates how the controller moves from
Gen1 to Gen2 speed mode, from Gen2 to Gen3 speed mode, from Gen3 to Gen4 speed mode, and from Gen4
to Gen5 speed mode, wherever applicable. The set of values also identifies the particular controller
configuration in Table 1-2. The controller always uses the same mechanism (DF or DW) to go from Gen1 to
Gen2, from Gen2 to Gen3, from Gen3 to Gen4, and from Gen4 to Gen5. However, some Gen3/Gen4/Gen5
PHYs use a mix of mechanisms (for example, the PHY in the fifth and sixth columns of Table 1-3) and others
support Dynamic Pacing (DP) which is indicated by the dp postfix (for example, PHY in the third column of
Table 1-3).

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PCI Express SW Controller Databook Controller-PHY Compatibility

Table 1-3 Gen5 Controller-PHY Combinations Supported

PHY

g1_2s g1_2s g1_4s g1_1s_dp g1_1s g1_1s g1_4s


g2_2s_df g2_2s_df g2_4s_df g2_1s g2_1s_df g2_1s_df g2_4s_df
g3_2s_df g3_4s_dw g3_4s_df g3_2s_dw g3_2s_dw g3_4s_dw g3_8s_dw
g4_2s_df g4_4s_df g4_4s_df g4_4s_dw g4_2s_df g4_4s_df g4_8s_df
g5_2s_df g5_4s_df g5_4s_df g5_4s_df g5_4s_dw g5_4s_df g5_8s_df

g1_2s
g2_2s_df
g3_4s_dw
g4_4s_df
C
g5_4s_df
O
N g1_4s
T g2_4s_df
R
g3_4s_df
O
L g4_4s_df
L g5_4s_df
E
g1_4s
R
g2_4s_df a
g3_8s_dw
g4_8s_df
g5_8s_df

a. Support for 64-bit (8s) PIPE is specific to Synopsys; the PIPE specification specifies a maximum of the
maximum data width of 32 bits. When CX_PIPERX_MULTI_BLOCK =0, the controller only accepts
64-bit-aligned SKP OS. If you use this configuration, your PHY PCS must follow this requirement. When
CX_PIPERX_MULTI_BLOCK =1, blocks can start any 32-bit boundary by extending bit-width of rxstart-
block and rxsyncheader (phy_mac_rxstartblock: 2-bit per-lane and phy_mac_rxsyncheader 4-bit per-lane).
For more information, see “64-Bit PIPE Receive Operation (CX_PIPERX_MULTI_BLOCK =1)” on page
308.

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Controller-PHY Compatibility PCI Express SW Controller Databook

Table 1-4 Gen4 Controller-PHY Combinations Supported

PHY

g1_1s_dp g1_1s_dp g1_1s g1_1s g1_1s g1_2s g1_2s_dp g1_4s g1_4s


g2_1s g2_1s g2_1s_df g2_1s_df g2_2s_dw g2_2s_df g2_2s_dp g2_4s_df g2_4s_df
g3_2s_dw g3_2s_dw g3_2s_dw g3_4s_dw g3_4s_dw g3_2s_df g3_2s g3_4s_df g3_8s_dw
g4_2s_df g4_4s_dw g4_2s_df g4_4s_df g4_8s_dw g4_2s_df g4_2s_df g4_4s_df g4_8s_dw

g1_1s
g2_2s_dw a

g3_4s_dw
g4_8s_dw
C g1_2s
O g2_2s_df b c
N
g3_2s_df
T
R g4_2s_df
O g1_4s
L d
g2_4s_df
L
E g3_4s_df
R g4_4s_df

g1_4s
g2_4s_df
g3_8s_dw
g4_8s_dw

a. Support for 64-bit (8s) PIPE is specific to Synopsys; the PIPE specification specifies a maximum of the maximum data width of 32
bits. When CX_PIPERX_MULTI_BLOCK =0, the controller only accepts 64-bit-aligned SKP OS. If you use this configuration, your
PHY PCS must follow this requirement. When CX_PIPERX_MULTI_BLOCK =1, blocks can start any 32-bit boundary by extending
bit-width of rxstartblock and rxsyncheader (phy_mac_rxstartblock: 2-bit per-lane and phy_mac_rxsyncheader 4-bit per-lane). For
more information, see “64-Bit PIPE Receive Operation (CX_PIPERX_MULTI_BLOCK =1)” on page 308.
b. DP PHY: doing Gen1 with 2:1 DP, Gen2 with no DP, Gen3 using DW, and obtaining Gen4 using DF.
c. DP PHY: doing Gen1 with 2:1 DP, Gen2 with 2:1 DP, Gen3 with no DP, and obtaining Gen4 using DF.
d. DP PHY: doing Gen1 with 2:1 DP, Gen2 with no DP, Gen3 using DW, and obtaining Gen4 using DW.

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PCI Express SW Controller Databook Controller-PHY Compatibility

Table 1-5 Gen3 Controller-PHY Combinations Supported

PHY

g1_1s_dp g1_1s g1_2s g1_2s g1_1s g1_2s g1_2s_dp g1_4s


g2_1s g2_2s_dw g2_2s_df g2_4s_dw g2_1s_df g2_2s_df g2_2s_dp g2_4s_df
g3_2s_dw g3_4s_dw g3_4s_dw g3_8s_dw g3_1s_df g3_2s_df g3_2s g3_4s_df

g1_1s
g2_1s_df
g3_1s_df

g1_1s
C
g2_2s_dw
O
N g3_4s_dw
T g1_2s
R a
g2_4s_dw
O
L g3_8s_dw
L
g1_2s b c
E
g2_2s_df
R
g3_2s_df

g1_4s
g2_4s_df
g3_4s_df

a. Support of a 64-bit (8s) PIPE is specific to Synopsys; the PIPE specification specifies a maximum of the maximum data width
of 32 bits. The controller only accepts 64-bit-aligned SKP OS. If you use this configuration, your PHY PCS must follow this
requirement
b. DP PHY: doing Gen1 with 2:1 DP, Gen2 with no DP, and obtaining Gen3 using DW.
c. DP PHY: doing Gen1 and Gen2 with 2:1 DP, Gen3 with no DP.

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Table 1-6 Gen2 Controller-PHY Combinations Supported

PHY

g1_1s g1_2s g1_1s g1_2s g1_4s


g2_2s_dw g2_4s_dw g2_1s_df g2_2s_df g2_4s_df

g1_1s
g2_2s_dw
C
O g1_2s
N g2_4s_dw
T
R g1_1s
O g2_1s_df
L
L g1_2s
E g2_2s_df
R
g1_4s
g2_4s_df

Table 1-7 Gen1 Controller-PHY Combinations Supported

PHY

g1_1s g1_2s g1_4s

C
g1_1s
O
N
T g1_2s
R
O
L
L g1_4s
E
R

Frequency Step Module (CX_FREQ_STEP_EN =1)


When the controller PIPE lane width (CX_NB) and PHY PIPE lane width (CX_PHY_NB) are different, or when
the controller and the PHY have different Gen2 speed modes, then the derived CX_FREQ_STEP_EN
parameter is defined, and a PIPE adapter module1 is added between the controller PIPE and the PHY PIPE.
If the controller clock frequency is slower than the pipe clock frequency, the derived parameter
CX_FREQ_STEP_DOWN_EN is defined. If the core_clk frequency is faster than the pipe_clk frequency, the
derived CX_FREQ_STEP_UP_EN parameter is defined. In typical configurations (CX_FREQ_STEP_EN =0),
the pipe_clk input in not present.

1. Located in workspace/src/common/freq_step.v

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PCI Express SW Controller Databook Controller-PHY Compatibility

Figure 1-3 Location of freq_step PIPE Adapter Module

Controller P pclk

freq_step
Sub- (pclkx2)
PIPE (core) PIPE (PHY) H
blocks Y

pipe_clk
CLK
core_clk Gen

This module steps up/down the signals at the PIPE interface and adjusts the controller PIPE width
according to the PHY PIPE width if the core_clk frequency is slower or faster than the pipe_clk frequency.

Controller-PHY Integration
The PHY module resides outside of the controller, interfacing through the standard PIPE interface. For more
information, see “Integrating the Controller with the PHY” in the User Guide.

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Deliverables PCI Express SW Controller Databook

1.5 Deliverables
The deliverables for the PCIe controllers include:
■ Synthesizable RTL source code
■ Synopsys coreConsultant tool for automated configuration, synthesis, and simulation
■ Synopsys PHY simulation model
■ A Verilog Testbench (VTB):
❑ Allows you to re-execute the regression tests on your configuration of the controller for the
purpose of verifying your configuration.
❑ Demonstrates connectivity and many types of transfers. Can be used for system-level testbench
integration.

1.5.1 Verification Environment Overview


The verification environment for the controller includes a packaged VTB and separate VIP components. The
VTB runs the packaged self-checking regression tests through coreConsultant to validate the configured
controller. For more information, see the “Simulating the Controller” section in the User Guide.

1.5.2 CoreConsultant Overview


The Synopsys coreConsultant tool allows you to configure, simulate, synthesize, and export the controller to
your design flow. The final output from the coreConsultant design flow is a set of RTL files (the configured
RTL controller) and scripts to allow you run various standalone tests within your own design flow. The
coreConsultant features and tasks include:
■ A graphical user interface (GUI) to guide you through design flow activities.
All activities may also be performed through a command line interface.
■ Interactive parameter selection.
The coreConsultant tool checks for consistent settings and automatically derives any dependent
parameters from your choices.
■ Testbench simulation and synthesis configuration consistent with your parameter choices.

1.5.3 Synthesis Overview


The coreConsultant tool is your interface to Synopsys tools for ASIC synthesis of the controller. Synthesis
scripts and constraints can be exported from coreConsultant and reused with non-Synopsys tools to
synthesize the controller in your own design flow.

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PCI Express SW Controller Databook Standards

1.6 Standards
The PCIe controller implements the following standards:
■ PCI Express Base Specification, Revision 4.0, Version 1.0
Access to this specification requires membership in PCI-SIG.
Download site:
http://pcisig.com/specifications
■ PIPE Specification for PCI Express, Version 4.4.1
Download site:
http://www.intel.com/technology/pciexpress/devnet/resources.htm
■ PCI Local Bus Specification, Revision 3.0
Access to this specification requires membership in PCI-SIG.
Download site:
http://www.pcisig.com/specifications/conventional/pci_30
■ PCI Bus Power Management Specification, Revision 1.2
Access to this specification requires membership in PCI-SIG.
Download site:
http://www.pcisig.com/specifications/conventional/pci_bus_power_management_interface
■ PCI Express Card Electromechanical Specification, Revision 3.0
Access to this specification requires membership in PCI-SIG.
Download site:
https://members.pcisig.com/wg/PCI-SIG/document/download/8250

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Architecture PCI Express SW Controller Databook

2
Architecture

This section describes the architecture of the PCI Express controller. The topics in this section are:
■ “Overview” on page 43
■ “RAM Requirements” on page 48
■ “Clock Requirements” on page 53
■ “Reset Requirements” on page 64
■ “Receive Queues” on page 74

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2.1 Overview
The implementation of the PCIe protocol and mode-specific features is split across several modules.

Figure 2-1 PCIe Architecture Overview

Application Interfaces

Application Dependent part of the


Transaction Layer

(RADM/XADM/CDM)

CXPL
Transaction Layer

Data Link Layer

Physical Layer(MAC)

PHY Interface (PIPE)

CLK/RST PIPE-Compliant PHY

■ Common Express Port Logic (CXPL) Module implements the basic functionality for the PCI Express
physical, link, and transaction layers. This module implements a large part of the transaction layer
logic, all of the data link layer logic, and the MAC portion of the physical layer, including the link
training and status state machine (LTSSM). The CXPL connects to the external PHY through the PIPE.
For more information, see “Integrating with the PHY in the PCI Express controller” in the User Guide.
■ Transmit Application-Dependent Module (XADM) implements the application-specific function-
ality of the PCI Express transaction layer for packet transmission. Its functions include:
❑ TLP Arbitration
❑ TLP Formation
❑ Flow Control (FC) Credit checking
The transmit path uses a cut-through architecture. It does not implement transmit buffering/queues
(other than the retry buffer).
■ Receive Application-Dependent Module (RADM) implements application-specific functionality of
the PCI Express transaction layer for packet reception. Its functions include:
❑ Sorting/filtering of received TLPs. The filtering rules and routing are configurable.
❑ Buffering and queuing of the received TLPs. For more information, see “Receive Queues” on page
74.

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❑ Routing of received TLP to the controller’s receive interfaces.


The RADM maintains a Receive Completion Lookup Table (LUT) for completion tracking and
completion-timeout monitoring of Tx non-posted requests. It indicates a timeout when an expected Rx
completion does not arrive within the timeout period.
■ Configuration-Dependent Module (CDM) implements:
❑ Standard PCI Express configuration space
❑ Controller-specific register space (Port Logic Registers)
For more information on the registers implementation in the CDM, see “Register Configuration Space
Overview” on page 100.
■ Power Management Controller (PMC) implements the power management features of the controller.
■ Local Bus Controller (LBC) and Data Bus Interface (DBI)
The LBC module provides a mechanism for a link partner or a local CPU (through the DBI) to access:
❑ Internal registers (in the CDM)
❑ External application registers connected externally to the ELBI
■ Message Generation Module (MSG_GEN) transmits messages generated by the controller. For more
information see, “Messages” on page 152.
■ Hot Plug Control Module (HOTPLUG) implements logic to generate interrupts on hot plug events.

Table 2-1 Output Signals Used to Notify of Hot Plug Events

Mode Output Signal Used

MSI or MSI-X hp_msi

INTx hp_int

PMEa hp_pme

a. The controller does not check if the PM state is D1, D2, or D3hot. It is up to your application to check the value on pm_dstate
to make sure the device is in D1, D2, or D3hot.

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Figure 2-2 SW Controller Block Diagram

RBYP
RAM
Application
Logic: TRGT1 RADM RX PIPE
Receive
TRGT1_CCIX

TRGT0
CPU DBI

CIC
Application ELBI LBC
Registers
iATU
1 PRBI PRC
CXPL Core PHY
Application CDM
Logic: Controller
PRC
MSI(-X) Registers
RAS
RAM
Application
Logic:
SII
Rx Vendor
Messages

XALI0

Application XALI1
Logic: XADM RAM TX PIPE
Transmit XALI2

XALI_CCIX CRPI

PMBC
1
Application
Logic:
Tx Vendor VMI MSG_GEN
Messages

Application CLK/RST
Logic: HOT PLUG
Optional
SII
System Status/
Control
Registers PMC

Application Optional
Logic: Note: In DSP there is no wire
Customer Logic
Coherent CXS access to CDM or ELBI.
CXS PCIe Protocol
Multichip Link Controller However, there is DBI access.
Synopsys
(CML) Specific

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Table 2-2 Controller Interface Summary

Interface Function

XALI0 is a transmit interface used by your application for transmission of


Transmit Client 0 Interface (XALI0)
outbound requests or CPL TLPs.

XALI1 is an additional application transmit interface, identical to XALI0. You


can use XALI0 and XALI1 as per your application requirements. For example,
Transmit Client 1 Interface (XALI1)
your application might use XALI0 exclusively for transmission of outbound
requests and XALI1 exclusively for transmission of completions.

XALI2 is an optional transmit client interface, identical to XALI0 and XALI1. An


example usage of the three transmit client interfaces can be, using XALI0
Transmit Client 2 Interface (XALI2)
exclusively for posted requests, XALI1 exclusively for non-posted requests,
and XALI2 exclusively for completions.

XALI_CCIX is a transmit interface used by your application for transmission of


Transmit CCIX Interface (XALI_CCIX)
CCIX TLPs.

Receive Target 0 Interface is an internal logical receive interface used to


Receive Target 0 (TRGT0)
access registers in the CDM, or external application registers on the ELBI.

Receive Target 1 (TRGT1)/ Receive TRGT1 and RBYP are receive interfaces used to connect the native controller
Bypass Interface (RBYP) and your application . RBYP is used by queues that are in bypass mode.

TRGT1_CCIX receive interface is used to connect the controller and the CCIX
Receive Target 1 CCIX Interface logic of your application.
(TRGT1_CCIX)

ELBI is used to deliver an inbound register RD/WR request received by the


controller, to external application registers. The controller generates a
completion TLP for this register RD/WR request.
External Local Bus Interface (ELBI) For switch applications, the ELBI is used tor incoming requests that are
targeted to local switch application registers, while TRGT1 is used for TLPs
that are passing through the switch. The controllers automatically generate
completions for requests that are routed to the ELBI.

DBI is used by your application to access the controller’s internal registers in


Data Bus Interface (DBI) the CDM, or your external application registers on the ELBI. You can
optionally connect a local CPU or controller to this port.

Message Signaled Interrupt (MSI) MSI Interface can be used by your application to send MSI requests to the
Interface controller, independent of XALI client interfaces.

MSI-X Interface can be used by your application to send MSI-X requests to


MSI-X Interface
the controller, independent of XALI client interfaces.

VMI can be used by your application for transmission of vendor messages,


Vendor Message Interface (VMI)
independent of the XALI client interfaces.

SII is used for exchanging system information between the controller and your
System Information Interface (SII)
application.

Standard PIPE interface (PIPE Specification for PCI Express, Version 4.4.1)
PIPE
between the PCI Express PHY and the controller.

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Interface Function

Allows your application logic to detect the occurrence of; and to modify the
behavior of Rx CFG requests (from the remote link partner) that are
Configuration Intercept Interface (CII)
accessing the controller's internal registers. See also CIC in “Configuration
Intercept Controller (CIC) for USP” on page 976.

This is an optional interface, that facilitates direct access of PHY registers by


your application through DBI or CFG requests.
PHY Register Bus Interface (PRBI) Note: Only Synopsys PHYs supporting Control Register Parallel Interface, for
example Synopsys C8/C10/E12/E16 PHYs can be accessed through this
interface.

CXS in the PCIe controller enables the use of PCIe IP in the implementation
CCIX Stream Interface (CXS)
of Coherent Multi-chip Links.

■ TRGT0/TRGT1 refer to the two logical Rx interfaces. RTRGT1 is a physical interface.


Hint
■ TRGT1 is mapped to RTRGT1 in native controller configurations.
■ TRGT0 can be mapped to the ELBI or CDM.

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2.2 RAM Requirements


This section covers RAM requirements for the controller. The following topics are discussed:
■ “Overview”
■ “Internal and External RAM Verilog Instances” on page 51
■ “ECC Protection Support” on page 51
■ “RAM Sizes” on page 52

2.2.1 Overview
The controller supports external and internal RAMs.
■ The value of configuration parameter CX_RAM_AT_TOP_IF indicates if the RAMs are external or
internal.
❑ CX_RAM_AT_TOP_IF =1; RAMs are external.
❑ CX_RAM_AT_TOP_IF =0; RAMs are internal.
■ RAMs are either dual-port (write port A and read port B) or one-port (one shared read/write port).
Note: All RAMs are dual-port, except the retry buffer and iMSI-RX RAMs, which are one port.
■ RAMs must have single-cycle access latency, that is, read data is expected on the next cycle after the
address is supplied. The controller supports the RAM types in Figure 2-3 and Figure 2-4.
■ RAMs do not have to be initialized.
■ When using the UPF flow (CX_ENHANCED_PM_EN =1), all RAMs are in the PD_VAUX power domain
and may be powered-down in L2 and L1.

UPF model for RAMs or isolation rules to cover the outputs of the RAMs are not provided
Note when RAMs are powered down. You should ensure that RAM power gating or isolation is
handled correctly in your application.

Figure 2-3 Types of Dual-Port RAMs Supported


CX_RAM2P_ARCH =0 CX_RAM2P_ARCH =1
(Registered Read Port Data Output ) (Registered Read Port Address Input)
g

adrA adrB adrA adrB


in
m
-t i
Re

wenA renB wenA renB


RAM RAM
dinA doutB dinA doutB
g
in

Cells Cells
tim
-
Re

clkA clkB clkA clkB

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Figure 2-4 Types of One-Port RAMs Supported


CX_RAM1P_ARCH =0 CX_RAM1P_ARCH =1
(Registered Read Port Data Output ) (Registered Read Port Address Input)

g
adr adr

in
m
-t i
Re
wen re wen ren
RAM RAM
din dout din dout

g
in
Cells Cells
tim
-
Re

clk clk clk clk

RAM Implementation
Each module that uses RAM instantiates one of the following synthesizable RAM models with the required
width and depth parameters:
■ workspace/src/vendor/generic/ram1p.v (for one-port RAM)
■ workspace/src/vendor/generic/ram2p.v (for dual-port RAM)
You must instantiate your technology-specific RAM models from your RAM vendor inside ram1p.v and
ram2p.v.
The CX_RAM_TYPE configuration parameter determines the type of RAMs used in the controller when you
are using internal RAM (CX_RAM_AT_TOP_IF =0).

To implement or synthesize a small RAM as a register file, either replace the ram1p.v/ram2p.v
Hint files with your own register-file implementation or choose CX_RAM_TYPE =1.

CX_RAM_TYPE can have the following values:

■ 0: Simple
This is synchronous RAM supplied by your vendor. For simulation, you do not need to do anything
because a Verilog register-based RTL code exists in the ram1p.v/ram2p.v files. For implementation,
ou need to instantiate your technology-specific compiled RAM inside ram1p.v and ram2p.v.
Note: External RAMs are always simple RAMs.
■ 1: DesignWare
This is Synopsys DesignWare Library (register-based) SRAM memory generator for sizes up to 256 X
256. For more information, see http://www.synopsys.com/dw/ipdir.php?c=DW_ram_2r_w_s_dff
or http://www.synopsys.com/dw/ipdir.php?c=DW_ram_rw_s_dff.
■ 2: FPGA RAM
This is FPGA memory. For simulation, you do not need to do anything because Verilog register-based
RTL code exists in the ram1p.v/ram2p.v files. For implementation, the FPGA synthesis tool should
infer the appropriate block RAMs.

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RAM Timing
The RAM read cycle latency is the delay between the time at which the read address is presented by the
controller to the RAM, and the time at which the read data is presented by the RAM to the controller. The
default read access time of the RAM is one clock cycle.
To ease timing closure at high clock frequencies, external pipelines on the read address path or the read data
path can be added to the RAM read path. You can configure the appropriate RAM read latency parameter
(described in the Table 2-3 ) so that the controller can sample the read data correctly. These parameters
specify the number of cycles after which the controller expects RAM read data to appear. For example, if the
AXI Master Completion Buffer RAM read data is externally re-timed, then you can set
CC_MSTR_CPL_SEG_BUF_RAM_RD_LATENCY =2.

Figure 2-5 RAM Read Interface Timing (CC_MSTR_CPL_SEG_BUF_RAM_RD_LATENCY =2)

clk

read_enable/
address

read_data

Table 2-3 RAM Read Latency Parameters for Native Controller RAMs

RAM Parameter

RADM Receive Queue RAM CX_RADM_RAM_RD_LATENCY (1-4 cycles)

Retry RAM CX_RETRY_RAM_RD_LATENCY (1-2 cycles)

SOT RAM CX_RETRY_SOT_RAM_RD_LATENCY (1-2 cycles)

MSIX Table RAM CX_MSIX_TABLE_RAM_RD_LATENCY (1-4 cycles)

By default, the AXI bridge registers RAM interfaces to facilitate timing closure. To reduce RAM
Note write/read latencies, pipeline stages on the write/read control interface signals can be removed,
subject to closing timing on these interfaces. Contact Synopsys support through SolvNet, if the
default RAM write/read latencies are of concern.

You can also set the following parameters to place a re-timing register at the output of the RAMs.
■ CX_RETRYSOTRAM_REGOUT
■ CX_RETRYRAM_REGOUT
The read data output of the Rx Queue RAMs is always re-timed/registered by the controller.
You can set the following parameter to place a register at the boundary between the Rx queue manager
outputs and the Rx queue RAM inputs.
■ CX_RADM_INQ_MGR_REGOUT
After you configure the RAM1P_RD_ACCESS, RAM1P_ADDR_SU, RAM2P_RD_ACCESS, and RAM2P_ADDR_SU
parameters, the coreConsultant tool generates the timing requirements. For more information on accessing

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synthesis scripts and SDC, see “Synthesizing to a Device Outside of coreConsultant” in the “Exporting a
Controller From coreConsultant to Your Chip Design Database” section of the User Guide.

2.2.2 Internal and External RAM Verilog Instances


This section provides the details of the internal and external RAM verilog instances. Most of the internal
RAMs are not in the controller top-level but are in the individual sub-blocks that use them.
For external RAMs, you can find a verified RAM wiring template that has the correct controller-to-RAM
connections in: workspace/examples/pcie_iip_rams.v. You should reuse this template, and not
manually wire your external RAMs to the controller because it is an error-prone process.

Table 2-4 Native Controller Receive and Transmit RAMs

Verilog Instance Name

Description Internal RAM External RAM

Native Controller Receive and Transmit RAMs

Transmit Retry Buffer u_ram_1p_rbuf

Start-Of-TLP (SOT) Buffera u_ram_2p_sotbuf

Receive Data Queueb u3_ram_radm_qbuffer_data[D-1:0]

Receive Header Queueb u0_ram_radm_qbuffer_hdr[H-1:0]

Receive Serialization Queue


u_ram_radm_formq_qdw[S-1:0]
(512-bit datapath)c

a. The retry buffer which stores transmitted TLPs for potential replaying has an associated Start-of-TLP (SOT) buffer. This
is required for identifying the start of TLPs in the retry buffer.
b. When you select 32-bit, 64-bit and 128-bit datapath configurations the controller instantiates one header RAM and one
data RAM, that is, H=D=1. When you select a 256-bit datapath configuration an additional header and data RAM are
required to process 2 TLPs in one cycle, that is, H=D=2. When you select a 512-bit datapath configuration one header
RAM and 4 data RAMs are instantiated, that is, H=1, D=4. Only one header RAM is required as the 512-bit Rx Queue
processes only 1 TLP per cycle. For 512-bit datapath configurations a serialization queue is used to send TLPs to the
Rx Queue, one TLP at a time. The data RAMs store 128 bits of data per cycle and scale with the data width, that is,
for datapath configurations up to 128-bit one data RAM is required, for 256-bit two data RAMs are required, for 512-bit
4 data RAMs are required. Note: the number of RAMs is not influenced by the number of VCs. As the number of VC's
increase the depth of the RAMs increase.
c. When you select a 512-bit datapath configuration a TLP serialization queue is instantiated before the Receive queues.
The Receive Serialization Queue is comprised of 6 RAMs when TLP prefixing is disabled (S=6), increasing to 7 RAMs
when TLP prefixing is enabled (S=7).

Table 2-5 RAS D.E.S. RAMs (CX_RAS_DES_ENABLE)

Description Verilog Instance Name

Internal RAM External RAM

Event Counter Memory u_ram_cdm_rasdes_ec_reg

Time-based Analysis Memory u_ram_cdm_rasdes_tb_reg

2.2.3 ECC Protection Support


For more information, see “RAS Data Protection (DP)” on page 126.

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2.2.4 RAM Sizes


The address and data widths of the memory interfaces are automatically derived based on other design
parameters. The coreConsultant tool generates a preliminary RAM report for your configuration in
workspace/report/RamSizes.html. You should not design to these reported RAM sizes. You can obtain
an accurate report of RAM sizes after running a simulation in coreConsultant. The testbench reports the
RAM sizes in the simulation log file at workspace/sim/<testname>/test.log. You must search for the
phrase RAM Size to find the memory report section as shown in Figure 2-6.

Figure 2-6 Snippet of Log File Showing the Reporting of RAM Sizes

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PCI Express SW Controller Databook Clock Requirements

2.3 Clock Requirements


This section covers the following clock generation topics for the controller, focusing on conventional PCIe.
■ “Overview”
■ “General Clock Relationships” on page 54
■ “Gen2, Gen3, Gen4, or Gen5 Speed Changing Considerations (CX_FREQ_STEP_EN =1)” on page 57
■ “Removing the Reference Clock” on page 58
■ “Additional Information” on page 60
■ “Clock Generation Module” on page 60

2.3.1 Overview
The PCIe controller requires the clocks outlined in Table 2-6.

Table 2-6 Generation of Individual Clock Signals by Your Clock Generation Logic

Clock Notes

■ This is the primary clock for the controller.


■ It can have a frequency of 62.5, 125, 250, 500, or 1000 MHz. For more information on
supported clock frequencies and datapath widths, see “Frequency, Speed, and Width
Support” on page 29.
core_clk
■ The core_clk is derived from the pipe_clk output of the PHY (whose TX PLL uses
the platform reference clock REFCLK).
■ The core_clk signal must be gated-off when muxd_aux_clk is being switched to run
at low frequency.

■ The gated version of the core_clk for modules retained during L1 power gating.
ret_core_clk ■ The ret_core_clk frequency is the same as core_clk.
■ You can gate this clock during the L1 and L2 low power states under the same condi-
tions as core_clk.

■ An ungated version of core_clk (called core_clk_ug) exists because a small number


of controller registers must receive core_clk during switching to-and-from low-power
states.
core_clk_ug ■ When DWC_pcie_clkrst.v has switched off core_clk, the controller uses core_-
clk_ug to detect and latch the PHY status from the pipe interface to complete the tran-
sition to the low-power state. After switching to the low-power state has completed,
core_clk_ug might not be active because the PHY might stop providing pipe_clk
(from which core_clk and core_clk_ug are derived).

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Clock Notes

■ This clocks the PMC.


■ It is derived from the platform AUX clk by DWC_pcie_clkrst.v which drives the
controller’s aux_clk input through the muxd_aux_clk wire.
■ When the controller output pm_sel_aux_clk is set to 1 the source of aux_clk should
be switched to the low frequency clock and core_clk should be gated off. For more
information, see “Removing the Reference Clock” on page 58.
■ When exiting L1/P2 you should increment the L1 Exit Latency in the Link Capabilities
register by two or three muxd_aux_clk periods to allow time for DWC_pcie_clkrst.v
aux_clk to switch muxd_aux_clk back to core_clk.
■ The aux_clk and core_clk clocks must be completely synchronous during normal
operation. You must ensure that the aux_clk and core_clk clock trees are balanced
during layout. There are no lower or upper limits on the frequency of aux_clk unless
you are using the “L1 Substates” on page 219.
■ The controller uses aux_clk for counting time during L1 substates. You must program
the frequency of this clock into the L1_SUBSTATES_OFF register with a value in the range
1...1000MHz to count real time. Frequencies lower than 1 MHz are possible, but with a
loss of accuracy in the time counted.

aux_clk_g ■ This is a gated version of aux_clk that is used to clock the CDM registers and the
LBC/DBI.

■ This is a gated version of core_clk that is used to clock the RADM (Rx filter and
queues).
radm_clk_g
■ The DWC_pcie_clkrst.v module uses the en_radm_clk_g controller outputa to
enable radm_clk_g.

■ In typical configurations (CX_FREQ_STEP_EN =0), this clock pin does not exist.
■ The pipe_clk input is used by the controller to clock the PIPE.
■ It can have a frequency of 62.5, 125, 250, 500, or 1000 MHz.
pipe_clk ■ The PHY TX PLL generates pipe_clk from the platform reference clock. The PHY
adapts and re-times RX data to pipe_clk.
■ The core_clk and pipe_clk clocks must have the same phase and have frequencies
that are integer multiples of each other.
■ In normal operation (L0/D0), core_clk and core_clk_ug are derived from pipe_clk.

■ Clock enable for phy_reg_clk_g.


en_phy_reg_clk
■ When en_phy_reg_clk_g clock signal is 1, phy_reg_clk_g becomes active.
_g
■ This clock exists only when CX_PHY_VIEWPORT_ENABLE =1.

■ This clock is gated by en_phy_reg_clk_g.


■ This clock exists only when CX_PHY_VIEWPORT_ENABLE =1.
phy_reg_clk_g
Note: For Synopsys PHYs supporting Control Register Parallel Interface, this clock should
be used as cr_para_clk, if the PHY registers are accessed through PRBI.

a. The controller de-asserts this signal when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty,
RADM completion LUT is empty, and there are no FLR actions pending. You must set the RADM_CLK_GATING_EN
field in the CLOCK_GATING_CTRL_OFF register to enable this functionality; otherwise the en_radm_clk_g output is
always be set to ‘1’.

2.3.2 General Clock Relationships


Figure 2-7 indicates the approximate relationships between the different clocks for the “Clock Generation
Module” on page 60. It is not cycle accurate and is given for the purpose of illustration only. You must

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simulate the controller to obtain precise timings. For the purposes of simplicity, the diagram shows
core_clk being derived from pipe_clk without division. For the meaning of signal labels, refer to the
“Clock Generation Module” on page 60.

Figure 2-7 Clock Waveforms with External PHY (Not Cycle Accurate)
REF_CLK

#
pipe_clk
Normally all clocks are derived
from pipe _clk

core_clk

core_clk_ug
core_clk_ug is never gated
or shut off. It runs until
pipe_clk ceases.
aux_clk
(platform AUX
clock)

muxd_aux_clk Application optionally


(controller’s removes reference clock
aux_clk input) to the PHY PLL which in
turn causes pipe _clk to
cease. PLL can also
ref_clk_req_n optionally turn off
auxclk_flop_d2 switches pipe_clk when REF_CLK
muxd_aux_clk from pipe_clk is still running.
to aux_clk and also shuts off
clk_rst.auxclk_flop_d2 core_clk

# In typical configurations (CX_FREQ_STEP_EN=0), this clock pin does not exist.

2.3.2.1 Synchronous To Attribute

In the “Signal Descriptions” chapter, the “Synchronous To:” attribute indicates which controller clocks
sample an input (or drive an output) when considering all possible configurations.
■ In many cases an output has components driven (or an input sampled) by multiple clocks.
■ The attribute lists all clocks which drive or sample for all possible configurations. It is an automatically
generated list accumulated over all configurations.
■ Your particular configuration might not have all of the clocks listed. If you have access to the Spyglass
tool, then you can generate a configuration-specific report using the process outlined in the “Running
Spyglass” section of the User Guide.
■ When there is only one clock in the list, this clock is normally but not always the same as the clock that
your application logic should use to clock (sample/drive) this pin.
■ When there is more than one clock in the list:
■ A {} is placed around the clock which is used in generating the synthesis in/out timing delay
constraints and which is also used in Spyglass boundary CDC checking.
■ In most cases, this is also the clock that you should use to drive/sample the pin in normal operational
(non low-power) mode.
■ If more1 than one clock has a {}, that clock is configuration-dependent, and you should look in your
SDC file (as explained in the “Synthesizing to a Device Outside of coreConsultant” section of the User
Guide) to see which one is relevant.

1. Normally only applies to the PIPE outputs which are clocked on pipe_clk or core_clk depending on CX_FREQ_STEP_EN.

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Figure 2-8 Snippet from Signal Descriptions Chapter Showing Synchronous To

■ When you see “perbitclk” in the clock list, it indicates that there is a different clock for some of the bits
in the multi-bit port, and/or that some of the bits in a multi-bit port falls into the various categories as
defined next by “None”.
■ When you see “None_as” in the clock list, it indicates the following and is equivalent/mapped to
core_clk for CDC synthesis.
❑ Asynchronous reset with synchronous de-assertion.
■ When you see “None” in the clock list, it indicates any of the following1 and is equivalent/mapped to
core_clk for CDC and synthesis.
❑ Direct or combinatorial feed-through.
❑ Gated-off (that is, unclocked) inputs.
❑ Unused inputs.
❑ Hard-coded outputs.
❑ Asynchronous outputs.
❑ Asynchronous resets.

For asynchronous inputs (excluding asynchronous resets), CDC synchronizers are


Note added in the RTL. For more information, see “Port Clocking and Input Synchonizers” on
page 943
■ Asynchronous inputs cannot be identified by the “Synchronous To” attribute. This attri-
bute identifies the sampling clock (synchronous or asynchronous).
■ Asynchronous outputs are indicated with “Synchronous To: None”.

Generalized Interface Clocking Guidelines Qualifying the Synchronous To Attribute


■ All clocks (except AXI) are quasi-synchronous and depending on the situation, it is not incorrect to use
any of them.
■ The presence of aux_clk (not aux_clk_g) implies a connection to a low-power feature and where
you see it listed, you can make use of that low-power feature by sampling/driving on aux_clk.
■ CDM Outputs (cfg_*/cdm_*)

1. In at least one of all possible configurations.

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❑ All are clocked out by aux_clk_g which runs slow in low-power mode.
❑ You might want to sample some of these outputs during L1 and take action.
❑ However, it is not expected that you have your complete application running in low-power mode
(on aux_clk_g) because this might result in higher and unnecessary power consumption.
■ Client Interfaces (client0/1/2_*)
❑ When driven from the aux_clk domain the client0_tlp_hv pin triggers exit from low power
as per “L1 Operation (Non-substates)” on page 230.
❑ The whole interface (all client0_tlp_* inputs) must be driven from the same clock because
header info and so on, needs to be provided at the same time as client0_tlp_hv.
❑ An alternative method to trigger L1 low-power exit is to use and clock xfer_pending on aux_clk
and to drive the client0_tlp_* interface on core_clk.
■ TRGT1 Interface (trgt1_*)
❑ The controller clocks this interface on radm_clk. However, there are some status paths going back
to the CDM (aux_clk_g and core_clk).
❑ If your application interface is receiving requests and generating responses (on client0_tlp_*), it
recommended to use core_clk to sample this interface and drive the response interface.
❑ If your application interface is only receiving requests, it recommended to use radm_clk to
sample this interface.
■ PIPE Interface (mac_phy_*/mac_phy_*)
❑ pipe_clk indicates a frequency step1.
❑ The PIPE interface also drives/samples logic on aux_clk for low-power entry and exit.

2.3.3 Gen2, Gen3, Gen4, or Gen5 Speed Changing Considerations (CX_FREQ_STEP_EN =1)
When the PHY is dynamic frequency and the controller is dynamic width, pipe_clk changes frequency
when moving between modes. However, core_clk should not change frequency. Your synthesized
controller logic operates at a fixed frequency, so it is imperative that your external clock generation and
switching logic (see DWC_pcie_clkrst.v) never generates core_clk with a higher frequency during
mode switching. The controller uses the mac_phy_rate output to negotiate the link data rate and waits for
a pulse on the phy_mac_phystatus input to confirm that the PHY has accepted the requested rate.
However, you must carefully consider the following facts when designing the logic that controls the
core_clk switch selection between pipe_clk and the divided pipe_clk:

■ The PHY can start generating pipe_clk at the newer frequency several clock cycles before it asserts
phy_mac_phystatus.
■ A typical anti-glitch clock switch does not switch the clock source until several clock cycles after it has
been instructed to do so.
Therefore, your external clock generation and switching logic should:
■ Start switching as soon as mac_phy_rate changes if moving to a faster speed mode. That is, do not
switch too late.

1. PIPE outputs which are clocked on pipe_clk or core_clk depending on CX_FREQ_STEP_EN.

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■ Delay switching until phy_mac_phystatus acknowledges mac_phy_rate if moving to a slower


speed mode. That is, do not switch too early to ensure that core_clk does not have a frequency higher
than what the controller is synthesized for.
The DWC_pcie_clkrst.v module implements this feature.

Figure 2-9 Recommended Clock Divider Switching Points During Speed Changes (Not Cycle Accurate)

#
pipe_clk

PLL can move to higher frequency before it asserts


phy_mac_phystatus. Therefore do not wait for Wait for phy_mac_status before
phy_mac_phystatus before dividing pipe _clk to generate core _clk removing pipe _clk division.

core_clk

mac_phy_rate Gen1 Gen2 Gen1

phy_mac_phystatus

pipe_clk divider /1 /2 /1

# In typical configurations (CX_FREQ_STEP_EN=0), this clock pin does not exist.

The controller uses core_clk to sample the phy_mac_phystatus input which the PHY generates at
pipe_clk. Therefore when the PHY is dynamic frequency and the controller is dynamic width (that is,
when core_clk is not equivalent to pipe_clk), you must ensure that:
■ core_clk is toggling when the PHY updates phy_mac_phystatus for a speed change
OR
■ your external logic holds phy_mac_phystatus (for the speed change) until core_clk toggles again.

2.3.4 Removing the Reference Clock


There are three schemes for removing the reference clock. For more information on low-power clocking see
“Power Management” on page 213 and “Synchronous To Attribute” on page 55.

Table 2-7 REFCLK Removal Schemes

REFCLK Removal Scheme Controller Outputs Used Notes

L1 CLK PM
clk_req_n
(CX_L1_SUBSTATES_EN =0) “L1 Clock PM (L1 with REFCLK removal/PLL Off)
L1 CLK PM Overview” on page 233
mac_phy_pclkreq_n[0]a
(CX_L1_SUBSTATES_EN =1)

L1 Substates “L1 Substates” on page 219 and “L1.1 and L1.2


mac_phy_pclkreq_n[1]
(CX_L1_SUBSTATES_EN =1) Entry and Exit Conditions” on page 221

a. mac_phy_pclkreq_n signal is relevant only for PIPE 4.2 version.

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Figure 2-10 Clock Removal Schemes

PCIe Controller PHY

REFCLK
pclk PLL

CX_L1_SUBSTATES_ENABLE =0 &
CX_PIPE_VER =0 (PIPE 4.2)
mac_phy_powerdown[1:0] mac_phy_powerdown[1:0]
mac_phy_powerdown[3:2] NC
phy_mac_phystatus[NL-1:0] phy_mac_phystatus[NL-1:0]
mac_phy_pclkreq_n mac_phy_pclkreq_n
phy_clk_req_n

CX_L1_SUBSTATES_ENABLE =0 &
CX_PIPE_VER >=1 (PIPE 4.3 or Later)
mac_phy_powerdown[3:0] mac_phy_powerdown[3:0]

phy_mac_phystatus[NL-1:0] phy_mac_phystatus[NL-1:0]
phy_clk_req_n

CX_L1_SUBSTATES_ENABLE =1 &
CX_PIPE_VER =0 (PIPE 4.2)
mac_phy_rxelecidle_disable mac_phy_rxelecidle_disable
mac_phy_txcommonmode_disable mac_phy_txcommonmode_disable
mac_phy_powerdown[1:0] mac_phy_powerdown[1:0]
mac_phy_powerdown[3:2] NC
mac_phy_pclkreq_n[0] mac_phy_pclkreq_n[0]
mac_phy_pclkreq_n[1] mac_phy_pclkreq_n[1]
phy_clk_req_n L1 substate
L1.CPM PLL on/off
phy_mac_pclkack_n phy_mac_pclkack_n
L1 substate Logic
Logic phy_mac_phystatus[NL-1:0] phy_mac_phystatus[NL-1:0]

CX_L1_SUBSTATES_ENABLE =1 &
CX_PIPE_VER >=1 (PIPE 4.3 or Later)
optional
mac_phy_rxelecidle_disable mac_phy_rxelecidle_disable
optional
mac_phy_txcommonmode_disable mac_phy_txcommonmode_disable
mac_phy_powerdown[3:0] mac_phy_powerdown[3:0]
optional
mac_phy_asyncpowerchangeack mac_phy_asyncpowerchangeack
phy_mac_phystatus[NL-1:0] phy_mac_phystatus[NL-1:0]
phy_clk_req_n

local_ref_clk_req_n

Platform Reference
cfg_l1_sub_en

Clock Generation
phy_ref_clk_req_n
clkreq_in_n
pm_sel_aux_clk
aux_clk_active

local_ref_clk_req_n
aux_clk

Pullup
muxd_aux_clk
aux_clk_active
Tristate Buffer
‘0’
aux_clk CLKREQ#
switching logic USP
clk divider/ 1
test mux DSP
DWC_pcie_clkrst_cpcie ‘1’ 0
device_type

aux_clk pipe_clk
* The aux_clk_active signals indicates that your external Example application specific logic to enable DSP drive hi-Z on CLKREQ#
clock logic has switched the aux_clk input from pipe_clk when L1 substates are disabled, such that the USP can assert/de-assert
to the platform auxiliary clock. The core does not request CLKREQ# freely as required in pre-L1 substates functionality.
the PHY to remove pipe_clk until you have switched Note: When L1 substates are enabled, the specification requires that the
aux_clk. This is used to give time to your application to DSP asserts CLKREQ# in the Recovery state when exiting L1. The example
switch aux_clk. When this signal is '0' in L1, the core stalls logic shown satisfies this requirement by ensuring that when the L1
the entry into the L1 substates and the de-assertion of substates are enabled, CLKREQ# is always asserted outside of the L1 link
mac_phy_pclkreq_n (clkreq_n). state (because mac_phy_pclkreq_n[1] will always be ‘0').

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2.3.5 Additional Information


For more information on power gating and associated clock removal, see “Advanced Power Management
and Power Domain Gating” on page 238.
For clock domain crossing (CDC) information, see “Advanced Information: Clock and Data Crossing
(CDC)” on page 941.

Figure 2-11 Schematic Overview of L2 Low Power Process


AUX_POWER

MAIN POWER

Power On Reset

AUX_CLK

RC Power Low Power Mode Power


Link Training Configuration Operation Link Training Config
PROCESS OFF Low Power Standby Low Power Sleep Power OFF ON

D-PM State D0 unini D0act D3 D0 _unini D0


Link State Detect Training L0 L1 L0 L2 Detect Training L0
PHY PM State P1 P0 P1 P0 P2 P1 P0

P ME_Tu rn _O F F Neg otia tion


sys_aux_pwr_det

core_clk Clocking Stop Clocking

muxd_aux_clk Clocking Clocking

PERST# (from RC)

WAKE# (from EP )

WakeUp
EP Power Low Power Mode
Link Training Configuration Operation Link Training Config
PROCESS OFF Low Power Standby Low Power Sleep

D-PM State D0unini D0act D3 D0unini D0


Link PM State Detect Training L0 L1 L0 L2 Detect Training L0
PHY PM State P1 P0 P1 P0 P2 P1 P0

sys_aux_pwr_det

core_clk Clocking Stop Clocking

muxd_aux_clk Clocking Clocking

When the controller transitions the PHY Powerdown state to P2 or P1.CPM, it simultaneously
Note requests the source of aux_clk to be switched to the slow clock. The clock switch design used
in the clock and reset generation module of the controller requires 2 cycles of the PHY clock to
perform the clock switch. It is assumed that the PHY clock runs for a minimum of 2 cycles after
the controller has transitioned PHY Powerdown to P2 or P1.CPM.

2.3.6 Clock Generation Module


The following circuits illustrate the clock generation for the controller, as used in the DWC_pcie_clkrst.v
module.

The design example in workspace/examples/DWC_pcie_clkrst.v has been functionally


Attention verified, but has not been explicitly targeted for verification metrics. However, it has been used
by Synopsys in the verification and regression environments for all controller configurations;
including verification of all power transitions for the controller.
Synopsys has only processed a small number of reference configurations of
DWC_pcie_clkrst.v through the Synthesis and Spyglass flows. Therefore, your configuration
of DWC_pcie_clkrst.v might not have been processed through these flows. The design
example is shipped as example code. For that reason, it is not qualified for tape-out release.
You must prove it in your SoC flow.

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Figure 2-12 Clock Generation Overview


PIPE?CLK

CORE?CLK?UG
PHY CLK_RST.v
mac_phy_rate CORE?CLK
2%&?#,+

PIPE?CLK
#LOCK $IVIDE
0 MUXD?AUX?CLK
&OR 'EN -UX
'EN 3PEED !58?#,+
1

AUX?CLK?G

En

0,, D

en_aux_clk_g

Conditions Required for muxd_aux_clk to Switch f(aux_clk_active)


From core_clk to AUX_CLK (CLK_REF Removal)
Link State Core Outputs
, PM?LINKST?IN?L Control Logic For
,33 PM?LINKST?IN?LSUB  Anti-Glitch Switching/Gating
of muxd_aux_clk and
, PM?LINKST?IN?L 
core_clk
2ESET PM?SEL?AUX?CLK 

APP?LTSSM?ENABLE

PM?EN?CORE?CLK
PM?SEL?AUX?CLK
LINK?REQ?RST?NOT
MAC?PHY?RATE
AUX?CLK?ACTIVE

EN?AUX?CLK?G
CONTROLLER
SYS?AUX?PWR?DET
Core Logic LBC/DBI/ELBI
;CORE?CLK= ;AUX?CLK?G=
;CORE?RST?N= ;CORE?RST?N= AUX?CLK?G
AUX?CLK
PERSTN CDM (sticky)
PMBC CORE?CLK
 APP?REQ?ENTR?L ;AUX?CLK?G=
;PIPE?CLK=
;STICKY?RST?N= CORE?CLK?UG
APP?REQ?EXIT?L ;CORE?CLK?UG=
 APP?READY?ENTR?L ;PIPE?MSGBUS?RST?N= PIPE?CLK
CDM (non-sticky)
PWR?RST?N ;PIPE?RST?N=
;AUX?CLK?G=
;CORE?RST?N=
 APPS?PM?XMT?PME ;NON?STICKY?RST?N=
outband_pwrup_cmd
PMC RxEI Squelch SLV?ACLK
;AUX?CLK= ;AUX?CLK= MSTR?ACLK
;PWR?RST?N= ;SQUELCH?RST?N=
DBI?ACLK
FREQ_STEP
PHY?MAC?PHYSTATUS ;PIPE?CLK=
;PIPE?RST?N=

CORE?CLK?UG
 4HESE SIGNALS DO NOT EXIST FOR 2# PORTS
 $30 CORE IGNORES THESE INPUTS

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Figure 2-13 Clock Switch and Gating Logic

AUX?CLK MUXD?AUX?CLK
CORE?CLK
#LOCK 'ATER
PM?SEL?AUX?CLK 'LITCH &REE #LOCK 3WITCH

%. '#,+ MUXD?AUX?CLK?G

#,+

EN?MUXD?AUX?CLK

CORE?CLK?UG

#LOCK 'ATER

PM?EN?CORE?CLK %. '#,+ CORE?CLK

#,+

#LOCK 'ATER

EN?RADM?CLK?G %. '#,+ RADM?CLK?G

#,+

Figure 2-13 describes the clock switch and gating logic which functions as follows:
■ The clock reset module implements a glitch free clock switch to permit the generation of the aux_clk
input to the controller. The switch is controlled by the output pm_sel_aux_clk, which selects the
aux_clk in certain low power states, and power on reset or fundamental reset.
■ The clock reset module implements architectural clock gating on core_clk, which permits the
disabling of core_clk in certain low power states as determined by the de-assertion of
pm_en_core_clk.
■ The clock for the RADM may be gated off when the signal en_radm_clk_g is de-asserted to allow
architectural clock gating in the receive path.
■ The clock muxd_aux_clk_g is a clock gated version of the muxd_aux_clk, which may be disabled
when power gating is supported in L1.2.
For more information on the clock switch logic and implemented architectural clock gating, see the RTL of
the clock and reset module.

Figure 2-14 Frequency Step Down Clock Divider

0IPE #LOCK $IVIDER

#LOCK 'ATER
MAC?PHY?RATE
PHY?MAC?PHYSTATUS 0IPE #LOCK
#8?0(9?." $IVIDE &ACTOR %. '#,+ CORE?CLK
#8?." ,OGIC
#,+

PCLK

Figure 2-14 describes the frequency step down clock divider logic which functions as follows:

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If the derived parameter CX_FREQ_STEP_DOWN_EN is defined, the core_clk frequency is slower than the
pipe_clk frequency, in this scenario it is necessary to generate the core_clk as a divided down version of
the pipe_clk.
■ The following factors contribute to the selection of the pipe_clk division factor used to generate the
core_clk:
❑ Number of symbols per cycle for the controller and the PHY
❑ The required link signaling rate as requested by the mac_phy_rate output of the controller
For example, if the PHY supports two symbols per pipe_clk cycle at GEN1 speed while the controller
supports four symbols per core_clk cycle at GEN1 speed, the divide by two is enabled.
■ A counter running on pclk is used to count the required number of pclk cycles, the output of this
counter in combination with the required division factor is used to enable the clock gating.
■ The clock divider uses a pulse suppression technique to generate the divided version of the pipe_clk.
This means that the generated core_clk do not have a 50% duty cycle.
For the detailed implementation of the divider circuit, see the RTL of the clock and reset generation module.
You could use a PLL/DPLL instead of the clock divider. This eases balancing of the core_clk ,
radm_clk_g, and pipe_clk clock trees as the PLL/DPLL can eliminate the divider insertion delay.

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2.4 Reset Requirements


This section covers reset generation for the controller, focusing on conventional PCIe. The following topics
are discussed:
■ “Overview”
■ “Implementing the PCIe Resets” on page 70
■ “Hot Reset” on page 72

2.4.1 Overview
The DWC_pcie_clkrst.v module generates the resets as per Table 2-8.
Note: Sticky is a PCIe term and means that the register retains its value during some reset sequences. There
are many reset inputs for the controller as describes in Table 2-8. All of these reset inputs are asserted on a
cold/fundamental/power-on reset. Not all these reset inputs are asserted during a hot reset (when link is
reset and most of controller logic is not reset but some small parts of the controller and some registers ARE
reset). Any registers that you want to remain un-reset during a hot reset must be wired to the
sticky_rst_n pin.

Table 2-8 Generation of Individual Reset Signals for each Reset Event

Cold Reset L1.2 Hot Reset


Clock Destinatio (Power On Warm Reset Power (Link-down)d
Reset Name Domain n Reset) (PERST#)a b Gatingc e

pwr_rst_n aux_clk Controller Yes

mstr_pwr_rst_nf mstr_aclk Controller Yes

slv_pwr_rst_ng slv_aclk Controller Yes

dbi_pwr_rst_nh dbi_aclk Controller Yes

sticky_rst_n aux_clk_g Controller Yes Yes Yesi

non_sticky_rst_n aux_clk_g Controller Yes Yes Yes Yes

core_clk /
core_rst_n Controller Yes Yes Yes Yes
radm_clk_g

pipe_rst_nj pipe_clk Controller Yes Yes Yes Yes

pipe_msgbus_rst_nk pipe_clk Controller Yes Yes Yes

phy_rst_n NA PHY Yes Yes Yes

phy_reg_clk_u
phy_reg_rst_nl Controller Yes Yes Yes
g

ret_sticky_rst_nm aux_clk_g Controller Yes Yes

ret_non_sticky_rst_n
d aux_clk_g Controller Yes Yes Yes

ret_core_rst_nd core_clk Controller Yes Yes Yes

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a. When CX_ENHANCED_PM_EN =1, the DWC_pcie_clkrst.v asserts all resets upon PERST# (perst_n) except
pwr_rst_n. PERST# is the trigger for L2 power removal.
b. On PERST# assertion, all of the controllers resets apart from pwr_rst_n are asserted synchronous to aux_clk. If a
register reset by core_rst_n, for example, fans in to a register reset by pwr_rst_n there is a reset domain crossing path.
The path through the preset or clear pin of the register being reset to the data pin of register which is not being reset
should be timed to ensure that there is no metastability on the register reset by pwr_rst_n.
c. CX_ENHANCED_PM_EN =1
d. TS protocol-based hot reset or link-down reset.
e. On link down reset the clock and reset module gates off the controller’s clocks when the resets are being asserted.
This is to ensure that the registers in the design are not being clocked when the resets are asynchronously asserted,
thereby avoiding any Reset Domain Crossing (RDC) issues.
f. This signal exists only when MSTR_CLK_DIFF_ENABLE ==1 && CX_ENHANCED_PM_EN ==1
g. This signal exists only when SLV_CLK_DIFF_ENABLE ==1 && CX_ENHANCED_PM_EN ==1
h. This signal exists only when DBISLV_CLK_DIFF_ENABLE ==1 && CX_ENHANCED_PM_EN ==1
i. See ret_sticky_rst_n.
j. pipe_rst_n and pipe_clk are not used when CX_FREQ_STEP_EN =0.
k. pipe_msgbus_rst_n is not used when CX_PIPE_VER <3.
l. Exists when CX_PHY_VIEWPORT_ENABLE =1.
m.Exists when CX_ENHANCED_PM_EN =1. ret_<resetname> is the reset signal for the logic that is retained in L1.2. In
L2, it is asserted identically to <resetname>. In L1.2, it is not asserted.

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Figure 2-15 PCIe Cold Reset Sequence


Application asserts Power-On Reset (power_up_rst_n)

VMAIN Power Good (perst_n =1)

- PHY in Reset
- DWC_pcie_clkrst.v asserts all PHY / Controller resets - Controller PMC in Reset
- Set app_ltssm_enable =0 for reprogramming before linkup. - Controller (other logic) in Reset

Application de-asserts Power-On reset (power_up_rst_n)

DWC_pcie_clkrst.v de-asserts controller’s PMC reset


(pwr_rst_n)

Controller de-asserts PHY and Controller reset request


(pm_req_phy_rst and pm_req_core_rst)
- PHY in Reset
- Controller PMC active
- Controller (other logic) in Reset
DWC_pcie_clkrst.v de-asserts PHY and Controller reset
(phy_rst_n and core_rst_n)

- PHY completes power- on - Controller de-asserts


sequence pm_sel_aux_clk - PHY Initializing
- PHY generates (stable) pclk - DWC_pcie_clkrst.v - Clocks Running
ungates core_clk

- Application keeps app_ltssm_enable =0 to disable link training - Reprogram Controller’s Registers [optional]
- Local application updates registers through DBI - Link Training Disabled

- Application sets app_ltssm_enable =1


- Link Establishment
- Controller starts link training

If you want to delay link reestablishment (after reset)


so that you can reprogram some registers through
DBI, you must set app_ltssm_enable =0 as
shown in the next diagram.

Unless app_ltssm_enable is de-asserted


immediately in Detect state, the controller will
continue to link up. If app_ltssm_enable is de-
asserted or the controller is reset when the controller
is out of the Detect state, the LTSSM moves
immediately back to the Detect state. This transition
is not defined in the PCIe Specification and might
cause a PIPE protocol violation.

If you want to delay link re-establishment (after reset) so that you can reprogram some registers through
DBI, you must set app_ltssm_enable =0 as shown in Figure 2-16.

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Figure 2-16 Delaying the Link Training After Cold Reset (Run a Simulation to Obtain Accurate Timing)
#
pipe_clk
core_clk
aux_clk

power_up_rst_n

pwr_rst_n

phy _rst_n

core_rst_n
non_sticky_rst_n
sticky_rst_n
To postpone Link Training;
set app_ltssm_enable =0
when core_rst_n -> 0;
app_ltssm_enable and release when finished programming

LTSSM Detect.Quiet Detect.Quiet Detect.Active

# In typical configurations (CX_FREQ_STEP_EN=0), this clock pin does not exist

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Figure 2-17 PCIe Cold Reset Sequence with PHY Initialization (CX_PHY_VIEWPORT_ENABLE =1)
- VMAIN Power Good (perst_n =1)
- Application asserts Power-On Reset (power_up_rst_n)

- DWC_pcie_clkrst.v asserts all PHY / controller resets


- Application generates stable aux_clk and phy_reg_clk
- Set app_ltssm_enable =0 for reprogramming before
linkup.
- Set app_hold_phy_rst = 1 for reprogramming the PHY
registers when CX_PHY_VIEWPORT_ENABLE =1
- Application directly controls and monitors PHY
signal(s) for initialization if necessary. (Refer to PHY
datasheet)

Application de-asserts Power-On Reset


(power_up_rst_n)

DWC_pcie_clkrst.v de-asserts controller’s PMC reset


(pwr_rst_n)

Controller de-asserts Controller Reset Request


(pm_req_core_rst)

DWC_pcie_clkrst.v de-asserts all controller resets

- Application keeps app_ltssm_enable =0 and


app_hold_phy_rst =1
- Application updates the PHY registers through DBI
when CX_PHY_VIEWPORT_ENABLE =1
- Application updates the MAC registers through DBI
- Application directly controls and monitors PHY
signal(s) for initialization if necessary. (Refer to PHY
datasheet)

- Application sets app_ltssm_enable =1 and


app_hold_phy_rst =0

Controller de-asserts PHY Reset Request


(pm_req_phy_rst)

DWC_pcie_clkrst.v de-asserts PHY reset (phy_rst_n)

- PHY completes power-on sequence


- PHY generates (stable) pclk

Controller de-asserts pm_sel_aux_clk

DWC_pcie_clkrst.v ungates core_clk

- Controller starts link training

For PHY Initialization information when CX_PHY_VIEWPORT_ENABLE =1, see Figure 3-2 on page 81.

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Figure 2-18 PHY Initialization After Cold Reset (CX_PHY_VIEWPORT_ENABLE =1)


pclk Stop Active

phy_reset (!power_up_rst_n)

PHY pipe_laneX_reset_n (phy_rst_n) Keep asserting during app_hold_phy_rst=1


Interface

phyX_cr_para_clk Stop Active Stop

phyX_cr_para_* Idle Active Stop

Read/Write access through PHY View Port regsiter

aux_clk/phy_reg_clk Active

power_up_rst_n

Application
app_hold_phy_rst
Logic

app_ltssm_enable

DBI Idle Active Idle

Updates PHY View Port register and the MAC registers

core_clk Stop Active

Active
muxd_aux_clk/aux_clk_g Active (aux_clk)
(pclk)
core_rst_n
non_sticky_rst_n
sticky_rst_n
clk/rst -
phy_reg_rst_n
Controller
Interface
pm_req_phy_rst

pm_req_core_rst
(sticky/non_sticky)

pm_sel_aux_clk

■ To obtain accurate timing of PHY initialization after cold reset you must run a simu-
Attention lation.
■ The controller's PHY Viewport (PRBI) to PHY registers can have high access
latency. If your application needs low latency to initialize Synopsys PHY registers or
SRAM, then PRBI should not be used. Instead, you should design a direct interface
to the PHY's SRAM or CR Bus. PRBI is recommended only for PHY debug.

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2.4.2 Implementing the PCIe Resets


For more information on descriptions of each I/O signal, see the appropriate section in “Signal Interfaces”
on page 278.

Figure 2-19 Reset Generation Overview

DWC_pcie_clkrst.v

Reset Generation Module ret_core_rst_n


ret_non_sticky_rst_n
PHY ret_sticky_rst_n
phy_rst_n pipe_rst_n
core_rst_n
non_sticky_rst_n
sticky_rst_n
pipe_msgbus_rst_n
pwr_rst_n
phy_reg_rst_n
button_rst_n
power_up_rst_n
test_rst_en
test_rst_n

link_req_rst_not
app_ltssm_enable

pm_req_phy_rst
pm_req_iso_vmain_to_vaux
pm_req_retention_rst
pm_req_core_rst
pm_req_non_sticky_rst
pm_req_sticky_rst
(Hot Reset)
From link_down event or
remote partner’s TS hot-
reset

Button
Reset
CONTROLLER
CORE
Core Logic LBC/DBI/ELBI
Vaux [aux_clk_g]
[core_clk]/
[radm_clk_g] [core_rst_n]
Power-On [core_rst_n]
Reset CDM (non-sticky)
(Cold Reset) PMBC [aux_clk_g]
[pipe_clk]/ [non_sticky_rst_n]
[core_clk_ug]
[pipe_msgbus_rst_n]/ CDM (sticky)
[pipe_rst_n]/ [aux_clk_g]
[core_rst_n] [sticky_rst_n]

PMC CDM (DMA)


perst_n
PERST# [aux_clk] [core_clk]
(Warm Reset) [pwr_rst_n] [core_rst_n]
(from board’s PERST# if Vaux present;
# FREQ_STEP PRC
otherwise from board’s power-on reset)
[pipe_clk] [phy_reg_clk_g]
[pipe_rst_n] [phy_reg_clk_ug]
RxEI Squelch [phy_reg_rst_n]
[aux_clk] [aux_clk_g]
[squelch_rst_n] [sticky_rst_n]

# pipe_rst_n and pipe_clk do not exist when CX_FREQ_STEP_EN =0


# pipe_msgbus_rst_n does not exist when CX_PIPE_VER < 3

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Figure 2-20 Reset Generation Module (Refer to RTL for Complete Design)
sync_reset
`1' pclk_link_down_rst_n test_rst_en
D Q D Q 0 sync_power_up_rst_n
muxd_aux_clk int_ret_core_rst_n
1 0 ret_core_rst_n
power_up_rst_n r r
0
dft_power_up_rst_n test_rst_n
1
test_rst_n
1
pm_req_retention_rst
test_rst_en sync_reset test_rst_en
`1'
D Q D Q 0 sync_button_rst_n int_non_sticky_rst_n ret_non_sticky_rst_n
muxd_aux_clk 0
1
button_rst_n r r test_rst_n
0 dft_button_rst_n 1
test_rst_n
1
pm_req_retention_rst
sync_reset test_rst_en
test_rst_en
`1'
D Q D Q 0 sync_perst_n int_sticky_rst_n
0 ret_sticky_rst_n
muxd_aux_clk
perst_n 1 test_rst_n
0 r r pm_req_retention_rst 1
dft_perst_n
test_rst_n
1
test_rst_en sync_reset test_rst_en
`1'
D Q D Q 0
int_mstr_axi_rstn
0 mstr_axi_resetn
mstr_axi_clk 1
r r test_rst_n
1

test_rst_en
sync_reset test_rst_en
`1'
D Q D Q 0
int_slv_axi_rstn
slv_axi_clk 0 slv_axi_resetn
1
r r test_rst_n
1

test_rst_en
sync_reset test_rst_en
`1'
D Q D Q 0
int_dbi_slv_rstn
dbi_axi_clk 0 dbi_axi_resetn
1
r r test_rst_n
1

test_rst_en
sync_reset test_rst_en
`1'
D Q D Q 0
int_pipe_rst_n
pipe_clk 0 pipe_rst_n
1
r r test_rst_n
1

test_rst_en

sync_reset test_rst_en
`1' pclk_link_down_rst_n
D Q D Q 0 sync_power_up_rst_n
muxd_aux_clk int_core_rst_n
1 0 core_rst_n
power_up_rst_n r r
0
dft_power_up_rst_n test_rst_n
1
test_rst_n
1
pm_req_core_rst
test_rst_en
test_rst_en sync_reset
`1'
D Q D Q 0 sync_button_rst_n
int_non_sticky_rst_n non_sticky_rst_n
muxd_aux_clk 0
1
button_rst_n r r test_rst_n
0 1
dft_button_rst_n
test_rst_n
1 test_rst_en
pm_req_non_sticky_rst

test_rst_en
int_sticky_rst_n
0 sticky_rst_n
test_rst_n
1
pm_req_sticky_rst

test_rst_en

int_pwr_rst_n
0 pwr_rst_n
test_rst_n
1'b1 0 1
link_down_rst_n
D Q
link_req_rst_not
1
app_ltssm_enable core_clk s

core_rst_n sync_generic
D Q D Q
pclk_link_down_rst_n
muxd_aux_clk r r
sync_generic

D Q D Q D Q D Q D Q 0
test_rst_n
auxclk s auxclk s s auxclk s auxclk s 1

dft_power_up_rst_n power_up_rst_n test_rst_en


pwr_rst_n
auxclk_link_down_rst_n
test_rst_en
sync_reset
`1'
D Q D Q 0 int_pipe_msg bus_rst_n
test_rst_en pipe_msgbus_rst_n
0
1
power_up_rst_n int_phy_rst_n pipe_clk r r test_rst_n
0 1
button_rst_n test_rst_n
1
test_rst_en
phy_rst_n
pm_req_phy_rst

Note: # pipe_rst_n and pipe_clk do not exist when CX_FREQ_STEP_EN =0


# pipe_msgbus_rst_n does not exist when CX_PIPE_VER < 3

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2.4.3 Hot Reset


A downstream port (DSP) can hot reset an upstream port (USP) by sending two consecutive TS1 ordered
sets with the hot reset bit asserted, or by pulsing the app_init_rst input. Eventually, the DSP and USP
assert link_req_rst_not to request external logic to reset them. Alternatively, during normal operation,
the link might fail and go down. After this link-down event, the controller requests the
DWC_pcie_clkrst.v module to hot-reset the controller. There is no difference in the handling of a
link-down reset or a hot reset; the controller asserts the link_req_rst_not output requesting the
DWC_pcie_clkrst.v module to reset the controller.
To prevent your application from hanging when the controller is reset, the controller must cleanly terminate
all transactions that are still in-progress.

Figure 2-21 Delaying the Controller Hot Reset (Run a Simulation to Obtain Accurate Timing)
pipe _clk
core_clk
aux _clk Software asserts the Secondary Software de-asserts the
Bus Reset (SBR) Secondary Bus Reset
BRIDGE_CTRL_PIN_LINE_REG.SBR
(Secondary Bus Reset)

Early warning that reset is imminent.


You can use this to create an interrupt to your application or software; informing it
smlh_req_rst_not that the link has gone down and that it should stop data transmission.

link_req_rst_not

non _sticky_rst_n

core_rst_n
slv_aresetn
mstr_aresetn

sticky_rst_n
pwr_rst_n To postpone ‘Reset Mode’; set app_ltssm_enable=0 immediately (combinatorially) when smlh_req_rst_not ->0.
The bridge enters ‘Reset Mode’ when it has finished ‘Flushing Mode’ and app _ltssm_enable=1.

app_ltssm_enable

slv_*ready

MODE Normal Mode Flushing Mode (variable duration depending on number of outstanding transactions ) Reset Mode Normal mode

LTSSM L0 Recovery Hot Reset Detect L0

If you want to delay link re-establishment (after reset) so that you can reprogram some registers through
DBI, you must set app_ltssm_enable =0 immediately after core_rst_n as shown in Figure 2-22. Also
applies to non-AXI configurations.

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Figure 2-22 Delaying the Link Training After Hot Reset (Run a Simulation to Obtain Accurate Timing)
pipe_clk
core_clk
aux_clk

link_req _rst_not

non_sticky_rst_n

core_rst_n
slv_aresetn
mstr_aresetn

phy _rst_n

sticky_rst_n
pwr_rst_n To postpone ‘Link Training;
set app_ltssm_enable =0 immediately
(combinatorially)
app_ltssm _enable after core_rst_n ->0.

LTSSM Detect.Quiet Pre.Detect.Quiet Detect.Quiet Detect.Active

Unless app_ltssm_enable is de-asserted immediately in Detect state, the controller continues to link up. If
app_ltssm_enable is de-asserted or the controller is reset when the controller is out of the Detect state, the
LTSSM moves immediately back to the Detect state. This transition is not defined in the PCIe Specification
and might cause a PIPE protocol violation.

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Receive Queues PCI Express SW Controller Databook

2.5 Receive Queues


This section covers the following buffering topics:
■ “Receive Queue Architecture”
■ “Configuring Your Queues” on page 76

2.5.1 Receive Queue Architecture


The receive queue uses a segmented-buffer architecture where multiple logical FIFOs are implemented in a
single buffer. For 32, 64, and 128-bit configurations, there is one header RAM and one data RAM regardless
of the number of VCs. For 256-bit configurations, there are two half-sized header RAMs and two half-sized
data RAMs; the controller can process up to two TLPs in a single clock cycle. For 512-bit configurations,
there are one header RAM and four data RAMs. The queue does not perform reassembly of split
completions.

Figure 2-23 Queue Architecture (512-bit Controller has Formation/Serialization Queue Before Receive Queue)

BYP‡

Receive Queues
CPL F I F O Output Pipe
(3-4 cycles )
TRGT1‡
P F I F O /CDM
/ELBI

NP F I F O trgt1_radm_halt

Order FIFO Order trgt1_radm_pkt_halt[2:0]


Controller radm_grant_tlp_type[2:0]
(records sequence in
which TLPs are received ) Controls the unloading of each receive queue .
Ordering algorithm is programmable :
1. PCIe ordering rules (default )
2. Strict Arbitration


CDM and ELBI are also possible destinations in an upstream port .

Queue Modes
The three possible queue modes for posted, non-posted and completion TLPs are described in Figure 2-9.
Table 2-9 shows the division of functionality for these actions between the controller and your application

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Table 2-9 Comparison of Queue Modes

RADM_<P|NP|CPL>_QMODE_VCn

0x1 0x2 0x4


a
Store-and-Forward (S/F) Cut-Through (C/T) Bypass (B/P)

Controller stores none


Controller stores all of the Controller stores some
Buffering Action of the TLP in a buffer;
TLP in the buffer of the TLP in the buffer
there is no buffer

When Controller Forwards


TLP to Your Application At end Immediately Immediately
(Affects Latency)

Application Halts TLP


Yes Yes No
Deliveryb

Your application.
Credit Manager Controller Controller Not necessary if infinite
credits advertised.

Ordering Rules Obeyed Obeyed Violatedc

Controller forwards TLP to Controller forwards TLP Controller forwards TLP


your application logic after to your application logic to your application logic
Error Checking
checking is complete and before checking is before checking is
error-free complete complete

Corrupt TLP Discarded By Controllerd Your applicationd Your applicatione

a. Cut-through mode decays into store-and-forward mode when the queues become full; if there is more than one TLP in
the buffer when the queue is in cut-through mode, the TLPs being received are treated the same as store-and-forward
mode. Only the first TLP in the queue behaves in cut-through mode.
b. For more information, see “TRGT1 Packet Grant and Halt” on page 291.
c. “CPL must not pass a previously-issued P” rule is violated, which is only a problem when you have a real “Producer-
Consumer” scenario. For more information, see “PCIe Ordering Rules” on page 969.
d. This is the default operation. You can optionally configure the controller to forward the corrupt TLP (not recommended).
For more information, see “Advanced Information: Advanced Error Handling for Received TLPs” on page 981.
e. When the controller signals an error or abort indication to your application at the end of the TLP, you must discard that
TLP. For more information, see “Advanced Information: Advanced Error Handling for Received TLPs” on page 981.

The following tables show which queue modes can be used in which controller configurations. You can set
the queue mode independently for each VC.

Table 2-10 Supported Queue Modes for 32-bit, 64-bit, and 128-bit Datapath (Default is Marked D)

S/F C/T B/P

Posted D Y Ya

Non-Postedb D Y Y

Completion D Y Y

a. In this configuration you cannot send posted requests to the ELBI interface; that is, you cannot memory map the
port logic registers.

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b. You cannot put the non-posted receive queue in bypass mode because the controller needs to manage credits for
both internally consumed non-posted TLPs (for example CFG requests to internal registers in the CDM), as well
as credit returns that are stalled while the controller is waiting to return completions to the remote link partner.

Table 2-11 Supported Queue Modes for 256-bit Datapath (Default is Marked D)

S/F C/T B/P

Posted D Y -

Non-Posted D Y -

Completion D Y -

2.5.2 Configuring Your Queues


The coreConsultant tool automatically calculates the native controller’s receive queue buffer sizes.

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Figure 2-24 Guide to Configuring your Receive Queues


Configure Main Parameters
(CX_NL, CX_MAX_TAG, CX_MAX_MTU, CX_FREQ, CX_GEN2_MODE, CX_GEN3_MODE, CX_PHY_RX_DELAY_PHY, CX_PHY_TX_DELAY_PHY;
For M-PCIe , use: CM_TXNL_GUI, CM_RXNL_GUI, CX_MAX_TAG, CX_MAX_MTU, CM_FREQ, CM_GEAR2_MODE, CM_GEAR3_MODE, CM_PHY_RX_DELAY_PHY, CM_PHY_TX_DELAY_PHY)

Use Default Queue Modes


Posted (P) Non-posted (NP) Completion (CPL)

S/F S/F

Yes 256-bit core or


need to obey “CPL must not No
S/F a
B/P
pass P” rule

No buffering.
Yes Assumption is that your
Infinite
application logic can always
Credits
accept all of the the read data
that it requested.

No Auto-size No (not recommended)


Buffer

Yes WARNING!
Internal and external backpressure
might cause overflow. See Note (c)

Core Auto-Calculates
For configurations with a 256-bit core
Credits and Buffer datapath, there is an additional
Sizes (from Credits) possibility of queue overflow even when
your application does not halt the queue.
This is caused by the fact that the
internal pop rate of very small
Set CX_APP_RD_REQ_SIZE completions from the receive queue is
= your application’s max less than the push (arrival) rate from the
individual read request size PCIe wire.

WARNING!
When a CPL is blocked by a P, then
Core Auto-Calculates there is a risk that the queue will
Buffer Sizes – see overflow.

Note (b)

Estimate and set buffer sizes.


RADM_CPLQ_DDP_VC0
RADM_CPLQ_HDP_VC0

Synopsys cannot offer guidance


.

Generate RAM size report

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■ (a) For more information, see “PCIe Ordering Rules” on page 969.
Note
■ (b) Size = (CX_MAX_TAG + 1) * (CX_APP_RD_REQ_SIZE + 1)
■ (c) A CPL buffer that advertises infinite credits and that is configured in
store-and-forward or cut-through modes, is not protected from overflow by the
"flow-control: credit-return" protocol. If you do not size the buffer to accept all of the
data that you have requested, the queue might overflow when the P queue is blocked
and the controller halts delivery of CPLs to your application when it is enforcing the
CPL must not pass P ordering rule. If you do not have a local Producer-Consumer
scenario, you can set the RO bit of the outbound NP requests to 1 so that CPL can
overtake P requests in the queue. For more information, see “PCIe Ordering Rules”
on page 969.
■ In the unlikely event that the buffer RAMs overflow, the controller asserts the
radm_qoverflow output. If overflow is caused by a lack of credits for incoming TLPs
(causing a TLP to be discarded), the controller sets the Receiver Overflow bit in the
AER Status Register.

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3
Controller Operations

This section describes the operations of the PCI Express controller. The topics in this section are:
■ “Initialization” on page 80
■ “Link Establishment” on page 83
■ “Transmit TLP Processing” on page 87
■ “Receive TLP Processing” on page 94
■ “Register Module, LBC, and DBI” on page 99
■ “Reliability, Availability, and Serviceability (RAS)” on page 124
■ “Messages” on page 152
■ “Interrupts” on page 170
■ “Flow Control” on page 176
■ “Internal Address Translation Unit (iATU)” on page 178
■ “Gen2/3/4/5 Speed Modes” on page 206
■ “Power Management” on page 213
■ “Completion Timeout Ranges” on page 254
■ “Crosslink” on page 255
■ “TLP Processing Hints” on page 256
■ “Atomic Operations (AtomicOps)” on page 257
■ “TLP Prefix” on page 259
■ “Separate Refclk Independent SSC (SRIS)” on page 260
■ “Readiness Notifications (RN)” on page 261
■ “Precision Time Measurement (PTM)” on page 263
■ “Access Control Services (ACS)” on page 271
■ “Completion Queue Management” on page 273

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3.1 Initialization
Immediately upon powerup the SW controller goes into either upstream or downstream port mode,
depending on the state of the device_type input. If you have enabled crosslink (CX_CROSSLINK_ENABLE
=1), then the determination of the device type is different.

Figure 3-1 PCIe Initialization Steps


Application sets app_ltssm_enable = 0 to disable link training
Application sets app_hold_phy_rst = 1 for reprogramming the PHY registers when
CX_PHY_VIEWPORT_ENABLE =1

LTSSM
Detect

DBI Programming
Your local application can reprogram the controller’s sticky registers before link
training

Application sets app_ltssm_enable 1 = 1 LTSSM


Controller starts link training 2 Polling

RC application confirms the link is up by sampling


LTSSM
smlh_link_up and rdlh_link_up
Configuration

Downstream Device Enumeration by Root Complex


1. Read the configuration space of the downstream devices.
2. Program device capabilities.
3. Program the base and limit registers of switch ports to reflect
the BAR range of the devices enumerated downstream.
4. Program the BARs of endpoints.

LTSSM
L0

Host software writes to Bus Master Enable (BME), Memory


Space Enable (MSE), and I/O Space Enable (ISE) bits3,4

Start Application Traffic Generation

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1. Your application can use the app_req_retry_en/app_pf_req_retry_en input to


Note program the controller (through the DBI) after the link is up. When app_req_retry_en
=1/app_pf_req_retry_en =1, the controller completes incoming CFG requests with a
configuration request retry status (CRS). Other incoming requests complete normally.Note:
The PCI Express Base Specification, Revision 4.0, Version 1.0 has requirements about
when CRS responses are permitted, your application must take these into account when
asserting app_req_retry_en/app_pf_req_retry_en.
2. For multiple VC configurations, only VC0 should be enabled before the link is up. Other VCs
should be enabled after rdlh_link_up is asserted.
3. The application logic must not generate any MEM or I/O requests until the host software has
enabled the BME. The Synopsys controller does not check this bit before transmitting
requests. Therefore, your application logic must monitor the status of the BME on the
cfg_bus_master_en output (or read it over the DBI).
4. RC application logic must not generate any MEM or I/O requests until the host has enabled
the MSE and ISE bits. The RC controller does not check these bits before transmitting
requests. Therefore, your application should monitor the status of the MSE on the
cfg_mem_space_enable output. There is no corresponding ISE output, so the RC applica-
tion must be aware of when the host software writes to this bit. Your application could also
read these bits over the DBI.

Figure 3-2 PHY Initialization (CX_PHY_VIEWPORT_ENABLE =1)


PHY DWC_pcie_clkrst.v Controller

phy_reg_clk
CLK phy_reg_clk_g
Gating
core_clk
auxclk
aux_clk/
Mux

pclk aux_clk_g

pm_sel_aux_clk

pm_req_phy_rst
!power_up_rst_n
pm_req_core_rst/pm_req_sticky_rst/pm_req_non_sticky_rst
phy_reset phy_rst_n
pipe_laneX_reset_n Reset Logic
phy_reg_rst_n
Reset core_rst_n
Logic sticky_rst_n
non_sticky_rst_n

cr_para_clk Configuration
Register
Control Register Bus Interface PHY View Port
Register
Control/Status signals for

app_ltssm_enable

app_hold_phy_rst
PHY Initialization

DBI
power_up_rst_n
phy_reg_clk

auxclk

Application Logic

The controller's PHY Viewport (PRBI) to PHY registers can have high access latency. If your
Attention application needs low latency to initialize Synopsys PHY registers or SRAM, then PRBI should
not be used. Instead, you should design a direct interface to the PHY's SRAM or CR Bus.
PRBI is recommended only for PHY debug.

For more information on cold reset sequence with PHY initialization see Figure 2-17 on page 68. For more
information on PHY initialization after cold reset, see Figure 2-18 on page 69.

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3.1.1 Bus and Device Number


For downstream ports, you must configure the bus and device number using the app_bus_num and
app_dev_num input signals to set the bus and device number respectively, in the Requester ID. The
PL_APP_BUS_DEV_NUM_STATUS register reflects the value of the bus and device number configured by
your application.
For upstream ports, the controller captures the bus and device number from the configuration write
requests completed by the function.

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PCI Express SW Controller Databook Link Establishment

3.2 Link Establishment


The controller implements the LTSSM function according to the PCI Express Base Specification, Revision 4.0,
Version 1.0. When you have unused lanes in your system, you must tie them off using the hardware and
software procedures outlined in “Advanced Information: How to Tie Off Unused Lanes” on page 978. The
controller supports link widths of x1, x2, x4, x8, and x16. It does not support x12.

3.2.1 Lane Resizing


Initially, the controller tries to linkup at maximum width; you can restrict the maximum width as follows:
1. Program the LINK_CAPABLE field of PORT_LINK_CTRL_OFF.
2. Program the NUM_OF_LANES field of GEN2_CTRL.
To conserve power, your PHY should ignore any signaling on the non-operational lanes. The controller
supports the PIPE turn off feature by using the TxElecIdle and TxCompliance signals only when the link
resizing happens through detect state, and not by the Upconfigure capability.
The link partners can change the link width after the link is up. Resizing1 options are shown in Table 3-1.

Table 3-1 Link Resizing Options

Remote Partner Initiates Software Initiates Locallya

Link Remains Up Link Remains Up

L0 -> Recovery -> Configuration L0 -> Recovery -> Configuration

Upsizingb Yes Yes

Downsizing Yesc Yes

a. Previous versions of the Databook described a method of link resizing by taking the link down, and transitioning the LTSMM
from L0 -> Recovery -> Loopback -> Detect. The controller still supports that method for legacy designs (see previous version
of databook for more information), but new designs should use the method described here.
b. Called UpConfigure in the PCI Express Specification.
c. If the lanes are reversed, your application must manually flip the lanes to achieve downsizing for some configurations. For more
information, see “Link Down-sizing with Non-reversed/Reversed Lanes; and Wide/Narrow Ports” on page 921.
The following steps show how you can initiate link resizing:
1. Ensure the link is in the L0 LTSSM state.
2. Program the TARGET_LINK_WIDTH[5:0] field of the MULTI_LANE_CONTROL_OFF register.
3. Program the DIRECT_LINK_WIDTH_CHANGE2 field of the MULTI_LANE_CONTROL_OFF register.
It is assumed that the PCIE_CAP_HW_AUTO_WIDTH_DISABLE field in the
LINK_CONTROL_LINK_STATUS_REG register is 0.

1. Resizing (up or down) only occurs if both link partners advertised the Upconfigure Capability bit. In cases of link reliability,
the PCIe specification permits the remote partner to initiate downsizing regardless of the value of this bit. You must set the
UPCONFIGURE_SUPPORT field in MULTI_LANE_CONTROL_OFF so that the controller advertises 1 in the Upconfigure
Capability bit of the TS2 OS. Default for this field comes from DEFAULT_UPCONFIGURE_SUPPORT parameter.
2. The controller clears the contents of this register after it has accepted the request.

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If your system has reversed lanes in Gen3, Gen4, or Gen5 mode, then you should perform
Note
upsizing at Gen1 or Gen2 speed only. Otherwise, there is a risk of link-down caused by LFSR
mismatching.
For Gen3 and above, the controller does not send the first EIEOS before the first TS1 OS in
Configuration.Linkwidth.Start state for the upconfiguring lanes because of the requirement
that TxDataValid and TxElecidle signals must be aligned with other active lanes. After the first
EIEOS, the upconfiguring lanes send all Ordered Sets including EIEOS, in the same manner
as the other active lanes.

3.2.2 Lane Reversal and Flipping


The controller supports lane reversal and lane flipping. Depending on the configuration of the link partners
and the topology of the link between them, the controller attempts to reverse and/or flip lanes to form a link
in any of the following scenarios:
■ The lanes are reversed by the physical layout of the PCIe link or chip package pinning.
■ When connecting a narrower link partner into upper lanes of a wider controller.
■ A lane is non-operational (broken).
A lane is said to be non-operational if it cannot be detected in Detect LTSSM state or it cannot receive
in Polling LTSSM state. This might be caused by any of (i) break on PCB (ii) electrical fault in trans-
mitter (iii) electrical fault in receiver.
Lane auto flip occurs in Detect and is useful to connect physical lane CX_NL-1 (or CX_NL/2-1 or
CX_NL/4-1) to logical Lane0 of the controller to form a link when physical Lane0 cannot be detected.
Lane auto reverse occurs in Configuration and is useful to form a link when logical Lane0 receives TS
Ordered Sets from the link partner with the Lane Number field different from ‘0’.

To enable lane auto flip and reverse support:


Note
■ You must set configuration parameters CX_LANE_FLIP_CTRL_EN =1 and CX_AU-
TO_LANE_FLIP_CTRL_EN =1
■ You must set GEN2_CTRL_OFF register fields AUTO_LANE_FLIP_CTRL_EN =1 and PRE_-
DET_LANE =0

Figure 3-3 to 3-5 show the muxing logic implemented in the controller as a function of parameters
CX_LANE_FLIP_CTRL_EN and CX_AUTO_LANE_FLIP_CTRL_EN.

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Figure 3-3 Muxing Logic when CX_LANE_FLIP_CTRL_EN =1 and CX_AUTO_LANE_FLIP_CTRL_EN =1


GEN2_CTRL_OFF Register fields
AUTO_LANE_FLIP_CTRL_EN = 1
PRE_DET_LANE = 0 CX_LANE_FLIP_CTRL_EN = 1
CX_AUTO_LANE_FLIP_CTRL_EN = 1

Auto Reverse Auto Flip Manual Flip


LTSSM LTSSM rx_lane_flip _en =1 /
(Config) (Detect) tx_lane_flip _en =1

Reversal Flip Mux


7 7
Mux 3

6 6
2

5 5
1

4 4 Logical Lane0
0

Remote Link
Partner
3 3

2 2

1 1

0 0 Physical Lane0
Logical Lane 0

Figure 3-4 Muxing Logic when CX_LANE_FLIP_CTRL_EN =1 and CX_AUTO_LANE_FLIP_CTRL_EN =0

CX_LANE_FLIP_CTRL_EN = 1
CX_AUTO_LANE_FLIP_CTRL_EN = 0

Manual Flip
rx_lane_flip _en =1 /
tx_lane_flip _en =1

Flip Mux
7
0

4 Logical Lane 0

Remote Link
Partner

Logical Lane 0 0 Physical Lane0

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Figure 3-5 Muxing Logic when CX_LANE_FLIP_CTRL_EN =0

CX_LANE_FLIP_CTRL_EN = 0

Logical Lane0
0
Physical Lane0
Remote Link
Partner

For more information, see “Advanced Information: Lane Reversal and Broken Lanes” on page 919.

You can also inspect the VTB test cases at


Hint <workspace>/doc/html/vtb/testenv/index.html for programming examples. For more
information on VTB, see the “Integrating the Controller and VIP using VTB” section in the
“Integrating the Controller with the PHY or Application RTL or Verification IP” chapter of the
User Guide.

Force Lane Flip


When CX_FORCE_LANE_FLIP_EN =1 and GEN2_CTRL_OFF.FORCE_LANE_FLIP =1 you can forcefully
connect the physical lane specified in GEN2_CTRL_OFF.LANE_UNDER_TEST to logical Lane0 of the controller
after reset. Only x1 link can be formed using the force lane flip feature. This feature overrides all the other
lane flip and reversal mechanisms.
The following conditions must be met for force lane flip to be effective:
■ Parameters CX_LANE_FLIP_CTRL_EN and CX_AUTO_LANE_FLIP_CTRL_EN must be ‘true’
■ PORT_LINK_CTRL_OFF.LINK_CAPABLE must be set to ‘1’

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PCI Express SW Controller Databook Transmit TLP Processing

3.3 Transmit TLP Processing


The following section describe the flow of transmit TLPs through the controller.
■ “Transmit TLP Arbitration”
■ “ACK/NAK Scheduling” on page 90
■ “Transmit Replay” on page 91
■ “Tx Interface Progression Detection (CX_INTERFACE_TIMER_EN =1)” on page 92

■ The controller does not check the TLP for errors.


Note
■ The native PCIe controller does not check that the TLP payload size is less than the
Maximum Payload Size limit.
■ The native PCIe controller does not check that the TLP payload size is less than CX_MAX-
_MTU limit. Exceeding this limit overflows the retry buffer, resulting in data corruption.

3.3.1 Transmit TLP Arbitration


TLPs and DLLPs have equal priorities during transmit arbitration as shown in Figure 3-6. The priority of
TLP types and DLLP types are shown in Table 3-2 and Table 3-3, respectively.

Figure 3-6 Transmit TLP/DLLP Arbitration

DLLP Arbiter TLP Arbiter


CPL of any DLLP In Progress 1

NAK 2 1 CPL of any TLP In Progress

High Priority ACK 3 2 Retry

Flow Control DLLPs 4 3 Internal CPL

Vendor Specific Msg DLLPs 5 4 TLP on TX interface

Power Management DLLPs 6


DLLP

TLP

Round Robin
Arbiter

TLP DLLP TLP DLLP TLP TLP

No DLLP pending

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Table 3-2 TLP Arbitration Priority (1 = Highest, 4 = Lowest)

Priority TLP Type

1 Completion of any TLP currently in progress

2 Retry buffer retransmissions

TLPs from the transaction layer (in the following order of priority):
■ Messages generated by the controller (including by your application through the MSI interface)
■ Upstream ports: Completions generated by the controller (including memory or I/O mapped appli-
3 cation register space) for Type 0 configuration read and write requests, or responses to error condi-
tions (unsupported requests)
■ Downstream ports: Completions generated by the controller for unsupported requests or completer
aborts

4 TLPs on the transmit client interface (XALI0/1/2)

Table 3-3 DLLP Arbitration Priority (1= Highest, 6 = Lowest)

Priority DLLP Type

1 Completion of any DLLP currently in progress

2 NAK DLLP

3 High Priority ACK DLLP

4 Flow Control DLLP

5 Vendor Specific DLLP

6 Power management or any other Low Priority DLLP

3.3.1.1 Selecting Transmit Client Arbitration Scheme

All transmit client interfaces XALI0/1/2 are served using one of the three arbitration schemes when credit
is available, regardless of the type of transaction. You can change the arbitration scheme using the
CX_XADM_ARB_MODE configuration parameter when CX_NVC >1.

■ 0: VC Based. Provides a VC-based programmable weighted round robin arbitration (WRR) using two
different arbitration methods for the two groups of VCs:
❑ Strict Priority for the High-Priority VC (HPVC) group
❑ RR or WRR for the Low-Priority VC (LPVC) group
Between the two groups of VCs, arbitration is as follows:
❑ The HPVC group is always the highest priority. Within the HPVC group, priority order is by VC
ID. The highest VC ID has the highest priority. Ties within the HPVC are resolved by client-based
Strict Priority arbitration; XALI0 has lowest, XALI1 higher, and XALI2 (if implemented) highest
priority.

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❑ The LPVC group is of lower priority than the HPVC group. Within the LPVC group, priority is
determined by RR or WRR arbitration as described later. Ties within the LPVC group are resolved
by client-based RR arbitration.
For more information, see “Advanced Information: VC-Based Arbitration” on page 948.
■ 1: Round Robin (RR). Provides round robin arbitration between the three transmit clients. This is the
default method.
■ 2: Strict Priority. Provides strict priority between the three transmit clients. XALI0 is lowest, XALI1 is
higher, XALI2 (if implemented) is highest.

3.3.1.2 Effects of Flow Control Credits on Transmit Client Arbitration

The controller checks that enough flow control (FC) credits are available in the remote device for the specific
type of transaction (posted, non-posted, completion) before allowing a transmission of a TLP. TLPs that
passed the credit check are arbitrated according to the supported arbitration method. Internally generated
completions and messages are also gated by the arbitration logic, though at highest priority, and must also
pass the FC credit test before they are accepted for transmission.
For example when using the RR scheme, when a posted (P) transaction is presented onto XALI1 followed by
a completion (CPL) on XALI0, and when credits permit, then the P transaction is transmitted onto the wire
before the CPL. When the credit is not available then the CPL on XALI0 can pass the P transaction on XALI1
and be sent onto the wire. However, any non-posted (NP) or CPL TLPs on XALI1 (behind the blocked P) are
blocked by the halted P. It is the responsibility of your application to make appropriate use of the three
interfaces. There is no guarantee that order is preserved among client interfaces.
When your application is using a single transmit client interface for more than one TLP type (for example,
posted and non-posted), and the current request (for example, a posted request) is being blocked due to lack
of available FC credits, then that client interface is effectively blocked from sending other requests (for
example, non-posted) even though credits might be available for that type. To avoid this situation, your
application can use different transmit client interfaces for different request types (for example, XALI0 for
posted requests, XALI1 for non-posted requests, and XALI2 for completions). Another way your application
can avoid this situation is to monitor the current FC credit availability on the xadm_*_cdts outputs from
the controller and only generate requests for which FC credits are available.
When using xadm_*_cdts to monitor credit availability, your application must consider that it is possible
that the controller might generate a message or completion TLP (which would change the number of credits
available), between the time your application samples xadm_*_cdts and when your application generates
the request. To avoid this scenario, your application can use the Application Credit Control feature, for
more information, see “Application Credit Control” on page 89.
For more information on flow control, see “Flow Control” on page 176. For more information on TLP
ordering, see “Advanced Information: Advanced Ordering Information” on page 968. For more information
on how to select the client interfaces, see the “Configuration Guide” appendix in the User Guide.

3.3.1.3 Application Credit Control

The optional application credit control feature (APP_CREDIT_CTRL =1) allows your application to monitor
and control the credit expenditure. In addition to a reporting interface for all credit consumption, an
interface is provided to grant your application control over transmission and credit consumption of internal
controller generated messages and completions. Only when your application grants the credits for
internally generated messages and completions, these TLPs enter arbitration. Using this feature your

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ACK/NAK Scheduling PCI Express SW Controller Databook

application can maintain an accurate credit count and define packet ordering to achieve the best
performance when using a single transmit client interface for more than one TLP type (for example, posted
and non-posted).
The credit control handshake between the controller and your application, as depicted in Figure 3-7, is as
follows:
■ Credit Request (controller => application)
The controller requests your application to grant credits for internally generated messages/comple-
tions by asserting the output signals xadm_crd_*_h_req/xadm_crd_*_d_req/xadm_crd_*_vc1.
■ Credit Grant (controller <= application)
Only when your application grants the credits by asserting app_crd_ms-
g_grant/app_crd_cpl_grant signals the internally generated messages/completions TLPs enter
arbitration, and are immediately transmitted by the controller.
■ Credit Consumption (controller => application)
The output signal xadm_*_consumed indicates that the granted credit has been consumed by the
controller.

Figure 3-7 Credit Control Handshake Between the Controller and Your Application
CLK

XADM?CRD? ?H?REQ

XADM?CRD? ?D?REQ

XADM?CRD? ?VC;=

XADM?CRD? ?CONSUMED

APP?CRD? ?GRANT

3.3.2 ACK/NAK Scheduling


Figure 3-8 shows how you can reprogram the controller to influence the sending of ACK and NAK DLLPs.
When the link is idle, the controller sends an ACK DLLP every time it receives a good TLP. For a typical
system, you do not have to modify the defaults, unless the remote device is executing unexpected replays.

1. Indicates the VC for the message/completion when multiple VCs exist.

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Figure 3-8 Ack Frequency and Latency Timers Operation (Representative)

ACK ACK NAK


TX Processing Datapath Sent Request Request

SET
D Q
LANE_SKEW_OFF register Enable ACK/NAK
ACK_NAK_DISABLE field request
CLR Q ACK Latency Timer
SET
reset
D Q
timer
TIMER_CTRL_MAX_FUNC_NUM_OFF register x64 + limit
TIMER_MOD_ACK_NAK field limit
CLR Q
increment reached
SET
D Q
ACK_LATENCY_TIMER_OFF register
ROUND_TRIP_LATENCY_TIME_LIMIT field
(automatically set; see register description) CLR Q
ACK Fr equency Counter
High Priority
SET ACK_FREQ counter ACK Request
D Q
limit
limit ACK_FREQ
ACK_F_ASPM_CTRL_OFF register reached
ACK_FREQ field TLPs received
CLR Q != 0 enable
increment
Low Priority NAK
ACK Request Request

Good TLP Good TLP Bad TLP


RX Processing Datapath received received received

When a low priority ACK request is scheduled for transmission to the remote link partner, the
Note
controller waits until either the ACK Latency Timer or the ACK Frequency Counter expires, then
converts the low priority ACK request to a high priority ACK request, and schedules it for
transmission to the remote link partner.

3.3.3 Transmit Replay


You can modify the time-out value of the replay buffer as shown in Figure 3-8. For a typical system, you do
not have to modify the default settings, unless the remote device is executing unexpected replays.

Figure 3-9 Replay Buffer and Time (Representative)

TX Processing Path
TX
Replay
Buffer
RAM

SET
Replay Timer
D Q
TIMER_CTRL_MAX_FUNC_NUM_OFF register x64 timer
TIMER_MOD_REPLAY_TIMER field
+ limit
CLR Q
SET
D Q
ACK_LATENCY_TIMER_OFF register reset limit
REPLAY_TIME_LIMIT field reached
(automatically set; see register description) CLR Q
Expired

Begin Replay
ACK NAK
Received Received

RX Processing
RX Processing
Path Path

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3.3.4 Tx Interface Progression Detection (CX_INTERFACE_TIMER_EN =1)


This feature provides a mechanism for the controller to inform the application about the lack of progression
on one of the data transmission interfaces XALI0/1/2 . It also monitors the internal MSG_GEN interface
and the LBC CFG completion interface. Progression on the data transmission interfaces is not expected to
halt under normal operating circumstances; it might halt if soft errors or silicon failures occur, or if your
application logic inadvertently hangs the TX application interfaces.

3.3.4.1 Tx Interface Progression Detection Features

■ 2-5 timeout detection units instantiated depending on your configuration.


❑ Timeout detection unit sets a flag when interface is stalling/waiting
❑ Timeout detection unit resets the flag when interface is not stalling/waiting.
■ Watchdog timer clocks the timeout detection units.
■ Programmable watchdog timer monitoring window (through INTERFACE_TIMER_TARGET_OFF
register).
■ Controller automatically adjusts watchdog timer’s incrementing interval when core_clk frequency
changes after Gen1/2/3/4 speed change.
■ Controller automatically adjusts watchdog timer’s incrementing interval in L1 and L2 low-power
states.
■ Simulation acceleration mode where one micro-second is counted as one milli-second.
■ Controller output if_timeout_status indicates a time-out event.
■ Programmable generation of AER message after time-out event.

3.3.4.2 Tx Interface Progression Detection Operational Details

The interface progression timer module instantiates a watchdog timer and timeout detection units in the
interfaces to be monitored. The application sets a window for monitoring transfer progression by
programming the watchdog timer period through INTERFACE_TIMER_TARGET_OFF register. The watchdog
timer signal is connected to the timeout detection units. When a change occurs in the watchdog timer signal,
the timeout detection unit checks the interface signals to determine if the interface is halted, and sets a flag.
For example, on XALI0/1/2, if client*_tlp_hv =1 and xadm_client*_halt =1 the timeout detection
unit sets the flag. This flag is reset if the interface is progressing. If the flag is found to be set on the next
change to the watchdog timer signal, interface timeout status signal (if_timeout_status ) is asserted.
This indicates to the application that a progression timeout has occurred on one of the interfaces. The
application can then read the INTERFACE_TIMER_STATUS_OFF register to determine which interface is
causing the timeout.

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Figure 3-10 Tx Interface Progression Detection Operation

XALI0 LBC CFG MSG_GEN


CPL (USP)

XALI1
For each of the above inter faces a timeout
detection unit is implemented.
When CX_INTERFACE_TIMER_EN =1,
2-5 timeout detection units are instantiated by
XALI2 the Progression Detection module, depending
upon your configuration.

Timeout Detection Unit Sets a Flag When an


Interface Is Halted/Stall ing.
2-5 Timeout Example for client0:
Detection *Non-AXI: client0_tlp_hv = client0_tlp_halt =1
Units
SET
INTERFACE_TIMER_CONTROL_OFF register D Q
INTERFACE_TIMER_EN field disable
CLR Q
Status
INTERFACE_TIMER_CONTROL_OFF register S ET Signal
D Q Timeout Detection Unit Resets the Flag If the
INTERFACE_TIMER_SCALING field /1000 Simulation Generation
Acceleration timer Logic Interface is Progressing.
limit Example for client0:
CLR Q
*Non-AXI: client0_tlp_hv=1 && client0_tlp_halt=0
S ET
INTERFACE_TIMER_TARGET_OFF register D Q
mS L0,
@ scale L0S
core_clk Watchdog
CLR Q Timer
Current
core_clk If the Flag is set for two
Frequency Progression subsequent sampling clock
L1, L2
aux_clk_freq
inc by 1 on each tick pm_sel_aux_clk =1
Detection Module cycles if_timeout_status is
(DWC_pcie_interface_timers) asserted.

INTERFACE_TIMER_STATUS_OFF register
SET
DS Q @ posedge
if_timeout_status 1. Read INTERFACE_TIMER_STATUS_OFF to locate halted transmit
interface
Register Write ‘1’ RCLR Q 2. Write ‘1’ to INTERFACE_TIMER_STATUS_OFF to clear status bit

INTERFACE_TIMER_CONTROL_OFF register D
SET
Q
AER Msg Generation
INTERFACE_T IMER_AER_EN field (MSG_GEN)
CLR Q

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3.4 Receive TLP Processing


This section describes the flow of received TLPs through the controller. The topics for this section are:
■ “Receive Filtering”
■ “Receive Routing” on page 95
■ “Error Handling” on page 97

3.4.1 Receive Filtering


The controller contains a filter module that is responsible for the following tasks:
■ Determine the status of a received TLP using filtering rules.
■ Determine the destination of a received TLP based on the filtering status.
■ Indicate the status of the received TLP using outputs.
■ Report Errors to AER registers based on filter results. When more than one type of error is detected,
Section 6.2.3.2.3, Error Pollution, of the PCI Express Base Specification, Revision 4.0, Version 1.0 is
followed.
The controller filters and routes received TLPs according to a set of rules determined by the TLP type based
on the PCI Express Base Specification, Revision 4.0, Version 1.0 and user-configurable filtering options. The
filtering rules for a received TLP are affected by the configuration parameters (compile-time options), I/O
signals (runtime options) and register values (runtime options).

Figure 3-11 RADM Block Diagram

Trash Queue Filter

P
TLP Filtering
CXPL

TRGT1
Routing NP
RBYP
Message
Processing
CPL
RTRGT0

MSG

ERR

MSG

DBI
LBC CFG Data CDM
ELBI

The following general rules apply to all incoming TLPs that are not malformed. For more information on
what happens to malformed TLPs, see “Error Detection for Received TLPs” on page 97. By default:
■ For a function in device power states D1, D2, and D3hot, the controller only accepts CFG and MSG
requests TLPs for that function. All other incoming request types for that function are treated as
unsupported requests (UR).
■ When the controller detects an error1 in a received TLP, it normally performs the following:
❑ Discards the TLP
❑ Generates a completion (for non-posted requests) with the completion status set to CA or UR

1. Excluding TLPs targeted for forwarding (and not for local resources) that have ECRC errors.

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❑ Sets the status in the PCI-compatible Status register


❑ Sets the status in the AER registers (when you enable AER)
❑ Generates an error message (upstream port only)
■ All error-free MSG requests are decoded internally, signaled on the SII interface and then dropped.
When you want to have the decoded message also sent to the application interface, then see “Routing
of Received Messages” on page 166.

For more information on advanced filtering, see “Advanced Information: Advanced Filtering and
Note Routing of TLPs” on page 954

3.4.2 Receive Routing


This section discusses how the RADM routes different TLP types to different receive interfaces depending
on TLP type and filter result.
TRGT0 refers to the internal interface used to access the CDM registers or the ELBI in an upstream port.

3.4.2.1 Upstream Port Routing Overview

TLPs that the controller receives over the link in a switch application fall into the following general classes:
■ TLPs that are to be routed through the switch to another port of the switch. The controller transfers
this class of TLP to your application through the TRGT1 interface. This category includes type 1 config-
uration requests that are received by an upstream switch port and must be sent downstream.
■ Configuration requests that target the controller. The controller processes this class of TLP internally
and automatically generates the required completion.
■ Memory or I/O requests that target the switch application logic. The controller transfers this class of
request to your application through the ELBI and automatically generates the required completion.
Memory and I/O requests targeted to the switch application logic are limited to single-dword
accesses.
The possible destinations of a posted or non-posted request TLP are TRGT1, TRGT0, and Discard1. By
default:
■ CFG0 requests are routed to TRGT0 and then to CDM through the LBC.
■ CFG1 requests are routed to TRGT1.
■ All of the following are routed to TRGT1:
❑ MEM requests inside of the memory range or prefetchable memory range as determined by the
corresponding Base and Limit fields in the Type-1 header.
❑ I/O requests inside of the I/O range as determined by the I/O Base and Limit fields in the Type-1
header.
❑ BAR-matched MEM (not I/O) requests.
■ MSG requests are decoded internally, signaled on the SII interface, and then terminated.

1. Dropped or terminated. Serviced internally but not passed to your application

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BAR memory region must always be outside the memory range as determined by the
Attention corresponding Base and Limit fields in the Type-1 header.

Figure 3-12 Default Request TLP Routing (Assuming no TLPs with CA/CRS/UR Error Status)

core
CDM
config CDM LBC TRGT0 CFG0
data LBC

TRGT1 CFG1

TRGT1 MEM/IO
C
X
P
TYPE 1 L
MEM & IO
Base & Limit
Checks

TRGT1 MEM

BAR Address
Check

BAR
TRGT1

SII MSG

The possible destinations of a completion TLP are TRGT1 and Discard1. Completions are not filtered inside
the SW filter. This is under an assumption that the SW does not generate a request locally. If an embedded
EP is involved in a switch application, there should be some modifications based on the requirements of
your application.

3.4.2.2 Downstream Port Routing Overview

The possible destinations of a posted or non-posted request are TRGT1 and Discard2. By default:
■ MEM requests outside of the memory range and prefetchable memory range as determined by the
corresponding Base and Limit fields in the Type-1 header, are routed to TRGT1.
■ I/O requests outside of the I/O range as determined by the corresponding Base and Limit fields in the
Type-1 header are routed to TRGT1.
■ MSG requests are decoded internally, signaled on the SII interface, and then terminated.
■ A downstream port does not expect to receive CFG requests.
■ BARs should be disabled and not used.
The possible destinations of a completion TLP are TRGT1 and Discard. Completions are not filtered inside
the SW filter. This is under an assumption that the SW does not generate a request locally. When an

1. Dropped or terminated. Serviced internally but not passed to your application


2. Dropped or terminated. Serviced internally but not passed to your application

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embedded EP is involved in a switch application, there should be some modifications based on the
requirements of your application.

For configuration requests targeted to downstream switch ports, the upstream switch
Attention port passes the configuration request to your application on TRGT1. Your application
logic must respond to the configuration request by executing a transaction on the DBI of
the downstream port, then generating the completion and presenting it on one of the
upstream port's XALI interfaces.

For more information on switches, see “Introduction to PCIe Switches” on page 1006. Completions are not
filtered inside the SW filter. It is assumed that the SW does not generate a request locally. If an embedded
endpoint is involved in a switch application, there should be some modifications based on the requirements
of your application.

■ For more information on advanced routing, see “Advanced Information: Advanced


Note Filtering and Routing of TLPs” on page 954
■ For more information on BAR operation, see “BAR Details” on page 117.

3.4.3 Error Handling


The controller supports the Baseline Capabilities, AER capabilities, and Advisory Non-Fatal Error
Messaging as specified in Section 6.2, Error Signaling and Logging of the PCI Express Base Specification,
Revision 4.0, Version 1.0. These include Correctable and Uncorrectable (Fatal and Non-Fatal) errors.

3.4.3.1 Error Detection for Received TLPs

The controller performs all mandatory error detections, the error reporting mechanism based on the PCI
Express Base Specification, Revision 4.0, Version 1.0, and some optional error detections (using the
ENABLE_OPTIONAL_CHECKS parameter). For more information of what error conditions contribute toward
a UR or CA status, see “Advanced Information: Advanced Filtering and Routing of TLPs” on page 954.
When the controller detects an error1 in a received TLP, it normally performs the following:
■ Discards the TLP
■ Generates a completion (for non-posted requests) with the completion status set to CA or UR
■ Sets the status in the PCI-compatible status register
■ Sets the status in the AER registers (when you enable AER)
■ Generates an error MSG (upstream port only)
■ For malformed TLPs credit is returned based on the buffer space which has been consumed by the TLP
For more information see “Advanced Information: Advanced Error Handling for Received TLPs” on page
981

1. Excluding TLPs targeted for forwarding (and not for local resources) that have ECRC errors.

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3.4.3.2 AER Multiple Header Logging

The controller supports the AER multiple header logging as specified in Section 6.2.4.2, “Multiple Error
Handling (Advanced Error Reporting Capability)” of the PCI Express Base Specification, Revision 4.0, Version
1.0.
A valid queue entry is never overwritten. If your software does not read the header log registers fast
enough, you can miss the new header log information when the queue is full.

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3.5 Register Module, LBC, and DBI


This section discusses how the controller’s register space is arranged and accessed. The following topics are
covered in this section
■ “Register Configuration Space Overview” on page 100
■ “Local Bus Controller (LBC)” on page 104
■ “PCIe Wire Access” on page 106
■ “Data Bus Interface (DBI) Access” on page 111
■ “Access Limitations” on page 113
■ “PHY Port Logic Registers” on page 114
■ “BAR Details” on page 117
■ “Generating Register Map” on page 122

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3.5.1 Register Configuration Space Overview


The controller has 4096 bytes of register space per function. Based on the location of the registers, this space
is divided into two groups, CDM and ELBI.
■ Configuration Dependant Module (CDM) Registers
Includes PCI Configuration Header, Standard and Extended Capabilities, and Port Logic registers.
❑ PCI Configuration Header, Standard Capability, and Extended Capability Registers are PCIe
controller configuration registers specified by the PCI Express Base Specification, Revision 4.0,
Version 1.0.
❑ Port Logic Registers (PL) registers are configuration registers which are not specified by the PCI
Express Base Specification, Revision 4.0, Version 1.0, but which are Synopsys-specific. The port logic
registers have specific pre-defined usages, and can optionally be removed from the controller
hardware configuration.
Note: There is one set of iATU port logic registers that are common for all functions.
■ External Local Bus Interface (ELBI) Registers
Your application registers that are external to the controller and connected to the ELBI.

Figure 3-13 Controller Configuration Space Layout: (Downstream Port)

Per Function Space Common for All Functions


CS2=0 CS2 =1
0xFFF
Customer Application Registers CDM/ELBI Select Bit
=1
(ELBI) CDM/ELBI Select Bit
=1
iATU Registers

Approx. (CDM)
0xD00 0x0000

Port Logic Registers


(excluding iATU/DMA Registers)

(CDM)

0x700
Per Function Space
CS2 =1
CDM/ELBI Select Bit
=0

PCIe Extended Capability Structures


AER, VC, SN, PB, ARI, SPCIE,
LTR, L1SS, RBAR Shadow Registers
for Some CDM/ELBI Select Bit
0x100 PCI Header Space, PCI Standard, & PCIe Extended =0
Capability Structures

PCI Standard Capability Structures (CDM)


PM, MSI, PCIE, MSI-X, VPD
CapPtr CapPtr
0x03F
PCI Configuration Header Space
(64 bytes / 16 DWORDs)
0x0000

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Figure 3-14 Controller Configuration Space Layout: (Upstream Port)

Per Function Space Common for All Functions


CS2=0 CS2 =1
0xFFF
Customer Application Registers CDM/ELBI Select Bit
=1
(ELBI) CDM/ELBI Select Bit
CONFIG_LIMIT_REG =1
(wire view only) iATU Registers

Approx. (CDM)
0xD00 0x0000

Port Logic Registers


(excluding iATU/DMA Registers)

(CDM)

0x700
Per Function Space
CS2 =1
CDM/ELBI Select Bit
=0

PCIe Extended Capability Structures


AER, VC, SN, PB, ARI, SPCIE,
LTR, L1SS, RBAR Shadow Registers
for Some CDM/ELBI Select Bit
0x100 PCI Header Space, PCI Standard, & PCIe Extended =0
Capability Structures

PCI Standard Capability Structures (CDM)


PM, MSI, PCIE, MSI-X, VPD
CapPtr CapPtr
0x03F
PCI Configuration Header Space
(64 bytes / 16 DWO RDs)
0x0000

Capability configuration registers are in structures (groups) identified by a capability ID. The groups are
linked together as in PCI. Register locations within a group are specified, but the starting location of each
group must be found by traversing the linked list.
There are two linked lists of register groups:
■ PCI compatible capability registers
PCI compatible capability register groups begin at the configuration address stored in the capability
pointer register at 0x34.
■ PCI Express extended capability registers
PCI Express extended capability register groups begin at address 0x100.
The capability pointer register in the PCI-compatible header register points to the next item in the linked list
of capabilities, which by default is the PCI Power Management capability.

For releases previous to 4.80a, the iATU registers have been programmed through an indirect
Attention addressing scheme using an index register (iATU_VIEWPORT_OFF), to reduce the address
footprint in the PCI Express extended configuration space. To use the legacy method of
accessing iATU and DMA registers, contact Synopsys support through Solvnet.

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3.5.1.1 Register Types

There are three types of registers in the controller as shown in Table 3-4 on page 102

Table 3-4 Types of Registers in PCIe Controller

Register
Type Description Access/Addressing Method

Single register accessed directly by its


Simple address. Most of the registers (including ATU) Direct addressing method. You just supply the address.
are of this type.

Another register exists at the same address Normally can only be accessed through the DBI where
as a Simple register. For example the BAR you select between the two registers using the dbi_cs2
Shadow
Mask registers have the same address as the input . This is called DBI2, CS2, dbi_cs2, DBI_CS2, or
BAR registers. Dbi2 access; all of these terms mean the same thing.

Indirect addressing method where you first write to a


Multiple (n) registers existing at the same
special index register to select which of the n registers at
Viewport address as a Simple register. For example
the address you want to access. You then proceed to
Gen3 Coefficient Preset registers.
write to the register address.

3.5.1.2 Register Views and Access

There are three views for most registers in the controller (see Table 3-5 on page 102), depending on how you
access a register.

Table 3-5 Types of Register Views in PCIe Controller

Typical Access Attributes (for example - R/W,


View Type Description read-only)

Remote access by link partner over the


Wire (USP only) As per PCI-SIG specification.
PCIe link.

■ Normally as per PCI-SIG specification.


Local (back-door) access to Simple
registers by your application logic ■ Some read-onlya registers are permanently R/W.
Dbi ■ Some read-onlya registers can be made temporarily
through the DBI interface with dbi_cs
=1 and dbi_cs2(or CS2) =0. R/W when you write 1 to the DBI_RO_WR_EN bit of the
MISC_CONTROL_1_OFF register.
DBI
Local (back-door) access to some read ■ Normally R/W
only, shadow, iATU, and DMA registers ■ One exception is the BAR mask registers which are
Dbi2 by your application logic through the W (write-only).
DBI interface with dbi_cs =1 and
dbi_cs2(or CS2) =1.

a. As specified by the PCI-SIG specification.

Table 3-6 describes the possible ways to access the controller registers in USP mode.

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Table 3-6 USP Mode Region Access

Register Location CDM ELBI

Synopsys-Specific (Port
Register Type PCI-SIG Logic) User

Normal Shadow Misc IATU User

DBI Access CDM/ELBI Selector Bita


Details Value 0 0 0 1 1

CS2 Selector Bit Value 0 1 0 1 0

DBI/Wire Access Allowed

DBI Y Y Y Y Y

CFG Request Y - Y - Y
Wire
BAR Matched MEM Request - - Yb Y Yc

a. Selector bit locations are configuration-dependent.


b. IO request also supported.
c. IO request also supported.

In DSP mode, the controller register space is fully accessible from the DBI without any restrictions. There is
no wire access in RC Mode.

3.5.1.3 Writing to Read-Only Registers

Your application can write to some read-only (RO) and HwInit registers over the DBI when you set the
“Write to RO Registers Using DBI” (DBI_RO_WR_EN) field of the MISC_CONTROL_1_OFF register to 1. The
app_dbi_ro_wr_disable input pin must be driven to 0 to allow writes to DBI_RO_WR_EN field. Setting the
app_dbi_ro_wr_disable input pin to 1 forces DBI_RO_WR_EN to 0, and disables writing to the
DBI_RO_WR_EN field.
Your application can write to some shadow registers using DBI CS2 accesses. For more information on DBI
CS2, see “Types of Register Views in PCIe Controller” on page 102.
For upstream ports (USP), you should set this to 1. For downstream ports, you can only program the PCIe
configuration space registers (in the CDM) using the DBI. There is no wire access for DSP. In this case, when
programming the Type-1 headers and capabilities, your host software can use the standard model of the
configuration space as in the PCI-SIG specification. Therefore register fields marked RO do not become
writable from the DBI. The exception to this is the SPCIE capability in a Gen3 configured device. RO
registers never become writable over the wire, regardless of the setting of this register bit. The same applies
for HwInit.

For configuration requests targeted to downstream switch ports, the upstream switch port
Note passes the configuration request to your application on TRGT1. Your application logic must
respond to the configuration request by executing a transaction on the DBI of the downstream
port, then generating the completion and presenting it on one of the upstream port's XALI
interfaces.

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3.5.2 Local Bus Controller (LBC)


The Local Bus Controller (LBC) module provides a mechanism for a link partner or a local CPU (through the
DBI) to access:
■ Internal registers (in the CDM)
■ External application registers connected externally to the ELBI

Figure 3-15 LBC Context (USP)


RX PIPE
Application RBYP
2 1
Logic: RADM
Receive TRGT1

DBI
CPU

Application ELBI LBC CIC


3
Registers
CXPL Core

4
CXPL PHY
Note: For DSP there is no
wire access to CDM or ELBI

CDM Core
Registers

Request flow
Response flow
XADM 5
TX PIPE

PCIe Wire Access to CDM Registers or ELBI


1 Incoming request from PCIe remote link partner

2 Request is filtered and routed by RADM through TRGT0 to LBC

3 LBC forwards the request to external registers (through ELBI) or internal registers in CDM

4 LBC forms completion TLPs with response received from ELBI or internal registers in CDM

5 PCIe controller transmits response completion to remote link partner

RX PIPE
Application RBYP
Logic: RADM
Receive TRGT1

CPU 1
DBI

Application ELBI LBC CIC


2
Registers
CXPL Core
2
3
CXPL PHY

CDM Core
Registers

Request flow
Response flow
XADM
TX PIPE

DBI Access to CDM Registers or ELBI

1 Request from Local CPU Through DBI

2 LBC forwards the request to external registers (through ELBI) or internal registers in CDM

3 LBC forms completion TLPs with response received from ELBI or internal registers in CDM

4 PCIe controller presents response to Local CPU through DBI

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Figure 3-16 LBC Context (DSP)


RX PIPE
Application RBYP
Logic: RADM
Receive TRGT 1

CPU 1
DBI

LBC CIC
2
CXPL Core

3
CXPL PHY

CDM Core
Registers

Request flow
Response flow
XADM
TX PIPE

DBI Access to CDM Registers

1 Request from Local CPU Through DBI

2 LBC forwards the request to registers in CDM

3 LBC forms completion TLPs with response received from registers in CDM

4 PCIe controller presents response to Local CPU through DBI

The LBC is single-threaded. Therefore the DBI and PCIe wire cannot use the LBC at the same time. A
non-posted PCIe wire transaction is not considered to be complete until the XADM has accepted the
completion for transmission. If there are not sufficient TX completion credits, then the LBC remains locked
and unavailable for the next request (from the DBI or PCIe wire). A request on the DBI is not accepted when
a PCIe wire transaction is already in progress, therefore, you must not use the ELBI to drive the DBI. This
would result in a deadlock of the LBC. When the DBI and the PCIe wire start a request at the same time
(regardless of the target/destination of each request), then the LBC grants access to the PCIe wire (TRGT0).

Figure 3-17 LBC Switch


Inbound request CDM (access to
through TRGT0 core’s registers)
1

3
ELBI (external local
DBI bus interface )
4

1 Inbound PCIe request to read /write the PCIe core’s internal configuration space registers .
2 Inbound PCIe request to read /write external application specific registers .
3 Local CPU request at DBI to read/write PCIe core’s internal configuration space registers .
4 Local CPU request at DBI to read/write external application specific registers .

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3.5.3 PCIe Wire Access


This section discusses the PCI Wire Access. The topics are:
■ “Overview”
■ “CDM/ELBI Register Space Access Through CFG Request” on page 106
■ “CDM/ELBI Register Space Access Through MEM/IO Requests” on page 108

3.5.3.1 Overview

The controller address space can be accessed from the wire using CFG request, BAR matched MEM request,
or BAR matched IO request in USP mode. Table 3-7 gives information of which address space can be
accessed through which type of request from the wire.
In DSP mode the controller address space cannot be accessed from the wire.

Table 3-7 USP Mode Region Access Through CFG/MEM/IO Request

Register Location CDM ELBI

PCI-SIG Synopsys-Specific (Port Logic) User


Register Type
Normal Shadow Misc IATU DMA User

CFG Request Y - Y - - Y

BAR Matched MEM


Request - - Y Y Y Y
Request
Type
BAR Matched IO
- - Y - - Y
Request

3.5.3.2 CDM/ELBI Register Space Access Through CFG Request

In Table 3-8, the value of CONFIG_LIMIT_REG and TARGET_ABOVE_CONFIG_LIMIT_REG fields of


MISC_CONTROL_1_OFF register determine the register location (CDM or ELBI) to which the CFG request is
routed. Figure 3-18 shows the controller configuration space layout in EP mode.

Table 3-8 USP Mode Region Access (CFG)

Register Location CDM ELBI

Register Group/Type PCI-SIG Synopsys Port Logic User

TLP Routing
Wire Access Type Allowed Path Normal Shadow Misc Rsvd IATU DMA Misc
(Figure 3-18)

CFG Request
Address >= 0x0 1 Ya - - - - - -
Address < 0x700

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CFG Request
Address >= 0x700 1 - - Y - - - -
Address <= 0xD00

CFG Request
Address > 0xD00 1 - - - Y - - -
b
Address <= 4*CONFIG_LIMIT_REG

CFG Request
(Address > 4*CONFIG_LIMIT_REG; 2 - - - - - - Yc
TARGET_ABOVE_CONFIG_LIMIT_REG
=ELBI)

CFG Request
(Address > 4*CONFIG_LIMIT_REG; 3 - - - - - - -
TARGET_ABOVE_CONFIG_LIMIT_REG
=TRGT1)

a. To access the Standard Capabilities and the PCIe Extended Capabilities, you should not use an absolute address but should
traverse the linked link using the “next” pointer of each capability.
b. MISC_CONTROL_1_OFF.CONFIG_LIMIT_REG (default =0x3FF DWORDs, which is 0xFFF bytes) specifies a DWORD
address limit, above which incoming CFG requests are routed to the destination defined by MISC_CON-
TROL_1_OFF.TARGET_ABOVE_CONFIG_LIMIT_REG, which can be ELBI or TRGT1 (default). CONFIG_LIMIT_REG is
normally set to a limit that divides the controller's configuration space registers in CDM from your application's external config-
uration space registers on ELBI. The default corresponds to the 0xFFF (4K bytes) upper limit of configuration space, and so
the controller consumes all CFG transactions by default. CONFIG_LIMIT_REG must be set to a value lower than this to have
an effect. Normally, you would never set it to less than 0x340 DWORDs (equivalent to 0xD00 bytes) which is the top of the
Synopsys Port Logic register space.
c. The function number (PF) that is being accessed is identified by a 1 on the corresponding lbc_ext_cs[NF-1:0] output bit loca-
tion. When the function is a VF, then it is identified on the lbc_ext_vfunc_active and lbc_ext_vfunc_num[NVF_WD-2:0]
outputs. The controller sets lbc_ext_bar_num[2:0] =3’b111 for all ELBI CFG accesses.

Figure 3-18 CFG Request TLP Routing


controller
1
config
data CDM 1
LBC TRGT0 0 2
D
Application Registers ELBI 0 M CFG
D U
3 2
M X 3
1
Application U
X C
Logic 1 register address >
CONFIG_LIMIT_REG X
AXI Bus Subsystem P
TARGET_ABOVE_CONFIG_LIMIT_REG =TRGT1(2)
L

TRGT1

For configuration requests targeted to downstream switch ports, the upstream switch port
Attention passes the configuration request to your application on TRGT1. Your application logic must
respond to the configuration request by executing a transaction on the DBI of the downstream
port, then generating the completion and presenting it on one of the upstream port's XALI
interfaces.

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3.5.3.3 CDM/ELBI Register Space Access Through MEM/IO Requests

A MEM/IO access with a TLP address within the range of any enabled memory BAR of any function (PF or
VF), is routed to the destination indicated by the BAR target parameter MEM_FUNC#_BAR#_TARGET_MAP of
the matched BAR. Table 3-9 shows the possible TLP routing paths for MEM/IO requests.

Table 3-9 USP Mode Region Access (MEM/IO)

Register Location CDM ELBI

Register Group/Type PCI-SIG Synopsys Port Logic User

TLP
Routing
Wire Access Type Alloweda Path Normal Shadow Misc Rsvd IATU DMA Misc
(Figure 3-1
9)

BAR Matched MEM (or IO) Request


b
(MEM_FUNC#_BAR#_TARGET_MAP =TRGT
0;
ENABLE_MEM_MAP_UNROLL_DMA_REG 2 - - - - - - Yc
=0; ENABLE_MEM_MAP_UNROLL_ATU_REG
=0;
ENABLE_MEM_MAP_PL_REG=0)

BAR Matched MEM (or IO) Request


(MEM_FUNCN_BARn_TARGET_MAP
=TRGT0;
ENABLE_MEM_MAP_PL_REG =1; 1 - - Y Y - - -
d
Address in range of BARn of physical function
N and whose offset is in range 0x700 to
4*CONFIG_LIMIT_REG, where n
=PL_BAR_NUM and N =PL_FUNC_NUM)

BAR Matched MEM Request


(MEM_FUNCN_BARn_TARGET_MAP
=TRGT0;
ENABLE_MEM_MAP_UNROLL_DMA_REG
=1; or
ENABLE_MEM_MAP_UNROLL_ATU_REG =1; 1 - - - - Y Y -
Address in range of BARn of physical function N
and whose offset is in range of ATU/DMA
registers, where
n =UNROLL_BAR_NUM and
N =UNROLL_FUNC_NUM)

else (address not in range) 2 Y

BAR Matched MEM (or IO) Request


(MEM_FUNC#_BAR#_TARGET_MAP 3 - - - - - - -
=TRGT1)

a. You cannot memory map Posted requests when the Posted queue is in bypass mode.

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b. Or VF_MEM_FUNC#_BAR#_TARGET_MAP for VFs. For other functions and BARs, change to FUNC# and BAR# respec-
tively.
c. The accessed function number (PF) s identified by a 1 on the corresponding lbc_ext_cs[NF-1:0] output bit location. When
the function is a VF, then it is identified on the lbc_ext_vfunc_active and lbc_ext_vfunc_num[NVF_WD-2:0] outputs. The
matched BAR number is identified by lbc_ext_bar_num[2:0]. For an I/O access, the controller also asserts the lbc_ext_io_-
access output.
d. Byte address.

Figure 3-19 MEM/IO TLP Request Routing


1
controller
config
data CDM
LBC
Application Registers ELBI
2
3
1
Application
Logic
TRGT0 0 2
D C
Customer Application M
U MEM/IO X
P
TRGT1 1 X
3 L
Address/Type Check

FUNCT# and BAR#


of matched BAR

BAR

* CX_NFUNC

MEM_FUNC#_BAR#_TARGET_MAP
MEM_FUNC0_BAR1_TARGET_MAP
MEM_FUNC0_BAR0_TARGET_MAP

Memory Mapping of CDM/ELBI Registers


■ Port Logic Registers (excluding DMA/iATU)
Port logic registers can be accessed by MEM requests when you use these configuration parameter
settings:
❑ MEM_FUNCN_BARn_TARGET_MAP =TRGT0
❑ ENABLE_MEM_MAP_PL_REG =1
❑ PL_BAR_NUM =n
❑ PL_FUNC_NUM =N
Then a MEM access with a TLP address within the range of memory BARn of physical function N, and
whose address offset is in the range (0x700 to CONFIG_LIMIT_REG*4), is routed to the internal port
logic registers in the CDM. This is called Memory Mapping the port logic registers. When you
configure the posted queue mode as bypass (in the segmented-buffer queue architecture), you cannot
memory map the port logic registers.
■ iATU and DMA Port Logic Registers
The DMA and iATU port logic registers can be accessed by MEM requests when you use these config-
uration parameter settings:
❑ MEM_FUNCN_BARn_TARGET_MAP =TRGT0
❑ UNROLL_BAR_NUM =n (BAR that you want to capture ATU/DMA register requests)
❑ UNROLL_FUNC_NUM =N (function that you want to capture ATU/DMA register requests)
DMA:

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❑ ENABLE_MEM_MAP_UNROLL_DMA_REG =1
❑ UNROLL_DMA_OFFSET_BAR =dma_offset_bar
ATU:
❑ ENABLE_MEM_MAP_UNROLL_ATU_REG =1
❑ UNROLL_ATU_OFFSET_BAR =atu_offset_bar
Then a MEM access with a TLP address within the range of memory BARn of physical function N, and
whose address offset is in the range (UNROLL_ATU_OFFSET_BAR to UNROLL_ATU_OFFSET_BAR+
UNROLL_ATU_SIZE1/UNROLL_DMA_OFFSET_BAR to UNROLL_DMA_OFFSET_BAR+UNROLL_DMA_-
SIZE1), is routed to the iATU/DMA registers. Parameters UNROLL_DMA_OFFSET_BAR and
UNROLL_ATU_OFFSET_BAR default to 02.
This is called “Memory Mapping” the iATU and DMA configuration registers. When you configure
the posted queue mode as bypass (in the segmented-buffer queue architecture), you cannot memory
map the iATU and DMA configuration registers.

ELBI Access
When MEM_FUNC#_BAR#_TARGET_MAP =TRGT0, then by default the BAR-matched MEM TLP is routed to
the ELBI. The accessed function number (PF) is identified by a 1 on the corresponding
lbc_ext_cs[NF-1:0] output bit location. When the function is a VF, then it is identified on the
lbc_ext_vfunc_active and lbc_ext_vfunc_num[NVF_WD-2:0] outputs. The matched BAR number is
identified by the lbc_ext_bar_num[2:0].When you configure the posted queue mode as bypass (in the
segmented-buffer queue architecture), you cannot send posted requests to the ELBI interface.

1. coreConsultant automatically calculates the size of the iATU and DMA address spaces (UNROLL_ATU_SIZE/
UNROLL_DMA_SIZE parameters) which are configuration-dependent.
2. If enabled the OFFSET is different. For example, UNROLL_ATU_OFFSET_BAR =h1000.

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PCI Express SW Controller Databook Data Bus Interface (DBI) Access

3.5.4 Data Bus Interface (DBI) Access


This section discusses the Data Bus Interface (DBI). The topics are:
■ “Overview” on page 111
■ “Native Controller DBI Access Details” on page 112

3.5.4.1 Overview

The DBI can access all 4096 bytes (1024 DWORDs) of the PCI Express configuration space per function. DBI
can also access iATU, DMA, MSI-X Table, and MSI-X PBA configuration space. This address space is fully
accessible from the DBI without any restrictions.

Native Controller DBI Access


Bit 0 of the DBI address input (dbi_addr) and chip select signal (dbi_cs2) determines the target of a DBI
transaction as follows:

Table 3-10 Native Controller DBI Address Bus Layout for Accessing CDM

Register Location CDM ELBI

PCI-SIG Synopsys-Specific (Port Logic) User


Register Type
Normal Shadow Misc IATU DMA User

CDM/ELBI Selector Bita


Access 0 0 0 1 1 1
Value
Details
CS2 Selector Bit Value 0 1 0 1 1 0

a. Selector bit locations are configuration-dependent.

Figure 3-20 DBI Access Using Native DBI Interface


Controller
LBC

iATU
DMA 11
Address/Type Check

Shadow 10 D BAR5
Registers M BAR4
BAR3
U BAR2
Application BAR1
ELBI 01 X BAR0
Registers
* CX_NFUNC
RTRGT0
* CX_NFUNC CDM 00
Receive Filter

dbi_addr[0]
dbi_cs2

Local CPU DBI

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3.5.4.2 Native Controller DBI Access Details

■ The DBI address must be a DWORD address with dbi_addr[1]=1b0.


■ Byte access within a DWORD for write requests is possible using dbi_wr[3:0].
■ The dbi_wr[3:0]bus also identifies the type of access as a write or read (4h0).

Table 3-11 Native Controller DBI Address Bus Layout for Accessing CDM (dbi_cs2 =0)

31-19 18-16 15-12 11-2 1 0

Not used 0x0 Not used 1 K-DWORD Register Address 0 0

The lower 12 bits are used to access the 4KB (1K DWORDs) of the PCI Express configuration space .

Table 3-12 Native Controller DBI Address Bus Layout for Accessing ELBI (dbi_cs2 =0; CX_LBC_EXT_AW
=5'd16)

31-19 18-16 15-2 1 0

Not used 0x0 16 K-DWORD Register Address 0 1

Only 12-bits are needed to access the 4 KB (1K DWORDs) of the PCI Express configuration
Note
space per function. However, to access more than 4 KB of ELBI register space, you can
increase the value of CX_LBC_EXT_AW up to a maximum of 32-bits. The addressing scheme
described in Table 3-13 is used to access the extended ELBI address space.

Table 3-13 Native Controller DBI Address Bus Layout for Accessing ELBI (dbi_cs2 =0; CX_LBC_EXT_AW
=6'd32)

31-19 18-16 15-2 1 0

1 G-DWORD Register Address 0 1

Table 3-14 Native Controller DBI Address Bus Layout for Accessing iATU and DMA Configuration
Registers(dbi_cs2 =1)

Access
Type 31-20 19 18-17 16-9 8 7-2 1 0

Region Number 0: Outbound Register


Not used 0 Reserved 0 1
Select Region Address
iATU
Region Number Register
Not used 0 Reserved 1:Inbound Region 0 1
Select Address

Channel Number Register


Not used 1 Reserved 0:Write Channel 0 1
Select Address
DMA
Channel Number Register
Not used 1 Reserved 1:Read Channel 0 1
Select Address

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3.5.5 Access Limitations


The following limitations exist for the LBC.
■ CDM Access Restrictions:
❑ Maximum payload Length =1 DWORD.
❑ PCIe MEM requests with Length >1 are processed as completer abort.
❑ PCIe MEM requests with Length =0 are processed as completer abort.
❑ PCIe IO or CFG requests with Length !=1 are processed as malformed TLPs.
■ ELBI Access Restrictions:
❑ CS2 bit must be 1’b0.
❑ Maximum payload Length =CX_LBC_NW (1 or 2 DWORDs).
❑ PCIe MEM requests with Length >CX_LBC_NW are processed as completer abort.
❑ PCIe MEM requests with Length =0 are processed as completer abort.
❑ PCIe IO or CFG requests with Length !=1 are processed as malformed TLPs.
❑ Address must be CX_LBC_NW aligned.
❑ Does not support “Atomic Operations (AtomicOps)” on page 257.
❑ Does not support TPH. Controller does not forward the TPH bits to the ELBI.
■ ELBI Data/Address Port Width Restrictions:
❑ Data (Write): CX_LBC_NW =1 or 2 DWORDs.
❑ Data (Read): CX_LBC_NW =1 or 2 DWORDs per function.
❑ Controller datapath width (CX_NW) must be >=CX_LBC_NW.
❑ Address: CX_LBC_EXT_AW =12-32.
It is expected that your application at the ELBI only decodes the valid address bits to the BAR limit
specified.
■ DBI Data/Address Port Widths:
❑ Data: 32-bit
❑ Address: 32-bit

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3.5.6 PHY Port Logic Registers


The controller implements PHY_VIEWPORT_CTLSTS_OFF and PHY_VIEWPORT_DATA_OFF registers which
control the PHY Register Bus Interface (PRBI) to perform read and write operations on the PHY sub-blocks.
These registers are enabled when CX_PHY_VIEWPORT_ENABLE parameter is set.

Figure 3-21 PHY Viewport Registers

PHY#
PHY0 PHY1 PHY2 PHY3
x2 x2 x2 x2

CRPI CRPI CRPI CRPI

PRBI
Controller

PHY Register
Controller
(PRC)

RADM

CDM
LBC
Port Logic Registers
CFG TRGT0 PHY Viewport Registers
PHY_VIEWPORT_CTLSTS_OFF

PHY_VIEWPORT _DATA_OFF

DBI #Considering a PHY containing 4 Sub-blocks of 2 lanes each

Control registers of all the PHY sub-blocks map to a single PHY_VIEWPORT_CTLSTS_OFF register. To
perform a read/write operation on the PHY, an indirect addressing mechanism is used, where first the
PHY_VIEWPORT_CTLSTS_OFF register is programmed through DBI (dbi_addr[0] =0 and dbi_cs =1) or
CFG to select the PHY block/lane to read from/write to, and then actual read/write on the PHY sub-block
happens.

Programming the PHY Viewport Registers to Read from PHY Registers


■ Set PHY_VIEWPORT_ADDR and PHY_VIEWPORT_NUM fields of PHY_VIEWPORT_CTLSTS_OFF register.
■ Set PHY_VIEWPORT_READ field of PHY_VIEWPORT_CTLSTS_OFF register to 1. When set,
phy_cr_para_rd_en is asserted and read operation is initiated on the PRBI.
Note: For DBI access, lbc_dbi_ack signal is asserted before the operation on the PRBI is completed.
For CFG access, completion is returned before the operation on the PRBI is completed.
■ When PHY_VIEWPORT_PENDING field of PHY_VIEWPORT_CTLSTS_OFF register becomes 0, check
PHY_VIEWPORT_STATUS field of PHY_VIEWPORT_CTLSTS_OFF register to confirm that the read oper-
ation on PRBI has completed successfully.
■ Read PHY_VIEWPORT_DATA_OFF register to fetch the data read from the PHY registers.

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Programming the PHY Viewport Registers to Write to the PHY Registers


■ Set PHY_VIEWPORT_ADDR, PHY_VIEWPORT_NUM, and PHY_VIEWPORT_BCWR fields of PHY_VIEW-
PORT_CTLSTS_OFF register.
■ Set PHY_VIEWPORT_DATA_OFF register with the data to be written on the PHY. The signal -
phy_cr_para_wr_en is asserted to initiate a write operation on PRBI once the data is written to
PHY_VIEWPORT_DATA_OFF register.
Note: For DBI access, lbc_dbi_ack signal is asserted before the operation on the PRBI is completed.
For CFG access, completion is returned before the operation on the PRBI is completed.
■ When PHY_VIEWPORT_PENDING field of PHY_VIEWPORT_CTLSTS_OFF register becomes 0, check
PHY_VIEWPORT_STATUS to confirm that the write operation on PRBI has completed successfully.

Write Operation: Role of PHY_VIEWPORT_ADDR, PHY_VIEWPORT_NUM, and PHY_VIEWPORT_BCWR


Table 3-15 shows the setting of PHY_VIEWPORT_BWCR, PHY_VIEWPORT_NUM and PHY_VIEWPORT_ADDR
fields of the PHY_VIEWPORT_CTLSTS_OFF register, for a few combinations of PHY sub-block and lane
writes. These settings are with reference to Consumer 8G PHY for TSMC 28 HPC.

Table 3-15 Write Operation: PHY_VIEWPORT_CTLSTS_OFF Field Values

PHY_VIEWPORT_ADDR

Access PHY_VIEWPORT_BWCR PHY_VIEWPORT_NUM 15 14-12 11-8 7-0

Write: Selected Sub-block, Selected Lane

PHY0.lane0 0 0 0 Address 0 Address

PHY0.lane1 0 0 0 Address 1 Address

Write: Selected Sub-block, All Lanes

PHY0.lane0/PHY0.lane1 0 0 1a Address NA Address

PHY1.lane0/PHY1.lane1 0 1 1a Address NA Address

Write: All Sub-blocks, Selected Lane

PHY0.lane0
PHY1.lane0
1 NAb 0 Address 0 Address
PHY2.lane0
PHY3.lane0

PHY0.lane1
PHY1.lane1
1 NAb 0 Address 1 Address
PHY2.lane1
PHY3.lane1

a. if PHY_VIEWPORT_ADDR[15] =1, all lanes inside sub-block selected by PHY_VIEWPORT_NUM are written.
b. if PHY_VIWEPORT_BWCR =1, PHY_VIWEPORT_NUM is not considered.

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PHY_VIEWPORT_ADDR

Access PHY_VIEWPORT_BWCR PHY_VIEWPORT_NUM 15 14-12 11-8 7-0

Broadcast Write: All Sub-blocks, All Lanes

PHY0.lane0/PHY0.lane1
PHY1.lane0/PHY1.lane1
1 NAa 1 Address NA Address
PHY2.lane0/PHY2.lane1
PHY3.lane0/PHY3.lane1

PHY0.lane0
PHY1.lane0
1 NAa 0 Address 0 Address
PHY2.lane0
PHY3.lane0

a. if PHY_VIWEPORT_BWCR =1, PHY_VIWEPORT_NUM is not considered.


For more information on cold reset sequence with PHY initialization, see Figure 2-17 on page 68. For more
information on PHY initialization after cold reset, see Figure 2-18 on page 69.

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3.5.7 BAR Details


In this section, the operation and programming of Base Addres Registers (BARs) is described.

3.5.7.1 RC Mode

The following topics are discussed:


■ “Overview”
■ “BAR Sizing” on page 118
■ “Disabling a BAR” on page 119
■ “General Rules for BAR Setup (Fixed Mask or Programmable Mask Schemes Only)” on page 119
■ “Memory BAR Sizes” on page 120
■ “IO BAR Sizes” on page 120
■ “BAR Mask Registers” on page 120
■ “Example BAR Setup” on page 121
■ “Expansion ROM BAR Mask Register (Offset: 0x38; same as the Expansion ROM BAR, but requires
dbi_cs2/CS2 for write access)” on page 121

3.5.7.1.1 Overview
Base Address Registers (Offset: 0x100x14)
Downstream Port: Two BARs are present but are not expected to be used. You should disable them (see
“Disabling a BAR” on page 119) to avoid unnecessary memory assignment during device enumeration. If
you do use a BAR, then you should program it to capture TLPs that are targeted to your local
non-application memory space residing on TRGT1, and not for the application on TRGT11. The BAR range
must be outside of the three Base/Limit regions. The controller provides one pair of 32-bit BARs (BAR0 and
BAR1). The BARs can be configured as follows:
■ One 64-bit BAR: BAR0 and BAR1 are combined to form a single 64-bit BAR.
■ Two 32-bit BARs: BAR0 and BAR1 are two independent 32-bit BARs.
■ One 32-bit BAR: BAR0 is a 32-bit BAR and BAR1 is either disabled or removed from controller alto-
gether to reduce gate count.
Upstream Port: Using MEM_FUNCN_BARn_TARGET_MAP you can configure each of the six BARs to capture
and route incoming MEM and I/O requests routed to:
■ 1: TRGT1
■ 0: TRGT0 (ELBI or Port Logic Registers)

1. Because in a DSP, there is no wire access to TRGT0 (ELBI or CDM) using CFG requests or BAR-matched MEM requests.

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■ For more information about routing requests to either TRGT1 or TRGT0 on a BAR-by-BAR
Note basis, see “Advanced Information: Advanced Filtering and Routing of TLPs” on page 954.
For more information on BAR operation, see “Receive Routing” on page 95.
■ If you have configured (MEM_FUNCN_BARn_TARGET_MAP =0) any BAR to have its
incoming requests routed to TRGT0 in upstream port, then you must disable1 that BAR
(through a DBI write) when operating the controller in downstream port. See “Disabling a
BAR” on page 119.

The following sections describe how to set up the BAR types and sizes by programming values into the base
address registers.

3.5.7.1.2 BAR Sizing


The BAR masks are used for indicating the amount of address space that each BAR requests from host
software. The BAR masks determine which bits in each BAR are non-writable by host software, which
determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of
low-order bits not to use for address matching. The BAR mask value also indicates the range of low-order
bits in the BAR that cannot be written from the host. Your application can write to all BAR bits to allow
setting of memory, I/O, and other standard BAR options. There are three schemes that each BAR can use for
setting the amount of address space that it requests.
■ BARn_SIZING_SCHEME_0 =Fixed Mask (0)
You hardwire the mask using the BARn_MASK_0 parameter. You cannot change it at runtime.
■ BARn_SIZING_SCHEME_0 =Programmable Mask (1)
Mask registers are instantiated in the controller. You set the default using BARn_MASK_0. You can
change it at runtime through the DBI, at the same address as the corresponding BAR register, by
asserting dbi_cs2 . The BAR mask registers are only writable through the DBI, and not readable. They
are not visible from the PCIe wire by the remote partner. When the BAR mask value for a BAR is less
than that required for the BAR type, the controller automatically uses the minimum value for the BAR
type.

Figure 3-22 Fixed and Programmable Mask Example for 32-bit Memory BAR0 (CX_BAR0_SIZING_SCHEME_0 !=2)

Flip-flops for bits [31:1] only present when


0 BAR0 Mask Register CX_BAR0_SIZING_SCHEME_0 = 1
1 x28 BAR0 Register
0
# 1 0
write data 31:1 31:4
0 0 31:4
DBI write 1
1 bar0_maski write data
dbi_cs2 WO(cs2) RW
0x0 1
To
x28 BAR
reset
BAR0_SIZING_SCHEME_0 = 1 PCIe Address
7FFF_FFFF Write Matching
BAR0_MASK_0[31:1] Logic in
reset Receive
dbi_cs Filter

DBI write
0
0 3:0
0 write 1
bar0_enabled data RO(cs)
0 0 1
write data 1
1 WO(cs2)
DBI write to 0x10 reset
DBI write BAR dbi_cs *
dbi_cs2 reset Enable

{ PREFETCHABLE_0_0,BAR0_TYPE_0,MEM0_SPACE_DECODER_0 }

Note: Register address decoding and register BAR0_ENABLED _0 * This is gated with theDBI _RO_WR_EN register field .
write enable generation not shown for clarity.
# The lower 8-bits of write data are overwritten with0xFF

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■ BARn_SIZING_SCHEME_0 =Resizable BAR (2)


When you enable the PCI-SIG resizable BAR feature, the host software reads the Supported Resource
Sizes field of the Resizable BAR Capability register.

Figure 3-23 Resizable BAR Example for 32-bit Memory BAR0 (CX_BAR0_SIZING_SCHEME_0 =2)
ResizableBAR Clear all bits that are changing from R/W to RO
0 Control Register
x28 BAR0 Register
0 encode Change read-write 0
1 RWS
data access of individual
1 0 31:4
BAR 0 register bits to 1
reflect the chosen BAR data
Wire write BAR Size RW
reset size 0x0 1
To
dbi_cs 2 x28 BAR
DBI write 0x0 RE S B A R_CTRL_RE G_0_RE G Address
Wire write
Matching
Logic in
reset Receive
dbi_cs Filter

0 DBI write
0
0
1 ROS(cs)
data 0 3:0
write 1
1 Resizable data
BAR RO(cs)
1
Capability
reset Register
DBI write to 0x10 reset
RE S B A R_CA P_RE G_0_RE G
dbi_cs
1
CX_BAR0_RESOURCE_AVAIL_N

{ PREFETCHABLE_0_0,BAR0_TYPE _0,MEM0_SPACE_DECODER_0 }
0
0 0
write data 1
WO(cs2)
1
DBI write BAR
Notes:
reset Enable
dbi_cs2 1 This is gated with theDBI_RO_WR_EN field.
2 The RESBAR _CTRL_REG_BAR _SIZE field is automatically updated when you write to RESBAR_CAP_REG_0_REG
through the DBI.

BAR0_ENABLED _0

After it selects a BAR size, it writes this value to the BAR Size field of Resizable BAR Control register. From
this field, the controller automatically derives the R/W mask for the BAR register. The host software can
now start the normal BAR query process. You can change the BAR size at runtime, because the “Supported
Resource Sizes” register field is writable through the local DBI (only).

3.5.7.1.3 Disabling a BAR


To disable a BAR (in any of the three schemes), your application can write 0 to the LSB of the BAR mask
register. The BAR mask register is at the same address as the BAR register, and you can access it through the
DBI (only) by asserting dbi_cs2.

3.5.7.1.4 General Rules for BAR Setup (Fixed Mask or Programmable Mask Schemes Only)
At runtime, application software can overwrite the BAR contents to reconfigure the BARs (unless the
affected BAR is removed during hardware configuration). Application software must observe the following
rules when writing to the BARs:
■ BAR0 and BAR1 can be configured as one 64-bit BAR, two 32-bit BARs, or one 32-bit BAR.
■ Any 32-bit BAR that is not needed can be removed during controller hardware configuration to reduce
gate count.
■ An I/O BAR must be a 32-bit BAR and cannot be prefetchable.
■ When BAR0 is configured as a 64-bit BAR:

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❑ BAR1 is the upper 32 bits of the combined 64-bit BAR formed by BAR0 and BAR1. Therefore, BAR1
must be disabled and cannot be configured independently.
❑ BAR0 must be a memory BAR and can be either prefetchable or non-prefetchable.
❑ The contents of the BAR0 mask register determine the number of writable bits in the 64-bit BAR,
subject to the restrictions described in “BAR Mask Registers” on page 120. The BAR1 mask register
contains the upper 32 bits of the BAR0 mask value.
❑ BAR0 can be disabled by writing 0 to bit [0] of the BAR0 mask register.
■ When BAR0 is configured as a 32-bit BAR:
❑ You can configure BAR1 as an independent 32-bit BAR or remove BAR1 from the controller hard-
ware configuration.
❑ BAR0 can be configured as a memory BAR or an I/O BAR.
❑ The contents of the BAR0 mask register determine the number of writable bits in the 32-bit BAR0,
subject to the restrictions described in “BAR Mask Registers” on page 120.
❑ BAR0 can be disabled by writing 0 to bit [0] of the BAR0 mask register.
■ When BAR0 is configured as a 32-bit BAR, BAR1 is available as an independent 32-bit BAR according
to the following rules:
❑ BAR1 can be configured as a memory BAR or an I/O BAR.
❑ The contents of the BAR1 mask register determine the number of writable bits in the 32-bit BAR1,
subject to the restrictions described in “BAR Mask Registers” on page 120.
❑ BAR1 can be disabled by writing 0 to bit [0] of the BAR1 mask register.
❑ When BAR1 is not required in your design, you can remove BAR1 from the hardware configura-
tion by setting both BAR1_ENABLED_0 and BAR1_MASK_TYPE_0 to 0.

3.5.7.1.5 Memory BAR Sizes


BAR bits [11:0] are always masked for a memory BAR. The PCI Express Base Specification, Revision 4.0, Version
1.0 states that the minimum memory address range requested by a BAR is 128 bytes. In the PCI Local Bus
Specification, it is recommended that devices that need less than 4 KB of address space should still consume
4 KB of address space in order to minimize the number of bits in the address decoder. The controller
requires each memory BAR to claim at least 4 KB as it does not perform end address checking.

3.5.7.1.6 IO BAR Sizes


BAR bits [7:0] are always masked for an I/O BAR. The controller requires each I/O BAR to claim at least 256
bytes. The PCI Local Bus Specification allows I/O BARs to consume between 4 bytes and 256 bytes of
address space. The controller only permits I/O BARs to consume 256 bytes of address space. This restriction
is used in order to minimize the number of bits in the address decoder.

3.5.7.1.7 BAR Mask Registers


You can change the mask at runtime through the local DBI. The mask register is at the same address as the
BAR register. The mask is a shadow register that is invisible to the PCIe wire but visible to the local
processor over the DBI. Furthermore, it is only visible for a write not for a read. So you cannot read the mask
register but you can write to it. The shadow register is accessed by asserting dbi_cs2 and dbi_cs. If you
assert dbi_cs (only) then you access the BAR which is the primary register at that location.

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3.5.7.1.8 Example BAR Setup


Figure 3-24 shows an example configuration of the BARs and their corresponding BAR mask registers. The
example configuration includes one 64-bit memory BAR (non-prefetchable).

Figure 3-24 Example Base Address Register Configuration


Base Address Registers
31 0

BAR1 (14h) Upper Address Bits of BAR0 (non-masked)


Writable Base Address Masked Base
64-bit Memory BAR
BAR0 (10h) Bits (31:20) Addr. Bits (19:4) 0100

BAR Mask Registers


31 0

BAR1 Mask (14h) 0x00000000


BAR0 Mask (10h) 0x000 FFFFF

3.5.7.1.9 Expansion ROM BAR Mask Register (Offset: 0x38; same as the Expansion ROM BAR, but
requires dbi_cs2/CS2 for write access)
Your local CPU can change the mask at runtime using the DBI. The mask register is at the same address as
the BAR register. The mask is a shadow register that is invisible to the PCIe wire but visible to the local
processor over the DBI. Furthermore, it is only visible for a write not for a read. So you cannot read the mask
register but you can write to it. The shadow register is accessed by asserting CS2 and CS. If you assert CS
(only) then you access the BAR which is the primary register at that location.

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3.5.8 Generating Register Map


The detailed descriptions for each register are given in DWC_pcie_ctl_sw_registers.pdf or
https://www.synopsys.com/dw/doc.php/iip/DWC_pcie/5.40a/doc/DWC_pcie_ctl_sw_registers.pdf.
There are multiple maps for the controller because some modes are determined by an input pin at reset
which adds or removes capability registers from the linked list.

Generating Register Map Documentation


Attention
When you configure the controller in coreConsultant, you can access the register descriptions
for your actual configuration at workspace/report/ComponentRegisters.html using the process
described in the “Creating Optional Views and Reports” section in the User Guide. This report
comes from the exact same source as the Databook but removes all the registers that are not
in your actual configuration.

Table 3-16 describes the parameters to consider for generating DocBook XML and HTML Register Reports.

Table 3-16 Parameters to Consider for Generating DocBook XML and HTML Register Reports

Parameter Name Values Notes

The memory map of an Upstream port is different to that


0: Upstream Port of a Downstream port. Using the
CX_MEMORY_MAP_POSTION CX_MEMORY_MAP_POSTION parameter you can
1: Downstream Port
generate the memory map either for the Upstream Port
or the Downstream Port.

The registers for each port type, Upstream


port/Downstream port can be accessed by the remote
0: DBI link partner through the wire or by your application
through DBI (DBI or DBI2). For more information on the
CX_MEMORY_MAP_VIEW 1: WIRE
register views, see Table 3-5.
2: DBI2
The wire view of the registers is different to the DBI view.
To choose the type of register view, use
CX_MEMORY_MAP_VIEW parameter.

You can generate the memory map view containing only


iATU and DMA registers by setting the parameter
0: NO_UNROLL
CX_UNROLL_VIEW CX_UNROLL_VIEW to ‘1’. To generate the memory
1: UNROLL map views without iATU and DMA registers set the
CX_UNROLL_VIEW parameter to ‘0’.

Figure 3-25 Memory Map Configuration Parameters in coreConsultant

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Register Default Values


The register descriptions in this chapter indicate the default of the register after a cold reset, either as a
specific numerical value or as the name of the design configuration parameter that sets the default. You can
inspect the values of the configuration parameters in two different locations:
■ In the Component Configuration report that is described in the Creating Optional Views and Reports
section in the User Guide
■ In workspace/src/DWC_pcie_ctl_cc_constants.svh

Rebuilding Capability Linked Lists


When your configuration software requires any set of standard PCI capability registers to be removed, it
can overwrite the next capability pointers through the DBI and rebuild the linked list structure.

■ Even though there is a unique standard capabilities linked lists provided per function,
Note specific capabilities cannot be included/excluded on a per-function basis. For example,
MSI-X capability is included/excluded for all functions (PF) at the same time through the
coreConsultant GUI.
■ Even though there is a unique extended capabilities linked list provided per function,
specific capabilities cannot be included/excluded on a per function basis (in particular for
LTR and VC, this is a non-fatal violation of a strict reading of the PCIe specification).
■ Each function can have a different setup of a capability structure after it is included,
although some features/settings are common across all functions.

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3.6 Reliability, Availability, and Serviceability (RAS)


This section discusses how the controller maintains the integrity of the link using different methods at
different points. It also discusses error injection and traffic, error, and state logging. The following topics are
covered.
■ “Overview”
■ “RAS Wire Protection (ECRC)” on page 125
■ “RAS Data Protection (DP)” on page 126
■ “RAS Debug, Error Injection, and Statistics (DES)” on page 136

3.6.1 Overview
PCIe system Reliability, Availability, and Serviceability (RAS) ensures that failures in the underlying
processes and hardware components do not cause any interruptions in the overall system operation.
Synopsys PCIe RAS consists of four fundamental components:
■ Reliable protocol architecture involving LCRC, ECRC, ACK/NAK handshake, and Replay mecha-
nisms.
■ Internal device-level Datapath and RAM protection (RAS DP) of data, header, and RAM control
signals from application I/F to LCRC extraction/generation points.
■ Debug, Error Injection, and Statistic gathering (RAS DES).
■ Hot-plug usage to swap out components with uncorrectable errors.

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3.6.2 RAS Wire Protection (ECRC)


The controller uses the optional ECRC checksum, as defined in the PCIe specification, to protect the wire
part of the link. The controller checks it in the receive logic.

3.6.2.1 Generation

It is expected that the ECRC is already present in traffic that your application is presenting on the transmit
interfaces of the controller. The controller forwards it unchanged. You should set client0_tlp_td =0.

3.6.2.2 Checking

When the ECRC is present, the controller checks it and forwards it unchanged. To enable ECRC checking:
■ Set CX_ECRC_ENABLE =AER_ENABLE =CX_ECRC_STRIP_ENABLE =1
■ Set the ECRC_CHECK_EN field of the ADV_ERR_CAP_CTRL_OFF AER register.
By default, when the controller detects a TLP, targeted for local resources and not for forwarding, with an
ECRC error, it performs the following:
■ Discards1 the TLP
■ Generates a completion (for non-posted requests) with the completion status set to CA or UR
■ Sets the status in the PCI-compatible status register
■ Sets the status in the AER registers (when you enable AER)
❑ When an ECRC error is detected by a PF, with ECRC checking enabled for any PF, ECRC error
status is set for all PFs
❑ ECRC error status is not set for VFs and reads zero
■ Generates an error message (upstream port only)
A TLP, targeted for local resources and not for forwarding, with an ECRC error is never discarded.

1. You can program the controller to forward the TLP. For more information, see “Advanced Information: Advanced Error
Handling for Received TLPs” on page 981.

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3.6.3 RAS Data Protection (DP)


The following topics are covered in this section:
■ “Overview”
■ “Features and Limitations” on page 127
■ “RAS DP Registers” on page 131
■ “Uncorrectable Error Handling” on page 133
■ “Correctable Error Handling” on page 135

3.6.3.1 Overview

For the parts of the controller outside of ECRC/LCRC protection, you can use the RAS DP feature
consisting of:
■ RAM Protection (ECC on data and Parity on address)
An ECC checksum is calculated and added to data that is written to the RAM. When the data is read
from the RAM, then the controller recalculates the ECC and compares it against the value read from
RAM. RAM ECC protection is provided for all of the RAMs in the controller, except for the RAS-DES
RAM. ECC corrects single-bit errors and reports (without correction) multi-bit errors.
■ Datapath Protection (ECC or Parity)
For Tx traffic, your local application logic must add ECC or parity protection codes1 to traffic using:
❑ client0_tlp_hdr_prot and client1_tlp_hdr_prot for the TLP header.
❑ Additional MSBs on client0_tlp_data and client1_tlp_data for the TLP data.
❑ Additional MSBs on client0_tlp_prfx and client1_tlp_prfx for the TLP prefixes.
For Rx traffic, your local application must check the protection codes on:
❑ radm_trgt1_hdr_prot and radm_bypass_hdr_prot for the TLP header.
❑ The MSBs on radm_trgt1_tlp_data and radm_bypass_tlp_data for the TLP data.
❑ The MSBs on radm_trgt1_tlp_prfx and radm_bypass_tlp_prfx for the TLP prefixes.

You can find a reference RASDP wiring template that has an example implementation of the
Attention application logic required to drive the controller's RASDP inputs and the expected outputs in:
workspace/examples/pcie_rasdp_glue.v. This file is for reference purpose only, it must
not be used as is.

The basic ECC module is based on http://www.synopsys.com/dw/ipdir.php?c=DW_ecc.

1. For more information on how to calculate the protection codes, see the description of these signals in the Signal Descriptions
chapter.

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Figure 3-26 RAS DP Protection Coverage

RAM
RBYP
RX PIPE
TRGT1 RADM

TRGT0
CIC
Application ELBI LBC
Registers
iATU

CXPL Core
PHY
Application MSI CDM Core
Logic :
MSI(-X) MSI-X
Registers
RAS
Application
Logic : RAM
SII
Rx Vendor
Messages

CPU DBI

XALI0

XALI1 RAM TX PIPE

XADM
XALI2

Application
Logic:
VMI MSG_GEN
Tx Vendor
Messages

Application HOT PLUG


Logic:
Optional
System Status/ SII PMC CLK/RST
Control
Registers

Protected by RAS

3.6.3.2 Features and Limitations

Table 3-17 describes RAS data protection features and limitations.

Table 3-17 RAS Data Protection Features and Limitations

RAM Protection Features (CX_RASDP_RAM_PROT =1)

RAM Data Protection ECCa

RAM Types Protected Internal/External

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RAM Protection Features (CX_RASDP_RAM_PROT =1)

# Errors Detectable 1, 2

# Errors Correctable 1

1-bit errors are Correctable

2-bit errors are Uncorrectable

Programmable Correction Enable/Disable Per Regionb

Corrected Data Rewritten to RAM

Controller Regenerates ECC Code at Output of RAM When Uncorrectable (2-bit) Error
Detected

ECC Protection Range

32-bit for 32-bit controller datapath width

64-bit all other controller datapath widths

ECC Code Size (8 bits ECC per 64 bits of RAM data)

<= 26-bit RAM Data 6 bits

<= 57-bit RAM Data 7 bits

<= 64-bit RAM Data 8 bits

Optional Pipeline Stage

RAM Address Protection Parity

Number of Bits per Address Bus 1

Address Parity Generated by Controller

Address Parity Checked by Controllerc

a. See Limitations.
b. Using the RASDP_ERROR_PROT_CTRL_OFF register.
c. The controller does not check the address parity. RAM address parity checking and error handling is application specific.

Datapath/Interface Protection Features (CX_RASDP >0)

Datapath (Header and Data) Protection Parity/ECC

Protection From Application Interfacesa to LCRC Insertion/Extraction

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Datapath/Interface Protection Features (CX_RASDP >0)

Controller Expects Application to Supply Parity/ECC on TX Path Interfaces

Controller Strips Parity/ECC After LCRC Insertion on TX Path

Controller Inserts Parity/ECC Before LCRC Extraction on RX Path

Controller Passes Parity/ECC to Application on RX Path

Controller Checks and Recalculates Protection Codes at all Internal Processing (Data
Manipulation) Stepsb

# Errors Detectable

ECC 1,2

Parity 1

# Errors Correctable

ECC 1

Parity 0c

Programmable ECC Correction Enable/Disable Per Regiond

Configurable ECC Correction On/Off Using CX_RASDP

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Datapath/Interface Protection Features (CX_RASDP >0)

ECC Protection Range

32-bit for 32-bit controller datapath width

64-bit all other controller datapath widths

ECC Code Size (8 bits ECC per 64 bitseof datapath)

32-bit Datapath 7 bits

64-bit Datapath 8 bits

128-bit Datapath 16 bits

256-bit Datapath 32 bits

512-bit Datapath 64 bits

Parity Protection Range

8-bit

32-bit

64-bit

Selectable Odd/Even Parity

a. See Limitations.
b. Detailed report of all check points is available at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/5.40a/doc/RASDP_-
CheckPoints.pdf.
c. The controller pulses app_parity_err[2:0]output bus. Your application can OR the bus bits and drive the Uncorrectable
Error bit of the app_err_bus input. This is not required when RASDP error mode is enabled because the controller handles the
parity error as an uncorrectable error in this mode.
d. Using the RASDP_ERROR_PROT_CTRL_OFF register.
e. Except for 32-bit datapath.

Statistics and Error Injection Features

Error Injection (Per TLP)

Programmablea 1-bit or 2-bit Injection

Programmable Continuous or Fixed-Number (n) Injection Modes

Programmable Global Enable/Disable

Programmable Selectable Location Where Injection Occurs

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Statistics and Error Injection Features

Error Statisticsb

Counts # Correctable Errors

Counts # Uncorrectable Errors

Reports Location of First and Last Errors (Correctable and Uncorrectable)

Reports RAM Addressesc of Detected Errors (Correctable and Uncorrectable)

a. Using the RASDP_ERROR_INJ_CTRL_OFF register.


b. A single RASDP error might increment more than one counter.
c. RASDP_RAM_ADDR_UNCORR_ERROR_OFF and RASDP_RAM_ADDR_UNCORR_ERROR_OFF registers.

Limitations

iMSIX-TX Module RAMs Protected

RAS DES RAM Protected

LBC Datapath (DBI or Wire Access to CDM/ELBI) Protected

MSI/MSI-X Interfaces Protected

Vendor Message Interface (VMI) Protected

iMSIX-TX Module Datapath Protected

3.6.3.3 RAS DP Registers

The controller has a set of RAS DP registers as defined in Table 3-18. For detailed descriptions of how you
use them, see the “Registers” chapter (DWC_pcie_ctl_sw_registers.pdf).

Table 3-18 RAS DP Vendor Specific Extended Capability (VSEC Registers)

Register Description

RASDP_EXT_CAP_HDR_OFF Vendor-Specific Extended Capability Header.

RASDP_VENDOR_SPECIFIC_HDR_OFF Vendor Specific Header.

RASDP_ERROR_PROT_CTRL_OFF Error Protection Control.

RASDP_CORR_COUNTER_CTRL_OFF Corrected error (1-bit ECC) counter selection and control.

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Register Description

RASDP_CORR_COUNT_REPORT_OFF Corrected error (1-bit ECC) counter data.

Uncorrected error (2-bit ECC and parity) counter selection and


RASDP_UNCORR_COUNTER_CTRL_OFF
control.

RASDP_UNCORR_COUNT_REPORT_OFF Uncorrected error (2-bit ECC and parity) counter data.

RASDP_ERROR_INJ_CTRL_OFF Error injection control.

RASDP_CORR_ERROR_LOCATION_OFF Corrected errors locations.

RASDP_UNCORR_ERROR_LOCATION_OFF Uncorrectable errors locations.

RASDP_ERROR_MODE_EN_OFF RASDP error mode enable.

RASDP_ERROR_MODE_CLEAR_OFF RASDP error mode clear.

RAM Address where a corrected error (1-bit ECC) has been


RASDP_RAM_ADDR_CORR_ERROR_OFF
detected.

RAM Address where an uncorrected error (2-bit ECC) has been


RASDP_RAM_ADDR_UNCORR_ERROR_OFF
detected.

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Figure 3-27 RAS DP Register Access to Error Counters (Same Method Applies to Uncorrectable Errors)
CORR_CLEAR _COUNTERS

CORR_EN_COUNTERS

CORR_COUNTER_SELECTION _REGION [3:0]

CORR_COUNTER_SELECTION [7:0]

Counter j
Software Write
Counter0
RST
EN

Region i
Counter j

error
RASDP_CORR_COUNTER_CONTROL_OFF

CORR_COUNTER_SELECTED [7:0]
Region 0
Counters CORR_COUNTER_SELECTION _REGION [3:0]

Software
. CORR_COUNTER[7:0]
Read

.
. Counter j
RASDP_CORR_COUNT_REPORT_OFF
Counter0
RST
EN

error

Region i
Counters

You can inspect the VTB test case (ft_rasdp.sv) at


Hint
<workspace>/doc/html/vtb/testenv/index.html for programming examples. For more
information on VTB, see the “Integrating the Controller and VIP using VTB” section in the
“Integration” chapter of the User Guide.

3.6.3.4 Uncorrectable Error Handling

Upon detection of first Uncorrectable error (RAM and Datapath/Interface Protection), depending on value
of AUTO_LINK_DOWN_EN field of the RASDP_ERROR_MODE_EN_OFF register, the controller takes one of the
two actions:
■ Forces the PCIe link to go down (AUTO_LINK_DOWN_EN =1), or
■ Enters RASDP Error Mode (AUTO_LINK_DOWN_EN =0)

PCIe Link Down


If the controller is configured to cause the link to go down upon detection of an Uncorrectable error, the
controller resets and resumes normal operation.

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RASDP Error Mode


On entering RASDP error mode, the controller sets cfg_rasdp_error_mode =1 (or
slv_rasdp_error_mode/mstr_rasdp_error_mode). Wire access to CDM/ELBI registers is suspended
to prevent corruption of the register configuration space.
TLP handling in RAS DP Error mode:
■ Rx TLP Handling
❑ Rx Errored TLPs are Forwarded to Your Application
❑ Subsequent Rx TLPs not Guaranteed to be Correct; you Must Discard all TLPs1
■ Tx TLP Handling (32-bit, 64-bit Datapath configurations)
❑ Bad TLP is Nullified2 (EDB Inserted and LCRC Inverted) and Transmitted
❑ Subsequent TLPs are Nullified and Transmitted
❑ In-progress Replay is Nullified and Transmitted
❑ Subsequent Replays are Silently Dropped
■ Tx TLP Handling (128-bit, 256-bit Datapath configurations which can carry two TLPs per clock cycle
❑ Bad TLP is Silently Dropped3
❑ Subsequent TLPs are Silently Dropped
❑ In-progress Replay is Nullified and Transmitted
❑ Subsequent Replays are Silently Dropped
Note: The controller attempts a best-effort recovery in RASDP Error Mode (after detection of an
uncorrectable error). Synopsys reserves the right to modify this best-effort behavior if deemed necessary.
Credits accuracy is not retained under uncorrectable error conditions. The controller implements a
best-effort approach in accounting for credits under uncorrectable error conditions. However, credit
inaccuracies are unavoidable in such conditions. This might result in performance degradation or triggering
of overflow protection mechanisms.
Error Logging:
■ Uncorrectable4 Error is Logged
■ Uncorrectable Internal Error Reported (AER)5
Your application can instruct the controller to exit RASDP error mode by writing to
RASDP_ERROR_MODE_CLEAR_OFF register through DBI. Your application must perform any cleanup it may
deem necessary prior to instructing the controller to exit RASDP error mode.
In RASDP error mode, some Uncorrectable errors can be severe enough to eventually cause the link to go
down. If link down occurs, the controller resets and resumes normal operation.

1. In RASDP error mode, TLPs are not guaranteed to be correct. You must discard all TLPs when this signal is high.
2. The controller might nullify TLPs that are received prior to the bad TLP.
3. The controller might drop TLPs that are received prior to the bad TLP.
4. 2-bit ECC and all parity errors.
5. The controller only reports uncorrectable errors when it exits RASDP error mode.

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3.6.3.5 Correctable Error Handling

The controller takes the following action to handle correctable (RAM and Datapath/Interface Protection)
errors:
■ Correctable1 Error is Logged
■ Correctable Internal Error Reported (AER)
■ TLP is Modified/Corrected
■ Errors Reported When Detected (Immediately)
■ Error Correction Enable/Disable Control (Per TX/RX Direction and Per-Layer)2

1. 1-bit ECC errors.


2. If the controller is capable of single bit error correction, disabling ECC error correction does not change the nature of the
errors and their reporting. A single-bit error is reported as a correctable error although correction might be disabled.

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3.6.4 RAS Debug, Error Injection, and Statistics (DES)


You enable the basic DES operation with the CX_RAS_DES_ENABLE parameter. To enable advanced features,
you have to enable the respective parameters in addition to CX_RAS_DES_ENABLE parameter.

3.6.4.1 Debug

To facilitate system level debugging the controller provides the following features:
■ General Diagnostic Support (Legacy Internal Probe Points).
■ Silicon Debug Support (Control and Status of PIPE, Deskew, Ack/Nak, Reversal, FC, EQ, LTSSM,
Replay)

General Diagnostic Support


The basic diagnostic operation is enabled when the CX_RAS_DES_ENABLE parameter is enabled. Your
application can use the signals in Table 3-19 to control and check the diagnostic results.

Table 3-19 General Diagnostic Signals

Signal Name Description

diag_ctrl_bus Diagnostic control bus.

This bus provides information regarding all the important status


diag_status_bus
signals from each controller module.

Silicon Debug Support


You enable this feature with the CX_RAS_DES_SD_ENABLE parameter. Your application can use the outputs
in Table 3-20 and registers in Table 3-21. For register descriptions, see DWC_pcie_ctl_sw_registers.pdf.

Table 3-20 Silicon Debug Outputs

Output Description

This is common debug signal bus that provides RAS D.E.S.


cdm_ras_des_sd_info_common
silicon debug information.

This is Lanei debug signal bus that provides RAS D.E.S.


cdm_ras_des_sd_info_i (for i = 0; i < CX_NL)
silicon debug information.

This is VCi debug signal bus that provides RAS D.E.S.


cdm_ras_des_sd_info_vi (for i = 0; i < CX_NVC)
silicon debug information.

Table 3-21 Vendor Specific and Silicon Debug Registers

Register Description

Vendor Specific Registers

RAS_DES_CAP_HEADER_REG Vendor-Specific Extended Capability Header.

VENDOR_SPECIFIC_HEADER_REG Vendor-Specific Header.

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Register Description

Silicon Debug Registers

SD_CONTROL1_REG on Silicon Debug Control1.

SD_CONTROL2_REG on Silicon Debug Control2.

SD_STATUS_L1LANE_REG Silicon Debug Status(Layer1 Per-lane).

SD_STATUS_L1LTSSM_REG Silicon Debug Status(Layer1 LTSSM).

SD_STATUS_PM_REG Silicon Debug Status(PM).

SD_STATUS_L2_REG Silicon Debug Status(Layer2).

SD_STATUS_L3FC_REG Silicon Debug Status(Layer3 FC).

SD_EQ_CONTROL1_REG Silicon Debug EQ Control1.

SD_EQ_STATUS1_REG Silicon Debug EQ Status1.

SD_EQ_STATUS2_REG Silicon Debug EQ Status2.

SD_EQ_STATUS3_REG Silicon Debug EQ Status3.

In addition, you can also use the non-optional silicon debug outputs in Table 3-22 and registers in Table 3-23
that always exist regardless of parameter settings.

Table 3-22 Pre-existing Silicon Debug Outputs

Output

rdlh_link_up Data link layer up/down indicator.

brdg_slv_xfer_pending AXI Slave non-DBI transfer pending status.

brdg_dbi_xfer_pending AXI Slave DBI transfer pending status.

edma_xfer_pending DMA transfer pending status.

radm_xfer_pending Receive request pending status.

Indicates that the controller received a flow control update


rtlh_rfc_upd
DLLP.

rtlh_rfc_data The data from a received flow control update DLLP.

Level indicating that the receive queues contain TLP


radm_q_not_empty
header/data.

Pulse indicating that one or more of the P/NP/CPL receive


radm_qoverflow
queues have overflowed.

cxpl_debug_info[63:0] State of selected internal signals,

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Output

State of selected internal signals in relation to electrical idle


cxpl_debug_info_ei[15:0]
(EI) at the receiver.

Table 3-23 Pre-existing Silicon Debug Registers

Register Fields

TX_P_HEADER_FC_CREDIT
TX_P_FC_CREDIT_STATUS_OFF
TX_P_DATA_FC_CREDIT

TX_NP_HEADER_FC_CREDIT
TX_NP_FC_CREDIT_STATUS_OFF
TX_NP_DATA_FC_CREDIT

TX_CPL_HEADER_FC_CREDIT
TX_CPL_FC_CREDIT_STATUS_OFF
TX_CPL_DATA_FC_CREDIT

RX_QUEUE_NON_EMPTY
QUEUE_STATUS_OFF TX_RETRY_BUFFER_NE
RX_TLP_FC_CREDIT_NON_RETURN

PL_DEBUG0_OFF DEB_REG_0

PL_DEBUG1_OFF DEB_REG_1

GEN3_EQ_COEFF_LEGALITY_STATUS_OFF GEN3_EQ_VIOLATE_COEF_RULES

VC0_P_TLP_Q_MODE
VC0_P_RX_Q_CTRL_OFF VC0_P_HEADER_CREDIT
VC0_P_DATA_CREDIT

VC0_NP_TLP_Q_MODE
VC0_NP_RX_Q_CTRL_OFF VC0_NP_HEADER_CREDIT
VC0_NP_DATA_CREDIT

VC0_CPL_TLP_Q_MODE
VC0_CPL_RX_Q_CTRL_OFF VC0_CPL_HEADER_CREDIT
VC0_CPL_DATA_CREDIT

GEN1_EI_INFERENCE
PRE_DET_LANE
GEN2_CTRL_OFF
NUM_OF_LANES
FAST_TRAINING_SEQ

PIPE_LOOPBACK_CONTROL_OFF PIPE_LOOPBACK

REPLAY_TIME_LIMIT
ACK_LATENCY_TIMER_OFF
ROUND_TRIP_LATENCY_TIME_LIMIT

VENDOR_SPEC_DLLP_OFF VENDOR_SPEC_DLLP

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Register Fields

CPL_SENT_COUNT
LINK_STATE
PORT_FORCE_OFF FORCE_EN
FORCED_LTSSM
LINK_NUM

ENTER_ASPM
L1_ENTRANCE_LATENCY
ACK_F_ASPM_CTRL_OFF
L0S_ENTRANCE_LATENCY
ACK_FREQ

TRANSMIT_LANE_REVERSALE_ENABLE
EXTENDED_SYNCH
BEACON_ENABLE
LINK_CAPABLE
LINK_RATE
PORT_LINK_CTRL_OFF FAST_LINK_MODE
LINK_DISABLE
DLL_LINK_EN
RESET_ASSERT
SCRAMBLE_DISABLE
VENDOR_SPECIFIC_DLLP_REQ

LANE_SKEW_OFF DISABLE_LANE_TO_LANE_DESKEW

UPDATE_FREQ_TIMER
TIMER_MOD_ACK_NAK
IMER_CTRL_MAX_FUNC_NUM_OFF
TIMER_MOD_REPLAY_TIMER
MAX_FUNC_NUM

MASK_RADM_1
SYMBOL_TIMER_FILTER_1_OFF DISABLE_FC_WD_TIMER
EIDLE_TIMER

FILTER_MASK_2_OFF MASK_RADM_2

AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_O
OB_RD_SPLIT_BURST_EN
FF

TIMER_MOD_FLOW_CONTROL_EN
QUEUE_STATUS_OFF
TIMER_MOD_FLOW_CONTROL

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Register Fields

USP_SEND_8GT_EQ_TS2_DISABLE
AUTO_EQ_DISABLE
GEN3_DC_BALANCE_DISABLE
GEN3_DLLP_XMT_DELAY_DISABLE
GEN3_EQUALIZATION_DISABLE
GEN3_RELATED_OFF RXEQ_PH01_EN
EQ_REDO
EQ_EIEOS_CNT
EQ_PHASE_2_3
DISABLE_SCRAMBLER_GEN_3
GEN3_ZRXDC_NONCOMPL

GEN3_EQ_LOCAL_FS
GEN3_EQ_LOCAL_FS_LF_OFF
GEN3_EQ_LOCAL_LF

GEN3_EQ_POST_CURSOR_PSET
GEN3_EQ_PSET_COEF_MAP__i
GEN3_EQ_CURSOR_PSET
(for i = 0; i <= 10)
GEN3_EQ_PRE_CURSOR_PSET

GEN3_EQ_PSET_INDEX_OFF GEN3_EQ_PSET_INDEX

GEN3_EQ_PSET_REQ_AS_COEF
GEN3_EQ_FOM_INC_INITIAL_EVAL
GEN3_EQ_PSET_REQ_VEC
GEN3_EQ_CONTROL_OFF
GEN3_EQ_EVAL_2MS_DISABLE
GEN3_EQ_PHASE23_EXIT_MODE
GEN3_EQ_FB_MODE

GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA
GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF
GEN3_EQ_FMDC_N_EVALS
GEN3_EQ_FMDC_T_MIN_PHASE23

3.6.4.2 Error Injection

You enable this feature with the CX_RAS_DES_EINJ_ENABLE parameter. The controller provides support for
your application to inject the following types of errors:
■ CRC Error
■ Sequence Number Error
■ DLLP Error
■ Symbol DataK Mask Error or Sync Header Error
■ FC Credit Update Error
■ TLP Duplicate/Nullify Error
■ Specific TLP Error

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Your application can use the registers in Table 3-24 to set up error injection. For register descriptions, see
DWC_pcie_ctl_sw_registers.pdf.

Table 3-24 Error Injection Vendor Specific Extended Capability (VSEC) Registers

Register Description

RAS_DES_CAP_HEADER_REG Vendor-Specific Extended Capability Header.

VENDOR_SPECIFIC_HEADER_REG Vendor-Specific Header.

.........other registers (for example, Event Counter, Time-based Analysis, Error Injection) .........

EINJ_ENABLE_REG Error Injection Enable.

EINJ0_CRC_REG Error Injection Control 0 (CRC Error).

EINJ1_SEQNUM_REG Error Injection Control 1 (SeqNum Error).

EINJ2_DLLP_REG Error Injection Control 2 (DLLP Error).

EINJ3_SYMBOL_REG Error Injection Control 3 (Symbol Error).

EINJ4_FC_REG Error Injection Control 4 (FC Credit Error).

EINJ5_SP_TLP_REG Error Injection Control 5 (Specific TLP Error).

EINJ6_COMPARE_POINT_H0_REG Error Injection Control 6 (Compare Point H0).

EINJ6_COMPARE_POINT_H1_REG Error Injection Control 6 (Compare Point H1).

EINJ6_COMPARE_POINT_H2_REG Error Injection Control 6 (Compare Point H2).

EINJ6_COMPARE_POINT_H3_REG Error Injection Control 6 (Compare Point H3).

EINJ6_COMPARE_VALUE_H0_REG Error Injection Control 6 (Compare Value H0).

EINJ6_COMPARE_VALUE_H1_REG Error Injection Control 6 (Compare Value H1).

EINJ6_COMPARE_VALUE_H2_REG Error Injection Control 6 (Compare Value H2).

EINJ6_COMPARE_VALUE_H3_REG Error Injection Control 6 (Compare Value H3).

EINJ6_CHANGE_POINT_H0_REG Error Injection Control 6 (Change Point H0).

EINJ6_CHANGE_POINT_H1_REG Error Injection Control 6 (Change Point H1).

EINJ6_CHANGE_POINT_H2_REG Error Injection Control 6 (Change Point H2).

EINJ6_CHANGE_POINT_H3_REG Error Injection Control 6 (Change Point H3).

EINJ6_CHANGE_VALUE_H0_REG Error Injection Control 6 (Change Value H0).

EINJ6_CHANGE_VALUE_H1_REG Error Injection Control 6 (Change Value H1).

EINJ6_CHANGE_VALUE_H2_REG Error Injection Control 6 (Change Value H2).

EINJ6_CHANGE_VALUE_H3_REG Error Injection Control 6 (Change Value H3).

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Register Description

EINJ6_TLP_REG Error Injection Control 6 (Packet Error).

You can inspect the VTB test case ft_ras_des_einj.sv at


Hint <workspace>/doc/html/vtb/testenv/index.html for programming examples. For more
information on VTB, see “Integrating the Controller and VIP using VTB” section in the
“Integration” chapter of the User Guide.

Limitations
You can use the Error Injection6 only when both the conditions are satisfied.
■ The RAS datapath protection (DP) has been disabled (CX_RASDP =0, CX_RASDP_RAM_PROT =0), and
■ The address translation has been disabled (ADDR_TRANSLATION_SUPPORT_EN =0)

3.6.4.3 Statistics

To facilitate collection of statistics the controller provides the following features:


■ Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM
state)
■ Event counters (Error and Non-Error)

Time Based Analysis


You enable this feature with the CX_RAS_DES_TBA_ENABLE parameter. Using this feature you can obtain
information regarding RX/TX data throughput and time spent in each low-power LTSSM state by the
controller. Your application can use the outputs in Table 3-25 and registers in Table 3-27. For register
descriptions, see DWC_pcie_ctl_sw_registers.pdf.

Table 3-25 Time-based Analysis Signals

Signal Name

app_ras_des_tba_ctrl This bus controls the start/end of time based analysis.

This is common event signal bus that provides RAS


cdm_ras_des_tba_info_common
D.E.S. time based analysis information.

Table 3-26 Time-based Analysis RAM Signals

Signal Name

This signal bus provides RAS D.E.S. time based


cdm_ras_des_tb_ram_*
analysis information for the RAMs.

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Table 3-27 Time-based Analysis Vendor Specific Extended Capability (VSEC) Registers

Register Description

RAS_DES_CAP_HEADER_REG Vendor-Specific Extended Capability Header

VENDOR_SPECIFIC_HEADER_REG Vendor-Specific Header.

.........other registers (for example, Event Counter).........

TIME_BASED_ANALYSIS_CONTROL_REG Time-based Analysis Control.

TIME_BASED_ANALYSIS_DATA_REG Time-based Analysis Data.

Figure 3-28 Time-based Analysis Register Access

aux _clk
app _ras_des _tba_ctrl[1:0] =01 (start)
TIMER_START =1 (start ) app _ras_des _tba_ctrl[1:0] =10 (stop)
0 0
TIMER_START =0 (stop)

(auto -reset at end of measurement duration ) 0

TIME_BASED _DURATION_SELECT [7:0] 15:8 Software Write

TIME_BASED _REPORT _SELECT [ 15:0] 31:24

TIME_BASED _ANALYSIS _CONTROL_REG

Counter

.
.
.

32 Software
Read

Counter

TIME_BASED _ANALYSIS _DATA_REG

The counters measure, for example, what percentage of time does the controller stay in L0 in a one second
window (configurable through TIME_BASED_DURATION_SELECT field). The measurement range of each
Event in Group#0 is shown in Figure 3-29.

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Figure 3-29 Measurement Ranges of Time-based Analysis Events in Goup#0

Measurement
duration

LTSSM STATE L0 Tx L0s Tx L0s and Rx L0s Rx L0s L0 L1 L1.1 L1 Recovery L0

aux_clk_active pclk aux_clk pclk

L0 Event

Tx L0s Event

Rx L0s Event

Tx L0s and Rx L0s


Event
TBA
Event
L1 Event

L1 aux Event

L1.1 Event

Config/Recovery
Event

This event counts when both This event counts when current state is L1 and This event counts when current state is L1 and the controller(PMC) is running on aux_clk.
Tx L0s and Rx L0s are active. the controller(PMC) is running on core_clk. It also counts even if the current state is L1.1 or L1.2.

Table 3-28 Time-based Analysis Counter Group #0 (32-bit Low-Power Cycle Counter (RAM)

Event # % of Measurement Window Spent in LTSSM State Note

0x01 Tx L0s -

0x02 Rx L0s -

0x03 L0 -

The controller (PMC) is running on


0x04 L1
core_clk

0x05 L1.1 -

0x06 L1.2 -

0x07 Configuration/Recovery -

The controller (PMC) is running on


0x08 L1 aux
aux_clk

0x09 Tx L0s and Rx L0s -

Table 3-29 Time-based Analysis Counter Group #1 (32-bit Throughput 4-DWORD Counter)

Event # Amount of Data Processed (Units of 16 bytes) Note

0x00 Tx PCIe TLP Data Payload -

0x01 Rx PCIe TLP Data Payload -

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Event # Amount of Data Processed (Units of 16 bytes) Note

PCIe Compatible TLP: CCIX TLP Data


Payload consists of the data payload +
TLP Header DW3
0x02 Tx CCIX TLP Data Payload
CCIX Optimized TLP: CCIX TLP Data
Payload consists of the data payload + 1
DW header

PCIe Compatible TLP: CCIX TLP Data


Payload consists of the data payload +
TLP Header DW3
0x03 Rx CCIX TLP Data Payload
CCIX Optimized TLP: CCIX TLP Data
Payload consists of the data payload + 1
DW header

Event Counters
You enable this feature with the CX_RAS_DES_EC_ENABLE parameter. Your application can use the outputs
in Table 3-30 and registers in Table 3-32. For register descriptions, see
DWC_pcie_ctl_sw_registers.pdf.

Table 3-30 Event Counter Signals

Output Description

This is a common signal bus that provides RAS D.E.S. event counter
cdm_ras_des_ec_info_common
information.

cdm_ras_des_ec_info_i This is Lanei event signal bus that provides RAS D.E.S. event counter
(for i = 0; i <CX_NL)) information.

Table 3-31 Event Counter RAM Signals

Signal Names Description

This signal bus provides RAS D.E.S. Event Counter information for the
cdm_ras_des_ec_ram_*
RAMs.

Table 3-32 Event Counter VSEC Registers

Register Description

RAS_DES_CAP_HEADER_REG Vendor-Specific Extended Capability Header.

VENDOR_SPECIFIC_HEADER_REG Vendor-Specific Header.

EVENT_COUNTER_CONTROL_REG Event Counter Control.

EVENT_COUNTER_DATA_REG Event Counter Data.

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Figure 3-30 Event Counter Register Access

EVENT _COUNTER_CLEAR [1:0] 1:0

EVENT _COUNTER_ENABLE [2:0] 4:2

EVENT _COUNTER_EVENT _SELECTION [11:8] 27:24

EVENT _COUNTER_EVENT _SELECTION [7:0] 23:16

EVENT _COUNTER_LANE_SELECT [3:0] 11:8


RST
EN

Group i

Event j

event
Lane k

Event Counter
* Group 0
* Event 0 Software Write
* Lane 0

.
.
EVENT_COUNTER_CONTROL_REG
.
RST
EN

Software
Read
event

Event Counter
* Group i EVENT_COUNTER_DATA_REG
* Event j
* Lane k

Event Counter Data Details


The following tables provide the Group/Event numbers which are required when using the
EVENT_COUNTER_CONTROL_REG viewport control register to read each of the event counters. Some of the
event counters only exist for specific configurations. Groups 5-7 are implemented in RAM as indicated. The
group # is set by EVENT_COUNTER_EVENT_SELECTION[11:8]and the event # is set by
EVENT_COUNTER_EVENT_SELECTION[7:0]

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Table 3-33 Event Counter Group #0 (4-bit Layer1 Error Counter Per-Lane)

Event # Description Note

0x00 EBUF Overflow -

0x01 EBUF Under-run -

0x02 Decode Error -

0x03 Running Disparity Error -

0x04 SKP OS Parity Error Gen3 Only

0x05 SYNC Header Error Gen3 or greater

0x06 Rx Valid de-assertion RxValid de-assertion without EIOSs

0x07 CTL SKP OS Parity Error Gen4

0x08 1st Retimer Parity Error Gen4

0x09 2nd Retimer Parity Error Gen4

0x0A Margin CRC and Parity Error Gen4

Table 3-34 Event Counter Group #1 (8-bit Layer1 Error Counter Common-Lane)

Event # Description Note

0x00 Reserved -

0x01 Reserved -

0x02 Reserved -

0x03 Reserved -

0x04 Reserved -

0x05 Detect EI Infer -

0x06 Receiver Error -

0x07 Rx Recovery Request When the controller receives TS1 OS in L0s state.

Timeout when the controller's Rx condition is in


0x08 N_FTS Timeout
Rx_L0s.FTS.

0x09 Framing Error Gen3

0x0A Deskew Error -

Table 3-35 Event Counter Group #2 (8-bit Layer2 Error Counter Common-Lane)

Event # Description Note

0x00 BAD TLP -

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Event # Description Note

0x01 LCRC Error -

0x02 BAD DLLP -

0x03 Replay Number Rollover -

0x04 Replay Timeout -

0x05 Rx Nak DLLP -

0x06 Tx Nak DLLP -

0x07 Retry TLP -

Table 3-36 Event Counter Group #3 (8-bit Layer3 Error Counter Common-Lane)

Eventa # Description Note

0x00 FC Timeout -

0x01 Poisoned TLP Any function

0x02 ECRC Error Any function

0x03 Unsupported Request Any function

0x04 Completer Abort Any function

0x05 Completion Timeout Any function

a. Malformed TLP, FC & DL Protocol errors are excluded because of low frequency.

Table 3-37 Event Counter Group #4 (4-bit Layer1 Non-Error Counter Per-Lane)

Event # Description Note

0x00 EBUF SKP Add -

0x01 EBUF SKP Del -

Table 3-38 Event Counter Group #5 (32-bit Layer1 Non-Error Counter [RAM] Common Lane)

Event # Description Note

0x00 L0 to Recovery Entry -

0x01 L1 to Recovery Entry -

0x02 Tx L0s Entry -

0x03 Rx L0s Entry -

(DSP): Send PM_Active_State_Nak


0x04 ASPM L1 reject
(USP): Received PM_Active_State_Nak

0x05 L1 Entry -

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Event # Description Note

0x06 L1 CPM CX_L1_SUBSTATES_ENABLE

0x07 L1.1 Entry CX_L1_SUBSTATES_ENABLE

0x08 L1.2 Entry CX_L1_SUBSTATES_ENABLE

(CX_L1_SUBSTATES_ENABLE)
0x09 L1 short duration No. of times link entered L1.0 state but exited to L0
without entering L1.1 or L1.2 states

(CX_L1_SUBSTATES_ENABLE)
No. of times link entered L1.2_Entry state but is forced
0x0A L1.2 abort to exit to L1.0 then L0 because it saw clkreq# asserted
while in this state

0x0B L2 Entry -

0x0C Speed Change Gen2

0x0D Link width Change x2

0x0E Reserved -

Table 3-39 Event Counter Group #6 (32-bit Layer2 Non-Error Counter [RAM])

Event # Description Note

0x00 Tx Ack DLLP -

0x01 Tx Update FC DLLP -

0x02 Rx Ack DLLP -

0x03 Rx Update FC DLLP -

0x04 Rx Nullified TLP -

0x05 Tx Nullified TLP -

0x06 Rx Duplicate TLP -

Table 3-40 Event Counter Group #7 (32-bit Layer3 Non-Error Counter [RAM])

Event # Description Note

0x00 Tx Memory Write -

0x01 Tx Memory Read -

0x02 Tx Configuration Write -

0x03 Tx Configuration Read -

0x04 Tx IO Write -

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Event # Description Note

0x05 Tx IO Read -

0x06 Tx Completion without data -

0x07 Tx Completion w data -

0x08 Tx Message TLP PCIe VC only

0x09 Tx Atomic -

0x0A Tx TLP with Prefix -

0x0B Rx Memory Write -

0x0C Rx Memory Read -

0x0D Rx Configuration Write -

0x0E Rx Configuration Read -

0x0F Rx IO Write -

0x10 Rx IO Read -

0x11 Rx Completion without data -

0x12 Rx Completion w data -

0x13 Rx Message TLP PCIe VC only

0x14 Rx Atomic -

0x15 Rx TLP with Prefix -

CCIX VC Only (PCIe Compatible TLP or CCIX


0x16 Tx CCIX TLP
Optimized TLP)

CCIX VC Only (PCIe Compatible TLP or CCIX


0x17 Rx CCIX TLP
Optimized TLP)

You can inspect the VTB test case ft_ras_des_event_count.sv at


Hint <workspace>/doc/html/vtb/testenv/index.html for programming examples. For more
information on VTB, see the “Integrating the Controller and VIP using VTB” section in the
“Integration” chapter of the User Guide.

Limitations
If the controller (PMC) is running on aux_clk during the measurement:
■ The measurement timers (TIME_BASED_DURATION_SELECT: 1 ms, 10 ms, …, 2 s, 4 s) have measure-
ment error less than 4 us.

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■ The measurement timers and event timers of all the events are stopped temporarily when aux_-
clk_active/pm_sel_aux_clk are controlled. Figure 3-31 describes the timing details when aux_-
clk_active/pm_sel_aux_clk are controlled.

Figure 3-31 No Measurement Period

No Measurement No Measurement

clk

pm_sel_aux_clk
䞉䞉䞉

aux_clk_active

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3.7 Messages
This section describes the processing of messages through the controller. The following topics are discussed:
■ “Message Generation” on page 153
■ “Message Reception” on page 164
For a proper understanding of messages you should be familiar with Section 2.2.8, “Message Request
Rules” of the PCI Express Base Specification, Revision 4.0, Version 1.0.
■ Messages (Msg/MsgD1) are posted transactions.
■ Vendor Defined and PTM messages are Msg / MsgD.
■ Set Slot Power Limit, Invalidate Request, and LN messages are MsgD.
■ All other messages are Msg.
For more information, see “Interrupts” on page 170.

1. With payload.

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3.7.1 Message Generation


The following topics are discussed in this section:
■ “Overview”
■ “Vendor Defined Message (VDM) Generation” on page 157
■ “Latency Tolerance Reporting (LTR) Message Generation” on page 158
■ “Application Msg/MsgD Programming Examples” on page 162
■ “Byte Mapping of Third and Fourth Message Header Dwords At I/O Interfaces” on page 162

3.7.1.1 Overview

Messages that are transmitted by the controller are derived from the following sources:
■ the controller (automatically)
■ the controller (under the control of your application)
■ your application
■ the host/client software

For internally generated messages, or for messages generated at any of the SII
Note interfaces:
■ ID Based Ordering (IDO) is not supported.
■ The controller does not check the messages for TLP errors; instead it sends the TLP
as presented on the message interfaces.

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Figure 3-32 Message Transmission: SW Upstream Port


Optional

Customer Logic RAM RX PIPE


PCIe Protocol

Synopsys Specific RADM

iATU

Indirect supply of any CXPL Core PHY


4a
class of Msg/MsgD

Application Logic :
Transmit XADM
Direct supply of any
4
class of Msg/MsgD
XALI1 TX PIPE

RAM

Application Logic :
Tx Vendor Messages
2 Error Signalling
5 Vendor Defined VMI

Application Logic :
Optional System Status/
Control Registers
Legacy PCI CLK/RST
7 SII: Interrupt Signals MSG_GEN
Interrupt
13 PTM Request

9 LTR Request SII: LTR Message Generation Signals


PTM
Power
1
Management
SII: Power Management Signals

App Error
8
Signalling
SII: Transmit Control Signals

3 LTR Clear

12 DRS/FRS

PMC

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Figure 3-33 Message Transmission: SW Downstream Port


Optional

Customer Logic RAM


PCIe Protocol

Synopsys Specific
RADM RX PIPE

LBC

CDM Core
Registers
Slot
Capabilities
CXPL Core
PHY
iATU

Indirect supply of any


4a
class of Msg/MsgD

Application Logic : TX PIPE


RAM
Transmit XADM
Direct supply of any
4
class of Msg /MsgD
XALI1

11 Set_Slot_Power_Limit
Application Logic :
Tx Vendor Messages
5 Vendor Defined VMI

Application Logic :
Optional System Status/
MSG_GEN 13 PTM Response
Control Registers
Locked CLK/RST
6 SII: PM, Unlock, and Error Messages
Transaction
PTM
Power
1
Management
SII: Power Management Signals

10 OBFF SII: OBFF Message Generation

For definitions of acronyms used for block and interface names, see “Terms and Descriptions” on page 17.

Table 3-41 Types of Transmitted Messages

Message Source
Index (Type) SW (Upstream Port) SW (Downstream Port)

Power Management For more information, see “Power For more information, see “Power
1
interface (Msg) Management” on page 213. Management” on page 213.

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Message Source
Index (Type) SW (Upstream Port) SW (Downstream Port)

COR_ERR / ERR_NONFATAL /
ERR_FATAL.
Error Signaling inside
2 For more information, see NA
the controller (Msg)
“Reliability, Availability, and
Serviceability (RAS)” on page 124.

For more information, see “Latency


Tolerance Reporting (LTR)
3 LTR Clear (Msg) NA
Message Generation” on page
158.

XALI0/1/2
Direct Supply of any
4 class of message For more information on how to generate a message at the XALI0/1/2
(Msg/MsgD) interface, see “Transmit Client Interface Protocol Rules” on page 279 and
“Application Msg/MsgD Programming Examples” on page 162.

For more information on generating Msg/MsgD from MWr/IOWr using an


Indirect Supply of any internal address translation unit (ATU), see “IO/MEM to Msg/MsgD Type
4a class of message Translation” on page 185.
(Msg/MsgD) For more information on the supported methods of Msg/MsgD generation,
see Table 3-43 and Table 3-44.

The controller generates Vendor Defined messages in response to requests


5 Vendor Defined (Msga)
on the VMI (see “Vendor Message Interface (VMI)” on page 305).

Unlock message, triggered by root


Locked Transaction
6 NA complex application logic through the
(Msg)
app_unlock_msg pin.

Legacy PCI Interrupt SII interrupt signals sys_int and


7 NA
(Msg) dp_intx.

The controller generates Error


Signaling messages in response to
application requests on the SII
Error Signaling from app_err* I/O. It is also possible to
8 NA
your application (Msg) generate Error messages through
the client interfaces. For more
information, see items 4 and 4a in
this table.

For more information, see “Latency


Tolerance Reporting (LTR)
9 LTR Request (Msg) NA
Message Generation” on page
158.

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Message Source
Index (Type) SW (Upstream Port) SW (Downstream Port)

OBFF messages, triggered by your


application logic through the
app_obff_obff_msg_req/app_obff_
Optimized Buffer Flush
10 NA idle_msg_req/app_obff_cpu_activ
Fill (OBFF) (Msg)
e_msg_req inputs. For more
information, see “OBFF Message
Generation” on page 159.

Set_Slot_Power_Limit message,
Set_Slot_Power_Limit triggered by writing to the Slot
11 NA
(MsgD) Capabilities register through the DBI, or
when LTSSM enters L0.

For more information, see


12 DRS/FRS (Msg) “Readiness Notifications (RN)” on NA
page 261.

13 PTM PTM Request (Msg) PTM Response (Msg/MsgD)

For more information, see “Precision Time Measurement (PTM)” on page


263.

a. MsgD transmission not possible on Vendor Message Interface (VMI). For more information, see “Vendor Defined
Message (VDM) Generation” on page 157. However, it is possible through (4).

3.7.1.2 Vendor Defined Message (VDM) Generation

VDMs can be generated by your application using any of the following methods:
■ The controller generates VDMs in response to requests on the VMI.
■ The VMI can be used to send Msg only. It does not support message with payload (MsgD).
■ The inputs ven_msg_fmt[1:0]and ven_msg_len[9:0] should be set to 0x1 and 0x0 respectively to
indicate 4-DWORD header and no payload.
■ VDMs created by you at the VMI are always subject to translation by the “Internal Address Transla-
tion Unit (iATU)” on page 178.

■ It is preferable to use the SII interface to send a VDM.


Note

■ Direct supply of Msg and MsgD TLPs at XALI0/1/2 .


■ Direct supply of I/O and MEM TLPs at XALI0/1/2 to be converted to VDM. The optional internal
address translation unit (iATU) can convert I/O and MEM TLPs to VDM TLPs. For more information,
see “IO/MEM to Msg/MsgD Type Translation” on page 185.

You must use 64-bit addressing when you are using the Direct supply method of VDM
Caution generation. For more information, see Figure 3-37 .

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3.7.1.3 Latency Tolerance Reporting (LTR) Message Generation

You can enable LTR message generation by setting CX_LTR_M_ENABLE =1. You can generate LTR messages
using any of the following methods:
■ The controller generates LTR messages in response to requests made by your application logic on the
SII input see app_ltr_msg_req.
■ Direct supply of Msg TLPs at XALI0/1/2 .
■ Direct supply of I/O and MEM TLPs at XALI0/1/2 to be converted to LTR messages. The iATU can
convert I/O and MEM TLPs to Msg TLPs. For more information, see “IO/MEM to Msg/MsgD Type
Translation” on page 185.
When the LTR is changing fast and dynamically with the data stream, the LTR message should be
synchronized with the data stream and transmitted over the cores XALI0/1/2 interfaces . For applications
where the LTR is changing slowly or is static, then you can transmit the LTR message over the SII message
interface. In that case, it is assumed that the LTR message is guided by software and the SII message
interface is externally stimulated by software (by writing to a memory mapped application register whose
outputs are driving the SII inputs). When you are using the SII interface you should drive the contents of the
LTR message header on the app_ltr_msg_latency[31:0] input. It has the same format as LTR messages
described in the PCIe specification.
The actual values in the LTR message transmitted by this upstream port are captured in the port logic LTR
Latency Register (PL_LTR_LATENCY_OFF). They are also reflected on the app_ltr_latency[31:0]output.
The values in the LTR Max Snoop and No-Snoop Latency register (LTR_LATENCY_REG) are reflected on the
cfg_ltr_max_latency output.

Figure 3-34 LTR Registers


LTR Port
Logic
Registers

LTR Msg
transmitted
SII or XALI0/1/2 to
XADM
TX wire

Device
cfg_ltr_m_en
Control 2
Registers

cfg_ltr_max_latency[31:0] LTR
Capability
(platform configured
max latency)
Registers

app_ltr_latency[31:0]
( reported latency)

The controller automatically generates a new LTR message with the Requirement bits set to 0 for both
Snoop and No-Snoop latencies when:

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■ A function is directed to a non-D0 state through a write to the Power State field of the Power Manage-
ment Control and Status register, and the LTR mechanism is active since the last DL_Down to DL_Up
transition.
or
■ The LTR mechanism is disabled by clearing the LTR Mechanism Enable field of the Device Control 2
register. This field is cleared through a CFG write or a function level reset (FLR).
■ By setting DISABLE_AUTO_LTR_CLR_MSG field of the MISC_CONTROL_1_OFF register to 1, the auto-
matic generation of the LTR clear message in the above situations can be disabled.
You must not send an LTR message when the LTR Mechanism Enable bit of the Device Control 2 Register is
0. When this bit is 0, the controller does not block transmission of LTR messages that you generate. The
value of the LTR Mechanism Enable bit is reflected on the cfg_ltr_m_en output.

■ It is preferable to use the SII interface to send LTR messages.


Note

3.7.1.4 OBFF Message Generation

You can enable OBFF message generation by setting CX_OBFF_SUPPORT. You can generate OBFF messages
using any of the following methods:
■ The controller generates OBFF messages in response to requests made by your application logic on the
SII app_obff_*_msg_req inputs.
■ Direct supply of Msg TLPs at XALI0/1/2 .
■ Direct supply of I/O and MEM TLPs at XALI0/1/2 to be converted to OBFF messages. The optional
iATU) can convert I/O and MEM TLPs to Msg TLPs. For more information, see “MEM or I/O Match
Modes” on page 224.
You must not send an OBFF message when the OBFF Enable field of the Device Control 2 Register
(DEVICE_CONTROL2_DEVICE_STATUS2_REG) is 00. When this field is 00, the controller does not block
transmission of OBFF messages that you generate. The value of the OBFF Enable field is reflected on the
cfg_obff_en[1:0] output.
When you configure the controller to support either variation (A or B) of OBFF messages (through the OBFF
Enable field of the Device Control 2 Register (DEVICE_CONTROL2_DEVICE_STATUS2_REG), and your
application sends an OBFF message when the controller is in the L0s or L1 TX states, then the controller
transitions to the L0 state and transmits the message. According to the PCI Express Base Specification, Revision
4.0, Version 1.0, the controller should drop a Variation A message in this scenario. Therefore, your
application must not send Variation A OBFF messages when the controller is in the L0s or L1 TX states.
Your application must monitor the pm_linkst_in_l0s, pm_linkst_in_l1sub, and pm_linkst_in_l1
outputs. For the purpose of controller optimization the controller does not do this check; your application
must do the check.

■ It is preferable to use the SII interface to send OBFF messages.


Note

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3.7.1.5 OBFF Wake Signal Encoder Reference Design

An optional example WAKE Signal Encoder design, that you can integrate into your application logic, is
provided at <workspace>/src/customer/generic/obff_wake_ref*. It translates OBFF requests (from
the same source that is driving the controller inputs app_obff_obff_msg_req,
app_obff_cpu_active_req, and app_obff_idle_msg_req) to WAKE# patterns

Note You must verify the integration of the example encoder/decoder in your design.

Figure 3-35 Encoder Example Design in (DSP)


Application WAKE# from USP to wake up main power and PCIe reference clock IN

ref_clk Encoder pullup


rst_n (obff_wake_ref_enc)
(tristate buffer)

Request type of WAKE # app_owre_idle '0' OUT


signalling pattern to Tx .
Waveform oe WAKE#
app_owre_obff Encoder owre_wake IO
Encoder asserts owre _grant (active low )
when request is accepted . app_owre_cpu_act OUT_EN
You must keep the request
signals asserted until the
encoder asserts the grant . owre_grant
I/O PAD
Current FSM
state for debug .
owre_cur_state
Not equal to
OBFF code .
cfg_wk_max_pls_wdt
cfg_wk_min_pls_wdt
Determine pulse
cfg_wk_max_f2f_wdt width and edge -to-
edge timing .
cfg_wk_min_f2f_wdt

PCIe Core

Table 3-42 OBFF WAKE# AC Specification (Table 2.6.2 of PCIe Specification)

Symbol Parameter Min Max Unit Relationship to Timing Inputs

TWKRF WAKE# rise-fall time 100 ns NA

Minimum WAKE# pulse width;


TWAKE-TX-MIN applies to both
300 ns cfg_wk_min_pls_wdt * TCK_PERIODa
-PULSE active-inactive-active and
inactive-active-inactive cases.

Maximum WAKE# pulse width;


applies to both
active-inactive-active and
N/A inactive-active-inactive Set to 500 ns cfg_wk_max_pls_wdt * TCK_PERIOD
less than 50% of
{cfg_wk_max_f2f_wdt *
TCK_PERIOD }

TWAKE-FALL-F Time between two falling min = cfg_wk_min_f2f_wdt * TCK_PERIOD


ALL-CPU-ACTIV WAKE# edges when signalling 700 1000 ns max = cfg_wk_max_f2f_wdt *
E CPU Active. TCK_PERIOD

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a. Period of the clock this is running to detect wakeup events.

Figure 3-36 Wake Event from EP to RC (Unrelated to OBFF Signalling)

WAKE# from downstream function to wake up main power and PCIe reference clock

owrd_wake_idle
owrd_wake_obff '1'
`RC
owrd_wake_cpu_act Decoder wake_rx
owrd_wake_err (obff_wake_ref_dec) IN
IN pullup
`EP
owrd_cur_state
device_type
(tristate_buffer)
app_owre_idle
'0' OUT
app_owre_obff Encoder owre_wake
oe
Application `RC IO
app_owre_cpu_act Encoder
(obff_wake_ref_enc) wake_tx
owre_grant OUT_EN
`EP
owre_cur_state

PCIe DM Core
(RC Mode) wake#
PMC I/O PAD for WAKE#
(u_pm_ctrl )
device_type
DM in RC Mode

DM in EP Mode
WAKE# from downstream function to wake up main power and PCIe reference clock

owrd_wake_idle
owrd_wake_obff '1'
`RC
owrd_wake_cpu_act wake_rx
Decoder
owrd_wake_err (obff_wake_ref_dec)
`EP IN
IN
owrd_cur_state
device_type
(tristate_buffer)
app_owre_idle
'0' OUT
app_owre_obff oe
Application `RC
`RC IO
app_owre_cpu_act Encoder wake_tx
owre_grant (obff_wake_ref_enc) OUT_EN
`EP
`EP
owre_cur_state

PCIe DM Core
(EP Mode) wake#
PMC I/O PAD for WAKE#
(u_pm_ctrl )
device_type

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3.7.1.6 Application Msg/MsgD Programming Examples

The following tables enumerate the different ways that your application can generate Msg and MsgD TLPs.

Table 3-43 Msg Without Payload Transmission Methods

Applicatio
n Interface Description Application I/O Signals

client1_tlp_type =MSG
client1_tlp_fmt[1:0] =01
client1_tlp_byte_len =0
Direct Supply using a Msg transaction.
client1_tlp_byte_en =message Code
client1_tlp_addr[31:0] =header bytes 12-15
client1_tlp_addr[63:32] =header bytes 8-11
XALI0/1/2
Indirect Supply (iATU) using an MWra transaction.
The iATU needs to be configured to translate MWr client1_tlp_type =MSG
to Msg TLPs.
client1_tlp_byte_len =0
A MWr with an “effective length of 0” is converted
client1_tlp_byte_en =00000000
to Msg and all other MWr TLPs are converted to
MsgD.

The controller generates Vendor Defined messages in response to requests on the VMI. For
VMI
more information, see “Vendor Message Interface (VMI)” on page 305.

Table 3-44 Msg With Payload Transmission Methods

Application
Interface Description Application I/O Signals

client1_tlp_type =MSG
client1_tlp_fmt[1:0] =11
client1_tlp_byte_len !=0
Direct Supply using a Msg transaction.
client1_tlp_byte_en =message Code
client1_tlp_addr[31:0] =header bytes 12-15
XALI0/1/2
client1_tlp_addr[63:32] =header bytes 8-11

Indirect Supply (iATU) using a MWr


transaction client1_tlp_type =MEM
The iATU needs to be configured to translate client1_tlp_byte_len !=0
MWr to MsgD TLPs.

VMI MsgD is not supported.

3.7.1.7 Byte Mapping of Third and Fourth Message Header Dwords At I/O Interfaces

Figure 3-37 indicates the byte mapping between the message generation interfaces and the third and fourth
DWORDs of the message TLP header. For more information, see:
■ Descriptions of client0_tlp_addr and client0_tlp_data at “Transmit Interfaces (XALI0/1/2)” on
page 279.

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■ Description of ven_msg_data at “Vendor Message Interface (VMI)” on page 305.


■ “Advanced Information: Endianness” on page 1003.

Figure 3-37 Transmitted 3rd and 4th DWORD Message Header Byte Mapping at Interfaces
SII.MESSAGE 31 bytes 12-15
(app _msg_*) 0
0

63 bytes 8-11
VMI
(ven_msg_data) 32
31 bytes 12-15
0
P
XALI0/1/2 Core I
Logic P
63 E
1
32 bytes 8-11

31
0
0

0x0 0
bytes 12-15

Byte 15 is in position [7:0]


4-dword header for 4-dword headers

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3.7.2 Message Reception


The following topics are discussed in this section:
■ “Overview”
■ “Message Reception I/O Interfaces” on page 166
■ “Routing of Received Messages” on page 166
■ “Latency Tolerance Reporting (LTR) Message Reception” on page 166
■ “OBFF Message Reception” on page 167
■ “Further Information” on page 169

3.7.2.1 Overview

The PCI Express controller can receive the following types of messages. The index in the first column refers
to the circled numbers in the following diagrams.

Table 3-45 Types of Received Messages

Message Source
Index (Type) SW (Upstream Port) SW (Downstream Port)

Power Management For more information, see “Power For more information, see “Power
1
(Msg). Management” on page 213. Management” on page 213.

Slot Power Limit Set_Slot_Power_Limit Support


1a NA
(MsgD) message

Error Signaling from


COR_ERR / ERR_NONFATAL /
2 Downstream NA
ERR_FATAL
Component (Msg).

Vendor Defined
3 For more information, see “Routing of Received Messages” on page 166.
(Msg/MsgD).

Locked Transaction
4 Unlock message NA
(Msg).

Legacy PCI Interrupts


For more information, see “Interrupts” on
5 from Downstream NA
page 170.
Devices (Msg).

For more information, see “Latency


LTR Request and
6 NA Tolerance Reporting (LTR) Message
Clear (Msg).
Reception” on page 166.

OBFF messages received on the


Optimized Buffer radm_msg_cpu_active/radm_msg
7 Flush Fill (OBFF) _idle/radm_msg_obff outputs. For NA
(Msg). more information, see “OBFF
Message Reception” on page 167.

8 PTM PTM Response (Msg/MsgD) PTM Request (Msg)

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Message Source
Index (Type) SW (Upstream Port) SW (Downstream Port)

For more information, see “Precision Time Measurement (PTM)” on page


263.

Figure 3-38 Message Reception: Upstream Port

Customer Logic RAM


PCIe Protocol

Synopsys Specific
TRGT1 RADM RX PIPE

3 Vendor Defined 8 PTM Response


Application Logic :
Rx Vendor Messages CXPL Core PHY
VMI

4
Locked PTM
Transaction

SII: PM, Unlock, and Error Messages

Slot Power
1a
Limit

SII: Power Management Signals


TX PIPE
Application Logic : RAM
7 OBFF
Optional System Status/
Control Registers SII: OBFF Message Generation

Power
1
Management CLK/RST

SII: Power Management Signals


PMC

Figure 3-39 Message Reception: Downstream Port

Customer Logic RAM


PCIe Protocol

Synopsys Specific
TRGT1 RADM RX PIPE

3 Vendor Defined 8 PTM Request


Application Logic :
Rx Vendor Messages CXPL Core PHY
VMI

2 Error Signalling PTM

SII: PM, Unlock, and Error Messages

Legacy PCI
5
Interrupt

SII: Interrupt Signals


Application Logic : TX PIPE
LTR
Optional System Status/
6
Request/Clear
RAM
Control Registers SII: LTR Message Generation Signals

Power
1
Management CLK/RST

SII: Power Management Signals


PMC

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For definitions of acronyms used for block and interface names, see “Terms and Abbreviations” on page 17.

3.7.2.2 Message Reception I/O Interfaces

The RADM filter provides a message interface that is grouped as part of the System Information Interface
(SII)to handle the message TLPs received from the upstream component. The RADM filter processes the
message and decodes the header before sending it to your application logic on the SII. Some of the message
reception signals are also used in “Interrupts” on page 170 and “Reliability, Availability, and Serviceability
(RAS)” on page 124.

3.7.2.3 Routing of Received Messages

All1 error-free MSG requests are decoded internally, signaled on the SII interface, and then dropped (not
forwarded to your application2 on TRGT1. When a MSG request is filtered with UR/CA/CRS status, the
TLP is always dropped.

Summary of Message Delivery


Note
■ By default received messagesa (Msg/MsgD) are delivered (without the payload for
MsgD) on the SII interface and are notb delivered on the TRGT1 interface.
■ The SII message reception interface provides1 the requester ID and message type
(from the first and second TLP DWORDs) and the contents of the third and fourth TLP
DWORDs.
■ If you also want the message delivered on the TRGT1 interface, then you must clear
the corresponding filter mask bit.
For more information, see “Advanced Information: Advanced Filtering and Routing of
TLPs” on page 954.

a. Except PTM
b. The exception to this is an ATS Invalidation Request which is too big and is delivered on the TRGT1 interface regard-
less of filter mask settings

3.7.2.4 Latency Tolerance Reporting (LTR) Message Reception

You can enable LTR message reception by setting CX_LTR_M_ENABLE. When the controller receives an LTR
message, it pulses the radm_msg_ltr output. You can access the LTR message information on the
radm_msg_payload output, which is part of the SII message interface. The actual values in the LTR message
received by this downstream port are captured in the port logic LTR Latency Register
(PL_LTR_LATENCY_OFF). They are also reflected on the app_ltr_latency[31:0]output.

1. Except PTM .
2. Vendor TYPE0 messages generate an UR error.

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Figure 3-40 LTR Registers

LTR Port
Logic
Registers

LTR Msg
received

from RX
RADM
wire

app_ltr_latency[31:0]
(reported latency)

When you configure the controller with a 256-bit datapath, and when two LTR messages are received in the
same clock cycle (back-to-back), the earlier message is discarded.

■ It is preferable to use the SII interface to receive LTR messages. The bridge master
Note cannot support reception of LTR messages.

3.7.2.5 OBFF Message Reception

You can enable OBFF message reception by setting CX_OBFF_SUPPORT. When you configure the controller
with a 256-bit datapath, and when two OBFF messages are received in the same clock cycle (back-to-back),
the earlier message is discarded. When you have not enabled OBFF in the Device Control 2 register, or when
the Traffic Class is non-zero; then the controller generates an UR completion when it receives an OBFF
message. When the upstream port receives an OBFF message, it pulses one of the radm_msg_obff,
radm_msg_cpu_active, or radm_msg_idle outputs. Your application logic must use these outputs to
control the traffic it generates. For more information, see PCI Express Base Specification, Revision 4.0, Version
1.0.

■ It is preferable to use the SII interface to receive OBFF messages. The bridge master
Note cannot support reception of OBFF messages.

An optional WAKE Signal Decoder example design, that you can integrate into your application logic, is
provided at workspace/src/customer/generic/obff_wake_ref*. It translates WAKE# patterns to the
corresponding OBFF codes. When it receives a reserved OBFF code, it decodes it as a CPU_ACTIVE event.

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Figure 3-41 Decoder Example Design (USP)


Application Decoder
(obff_wake_ref_dec)
ref_clk Asynchronous low reset with a synchronous de -assertion to
ref_clk. Only one reset cycle is required to reset the logic
rst_n associated with the corresponding clock .

app_init Error reset: one cycle pulse to reset the decoder into the state specified
by app _idle, app _obff, or app_cpu_act.
app_idle
Used when your application detects (one cycle pulse on
app_obff owrd_wake_err) that the decoder has received an invalid WAKE #
pattern (for example, a valid inactive pulse after a valid active pulse
app_cpu_act drives the OBFF code from IDLE to CPU _ACT, but the falling -to-falling
width is smaller than the minimum falling edge -to-falling edge width ).

owrd_wake_idle Waveform
1-cycle pulse
owrd_wake_obff Decoder
indicating type
of WAKE #
pattern received owrd_wake_cpu_act wake IN
pullup
owrd_wake_err

Current FSM
(tristate buffer)
state for debug .
owrd_cur_state
'0' OUT
Not equal to
oe WAKE#
OBFF code .
cfg_wk_max_pls_wdt IO

cfg_wk_min_pls_wdt OUT_EN
Determine pulse
cfg_wk_max_f2f_wdt width and edge -to-
edge timing .
cfg_wk_min_f2f_wdt I/O PAD

PCIe Core

wake
(active high )

Note You must fully verify the integration of the example encoder/decoder in your testbench.

Table 3-46 OBFF WAKE# AC Specification (Table 2.6.2 of PCIe Specification)

Symbol Parameter Min Max Unit Relationship to Timing Inputs

TWKRF WAKE# rise-fall time 100 ns NA

Minimum WAKE# pulse width;


TWAKE-TX-MIN applies to both
300 ns cfg_wk_min_pls_wdt * TCK_PERIODa
-PULSE active-inactive-active and
inactive-active-inactive cases.

Maximum WAKE# pulse width;


applies to both
active-inactive-active and
N/A inactive-active-inactive Set to 500 ns cfg_wk_max_pls_wdt * TCK_PERIOD
less than 50% of
{cfg_wk_max_f2f_wdt *
TCK_PERIOD }

TWAKE-FALL-F Time between two falling min = cfg_wk_min_f2f_wdt * TCK_PERIOD


ALL-CPU-ACTIV WAKE# edges when signalling 700 1000 ns max = cfg_wk_max_f2f_wdt *
E CPU Active. TCK_PERIOD

a. Period of the clock this is running to detect wakeup events.

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3.7.2.6 Further Information

■ For specific information on how the handling of a message is affected by its error status, see
“Advanced Information: Advanced Error Handling for Received TLPs” on page 981 and“Advanced
Information: Advanced Filtering and Routing of TLPs” on page 954.
■ For more information on optional address translation of VDMs, see “MSG/MSGD Match Mode” on
page 195.
■ For more information on ordering considerations, see “Advanced Information: Advanced Ordering
Information” on page 968.

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3.8 Interrupts
The following section describes the processing of interrupts in the controller. You should be familiar with
the different types of interrupts as specified in Sections 6.1.1, “Rationale for PCI Express Interrupt Model”,
6.1.4, “Message Signaled Interrupt (MSI/MSI-X) Support”, 6.1.2, “PCI Compatible INTx Emulation”, and
6.1.3, “INTx Emulation Software Model” of the PCI Express Base Specification, Revision 4.0, Version 1.0.
■ “Interrupt Generation (USP)” on page 171
■ “Interrupt Reception (DSP)” on page 175

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3.8.1 Interrupt Generation (USP)

3.8.1.1 Overview

An USP creates MSI’s using MWr requests. Your application logic issues MSI requests through the MSI
interface; the controller then generates the corresponding memory write. Alternatively, your application
logic can create the MSI MWr and supply it on a XALI0/1/2 Tx interface .

Figure 3-42 Example MSI Application Logic (MSI_CAP_ENABLE =1)


MSI Generation Method A MSI Generation Method B
(SII MSI Interface) (Normal Traffic Interface)
PCIe core PCIe core

Traffic Ar biter Traffic Ar biter


Normal Traffic Normal Traffic
Lo Lo
A Tx A Tx
MWr D MWr D
Message Generator Hi Hi
XALI0/1/2 or
AXI
Slave Interface

MSI Capability MSI Capability


1 1
Capability/Control Capability/Control
Request/
Lower Address A Lower Address
Grant A
Handshake Upper Address Upper Address
D D
Data Data
Mask Bits 5 Mask Bits 5
Pending Bits Pending Bits
cfg_msi_pending[31:0]

cfg_msi_pending[31:0]
cfg_msi_addr[63:0]

cfg_msi_data[15:0]

cfg_msi_mask[31:0]
cfg_msi_mask[31:0]
ven_msi_vector[4:0]
ven_msi_grant

ven_msi_req

cfg_msi_en
cfg_msi_en

Your
Your
Application
Application
Logic
Logic

3 3
MSI FSM MSI FSM

5 5

Priority Encoder Priority Encoder

4 4

Clear Clear
Pending Pending
Bit Bit

Pending Bit Array[31:0] Pending Bit Array[31:0]


Example for 64-bit with PVM;
2 2
32 Single-function non-VF. 32
Local Interrupt Lines Local Interrupt Lines

An MSI-X interrupt is identical to an MSI, except that it: supports more than 32 vectors (2048) through the
use of multiple address and data pairs that are written by software to an MSI-X Table. Your application
logic issues MSI requests through the MSI interface; the controller then generates the corresponding
memory write. Alternatively, your application logic can create the MSI MWr and supply it on a XALI0/1/2
Tx interface .

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Figure 3-43 Example MSI-X Application Logic Using SII MSI Interface (MSIX_CAP_ENABLE =1)

MSI Generation Method A


(SII MSI Interface)

Traffic Arbiter
Normal Traffic PCIe
Lo core
A
MWr D
Tx
Message Generator Hi

PCI Header BARS


MSI-X Capability 1 BAR 5
Capability /Control BAR 4
Request /
Table Offset BIR BAR 3
Grant
Handshake PBA Offset BIR BAR 2
BAR 1
BAR 0
ven_msi_grant

cfg_msix_table_of fset[28:0]

cfg_msix_table_bir[2:0]

cfg_bar5_start/limit[31:0]
cfg_bar4_start/limit[63:0]
cfg_bar3_start/limit[31:0]
cfg_bar2_start/limit[63:0]
cfg_bar1_start/limit[31:0]
cfg_bar0_start/limit[63:0]

cfg_bar0_start/limit[63:0]
cfg_bar1_start/limit[31:0]
cfg_bar2_start/limit[63:0]
cfg_bar3_start/limit[31:0]
cfg_bar4_start/limit[63:0]
cfg_bar5_start/limit[31:0]
cf g_msix_en =1
cfg_msix_func_mask =0

msix_addr[ 63:0]
msix_data[31:0]

cfg_msix_pba_bir[2:0]
cfg_msix_pba_offset[28:0]
N = cfg_msix_table_size[]
ven_msi_req

3
MSI-X FSM
+ +
5
Address Address
Priority Encoder 3 Decoder Decoder

D,A
rdata raddr r/ waddr
MSI-X Table Host Read
PBA Access
(N)
r/ wdata
Clear
Pending mask
Bit 1 Host Write
Set/ clear pending Access
bit control

2
N
Example for single -function non -VF.
Local Interrupt Lines Your Application Logic

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Figure 3-44 Example MSI-X Application Logic Using Normal Tx Interfaces

MSI Generation Method B


(Normal Traffic Interface)

Traffic Ar bi ter
Normal Traffic
PCIe
Lo core
A Tx
MWr D
Hi
XALI0/1/ 2 or
AXI
Slave Interface
PCI Header BARS
MSI-X Capability 1 BAR5
Capability/Control BAR4
Table Of fset BI R BAR3
PBA Of fset BI R BAR2
BAR1
BAR0

cfg_msix_table_bir[2:0]
cfg_msix_table_off set[ 28: 0]

cfg_bar5_start/limit [31:0]
cfg_bar4_start/limit [63:0]
cfg_bar3_start/limit [31:0]
cfg_bar2_start/limit [63:0]
cfg_bar1_start/limit [31:0]
cfg_bar0_start/limit [63:0]
cfg_msix_func_mask =0

cfg_bar0_start/limit [63:0]
cfg_bar1_start/limit [31:0]
cfg_bar2_start/limit [63:0]
cfg_bar3_start/limit [31:0]
cfg_bar4_start/limit [63:0]
cfg_bar5_start/limit [31:0]
cfg_msix_en =1

cfg_msix_pba_bir[2:0]

cfg_msix_pba_off set[ 28: 0]


N = cfg_msix_table_size[]

3
MSI-X FSM
+ +
5

D,A Address Address


Priority Encoder 3 Decoder Decoder

rdata raddr r/waddr


Host Read
5 MSI-X Table PBA Access
(N entries)
r/wdata
Clear
Pending mask
Bit 1 Host Write
Set/clear pending Access
bit control

2
N
Example for single-function non-VF.
Local Interrupt Lines Your Application Logic

MSI/MSI-X requests created at the MSI interface are given higher Tx priority than traffic at the
Note
XALI0/1/2 transmit interfaces . To preserve ordering, you should supply MSI/MSI-X MWr
requests at the XALI0/1/2 transmit interfaces .

PCI Legacy Interrupts (USP)


Your USP application asserts the level-sensitive sys_int input to notify the controller that it should send
an interrupt message. The controller generates two message TLPs, Assert_INTx and Deassert_INTx, in
response to the assertion and the de-assertion of this input. Your application needs to de-assert the virtual
interrupt inputs when the link has been placed in a low power state. The controller does not automatically
send a Deassert_INTx interrupt message when the power state changes.

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In addition, a SW USP generates Assert_INTx /Deassert_INTx messages when:


■ Your application logic asserts/de-asserts any of the dp_inti (where i=a,b,c,d) input signals to indi-
cate that your application logic's Virtual interrupt wires have changed state. Typically, SW logic
decodes these virtual wires from the SW DSPs radm_inti_asserted/radm_inti_deasserted
outputs (where i =a,b,c,d).
■ Any of these hot-plug (HP) events and the associated interrupt is enabled in the Slot Control register:
❑ Power Fault Detected
❑ MRL Sensor Changed
❑ Presence Detect Changed
❑ Command Completed
❑ Attention Button Pressed

Figure 3-45 Interrupt Handling in an Upstream Switch Port

S W DS P S W US P

radm_int _* A pplic ation


Interrupt Interrupt
Mes sage S witc h Logic Mes sage
Decoding Generation
dp_int*

Msg

A ss ert_ INTx /
Deass ert_ INTx
s ys_int *

Hot P lug E v ents

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3.8.2 Interrupt Reception (DSP)

3.8.2.1 Overview

PCI Legacy Interrupts (DSP)


The controller decodes received Assert_INTx/Deassert_INTx messages and pulses the
radm_inti_asserted and radm_inti_deasserted outputs where i=a,b,c,d.

PCI Express Hot-Plug Logic Interrupt and Wakeup (DSP)


When MSI or MSI-X is enabled, the controller asserts the hp_msi output upon detection of any of these HP
events:
■ Power Fault Detected
■ MRL Sensor Changed
■ Presence Detect Changed
■ Command Completed
■ Attention Button Pressed
■ Electromechanical Interlock Status Changed
■ Data Link Layer State Changed
When INTx interrupt mode is enabled, the controller asserts the hp_int output upon detection of any of
the hot-plug events. When PME mode is enabled, the controller asserts the hp_pme output upon detection of
any of the hot-plug events. The controller does not check if the PM state is D1, D2, or D3hot. Your
application must check the value on pm_dstate to make sure the device is in D1, D2, or D3hot upon receipt
of a hp_pme notification.

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3.9 Flow Control


The flow control mechanism is divided into two phases: initialization and update. The controller
automatically performs both of these phases with minimal support required from your application. By
default the RADM is responsible for returning flow control credits when it reads data out of the receive
queues.
The controller provides optional I/O signals to enable your application to handle flow control returns in an
application-specific manner. For error scenarios in bypass queue mode your application can decide whether
to return credits or not based on state of the Bypass/RTRGT1 Interface signals described in Table 3-47.

Table 3-47 Bypass/RTRGT1 Interface Signals to Consider for Credit Return


Bypass/RTRGT1 Interface Signal State Credit return policy

radm_bypass_tlp_abort
Asserted Credit needs to be returned
radm_trgt1_tlp_abort

radm_bypass_dllp_abort
Asserted Credit need not be returned
radm_trgt1_dllp_abort

Credit need not be returned.


radm_bypass_ecrc_err
Asserted But, it is strongly recommended to return the credit if the
radm_trgt1_ecrc_err
TLP is not ambiguous.

For more information, see “System Information Interface (SII)” on page 306 and “Advanced Information:
Advanced Error Handling for Received TLPs” on page 981. The controller does not return flow control
credits for packets that have data link layer errors.

Calculation of Initial Credits and Receive Buffer Sizes


The default buffer sizes and credits for each TLP type are automatically calculated from the number of
lanes, the controller datapath width, the maximum PCIe payload (CX_MAX_MTU), flow control update
latencies, internal delays, and the PHY latency. For more information, see “Advanced Information: Flow
Control Credit Calculation” on page 1030.
You can determine the transmit posted, non-posted, and completion credits that are advertised by the
receiver at the other end of the link by reading the following port logic registers:
■ Transmit Posted FC Credit Status (TX_P_FC_CREDIT_STATUS)
■ Transmit Non-Posted FC Credit Status (TX_NP_FC_CREDIT_STATUS)
■ Transmit Completion FC Credit Status (TX_CPL_FC_CREDIT_STATUS)

You can override the default flow control update latency timer value using the FC Latency
Note
Timer Override Value field (TIMER_MOD_FLOW_CONTROL) in the Queue Status register
(Q_STATUS).

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3.9.1 Scaled Flow Control


The controller supports Scaled Flow Control (DL_FEATURE_EN =1 followed by FC_SCALE_EN =1) as
described in PCI Express Base Specification, Revision 4.0, Version 0.7 with the following features and
limitations:
■ This feature when enabled applies individually to all P, NP, or CPL TLPs.
■ This feature when enabled applies to all VCs.
■ The allocated initial credits scale down to 127 header credits and 2047 data credits, if the link partner
does not support scaling.
■ At larger scaling factors, it is not possible to return single credits.
■ When scaling, the minimum number of header and data credits must be calculated as follows:
❑ Minimum Number of Header Credits =32 * Scaling Factor, and
❑ Minimum Number of Data Credits =512 * Scaling Factor.
■ When manually enabling Flow Control Scaling on a new configuration by editing the configuration
file (without going through the coreConsultant flow):
❑ If you are modifying the Header and Data credits, the scaling factors must be specified.
❑ If the Header and Data credits have default values, there is no need to add the scaling factors.
■ Due to a potential deadlock scenario, if an MRIOV_INIT is received during Data Link (DL) Feature
setup, the link immediately exits DL Feature, and starts transmitting INITFCs.
Note: Synopsys does not support, or recognize MRIOV DLLPs, outside of this scenario.

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3.10 Internal Address Translation Unit (iATU)


The controller uses the iATU to implement a local address translation scheme that replaces the TLP address
and TLP header fields in the current TLP request header. The topics for this section are:
■ “Configuring the iATU” on page 179
■ “Outbound Features” on page 180
■ “Outbound Limitations” on page 181
■ “Outbound Basic Operation (Address Match Mode)” on page 182
■ “Outbound Detailed Operation” on page 185
■ “Outbound Programming” on page 189
■ “Inbound Features” on page 191
■ “Inbound Limitations” on page 192
■ “Inbound Basic Operation” on page 193
■ “Inbound Detailed Operation” on page 197
■ “Inbound Programming” on page 203

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3.10.1 Configuring the iATU


The configuration parameters relevant to the iATU are described in Table 3-48.

Table 3-48 iATU Configuration Parameters

Parameter Name Parameter Label Value Range Default

CX_INTERNAL_ATU_ENABLE iATU Enable 1, 0 0

CX_ATU_NUM_OUTBOUND_REGIONS Number of Outbound Translation Regions 256,255,.....3,2,1,0 2

CX_ATU_NUM_INBOUND_REGIONS Number of Inbound Translation Regions 256,255,.....3,2,1,0 2

CX_ATU_MIN_REGION_SIZE Minimum Size of Translation Region 4, 8, 16, 32, 64 kB 64 kB

CX_ATU_MAX_REGION_SIZE Maximum Size of Translation Region 4 GB, 8 GB...16 ZB 4 GB

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3.10.2 Outbound Features


Address translation is used for mapping different address ranges to different memory spaces supported by
your application. A typical example maps your application memory space to PCI memory space. The iATU
also supports type translation. Without address translation, your application address is passed unmodified
to the TLPs directly through the Tx application interface. You can program the iATU to implement your
own outbound address translation scheme without external logic.
Outbound Features:
■ Address Match mode operation for MEM and I/O, CFG, and MSG TLPs. No translation for comple-
tions.
■ Supports type translation through TLP type header field replacement for MEM or I/O types to
MSG/CFG types.
❑ Includes posted to non-posted translation (for example, MWr to CfgWr0)
❑ No translation from completions
■ Programmable TLP header field replacement.
❑ TYPE/TC/AT/ATTR/MSG-Code/TH/PH/ST
■ Multiple (up to 256) address regions programmable for location and size.
■ Programmable enable/disable per region.
■ Automatic FMT field translation between three DWORDs and four DWORDs for 64-bit addresses.
■ Invert Address Matching mode to translate accesses outside of a successful address match.
■ Configuration Shift mode. Optimizes the memory footprint of CFG accesses destined for the Rx appli-
cation interface in a multifunction device.
■ Response code which defines the completion status to return for accesses matching a region.
■ Supports regions from 4 KB to 16 ZB in size.The minimum and maximum region sizes are determined
by CX_ATU_MIN_REGION_SIZE and CX_ATU_MAX_REGION_SIZE. Smaller region sizes consume extra
decode logic.
■ Payload Inhibit marks all TLPs as having no payload data.
■ Header Substitution replaces bytes 8 to 11 (for 3 DWORD header) or bytes 12 to 15 (for 4 DWORD
header), inclusive, of the outbound TLP header.
■ Tag Substitution of the outbound TLP tag field.
■ Function number bypass mode to allow function number information to be supplied from your appli-
cation transmit interface while translating the address and other attributes of the TLP.
■ TLP Header fields bypass mode to allow header information to be supplied from your application
transmit interface or, if AMBA is configured, from the AMBA sideband bus while translating the
address and Type of the TLP.

The default behavior of the ATU when there is no address match in the outbound direction or
Note
no TLP attribute match in the inbound direction, is to pass the transaction through.

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3.10.3 Outbound Limitations


■ Generation of ATS requests and messages not supported (no facility to insert NW and iTAG fields).

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3.10.4 Outbound Basic Operation (Address Match Mode)


The address field of each request MEM and I/O TLP is checked to see if it falls into any of the enabled1
address regions defined by the Start and End addresses as defined in Figure 3-48 on page 184. When an
address match is found, then the TLP address field is modified as follows:
Translated Address = Original Address - Base Address + Target Address
and the TYPE, TC, AT, TH, PH, ST, Function Number, and ATTR header fields are replaced with the
corresponding fields in the IATU_REGION_CTRL_1_OFF_OUTBOUND_0 register. When your application
(XALI0/1/2) address field matches more than one of the CX_ATU_NUM_OUTBOUND_REGIONS address
regions, then the first (lowest of the numbers from 0 to CX_ATU_NUM_OUTBOUND_REGIONS-1) enabled region
to be matched is used. For more information on what happens when there is no address match, see “No
Address Match Result” on page 186. This operational mode (called Address Match Mode) is always used for
outbound translation. Figure 3-46 to Figure 3-48 provides more information on this translation process.

Note The iATU does not translate DBI requests.

Figure 3-46 64-bit Region Mapping: Outbound and Inbound (Address Match Mode); INCREASE_REGION_SIZE=0
Region Size =
Untranslated Translated
End Address – Start Address
Upper Base Address Limit Address Address Map Address Map

31 0 31
* 0

0xFFFF

63 0 Region #n
End Address

Region #n

63 0

0x0000
Start Address 31 0 31
* 0

63 0 Upper Target Address Lower Target Address

0x0000
31 0 31
* 0

Upper Base Address Lower Base Address

Note: * is log2(CX_ATU_MIN_REGION_SIZE)

1. When the Region Enable bit of the Region Control 2 register is ‘0’, then that region is not used for address matching.

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Figure 3-47 64-bit Region Mapping: Outbound and Inbound (Address Match Mode); INCREASE_REGION_SIZE=1
Upper Upper Region Size =
Base Limit Untranslated Translated
End Address – Start Address
Address Address Limit Address Address Map Address Map

#
31 0 31
* 0

0xFFFF

63 0 Region #n
End Address

Region #n

63 0

0x0000

Start Address 31 0 31
* 0

63 0 Upper Target Address Lower Target Address

0x0000
31
Upper Base Address
0 31
*
Lower Base Address
0

Note: * is log2(CX_ATU_MIN_REGION_SIZE)

The CX_ATU_MIN_REGION_SIZE configuration parameter (4 kB - 64 kB) specifies the minimum size of an


address translation region. For example, when set to 64 kB, the lower 16 bits of the Base and Target registers
are zero, the lower 16 bits of the Limit register is 0xFFFF, and all address regions are aligned on 64 kB
boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero. In Figure 3-47, # is
CX_ATU_MAX_REGION_SIZE; if =0, Upper Limit Address register does not exist.
The INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i determines if the
maximum region size is 4 GB or is set by the CX_ATU_MAX_REGION_SIZE configuration parameter. This
only applies to 64-bit addressing.

The combination of region size and number of regions must not consume the maximum space
Caution
that is addressable with your 32-bit or 64-bit system address.

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Figure 3-48 32-bit Region Mapping: Outbound and Inbound (Address Match Mode)
Region Size =
Untranslated Translated
End Address – Start Address
Limit Address Address Map Address Map

31
* 0

0xFFFF

31 0 Region #n
End Address The resulting translated address space can
be 64-bits or 32-bits.

Region #n

63 0

0x0000

Start Address 31 0 31
* 0

31 0 Upper Target Address Lower Target Address

0x0000
31
* 0

Lower Base Address

Note: * is log2(CX_ATU_MIN_REGION_SIZE)

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3.10.5 Outbound Detailed Operation


The following advanced topics are discussed:
Default Operation
■ “RID BDF Number Replacement”
■ “IO/MEM to Msg/MsgD Type Translation” on page 185
■ “Writing to a MRdLk Region” on page 186
■ “No Address Match Result” on page 186
Optional Features
■ “Address Match Invert” on page 186
■ “General Bypass” on page 186
■ “TLP Header Field Translation Bypass” on page 187
■ “Payload Inhibit” on page 187
■ “Tag Substitution” on page 188

3.10.5.1 RID BDF Number Replacement

Overview: When there is a successful address match on an outbound TLP, then the function number used
in generating the function part of the requester ID1 field of the TLP is taken from the 3-bit Function Number
field of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i register. To override this behavior, use the “Function
Number Translation Bypass” on page 186.

3.10.5.2 IO/MEM to Msg/MsgD Type Translation

Overview: The iATU supports TYPE translation/conversion of MEM and I/O TLPs to Msg/MsgD TLPs.
When there is a successful address match on an outbound MEM TLP, and the translated TLP type field is
MSG (that is, the type field of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i register is 10xxx), then the
message code field of the TLP is set to the value in the Message Code field of the
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register. A MWr with an effective length of ‘0’ is converted to
Msg and all other MWr TLPs are converted to MsgD. For more information on generating messages, see
“Message Generation” on page 153

Caution The iATU does not translate outbound messages.

Usage Scenario: This is useful for applications that are unable to generate Msg/MsgD TLPs.

3.10.5.3 FMT Translation

Overview: The iATU automatically sets the TLP format field for three DWORDs when it detects all zeros in
the upper 32 bits of the translated address. Otherwise, it sets it to four DWORDs when it detects a 64-bit

1. Uses the 8:5:3 bit PCI Bus.Device.Function (BDF) format.

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address (that is, when there is a ‘1’ in the upper 32 bits of the translated address). When the original address
and the translated address are of different format, the iATU ensures that the TLP header size matches the
translated address format.

3.10.5.4 Writing to a MRdLk Region

Overview: When there is a successful address match for an outbound write and the type header field in the
IATU_REGION_CTRL_1_OFF_OUTBOUND_i register is “00001” indicating a locked MEM transfer, then the
controller sets the type field to “0000” (MEM).

3.10.5.5 No Address Match Result

Overview: When there is no address match then the address is untranslated but the TLP header information
(for fields that are programmable) comes from the relevant fields on the application transmit interface
XALI* or .

3.10.5.6 Address Match Invert

Overview: In normal operation an address match on an outbound TLP occurs when the untranslated
address is in the region bounded by the base address and limit address. When the invert feature is enabled,
an address match occurs when the untranslated address is not in the region bounded by the base address
and limit address.
Feature Configuration: To enable Invert feature, set the INVERT_MODE field of the
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to ‘1’.

3.10.5.7 General Bypass

Overview: When you set client0_tlp_iatu_bypass, the iATU does not process that transaction.

3.10.5.8 Function Number Translation Bypass

Overview: When function number translation bypass is enabled and region address is matched, the
function number of the translated TLP is taken from your application transmit interface and not from the
Function Number field of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i register .
Usage Scenario: This is useful for AXI-based SR-IOV applications where the upper bits of the AXI ID are
used to identify the source (PF or VF) of a request. These upper bits of the ID can be mapped to the function
number of the slave request PF/VF misc_info buses of the controller. There is then no need for the iATU to
translate the PF and VF information.
Feature Configuration: To enable function number translation bypass, set the FUNC_BYPASS field of the
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to ‘1’.

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3.10.5.9 TLP Header Field Translation Bypass

Overview: When TLP header field bypass is enabled and region address is matched, header fields of the
translated TLP are taken from your application transmit interface or, if AMBA is configured, from the
AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the
IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The
header fields are TC, AT, PH, TH, ST and Attr (IDO, RO and NS) fields.
Feature Configuration: To enable TLP header field bypass, set the TLP_HEADER_FIELDS_BYPASS field of
the IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to '1'.

3.10.5.10 Payload Inhibit

Overview: When payload inhibit is enabled and region address is matched, the iATU converts transactions
with data payload to TLPs without payload data by forcing the TLP header Fmt[1] bit =0, regardless of the
application inputs .
Note: This feature is not supported for MemWr/IOWr with data payload greater than 1DW.

This feature must not be used for outbound transactions with data poisoning, because the EP
Caution bit is set for TLPs without data payload, this is a violation of data poisoning rules defined in
section “2.7.2.2. Rules For Use of Data Poisoning” of the PCI Express Base Specification,
Revision 4.0, Version 1.0.

Usage Scenario: This is useful for Vendor Defined Msg (without data); your application sends a MWr but
does not set the byte write enables to 0.
Feature Configuration: To enable payload inhibit, set the INHIBIT_PAYLOAD field of
IATU_REGION_CTRL_2_OFF_OUTBOUND_i to ‘1’.

3.10.5.11 Header Substitution

Overview: When header substitution is enabled and region address is matched, the iATU fully substitutes
bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with
the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i.
Note: For a Vendor Defined Msg/MsgD having 4 DWORD header, when HEADER_SUBSTITUTE_EN =1, the
4th DWORD (bytes 12-15) is replaced with the contents of LWR_TARGET_RW field in the
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register. But regardless of the value of
HEADER_SUBSTITUTE_EN, the 3rd DWORD is replaced with the contents of UPPER_TARGET_RW field in the
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_i register. So for a Vendor Defined Msg, BDF (or reserved)
and Vendor ID must be programmed in UPPER_TARGET_RW.
Usage Scenario: This is useful for Vendor Defined Msg/MsgD and ATS transactions which is normally
inefficient requiring a very large iATU region.
Feature Configuration: To enable header substitution, set the HEADER_SUBSTITUTE_EN field in
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to ‘1’.

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3.10.5.12 Tag Substitution

Overview: When tag substitution is enabled and region address is matched, the iATU substitutes the TAG
field of the outbound TLP header with the contents of the TAG field in
IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_TPH_ENABLE =1): TAG substitution for MWr does not occur because this field (byte 6) in the TLP
header is the ST field. ST substitution can still take place using the MSG_CODE field in
IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Your application must not attempt to perform TAG substitution for outgoing non-posted TLPs.
Usage Scenario:
Feature Configuration: To enable tag substitution, set the TAG_SUBSTITUTE_EN field of the
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to ‘1’.

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3.10.6 Outbound Programming


This section discusses the register programming interface and provides details of programming examples.

3.10.6.1 iATU Outbound Programming Overview

You can access the iATU registers through the DBI interface or through BAR Matched Mem/IO requests.
The following registers are used for programming the iATU.

Table 3-49 iATU Register Map


Address Label (i = 0 to CX_ATU_NUM_OUTBOUND_REGIONS-1) Description

0x000 IATU_REGION_CTRL_1_OFF_OUTBOUND_i Region Control 1

0x004 IATU_REGION_CTRL_2_OFF_OUTBOUND_i Region Control 2

0x008 ATU_LWR_BASE_ADDR_OFF_OUTBOUND_i Lower Base Address

0x00C IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_i Upper Base Address

0x010 IATU_LIMIT_ADDR_OFF_OUTBOUND_i Limit Address

0x014 IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i Lower Target Address

0x018 IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_i Upper Target Address

0x01C IATU_REGION_CTRL_3_OFF_OUTBOUND_i Region Control 3

0x020 IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_i Upper Limit Address

The detailed descriptions for each register are given in DWC_pcie_ctl_sw_registers.pdf.

Table 3-50 iATU Register Address Bus Layout


Register Bit 31-20 19 18-17 16-9 8 7-2 1 0

Value Not used 0 Reserved Region Inbound/Outbound Register Address 0 1

Table 3-51 Example: Address Table for Accessing iATU Outbound Region 1 Configuration Registers
Register Bit Value

Address Register Name 31-20 19 18-17 16-9 8 7-2 1 0

0x200 Region Control 1 0 0 0 1 000

0x204 Region Control 2 0 0 0 1 004

0x208 Lower Base Address 0 0 0 1 008

0x20C Upper Base Address 0 0 0 1 00C

0x210 Limit Address 0 0 0 1 010

0x214 Lower Target Address 0 0 0 1 014

0x218 Upper Target Address 0 0 0 1 018

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For releases previous to 4.80a, the iATU registers have been programmed through an indirect
Attention addressing scheme using an index register (iATU_VIEWPORT_OFF), to reduce the address
footprint in the PCI Express extended configuration space. To use the legacy method of
accessing iATU registers, contact Synopsys support through SolvNet.

You can inspect the VTB test cases at <workspace>/doc/html/vtb/testenv/index.html


Note
for programming examples. For more information on VTB, see the “Integrating the Controller
and VIP using VTB” section in the “Integration” chapter of the User Guide.

3.10.6.2 Outbound iATU Programming Example

Define Outbound Region 1 as:


64 kB I/O region from 0x80000000_d000000 to 0x80000000_d000ffff, to be mapped to 0x00010000 in
the PCIe I/O space.
1. Setup the Region Base and Limit Address Registers.
Write 0xd0000000 to Address {0x208} to set the Lower Base Address.
Write 0x80000000 to Address {0x20C} to set the Upper Base Address.
Write 0xd000ffff to Address {0x210} to set the Limit Address.
2. Setup the Target Address Registers.
Write 0x00010000 to Address {0x214} to set the Lower Target Address.
Write 0x00000000 to Address {0x218} to set the Upper Target Address.
3. Configure the region through the Region Control 1 Register.
Write 0x00000002 to Address {0x200} to define the type of the region to be I/O.
4. Enable the region.
Write 0x80000000 to Address {0x204} to enable the region.

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3.10.7 Inbound Features


Address translation is used for mapping different address ranges to different memory spaces supported by
your application. A typical example maps your application memory space to PCI memory space. The iATU
supports type translation. Without address translation, your application address is passed from the TLPs
directly through the TRGT1 application interface. You can program the iATU to implement your own
inbound address translation scheme without external logic.
■ Programmable Match mode operation for MEM, I/O, CFG, and MSG TLPs. No translation for comple-
tions.
■ Selectable BAR Match mode operation for I/O and MEM TLPs.
❑ TLPs destined for the internal CDM (or ELBI) in an upstream port are not translated.
❑ TLPs that are not error-free (ECRC, malformed and so on) are not translated.1
■ Programmable TLP header field matching.
❑ TYPE/TD/TC/AT/ATTR/MSG-Code/TH/PH/ST
■ Multiple (up to 256) address regions programmable for location and size.
■ Programmable enable/disable per region.
■ Automatic FMT field translation between three DWORDs and four DWORDs for 64-bit addresses.
■ Invert Address Matching mode to translate accesses outside of a successful address match.
■ ECAM Configuration Shift mode to allow a 256 MB CFG1 space to be located anywhere in the 64-bit
address space.
■ Supports regions from 4 KB to 16 ZB in size.The minimum and maximum region sizes are determined
by CX_ATU_MIN_REGION_SIZE and CX_ATU_MAX_REGION_SIZE. Smaller region sizes consume extra
decode logic.
■ Single Address Location to allow all TLPs to be translated to a single address location.
■ Msg Type Match Mode to allow matching of any TLP of type Message.

The default behavior of the ATU when there is no address match in the outbound direction or
Note
no TLP attribute match in the inbound direction, is to pass the transaction through.

1. If DEFAULT_TARGET =1, UR/CA TLPs which are BAR matched for an ATU region are forwarded to the TRGT1 interface
and translated.

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3.10.8 Inbound Limitations


■ Generation of ATS requests and messages not supported (no facility to insert NW and iTAG fields).

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3.10.9 Inbound Basic Operation


This section discusses how the iATU processes inbound requests. The topics are:
■ “Overview”
■ “MEM or I/O Match Modes” on page 193
■ “CFG Match Mode” on page 195
■ “MSG/MSGD Match Mode” on page 195

3.10.9.1 Overview

The following translation rules and limitations apply:


■ When there is no match, then the address is untranslated. In addition,
❑ TLPs destined for the internal CDM or ELBI in an upstream port are not translated.
❑ TLPs that are not error-free (ECRC, malformed, and so on) are not translated.
■ Address translation of completions is not supported in Address Match mode.
The setting of the MATCH_MODE field in IATU_REGION_CTRL_2_OFF_INBOUND_i determines how iATU
inbound matching is done for each TLP type.

Table 3-52 Determination of Match Mode

TLP Type MATCH_MODE =0 MATCH_MODE =1

MEM or I/O Address Match Mode BAR Match Mode

CFG0 Routing ID Match Mode Accept Mode

MSG/MSGD Address Match Mode Vendor ID Match Mode

The main difference between inbound and outbound iATU operation is that the TLP type is
Note
never changed in the inbound direction. Instead, the type field is used for more precise
matching. Other fields can also be optionally used to further refine the matching process.
Another difference is that for MEM and I/O TLPs, you can select between address matching
(as used in outbound operation) or BAR matching. Normally, an endpoint uses BAR match
mode, and a root complex uses address mode as an root complex normally does not
implement BARs.

3.10.9.2 MEM or I/O Match Modes

Address Match Mode: The operation is similar to “Outbound Basic Operation (Address Match Mode)” on
page 182. The address field of each request TLP is checked to see if it falls into any of the enabled1 address
regions as shown in Figure 3-50. When an address match is found then the TLP address field is modified as
follows:
Address = Address - Base Address + Target Address

1. When the Region Enable bit of the Region Control 2 register is 0, then that region is not used for address matching.

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When the TLP address field matches more than one of the CX_ATU_NUM_INBOUND_REGIONS address
regions, then the first (lowest of the numbers from 0 to CX_ATU_NUM_INBOUND_REGIONS - 1)enabled region
to be matched is used.
BAR Match Mode
Looking for an address match is a two-step process.
1. The standard internal PCI Express BAR Matching mechanism checks if the address field of any MEM
and I/O request TLP falls into any address region defined by the enabled BAR addresses and masks.
2. When a matched BAR is found, then the iATU compares the BAR ID to the BAR Number (BAR_NUM)
field in the IATU_REGION_CTRL_2_OFF_INBOUND_i register for all enabled regions. Figure 3-49 and
Figure 3-50 on page 195 provide more information on inbound translation in BAR Match Mode.
When the PCIe controller is operating with 64-bit BARs, the operation is defined as in Figure 3-49 where * is
log2(BAR_MASK+1).

Figure 3-49 iATU Address Region Mapping: Inbound (BAR Match Mode), 64-bit BAR
Region Size = set by the BAR Mask
of the matched-BAR.
Untranslated Translated
Address Map Address Map
x = Matched-BAR number

Region #x
The resulting translated address space can
be 64-bits or 32-bits.

Region #x

63 0

0x0000

Start Address 31

Upper Target Address


0 31
*
Lower Target Address
0

63 0
eATU Region#x Register eATU Region#x Register

63 0

BAR#x

In address match mode, when the address range does not match one of its BAR ranges in an upstream port,
then the device rejects the request with unsupported request (UR) completion status and no translation
occurs. When the PCIe controller is operating with 32-bit BARs, the operation is defined as in Figure 3-50.

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Figure 3-50 iATU Address Region Mapping: Inbound (BAR Match Mode), 32-bit BAR
Region Size = set by the BAR Mask
of the matched-BAR.
Untranslated Translated
Address Map Address Map
x = Matched-BAR number

Region #x
The resulting translated address space can
be 64-bits or 32-bits.

Region #x

63 0

0x0000

Start Address 31
Upper Target Address
0 31
*
Lower Target Address
0

31 0
eATU Region#x Register eATU Region#x Register

31
* 0

BAR #x % is determined by BAR#x Mask Register

3.10.9.3 CFG Match Mode

The controller normally routes CFG TLPs (to the internal CDM or ELBI) without translation. The iATU only
translates CFG0 TLPs that the controller has routed to the TRGT1.
Accept Mode
In Accept Mode, the controller always accepts CFG0 TLPs even when the CFG bus number does not match
the current bus number of the device. The routing ID of received CFG0 TLPs are ignored when determining
a match.
Routing ID Match Mode
The operation is similar to “Outbound Basic Operation (Address Match Mode)” on page 182. The routing ID
of the inbound CFG0 TLP must fall within the Base and Limit of the defined iATU region for matching to
proceed. The iATU interprets the routing ID (Bytes1 8-11 of TLP header) as an address. This corresponds to
the upper 16 bits of the address in MEM and I/O transactions.

3.10.9.4 MSG/MSGD Match Mode

Address Match Mode


The third and fourth header DWORDs are treated as an address and are compared against the iATU Region
Base and Limit Address registers. For vendor defined messages this allows specific messages to be filtered
into memory at the target address. The Upper Base address should be set to Bus.Device.Function (BDF) and
Vendor ID. The Lower Base address can be used as a filter for specific messages.

1. For more information, see Figure 2-18 Request Header Format for Configuration Transactions in Section 2.2.7 Memory, I/O,
and Configuration Request Rules of the PCI Express Base Specification, Revision 4.0, Version 1.0.

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Vendor ID Match Mode


This mode is relevant for ID-routed vendor defined messages. The iATU ignores the routing ID (BDF) in
bits [31:16] of the third DWORD of the TLP header1, but compares it against the vendor ID in bits [15:0] of
the third DWORD of the TLP header (bytes2 10 and 11). This allows vendor defined messages to be filtered
against specific vendor IDs without needing to know the BDF number which might vary depending on the
PCI topology. Bits [15:0] of the Region Upper Base register should be programmed with the required vendor
ID as follows:
Region Upper Base[15:8] =byte 10
Region Upper Base[7:0] =byte 11
The lower base and limit register should be programmed to translate TLPs based on vendor-specific
information in the fourth DWORD of the TLP header.

For more information on generating messages, see “Message Generation” on page 153.
Hint
For a proper understanding of messages, you should be familiar with Section 2.2.8, Message
Request Rules of the PCI Express Base Specification, Revision 4.0, Version 1.0.

1. In Figure 2-25 Header for Vendor_Defined Messages in Section 2.2.8.6, Vendor_Defined Message of the PCI Express Base
Specification, Revision 4.0, Version 1.0.
2. In Figure 2-25 Header for Vendor_Defined Messages in Section 2.2.8.6, Vendor_Defined Message of the PCI Express Base
Specification, Revision 4.0, Version 1.0.

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3.10.10 Inbound Detailed Operation


The following advanced topics are discussed:
Default Operation
■ “FMT Translation”
Optional Features
■ “Optional Matching Fields” on page 197
■ “Single Address Location” on page 198
■ “CGF Shift” on page 200
■ “Response Code” on page 201
■ “Message Type Match” on page 201
■ “Fuzzy Type Match” on page 201
■ “Invert” on page 202

3.10.10.1 FMT Translation

The iATU automatically sets the TLP format field for three DWORDs when it detects all zeroed in the upper
32 bits of the translated address. Otherwise it sets it to four DWORDs when it detects a 64-bit address (when
there is a 1 in the upper 32 bits of the translated address). When the original address and the translated
address are of a different format then the iATU ensures that the TLP header size matches the translated
address format.

3.10.10.2 Optional Matching Fields

Overview: In address and BAR match modes, a successful address/BAR match can be optionally gated by
successful matching of the programmable TLP header fields (per region) mentioned in Table 3-53. When the
associated Match Enable bit is set, the TLP header field of an inbound TLP is matched to the programmed
TLP header field value.
Feature Configuration: Table 3-53 provides information on the registers to consider for TLP header field
matching.

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Table 3-53 Registers to Consider for TLP Header Field Matching

Match Enable Bit TLP Header Field Value to Match

TLP
Header
Field Field Register Field Register

TC TC_MATCH_EN TC

TD TD_MATCH_EN TD

ATTR ATTR_MATCH_EN ATTR IATU_REGION_CTRL_


TH TH_MATCH_EN TH 1_OFF_INBOUND_i

AT AT_MATCH_EN IATU_REGION_CTRL_ AT
2_OFF_INBOUND_i
PH PH_MATCH_EN PH

MSG_CODE_MATC
ST MSG_CODE
H_EN IATU_REGION_CTRL_
Message MSG_CODE_MATC 2_OFF_INBOUND_i
MSG_CODE
Code H_EN

Note Address translation only proceeds when compares on all enabled field are successful.

3.10.10.3 Single Address Location

Overview: Single address location feature has two modes of operation, fixed and circular buffer.
Fixed: When enabled and region address matches, the TLPs translates to a single address location as
determined by the target address register of the iATU region.
Received Message TLP Header Bytes 8 - 15 at TRGT1 Interface
Bytes 8 to 15 of the received TLPs header destined for TRGT1 are made available on radm_trgt1_
hdr_uppr_bytes irrespective of TLP translation. When radm_trgt1_hdr_uppr_bytes_valid is asserted
your application should use radm_trgt1_hdr_uppr_bytes along with radm_trgt1_data.The
radm_trgt1_hdr_uppr_bytes_valid is set only when an ATU match occurs for Single Address Location
enabled region.
For example, if a received MsgD matches a Single Address Location enabled ATU region, bytes 8 to 15 of the
MsgD header are available on radm_trgt1_hdr_uppr_bytes when
radm_trgt1_hdr_uppr_bytes_valid is asserted, and radm_trgt1_hv is true. The available
radm_trgt1_hdr_uppr_bytes can be concatenated with radm_trgt1_data and used by your
application.

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■ The width of radm_trgt1_hdr_uppr_bytes is FLT_Q_ADDR_WIDTH bits.


Note
■ For radm_trgt1_hdr_uppr_bytes[63:32] to exist FLT_Q_ADDR_WIDTH must be
64.
■ If 32 < FLT_Q_ADDR_WIDTH < 64, radm_trgt1_hdr_uppr_bytes[FLT_Q_AD-
DR_WIDTH-1:32] =0.

Circular Buffer: In this mode, the first TLP translates to a single address location as determined by the
target address register of the iATU region. But, for subsequent TLPs, the target address increments by a
programmable increment size (CBUF_INCR), each time a region address matches. You can program the
increment size using CBUF_INCR field of the IATU_LIMIT_ADDR_OFF_INBOUND_i register (the maximum
increment size is 8192; this incorporates the maximum VDM data payload of 4096 and 2 DWs of header
radm_trgt1_hdr_uppr_bytes). On reaching the circular buffer window size, the target address wraps
around, and resets to single location base address. The controller uses the output signal
radm_trgt1_atu_cbuf_err to notify your application if the region matched received VDM size is greater
than the programmed circular buffer increment size (CBUF_INCR).

Figure 3-51 Circular Buffer Operation

Upper Target Address Limit Address


31 0 31
* 0

0xFFFF
When target address =
Translated
63 0 Single Location Base Address +
Address Map 4 Circular Buffer Window Size,
End Address
target address is wrapped around to Single Location
Circular Buffer Base Address
Window
Third translation to Single Location Base Address +
3
2 * CBUF_INCR (and so on ...)
Circular Buffer Window Size =
End Address – Single Location Base Address 2 Second translation to Single Location Base Address
+ CBUF_INCR

First translation to Single Location Base Address

63 0

0x0000
31 0 31
* 0

Upper Target Address Lower Target Address

* = log2(CX_ATU_MIN_REGION_SIZE)

The controller output port radm_trgt1_atu_sloc_match can be used as IRQs for any
Note VDM received which is processed in the iATU using the circular buffer feature.

Usage Scenario: The main usage scenario is translation of Messages (such as Vendor Defined or ATS
Messages) to MWr TLPs when the AXI bridge is enabled.

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Feature Configuration: To enable single address location feature, set the SINGLE_ADDR_LOC_TRANS_EN
field of the IATU_REGION_CTRL_2_OFF_INBOUND_i register to ‘1’. Table 3-54 describes additional
configuration settings for choosing the single address location operation mode.
Steps to Program ATU Circular Buffer Registers
1. Write to Upper Target Address, Lower Target Address, and Limit Address (all inbound) registers for
start and end address values of Circular Buffer window for the ATU region.
2. Set SINGLE_ADDR_LOC_TRANS_EN =1 to enable single location address.
3. Write the desired increment value to the CBUF_INCR field of the IATU_LIMIT_ADDR_OFF_INBOUND_i
register. This enables the circular buffer feature.

Table 3-54 Setting the Single Address Location Operation Mode

Fixed Circular Buffer

IATU_LIMIT_ADDR_OFF_INBOUND_i.
CBUF_INCR >0

IATU_LIMIT_ADDR_OFF_INBOUND_i. IATU_REGION_CTRL_2_OFF_INBOUND_i.
CBUF_INCR =0 SINGLE_ADDR_LOC_TRANS_EN =1

CX_ATU_SLOC_CBUF =1(default)

CX_ATU_MAX_REGION_SIZE =0

3.10.10.4 CGF Shift

Overview: Inbound CFG transactions routed to the Rx application interface can exist anywhere in address
space, because the PCIe controller filter processes the routing ID (BDF) as bits [31:16] of an address. This
BDF changes according on the PCIe bus topology. Bits [15:12] of the third DWORD1 of CFG TLPs are
reserved. The CFG shift feature uses this fact to reduce the memory requirement. The CFG shift feature
shifts/maps the BDF (bits [31:16] of the third header DWORD, which would be matched against the Base
and Limit addresses) of the incoming CfgRd0/CfgWr0 down to bits[27:12] of the translated address.
CFG1 Transactions
For CfgRd1/CfgWr1 transactions, the base and limit addresses could enclose the entire 32-bit 4 GB memory
space with the routing ID forming the upper 16 bits. The target address maps these CFG transactions to
anywhere in application address space.
Usage Scenario: This is useful for CFG transactions where the PCIe configuration mechanism maps bits
[27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be
located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits
[31:16] of the untranslated address to form bits [27:12] of the translated address.
Feature Configuration: To enable CFG shift (compressor) feature, set the CFG_SHIFT_MODE field of the
IATU_REGION_CTRL_2_OFF_INBOUND_i register to ‘1’.

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3.10.10.5 Response Code

Overview: Based on the setting of the response code field of the IATU_REGION_CTRL_REG_2_INBOUND_i
register (2b00: Normal RADM filter response, 2b01: UR, or 2b10: CA), the controller sets the completion
status field of completion TLPs, sent in response to successfully matched non-posted TLPs. When the
response code field is set to 2b00, then the normal receive filter response for this TLP is used.

Response Code feature is not available in regions where Single Address Location
Note Enable is set.

Feature Configuration: To enable response code feature, set the RESPONSE_CODE field of the
IATU_REGION_CTRL_2_OFF_INBOUND_i register!=‘00’.

3.10.10.6 Message Type Match

Overview: When this feature and “Single Address Location” on page 198 is enabled, the iATU matches
Msg/MsgD TLP Type field with TYPE field of IATU_REGION_CTRL_1_OFF_INBOUND_i register.
If “Fuzzy Type Match” on page 201 is also enabled, then any Msg received is matched (that is, Msg Type's
sub-field r[2:0], which specifies the Message routing mechanism, is ignored).

The Message should be consumed by your application before the next message arrives
Caution as all messages go to the same address.

If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN is set for any region, then you must


Note ensure that the same TLP cannot be matched in any other region where
SINGLE_ADDRESS_LOCATION_TRANSLATE_EN is not set. If this happens
radm_trgt1_hdr_uppr_bytes could have incorrect data.

Usage Scenario: This feature can be used for translation of VDM or ATS messages when AXI bridge is
configured on client interface.
Feature Configuration: To enable message type match feature, set the MSG_TYPE_MATCH_MODE field of the
IATU_REGION_CTRL_2_OFF_INBOUND_i register to =‘1’.

3.10.10.7 Fuzzy Type Match

Overview: When this feature is enabled, the iATU relaxes the matching of the TLP type field against the
expected type field so that:
■ CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1.
■ MWr, MRd, and MRdLk TLPs are seen as identical.
■ The routing field of MsgD TLPs is ignored.

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■ Atomic Ops TLPs - FetchAdd, Swap, and CAS are seen as identical.
For example, CFG0 in the type field in the IATU_REGION_CTRL_1_OFF_INBOUND_i register matches
against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP. To enable this feature, set the Fuzzy Type
Match Mode bit of the IATU_REGION_CTRL_OFF_2_INBOUND_i register.
Feature Configuration: To enable fuzzy type match feature, set the FUZZY_TYPE_MATCH_CODE field of the
IATU_REGION_CTRL_2_OFF_INBOUND_i register to =‘1’.

3.10.10.8 Invert

Overview: Normally an address match on an inbound TLP occurs when the untranslated address is in the
region bounded by the Base address and Limit address. When the invert feature is enabled, an address
match occurs when the untranslated address is not in the region bounded by the Base address and Limit
address.
Usage Scenario: This feature is supported only when all regions of that type are set to address match mode.
Feature Configuration: To enable invert feature, set the INVERT_MODE field of the
IATU_REGION_CTRL_2_OFF_INBOUND_i register to =‘1’.

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3.10.11 Inbound Programming


This section discusses the register programming interface and provides details of programming examples.

3.10.11.1 iATU Inbound Programming Overview

You can access the iATU registers through the DBI interface or through BAR Matched Mem/IO requests.
The following registers are used for programming the iATU.

Table 3-55 iATU Register Map


Address Label (i = 0 to CX_ATU_NUM_INBOUND_REGIONS-1) Description

0x100 IATU_REGION_CTRL_1_OFF_INBOUND_i Region Control 1

0x104 IATU_REGION_CTRL_2_OFF_INBOUND_i Region Control 2

0x108 ATU_LWR_BASE_ADDR_OFF_INBOUND_i Lower Base Address

0x10C IATU_UPPER_BASE_ADDR_OFF_INBOUND_i Upper Base Address

0x110 IATU_LIMIT_ADDR_OFF_INBOUND_i Limit Address

0x114 IATU_LWR_TARGET_ADDR_OFF_INBOUND_i Lower Target Address

0x118 IATU_UPPER_TARGET_ADDR_OFF_INBOUND_i Upper Target Address

0x11C IATU_REGION_CTRL_3_OFF_INBOUND_i Region Control 1

0x120 IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_i Upper Limit Address

Table 3-56 iATU Register Address Bus Layout


Register Bit 31-20 19 18-17 16-9 8 7-2 1 0

Value Not used 0 Reserved Region Inbound/Outbound Register Address 0 1

Table 3-57 Example: Address Table for Accessing iATU Inbound Region 1 Configuration Registers
Register Bit Value

Address Register Name 31-20 19 18-17 8 7-2 1 0

0x300 Region Control 1 0 0 0 100

0x304 Region Control 2 0 0 0 104

0x308 Lower Base Address 0 0 0 108

0x30C Upper Base Address 0 0 0 10C

0x310 Limit Address 0 0 0 110

0x314 Lower Target Address 0 0 0 114

0x318 Upper Target Address 0 0 0 118

0x31C Region Control 3 0 0 0 118

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Register Bit Value

Address Register Name 31-20 19 18-17 8 7-2 1 0

0x320 Upper Limit Address 0 0 0 118

The detailed descriptions for each register are given in DWC_pcie_ctl_sw_registers.pdf.

For releases previous to 4.80a, the iATU registers have been programmed through an indirect
Attention addressing scheme using an index register (iATU_VIEWPORT_OFF), to reduce the address
footprint in the PCI Express extended configuration space. To use the legacy method of
accessing iATU registers, contact Synopsys support through Solvnet.

You can also inspect the VTB test cases at


Note
<workspace>/doc/html/vtb/testenv/index.html for programming examples. For more
information on VTB, see the “Integrating the Controller and VIP using VTB” section in the
“Integration” chapter of the User Guide.

3.10.11.2 Inbound Programming Examples

Address Match Mode Example


Define Inbound Region 0 as, MEM region matching TLPs with addresses in the range 0x00010000 to
0x0005ffff mapped to 0x1000_0000_2000_0000 - 0x1000_0000_2004_ffff in your application
memory space.
1. Setup the Region Base and Limit Address Registers.
Write 0x00010000 to Address {0x108} to set the Lower Base Address.
Write 0x00000000 to Address {0x10C} to set the Upper Base Address.
Write 0x0005ffff to Address {0x110} to set the Limit Address
2. Setup the Target Address Registers.
Write 0x20000000 to Address {0x114} to set the Lower Target Address.
Write 0x10000000 to Address {0x118} to set the Upper Target Address.
3. Configure the region through the Region Control 1 Register.
Write 0x00000000 to Address {0x100} to define the type of the region to be MEM.
4. Enable the region.
Write 0x80000000 to Address {0x104} to enable the region in address match mode.

BAR Match Mode Example

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Define Inbound Region 2 as MEM region matching BAR4 (BAR match mode) mapping to
0x8000_0000_2000_0000 in your application memory space.

1. Setup the Target Address Registers.


Write 0x20000000 to Address {0x508} to set the Lower Target Address.
Write 0x80000000 to Address {0x50C} to set the Upper Target Address.
2. Configure the region through the Region Control 1 Register.
Write 0x00000000 to Address {0x500} to define the type of the region to be MEM.
3. Enable the region for BAR Match Mode.
Write 0xC0000400 to Address {0x504} to enable the region for BAR match mode for BAR#4.
Note: Default number of inbound regions is 2 (CX_ATU_NUM_INBOUND_REGIONS), so region 2 is not
accessible by default.

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3.11 Gen2/3/4/5 Speed Modes

3.11.1 Gen2 5.0 GT/s Operation


The controller supports all of the non-optional Gen2 5.0 GT/s features defined in the PCI Express Base
Specification, Revision 4.0, Version 1.0. The interface between the controller and the PHY is compliant with
PIPE Specification for PCI Express, Version 4.4.1. The controller supports two different mechanisms of
achieving the Gen2 rate: dynamic frequency and dynamic width.
■ For dynamic frequency configurations, the number of active symbols on the PIPE is constant and the
frequency of the controller doubles each time as the controller transitions from Gen1 => Gen2 rate.
■ When supporting dynamic width, the clock frequency of the controller remains constant and the
number of active symbols on the PIPE doubles each time as the controller transitions from Gen1 =>
Gen2 rate.

For more information on supported clock frequencies and datapath widths, see “Frequency,
Note Speed, and Width Support” on page 29.

3.11.1.1 Gen2 Speed Changing

When you set the default of the Directed Speed Change field of the Link Width and Speed Change Control
register (GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE) using the DEFAULT_GEN2_SPEED_CHANGE
configuration parameter to 1, then the speed change is initiated automatically after link up, and the
controller clears the contents of GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE. If you want to prevent this
automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2
register (LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before
link up.
To manually initiate the speed change then:
■ Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device
■ De-assert GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE in the local device
■ Assert GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE in the local device
The controller uses the mac_phy_rate output to negotiate the link data rate. It changes the rate signal and
waits for a pulse on the phy_mac_phystatus signal to confirm that the PHY has accepted the requested
rate. For core_clk considerations when changing speed, see “Gen2, Gen3, Gen4, or Gen5 Speed Changing
Considerations (CX_FREQ_STEP_EN =1)” on page 57.

As per the PCI Express Base Specification, Revision 4.0, Version 1.0, the controller
Note does not implement the optional Compliance Receive bit for Gen1 configurations.

3.11.2 Gen3 8.0 GT/s Operation


The controller supports all of the non-optional Gen3 8.0 GT/s features defined in the PCI Express Base
Specification, Revision 4.0, Version 1.0. The interface between the controller and the PHY is compliant with

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PIPE Specification for PCI Express, Version 4.4.1. The controller supports two different mechanisms of
achieving the Gen3 rate: dynamic frequency and dynamic width.
■ For dynamic frequency configurations, the number of active symbols on the PIPE is constant and the
frequency of the controller doubles each time as the controller transitions from Gen1 => Gen2 => Gen3
rates.
■ When supporting dynamic width, the clock frequency of the controller remains constant and the
number of active symbols on the PIPE doubles each time as the controller transitions from Gen1 =>
Gen2 => Gen3 rates.

For more information on supported clock frequencies and datapath widths, see “Frequency,
Note Speed, and Width Support” on page 29.

3.11.2.1 Gen3 Speed Changing

See “Gen2 Speed Changing” on page 206.

3.11.2.2 Gen3 8.0 GT/s Transmitter Equalization

The controller performs link equalization during link training to improve signal quality by adjusting the
transmitter and receiver equalization parameters for each lane on each side of the link. There are three
modes for the mapping of presets to coefficients, selectable at configuration time using the
CX_GEN3_EQ_PSET_COEF_MAP_MODE parameter:

■ Dynamic PHY: The coefficients are dynamically mapped in the PHY. This is the default mode.
■ Dynamic MAC: The coefficients are dynamically mapped in the MAC.
■ Programmable Table: The coefficients are programmed in a table by your application.
There are two feedback modes for determining the optimal equalization settings, programmable using the
Gen3 EQ Control Register (GEN3_EQ_CONTROL_OFF).
■ Figure of merit (FOM)
■ Direction change with optional convergence support

For more information on the EQ procedure and a usage guide, see “Advanced
Hint Information: Gen3/4/5 Equalization Details and Example” on page 897.

3.11.3 Gen4 16.0 GT/s Operation


The controller supports the Gen4 16.0 GT/s feature defined in the PCI Express Base Specification, Revision 4.0,
Version 1.0. The interface between the controller and the PHY is compliant with PIPE Specification for PCI
Express, Version 4.4.1. The controller supports two different mechanisms of achieving the Gen4 rate:
dynamic frequency and dynamic width.
■ For dynamic frequency configurations, the number of active symbols on the PIPE is constant and the
frequency of the controller doubles each time as the controller transitions from Gen1 => Gen2 => Gen3
=> Gen4 rates.

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■ When supporting dynamic width, the clock frequency of the controller remains constant and the
number of active symbols on the PIPE doubles each time as the controller transitions from Gen1 =>
Gen2 => Gen3 rates => Gen4.

For more information on supported clock frequencies and datapath widths, see “Frequency,
Note Speed, and Width Support” on page 29.

3.11.3.1 Gen4 Speed Changing

See “Gen2 Speed Changing” on page 206.

3.11.3.2 Gen4 16.0 GT/s Transmitter Equalization

The controller performs link equalization during link training to improve signal quality by adjusting the
transmitter and receiver equalization parameters for each lane on each side of the link. There are three
modes for the mapping of presets to coefficients, selectable at configuration time using the
CX_GEN3_EQ_PSET_COEF_MAP_MODE parameter:

■ Dynamic PHY: The coefficients are dynamically mapped in the PHY. This is the default mode.
■ Dynamic MAC: The coefficients are dynamically mapped in the MAC.
■ Programmable Table: The coefficients are programmed in a table by your application.
There are two feedback modes for determining the optimal equalization settings, programmable using the
Gen3 EQ Control Register (GEN3_EQ_CONTROL_OFF).
■ Figure of merit (FOM)
■ Direction change with optional convergence support

For more information on the EQ procedure and a usage guide, see “Advanced
Hint Information: Gen3/4/5 Equalization Details and Example” on page 897.

3.11.3.3 Gen4 Lane Margining

The controller supports all mandatory PIPE message bus interface features specified in PIPE Specification for
PCI Express, Version 4.4.1, except for elastic buffer depth control and generation of read command from the
controller to PHY. Figure 3-52 to Figure 3-58 describe the lane margining operation.

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Figure 3-52 Start Margining


Step Margin : Respon se
No
Margin Status Command Setu p for margin margining in progress
Software
IF
No Step Margin: Tim/Left
Margin Control Command Offset: 0x1

MAC LTSSM L0

Error Count[5:0] Don’t care 0 1

Sample Count[6:0] Don’t care 0 3 7


Margin Margin command =
left/offset=0x1 Tim + StartMagin
cmd addr data cmd addr data
M2P_MessageBus[7:0] 0x0 WU 0x1 0x1 WC 0x0 0x3 0x0 WA 0x0 WA 0x0 WA 0x0 WA 0x0

PIPE Margin statu s


Sample Erro r Sample
Cnt=0x3 Cnt=0x1 Cnt=0x7
P2M_MessageBus[7:0] 0x0 WA 0x0 WC 0x0 0x1 0x0 WC 0x1 0x3 0x0 WC 0x2 0x1 0x0 WC 0x1 0x7 0x0

Step Margin : Tim/Left


Margining function DISABLE
Offset: 0x1

Error Count[5:0] 0 1
PHY
Used only when IndErrorSampler=1
Sample Count[6:0] 0 3 5 6 7

Used only when IndErrorSampler=1 and SampleReportingMethod=0

Note:
If the DEFAULT_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH is less than 2 for PIPE 5.1.1 or 1 for PIPE 4.4.1, the Controller sends only write_committed command instead of
using write_uncommitted command.
Margin Margin co mmand =
left/offset=0x1 Tim + StartMagin
cmd addr data cmd addr data
M2P_MessageBus[7:0] 0x0 WC 0x1 0x1 0x0 WC 0x0 0x3 0x0

P2M_MessageBus[7:0] 0x0 WA 0x0 WA 0x0

Figure 3-53 Stop Margining


Step Margin: Response
No Clear
Go To No No
Comm Error
Margin Status margining in progress Normal Command Command
Software and Log

IF
No Clear
Step Margin: Tim/Left Go To No No
Margin Control Offset: 0x5
Comm
Normal Command
Error
Command
and Log

MAC LTSSM
Error Count[5:0] 1 Don’t care

Sample Count[6:0] 8 9 Don’t care

Stop Margin
cmd addr data
M2P_MessageBus[7:0] 0x0 WA 0x0 WC 0x0 0x0 0x0 WA 0x0

PIPE Sample
Margin status
Cnt=0x9
P2M_MessageBus[7:0] 0x0 WC 0x1 0x9 0x0 WA 0x0 WU 0x2 0x2 WC 0x0 0x1 0x0

Margining Step Margin: Tim/Left


DISABLE
Offset: 0x5
function

Error Count[5:0] 1 2 0
PHY
Used only when IndErrorSampler=1
Sample Count[6:0] 8 9 0

Used only when IndErrorSampler=1 and SampleReportingMethod=0

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Figure 3-54 Offset Change


Step Margin: Resp onse Step Margin: Resp onse
No
Margin Status margining in progress Command Setu p for margin margining in progress
Software
IF
Step Margin: Tim/Left No Step Margin: Tim/Left
Margin Control Offset: 0x1 Command Offset: 0x2

MAC LTSSM L0

Error Count[5:0] 1 Don’t care 0

Sample Count[6:0] 5 6 Don’t care 0 3


Margin
offset=0x2
cmd addr data
M2P_MessageBus[7:0] 0x0 WA 0x0 WC 0x1 0x2 0x0 WA 0x0 WA 0x0 WA

PIPE Sample Sample


Margin status
Sample
Cnt=0x6 Cnt=0x7 Cnt=0x3
P2M_MessageBus[7:0] 0x0 WC 0x1 0x6 0x0 WC 0x1 0x7 0x0 WA 0x0 WC 0x0 0x1 0x0 WC 0x1 0x3 0x0

Step Margin: Tim/Left Step Margin: Tim/Left


Margining function Offset: 0x1 Offset: 0x2

Error Count[5:0] 1 0
PHY
Used only when IndErrorSampler=1
Sample Count[6:0] 5 6 7 0 3 5

Used only when IndErrorSampler=1 and SampleReportingMethod=0

Figure 3-55 NAK Response


Step Margin: Response
No Clear
No Go To No No
Comm Error
Margin Status Command Setup for margin NAK Normal Command Command
Software and Log

IF
No Clear
No Step Margin: Voltage/Up Go To No No
Margin Control Command Offset: 0x5
Comm
Normal Command
Error
Command
and Log

MAC
LTSSM L0

Margin Margin command =


up/offset=0x5 Vol + StartMagin Stop Margin
cmd addr data cmd addr data cmd addr data
M2P_MessageBus[7:0] 0x0 WU 0x1 0x5 WC 0x0 0x1 0x0 WA 0x0 WC 0x0 0x0 0x0 WA 0x0

PIPE Margin status Margin status

P2M_MessageBus[7:0] 0x0 WA 0x0 WC 0x0 0x2 0x0 WA 0x0 WC 0x0 0x1 0x0

Margining
PHY DISABLE
function

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Figure 3-56 Recovery Transition (IndErrorSampler =0)


Step Margin: Response

Margin Status margining in progress


Software
IF
Step Margin: Tim/Left
Margin Control Offset: 0x1

MAC LTSSM L0 Recovery L0

Error Count[5:0] 3 4

Margin Margin
offset=0x0 offset=0x1
cmd addr data cmd addr data
M2P_MessageBus[7:0] 0x0 WC 0x1 0x0 0x0 WA 0x0 WC 0x1 0x1 0x0 WA 0x0

PIPE Margin status Margin status

P2M_MessageBus[7:0] 0x0 WA 0x0 WC 0x0 0x1 0x0 WA 0x0 WC 0x0 0x1 0x0

Step Margin: Tim/Left Step Margin: Tim/Left Step Margin: Tim/Left


Margining function Offset: 0x1 Offset: 0x0 Offset: 0x1
PHY

Note: This behaviour applies only when IndErrorSampler =0.


When IndErrorSampler=1 and LTSSM transitions to Recovery State, the controller doeS not issue any Margining commands to the PHY.

Figure 3-57 Clear Error Log


Step Margin: Resp onse Step Margin: Resp onse
Clear
No No
Error
Margin Status margining in progress Command Command margining in progress
Software Log

IF
Clear
Step Margin: Tim/Left No No Step Margin: Tim/Left
Margin Control Offset: 0x1 Command
Error
Command Offset: 0x1
Log

MAC LTSSM L0

Error Count[5:0] 0 1 0

Sample Count[6:0] 5 6

Error C ount Reset

M2P_MessageBus[7:0] 0x0 WA 0x0 WA 0x0 WC 0x0 0x7 0x0 WA 0x0

PIPE Erro r Sample Erro r


Cnt=0x1 Cnt=0x6 Cnt=0x0
P2M_MessageBus[7:0] 0x0 WC 0x2 0x1 0x0 WC 0x1 0x6 0x0 WA 0x0 WC 0x2 0x0 0x0 WC

Step Margin: Tim/Left


Margining function Offset: 0x1

Error Count[5:0] 0 1 0
PHY
Used only when IndErrorSampler=1
Sample Count[6:0] 5 6 7

Used only when IndErrorSampler=1 and SampleReportingMethod=0

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Figure 3-58 Exceeding Error Limit


Step Margin: Resp onse
No Clear
Go To No No
Comm Error
Margin Status margining in progress Too many Error Normal Command Command
Software and Lo g

IF
No Clear
Step Margin: Tim/Left Go To No No
Margin Control Offset: 0x1
Comm
Normal Command
Error
Command
and Log

MAC LTSSM L0
Error Count > Error Count Limit
Error Count[5:0] 3 4 Don’t care

Offset=0 Stop Margin


cmd addr data cmd addr data
M2P_MessageBus[7:0] 0x0 WU 0x1 0x0 WC 0x0 0x0 0x0 WA 0x0

PIPE Margin status

P2M_MessageBus[7:0] 0x0 WA 0x0 WC 0x0 0x1 0x0

Step Margin: Tim/Left


Margining function Offset: 0x1
Disable
PHY

3.11.4 Gen5 32.0 GT/s Operation


The controller supports the Gen5 32.0 GT/s feature defined in the PCI Express Base Specification, Revision 4.0,
Version 1.0. The interface between the controller and the PHY is compliant with PIPE Specification for PCI
Express, Version 4.4.1. The controller supports only one mechanism of achieving the Gen5 rate in this release,
that is, dynamic frequency.
For dynamic frequency configurations, the number of active symbols on the PIPE is constant and the
frequency of the controller doubles each time as the controller transitions from Gen1 -> Gen2 -> Gen3->
Gen4 -> Gen5 rates.

3.11.4.1 Gen5 Speed Changing

See “Gen2 Speed Changing” on page 206.

3.11.4.2 Gen5 32.0 GT/s Transmitter Equalization

See “Gen4 16.0 GT/s Transmitter Equalization” on page 208.

3.11.4.3 Lane Margining

See “Gen4 Lane Margining” on page 208.

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3.12 Power Management


This section discusses the power management (PM) features of the controller. For a proper understanding
of PCIe power management, you should read Chapter 5, Power Management of the PCI Express Base
Specification, Revision 4.0, Version 1.0. The following topics are discussed:
■ “Overview” on page 214
■ “L1 Substates” on page 219
■ “L0s Entry and Exit Conditions” on page 229
■ “L1 Operation (Non-substates)” on page 230
■ “L2 and L3 Power Down Entry and Exit Conditions (USP)” on page 235
■ “Outbound TLP Blocking in USP” on page 237
■ “Advanced Power Management and Power Domain Gating” on page 238

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3.12.1 Overview
The controller supports two categories of PM operations to control the device state (D-state) and link state.
■ Software PCI Compatible PM (PCI-PM)
❑ D-state PM of Function
The host software can direct the function to enter any of the D1, D2, or D3 low-power states. It does
this by writing to the Power Management Control and Status Register (PMCSR) in the PCI-PM
capability structure.
❑ D-state PM of Link
Link states are not visible to PCI-PM legacy compatible software, and are derived from the power
management D-states of the components connected to that link. The action of changing the D-state
in the PMCSR indirectly causes a change in the link power state. The L1 state is entered whenever
all functions of a USP on a link are programmed to a non-D0 state. The entry into L2 and L3 states
is initiated by the DSP.
❑ Clock PM (L1 with REFCLK removal/PLL Off)
This is an optional feature that enables components on a link to further reduce idle power
consumption while the link is in L1, by turning off the PLL.
■ Native PCIe PM Mechanisms
❑ Active State PM (ASPM)
When the USP is in L0 and detects idleness on the link for a specific amount of time, it automati-
cally transitions the link to the L0s or L1 (optional) power state.
❑ L1 Substates
This is an optional PCIe feature that enables components on a link to further reduce idle power
consumption while the link is in L1, including almost complete removal of power for the high
speed PHY circuits.

3.12.1.1 Relationship Between D-state, Link State, and PHY State

The link state and D-state determine what power and clock supplies are on or off. For implementation
information of low-power clocking logic, see “Clock Requirements” on page 53.

Table 3-58 Power/Clock Supply Status in Low-Power States of Interest

Permissible Link State Active


Quiescent Change Trigger Power Active Clock pipe_clk
D-State Link States (see Table 3-59) Supplies Suppliesa core_clk PHY State

D0unitialized L0 NA

L0 ON P0, P0S
Vmainb REFCLK
D0active L0S ASPM
Vaux AUXCLK
L1
ONc P1
D1, D2, D3hot L1 PCI-PM

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Permissible Link State Active


Quiescent Change Trigger Power Active Clock pipe_clk
D-State Link States (see Table 3-59) Supplies Suppliesa core_clk PHY State

L2 Vaux AUXCLK
D3coldd PCI-PM OFF P2/OFFe
L3f None None

a. REFCLK is the platform reference clock for the PHY TX PLL. AUXCLK is the platform low-power clock. For more information,
see “Clock Requirements” on page 53
b. Optionally removable in L2 and L1.2 using “Advanced Power Management and Power Domain Gating” on page 238.
c. You can remove REFCLK (and pipe_clk/core_clk). For more information, see “Removing the Reference Clock” on page 58
d. Transitioned from D3hot to D3cold by removal of Vmain. D3cold is entered by the controller in response to PME_Turn_Off
MSG
e. When CX_P2NOBEACON_ENABLE =1 and PHY_INTEROP_CTRL_OFF.P2NOBEACON_ENABLE =1, mac_phy_power-
down drives P2.NoBeacon encoding, instead of P2 encoding, when the link goes to L2.
f. A function can be transitioned from L2 to L3 by the removal of Vaux.

D0active and D0uninitialized


Note
D0 is divided into two distinct substates, the uninitialized substate and the active substate.
When a component comes out of conventional reset or FLR, it defaults to the D0uninitialized
state. A function enters the D0active state whenever any of the functions Memory Space
Enable, I/O Space Enable, or Bus Master Enable bits have been enabled by system software.

Table 3-59 Link-State-Change Trigger Capabilities for Each Port Type

Can Trigger L0/L0s Can Trigger L2/L3


Port Type Entry Can Trigger L1 Entry Entry

Yes, on any of these triggersa:


■ Software programs non-D0 state (PCI-PM)
USP Yes No
■ USPs idle timer expires (ASPM)
■ Application requests the USP to enter L1b

DSP Yes Noc Yesd

a. You can prevent/delay the controller from entering L1-ASPM (not L1-PCI-PM) by asserting app_xfer_pending.
b. USP application asserts the app_req_entr_l1 input. A DSP controller ignores this input.
c. DSP can indirectly initiate L1 by writing non-D0 value to PMCSR of the USP link partner. A non-D0 write to the USP PMCSR
always triggers a transition to L1.
d. L2/L3 entry is initiated after the RC PM software transitions a device into a D3 state and subsequently instructs the DSP to
transmit PME_Turn_Off message TLP to initiate the removal of power and clocks.

Table 3-60 indicates the different levels of power savings (obtained by switching off circuits outside the
controller) that can be expected from executing L1 in different ways. Higher exit latencies are associated
with higher power savings. Power saving and latency are PHY implementation specific, and may be
determined by consulting your PHY documentation.

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Table 3-60 L1 Execution Modes and Permissible Power States of PHY Circuits

Permissible Power States for PHY Circuits

RX Electrical Idle
L1 Execution Mode PLL/REFCLK Detector TX Common Mode

L1 without Clock PM ON ON ON

L1 with Clock PM OFF ON ON

L1.1 OFF OFF ON

L1.2 OFF OFF OFF

For more information on power consumption figures, see “Advanced Information: Area, Power
Note
Estimates, and RAM Sizes” on page 1026.
For more information on optimizing system resumption time after exiting low-power states, see
“Readiness Notifications (RN)” on page 261.

3.12.1.2 Device State (D-state) Power Management of a Function (USP)

The host software can direct the downstream device function to enter any of the low-power states:
■ D1 (light sleep)
■ D2 (deep sleep)
■ D3hot (full of; reference clock optionally removed; Vmain normally available)
■ D3cold (full of; reference clock removed; Vmain removed; Vaux optionally available)
It does this by writing to the PMCSR in the PCI-PM capability structure. This action also indirectly causes
the downstream component (USP) to change the link power state. The controller negotiates with the link
partner using PM TLPs and DLLPs before entering the corresponding low-power link state. The controller
exits the device low-power state (and returns to D0) when it detects a CFG access to a device function, or
when it detects a PME such as an event on the outband_pwrup_cmd1 input signal. For a function in device
power states D1, D2, and D3hot, the controller only accepts CFG and MSG requests TLPs for that function.
All other incoming request types for that function are treated as unsupported requests (UR). For more
information see Section 5.3.3, “Power Management Event Mechanisms” of the PCI Express Base Specification,
Revision 4.0, Version 1.0.

3.12.1.3 Active State Power Management (ASPM)

You must enable ASPM through the ASPM Control field in the Link Control register. When the USP is in L0
and detects idleness on the link for a specific amount of time (determined by the L0s Entrance Latency field2
in the “Ack Frequency and L0-L1 ASPM Control Register” ACK_F_ASPM_CTRL_OFF), it automatically
transitions the link to the L0s power state. Each link direction (TX and RX) is processed separately. The
controller exits L0s when there is traffic waiting to be sent.

1. Or on apps_pm_xmt_pme as these inputs are functionally identical.


2. You set this by writing to this register or by setting DEFAULT_L0S_ENTR_LATENCY or DEFAULT_L1_ENTR_LATENCY.

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When the USP is in L0 or L0s and it detects idleness on the link (both directions) for a specific amount of
time (determined by the L1 Entrance Latency field in ACK_F_ASPM_CTRL_OFF), it automatically transitions
the link to the L1 power state. The link partners must negotiate entry into the L1 link power state using PM
TLPs and DLLPs. The L1 state achieves greater power savings but the exit latency from this state is higher
than from L0s. You can also instruct an USP controller (only) to enter L1 by asserting the app_req_entr_l1
input. The USP exits L1 when there is traffic waiting to be sent or when a PME (such as an event on the
app_req_exit_l1 input) is received.
If the ASPM exit latencies from L0s or L1 are too high for the overall PCIe system data latency requirements,
then the host software can disable ASPM using the ASPM Control Field of the Link Control register. The
controller reports the exit latencies using the Link Capability registers. You set these by writing to these
registers or by setting the DEFAULT_L0S_EXIT_LATENCY and DEFAULT_L1_EXIT_LATENCY parameters.

3.12.1.4 Registers Shadowed in Power Management Controller

Table 3-61 lists the registers shadowed in the power management controller (PMC) and the reason for
shadowing them.

Table 3-61 Registers Shadowed in PMC

Register Field Description Reason for Shadowing

The PCI Express Base


Specification, Revision 4.0,
Version 1.0 specifies that the
value of this bit must be
Enable aux power support for a preserved in the D3cold state.
Device Control Register Aux Power PM Enable
function. In L2 when power is removed
the CDM loses its context. This
bit is preserved in the PM
under AUX power and fed back
to the CDM.

PME message request, if


Indicates if a function is permitted enabled, can trigger a wakeup
PMCSR PME_EN
to generate a PME. from L2 if main power has been
removed.

Indicates the D-state of a Used for entry to low power


PMCSR_BSE PowerState
function. states.

If set to 1 this indicates that an


Used for the removal of
Link Capabilities Clock Power upstream port tolerates the
reference clock in L1 or L2/L3
Register Management removal of reference clock when
Ready.
the link is in L1 or L2/L3 Ready.

This field is used to scale


certain timers in the power
The frequency of the aux_clk in management block. It needs to
AUX_CLK_FREQ_OFF AUX_CLK_FREQ
MHz. be shadowed because the
CDM is reset when power is
removed in L2.

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Register Field Description Reason for Shadowing

GEN3_ZRXDC_NON GEN3 Receiver impedance This bit enables a 100ms timer


GEN3_RELATED_OFF
COMPL zrx-dc not compliant. which can trigger exit from L1.

The shadowed register field is


PHY_INTEROP_CTRL P2NOBEACON_ENA used to pick the PHY
P2.NoBeacon enable bit.
_OFF BLE powerdown encoding;
P2.NoBeacon instead of P2.

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3.12.2 L1 Substates
This section discusses the L1 link substates. The following topics are discussed:
■ “L1.1 and L1.2 Entry and Exit Conditions” on page 221
■ “L1 Exit Latency (PIPE 4.2)” on page 225
■ “L1 Exit Latency (PIPE 4.3 or Later)” on page 227
The L1 substates are applicable in both the ASPM and PCI-PM L1 link states. L1 substates management
utilizes a per-link sideband signal called CLKREQ#. The controller supports this feature (with the additional
I/O as shown in “Removing the Reference Clock” on page 58) when you set CX_L1_SUBSTATES_ENABLE
=1.

To prevent L1 substates entry you can either perform a configuration write to change the
Note settings of the L1 Substates Control 1 register or set app_l1sub_disable =1.

Assumptions and Limitations


■ The CLKREQ# signal is not directly controlled by the controller. You must implement external logic to
do so; see “Removing the Reference Clock” on page 58 for examples.
■ During L1 substates it is assumed that core_clk is turned off and that aux_clk is active. It is required
that your application switches aux_clk to a low frequency free running clock on entry into L1.
■ The controller uses aux_clk for counting time during L1 substates. You must program the frequency
of this clock into the L1_SUBSTATES_OFF register with a value in the range 1...1000MHz to count real
time. Frequencies lower than 1 MHz are possible, but with a loss of accuracy in the time counted.
■ When the electrical idle detection circuitry is disabled it is assumed that the PHY holds the signal
phy_mac_rxelecidle to 1.

PIPE Operation
The controller supports three interface options for L1 substates.
■ PIPE 4.2 + Sideband signals (CX_PIPE_VER =0)
❑ The controller uses the sideband signals mac_phy_rxelecidle_disable, mac_phy_txcommon-
mode_disable, and phy_mac_pclkack_n.
■ PIPE 4.3 or later (CX_PIPE_VER >1)
❑ The controller and PHY use the mac_phy_powerdown[3:0] output to indicate the PHY power
state.
❑ You can specify the power-down encodings using the CX_PIPE43_P1CPM_ENCODING,
CX_PIPE43_P1_1_ENCODING, and CX_PIPE43_P1_2_ENCODING parameters.
❑ You can specify P1.CPM entry sequence using the CX_PIPE43_P0_P1CPM parameter.
❑ You can specify P1.1 (P1.2) exit sequence using the CX_PIPE43_P1CPM_P1 parameter.
❑ The sideband signals mac_phy_rxelecidle_disable and mac_phy_txcommonmode_disable
exist on top of the controller. PHY can optionally use these signals.
❑ The sideband signal phy_mac_pclkack_n does not exist on the top of the controller.

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Contact your PHY vendor regarding L1 substates operation because the PIPE specification
Note does not clarify all details.

Figure 3-59 PIPE 4.3 L1 SS Operation (CX_PIPE43_ASYNC_HS_BYPASS=0 / CX_PIPE43_P0_P1CPM=0/


CX_PIPE43_P1CPM_P1 =0)
T-power_off T-L1.2 T-power_on

PHY(in) REFCLK active stop active


PHY(out) PCLK active stop active
MAC(in) core_clk active stop active
MAC(in) aux_clk pclk aux_clk pclk
MAC -> PHY mac_phy_rxelecidle_disable
MAC -> PHY mac_phy_txcommonmode_disable if the target L1 substate is L1.2
MAC -> PHY mac_phy_powerdown[3:0] P0 P1 P1.CP M(CX_P IPE43_P1CPM_ENCODING) P1.1 or P1.2 (CX_P IPE43_P1_1_ENCODIN G/CX_P IPE43_P1_2_ENCODING) P1 P0
PHY -> MAC phy_mac_phystatus[NL-1:0]
MAC -> PHY mac_phy_asyncpowerchangeack 1

MAC -> clk_rst pm_sel_aux_clk

clk_rst -> MAC aux_clk_active


MAC -> clk_rst local_ref_clk_req_n[1]

MAC(in) clkreq_in_n

wake up event from


1 At this point, the assertion of phy _mac_phystatus is detected on PCLK, and its de-assertion is detected on the aux _clk.
application logic

Figure 3-60 PIPE 4.3 L1 SS Operation (CX_PIPE43_ASYNC_HS_BYPASS=0 / CX_PIPE43_P0_P1CPM=1/


CX_PIPE43_P1CPM_P1 =1)
T-power_off T-L1.2 T-power_on

PHY(in) REFCLK active stop active


PHY(out) PCLK active stop active
MAC(in) core_clk active stop active
MAC(in) aux_clk pclk aux_clk pclk
MAC -> PHY mac_phy_rxelecidle_disable
MAC -> PHY mac_phy_txcommonmode_disable if the target L1 substate is L1.2
MAC -> PHY mac_phy_powerdown[3:0] P0 P1.CP M(CX_P IPE43_P1CPM_ENCODING) P1.1 or P1.2 (CX_P IPE43_P1_1_ENCODIN G/CX_P IPE43_P1_2_ENCODING) P1.CPM P1 P0
PHY -> MAC phy_mac_phystatus[NL-1:0]
MAC -> PHY mac_phy_asyncpowerchangeack

MAC -> clk_rst pm_sel_aux_clk

clk_rst -> MAC aux_clk_active


MAC -> clk_rst local_ref_clk_req_n[1]

MAC(in) clkreq_in_n

wake up event from


application logic

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Figure 3-61 PIPE 4.3 L1 SS Operation (CX_PIPE43_ASYNC_HS_BYPASS=1 / CX_PIPE43_P0_P1CPM=1/


CX_PIPE43_P1CPM_P1 =1)
T-power_off T-L1.2 T-power_on

PHY(in) REFCLK active stop active


PHY(out) PCLK active stop active
MAC(in) core_clk active stop active
MAC(in) aux_clk pclk aux_clk pclk
MAC -> PHY mac_phy_rxelecidle_disable
MAC -> PHY mac_phy_txcommonmode_disable if the target L1 substate is L1.2
MAC -> PHY mac_phy_powerdown[3:0] P0 P1.CP M(CX_P IPE43_P1CPM_ENCODING) P1.1 or P1.2 (CX_P IPE43_P1_1_ENCODIN G/CX_P IPE43_P1_2_ENCODING) P1.CPM P1 P0
PHY -> MAC phy_mac_phystatus[NL-1:0]
MAC -> PHY mac_phy_asyncpowerchangeack

MAC -> clk_rst pm_sel_aux_clk

clk_rst -> MAC aux_clk_active


MAC -> clk_rst local_ref_clk_req_n[1]

MAC(in) clkreq_in_n

wake up event from


application logic

3.12.2.1 L1.1 and L1.2 Entry and Exit Conditions

This section discusses the L1 link state. The following topics are discussed
■ “Overview”
■ “PIPE 4.2 L1 Substates Entry” on page 221
■ “PIPE 4.2 L1 Substates Exit (Locally Initiated)” on page 222
■ “PIPE 4.2 L1 Substates Exit (Remotely Initiated)” on page 222
■ “PIPE 4.3 or Later L1 Substates Entry” on page 222
■ “PIPE 4.3 or Later Substates Exit (Locally Initiated)” on page 223
■ “PIPE 4.3 or Later Substates Exit (Remotely Initiated)” on page 225
■ “L1 Substates Software Control” on page 223

3.12.2.1.1 Overview
After the link has entered L1 through the normal L1 negotiation, the USP can initiate the sequence for
entering the target L1 substate (L1.1 or L1.2) by tri-stating its CLKREQ# output buffer. The entry sequence
can only proceed if the DSP is also tri-stating its CLKREQ# output buffer, resulting in the bidirectional
CLKREQ# signal being pulled up to 1. Otherwise CLKREQ# remains asserted at 0 and the link state stays in
L1. The exit sequence can be initiated by either ports by asserting CLKREQ# to 0. For each port there are two
cases to consider, the first where the exit is initiated locally, the second where the exit is initiated remotely.
The following sections provide details on the signaling that occurs between the PCIe controller as the MAC,
the PHY, and the CLKREQ# output buffer, for entering and exiting L1 substates. L1 substates management
utilizes a per-link sideband signal called CLKREQ#. After all of the entry conditions for a L1 substate are met,
the controller asserts the mac_phy_rxelecidle_disable output. When the target L1 substate is L1.2, it
also asserts the mac_phy_txcommonmode_disable output.

3.12.2.1.2 PIPE 4.2 L1 Substates Entry


1. Controller de-asserts mac_phy_pclkreq_n[1]
2. PHY de-asserts phy_mac_pclkack_n when ready for REFCLK removal, PCLK is off

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3. CLKREQ# output buffer tri-stated


4. Controller waits for clkreq_in_n to de-assert
5. Controller asserts mac_phy_rxelecidle_disable (and mac_phy_txcommonmode_disable if the
target L1 substate is L1.2)
6. PHY disables receiver Electrical Idle detection, phy_max_rxelecidle is maintained stable to 1, if
mac_phy_txcommonmode_disable =1 the PHY also disables transmitter Common Mode.
Note: If PHY does not de-assert phy_mac_pclkack_n within 3us in step 2, controller asserts
mac_phy_pclkreq_n again.

3.12.2.1.3 PIPE 4.2 L1 Substates Exit (Locally Initiated)


1. Any of the normal L1 exit conditions in “L1-PM/L1-ASPM Exit” on page 232 are met
2. Controller asserts mac_phy_pclkreq_n[1]
3. Controller de-asserts mac_phy_rxelecidle_disable (and mac_phy_txcommonmode_disable if
asserted)
4. PHY re-enables receiver Electrical Idle detection, if disabled the PHY also re-enables transmitter
Common Mode
5. CLKREQ# output buffer is asserted
6. PHY asserts phy_mac_pclkack_n when PCLK is on
7. Controller transitions the PHY to P0 in the usual way

3.12.2.1.4 PIPE 4.2 L1 Substates Exit (Remotely Initiated)


1. The remote link partner asserts CLKREQ#
2. Controller input clkreq_in_n asserts
3. Controller asserts mac_phy_pclkreq_n[1]
4. Controller de-asserts mac_phy_rxelecidle_disable (and mac_phy_txcommonmode_disable if
asserted)
5. PHY re-enables receiver Electrical Idle detection, if disabled the PHY also re-enables transmitter
Common Mode
6. PHY asserts phy_mac_pclkack_n when PCLK is on
7. Controller transitions the PHY to P0 in the usual way

3.12.2.1.5 PIPE 4.3 or Later L1 Substates Entry


1. MAC transitions the PHY to P1
2. PHY asserts phy_mac_phystatus for P1 entry
3. Controller transitions the PHY to P1.CPM and asserts pm_sel_aux_clk to turn off core_clk
4. PHY asserts phy_mac_phystatus for P1.CPM entry and CLK_RST asserts aux_clk_active
5. Controller de-asserts local_ref_clk_req_n[1]
6. CLKREQ# output buffer tri-stated
7. Controller waits for clkreq_in_n to de-assert
8. Controller transitions the PHY to P1.1 (or P1.2)

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9. PHY asserts phy_mac_phystatus for P1.1 (or P1.2)


10. Controller asserts mac_phy_asyncpowerchangeack
11. PHY de-asserts phy_mac_phystatus
12. Controller de-asserts mac_phy_asyncpowerchangeack
Note: When CX_PIPE43_P0_P1CPM =1, steps 1- 2 are bypassed and when CX_PIPE43_ASYNC_HS_BYPASS
=1, steps 9 - 12 are bypassed.

3.12.2.1.6 PIPE 4.3 or Later Substates Exit (Locally Initiated)


1. Any of the normal L1 exit conditions in “L1-PM/L1-ASPM Exit” on page 232 are met
2. Controller asserts local_ref_clk_req_n[1]
3. CLKREQ# output buffer is asserted
4. Controller transitions the PHY to P1.CPM
5. PHY asserts phy_mac_phystatus for P1.1 (or P1.2)
6. Controller asserts mac_phy_asyncpowerchangeack
7. PHY de-asserts phy_mac_phystatus
8. Controller de-asserts mac_phy_asyncpowerchangeack
9. Controller transitions the PHY to P1 and de-asserts pm_sel_aux_clk to turn on core_clk
10. PHY asserts phy_mac_phystatus for P1 entry and CLK_RST de-asserts aux_clk_active
11. Controller transitions the PHY to P0 in the usual way
Note: When CX_PIPE43_P1CPM_P1 =0, steps 4 - 8 are bypassed and when CX_PIPE43_ASYNC_HS_BYPASS
=1, steps 5 - 8 are bypassed.

3.12.2.1.7 L1 Substates Software Control


To facilitate L1 substates entry, your application must,
1. Set app_l1sub_disable =0
2. Set app_clk_pm_en =1 and PCIE_CAP_EN_CLK_POWER_MAN field in LINK_CONTROL_LINK_STA-
TUS_REG =1(only for PIPE 4.3 or later)
3. Set app_clk_req_n =1, to indicate that your application logic is ready to have reference clock
removed, and the controller can switch to aux_clk
When the controller enters L1, the target L1 substate depends on the following programmable register
fields:
■ PM Control/Status Register
❑ USP: The current D-state
❑ The DLLP type that is used by USP to request L1
■ L1 Substates Control 1 Register
❑ ASPM PM L1.1 Enabled
❑ ASPM PM L1.2 Enabled
❑ PCI PM L1.1 Enabled
❑ PCI PM L1.2 Enabled

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After the USP controller enters L1, it uses the D-state of the device to determine if L1 is entered in ASPM
mode or PCI-PM mode. Table 3-62 shows the target L1 substate as a function of the relevant programmable
register fields.
After the DSP controller enters L1, it uses the USPs DLLP L1 request type to determine if L1 is entered in
ASPM mode or PCI-PM mode. Table 3-63 shows the target L1 substate as a function of the relevant
programmable register fields.

Table 3-62 Target L1 Substate as a Function of Software Controls (USP)

PCI PM
ASPM PM L1.1 ASPM PM L1.2 Reported LTR >= L1.1 PCI PM L1.2 Target L1
D-Statea Enabled Enabled L1.2 Threshold Enabled Enabled Substate

!D0 - - - 0 0 L1

!D0 - - - 1 0 L1.1

!D0 - - - - 1 L1.2

D0 0 0 - - - L1

D0 1 0 - - - L1.1

D0 0 1 0 - - L1

D0 1 1 0 - - L1.1

D0 - 1 1 - - L1.2

a. In all functions of a multifunction device

Table 3-63 Target L1 Substate as a Function of Software Controls (DSP)

DLLP ASPM PM ASPM PM L1.2 Reported LTR >= PCI PM L1.1 PCI PM L1.2 Target L1
Received L1.1 Enabled Enabled L1.2 Threshold Enabled Enabled Substate

- - - 0 0 L1
PM_Enter_L
- - - 1 0 L1.1
1
- - - - 1 L1.2

0 0 - - - L1

1 0 - - - L1.1
PM_Active_
State_Reque 0 1 0 - - L1
st_L1
1 1 0 - - L1.1

- 1 1 - - L1.2

The Reported LTR is the maximum of the snoop/nosnoop latency values embedded in LTR messages
transmitted by the upstream ports or received by the downstream port. The controller stores these values in

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the port logic LTR Latency Register (PL_LTR_LATENCY_OFF). When the requirement bit in the message is 0,
the latency value is considered infinite (that is, the check with the threshold always pass).
For more information on LTR, see “Latency Tolerance Reporting (LTR) Message Reception” on page 166
and “Latency Tolerance Reporting (LTR) Message Generation” on page 158.

Figure 3-62 Role of LTR in L1 Substates


from
RADM
RX wire

L1Substates
Capability Registers
LTR Msg
received DP LTR Port > target L1 L1Substates
Logic < substate FSM
UP Registers
L1.2 Threshold
LTR Msg device_type
transmitted

to
XADM
TX wire

Device
cfg_ltr_m_en Colour Code:
Control 2
Register only required for UP (Upstream Port)

cfg_ltr_max_latency[31:0] LTR only required for DP (Downstream Port)


Capability required for both UP and DP
(platform configured Registers
max latency)

app_ltr_latency[31:0]
(reported latency)

3.12.2.1.8 PIPE 4.3 or Later Substates Exit (Remotely Initiated)


1. The remote link partner asserts CLKREQ#
2. Controller input clkreq_in_n asserts
3. Controller asserts local_ref_clk_req_n[1]
4. Controller transitions the PHY to P1.CPM
5. PHY asserts phy_mac_phystatus for P1.1 or (P1.2)
6. Controller asserts mac_phy_asyncpowerchangeack
7. PHY de-asserts phy_mac_phystatus
8. Controller de-asserts mac_phy_asyncpowerchangeack
9. Controller transitions the PHY to P1 and de-asserts pm_sel_aux_clk to turn on core_clk
10. PHY asserts phy_mac_phystatus for P1 entry and DWC_pcie_clkrst.v de-asserts aux_clk_activ
11. Controller transitions the PHY to P0 in the usual way
Note: When CX_PIPE43_P1CPM_P1 =0, steps 4 - 8 are bypassed and when CX_PIPE43_ASYNC_HS_BYPASS
=1, steps 5 - 8 are bypassed.

3.12.2.2 L1 Exit Latency (PIPE 4.2)

This section provides a breakdown of the L1 exit latency when CX_L1_SUBSTATES is enabled for L1
substates or L1 Clock PM in a PIPE 4.2 system.

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Table 3-64 L1 (PIPE 4.2) Substates and L1 Clock PM Exit Latency Component Values

A B C D E

mac_phy_powerdo
pipe_clk stable
CLKREQ# mac_phy_pclkreq_n wn Recovery
Event in Figure ->
-> -> -> ->
3-63
mac_phy_pclkreq_n phy_mac_pclkack_n mac_phy_powerdow phy_mac_phystatu L0
n
s & LTSSM change

Includes time to
Time required after
Time required to switch aux_clk back
pipe_clk is stable
Description 0 produce a stable to pipe_clk and -
to power up circuits
pipe_clk. ungating of
for P0
core_clk.

Time to
Values when 400ns to reactivate
0 execute
exiting L1.1 REFCLK + 15 us
Recovery
Estimate: 3 aux_clk T_common
cycles (slow freq) + Time to P0, ~ 2 us modea (~
T_power_on to 3 core_clk cycles.
Values when 255 us) +
0 reactivate REFCLK
exiting L1.2 time to
+ 15 us
execute
Recovery

a. T_commonmode is only used for DSP.

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Figure 3-63 L1 Exit (PIPE 4.2) Latency Components

3.12.2.3 L1 Exit Latency (PIPE 4.3 or Later)

This section provides a breakdown of the L1 exit latency when CX_L1_SUBSTATES is enabled for L1
substates or L1 Clock PM in a PIPE 4.3 or later system.

Table 3-65 L1 (PIPE 4.3 or Later) Substates and L1 Clock PM Exit Latency Component Values

A B C D E

mac_phy_powerd
mac_phy_powerdo
CLKREQ# own pipe_clk stable
wn Recovery
Event in -> -> ->
-> ->
Figure 3-64 mac_phy_power phy_mac_phystat mac_phy_powerdo
down us phy_mac_phystatu L0
wn
s & LTSSM change
(pipe_clk stable)

Includes time to
Time required after
Time required to switch aux_clk back
pipe_clk is stable to
Description 0 produce a stable to pipe_clk and -
power up circuits
pipe_clk. ungating of
for P0
core_clk.

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A B C D E

400ns to
Values when Time to execute
0 reactivate
exiting L1.1 Estimate: 3 aux_clk Recovery
REFCLK + 15 us
cycles (slow freq) + Time to P0, ~ 2 us
T_power_on to 3 core_clk cycles. T_common mode
Values when
0 reactivate (~ 55 us) + time to
exiting L1.2
REFCLK + 15a us execute Recovery

a. The 15us time includes the P1.1 to P1.CPM transition time for PIPE 4.4.

Figure 3-64 L1 (PIPE 4.3 or Later) Exit Latency Components


A B C D E

CLKREQ#

REFCLK

PCLK

mac_phy_powerdown P1.1 P1 P0

phy_mac_phystatus

LTSSM L1 Recovery L0

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3.12.3 L0s Entry and Exit Conditions


This section discusses the L0s link state. The following topics are discussed:
■ “Overview”
■ “L0s Entry”
■ “L0s Exit”

3.12.3.1 Overview

L0s is a low-power state enabled by ASPM. ASPM controls entry into L0s for the transmitter. The remote
device controls entry into L0s for the receiver.

3.12.3.2 L0s Entry

All of these condition must be met:


■ ASPM L0s is enabled through the ASPM Control field in the Link Control register.
■ L0s entry conditions as defined in Section 5.4.1.1.1, “Entry into the L0s State” of the PCI Express Base
Specification, Revision 4.0, Version 1.0, exist for a duration of time (determined by the L0S_EN-
TRANCE_LATENCY field in ACK_F_ASPM_CTRL_OFF).
■ No higher stage of power-down requested.

3.12.3.3 L0s Exit

Any of these condition can be met:


■ A DLLP or TLP is pending to be sent.
■ L1 entry conditions as defined in Section 5.4.1.2.1, “Entry into the L1 State” of the PCI Express Base
Specification, Revision 4.0, Version 1.0 are satisfied.
■ PCIe link partner requests to enter into link recovery.

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3.12.4 L1 Operation (Non-substates)


The following topics are discussed:
■ “L1 (ASPM/PM) Entry and Exit Conditions”
■ “L1 Clock PM (L1 with REFCLK removal/PLL Off) Overview” on page 233
■ “L1 Clock PM (L1 with REFCLK removal/PLL Off); Entry and Exit Conditions” on page 234

3.12.4.1 L1 (ASPM/PM) Entry and Exit Conditions

This section discusses the L1 link state. L1 is a low-power state enabled either by ASPM (L1-ASPM) or by
the software changing the D-state (L1-PM). The L1 state is a bi-directional link low-power state and both
link partners must negotiate to go to this state.
■ “L1-ASPM Overview”
■ “L1-ASPM Entry (Scenario 1): L1 Idle Timeout in L0s” on page 230
■ “L1-ASPM Entry (Scenario 2): L1 Idle Timeout in L0” on page 231
■ “L1-ASPM Entry (Scenario 3): Application Controlled (USP only)” on page 231
■ “L1-PM Entry” on page 231
■ “L1-PM/L1-ASPM Exit” on page 232

3.12.4.1.1 L1-ASPM Overview


The L1-ASPM entry negotiation handshake uses PM_Active_State_Request_L1 DLLPs, PM_Request_Ack
DLLPs, and PM_Active_State_Nak MSG TLPs. There are three scenarios that cause the controller to enter L1
under ASPM conditions.

3.12.4.1.2 L1-ASPM Entry (Scenario 1): L1 Idle Timeout in L0s


The controller enters L1-ASPM when all of these conditions are met in the USP:
■ ASPM L1 and L0s are enabled through the ASPM Control field in the Link Control register.
■ The ENTER_ASPM field of ACK_F_ASPM_CTRL_OFF is set to ‘0’ and the link state is L0s for both link
partners,
or
the ENTER_ASPM field of ACK_F_ASPM_CTRL_OFF is set to ‘1’.
■ L1 entry conditions as defined in Section 5.4.1.2.1, “Entry into the L1 State” of the PCI Express Base
Specification, Revision 4.0, Version 1.0, exist for a duration of time (determined by the L1_EN-
TRANCE_LATENCY field in ACK_F_ASPM_CTRL_OFF).
■ No higher stage of power-down requested.
■ Your USP application is not asserting the app_xfer_pending input.
■ There are no in-progress transactions1 in the controller such as:
❑ Rx queue P/NP Request TLPs
❑ Rx queue CPL TLPs

1. Created by your application, or remote link partner. DBI requests do not prevent L1 entry because the CDM registers are
clocked off aux_clk_g.

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❑ Outstanding/expected wire completions


❑ Outstanding/expected application completions

3.12.4.1.3 L1-ASPM Entry (Scenario 2): L1 Idle Timeout in L0


The controller enters L1-ASPM when all of these conditionsare met in the USP:
■ ASPM L1 is enabled and L0s is not enabled through the ASPM Control field in the Link Control
register.
■ Link state is L0.
■ L1 entry conditions as defined in Section 5.4.1.2.1, “Entry into the L1 State” of the PCI Express Base
Specification, Revision 4.0, Version 1.0, exist for a duration of time (determined by the L1_EN-
TRANCE_LATENCY field in ACK_F_ASPM_CTRL_OFF).
■ No higher stage of power down-requested.
■ Your USP application is not asserting the app_xfer_pending input.
■ There are no in-progress transactions in the controller such as:
❑ Rx queue P/NP Request TLPs
❑ Rx queue CPL TLPs
❑ Outstanding/expected wire completions
❑ Outstanding/expected application completions

3.12.4.1.4 L1-ASPM Entry (Scenario 3): Application Controlled (USP only)


The controller enters L1-ASPM when all of these conditions are met in the USP:
■ ASPM L1 is enabled through the ASPM Control field in the Link Control register.
■ Your application logic pulses the app_req_entr_l1 input.
■ Your USP application is not asserting the app_xfer_pending input.
■ There are no in-progress transactions1 in the controller such as:
❑ Rx queue P/NP Request TLPs
❑ Rx queue CPL TLPs
❑ Outstanding/expected wire completions
❑ Outstanding/expected application completions

3.12.4.1.5 L1-PM Entry


The power management state of a link is determined by the D-state of the USP. When you change the device
state of the USP to D1, D2, or D3hot by writing to the PMCSR, the controller must initiate a link state
transition to L1. L1 state is a bi-directional link low-power state. Both link partners must negotiate to go this
state. The L1-PM negotiation handshake uses the following DLLPs:
■ PM_Enter_L1
■ PM_Request_Ack

1. Created by your application or remote link partner. DBI requests do not prevent L1 entry because the CDM registers are
clocked off aux_clk_g.

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All of these condition must be met:


■ L1 entry conditions are satisfied as defined in Section 5.3.2.1, “Entry into the L1 State” of the PCI
Express Base Specification, Revision 4.0, Version 1.0.
Note: An USP application asserting the app_xfer_pending input does not prevent L1-PM entry, but
causes immediate exit from L1-PM.

3.12.4.1.6 L1-PM/L1-ASPM Exit


The controller exits L1-PM/L1-ASPM if any of these conditions is met:
■ A DLLP or TLP is pending to be sent.
■ Link partner is requesting exit from L1.
■ Your application asserts the app_xfer_pending input.
■ Your application asserts the apps_pm_xmt_pme input.
When the USP is programmed1 with capability to support PME; it sends a PME message to the RC
which calls the PM software to transition the USP to the D0 state. Therefore, you should only use
apps_pm_xmt_pme for L1-PM exit.
■ PM software (RC) requests a higher stage of power-down by writing to the PMCSR in the USP.
■ Your application (USP) requests transmission of VDM, MSI/MSIX2, or LTR message.
■ Your application is requesting to send traffic by asserting client0_tlp_hv
■ Your application (DSP) initiates link disable, or link retrain (by setting PCIE_CAP_LINK_DISABLE or
PCIE_CAP_RETRAIN_LINK field in LINK_CONTROL_LINK_STATUS_REG to 1).
■ Your application (DSP) initiates hot reset by either:
❑ setting RESET_ASSERT field in PORT_LINK_CTRL_OFF to 1, or
❑ setting SBR field in BRIDGE_CTRL_INT_PIN_INT_LINE_REG to 1, or
❑ toggling app_init_rst
■ Your application (DSP) requests transmission of Unlock message.
■ Your application requests a speed change (by setting DIRECT_SPEED_CHANGE field in GEN2_C-
TRL_OFF to 1).
■ Your application requests link width change (by setting DIRECT_LINK_WIDTH_CHANGE field in
MULTI_LANE_CONTROL_OFF is set to 1).
■ Any activity in the RADM, as indicated by radm_idle being set to 1'b0.

1. PME_ENABLE bit is set in CON_STATUS_REG, and the PME_SUPPORT bit is set in CAP_ID_NXT_PTR_REG for the
corresponding D-state for which the function is currently in.
2. This exit mechanism does not apply to legacy interrupts. Before requesting the transmission of a legacy interrupt the
application should use an existing L1 exit mechanism.

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L1 Exit
Note
■ The CDM space is accessible in L1, but some CDM register bits do not produce the
desired results.
■ Writing to CDM register bits which trigger LTSSM state transitions in L1 does not
have the desired effect because the LTSSM clock is not running in L1.
■ radm_idle is set to 1'b0 if ADV_ERR_CAP_CTRL_OFF[ECRC_CHK_EN] is set to 1'b1
during L1.

3.12.4.2 L1 Clock PM (L1 with REFCLK removal/PLL Off) Overview

This feature allows you to shut down the PLL and the reference clock during standard (non-substates) L1.
Table 3-66 lists the inputs and outputs that are considered for L1 Clock PM.

Table 3-66 Inputs and Outputs to Consider for L1 Clock PM

CX_L1_SUBSTATES_EN CX_PIPE_VER I/O Signals

clk_req_n
0
phy_clk_req_n
0 clk_req_n
1 mac_phy_powerdown[3:0] =CX_PIPE43_P1CPM_ENCODING
phy_mac_phystatus

mac_phy_pclkreq_n[0]
0
phy_mac_pclkack_n
1
mac_phy_powerdown[3:0] =CX_PIPE43_P1CPM_ENCODING
1
phy_mac_phystatus

For PIPE 4.3 (CX_PIPE_VER =1),


■ The controller and PHY use mac_phy_powerdown[3:0] to indicate the PHY power state.
■ You can specify the power-down encodings using the CX_PIPE43_P1CPM_ENCODING parameter.
■ You can specify P1.CPM entry sequence using the CX_PIPE43_P0_P1CPM parameter.
For an USP, host software uses the Enable Clock Power Management bit in the Link Control register to
enable this feature. For a DSP, this register bit is hard coded to ‘0’ and cannot be used to control this
behavior. Your application can use the app_clk_pm_en input to dynamically control whether to execute L1
with or without Clock PM. The CLKREQ# signal is not directly controlled by the controller. You must
implement external logic to do so; see “Removing the Reference Clock” on page 58 for examples.

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Figure 3-65 PIPE 4.3 L1 CPM Operation (CX_PIPE43_P0_P1CPM=0)


PHY(in) REFCLK active stop active
PHY(out) PCLK active stop active
MAC(in) core_clk active stop active
MAC(in) aux_clk pclk aux_clk pclk

MAC -> PHY mac_phy_powerdown[3:0] P0 P1 P1.CP M(CX_P IPE43_P1CPM_ENCODING) P1 P0


PHY -> MAC phy_mac_phystatus[NL-1:0]

MAC -> clk_rst pm_sel_aux_clk

clk_rst -> MAC aux_clk_active

local_ref_clk_req_n[0] (L1SS=1)
MAC -> clk_rst
clk_req_n (L1SS=0)

MAC(in) clkreq_in_n
wake up event

Figure 3-66 PIPE 4.3 L1 CPM Operation (CX_PIPE43_P0_P1CPM=1)


PHY(in) REFCLK active stop active
PHY(out) PCLK active stop active
MAC(in) core_clk active stop active
MAC(in) aux_clk pclk aux_clk pclk

MAC -> PHY mac_phy_powerdown[3:0] P0 P1.CP M(CX_P IPE43_P1CPM_ENCODING) P1 P0


PHY -> MAC phy_mac_phystatus[NL-1:0]

MAC -> clk_rst pm_sel_aux_clk

clk_rst -> MAC aux_clk_active

local_ref_clk_req_n[0](L1SS=1)
MAC -> clk_rst
clk_req_n (L1SS=0)

MAC(in) clkreq_in_n
wake up event

3.12.4.3 L1 Clock PM (L1 with REFCLK removal/PLL Off); Entry and Exit Conditions

To enable the controller (upstream port only) to execute L1 with Clock PM:
■ The Support Clock Power Management bit in the Link Capabilities register must be set. The default
value of this register is controlled by the DEFAULT_CLK_PM_CAP parameter. For downstream ports it
is hardcoded to 0, for upstream ports it can be accessed through the DBI.
■ The Enable Clock Power Management bit in the Link Control register must be set.
■ You must set the app_clk_pm_en input to 1. The controller only samples app_clk_pm_en when L1
is entered.
L1 with Clock PM and L1 substates work orthogonal to each other. L1 with Clock PM uses the
mac_phy_pclkreq_n[0] signaling, and L1 substates uses the mac_phy_pclkreq_n[1]signaling. However,
L1 substates takes precedence over Clock PM within the cores PM state machine. This means that when the
entry conditions for any L1 substate are satisfied (as per “L1 Substates Software Control” on page 223), then
the controller's LTSSM executes the corresponding L1 substate protocol.
For more information on L1 exit latency, see “L1-PM/L1-ASPM Exit” on page 232.

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3.12.5 L2 and L3 Power Down Entry and Exit Conditions (USP)


This section discusses the L2 and L3 link states. The following topics are discussed:
■ “Overview”
■ “L2/L3 Entry”
■ “L2/L3 Exit”

3.12.5.1 Overview

L2/L3 entry is initiated1 after the RC calls power management software to initiate the removal of power and
clocks. USPs of devices in D0, D1, D2, and D3hot must respond to the receipt of a PME_Turn_Off MSG TLP
by transmitting a PME_TO_Ack MSG TLP. The device must then request a link transition to L2/L3_Ready.
L2/L3_Ready is a bi-directional link power down state. If your application is not ready to be shut-down, it
must keep the app_ready_entr_l23 input de-asserted. This causes the controller to delay sending the
PM_Enter_L23 DLLP and thereby stalling the negotiation handshake that uses the following DLLPs:
■ PM_Enter_L23
■ PM_Request_Ack
When your application is eventually ready for transitioning to D3cold, that is, loss of main power and
reference clock, L2/L3_Ready is entered and the downstream device begins preparation for the power and
clock removal. After main power has been removed, the link transitions to L2 if Vaux is provided, or it
transitions to L3 if no Vaux is provided.

3.12.5.2 L2/L3 Entry

All of these condition must be met:


■ PME_Turn_Off/PME_TO_Ack handshake has been completed.
■ Your USP application is ready to be turned off; app_ready_entr_l23 =1.
■ After sending the PME_TO_Ack, the USP initiates the L2/L3 Ready transition protocol by sending the
PM_Enter_L23 DLLP. The RC responds with the PM_Request_Ack.

3.12.5.3 L2/L3 Exit

Any of these condition can be met:


■ When the USP is programmed2 with capability to support PME, your application can assert the
apps_pm_xmt_pme input to request the controller to wakeup. The USP then sends a PM_PME MSG
TLP to the RC which calls the PM software to transition the USP out of the D3 state.
■ Device is programmed with capability to support PME and your application requests the controller to
wakeup by triggering a native hot-plug event.
■ Link partner is requesting exit from L2/L3.

1. In preparation for removing the main power source, your RC application asserts the apps_pm_xmt_turnoff input which
causes the RC to broadcast the PME_Turn_Off MSG TLP to all USPs.
2. PME_ENABLE bit is set in CON_STATUS_REG, and the PME_SUPPORT bit is set in CAP_ID_NXT_PTR_REG for the
corresponding D-state for which the function is currently in.

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The controller directs the PHY to generate beacon signaling when a PCIe device initiates a wake-up event.

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3.12.6 Outbound TLP Blocking in USP


According to the section “B69 Messages in non-D0 states” in the Errata for the PCI Express Base Specification
Revision 4.0, it is strongly recommended that Type 0 functions support generation and reception of messages
in D1, D2, or D3 low-power state (non-D0 state). A function can send completion TLPs regardless of the
D-state. The USP controller sets pm_xtlh_block_tlp =1 when it is in a low-power state.
Table 3-67 describes the configuration settings for blocking outbound TLPs (regardless of TLP type) on
transmit interfaces in non-D0 state.
It not recommended to block completion TLPs on any transmit client interface. When a transmit client
interface (XALI0, XALI1, or XALI2) is used for transmission of completion TLPs only, you should retain the
default value of the parameter CX_CLIENT0/1/2_BLOCK_NEW_TLP, that is ‘0’, so that the controller allows
all outbound completion TLPs on that transmit interface in non-D0 state.

Table 3-67 Configuration Settings for Blocking all Outbound TLPs on Transmit Interfaces in Non-D0 State

Type of TLPs PCIPM_TRAFFIC_CTRL_OFF


Interface Transmitted Parameter Setting Register Field Setting

PCIPM_NEW_TLP_CLIENT0/1/2_BLO
Only Request TLPs CX_CLIENT0/1/2_BLOCK_NEW_TLP =1
XALI0, CKED =1
XALI1, Both Request and
or Completion TLPs
XALI2a CX_CLIENT0/1/2_BLOCK_NEW_TLP =0b NA
(not Message
TLPs)

VMI VDMs CX_BLOCK_VDM_TLP =1 PCIPM_VDM_TRAFFIC_BLOCKED =1

a. Depending on the interface being used, the corresponding parameter or PCIPM_TRAFFIC_CTRL register field must be set.
b. That is, the default value of parameter CX_CLIENT0/1/2_BLOCK_NEW_TLP, so that the controller allows all outbound comple-
tion TLPs on that transmit interface in non-D0 state. Your application must prevent new request TLPs from appearing on the
corresponding transmit interface when pm_xtlh_block_tlp =1.

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3.12.7 Advanced Power Management and Power Domain Gating


This section discusses advanced power management and power gating. The following topics are discussed:
■ “Advanced Power Management Overview”
■ “C-PCIe System-Initiated L2 Power Gating” on page 241
■ “C-PCIe L2 Power Gating + Autonomous L1.2 Power Gating (No Retention Registers)” on page 244
■ “C-PCIe L2 Power Gating + Autonomous L1.2 Power Gating (Using Retention Registers)” on page 247
■ “C-PCIe Autonomous L1.2 Power Gating (No Retention Registers)” on page 250
■ “C-PCIe Autonomous L1.2 Power Gating (Using Retention Registers)” on page 252
■ “UPF Files” on page 253
■ “P2.NoBeacon Support” on page 253

3.12.7.1 Advanced Power Management Overview

This feature allows you to implement power domain gating in your SoC design. It provides all the necessary
clock, reset, and power gating controls.

Table 3-68 Advanced Power Management Features and Assumptions

Description Supported

C-PCIe Features

System-initiated L2 Power Gating


■ Power is removed from all of the controller (including all CDM registers) except the Power Manage-
ment Controller (PMC) and DWC_pcie_clkrst.v.

Autonomous L1 Power Gating

Autonomous L1.1 Power Gating

Autonomous L1.2 Power Gating Using Power Islands

Autonomous L1.2 Power Gating Using Retention Registers


■ (Requires Specific Technology Library)

Optional Wait for External Application/PHY to Save Any State Before Power Removal in L1.2
■ The PHY or your application can use the pm_save_state_req and pm_restore_state_req outputs to
retain any useful information in the always-on memory. For example, the PHY configuration regis-
ters.

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Description Supported

Prevent L1.2 Power Removal by Setting app_l1_pwr_off_en=0

PIPE Status Frozen Using Controller Logic (no Change in Value) in L1.2
■ The controller freezes all PIPE outputs at the values prior to power removal using shadow registers
in the RTL. This includes Gen3 equalization data. The controller does not redo Gen3 equalization
after restoration of power.

FSM To Control Isolation, Clock and Reset Generation, Power Sequencing

Override All Isolation in Test Mode by Setting test_bypass_lp=1

Power Removal Conditions

Power Removal in L1.2 Waits for Pending Transactions to Complete


The controller does not request power removal in L1.2 (and subsequently L1.2 and L1.2 power
removal) if:
■ There are in-progress transactions in the controller , or
■ There are outstanding/expected completions from the wire or application; as indicated by the Rx
Completion LUT

Note: DBI requests do not prevent L1 entry because the CDM registers ) are clocked off aux_clk_g.
However, outstanding DBI transactions forces the controller to keep the link in L1 (with core_clk gated
off) and power gating deactivated.

Power Restoration Conditions

Power Restoration in L1.2


■ The controller does not restore power until it is required to exit L1.2 (as determined by the criteria in
“L1-PM/L1-ASPM Exit” on page 232) or there is a DBI access as described in the next row.

Power Restoration in L1.2 Directly Triggered by DBI Access to CDM/ELBI.


■ DBI access to the CDM registers (which are on aux_clk_g) when the controller is L1.2 power-gated
causes the controller to exit power-gating without exiting L1.2 and waking up the link. When DBI
access is completed, power-gating is resumed. DBI access does not cause the controller to exit L1.2
(or L1).

Power Restoration in L1.2 Indirectly Triggered by Application Activity Causing L1.2 Exit
■ The controller does not restore power until it is required to exit L1.2. The controller exits L1.2 (and
L1) when your application is requesting to send traffic by asserting client0_tlp_hv. This consequently
triggers restoration of power. For more information, see “L1-PM/L1-ASPM Exit” on page 232.

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Description Supported

Power Restoration in L1.2 Indirectly Triggered by SII Activity Causing L1.2 Exit
■ The controller does not restore power until it is required to exit L1.2. Activity on any of the SII or ancil-
lary interfaces does not trigger L1.2 exit. Therefore activity on any of the SII or ancillary interfaces
do not trigger restoration of power.

Assumptions/Limitations

PHY Autonomously Generates its Own Reset When Exiting L1.2 Power Gating
■ The controller does not reset the PHY when exiting L1.2 power gating.

PCIe PHY Autonomously Saves State Internally


■ The controller does not save/restore any PHY configuration information.

Power-gating Interoperability with Synopsys PHYs Using L1 Clock Power Management (CPM)
■ PHY controller interoperability with some Synopsys PHY's is ongoing.
L1.CPM with power-gating is not supported when some Synopsys PHYs are power-gating their
receiver electrical idle detection circuitry in that state; because this causes violations of the specifi-
cation.

UPF Features

Configuration-specific UPF File Provided

PHY UPF File Provided (Example)


■ Sample UPF assumes PHY is off in L2
Sample UPF assumes PHY is on in L1.2

SoC Integration UPF File Provided (Example)

Optional Level Shifting on Always-on PD_VAUX (PMC) Boundary in L2

Powered-Down Outputs Isolated (Not in Controller but at System/Device Level in UPF)

Powered-Down Inputs from PHY Clamped in Controller

VTB Simulation Support

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Description Supported

Retention Registers Supported

L1.2 Retention Register Type


■ 2-Pin Save/Restore
■ 1-Pin Save/Restore
■ 1-Pin Save-Only
■ 1-Pin Restore-Only
■ 0-Pin

Figure 3-67 Configuration Parameters

CX_ENHANCED_PM_EN

CX_L2_PG_EN

CX_L12_PG_EN

CX_L1_RETENTION

CX_RETENTION_TYPE

CX_LEVEL_SHIFT_EN

CM_STORE_MPHY_ATTR_ENABLE

You can also inspect the VTB test cases at


Hint
<workspace>/doc/html/vtb/testenv/index.html for programming examples. For more
information on VTB, see the “Integrating the Controller and VIP using VTB” section in the
“Integration” chapter of the User Guide.

3.12.7.2 C-PCIe System-Initiated L2 Power Gating

When the controller MAC is in L2 (after being programmed to D3), the system might decide to power-down
the primary supply of VMAIN by asserting perst_n. Therefore, the assertion of perst_n is an indication
that the system power controller is going to switch off VMAIN.
■ CX_L2_PG_EN =1
■ CX_L12_PG_EN =0
■ CX_L1_SUBSTATES_ENABLE =0 || (CX_L1_SUBSTATES_ENABLE =1 && app_l1_pwr_off_en
=0)

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■ CX_L1_RETENTION =0

Table 3-69 L2 Configuration

Power Supply

Link State AUX MAIN

L0/L1 ON ON

L2 ON OFF

L3 OFF OFF

Figure 3-68 L2 Symbolic Overview

PCIe Controller
All Controller Logic
(DWC_pcie_ctl)
(DWC_pcie_core)

iso_vmain_to_
vaux

iso User
PMC Application
Isolation Logic
Cell
PHY

Isolation
Cell
iso

DWC_pcie
_clkrst.v iso_vmain_to_vaux

VAUX Board
perst_n L2
Power Domains
Power
Switch PD_VAUX
PD_VMAIN_SW

(pcie_iip_device.upf) VMAIN

Figure 3-69 L2 Simple Timing


VAUX

PD_VMAIN_SW

pm_linkst_in_l2

perst_n

iso_vmain_to_vaux

core_rst_n

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Figure 3-70 L2 Power Gating

L2 Power Gating Process

0RE REQUISITE
v .EGOTIATION FOR , ENTRY HAS BEEN SUCCESSFULLY COMPLETED
0
4HE CONTROLLER WILL ASSERT THE OUTPUT pm_linkst_in_l2
WHEN THIS IS THE CASE

0%234 ,
4HE CONTROLLER WAITS FOR THE INPUT perst_n TO BE SET TO B
1
BEFORE IT BEGINS THE PROCESS OF ISOLATING THE ALWAYS ON DOMAIN

4HE CONTROLLER ISOLATES THE OUTPUTS FROM ITS SWITCHABLE POWER


DOMAINS
3YNCHRONIZE THE v )F !-"! BRIDGE IS PRESENT AND ASYNCHRONOUS TO THE
)SOLATION ENABLES TO
THE !8) #LOCK
)3/,!4)/. 2 CORE?CLK THE ISOLATION ENABLE IS SYNCHRONIZED TO THE !-"!
DOMAINS CLOCK DOMAINS
v 4HE CONTROLLER WAITS FOR ALL ISOLATION ENABLES TO BE ASSERTED
BEFORE PROCEEDING WITH POWER REMOVAL
)3/,!4)/. $/.%
4HE CONTROLLER SETS THE OUTPUT pm_en_vmain TO B TO
INDICATE THE IT IS READY FOR MAIN POWER REMOVAL
v 4HE CONTROLLER ASSERTS THE RESET REQUEST OUTPUTS TO REQUEST
0/7%2
2%3%4
$/7.
3 THE ASSERTION OF THE CONTROLLER RESETS
v 7HEN THE RESETS HAVE ALL BEEN ASSERTED THE CONTROLLER
REMAINS IN THE POWER DOWN STATE UNTIL A WAKEUP EVENT
OCCURS
2%3%4
0%234
$/.%
7HEN AN , WAKEUP EVENT OCCURS THE UPSTREAM PORT WILL
ASSERT THE WAKE OUTPUT TO REQUEST THE RESTORATION OF MAIN
POWER
v 9OUR APPLICATION SHOULD RESTORE THE MAIN POWER AND SET THE
0/7%2 50 4
CONTROLLERS PERST?N INPUT TO gB WHEN THE MAIN POWER IS
STABLE
v 7HEN THE CONTROLLER SAMPLES perst_n AT gB IT BEGINS THE
0/7%2 POWER UP SEQUENCE
34!",%

4HE ISOLATION ENABLE SIGNALS ARE DE ASSERTED


2%,%!3%
)3/,!4)/.
5 v 4HE CONTROLLER WILL WAIT FOR ALL ISOLATION ENABLES TO BE DE
ASSERTED BEFORE PROCEEDING WITH THE WAKEUP SEQUENCE

)3/,!4)/.
$/.%

2%,%!3%
2%3%4
6 4HE RESET REQUESTS ARE DE ASSERTED

%.!",% 4HE CONTROLLER SETS THE OUTPUT PM?SEL?AUX?CLK TO B TO TURN


7
#/2%?#,+ BACK ON THE CORE?CLK AND SWITCH AUX?CLK BACK TO CORE?CLK

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3.12.7.3 C-PCIe L2 Power Gating + Autonomous L1.2 Power Gating (No Retention Registers)

There is a power switch in the UPF to allow the power management circuitry of the controller to
automatically switch off the primary power supply to the selected parts of the design. Certain parts1 of the
design may still need to retain the state when power is removed. The state retention task is achieved by
creating always on supply islands for modules requiring power in L1 sub-states. There are seven L1ON
power islands (representing different parts of the RTL hierarchy) defined in the UPF. You can merge these
into one power domain (PD_L1ON).
■ CX_L2_PG_EN =1
■ CX_L12_PG_EN =1
■ CX_L1_SUBSTATES_ENABLE =1 && app_l1_pwr_off_en =1
■ CX_L1_RETENTION =0

Table 3-70 L2 + L1.2_PD Configuration

Power Supply

Link State AUX MAIN

L0/L1/L1.1 ON ON

L1.2 ON ONa

L2 ON OFF

L3 OFF OFF

a. In L1.2 mode the MAIN power domain inside the controller is completely switched off. It might be ON at the SoC level, but in
PCIe controller context it is switched off.

1. Such as CDM register block, Gen3 EQ settings, credits, lane reversal information and so on.

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Figure 3-71 L2 + L1.2_PD Symbolic Overview

iso_vmain_to_von
PCIe Controller User
All Controller Logic
(DWC_pcie_ctl) iso Application
(DWC_pcie_core)
Logic
iso_vmain_to_vl1on
pm_en_vmain_n

Isolation
L1.2 Always On

Cells
Logic

PMC
iso

Tx iso_vmain_to_vaux
PHY

pm_en_vmain_n

Autonomous
DWC_pcie L1.2 SoC
_clkrst.v Power Switch
Note: This switch
representation will
reflect in the UPF
deliverables of the
controller.

VAUX
perst_n

Power Domains
Board L2
Power Switch PD_VAUX
Note: This switch PD_VMAIN_SW
VMAIN
representation will NOT
PD_L1ON
reflect in the UPF
(pcie_iip_device_upf) deliverables of the controller. PD_PHY

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Figure 3-72 L2 + L1.2_PD Simple Timing


L2 Timing

VAUX

PD_PLL
PD_L1ON
PD_VMAIN_SW
pm_linkst_in_l2

perst_n
iso_vmain_to_vaux
iso_vl1on_to_vaux
iso_vmain_to_vl1on

core_rst_n

L1.2 Timing Not showing optional external save/restore

VAUX
PD_L1ON
PD_PLL
PD_VMAIN_SW assume ack_en_vmain =1

pm_link_st_in_l1sub

iso_vmain_to_vaux

iso _vl1on_to_vaux

iso_vmain_to_vl1on

core_rst_n

en_vmain_n

app_req_exit_l1

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Figure 3-73 L1.2_PD Detailed Timing

L1.2 Power Gating Process

0RE REQUISITE
, 0/7%2$/7.
0 ! PRE REQUISITE FOR THE POWER GATING PROCESS IS THAT THE LINK HAS
ENTERED THE , 0- 3UB STATE
4HE CONTROLLER PERFORMS A HANDSHAKE WITH THE !-"! BRIDGE IF
v !-"! BRIDGE 1
HANDSHAKE
PRESENT TO ENSURE THAT THERE ARE NO TRANSFERS PENDING 4HE
v #HECK $") 6 CONTROLLER CHECKS FOR PENDING !8) TRANSFERS AND $") TRANSFERS
!#4)6%
PENDING 1 AND ONLY PROCEEDS WITH THE POWER GATING PROCESS IF THERE ARE
v #HECK , SUB 0OWER 3WITCH NO PENDING TRANSFERS AND THE BRIDGE HAS ACKNOWLEDGED
STATES EXIT REQUEST !CKNOWLEDGE READINESS FOR POWER GATING )F THE LINK EXITS , DURING THIS
PROCESS THE POWER GATING PROCESS WILL NOT BE INITIATED
2 4HE CONTROLLER ASSERTS AN OUTPUT CALLED pm_save_state_req
2EADY AND WAITS FOR THE APPLICATION TO ASSERT THE INPUT
FOR 0OWER 7 2
2EMOVAL
save_state_ack THIS IS INTENDED TO ALLOW ANY APPLICATION
SPECIFIC STATE TO BE SAVED
0/7%2 50
4HE CONTROLLER ISOLATES THE OUTPUTS FROM ITS SWITCHABLE POWER
DOMAINS
v )F !-"! BRIDGE IS PRESENT AND ASYNCHRONOUS TO THE
!PPLICATION 8 3 core_clk THE ISOLATION ENABLE IS SYNCHRONIZED TO THE
3!6%?34!4%
3AVES 3TATE !-"! CLOCK DOMAINS
0OWER 3WITCH v 4HE CONTROLLER WAITS FOR ALL ISOLATION ENABLES TO BE ASSERTED
!CKNOWLEDGE BEFORE PROCEEDING WITH POWER REMOVAL

4HE CONTROLLER ASSERTS THE RESET REQUEST OUTPUTS TO REQUEST THE


3!6%?34!4%
4 ASSERTION OF THE RESETS FOR THE LOGIC IN THE SWITCHABLE POWER
!CKNOWLEDGE 9 DOMAINS

2%,%!3%?2%3%4
4HE CONTROLLER SETS THE OUTPUT pm_en_vmain TO 1’b0 TO
5
INDICATE THAT IT IS READY FOR POWER REMOVAL
3
4HE CONTROLLER EXPECTS AN ACKNOWLEDGEMENT FROM THE EXTERNAL
10 6
)3/,!4%
POWER SWITCH TO INDICATE POWER HAS BEEN REMOVED
2%3%4 7HEN A POWER UP REQUEST IS DETECTED THE CONTROLLER SETS THE
$/.%
7 OUTPUT pm_en_vmain TO 1’b1 TO REQUEST THE RESTORATION OF
POWER

)3/,!4)/. 4HE CONTROLLER WAITS FOR AN ACKNOWLEDGEMENT FROM THE EXTERNAL


$/.% 8
!#4)6%
POWER SWITCH TO INDICATE POWER HAS BEEN RESTORED

4 11 9 4HE RESET REQUESTS ARE DE ASSERTED


!PPLICATION
2%3%4 2%34/2%?34!4% 2ESTORES
3TATE 10 4HE ISOLATION ENABLE SIGNALS ARE DE ASSERTED

4HE CONTROLLER ASSERTS THE pm_restore_state_req SIGNAL TO


ALLOW THE APPLICATION TO RESTORE STATE IF NECESSARY 4HE
CONTROLLER WAITS FOR THE APPLICATION TO SET THE RESTORE?STATE?ACK
11
2%3%4 $/.%
2%34/2%?34!4% SIGNAL TO B BEFORE RETURNING TO THE !#4)6% STATE !T THIS
!CKNOWLEDGE POINT THE LINK WILL EITHER REMAIN IN , , OR RETURN TO ,
DEPENDING ON THE TYPE OF WAKEUP EVENT
5

3.12.7.4 C-PCIe L2 Power Gating + Autonomous L1.2 Power Gating (Using Retention Registers)

There is a power switch in the UPF to allow the power management circuitry of the controller to
automatically switch off the primary power supply to selected parts of the design. Certain parts1 of the
design may still need to retain the state when power is removed. The state retention task is achieved by
implementing (using your technology vendors library) retention registers in selected modules.

1. Such as CDM register block, Gen3 EQ settings, credits, lane reversal information and so on.

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■ CX_L2_PG_EN =1
■ CX_L12_PG_EN =1
■ CX_L1_SUBSTATES_ENABLE =1 && app_l1_pwr_off_en =1
■ CX_L1_RETENTION =1

Table 3-71 L2 + L1.2_RET Configuration

Power Supply

Link State AUX MAIN

L0/L1/L1.1 ON ON

L1.2 ON ONa

L2 ON OFF

L3 OFF OFF

a. In L1.2 mode the MAIN power domain inside the controller is completely switched off. It might be ON at the SoC level, but in
PCIe controller context it is switched off.

Figure 3-74 L2 + L1.2_RET Symbolic Overview

PCIe Controller iso_vmain_to_vaux


(DWC_pcie_ctl) User
All Controller Logic iso Application
(DWC_pcie_core) Logic
pm_en_vmain_n
pm_save_state_req
Retention
pm_restore_state_req Registers

PMC
iso

iso_vmain_to_vaux

pm_ en_vmain_n

Autonomous
DWC_pcie L1.2 SoC
_clkrst.v Power
Switch

VAUX Board
perst_n L2
Power Domains
Power
Switch PD_VAUX
PD_VMAIN_SW
(pcie_iip_device_upf) VMAIN
VMAIN

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Figure 3-75 L2 + L1.2_RET Simple Timing


L2 Timing
VAUX
PD_PLL
PD_VMAIN_SW

pm_linkst_in_l2

perst_n

iso_vmain_to_vaux
iso_vl1on_to_vaux

core_rst_n

L1.2 Timing
VAUX

PD_PLL

PD_VMAIN_SW assume ack_en_vmain=1

pm_link_st_in_l1sub

save_state

iso_vmain_to_vaux

iso_vl1on_to_vaux

core_rst_n

en_vmain_n

app_req_exit_l1

restore_state

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Figure 3-76 L1.2_RET Detailed Timing

, L1.2 Power Gating Process


v !-"! BRIDGE 0RE REQUISITE
HANDSHAKE 1
0 ! PRE REQUISITE FOR THE POWER GATING PROCESS IS THAT THE LINK HAS
v #HECK $")
PENDING !#4)6% 0/7%2$/7. ENTERED THE , 0- 3UB STATE
v #HECK , SUB
STATES EXIT 4HE CONTROLLER PERFORMS A HANDSHAKE WITH THE !-"! BRIDGE IF
REQUEST PRESENT TO ENSURE THAT THERE ARE NO TRANSFERS PENDING 4HE
CONTROLLER CHECKS FOR PENDING !8) TRANSFERS AND $") TRANSFERS
1
AND ONLY PROCEEDS WITH THE POWER GATING PROCESS IF THERE ARE
2EADY
FOR 0OWER 0OWER 3WITCH NO PENDING TRANSFERS AND THE BRIDGE HAS ACKNOWLEDGED
6 !CKNOWLEDGE
2EMOVAL READINESS FOR POWER GATING )F THE LINK EXITS , DURING THIS
PROCESS THE POWER GATING PROCESS WILL NOT BE INITIATED
2
4HE CONTROLLER ASSERTS THE SAVE STATE REQUEST WHICH IS USED BY
2
THE RETENTION REGISTERS TO RETAIN THEIR STATE
3!6%?34!4% 4HE CONTROLLER ISOLATES THE OUTPUTS FROM ITS SWITCHABLE POWER
0/7%2 50
DOMAINS
v )F !-"! BRIDGE IS PRESENT AND ASYNCHRONOUS TO THE
7 3 CORE?CLK THE ISOLATION ENABLE IS SYNCHRONIZED TO THE !-"!
CLOCK DOMAINS
3!6%?34!4% v 4HE CONTROLLER WAITS FOR ALL ISOLATION ENABLES TO BE ASSERTED
!CKNOWLEDGE 0OWER 3WITCH BEFORE PROCEEDING WITH POWER REMOVAL
8
!CKNOWLEDGE
4HE CONTROLLER ASSERTS THE RESET REQUEST OUTPUTS TO REQUEST THE
3 4 ASSERTION OF THE RESETS FOR THE LOGIC IN THE SWITCHABLE POWER
DOMAINS
)3/,!4% 4HE CONTROLLER SETS THE OUTPUT pm_en_vmain TO 1’b0 TO
5
INDICATE THAT IT IS READY FOR POWER REMOVAL
9 2%34/2%?34!4%
4HE CONTROLLER EXPECTS AN ACKNOWLEDGEMENT FROM THE EXTERNAL
6
POWER SWITCH TO INDICATE POWER HAS BEEN REMOVED
7HEN A POWER UP REQUEST IS DETECTED THE CONTROLLER SETS THE
)3/,!4)/.
10 2%,%!3%?2%3%4
7 OUTPUT pm_en_vmain TO B TO REQUEST THE RESTORATION OF
$/.%
POWER
4HE CONTROLLER WAITS FOR AN ACKNOWLEDGEMENT FROM THE EXTERNAL
8
4
POWER SWITCH TO INDICATE POWER HAS BEEN RESTORED
4HE CONTROLLER ASSERTS THE RESTORE STATE REQUEST WHICH IS USED
2%3%4 9
2%3%4
11
$/.%
BY THE RETENTION REGISTERS TO RESTORE THEIR STATE

10 4HE RESET REQUESTS ARE DE ASSERTED

11 4HE ISOLATION ENABLE SIGNALS ARE DE ASSERTED


2%3%4
12 !#4)6% 4HE CONTROLLER RETURNS TO THE !#4)6% STATE AT THIS POINT THE LINK
$/.%
12 WILL EITHER REMAIN IN , , OR RETURN TO , DEPENDING ON THE
5 TYPE OF WAKEUP EVENT

3.12.7.5 C-PCIe Autonomous L1.2 Power Gating (No Retention Registers)

This scheme is similar to “C-PCIe L2 Power Gating + Autonomous L1.2 Power Gating (No Retention
Registers)” on page 244 except that there is no always-on power supply available in L2.
■ CX_L2_PG_EN =0
■ CX_L12_PG_EN =1
■ CX_L1_SUBSTATES_ENABLE =1 && app_l1_pwr_off_en =1
■ CX_L1_RETENTION =0

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Table 3-72 L1.2_PD Configuration

Power Supply

Link State AUX MAIN

L0/L1/L1.1 Not present ON

L1.2 Not present ON

L2/L3 Not present OFF

Figure 3-77 L1.2_PD Symbolic Overview

PCIe Controller iso_vmain_to_vaux


User
(DWC_pcie_ctl)
All Controller Logic Application
(DWC_pcie_core) iso Logic

Isolation
pm_en_vmain_n L1.2 Always

Cells
iso_vmain_to_vl1on On Logic

PMC
iso

iso_vmain_to_vaux
Tx
PHY

pm_en_vmain_n

DWC_pcie Autonomous
_clkrst.v L1.2 SoC
Power
Switch

Power Domains
VMAIN
PD_VAUX
PD_VMAIN_SW
PD_L1ON
(pcie_iip_device_upf) PD_PHY

Figure 3-78 L1.2_PD Simple Timing


PD_L1ON
PD_PLL Not showing optional external save/restore

PD_VMAIN_SW assume ack_en_vmain =1

pm_link_st_in_l1sub

iso _vmain_to_vaux

iso _vl1on_to_vaux

iso_vmain_to_vl1on

core_rst_n

en_vmain_n

app_req_exit_l1

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3.12.7.6 C-PCIe Autonomous L1.2 Power Gating (Using Retention Registers)

This scheme is similar to “C-PCIe L2 Power Gating + Autonomous L1.2 Power Gating (Using Retention
Registers)” on page 247 except that there is no always-on power supply available in L2.
■ CX_L2_PG_EN =0
■ CX_L12_PG_EN =1
■ CX_L1_SUBSTATES_ENABLE =1 && app_l1_pwr_off_en =1
■ CX_L1_RETENTION =1

Table 3-73 L1.2_RET Configuration

Power Supply

Link State AUX MAIN

L0/L1/L1.1 Not present ON

L1.2 Not present ON

L2/L3 Not present OFF

Figure 3-79 L1.2_RET Symbolic Overview

PCIe Controller
iso_vmain_to_vaux User
(DWC_pcie_ctl)
Application
All Controller Logic iso Logic
pm_en_vmain_n (DWC_pcie_core)
pm_save_state_req
Retention
Registers
pm_restore_state_req

PMC
iso

iso_vmain_to_vaux

pm_en_vmain_n

DWC_pcie Autonomous
_clkrst.v L1.2 SoC
Power
Switch

Power Domains
VMAIN
PD_VAUX
PD_VMAIN_SW
VMAIN
(pcie_iip_device_upf)

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Figure 3-80 L1.2_RET Simple Timing


VMAIN
PD_PHY
PD_VMAIN_SW assume ack_en_vmain =1

pm_link_st_in_l1sub

save_state

iso_vmain_to_vaux

iso _vl1on_to_vaux

core_rst_n

en_vmain_n

app_req_exit_l1

restore_state

3.12.7.7 UPF Files

A set of configuration-specific UPF files which are supported by VTB simulations and synthesis are created
by the coreConsultant tool in workspace/upf. The main UPF file defines:
■ Power domains
■ Isolation rules
■ Level shifter rules
■ Retention cell technology cell name. You must edit the UPF and replace this with the actual name of
the retention registers in your technology vendor s library.
■ Power supplies
■ Power states
■ Power state table

Note For more information, see the “UPF Flow and Methodology” section in the User Guide

3.12.7.8 P2.NoBeacon Support

P2.NoBeacon is a custom powerdown encoding supported by Synopsys PHYs that enables deeper power
saving as compared to the P2 state. To enable the controller to drive the PHY’s P2.NoBeacon state you must
set the parameter CX_P2NOBEACON_ENABLE to ‘1’.
When this feature is enabled,
■ The controller/PHY exits from L2/P2 only when PERST# is de-asserted. Beacon is not supported as
an exit condition by the PHY, and is ignored
■ mac_phy_powerdown drives P2.NoBeacon encoding, instead of P2 encoding, when the link goes to L2
To configure P2.NoBeacon encoding use CX_PIPE43_P2NOBEACON_ENCODING parameter. The default
value of this parameter is 4'b1111. To disable this feature, set P2NOBEACON_ENABLE field of the
PHY_INTEROP_CTRL_OFF register to ‘0’.

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Completion Timeout Ranges PCI Express SW Controller Databook

3.13 Completion Timeout Ranges


Timeout ranges are supported as defined in the PCI Express Base Specification, Revision 4.0, Version 1.0. The
controller supports all ranges. The Device Control 2 Register has a default equal to the default in the
specification: 0000b Default range: 50 us to 50 ms. When the default is used, then the timeout is in Range B:
0101b: 16 ms to 55 ms. This range is chosen for the default because the PCI Express Base Specification, Revision
4.0, Version 1.0 states, “It is strongly recommended that the completion Timeout mechanism not expire in
less than 10 ms”. Table 3-74 illustrates the specification values versus the PCI Express controller values for
the ranges.

As the PCIe specification states, This mechanism is intended to be activated only when there
Attention is no reasonable expectation that the completion is returned, and should never occur under
normal operating conditions.

Table 3-74 Comparison of PCIe Specification and Synopsys PCIe Controller Completion Timeout Ranges
(CX_CPL_TO_RANGES_ENABLE =1)
PCIe controller PCIe controller
Range Encoding Spec Minimum Spec Maximum Minimum Maximum

Default 0000b 50 us 50 ms 28 ms 44 ms (M-PCIe: 45)

A 0001b 50 us 100 us 65 us 99 us (M-PCIe: 100)

A 0010b 1 ms 10 ms 4.1 ms 6.2 ms (M-PCIe: 6.4)

B 0101b 16 ms 55 ms 28 ms 44 ms (M-PCIe: 45)

B 0110b 65 ms 210 ms 86 ms 131 ms (M-PCIe: 133)

C 1001b 260 ms 900 ms 260 ms 390 ms (M-PCIe: 398)

C 1010b 1s 3.5 s 1.8 s 2.8 s (M-PCIe: 2.8)

D 1101b 4s 13 s 5.4 s 8.2 s (M-PCIe: 8.4)

D 1110b 17s 64 s 38 s 58 s (M-PCIe: 59)

Note If CX_CPL_TO_RANGES_ENABLE =0, the default timeout range is 8ms to 12 ms.

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PCI Express SW Controller Databook Crosslink

3.14 Crosslink
Crosslink allows a downstream port to be connected to another downstream port or an upstream port to be
connected to another upstream port. When a crosslink capable port negotiates a crosslink connection, the
port changes its behavior accordingly (see description of device_type input in “SII: Global Controller
Control” on page 306. For this reason crosslink is supported in the SW controller because this product
already contains the functionality for both upstream and downstream support.
Crosslink provides more than simply the ability to connect two like ports together. For instance, a DM
operating in EP mode that negotiates a crosslink connection switches to RC mode and follows all of the PCI
Express Base Specification, Revision 4.0, Version 1.0 rules for an RC.
Part of the crosslink functionality requires a random timeout to be used. Your application is required to
provide this non-zero value on the app_crosslink_time[7:0] input. Your application must update this
value randomly every time the controller pulses the smlh_crosslink_time_request signal. The
controller samples the app_crosslink_time[7:0] inputs 4 us later for a CX_FREQ =1 configuration, 8 us
later for a CX_FREQ =2 configuration, and 16 us later for a CX_FREQ =3 configuration, after it pulses the
smlh_crosslink_time_request signal.
The crosslink feature is enabled by the CX_CROSSLINK_ENABLE configuration parameter.

To be compliant with the PCI Express Specification and to make sure crosslink functions
Note properly when two instances of the same device are connected together, the random timeout
must be unique to each device.

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TLP Processing Hints PCI Express SW Controller Databook

3.15 TLP Processing Hints


TLP Processing Hints (TPH) allows an application to provide or process hints on a per transaction basis to
optimize the processing of transactions targeting memory space. Posted and non-posted requests targeting
memory space can use the PH and 2-byte ST fields in the header. For more information, see the PCI Express
ECN TLP Processing Hints document. The switch port controller inherently (without extra configuration)
supports TPH by passing through all of the TLP reserved header fields (including TPH information) on the
inputs and outputs defined in “Peer-to-Peer Signals” section in the “Signal Descriptions” chapter.

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PCI Express SW Controller Databook Atomic Operations (AtomicOps)

3.16 Atomic Operations (AtomicOps)


You can enable support for AtomicOps by setting the CX_ATOMIC_ENABLE parameter. AtomicOps defines
three new PCIe request TLPs:
■ Fetch and Add (FetchAdd)
■ Unconditional Swap (Swap)
■ Compare and Swap (CAS)
FetchAdd and Swap supports 32-bit and 64-bit operand sizes. CAS supports 32-bit, 64-bit, and 128-bit
operand sizes. For more information, see the PCI Express ECN Atomic Operations PCI-SIG document.
When you enable AtomicOps, the controller receives and forwards AtomicOp TLPs to your application, and
generates AtomicOp TLPs in response to requests from your application on the XALI client interfaces. Your
application must generate the required completion for any AtomicOps that are passed to it. The PCI Express
controller does not generate completions for AtomicOps.
Four bit fields in the Device Capabilities 2 Register allow your software to discover the completer
capabilities for PCIe functions, and the AtomicOp routing capabilities of routing elements. Two bit fields in
the Device Control 2 Register allow your software to program a function, enabling it to:
■ Initiate AtomicOp requests
or
■ Block the egress port of a routing element (SW) to avoid forwarding an AtomicOp request to a compo-
nent that should not receive it.

Limitations
■ When you enable 128-bit Atomic CAS instructions (through the CX_ATOMIC_128_CAS_EN configura-
tion parameter), you must configure the controller (through the RADM_NP_DCRD_VCn configuration
parameter) to advertise more than one non-posted data credit on at least one VC.
■ The controller rejects AtomicOps that target the ELBI, and returns a completion with CA status.
■ AtomicOp TLP type cannot be nullified on TX.

Internal Address Translation Unit (iATU) Support


The “Internal Address Translation Unit (iATU)” on page 178 supports AtomicOps. Outbound address
translation is provided through address matching. By correctly programming the type field, a matched
address can be translated into an AtomicOp. The setting of the format field is automatically handled within
the controller.
For inbound address matching, you can program the iATU to also match other fields, including the type
field. The iATU also supports fuzzy match mode to allow a group of requests to be matched to a partial type
field. When fuzzy mode is set (bit 27 of the iATU Control 2 Register, and the type[4:2] field (iATU
Control 1 Register) is set to 3'b011, all AtomicOp requests are matched.
Atomic Routing - Egress Blocked Support
When AtomicOp Egress Blocking is enabled through the Device Control 2 Register in an egress port (A in
Figure 3-81), and an AtomicOp request is scheduled to or go out that port, then that port must:
■ Handle the request as an AtomicOp Egress Blocked error by setting the appropriate bit in the Uncor-
rectable Error Status Register.

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■ Return a completion with a completion status of UR.


A possible way to do this (using a switch as an example) is:
■ Set As AtomicOp Egress Blocking bit in the Device Control 2 Register.
■ Design an AtomicOp Detector (C in Figure 3-81) in your application logic that:
a. Detects an AtomicOp forwarded by the ingress/downstream port (B in Figure 3-81).
b. Discards (blocks) that AtomicOp.
c. Generates downstream completion with status of UR1, for the blocked AtomicOp.
d. Sets the AtomicOp Egress Blocked error status bit in the egress port using the app_err_bus[8].

Figure 3-81 Example of AtomicOp Egress Blocking Using Switch


Upstream Device not
supporting AtomicOps

DWC_pcie_sw A
(Egress Port/USP)

cfg_atomic_egress_block

app_err_bus[8]
Upstream
Traffic
Downstream
Traffic

UR Cpl
Discard
AtomicOp enable
Detector
1 0
detected demux
0 1
mux
C

Switch Application
1
Logic
Upstream Atomic
2 Request
Downstream
UR Cpl

DWC_pcie_sw B
(Ingress Port/DSP)

1. The unsupported request detected bit in the Device Status register is not set.

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PCI Express SW Controller Databook TLP Prefix

3.17 TLP Prefix


The TLP prefix mechanism extends the TLP by adding DWORDs in front of the TLP header to carry
additional information. The controller supports this feature when you set the parameter CX_NPRFX >0. The
controller forwards TLP prefixes unaltered. It validates each prefix by checking its format field before
forwarding it. Each validated prefix has its type field read to determine if it is Local or End-End. Only
End-End prefixes are included in the ECRC (if enabled). The controller analyzes the extracted prefixes to
ensure that the TLP prefix rules are met.

Features and Limitations


■ The controller supports a maximum of seven prefixes, including a maximum of four End-End
prefixes.
■ There is no prefix support for messages which are handled over the SII (such as LTR messages) or over
the VMI (vendor-defined messages).

End-End TLP Prefix Blocking (RC mode only)


When enabled, your application must report blocking errors on the SII. It must set the End-End TLP Prefix
Blocking bit field in the Device Control 2 Register (DEVICE_CONTROL2_DEVICE_STATUS2_REG) in ports
that support End-End TLP Prefixes but that do not support forwarding of End-End TLP Prefixes.

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Separate Refclk Independent SSC (SRIS) PCI Express SW Controller Databook

3.18 Separate Refclk Independent SSC (SRIS)


You can enable support for the Separate Refclk with Independent Spread Spectrum Clocking (SRIS) feature
as defined by the PCI-SIG ECN, by setting CX_SRIS_SUPPORT =1. This also populates the app_sris_mode
input pin. When CX_SRIS_SUPPORT =1 and app_sris_mode =1, then L0s is not supported and must not
be advertised in the ASPM Support Capability Registers.

Table 3-75 SKP Ordered Set Intervals in SRIS and non-SRIS Modes
SKP Ordered Set Intervals SKP Ordered Set Intervals
CX_SRIS_SUPPORT app_sris_mode (8b/10b Encoding) (128b/130b Encoding)

Normal (between 1180 and 1538


0 NA Normal (between 370 to 375 Blocks)
Symbol times)

1 0 Normal Normal

1 1 Short (less than 154 Symbol times) short (less than 38 Blocks)

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PCI Express SW Controller Databook Readiness Notifications (RN)

3.19 Readiness Notifications (RN)


The controller supports the optional Readiness Notification features as outlined in Table 3-76. These
features provide multiple mechanisms for a device or function to notify the host software that it is
configuration-ready. A configuration-ready function always responds to a valid configuration request with
a completion indicating successful completion status, and not CRS. For more information, see Readiness
Notification in the PCI Express Base Specification, Revision 4.0, Version 1.0.

Table 3-76 Controller Operations

Parameter Name Description

Enable Immediate Readiness.


When you set the Immediate Readiness bit in the PCI header Status Register, the
CX_RN_IMM_EN
function is configuration-ready. Software is exempt from all requirements to delay
configuration accesses following any type of reset or exit from low-power states.

Enable Readiness Time Reporting (RTR).


RTR provides an optional mechanism for describing the time required for a device or
function to become configuration-ready. Software is permitted to issue requests to
CX_RN_RTR_EN
the device or function (following any type of reset or exit from low-power states) after
waiting for the time advertised in this capability and need not wait for the (longer)
times required elsewhere.

Enable Function Readiness Status (FRS).


FRS provides an optional mechanism for messaging the host software when a
function has become configuration-ready. The controller autonomously sends a
Vendor-Defined Message (VDM) with no payload when any of these events occur:
■ Completion of D3hot to D0 transition
■ DRS message received (by downstream port)

1. Your application can delay/prevent FRS message generation by setting app_p-


f_frs_ready =0; (or app_vf_frs_ready for VFs)
CX_RN_FRS_SUPPORTED 2. When multiple FRS events occur in close proximity:
■ Sometimes the controller may transmit a single FRS.

■ The reason field in the transmitted message may contain a code from any of
the events.
3. Software is permitted to issue requests to the function (following any of these
events) after receiving an FRS message from this function and need not wait for
the (longer) times required elsewhere in the specification for these events.
4. The DSP controller asserts the cfg_up_drs_to_frs output and sends an FRS
message with the reason code set to “DRS Message Received” when:
■ It receives a DRS message, and

■ PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STA-
TUS_REG is 2b10

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Parameter Name Description

Enable Device Readiness Status (DRS).


DRS provides an optional mechanism for messaging the host software when a
device has become configuration-ready.
The controller autonomously sends a Vendor-Defined Message (VDM) with no
payload when any of these events occur:
■ Exit from Cold, Warm, or Hot Reset
■ Exit from Loopback or Disabled
■ Exit from L2/L3_Ready
■ Port transitions from DL_Down DL_Up status

CX_RN_DRS_SUPPORTED
1. Your application can delay/prevent DRS message generation by setting
app_req_retry_en/app_pf_req_retry_en =1 or app_drs_ready =0.
2. Software is permitted to issue requests to the function (following any of these
events) after receiving an DRS message from this function and need not wait for
the (longer) times required elsewhere in the specification for these events.
3. The DSP controller asserts the cfg_drs_msi output when all of the following are
true:
■ It receives a DRS message

■ PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STA-
TUS_REG is 2b01
■ MSI or MSI-X is enabled

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PCI Express SW Controller Databook Precision Time Measurement (PTM)

3.20 Precision Time Measurement (PTM)


The controller supports the optional PTM feature (CX_PTM_ENABLE =1) as defined in Section 6.22, Precision
Time Measurement (PTM) Mechanism of the PCI Express Base Specification, Revision 4.0, Version 1.0. This
enables the coordination of timing information across multiple devices with independent local time-bases.
The PTM synchronization is initiated from a downstream requester (USP) to an upstream responder (DSP).
The controller handles the entire timestamp update process without software intervention. Each current
(t#n) and previous timestamp (t#n-1) value as well as other context information (clock) can be read from the
VSEC registers (PTM_REQ_*_OFFPTM_RES_*_OFF) by software.

3.20.1 PTM Timers


The controller implements 1us, 100us, and 10ms (used to invalidate local context) timers as per the
requirements of the PCI Express Base Specification, Revision 4.0, Version 1.0. The 10 ms timer is also used for
automatic update of PTM context by the Requester (USP).

3.20.2 Transmit and Receive Latencies


A key operational goal of PTM is to stamp the time at which a message is transmitted from the physical
boundary of the PCIe device. The Tx latency is the time that it takes a message to travel from the boundary
of the controller to the boundary of the PCIe device. It is added to the time at which the message left the
controller. The Rx latency is the time that it takes a message to travel from the boundary of the PCIe device
to the boundary of the controller. It is subtracted from the time at which the message reaches the controller.
The Latency registers may be written to at any time with a more accurate value if required.
For example:
■ t1 = Local PTM Clock time when message leaves controller + PTM_REQ_TX_LATEN-
CY_OFF.PTM_REQ_TX_LATENCY
■ t3 = Local PTM Clock time when message leaves controller + PTM_RES_TX_LATEN-
CY_OFF.PTM_RES_TX_LATENCY
■ t2 = Local PTM Clock time when message received by controller - PTM_RES_RX_LATEN-
CY_OFF.PTM_RES_RX_LATENCY
■ t4 = Local PTM Clock time when message received by controller - PTM_REQ_RX_LATEN-
CY_OFF.PTM_REQ_RX_LATENCY
Note: The Tx latency includes all delays from the moment timestamp is captured, to the time the message
reaches the port pins. The Rx latency includes all delays from the time the message reaches the port pins, to
the time the timestamp is captured. These delays depend on the characteristics of the PHY used, skew on
the link, and deviation between the reference clocks of the two ports. There may be a dependency on link
width and the current link speed also.
For best accuracy the Tx and Rx latency values should be programmed during initialization, for each
supported link speed. For more information, see “Programming Tx and Rx Latencies for Each Link Speed”
on page 264. The controller automatically selects the Tx and Rx latency based on current link speed.

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Transmit and Receive Latencies PCI Express SW Controller Databook

Figure 3-82 Tx and Rx Latencies


PTM Request Message PTM Response or ResponseD
Received Message Sent
t2 updated t3 updated
t2' updated t3' updated

Controller Logic

Receive Latency Transmit Latency

Physical Boundary

PTM Response
Increasing Time PTM Request Message or ResponseD Increasing Time
Message

Physical Boundary

Transmit Latency Receive Latency

Controller Logic

PTM Request Message Sent PTM Response or ResponseD


t1 updated Message Received
t1' updated t4 updated
t4' updated

3.20.2.1 Programming Tx and Rx Latencies for Each Link Speed

The Tx and Rx Latency registers are programmed through an indirect addressing scheme using an index
register (PTM_[RES|REQ]_LATENCY_REG_SEL_OFF), to reduce the address footprint in the PCI Express
extended configuration space. The index register has Responder/Requester Latency Register Write Select
field (PTM_[RES|REQ]_LATENCY_REG_SEL), referred to as index, to determine which Tx or Rx Latency
viewport register (PTM_RES_[TX|RX]_LATENCY_OFF) to program/read for each link speed. Table 3-77
provides the index to link speed mapping.

Table 3-77 Index to Link Speed Mapping

PTM_[RES|REQ]_ESM_SEL PTM_[RES|REQ]_LATENCY_REG_SEL Link Speed (GT/s)

PCI Express Speed Mode

0 0 2.5

0 1 5

0 2 8

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PCI Express SW Controller Databook Transmit and Receive Latencies

PTM_[RES|REQ]_ESM_SEL PTM_[RES|REQ]_LATENCY_REG_SEL Link Speed (GT/s)

0 3 16

0 4 32

CCIX ESM Speed Mode (CX_CCIX_ESM_SUPPORT =1)a

1 0 20

1 1 25

a. Additional ESM Speeds

If the Tx and Rx latency registers are not programmed, the default latency values are the same for all speeds,
and are set by configuration parameters, as follows:
■ Tx Latency =CX_PHY_TX_DELAY_PHY + CX_PHY_TX_DELAY_MAC
■ Rx Latency =CX_PHY_RX_DELAY_PHY + CX_PHY_RX_DELAY_MAC

Programming Examples
Example 1: To setup PTM Requester Tx Latency to 56ns and Rx Latency to 334ns for 2.5 GT/s
1. Setup speed mode (PCI Express or CCIX ESM)
Write 1'b0 to PTM_REQ_ESM_SEL, to set PCI Express speed mode
2. Setup the index
Write 32'h0000_0000 to PTM_REQ_LATENCY_REG_SEL, to select 2.5 GT/s Latency viewport Tx and Rx
registers
3. Write the Tx/Rx Latency values
Write 32'h0000_0038 to PTM_REQ_TX_LATENCY, to set 2.5 GT/s Tx latency to 56 ns
Write 32'h0000_014E to PTM_REQ_RX_LATENCY, to set 2.5 GT/s Rx latency to 334 ns
Example 2: To setup PTM Responder Tx Latency to 24ns and Rx Latency to 115ns for 8 GT/s
1. Setup speed mode (PCI Express or CCIX ESM)
Write 1'b0 to PTM_RES_ESM_SEL, to set PCI Express speed mode
2. Setup the index
Write 32'h0000_0002 to PTM_RES_LATENCY_REG_SEL, to select 8 GT/s Latency viewport Tx and Rx
registers
3. Write the Tx/Rx Latency value
Write 32'h0000_0018 to PTM_RES_TX_LATENCY, to set 8 GT/s Tx latency to 24ns
Write 32'h0000_0073 to PTM_RES_RX_LATENCY_OFF register, to set 8 GT/s Rx latency to 115ns
Example 3: To setup PTM Requester Tx Latency to 7ns and Rx Latency to 18ns for 20 GT/s
(CX_CCIX_ESM_SUPPORT =1)
1. Setup speed mode (PCI Express or CCIX ESM)
Write 1'b1 to PTM_REQ_ESM_SEL, to set CCIX ESM speed mode

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Requester (USP) Features PCI Express SW Controller Databook

2. Setup the Index


Write 32'h0000_0004 to PTM_REQ_LATENCY_REG_SEL, to select 20 GT/s Latency viewport Tx and Rx
registers
3. Write the Tx/Rx Latency value
Write 32'h0000_0007 to PTM_REQ_TX_LATENCY, to set 20 GT/s Tx latency to 7ns
Write 32'h0000_0012 to PTM_REQ_RX_LATENCY, to set 20 GT/s Rx latency to 18ns

You can inspect the VTB test case tl_ptm_latency.sv at


Note <workspace>/doc/html/vtb/testenv/classtl__ptm__latency.html. For more
information on how to determine latency values by simulation, see “Detailed Description”
section.

3.20.3 Requester (USP) Features


■ Integrated hardware for scheduling of requests to start PTM dialogs

Figure 3-83 PTM Requester (USP)


Requester
Responder

TX Processing Path

PTM Request Message


TX PTM Request RX Received
Message t2 updated
ptm_manual _update _pulse PTM Request
Message t2' updated
SET OR Rx Latency
PTM_REQ_CONTROL_OFF D Q OR Generator PTM Request Message
register
PTM_REQ_START_UPDATE Sent Tx Latency
field (self-clearing) CLR Q
1
Trigger t1 updated
Request t1' updated

ptm_auto_update _signal
SET OR EN
PTM_REQ_CONTROL_OFF D Q 10 mS
register PTM Timer
PTM_REQ _AUTO_UPDATE_ENABLED
field CLR Q

VSEC Registers
(PTM_REQ_*)
PTM Response or
Timestamps ResponseD Message
Received
t4 updated
1uS / t4' updated
100 uS name
PTM
Update PTM PTM Master Time at t 1' is
3 Timers
Context Clock Software calculated when
access
ResponseD message is
received, and Local Clock Tx Latency
is also updated Rx Latency
PTM Request
Message Receiver
PTM Response or ResponseD
PTM Response Message Sent
RX or ResponseD TX
t3 updated
Message t3' updated
RX Processing Path
Receive
2
Response

■ Requester indicates PTM response timeout (through ptm_req_response_timeout) if no PTM


response is received within 100µs of sending a PTM request

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PCI Express SW Controller Databook Requester (USP) Features

When PTM context is invalidated due to duplicates or replays, speed change, or L0 exit,
the Requester waits for a PTM response or for 100µs timeout since the previous request
was sent before allowing a new update cycle to start. If a timeout occurs while waiting,
Note ptm_req_response_timeout is asserted. To check for unexpected
ptm_req_response_timeout assertions, externally AND the timeout indication with the
ptm_updating output.

■ Requester automatically updates PTM context (starting dialogs) when enabled using any or all of:
❑ Automatic trigger every 10ms (can be enabled through top-level pin or through a register)
❑ Manual trigger through top-level pin, if ptm_trigger_allowed is asserted
❑ Manual trigger through a register write, if ptm_trigger_allowed is asserted or PTM_REQ_MAN-
UAL_UPDATE_ALLOWED field in the PTM_REQ_STATUS_OFF register is set
■ Requester indicates that a PTM update is in progress (through ptm_updating)
■ Requester indicates reception of duplicate PTM TLP (through ptm_req_dup_rx) while PTM updates
are in progress, or between updates when PTM context is valid

If a new update is started immediately after context was invalidated due to duplicate
TLP it results in a double assertion of the ptm_req_dup_rx output and the update is
Note delayed by a cycle. This can happen when auto-update is used.

■ Requester indicates that a PTM request is replayed (through ptm_req_replay_tx) while PTM
updates are in progress, or between updates when PTM context is valid
■ Local PTM Clock
❑ Runs on core_clk, counts time in non-integer nanosecond, and its minimum granularity is
defined by the core_clk frequency
❑ Auto-updated on PTM context refresh
❑ Can also be updated by software
❑ Can be read by software
❑ Available through top-level port
■ Context automatically invalidated when:
❑ core_clk stops or runs at the wrong frequency (for example, in L1 substates or when the link
speed is changing), or
❑ PTM is disabled by clearing the PTM_ENABLE bit in the PTM_CONTROL_OFF register, or
❑ PTM response timeouts (the requester restarts the PTM dialog when the auto-update or manual
update start conditions are met), or
❑ A duplicate PTM TLP is received or a replay TLP is sent (if waiting for a response the requester
waits for 100µs since the last non-duplicate request has been sent, before allowing a new PTM
dialog to be started)

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If PTM is disabled by clearing the PTM_ENABLE bit, it is recommended to wait for some
time to allow the PTM Responder in the link partner to complete sending a response
Note before re-enabling PTM. The wait time will depend on the maximum response time of
the PTM Responder.

■ Context information stored in PTM Requester VSEC (PTM_REQ_*_OFF); one instance shared across all
functions):
❑ Provides access to timestamps of most recent context refresh
❑ Provides notification when context is valid
❑ Programmable Tx and Rx latency values for each link speed, automatically selected based on
current link speed
■ Requester prevents low power entry due to ASPM during PTM updates

3.20.4 Responder (DSP) Features


■ Integrated hardware for scheduling of PTM responses to dialog requests when context is valid
■ Timestamp generation when PTM Messages are detected

Figure 3-84 PTM Responder (DSP)


Requester Responder

PTM Request
Message Received
t2 updated
t2' updated

RX Processing Path
PTM Request Message Sent
t1 updated PTM Request
TX RX
t1' updated Message
PTM Request
Rx Latency Message Receiver

Tx Latency
Receive
1 Request

VSEC Registers
(PTM_RES_*)

Timestamps

1uS /
100 uS name
PTM
PTM Timers
Clock Software
access
PTM Response or
ResponseD Message
Sent
Generate
Tx Latency t3 updated 2 Response
Rx Latency t3' updated
PTM Response or ResponseD
Message Received
t4 updated PTM Response
t4' updated PTM Response Message Generator
RX or ResponseD TX

PTM Master Time at t 1' is Message


calculated when ResponseD
TX Processing Path
message is received , and
Local Clock is also updated

■ Local PTM Clock

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PCI Express SW Controller Databook Local PTM Clock Scaling

❑ If CX_PTM_EXTERNAL_MASTER_TIME =1 an external master time can be used to set the clock value
Note: The external master time is latched when ptm_external_master_strobe signal is set to 1.
❑ Can also be updated by software
❑ Can be read by software
❑ Available through top-level port
■ Context automatically invalidated when core_clk stops, or runs at the wrong frequency (for
example, in L1 substates or when the link speed is changing), or when PTM is disabled by clearing the
PTM_ENABLE bit in the PTM_CONTROL_OFF register. When the controller asserts ptm_respond-
er_rdy_to_validate signal, your application can re-validate the context by either,
❑ [CX_PTM_EXTERNAL_MASTER_TIME =1]: Updating the local PTM clock using the ptm_exter-
nal_master_time and ptm_external_master_strobe signals, which automatically asserts
the ptm_context_valid signal, or
❑ [DBI Access]: Updating the local PTM clock by writing to PTM_RES_LOCAL_LSB_OFF and
PTM_RES_LOCAL_MSB_OFF registers, and then setting the PTM_RES_CCONTEXT_VALID field of
PTM_RES_CONTROL_OFF to 1, which automatically asserts ptm_context_valid signal
■ Root Support
❑ Ideally a PTM root behaves like a responder with permanently valid context. However,
- If the PTM root enters low power modes or changes link frequency, PTM context is invalidated
(indicated by ptm_context_valid =0)
- Following PTM context invalidation, the application must re-validate PTM context, by using
either the PTM master time interface signals or the PTM responder VSEC registers, as described in
the previous list item
❑ PTM messages must not contain TLP prefixes
■ Context information stored in PTM Responder VSEC (PTM_RES_*_OFF):
❑ Provides access to timestamps of most recent context refresh
❑ Provides notification when context is valid
❑ Programmable Tx and Rx latency values for each link speed, automatically selected based on
current link speed

3.20.5 Local PTM Clock Scaling


PTM clock scaling feature allows the local PTM clock to increment a programmable non-integer nanosecond
amount in each controller clock period. This allows the PTM local time to remain coherent if there is a
frequency deviation between PTM Requester and Responder. PTM clock scaling also allows the controller
to use PTM when the clock period is a non-integer nanosecond multiple, for example when running at CCIX
ESM data rates.

3.20.5.1 PTM Requester

To enable this feature set the PTM_REQ_SCALED_CLOCK_T_EN field of PTM_REQ_SCALED_CLOCK_T_OFF


register to ‘1’ (this bit can be set only when ptm_context_valid is set). You can set a 24-bit value
consisting of an 8-bit integral part (nanoseconds) and 16-bit fractional part (1/216 nanoseconds) using
PTM_REQ_SCALED_CLOCK_T_INT and PTM_REQ_SCALED_CLOCK_T_FRAC fields of the
PTM_REQ_SCALED_CLOCK_T_OFF register, which represents the scaled local PTM clock period.

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Local PTM Clock Scaling PCI Express SW Controller Databook

The clock scaling procedure is as follows:


■ Following the second and subsequent assertions of the ptm_clock_updated output signal, while
ptm_context_valid remains asserted, your application may read the PTM Requester Clock Correc-
tion register (PTM_REQ_CLOCK_CORR_LSB_OFF)
■ If the correction is below a threshold expected by your the application, your application may calculate
a scaled local PTM clock period value, based on the current default clock period value, the
programmed auto-update interval, and the contents of the PTM Clock Correction register (PTM_REQ_-
CLOCK_CORR_LSB_OFF)
■ Your application may write the scaled PTM clock period to PTM Requester's Scaled PTM Clock Period
register (PTM_REQ_SCALED_CLOCK_T_OFF), which represents the scaled local PTM clock period. This
should happen as quickly as possible after the ptm_clock_updated pulse to avoid error accumula-
tion
If the PTM context is invalidated, any pending scaled PTM clock period update should be aborted the clock
scaling steps listed in this section to be restarted.

3.20.5.2 PTM Responder

For the PTM Responder, your application fully controls PTM local clock updates. If the external master
clock runs from the same source clock as the PCIe controller, clock scaling is not needed. However, for
applications where the external master and PCIe controller run on unrelated clock sources, it may be
necessary to scale the local PTM clock period.
To enable this feature set the PTM_RES_SCALED_CLOCK_T_EN field of PTM_RES_SCALED_CLOCK_T_OFF
register to ‘1’ (this bit can only be set when ptm_context_valid is set). You can set a 24-bit value
consisting of an 8-bit integral part (nanoseconds) and 16-bit fractional part (1/216 nanoseconds) using
PTM_RES_SCALED_CLOCK_T_INT and PTM_RES_SCALED_CLOCK_T_FRAC fields of the
PTM_RES_SCALED_CLOCK_T_OFF register, which represents the scaled local PTM clock period.
The clock scaling procedure is as follows:
■ Your application initializes the PTM Responder with a known time from an external master
■ The PTM Responder counts local PTM time using the Nominal PTM Clock Period, which your appli-
cation can read from the PTM_RES_NOM_CLOCK_T_OFF register
■ Your application waits for a known time and reads the local PTM clock value again
■ Your application calculates the scaled PTM clock period using the deviation between the external
master clock and the local PTM clock, and writes the scaled PTM clock period to PTM Responder's
Scaled PTM Clock Period register (PTM_RES_SCALED_CLOCK_T_OFF), which represents the scaled
local PTM clock period
If the PTM context becomes invalid your application must reiterate the steps listed in this section.

3.20.5.3 Use of Scaled Clock Period and Clock Rate Changes

The PTM Requester and PTM Responder scaled clock period enable bits are cleared when the core_clk
rate changes, and can only be set when the clock rate change is complete. The core_clk rate is controlled
by LTSSM, using the mac_phy_rate signal. When mac_phy_rate changes, the register bits are cleared.
When the current data rate has been updated to match mac_phy_rate, setting of the bits is enabled.

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PCI Express SW Controller Databook Access Control Services (ACS)

3.21 Access Control Services (ACS)


The controller supports Access Control Services (CX_ACS_ENABLE =1) as described in PCI Express Base
Specification, Revision 4.0, Version 1.0.

Figure 3-85 ACS Overview

V ACS Source Validation

SW-USP B ACS Translation Blocking

R ACS P2P Request Redirect

C ACS P2P Completion Redirect


U R
E Switch Fabric U ACS Upstream Forwarding
T C
E ACS P2P Egress Control

T ACS Direct Translated P 2P


Indicates only Capability Structure and
U V B U V B
ports for the feature (no feature hardware )
SW-DSP SW-DSP Indicates implementation of hardware to
E R C T E R C T support the feature

Features and Limitations:


■ A DSP (single function or multi-function device) supports all access control types listed in Table 3-78.
■ An USP (multi-function device or SR-IOV enabled device) supports only peer-to-peer access control
types listed in Table 3-79.
■ Per-function egress control vector mask can be set using the parameter CX_ACS_UP_EGRESS_C-
TRL_MASK_# for USP. Setting a 1 in the egress control vector mask makes the corresponding bit in the
egress control vector read only.
Note: The egress control vector masks can be written through the DBI using the dbi_cs2 select at the
same address as the egress control vector.
■ Per-port egress control vector mask can be set using the parameter CX_ACS_DW_EGRESS_C-
TRL_MASK_# for DSP. Setting a 1 in the egress control vector mask makes the corresponding bit in the
egress control vector read only.
Note: The egress control vector masks can be written through the DBI using the dbi_cs2 select at the
same address as the egress control vector.

Table 3-78 ACS Violation Error Handling DSP

Parameter to be set in addition


Access Control Type to CX_ACS_ENABLE ACS Violation Error Handling

ACS Source Validation (V) CX_ACS_SRC_VALID ■ The controller returns CA status CPL for NP
requests.
■ The controller reports AER: ACS Violation Error.
Note: For NP Requests, If ACS violation is
ACS Translation Blocking non-fatal, Advisory Non-Fatal Error is reported.
CX_ACS_AT_BLOCK
(B) ■ The controller sets the Signaled Target Abort bit
in the PCI compatible Status, or Secondary
Status register.

ACS Upstream Forwarding ■ Not an error condition.a


CX_ACS_UP_FORWARD
(U)

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Parameter to be set in addition


Access Control Type to CX_ACS_ENABLE ACS Violation Error Handling

ACS P2P Request Redirect CX_ACS_P2P_REQ_REDIRECT_n ■ The controller does not take any action.
(R)b (n =0; n <=CX_NFUNC-1) ■ Your application logic should generate CPL for
NP requests.
CX_ACS_P2P_COMPL_REDIRECT ■ Your application logic can use the controller
ACS P2P Completion
_n signal app_err_bus[12] to detect ACS viola-
Redirect (C)a tion, and take action accordingly.
(n =0; n <=CX_NFUNC-1)

CX_ACS_P2P_EGRESS_CTRL_n
ACS P2P Egress Control (E)
(n =0; n <=CX_NFUNC-1)

CX_ACS_P2P_DIRECT_TRANSL_
ACS Direct Translated P2P
n
(T)
(n =0; n <=CX_NFUNC-1)

a. When CX_ACS_UP_FORWARD =1, DSP forwards TLPs within the memory/IO ranges upstream. When CX_ACS_UP_FOR-
WARD =0, these TLPs are treated as UR.
b. It is not used by the controller internally to gate peer-to-peer traffic.

Table 3-79 ACS Violation Error Handling

Parameter to be set in addition to


Access Control Type CX_ACS_ENABLE ACS Violation Error Handling

CX_ACS_P2P_REQ_REDIRECT_n ■ The controller does not take any


ACS P2P Request Redirect (R)a action.
(n =0; n <=CX_NFUNC-1)
■ Your application logic should
ACS P2P Completion Redirect CX_ACS_P2P_COMPL_REDIRECT_n generate CPL for NP requests.
(C)a (n =0; n <=CX_NFUNC-1) ■ Your application logic can use the
controller signal app_err_bus[12]
CX_ACS_P2P_EGRESS_CTRL_n to detect ACS violation, and take
ACS P2P Egress Control (E) action accordingly.
(n =0; n <=CX_NFUNC-1)

CX_ACS_P2P_DIRECT_TRANSL_n
ACS Direct Translated P2P (T)
(n =0; n <=CX_NFUNC-1)

a. It is not used by the controller internally to gate peer-to-peer traffic.

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PCI Express SW Controller Databook Completion Queue Management

3.22 Completion Queue Management


The controller provides the Completion Queue Management feature to allow operation with completion
queues sized appropriately for the expected round trip latency and available bandwidth. Typically this
results in smaller completion queues than those which are required when this feature is disabled. This
feature works as a high-level flow control mechanism limiting the number of outbound Non-Posted
requests when enough space to receive the associated completions is not available.
To enable Completion Queue Management feature set the parameter CX_CPLQ_MANAGEMENT_ENABLE to ‘1’.
The feature can be disabled at run-time by setting the CPLQ_MANAGEMENT_ENABLE field of
MISC_CONTROL_1_OFF register to ‘0’. If the feature is disabled, your application must implement logic to
prevent completion queue overflow.
Figure 3-86 describes the high level overview of Completion Queue Management operation.

Figure 3-86 Completion Queue Management Operation


XADM
Completion Queue Manager

XADM_MUX
Decide whether to
Scan the NP request 2 transmit or halt the
for the number of NP request Cpl_I/F
Data and Header
TLP A 1 Msg_I/F
credits required Mux_out
client0_tlp_* Client0_I/F

TLP B client1_tlp_* Client1_I/F


“Is
client2_tlp_* Client2_I/F
there enough
space in the
Completion
YES
Queue for the
expected
CPL?”

NO

The completion queue manager decides to transmit or halt the NP request transmission on a particular
transmit client interface (XALI 0/1/2) based on the number of split completions that can be expected in the
worst case, and free slots available in RADM header and data completion queues.
A few example scenarios that depict the completion queue operation are as follows:
Scenario 1: A 64 byte MemRd request at XALI0 complying with RCB rules can be completed two ways:
■ One Completion with 64bytes of data
■ Two Completions with Completion A data + Completion B data =64bytes (worst case scenario)
Considering the worst case, in this scenario the completion queue manager allows transmission of MemRd
request because the completion header queue has 2 free slots and the completion data queue has more than
64 bytes of space available, as described in Figure 3-87.

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Figure 3-87 Scenario 1: 64 Byte MemRd Request at XALI0


RCB = 64 bytes
64 bytes / 64 bytes = 1
Maximum expected CPL HDR = 1 + 1(misalignement) = 2

Expected CPL XADM


Completion Queue Manager
CPL DATA VC0 CPL HDR VC0
XADM_MUX
63 bytes
...
Cpl_I/F
TLP A
1 1
Msg_I/F
0 0
Mux_out
client0_tlp_* CPLQ HDR Client0_I/F
Free Slot >
MemReq client1_tlp_* 2 Client1_I/F
client2_tlp_* CPLQ DATA YES Client2_I/F
Free Slot >=
64

Layers3/2/1 PHY LINK PARTNER


RCB = 64 bytes
RADM_CPLQ_DDP_VC0 = 256 bytes
RADM
Queues
CPLQ DATA VC0 CPLQ HDR VC0
RADM_CPLQ_DDP_VC0 RADM_CPLQ_HDP_VC0
... ...
4 4
3 3 CPL

2 2 CPL DATA VC0 CPL HDR VC0


1 1 63 bytes
Filled ...
0 0
positions 1
0 0

Scenario 2: A 256 bytes MemRd request at XALI0 complying with RCB rules can be completed several
ways, the worst case would be five Completions with Completion A data + Completion B data +
Completion C data + Completion D data + Completion E data =256 bytes.
In this scenario, the completion queue manager does not allow transmission of MemRd request because
even though the completion header queue has 5 free slots, the completion data queue has space available for
248 bytes (62 DW) only, as described in Figure 3-88.

Figure 3-88 Scenario 2: 256 Byte MemRd Request at XALI0


RCB = 64 bytes
MemReq = 256 bytes / 64 bytes = 4
Maximum expected CPL HDR = 256 bytes / 64 bytes + 1 (mis-alignment)
=4+1
=5

Expected CPL XADM


Completion Queue Manager
CPL DATA VC0 CPL HDR VC0
XADM_MUX
255 bytes 4
... ...
Cpl_I/F
TLP A
1 1
Msg_I/F
0 0
Mux_out
client0_tlp_* CPLQ HDR Client0_I/F
Free Slot >
MemReq client1_tlp_* 5 Client1_I/F
client2_tlp_* CPLQ DATA Client2_I/F
Free Slot >=
256

Layers3/2/1 PHY LINK PARTNER

RCB = 64 bytes
RADM_CPLQ_DDP_VC0 = 256 bytes
RADM
Queues
CPLQ DATA VC0 CPLQ HDR VC0
RADM_CPLQ_DDP_VC0 RADM_CPLQ_HDP_VC0
... ...
4 4
3 3
2 2
1 1
Filled
0 0
positions

Scenario 3: In scenario 2, let us suppose that after some time the controller pops the header and data
completion queues. Now, enough space has been created in header and data completion queues to

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accommodate the halted MemRd completions, so the completion queue manager transmits the halted
MemRd request, as described in Figure 3-89.

Figure 3-89 Scenario 3: Transmission of Halted 256 Byte MemRd Request at XALI0
RCB = 64 bytes
MemReq = 256 bytes / 64 bytes = 4
Maximum expected CPL HDR = 256 bytes / 64 bytes + 1 (mis-alignment)
=4+1
=5

Expected CPL XADM


Completion Queue Manager
CPL DATA VC0 CPL HDR VC0
XADM_MUX
255 bytes
...
Cpl_I/F
TLP A
1 1
Msg_I/F
0 0
Mux_out
client0_tlp_* CPLQ HDR Client0_I/F
Free Slot >
MemReq client1_tlp_* 5 Client1_I/F
client2_tlp_* CPLQ DATA YES Client2_I/F
Free Slot >=
256

Layers3/2/1 PHY LINK PARTNER


RCB = 64 bytes
RADM_CPLQ_DDP_VC0 = 256 bytes
RADM
Queues
CPLQ DATA VC0 CPLQ HDR VC0
RADM_CPLQ_DDP_VC0 RADM_CPLQ_HDP_VC0
... ...
4 4
3 3 CPL

2 2 CPL DATA VC0 CPL HDR VC0


1 1 255 bytes
Popped ...
0 0
positions 1
0 0

Limitations
■ This feature is supported only for PCIe devices. It is not supported for PCI-X devices.
■ This feature is supported only when ECRC stripping is enabled (CX_ECRC_STRIP_ENABLE =1).
■ For correct operation of the completion queue management feature the following filter rules must not
be changed from the default value of 0.
❑ CX_FLT_MASK_CPL_LEN_MATCH
❑ CX_FLT_MASK_CPL_TC_MATCH
❑ CX_FLT_MASK_CPL_TAGERR_MATCH
❑ CX_FLT_MASK_CPL_ECRC_DISCARD
❑ CX_FLT_MASK_DABORT_4UCPL

Completion Timeout
In the event of a Completion Timeout it is recommended that your application perform the following steps:
■ Disable completion queue management feature by setting the CPLQ_MANAGEMENT_ENABLE field of
MISC_CONTROL_1_OFF register to 0. This resets the completion queue counters to the initial value.
■ Wait until the completion queue is empty and there is no NP request pending in the LUT.
■ Enable completion queue management feature by setting the CPLQ_MANAGEMENT_ENABLE field of
MISC_CONTROL_1_OFF register to 1.

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3.22.1 Header and Data Completion Queue Size Calculation


When Completion Queue Management feature is enabled, the controller automatically calculates the
completion queue sizes for each VC based on the value of the following parameters entered in
coreConsultant:
■ Round Trip Latency [ns] which should take into account:
❑ Local Controller and PHY latencies
❑ Remote Controller and PHY latencies
❑ Retimers
❑ Response time of the remote side
■ Critical Request size [bytes], for which full bandwidth usage must be retained (commonly this is 64 bytes
due to cache line size).
Using the values of these parameters the controller automatically calculates:
■ Recommended number of TAGs , to keep the maximum bandwidth of the configuration for the Minimum
Request Size.
■ Header Completion Queue size [Hdr]. This is the number of entries required in the Completion
Header Queue to cover the expected latency given the available bandwidth. The controller considers
only two split completions per TAG when calculating this value, other possible split completions
scenarios are not taken into account. You can change this value to cover the worst case scenarios as per
your requirements.
■ Data Completion Queue size [bytes]. This is the size of the Completion Data Queue in bytes to cover
the expected latency given then available bandwidth.
■ Header/Data Completion Queue Depth, needed for the queue control logic. The controller sets the param-
eters RADM_CPLQ_HDP_VCn and RADM_CPLQ_DDP_VCn to these values.

Figure 3-90 Completion Queue Size Parameters in coreConsultant GUI

Legacy Method of Header and Data Completion Queue Size Calculation


It is generally mandatory to advertise infinite credits for completion queues according to the PCI Express
Base Specification, Revision 4.0, Version 1.0 to avoid deadlocks or ordering rule violations in the PCIe
hierarchy.
When completion queue credits are finite the completion queue sizes are determined by the credits. When
completion credits are infinite and completion queue management is disabled, the completion queue size
per VC is as big as the maximum possible request size times the maximum number of requests that your

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application can make. The completion header queue depth (CPLQ_HDP) and completion data queue depth
(CPLQ_DDP) are calculated as follows:
CPLQ_HDP = (CX_MAX_TAG + 1) * [CX_APP_RD_REQ_SIZE / RCB + 1]
CPLQ_DDP = [(CX_MAX_TAG + 1) * CX_APP_RD_REQ_SIZE / 4]/CX_NW
Where,
■ CX_MAX_TAG: Specifies the maximum number of simultaneous outbound PCIe non-posted requests in
total for all functions.
■ CX_APP_RD_REQ_SIZE: This parameter is used to set the depth of the receive completion data queue
(CX_CPLQ_DDP_VC*) when completions are in store-and-forward or cut-through modes, and comple-
tion credits are infinite. It is the maximum individual MRd size that your application (or AXI bridge
slave) makes.
■ RCB: Specifies the minimum Read Completion Boundary (RCB) of all CPLs with which the controller
inter-operates. For a root port this can be set to 128 bytes, all other components should assume an RCB
of 64 bytes unless they exist entirely within closed systems where the minimum RCB is known. This
parameter is used only to calculate the required size of the completion header queues when comple-
tion credits are infinite and the completion queues are not bypassed.
RCB (RC) = 128/64 bytes
RCB (no RC) = 64 bytes
■ CX_NW: Specifies the width of the datapath in dwords.
For example, for a configuration with CX_MAX_TAG = 255, CX_APP_RD_REQ_SIZE = 4096 bytes, RCB = 128
bytes, CX_NW = 256 bits, the completion queue header and completion queue data size per VC are calculated
as follows:
CPLQ_HDP = (255 + 1) * [4096 / 128 + 1] = 8448 (128 bits) = 135168 bytes
CPLQ_DDP = [(255 + 1) * 4096 / 4] / 8 = 32768 (256 bits) = 1048576 bytes
There is a relation between the number of tags and the latency of the PCIe link to optimize the design based
on the bandwidth expected. The higher the latency the higher the number of TAGs that can be used.

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4
Signal Interfaces

The descriptions for each I/O are given in the next chapter.

When you configure the controller in coreConsultant, you can access the I/O descriptions for
Attention your actual configuration at workspace/report/IO.html using the process described in the
“Creating Optional Views and Reports” section in the User Guide. This report comes from the
exact same source as the Databook but removes all the signals that are not in your actual
configuration.

RX_TLP is the number of TLPs processed per clock cycle and is also the number of receive queues per TLP
type per VC. It is 2 for 256-bit datapath configurations, and 1 for all other configurations.
This section describes any relevant timing protocols for the following signal interfaces.
■ “Transmit Interfaces (XALI0/1/2)” on page 279
■ “CCIX Transmit Interface (XALI_CCIX)” on page 286
■ “Receive Bypass Interface (RBYP)” on page 289
■ “Receive Request Interface (TRGT1)” on page 290
■ “CCIX Receive Request Interface (TRGT1_CCIX)” on page 293
■ “Data Bus Interface (DBI)” on page 296
■ “External Local Bus Interface (ELBI)” on page 298
■ “Message Signaled Interrupt (MSI) Interface” on page 300
■ “MSI-X Interface” on page 301
■ “Vendor Message Interface (VMI)” on page 305
■ “System Information Interface (SII)” on page 306
■ “PIPE Interface” on page 307
■ “PHY Register Bus Interface (PRBI)” on page 310

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4.1 Transmit Interfaces (XALI0/1/2)


XALI0 and XALI1 are two similar client interfaces connected to two clients at your application side. Each
client can be a requester or a completer. The XALI2 interface (if implemented) is identical to XALI0 and
XALI1. Requests on XALI0, XALI1, and XALI2 can be asserted in the same clock cycle. The XADM
automatically arbitrates requests received from the XALI0, XALI1, and XALI2 interfaces.

In the timing diagrams, the actual clock used to clock the interface might vary in low-power
Attention mode. In this case, you should use a different clock than the one indicated in the timing
diagram. For more information, see “Synchronous To Attribute” on page 55.

For more information on how to select these client interfaces, see the Configuration Guide
Hint
section in the Configuring the PCI Express controller chapter of the User Guide.

Differences Between the Three Transmit Client Interfaces


The XALI1 interface is identical to the XALI0 interface. Application logic can assert input signals on both
XALI0 and XALI1 on the same cycle; the controller arbitrates between them. The optional XALI2 interface is
present only when CLIENT2_POPULATED is defined. the XALI2 interface is identical to the XALI1 interface.
Application logic can assert input signals on XALI0, XALI1, and/or XALI2 on the same cycle and the
controller arbitrates between them.

4.1.1 Transmit Client Interface Protocol Rules


The transmit client provides information on the header bus and payload data on the data bus. The controller
does not have internal queues for transmit TLPs. After your application starts a transaction transfer request,
it must continue to stream data unless the controller halts the client interface. The protocol rules for each of
the transmit client interfaces (using the client0* signals as the example) are:
■ For transactions without an associated payload (for example MRd), the data valid (client0_tlp_dv)
signals must never be asserted. For more information, see Figure 4-91.
■ For transactions with an associated payload (for example MWr), the header valid (client0_tlp_hv)
and data valid (client0_tlp_dv) signals must be asserted in the same cycle for the header phase.
However, during the payload phase, client0_tlp_dv can be asserted without client0_tlp_hv
having to be asserted. For more information, see Figure 4-93.
■ The end of transaction indication signal (client0_tlp_eot) must be asserted during the last cycle of
data valid (client0_tlp_dv) or of header valid (client0_tlp_hv) when no payload is present. You
must not assert it at any other time.
■ When the xadm_client0_halt signal is asserted, your application must maintain the information on
the header bus and data bus.
■ When idle, the transmit client interface maintains xadm_client0_halt =1 by default. At the end of
a packet when client arbitration for the next packet is underway xadm_client0_halt may toggle.
The behavior of the xadm_client0_halt signal is dependent on the datapath width of the controller.
■ The client0_tlp_bad_eot signal is used to abort a transfer that is in progress. It must be asserted
on the same cycle as client0_tlp_eot.
■ Not all header information has to be driven dynamically. Some header input signals can be hardwired,
where suitable for your application.

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■ To send a message through the transmit client interface, your application asserts the message code on
client0_tlp_byte_en, and the last two DWORDs of the header through
client0_tlp_addr[63:0], where client0_tlp_addr[63:32] is the third DWORD (bytes 8-11) of
the header. When there is data to send with the message, your application sends the data through
client0_tlp_data, as with other TLP data. For more information, see “Message Generation” on
page 153.

Payload and Read Request Length rules


■ The controller does not check for TLP errors; instead it sends the TLP as presented on the XALI inter-
face.
■ The native PCIe controller does not check that the TLP payload size is less than the Maximum Payload
Size limit.
■ The native PCIe controller does not check that the TLP payload size is less than CX_MAX_MTU limit.
Exceeding this limit overflows the retry buffer, resulting in data corruption.
■ When address alignment is enabled (GLOB_ADDR_ALIGN_EN =1), your application logic must make
sure that the length of the TLP is less than the maximum payload supported. For more information,
see “Transmit Address Alignment” on page 282.

Header Reserved Fields


Access to the TLP headers reserved fields is through the signals described in “Peer-to-Peer Signals” section in
the “Signal Descriptions” chapter.

4.1.2 Transmit Client Transactions


The following diagrams illustrate example transactions on the transmit client interfaces:
■ Figure 4-91 depicts three memory read (MRd) request TLPs. The client0_tlp_eot and
client0_tlp_hv signals remain asserted for two back-to-back MRd TLPs. The TLP header inputs
remain valid until the controller de-asserts xadm_client0_halt. The controller asserts the xadm_-
client0_halt signal when it is not ready to process any transactions.
■ Figure 4-92 shows a memory write (MWr) request TLP. The TLP header and payload inputs remain
unchanged when xadm_client0_halt is asserted.
■ Figure 4-93 shows back-to-back MRd and MWr transactions. The client0_tlp_eot and
client0_tlp_hv signals remain asserted across multiple TLPs.
■ Figure 4-94 shows a completion TLP requested by client0.

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Figure 4-91 Client0 Transaction: MRd Request TLPs


TLP1 TLP2 TLP3

core_clk

client0_tlp_hv

client_tlp_dv

xadm_client0_halt

client0_tlp_eot

client0_tlp_data[DW-1:0]

client0_tlp_* MEM_RD MEM_RD MEM_RD


(TLP header signals)

Figure 4-92 Client0 Transaction: MWr Request TLPs

core_clk

client0_tlp_hv

client0_tlp_dv

xadm_client0_halt

client0_tlp_eot

client0_tlp_data[DW-1:0] W0 W1 W2 W3 W4

client0_tlp_*
MEM_WR
(TLP header signals)

Figure 4-93 Client0 Transaction: Back-to-Back MRd and MWr TLPs


TLP1 TLP2 TLP3 TLP4

core_clk

client0_tlp_hv

client0_tlp_dv

xadm_client0_halt

client0_tlp_eot

client0_tlp_dwen[NW-1:0] 0xF

client0_tlp_data[DW-1:0] W0

client0_tlp_* MEM_RD MEM_RD MEM_WR MEM_RD


(TLP header signals )

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Figure 4-94 Client0 Transaction: CPL TLP

core_clk

client0_tlp_hv

client0_tlp_dv

xadm_client0_halt

client0_tlp_eot

client0_tlp_dwen[NW-1:0] 0xF

client0_tlp_data[DW-1:0] W0 W1 W2 W3 W4

client0_tlp_* CPL
(TLP header signals )

4.1.3 Transmit Address Alignment


For outbound memory and I/O requests (but not for completions), the controller provides an address
alignment feature using the clienti_addr_align_en signal so that your application can have per-TLP
control of how the address is aligned on the transmit client interface. To enable this feature, set
GLOB_ADDR_ALIGN_EN. When address alignment is off1 for a packet (clienti_addr_align_en =0), your
application is responsible for setting the appropriate first and last byte enable (FBE, LBE) values and
presenting the payload in the correct format. The controller transmits it without realignment (if required).
When address alignment is on for a packet (clienti_addr_align_en=1), the controller uses the lower
two bits of the clienti_tlp_addr bus to determine the appropriate byte enable values and the alignment
of any data included for the transmitted TLP.
Address Alignment Off
When address alignment is off, the transmit client interface essentially becomes a DWORD interface for that
packet. In this case, your application must provide the TLP header exactly as it is to be inserted in the
outgoing TLP. Using client0 as the example, the requirements are:
■ client0_tlp_addr: Bits [1:0] must be 00, that is, the address must be DWORD-aligned.
■ client0_tlp_byte_en: The byte enables are placed directly into the transmitted TLP. Bits [3:0] form
the FBE; bits [7:4] form the LBE. Non-contiguous byte enables can be transmitted in this way.
■ client0_tlp_byte_len: Bits [1:0] must be set to 00. The byte length value must be rounded up to
the next DWORD boundary. For example, when the request is five bytes long, the value of bits [12:0]
must be eight.
■ client0_tlp_data: The controller transmits the data just as it is presented on client0_tlp_data.
Your application is responsible for shifting the data up according to the byte address.

1. Should always be off for completions.

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Figure 4-95 Client0 Transaction: Address Alignment Off


TLP1 TLP2 TLP3 TLP4

core_clk

client0_tlp_hv

client0_tlp_dv

xadm_client0_eot

client0_tlp_halt

client0_addr _align_en

client0_tlp_byte_en[7:0] 0x07 0x0e 0x1c 0x38

client0_tlp_addr [63:0] 0x0000000080000000 0x0000000080000000 0x0000000080000000 0x0000000080000000

client0_tlp_byte_len[12:0] 0x0004 0x0004 0x0008 0x0008

client0_tlp_data[127 :0] *0000000020100 *0000002010000 *0000201000000 *0020100000000

For read requests, the client0_tlp_data bus has no requirements. Figure 4-95 shows example waveforms
for the transmission of four 3-byte memory write requests with incrementing byte addresses starting from
0x80000000 and ending at 0x80000003. Note that the first enabled byte is shifted up for each request with
increasing address. Also, when the address plus length crosses a DWORD boundary (third TLP in Figure
4-95), the byte length goes directly from four to eight.

You must not use address alignment for completions and must set clienti_addr_align_en
Note
=0. Your application must drive the correct byte address on clienti_tlp_addr so that the
completion lower address bits [6:0] are derived from the DWORD-aligned address and FBE of
the original request.

Address Alignment On
When address alignment is on for a packet, the client interface becomes more of a byte interface. The
formatting information that your application provides is as follows:
■ client0_tlp_addr: The address is the full byte address of the first enabled byte of the request. That
is, the request must be byte-aligned.
■ client0_tlp_byte_en: Should be 0x0, that is, not used for a packet with address alignment on.
■ client0_tlp_byte_len: Must be the full byte length of the request.
■ client0_tlp_data: The first enabled byte of the request must be on bits [7:0] of this data bus. The
controller up-shifts the data in the transmitted TLP based on the lower two bits of the byte address.

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Figure 4-96 Client0 Transaction: Address Alignment On


TLP1 TLP2 TLP3 TLP4

core_clk

client0_tlp_hv

client0_tlp_dv

xadm_client0_eot

client0_tlp_halt

client0_addr _align_en

client0_tlp_byte_en[7:0] 0x00

client0_tlp_addr [63:0] 0x0000000080000000 0x0000000080000001 0x0000000080000002 0x0000000080000003

client0_tlp_byte_len[12:0] 0x0003 0x0003 0x0003 0x0003

client0_tlp_data[127 :0] *0000000020100 *0000000020100 *0000000020100 *0000000020100

Based on the address and byte length, the controller determines the FBE and LBE fields of the TLP. For read
requests, the client0_tlp_data signal has no requirements. For write requests, the controller determines
how many DWORDs of data payload is transmitted in the associated TLP. Figure 4-96 shows the same
sequence of memory write requests as Figure 4-95, except that address alignment is on. The data vector does
not change based on the byte address. The controller never generates a TLP with non-contiguous LBE/FBE.

When address alignment is enabled, application logic must make sure that the transmitted
Note
TLP sent has a length value less than the maximum payload supported. For example, when
maximum payload is set to 128 bytes (32 DWORDs) and your application sends a request of
128 bytes but with a non-DWORD-aligned address the controller sends the request with a
DWORD-aligned address and with a length of 33 DWORDs. This is detected as a malformed
TLP at the destination.

Address Alignment and Data Bus Cycles


For a write request, the number of clock cycles on your application data bus can be greater when address
alignment is off. This occurs when the data payload of the write request crosses the boundary of the data
vector size. Figure 4-97 shows two identical memory write requests on a 32-bit transmit data bus. The byte
address is 0x80000002 and the byte length is three. The first request has address alignment on and requires
only one cycle on the transmit client interface. The second request has address alignment off and requires
two clock cycles on the transmit client interface. This has no effect on aggregate bandwidth; the only
difference is where the TLP formatting is performed, by the controller (first request) or by your application
(second request).

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Figure 4-97 Client0 Transaction: Address Alignment and Data Bus Cycles
TLP1 TLP2 TLP3 TLP4

core_clk

client0_tlp_hv

client0_tlp_dv

xadm_client0_eot

client0_tlp_halt

client0_addr _align_en

client0_tlp_byte_en[7:0] 0x00 0x1c

client0_tlp_addr [63:0] 0x0000000080000002 0x0000000080000000

client0_tlp_byte_len[12:0] 0x0003 0x0008

client0_tlp_data[31:0] 0x00020100 0x01000000 0x00000002

Address Alignment and ECRC


When your application transmits requests across the client interface with ECRC included, the
clienti_addr_align_en signal must be zero for those TLPs that contain ECRC (TD =1). This is because
there is no way for the controller to know the value of the bytes below the first enabled bytes. When the
ECRC is computed over these unknown bytes, the validity of the ECRC in the transmitted TLP cannot be
guaranteed when clienti_addr_align_en is high for that TLP.

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CCIX Transmit Interface (XALI_CCIX) PCI Express SW Controller Databook

4.2 CCIX Transmit Interface (XALI_CCIX)


The CCIX specification relies on the use of a dedicated high priority Virtual Channel (VC) to transfer data
between devices. A dedicated XALI_CCIX interface for transmitting CCIX TLPs provides the following
advantages:
■ Minimize latency of CCIX traffic on the transmit path
■ Provide CCIX support without affecting the standard PCIe functionality
■ Minimize collision between standard PCIe traffic and CCIX traffic
XALI_CCIX interface implements a simple handshake mechanism between the controller and your
application.

4.2.1 CCIX Transmit Client Transactions


The following diagrams illustrate example transactions on the CCIX transmit client interface:
■ Figure 4-98 depicts an example of generic operation of XALI_CCIX interface when CCIX TLPs in PCIe
compatible TLP format are transmitted on XALI_CCIX interface.
■ Figure 4-99 depicts an example of generic operation of XALI_CCIX interface when CCIX TLPs in opti-
mized CCIX TLP format are transmitted on XALI_CCIX interface.
■ Figure 4-100 depicts an example scenario for a 128-bit controller when the amount of data transmitted
in one clock cycle is not enough to fill the complete ccix_tlp_data bus.
In the timing diagrams, hdri (where i is 1,2,3 and so on) represents the header for different TLPs, data1
represents the first data cycle, data2 represents the second data cycle, and so on.

Figure 4-98 XALI_CCIX PCIe Compatible TLP Format


           

CORE?CLK

CCIX?TLP?HV

CCIX?TLP?HDR;= HDR HDR HDR HDR

CCIX?TLP?DV

CCIX?TLP?DATA;$7 = DATA DATA DATA DATA DATA DATA

CCIX?TLP?EOT

CCIX?TLP?BAD?EOT

CFG?CCIX?OPT?TLP?EN

XADM?CCIX?TLP?HALT

For PCIe compatible TLP format the complete header bus is used (ccix_tlp_hdr[127:0]) to transmit the
header information.

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PCI Express SW Controller Databook CCIX TLP Header Fields and ccix_tlp_hdr Mapping

Figure 4-99 XALI_CCIX Optimized CCIX TLP Format


            

CORE?CLK

CCIX?TLP?HV

CCIX?TLP?HDR;= 2ESERVED?NOT?USED?FOR?OPTIMIZED?4,0?FORMAT

CCIX?TLP?HDR;= HDR HDR HDR HDR

CCIX?TLP?DV

CCIX?TLP?DATA;$7 = DATA DATA DATA DATA DATA DATA

CCIX?TLP?EOT

CCIX?TLP?BAD?EOT

CFG?CCIX?OPT?TLP?EN

XADM?CCIX?TLP?HALT

For optimized CCIX TLP format only 32 bits of the header bus are used (ccix_tlp_hdr[31:0]) to transmit
the header information. The remaining header bits are reserved.

Figure 4-100 XALI_CCIX Data Bus Usage Example for 128-bit Datapath
            

CORE?CLK

CCIX?TLP?DV

CCIX?TLP?DATA;= $7 $7 $7

CCIX?TLP?DATA;= $7 $7 $7 $7

CCIX?TLP?DATA;= $7 $7 $7 $7 $7

CCIX?TLP?DATA;= $7 $7 $7 $7 $7

CCIX?TLP?EOT

XADM?CCIX?TLP?HALT

Clock cycle one and clock cycle five in Figure 4-100 illustrate how the ccix_tlp_data bus is expected to be
used when the amount of data to transmit in one clock cycle is not enough to fill the complete
ccix_tlp_data bus. For both PCIe compatible TLP format and optimized CCIX TLP format the same
behavior applies.

4.2.2 CCIX TLP Header Fields and ccix_tlp_hdr Mapping


Table 4-80 illustrates the mapping between CCIX TLP header fields and the bits in the transmit CCIX
interface header ccix_tlp_hdr.

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CCIX TLP Header Fields and ccix_tlp_hdr Mapping PCI Express SW Controller Databook

Table 4-80 Mapping Between CCIX TLP Header Fields and ccix_tlp_hdr

CCIX TLP Field

PCIe Compatible TLP Format Optimized CCIX TLP Format ccix_tlp_hdr bits

TLP DW3 96 - 127

Vendor ID 95 - 80

Device Number 79 - 75

Function Number 74 - 72
NOT USED
Bus Number 71 - 64

Message Code 63 - 56

TAG 55 - 48

Requester ID 47 - 32

CCIX DW0 Content 31


Length[7:0]
Length[6:0] 30 - 24

TD 23

EP 22

Attr 21 -20

AT CCIX DW0 Content 19 -18

Length[9] 17

Length[8] 16

R 15

TC TC 14 - 12

R 11

Attr[2] 10
CCIX DW0 Content
R 9

TH 8

0 7

FMT Type 6

5
CCIX DW0 Content
Type 4-0

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PCI Express SW Controller Databook Receive Bypass Interface (RBYP)

4.3 Receive Bypass Interface (RBYP)


The RBYP interface is used for any queue that you have configured in bypass mode. For more information,
see “Receive Queues” on page 74.

4.3.1 Bypass Interface Protocol Rules


The bypass interface protocol rules are:
■ radm_bypass_hv indicates the cycle when the header information of the TLP is valid.
■ radm_bypass_dv indicates the cycles when the payload data is valid.
■ A transfer begins with the assertion of radm_bypass_hv and ends with the assertion of radm_by-
pass_eot.
■ radm_bypass_hv and radm_bypass_dv can both be asserted in the same cycle.
■ radm_bypass_tlp_abort and radm_bypass_dllp_abort are asserted only when radm_by-
pass_eot is asserted, and when the queue mode is not store-and-forward.
Header Reserved Fields
Access to the TLP headers reserved fields is through the signals described in “Peer-to-Peer Signals” section in
the “Signal Descriptions” chapter.

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Receive Request Interface (TRGT1) PCI Express SW Controller Databook

4.4 Receive Request Interface (TRGT1)


The controller uses TRGT1 to pass incoming TLPs to your application after they have been filtered. For
more information, see “Receive Queues” on page 74.

In the timing diagrams, the actual clock used to clock the interface might vary in low-power
Attention mode. In this case, you should use a different clock than the one indicated in the timing
diagram. For more information, see “Synchronous To Attribute” on page 55.

4.4.1 TRGT1 Protocol Rules


■ All header information is valid in the cycle when radm_trgt1_hv is asserted.
■ In cut-through queue mode, the controller might intermittently de-assert the radm_trgt1_dv output.
In store-and-forward queue mode, the controller de-asserts radm_trgt1_dv only when the TLP data
transfer is complete.
■ The controller uses the radm_cpl_trgt1_abort and radm_trgt1_dllp_abort outputs in bypass
and cut-through modes only. For more information, see Advanced Information: Advanced Error
Handling for Received TLPs.
Access to the TLP headers reserved fields is through the signals described in “Peer-to-Peer Signals” section in
the “Signal Descriptions” chapter.

4.4.2 TRGT1 Protocol Transactions


■ Figure 4-101 shows an example TRGT1 transaction in cut-through queue mode where the controller
might intermittently de-assert the radm_trgt1_dv output. Your application should be able to absorb
the gaps.
■ Figure 4-102 shows an example when a memory write (MWr) TLP from upstream is received at the
TRGT1 interface. The assertion of radm_trgt1_ecrc_err indicates that the MWr TLP has a bad
ECRC; the assertion of radm_trgt1_abort indicates that the MWr TLP is malformed.
■ Figure 4-103 shows an example TRGT1 transaction in which your application inserts wait states by
asserting trgt1_radm_halt. The controller begins a transaction by asserting radm_trgt1_hv and
radm_trgt1_dv along with valid data and header on radm_trgt1_data and the header outputs,
then holds all TRGT1 outputs at their current values until your application de-asserts trgt1_rad-
m_halt. After sampling trgt1_radm_halt de-asserted, the controller continues the 5-DWORD
transaction to completion.

Figure 4-101 TRGT1 TLP with Gaps (Cut-Through Mode Only)

core_clk

radm_trgt1_hv

radm_trgt1_dv

radm_trgt1_data[ ] W0 W1 W2 W3 W4 W5

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PCI Express SW Controller Databook TRGT1 Packet Grant and Halt

Figure 4-102 TRGT1 Transaction: MWr Request TLP


core_clk

radm_trgt1_hv

radm_trgt1_dv

radm_trgt1_eot

radm_trgt1_ecrc_err

radm_trgt1_tlp_abort

radm_trgt1_data[ ] W0 W1 W2 W3 W4 W5 W6

radm_trgt1_* Header
(TLP header signals) signals

radm_trgt1_dwen[3:0] 0xF

Figure 4-103 TRGT1 Transaction: MWr Request TLP with Wait States

core_clk

radm_trgt 1_hv

radm_trgt 1_dv

radm _trgt1_eot

trgt1_radm _halt

radm_trgt 1_data[ ] W0 W1 W2 W3 W4

radm_trgt 1_*
Header signals
(TLP header signals )

radm_trgt1_dwen[3:0] 0xF

4.4.3 TRGT1 Packet Grant and Halt


In Figure 4-104, note that the ordering controller operates between the receive queues and the output pipe.
If a packet enters the output pipe and becomes blocked by the global TRGT1 halt signal trgt1_radm_halt
or by a too-late assertion of trgt1_radm_pkt_halt[2:0], it blocks the delivery of all other packets and
lead to a potential deadlock scenario when a non-posted TLP blocks a posted TLP.
To avoid this you must design a “Non-Posted TLP Tracker” and use the packet halt inputs
(trgt1_radm_pkt_halt[2:0]) to notify the controller in advance that your application cannot accept any
more of a particular packet type. This causes the order controller (in Figure 4-104) to block that particular

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TRGT1 Packet Grant and Halt PCI Express SW Controller Databook

packet type in the receive queue and not unload it into the output pipe. You must implement a
counter/tracker in your application logic for each TLP type using the radm_grant_tlp_type[2:0]
outputs. For example, design a counter that increments on radm_grant_tlp_type[2:0]. When
radm_trgt1_hv of the correct type of transaction is asserted, decrement the counter. When this counter
reaches the number of free TLP locations in your applications buffer, assert trgt1_radm_pkt_halt.

Figure 4-104 Receive Queue and Output Queue Halting (Single-VC Design)
optional RBYP

Receive Queues
CPL
F I F O Output Pipe
(3-4 cycles )
P
F I F O TRGT1

NP trgt1_radm_halt
F I F O (global interface halt )

trgt1_radm_pkt_halt[2:0]
Order FIFO Order Controller Packet Halt/Unload
(controls the unloading 0: P Tracker/Counter Per-
of each receive queue 1: NP TLP-Type and Per-Vc
based on ordering 2: CPL (Implemented in your
rules) application logic)
radm_grant _tlp_type[2:0]

The radm_grant_tlp_type[2:0] signals are pulse outputs indicating that a transaction has been granted
to dequeue from the receive queue. The level input signal trgt1_radm_pkt_halt[2:0] acts like a flow
control On/Off. It alone does not control the exact number of transactions that the controller delivers,
because of the pipelines inside the output pipe. The signal radm_grant_tlp_type[2:0] is a clocked
output. Therefore you must combinatorially assert the signaltrgt1_radm_pkt_halt[2:0] to stop extra
transactions from being dequeued from the receive-queue. There is a minimum delay of one clock cycle
from the de-assertion of trgt1_radm_pkt_halt[2:0] to the assertion of radm_grant_tlp_type[2:0].

Figure 4-105 Grant/Halt Unloading Example

core_clk

trgt1_radm_pkt_halt[0]

radm_grant_tlp_type[0] 1 2 3 4

When you have used all the entries in the Target LUT, the RADM automatically halts the TRGT1 interface.

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PCI Express SW Controller Databook CCIX Receive Request Interface (TRGT1_CCIX)

4.5 CCIX Receive Request Interface (TRGT1_CCIX)


The CCIX specification relies on the use of a dedicated high priority Virtual Channel (VC) to transfer data
between devices. A dedicated TRGT1_CCIX interface to pass incoming CCIX TLPs to your application
provides the following advantages:
■ Minimizes the latency of CCIX traffic on the receive path
■ Provides CCIX support without affecting the standard PCIe functionality
■ Minimizes collision between standard PCIe traffic and CCIX traffic
TRGT1_CCIX interface implements a simple handshake mechanism between the controller and your
application.

4.5.1 CCIX TRGT1 Protocol Transactions


The following diagrams illustrate example transactions on the CCIX receive client interface:
■ Figure 4-106 depicts an example of generic operation of TRGT1_CCIX interface when CCIX TLPs in
PCIe compatible TLP format are received at TRGT1_CCIX interface.
■ Figure 4-107 depicts an example of generic operation of TRGT1_CCIX interface when CCIX TLPs in
optimized CCIX TLP format are received at TRGT1_CCIX interface.
■ Figure 4-108 depicts an example scenario for a 128-bit controller when the amount of data received in
one clock cycle is not enough to fill the complete radm_ccix_data bus.
In the timing diagrams, hdri (where i is 1,2,3 and so on) represents the header for different TLPs, data1
represents the first data cycle, data2 represents the second data cycle, and so on.

Figure 4-106 CCIX_TRGT1 PCIe Compatible TLP Format1


                 

CORE?CLK

RADM?CCIX?HV

RADM?CCIX?HDR;= HDR HDR HDR HDR HDR HDR HDR

RADM?CCIX?DV

RADM?CCIX?DATA;$7 = DATA DATA DATA DATA DATA DATA DATA DATA DATA

RADM?CCIX?DWEN;.7 = [.[gBg]] [.7[gBg]] [.[gBg]] [.[gBg]] [.7[gBg]] [.[gBg]] [.[gBg]] [.[gBg]] [.[gBg]]

RADM?CCIX?EOT

RADM?CCIX?TLP?ABORT

RADM?CCIX?DLLP?ABORT

CFG?CCIX?OPT?TLP?EN

CCIX?RADM?HALT

1. For radm_ccix_dwen, 1 <= N <= NW.

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CCIX TLP Header Fields and radm_ccix_hdr Mapping PCI Express SW Controller Databook

Figure 4-107 CCIX_TRGT1 Optimized CCIX TLP Format1


                 

CORE?CLK

RADM?CCIX?HV

RADM?CCIX?HDR;= 2ESERVED?NOT?USED?FOR?OPTIMIZED?4,0?FORMAT

RADM?CCIX?HDR;= HDR HDR HDR HDR HDR HDR HDR

RADM?CCIX?DV

RADM?CCIX?DATA;$7 = DATA DATA DATA DATA DATA DATA DATA DATA DATA

RADM?CCIX?DWEN;.7 = [.[gBg]] [.7[gBg]] [.[gBg]] [.[gBg]] [.7[gBg]] [.[gBg]] [.[gBg]] [.[gBg]] [.[gBg]]

RADM?CCIX?EOT

RADM?CCIX?TLP?ABORT

RADM?CCIX?DLLP?ABORT

CFG?CCIX?OPT?TLP?EN

CCIX?RADM?HALT

Figure 4-108 CCIX_TRGT1 Data bus Usage Example for 128-bit Datapath
            

CORE?CLK

RADM?CCIX?DV

RADM?CCIX?DATA;= $7 $7 $7

RADM?CCIX?DATA;= $7 $7 $7 $7

RADM?CCIX?DATA;= $7 $7 $7 $7 $7

RADM?CCIX?DATA;= $7 $7 $7 $7 $7

RADM?CCIX?DWEN;= H H& H H& H&

RADM?CCIX?EOT

CCIX?RADM?HALT

Clock cycle one and clock cycle five in Figure 4-108 illustrate how the radm_ccix_data bus is expected to
be used when the amount of data received in one clock cycle is not enough to fill the complete
radm_ccix_data bus. For both PCIe compatible TLP format and optimized CCIX TLP format the same
behavior applies.

4.5.2 CCIX TLP Header Fields and radm_ccix_hdr Mapping


Table 4-81 illustrates the mapping between CCIX TLP header fields and the bits in the reveive CCIX
interface header radm_ccix_hdr.

1. For radm_ccix_dwen, 1 <=N <=NW.

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PCI Express SW Controller Databook CCIX TLP Header Fields and radm_ccix_hdr Mapping

Table 4-81 Mapping Between CCIX TLP Header Fields and radm_ccix_hdr

CCIX TLP Field

PCIe Compatible TLP Format Optimized CCIX TLP Format radm_ccix_hdr bits

TLP DW3 96 - 127

Vendor ID 95 - 80

Device Number 79 - 75

Function Number 74 - 72
NOT USED
Bus Number 71 - 64

Message Code 63 - 56

TAG 55 - 48

Requester ID 47 - 32

CCIX DW0 Content 31


Length[7:0]
Length[6:0] 30 - 24

TD 23

EP 22

Attr 21 -20

AT CCIX DW0 Content 19 -18

Length[9] 17

Length[8] 16

R 15

TC TC 14 - 12

R 11

Attr[2] 10
CCIX DW0 Content
R 9

TH 8

0 7

FMT Type 6

5
CCIX DW0 Content
Type 4-0

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Data Bus Interface (DBI) PCI Express SW Controller Databook

4.6 Data Bus Interface (DBI)

In the timing diagrams, the actual clock used to clock the interface might vary in low-power
Attention mode. In this case, you should use a different clock than the one indicated in the timing
diagram. For more information, see “Synchronous To Attribute” on page 55.

For more information, see “Data Bus Interface (DBI) Access” on page 111. Limitations are detailed in
“Access Limitations” on page 113.

4.6.1 DBI Protocol Rules


The DBI protocol rules are similar to the ELBI protocol rules:
■ Assertion of dbi_cs indicates an active CPU cycle.
■ The dbi_wr input indicates the byte enables of a write access. All bits zero indicates a read access.
■ The dbi_cs and lbc_dbi_ack signals form a synchronous handshake. The signal dbi_cs must
remain asserted until the controller asserts lbc_dbi_ack.
■ The controller asserts lbc_dbi_ack for two clock cycles.
■ When dbi_addr[0] =0, the access is to an internal configuration register in the CDM.
■ When dbi_addr[0] =1, the access is to an external register on the ELBI.
■ The DBI includes a second chip select signal (dbi_cs2) to access shadow and iATU configuration
registers. For more information, see “Register Types” on page 102.

4.6.2 DBI Protocol Transactions


The following diagrams illustrate example transactions on the DBI:
■ Figure 4-109 depicts an example of a CPU performing write accesses to internal configuration space
registers through the DBI.
■ Figure 4-110 depicts an example of a CPU performing read accesses to configuration space registers
through the DBI.

Figure 4-109 DBI Transaction: Register Write

core_clk

dbi_cs

lbc_dbi_ack

dbi_addr [31:0] Addr 0 Addr 1

dbi_din[31:0] DW 0 DW 1

dbi_wr[3:0] 0xF 0x0 0xF

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PCI Express SW Controller Databook DBI Protocol Transactions

Figure 4-110 DBI Transaction: Register Read

core_clk

dbi_cs

lbc_dbi_ack

dbi_addr [31:0] Addr 1 Addr 2

lbc_dbi_out[31:0] Valid Data 1

dbi_wr[3:0] 0x0

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External Local Bus Interface (ELBI) PCI Express SW Controller Databook

4.7 External Local Bus Interface (ELBI)


For more information, see “Register Module, LBC, and DBI” on page 99. Limitations are detailed at “Access
Limitations” on page 113.

4.7.1 ELBI Protocol Rules


■ Assertion of lbc_ext_cs indicates an active request cycle.
■ The lbc_ext_wr output indicates the byte enable of a write access. For a read access, the controller
de-asserts all bits of this signal.
■ Refer to the ELBI Access Restrictions in“Access Limitations” on page 113.
■ It is expected that your application only decodes the valid address bits to the BAR limit specified.
■ The lbc_ext_dout output is only valid when lbc_ext_cs is asserted.
■ The lbc_ext_cs and ext_lbc_ack signals form a synchronous handshake. The controller keeps
lbc_ext_cs asserted until your application asserts ext_lbc_ack. The wait time between
lbc_ext_cs and ext_lbc_ack is unlimited.
❑ Your application must return an ack, otherwise, the transaction hangs. It is suggested that your
application designs an error access detection circuit. When mis-access is encountered, return an
ack with null data.
❑ The ext_lbc_ack signal should never be hardwired to 1b1, even if the ELBI is not being used. It
should only be high when lbc_ext_cs is 1b1. That is, it should be inactive when lbc_ext_cs is
inactive.
❑ Your application must assert ext_lbc_ack for two clock cycles, except for an error response
(accessing a non-existent register or writing to a read-only register), when ext_lbc_ack must be
asserted for one clock cycle.
■ The controller sets the lbc_ext_bar_num output to 3'b111 for all DBI accesses.

4.7.2 ELBI Protocol Transactions


The following diagrams illustrate example transactions on the ELBI:
■ Figure 4-111 depicts an example of the LBC performing a 32-bit write access to an external application
register through the ELBI.
■ Figure 4-112 depicts an example of the LBC performing a 32-bit read access to an external application
register through the ELBI.

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PCI Express SW Controller Databook ELBI Protocol Transactions

Figure 4-111 ELBI Transaction: 32-bit Write Access to External Registers

core_clk

lbc_ext_cs

ext_lbc_ack

lbc_ext_addr [15:0] Addr 0 Addr 1

lbc_ext_dout [31:0] DW 0 DW 1

lbc_ext_wr[3:0] 0xF 0x0 0xF

lbc_ext_rom_access/
lbc_ext_io_access

Figure 4-112 ELBI Transaction: 32-bit Read Access to External Registers

core_clk

lbc_ext_cs

ext_lbc_ ack

lbc_ext_ addr[ 31:0] Addr 1 Addr 2

ext_lbc_din[ 31:0] Valid Data1

lbc_ext_ wr[3:0] 0x0

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Message Signaled Interrupt (MSI) Interface PCI Express SW Controller Databook

4.8 Message Signaled Interrupt (MSI) Interface


The MSI interface enables your application to request the controller to send an MSI. The MSI interface is
only used for upstream ports.

4.8.1 MSI Protocol Rules


■ The MSI interface protocol is a simple synchronous request/acknowledge handshake.
■ When you assert the ven_msi_req input, it must remain asserted until the controller asserts ven_m-
si_grant.
■ The MSI is requested by your application logic through the MSI interface. The controller then gener-
ates the corresponding memory write.
■ The following MSI interface signals are also used for the “MSI-X Protocol Transactions” on page 301:
ven_msi_req, ven_msi_func_num, ven_msi_tc, andven_msi_grant.
■ The controller supports PVM (Per Vector Masking). For more information, see “Interrupts” on page
170 and “Relationship Between Configuration Parameters, Registers, and I/O for MSI-X and MSI” on
page 301.

4.8.2 MSI Protocol Transactions


■ Figure 4-113 depicts an example of your application client requesting the controller to send an MSI
message upstream when cfg_msi_en is asserted. ven_msi_req stays asserted until the controller
asserts ven_msi_grant.

Figure 4-113 MSI Message Request

core_clk

ven_msi_req

ven_msi_grant

ven_msi_vector[4:0] valid vector

ven_msi_tc[2:0] 3'b000

cfg_msi_en

cfg_msix_en

The internal MSI arbiter performs arbitration for MSI requests from different functions. ven_msi_grant is
a one-cycle pulse acknowledging ven_msi_req. ven_msi_req is not required to be de-asserted before
reasserting again. When ven_msi_req remains asserted, the controller generates another MSI.

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PCI Express SW Controller Databook MSI-X Interface

4.9 MSI-X Interface


The MSI-X interface enables your application to request the controller to send an MSI-X message. The MSI-X
interface is only used for upstream ports.

4.9.1 MSI-X Protocol Rules


■ When MSI-X is enabled, the following MSI interface signals are used for MSI-X: ven_msi_req,
ven_msi_func_num, ven_msi_tc, and ven_msi_grant.
■ To request the controller to send an MSI-X message, your application uses the signals listed previously
in the same manner as when sending an MSI.
■ In addition, your application must supply the MSI-X address and data, on msix_addr and msix_-
data, respectively.
■ Host system software stores the MSI-X address and data values in the MSI-X tables located in appli-
cation memory space during system initialization.

4.9.2 MSI-X Protocol Transactions


■ Figure 4-113 depicts an example of your application requesting the controller to send an MSI-X
Message upstream when cfg_msix_en is asserted. ven_msi_req stays asserted until the controller
asserts ven_msi_grant.

Figure 4-114 MSI-X Message Request

core_clk

ven_msi_req

ven_msi_grant

msix_addr[63:0] valid address

msix_data[31:0] valid data

ven_msi_tc[2:0] 3'b000

cfg_msix_en

cfg_msi_en

As with MSI, the internal arbiter performs arbitration for MSI-X requests from different functions.
ven_msi_grant is a one-cycle pulse, after which the controller does not wait for ven_msi_req to be
de-asserted. When ven_msi_req remains asserted, the controller generates another MSI-X.

4.9.3 Relationship Between Configuration Parameters, Registers, and I/O for MSI-X and MSI
Figure 4-115 and Figure 4-116 show the configuration parameters that the controller uses to set the default
values of the MSI-X and MSI Capability Registers. Figure 4-115 and Figure 4-118 show which configuration
parameters are used to set the default of the MSI-X and MSI Capability Registers. They also show how the
controller makes the contents of the Capability Registers available on I/O signals. The contents of the

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Relationship Between Configuration Parameters, Registers, and I/O for MSI-X and MSI PCI Express SW Controller Databook

Read-Only (RO) fields of the VF MSI-X Capability registers are not available as I/O, because the values of
these registers are the same for all VFs, and these values are set using configuration parameters. There is one
exception, which is the Table Size field of the Control Register.

Figure 4-115 MSI-X Signals, Registers, and Configuration Parameters


VF Configuration Parameters
One set of values
for all VFs.

PF Configuration Parameters

*1
* NF
A set of values
for EACH PF.

PF MSI-X Capability Structure VF MSI-X Capability Structure


Control C ontrol
Table Offset BIR Table Offs et BIR
PBA Offset BIR PBA Offset BIR

* NF * NVF

PF Capability Register I/O MSI-X Generation I/O (PF and VF) VF Capability Register I/O

The contents of most of the VF MSI-X Capability


registers are not available as I/O because they
are RO, and wil l never change. Their values are
given by the VF MSI-X configuration parameters.

These I/O (excl. msix_data/addr) are also used for MSI

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PCI Express SW Controller Databook Relationship Between Configuration Parameters, Registers, and I/O for MSI-X and

Figure 4-116 MSI Signals, Registers, and Configuration Parameters


Configuration Parameters

*1

One set of values for all PFs and VFs.

PF MSI Capability Structure VF MSI Capability Structure


Message Control Message Control
Lower Address Lower Address
Upper Address Upper Address
Data Data
Mask Bits Mask Bits
Pending Bits Pending Bits

* NF * NVF

PF Capability Register /IO MSI Generation I/O (PF and VF) VF Capability Register /IO
These I/O are also used for MSI-X

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Figure 4-117 MSI-X Signals, Registers, and Configuration Parameters


Configuration Parameters

MSI-X Capability Structure


Control
Table Offset BIR
PBA Offset BIR

PF Capability Register /IO MSI-X Generation I/O

Figure 4-118 MSI Signals, Registers, and Configuration Parameters


Configuration Parameters

MSI Capability Structure


Message Control
Lower Address
Upper Address
Data
Mask Bits
Pending Bits

Capability Register /IO MSI Generation I/O

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PCI Express SW Controller Databook Vendor Message Interface (VMI)

4.10 Vendor Message Interface (VMI)


The VMI is an interface for sending vendor-defined messages. The VMI protocol is a simple synchronous
request/acknowledge handshake. The VMI can only be used to send a header-only (no payload)
vendor-defined message (Msg). MsgD is not supported. To send a vendor-defined MsgD, you must use one
of the transmit client interfaces XALI0/1/2

In the timing diagrams, the actual clock used to clock the interface might vary in low-power
Attention mode. In this case, you should use a different clock than the one indicated in the timing
diagram. For more information, see “Synchronous To Attribute” on page 55.

4.10.1 VMI Protocol Rules


■ The ven_msg_req pin must be tied to 0 if the VMI is not used. For more information, see “Message
Generation” on page 153.
■ When ven_msg_req is asserted, it must remain asserted until the controller asserts ven_msg_grant.
■ The time between ven_msg_req and ven_msg_grant is undefined.
■ Your application must de-assert ven_msg_req on the next clock cycle after sampling ven_msg_grant
high.

4.10.2 VMI Protocol Transactions


■ Figure 4-119 depicts an example where your application client requests the controller to send a
vendor-defined message upstream. The ven_msg_req signal stays asserted until the controller asserts
ven_msg_grant.

Figure 4-119 Vendor Message Request

core_clk

ven_msg_req

ven_msg_grant

ven_msg_* (header) valid header info

ven_msg_data[63:0] valid data

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System Information Interface (SII) PCI Express SW Controller Databook

4.11 System Information Interface (SII)


The SII exchanges various system-related information between the controller and your application. Most of
the SII signals are provided for flexibility. Your application is not required to use all of the SII signals. Your
application logic is expected to drive and monitor the signals that it needs to function correctly. SII inputs
that your application does not require, must be driven to 0.

4.11.1 SII: Global Controller Control

Figure 4-120 Determination of Device Type Using device_type[3:0]


core_rst_n

0 S/R
1
SW_up <-> 1
device_type[3:0]
SW_down To Configuration
Registers and
Core Logic
smlh_crosslink _active

CX_CROSSLINK_ENABLE

Note A change in device_type[3:0] must be associated with a full reset.

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PCI Express SW Controller Databook PIPE Interface

4.12 PIPE Interface


The PHY is instantiated outside of the controller, and there is an external PIPE interface for connection to
the external PHY. For more information, see the Integrating the controller with the PHY section in the User
Guide. In the multi-lane case, the per-lane signals are concatenated to form a bus, with the low-order bits
corresponding to lane0. The PIPE is compliant with the PIPE Specification for PCI Express, Version 4.4.1.

The controller does not use the following PIPE signals:


Note
■ PHY Mode[1:0] output. You must externally drive the corresponding PHY input with the
value 00.
■ DataBusWidth[1:0] input.
■ Max PCLK input.

In addition to the PIPE-compliant interface signals, the controller provides two 32-bit sideband buses
(cfg_phy_control and phy_cfg_status) that connect to controller configuration registers. You can
optionally use the sideband buses for additional PHY control and/or status monitoring.
When the automatically derived CX_FREQ_STEP_DOWN_EN parameter is ‘1’, then a module called
freq_step (workspace/src/common/freq_step.v) is placed between the PHYs PIPE and the cores
PIPE. This module steps up/down the signals to/from the PIPE interface. For more information, see
“Frequency Step Module (CX_FREQ_STEP_EN =1)” on page 38.

4.12.1 64-bit PIPE


The controller supports 64-bit PIPE. This section describes the 64-bit PIPE transmit and receive operation.

4.12.1.1 64-bit PIPE Transmit Operation

Figure 4-121 describes the 64-bit PIPE transmit operation.


■ De-assert txdatavalid for one cycle on every 32 blocks
■ Block length is always 128-bit aligned

Figure 4-121 64-bit PIPE Transmit Operation

clk

mac_phy_txelecidle

mac_phy_txdatavalid
32 blocks
mac_phy_txstartblock

mac_phy_txsyncheader[1:0] V V V V V V

mac_phy_txdata[63:32] 1 3 1 3 1 3 1 3 1 3 1 3
mac_phy_txdata[31:0] 0 2 0 2 0 2 0 2 0 2 0 2

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4.12.1.2 64-bit PIPE Receive Operation (CX_PIPERX_MULTI_BLOCK =0)

Figure 4-122 describes the 64-bit PIPE transmit operation when CX_PIPERX_MULTI_BLOCK =0.
■ The controller only accepts 64-bit-aligned SKP OS
■ rxdatavalid can be de-asserted at anytime
■ Possible SKP OS length: 64/128/192 bit

Figure 4-122 64-bit PIPE Receive Operation (CX_PIPERX_MULTI_BLOCK =0)


clk

phy_mac_rxvalid

phy_mac_rxdatavalid

phy_mac_rxstartblock 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0

phy_mac_rxsyncheader[1:0] V V V V V V V V V V V V

phy_mac_rxdata[63:32] 1 3 1 3 END 1 3 1 3 SKP END 1 3 1 3 SKP SKP END 1 3 1 3 EIOS EIOS

phy_mac_rxdata[31:0] 0 2 0 2 SKP 0 2 0 2 SKP SKP 0 2 0 2 SKP SKP SKP 0 2 0 2 EIOS EIOS

phy_mac_rxstatus[2:0] 0 DEL 0 0 ADD 0 0

4.12.1.3 64-Bit PIPE Receive Operation (CX_PIPERX_MULTI_BLOCK =1)

Figure 4-122 describes the 64-bit PIPE transmit operation when CX_PIPERX_MULTI_BLOCK =1.
■ Extend bit width of rxstartblock and rxsyncheader
❑ phy_mac_rxstartblock 2-bit (per-lane)
❑ phy_mac_rxsyncheader 4-bit (per-lane)
■ rxdatavalid can be de-asserted at anytime
■ Possible SKP OS length: 32/64/96/128/160/192/224 bit

Figure 4-123 64-bit PIPE Receive Operation (CX_PIPERX_MULTI_BLOCK =1)


clk

phy_mac_rxvalid

phy_mac_rxdatavalid

phy_mac_rxstartblock[1] 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0
phy_mac_rxstartblock[0] 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0

phy_mac_rxsyncheader[3:2] V V V V V V
phy_mac_rxsyncheader[1:0] V V V V V V

phy_mac_rxdata[63:32] 1 3 1 3 SKP 0 2 0 2 SKP SKP SKP END 1 3 1 3 0 2 0 2 EIOS EIOS

phy_mac_rxdata[31:0] 0 2 0 2 SKP END 1 3 1 3 SKP SKP SKP 0 2 0 2 END 1 3 1 3 EIOS EIOS

phy_mac_rxstatus[2:0] 0 DEL 0 0 ADD 0 DEL 0

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PCI Express SW Controller Databook PIPE 5.1.1

4.12.2 PIPE 5.1.1


The controller implements Low Pin Count Interface (CX_PIPE_VER =PIPE 5.1.1) of the PIPE Specification
for PCI Express, Version 5.1.1 with the following features and limitations:
Features
■ Obsolete Legacy Pin Interface signals are removed.
■ The controller implements PHY/MAC Message Bus registers.
■ The controller supports Gen1, Gen2, Gen3, Gen4, and Gen5 speed.
Limitations
■ The following PHY Message Bus registers are not supported:
❑ Elastic Buffer Control (2h)/Elastic Buffer Depth Control
❑ PHY RX Control4 (8h)/ElasticBufferResetControl
■ The following MAC Message Bus registers are not supported:
❑ Elastic Buffer Status (3h)/Elastic Buffer Status
❑ Elastic Buffer Location (4h)/ElasticBufferLocation
The controller does not issue any Message Bus command to the unsupported PHY registers. Likewise, any
Message Bus commands to the unsupported MAC registers does not affect to the behavior of the controller.

SerDes architecture and PCLK as PHY input features of the PIPE Specification for PCI
Note
Express, Version 5.1.1 are not supported in this release.

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PHY Register Bus Interface (PRBI) PCI Express SW Controller Databook

4.13 PHY Register Bus Interface (PRBI)


PHY Register Bus Interface (CX_PHY_VIEWPORT_ENABLE =1) is an optional interface between the controller
and Synopsys PHYs which communicate with the PHY’s Control Register (CR) Parallel Interface. It
facilitates in direct access of PHY control registers through DBI or CFG requests to the controller. PRBI is a
synchronous (maximum frequency 100MHz), 16-bit data/address parallel interface that follows a simple
synchronous request/acknowledge handshake protocol. The interface also implements timeouts to avoid
deadlocks.
The PHY_VIEWPORT_CTLSTS_OFF port logic register, controls the access of PHY through CFG or DBI
requests. For more information, see “PHY Port Logic Registers” on page 114. For more information on cold
reset sequence with PHY initialization see Figure 2-17. For more information on PHY initialization after cold
reset, see Figure 2-18.

■ The PHY can be controlled through PRBI only when PHY’s Control Register (CR) Parallel
Note Interface Select signal (cr_para_sel) is set to 1.
■ This feature does not work during L1.CPM and L1 substate, if CX_PHY_ENHANCED_PM_EN
=1.
■ This feature does not work during L2.

The controller's PHY Viewport (PRBI) to PHY registers can have high access latency. If your
Attention application needs low latency to initialize Synopsys PHY registers or SRAM, then PRBI should
not be used. Instead, you should design a direct interface to the PHY's SRAM or CR Bus.
PRBI is recommended only for PHY debug.

4.13.1 PRBI Protocol Transactions


■ Figure 4-124 depicts an example of the controller performing a write operation on a PHY containing
a single sub-block.
■ Figure 4-125 depicts an example of the controller performing a read operation on a PHY containing a
single sub-block.
■ Figure 4-126 depicts an example of the controller performing a write operation on PHY0 sub-block of
a PHY containing four sub-blocks.
■ Figure 4-127 depicts an example of the controller performing a read operation on PHY0 sub-block of
a PHY containing four sub-blocks.
■ Figure 4-128 depicts an example of the controller performing a write operation on all the sub-blocks
of a PHY containing a four sub-blocks.

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PCI Express SW Controller Databook PRBI Protocol Transactions

Figure 4-124 Write Operation: PHY Containing Single PHY Sub-block


Tcr

phy_reg_clk_g

phy_cr_para_addr [15:0] valid valid

phy_cr_para_wr_data [15:0] valid valid

phy_cr_para_ack

phy_cr_para_wr_en

>= 1*Tcr

Maximum (6+2N)*Tref

CREG Write Cycle

Tcr : Time period of phy_reg_clk_g clock with minimum vale of 10 ns


Tref : Buffered version of input reference clock for the PHY in use with minimum value of 10ns
N : Number of Lanes (for example, N=4 for 4-lane PHY)

phy_cr_para_wr_en is asserted for a single cycle. When asserted, the data on


phy_cr_para_wr_data[15:0] is written to the address on phy_cr_para_addr[15:0]. Assertion of
phy_cr_para_ack indicates completion write access.

Figure 4-125 Read Operation: PHY Containing Single PHY Sub-block


Tcr

phy_reg_clk_g

phy_cr_para_addr [15:0] valid

phy_cr_para_ack

phy_cr_para_rd_en

phy_cr_para_rd_data [15:0] valid

>= 1*Tcr
Maximum (6+2N)*Tref + 5*Tcr

CREG Read Cycle

Tcr : Time period of phy_reg_clk_g clock with minimum vale of 10 ns


Tref : Buffered version of input reference clock for the PHY in use with minimum value of 10ns
N : Number of Lanes (for example, N=4 for 4-lane PHY)

phy_cr_para_rd_en is asserted for a single cycle. When asserted, the data at address
phy_cr_para_addr[15:0] is read and provided on phy_cr_para_rd_data[15:0]. Assertion of
phy_cr_para_ack indicates completion of read access.

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PRBI Protocol Transactions PCI Express SW Controller Databook

Figure 4-126 Write Operation: PHY0 Sub-block of a PHY Containing 4 Sub-blocks


Tcr

phy_reg_clk_g

phy_cr_para_addr[15:0] valid

phy_cr_para_wr_data[15:0] valid

phy_cr_para_ack[3:0] 0000b 0001b 0000b

phy_cr_para_wr_en[3:0] 0000b 0001b 0000b

>=1*Tcr

Maximum (6+2N)*Tref

Tcr : Time period of phy_reg_clk_g clock with minimum vale of 10 ns


Tref : Buffered version of input reference clock for the PHY in use with minimum value of 10ns
N : Number of Lanes (for example, N=4 for 4-lane PHY)

phy_cr_para_wr_en[3:0] is asserted for a single cycle. The value 0001b indicates write access to PHY0
sub-block of the PHY. The controller waits for response from PHY0 sub-block.

Figure 4-127 Read Operation: PHY0 Sub-block of a PHY Containing 4 Sub-blocks


Tcr

phy_reg_clk_g

phy_cr_para _addr [15:0] valid

phy _cr_para_ack[3:0] 0000b 0001b 0000b

phy_cr_para _rd_en[3:0] 0000b 0001b 0000b

phy_cr_para _rd_data[16*4-1:16]

phy _cr_para_rd_data[15:0] valid

>=1*Tcr

Maximum (6+2N)*Tref + 5*Tcr

Tcr : Time period of phy_reg_clk_g clock with minimum vale of 10 ns


Tref : Buffered version of input reference clock for the PHY in use with minimum value of 10ns
N : Number of Lanes (for example, N=4 for 4-lane PHY)

phy_cr_para_rd_en[3:0] is asserted for a single cycle. The value 0001b indicates read access to PHY0
sub-block of the PHY. Data at address phy_cr_para_addr[15:0] is read and provided on
phy_cr_para_rd_data[15:0]. The controller waits for response from PHY0 sub-block.

Figure 4-128 Write Operation: Broadcast to all Sub-blocks of a PHY Containing 4 Sub-blocks
phy_reg_clk_g

phy_cr_para_wr_en[3:0] 0000b 1111b 0000b

phy_cr_para_ack[3:0] 0000b 1000b 0101b 0000b 0010b 0000b

Start timeout timer


Complete broadcast

phy_cr_para_wr_en[3:0] is asserted for a single cycle. Value 1111b indicates write access to all the four
sub-blocks of the PHY. The controller waits for response from all the four sub-blocks.

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PCI Express SW Controller Databook Signal Descriptions

5
Signal Descriptions

This chapter details all possible I/O signals in the controller. For configurable IP titles, your actual
configuration might not contain all of these signals.
Inputs are on the left of the signal diagrams; outputs are on the right.
Attention: For configurable IP titles, do not use this document to determine the exact I/O footprint of the
controller. It is for reference purposes only.
When you configure the controller in coreConsultant, you must access the I/O signals for your actual
configuration at workspace/report/IO.html or workspace/report/IO.xml after you have completed the
report creation activity. That report comes from the exact same source as this chapter but removes all the
I/O signals that are not in your actual configuration. This does not apply to non-configurable IP titles. In
addition, all parameter expressions are evaluated to actual values. Therefore, the widths might change
depending on your actual configuration.
Some expressions might refer to TCL functions or procedures (sometimes identified as <functionof>) that
coreConsultant uses to make calculations. The exact formula used by these TCL functions is not provided in
this chapter. However, when you configure the controller in coreConsultant, all TCL functions and
parameters are evaluated completely; and the resulting values are displayed where appropriate in the
coreConsultant GUI reports.
In addition to describing the function of each signal, the signal descriptions in this chapter include the
following information:
■ Active State: Indicates whether the signal is active high or active low. When a signal is not intended
to be used in a particular application, then this signal needs to be tied or driven to the inactive state
(opposite of the active state).
■ Registered: Indicates whether or not the signal is registered directly inside the IP boundary without
intervening logic (excluding simple buffers). A value of No does not imply that the signal is not
synchronous, only that there is some combinatorial logic between the signal's origin or destination
register and the boundary of the controller. A value of N/A indicates that this information is not
provided for this IP title.
■ Synchronous to: Indicates which clocks in the IP sample this input (drive for an output) when consid-
ering all possible configurations. A particular configuration might not have all of the clocks listed. This
clock might not be the same as the clock that your application logic should use to clock (sample/drive)
this pin. For more details, consult the clock section in the databook.
■ Exists: Name of configuration parameter that populates this signal in your configuration.

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■ Validated by: Assertion or de-assertion of signals that validates the signal being described.
Synchronous To
The Synchronous To: attribute indicates which controller clocks sample an input (or drive an output) when
considering all possible configurations. In many cases an output has components driven (or an input
sampled) by multiple clocks. The attribute lists all clocks which drive or sample for all possible
configurations. It is an automatically generated list accumulated over all configurations. Your particular
configuration might not have all of the clocks listed.
■ When there is only one clock in the list, this clock is normally but not always the same as the clock that
your application logic should use to clock (sample/drive) this pin.
■ When there is more than one clock in the list:
❑ A {} is placed around the clock which is used in generating the synthesis in/out timing delay
constraints and which is also used in Spyglass boundary CDC checking.
❑ In most cases, this is also the clock that you should use to drive/sample the pin in normal opera-
tional (non low-power) mode.
❑ If more than one clock has a {}, that clock is configuration-dependent and you should look in your
SDC file (as explained in the Synthesizing to a Device Outside of coreConsultantsection of the User
Guide) to see which one is relevant. Normally only applies to the PIPE outputs which are clocked
on pipe_clk or core_clk depending on CX_FREQ_STEP_EN.
■ When you see perbitclockin the clock list, it indicates that there is a different clock for some of the bits
in the multi-bit port, and/or that some of the bits in a multi-bit port falls into the various categories as
defined next by None.
■ When you see None_asin the clock list, it indicates the following and is equivalent/mapped to core_clk
for CDC synthesis.
❑ Asynchronous reset with synchronous de-assertion.
■ When you see Nonein the clock list, it indicates any of the following and is equivalent/mapped to
core_clk for CDC and synthesis.
❑ Direct or combinatorial feed-through.
❑ Gated-off (that is, unclocked) inputs.
❑ Unused inputs.
❑ Hard-coded outputs.
❑ Asynchronous outputs.
❑ Asynchronous resets.
■ For asynchronous inputs (excluding asynchronous resets), CDC synchronizers are added in the RTL,
and are detailed in Port Clocking and Input Synchonizersin the Databook. Asynchronous inputs are indi-
cated with Synchronous To: myclock, where myclock is the synchronizer clock.
■ Asynchronous outputs are indicated with Synchronous To: None.
For more information on Generalized interface clocking guidelines qualifying the synchronous to: attribute,
see 2.3.2 General Clock Relationshipsin Clock Requirementssection of the Databook.

The I/O signals are grouped as follows:


■ “Distributed Translation Interface AXI4-Stream Master Signals” on page 317

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PCI Express SW Controller Databook Signal Descriptions

■ “Distributed Translation Interface AXI4-Stream Slave Signals” on page 319


■ “Distributed Translation Interface Interrupt Signals” on page 321
■ “Distributed Translation Interface Invalidate Request Timeout Signals” on page 323
■ “CXS Rx Interface Signals” on page 324
■ “CXS Tx Interface Signals” on page 327
■ “XALI0 Interface Signals” on page 330
■ “XALI1 Interface Signals” on page 341
■ “XALI2 Interface Signals” on page 351
■ “XALI_CCIX Interface Signals” on page 361
■ “ADM adaptor Interface Signals” on page 363
■ “Bypass Interface Signals” on page 365
■ “RTRGT1 Interface Signals” on page 373
■ “TRGT1_CCIX Interface Signals” on page 386
■ “Clock and Reset (APM) Signals” on page 389
■ “Clock and Reset Signals” on page 394
■ “DBI Interface Signals” on page 403
■ “ELBI Interface Signals” on page 405
■ “CXS Rx FIFO RAM Signals” on page 409
■ “CXS Tx FIFO RAM Signals” on page 412
■ “Receive Data Queue RAM Signals” on page 415
■ “Receive Formation Queue RAM Signals” on page 420
■ “Receive Header Queue RAM Signals” on page 424
■ “Transmit Retry Buffer RAM Signals” on page 429
■ “Transmit Retry SOT Buffer RAM Signals” on page 433
■ “MSI Interface Signals” on page 435
■ “MSI-X Interface Signals” on page 439
■ “VMI Signals” on page 442
■ “Power Budgeting Signals” on page 445
■ “SII: AER Control Signals” on page 446
■ “SII: CCIX Configuration/Control/Status Signals” on page 447
■ “SII: Configuration Information Signals” on page 451
■ “SII: Debug Signals” on page 471
■ “SII: Diagnostic Control Signals” on page 476
■ “SII: Electromechanical Signals” on page 483
■ “SII: FRS/DRS Messaging Signals” on page 486
■ “SII: General Core Control Signals” on page 488
■ “SII: General Messaging Reception Signals” on page 494

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■ “SII: Interrupt Signals” on page 499


■ “SII: Link Reset/Status Signals” on page 511
■ “SII: LTR Message Generation Signals” on page 513
■ “SII: LTR Message Reception Signals” on page 515
■ “SII: Miscellaneous Signals” on page 516
■ “SII: OBFF Message Generation Signals” on page 517
■ “SII: OBFF Message Reception Signals” on page 518
■ “SII: PM, Unlock, and Error Messages Signals” on page 519
■ “SII: Power Management Signals” on page 522
■ “SII: Precision Time Management Signals” on page 536
■ “SII: RAS Data Protection Signals” on page 541
■ “SII: Receive Control/CPL Timeout Signals” on page 542
■ “SII: Transmit Control Signals” on page 545
■ “Common PIPE Signals” on page 556
■ “Gen2/3-Only PIPE Signals” on page 571
■ “Gen3-Only Equalization PIPE Signals” on page 575
■ “Gen3-Only Equalization V7 Signals” on page 581
■ “Gen3-Only PIPE Signals” on page 587
■ “Gen4-Only Margining Signals” on page 591
■ “Gen4-Only PIPE Signals” on page 592
■ “SerDes PIPE Signals” on page 593
■ “Crosslink Signals” on page 594
■ “Peer-to-Peer Signals” on page 595
■ “RAS D.E.S. Event Counter RAM Signals” on page 598
■ “RAS D.E.S. Event Counters Debug Signals” on page 600
■ “RAS D.E.S. Silicon Debug Internal Signals” on page 603
■ “RAS D.E.S. Time-Based Analysis Debug Signals” on page 609
■ “RAS D.E.S. Time-Based Analysis RAM Signals” on page 610
■ “Configuration Intercept Interface (CII) Signals” on page 612
■ “EXTSRIOV: PF Registers Value for VF Function Signals” on page 616
■ “PHY Register Bus Interface Signals” on page 617
■ “SII: ATS Capability Signals” on page 620
■ “SII: BDF Signals” on page 621
■ “SII: DPC Signals” on page 622
■ “SII: TLP Bypass Internal Error Reporting Signals” on page 627

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PCI Express SW Controller Databook Distributed Translation Interface AXI4-Stream Master Signals

5.1 Distributed Translation Interface AXI4-Stream Master Signals

tready_dti_up - - tvalid_dti_dn
- tdata_dti_dn
- tkeep_dti_dn
- tlast_dti_dn
- tprot_dti_dn

Table 5-1 Distributed Translation Interface AXI4-Stream Master Signals

Port Name I/O Description

tvalid_dti_dn O tvalid_dti_dn indicates that the master is driving a valid transfer. A


transfer takes place when both tvalid_dti_dn and tready_dti_up are
asserted.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

tready_dti_up I tready_dti_up indicates that the slave can accept a transfer in the
current cycle.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

tdata_dti_dn[(DTIM_DATA_WD-1):0] O tdata_dti_dn is the primary payload that is used to provide the data that
is passing across the interface. The width of the data payload is an
integer number of bytes.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: tvalid_dti_dn

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Port Name I/O Description

tkeep_dti_dn[(DTIM_NUM_BYTES_PER_ O tkeep_dti_dn is the byte qualifier that indicates whether the content of
BEAT-1):0] the associated byte of tdata_dti_dn is processed as part of the data
stream. Associated bytes that have the tkeep_dti_dn byte qualifier
deasserted are null bytes and can be removed from the data stream.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: tvalid_dti_dn

tlast_dti_dn O tlast_dti_dn indicates the boundary of a packet.


Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: tvalid_dti_dn

tprot_dti_dn[(DTIM_INTF_PROT_WD-1):0 O tprot_dti_dn contains the parity protection bits generated by the


] controller for the Distributed Translation Interface AXI4-Stream Master.
Your application must calculate the protection code from the following
ordered interface signals: tdata_dti_dn, tkeep_dti_dn, and tlast_dti_dn.
Exists: (CC_DTIM_ENABLE) && (((CX_RASDP==0)? 0: 1))
Synchronous To: mstr_aclk
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: tvalid_dti_dn

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PCI Express SW Controller Databook Distributed Translation Interface AXI4-Stream Slave Signals

5.2 Distributed Translation Interface AXI4-Stream Slave Signals

tvalid_dti_up - - tready_dti_dn
tdata_dti_up -
tkeep_dti_up -
tlast_dti_up -
tprot_dti_up -

Table 5-2 Distributed Translation Interface AXI4-Stream Slave Signals

Port Name I/O Description

tvalid_dti_up I tvalid_dti_up indicates that the master is driving a valid transfer. A


transfer takes place when both tvalid_dti_up and tready_dti_dn are
asserted.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

tready_dti_dn O tready_dti_dn indicates that the slave can accept a transfer in the
current cycle.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

tdata_dti_up[(DTIM_DATA_WD-1):0] I tdata_dti_up is the primary payload that is used to provide the data that
is passing across the interface. The width of the data payload is an
integer number of bytes.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: tvalid_dti_up

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Distributed Translation Interface AXI4-Stream Slave Signals PCI Express SW Controller Databook

Port Name I/O Description

tkeep_dti_up[(DTIM_NUM_BYTES_PER_ I tkeep_dti_up is the byte qualifier that indicates whether the content of
BEAT-1):0] the associated byte of tdata_dti_up is processed as part of the data
stream. Associated bytes that have the tkeep_dti_up byte qualifier
deasserted are null bytes and can be removed from the data stream.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: tvalid_dti_up

tlast_dti_up I tlast_dti_up indicates the boundary of a packet.


Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: tvalid_dti_up

tprot_dti_up[(DTIM_INTF_PROT_WD-1):0 I tprot_dti_up contains the parity protection bits generated by the


] application for the Distributed Translation Interface AXI4-Stream Slave.
Your application must generate the protection code from the following
ordered interface signals: tdata_dti_up, tkeep_dti_up, and tlast_dti_up.
Exists: (CC_DTIM_ENABLE) && (((CX_RASDP==0)? 0: 1))
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: tvalid_dti_up

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PCI Express SW Controller Databook Distributed Translation Interface Interrupt Signals

5.3 Distributed Translation Interface Interrupt Signals

- dtim_int
- dtim_err_tresp_oas_int
- dtim_err_tresp_uid_int
- dtim_err_icpl_uc_int
- dtim_err_ireq_opertn_int
- dtim_err_ireq_to_int

Table 5-3 Distributed Translation Interface Interrupt Signals

Port Name I/O Description

dtim_int O Indicates that the Distributed Translation Interface Master (DTIM) has
detected one or more errors. This is a level interrupt. For more details,
refer to the DTI "Interrupts and Error Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.

dtim_err_tresp_oas_int O Indicates that the Distributed Translation Interface Master (DTIM) has
detected a DTI-ATS translation response output address size mismatch
error. This is a level interrupt. For more details, refer to the DTI
"Interrupts and Error Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.

dtim_err_tresp_uid_int O Indicates that the Distributed Translation Interface Master (DTIM) has
detected an unexpected DTI-ATS translation response. The translation
response translation ID can not be associated with an outstanding
DTI-ATS translation request. This is a level interrupt. For more details,
refer to the DTI "Interrupts and Error Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.

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Port Name I/O Description

dtim_err_icpl_uc_int O Indicates that the Distributed Translation Interface Master (DTIM) has
detected an unexpected PCIe invalidate completion error. The PCIe
invalidate completion tag can not be associated with an outstanding
DTI-ATS invalidate request. This is a level interrupt. For more details,
refer to the DTI "Interrupts and Error Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.

dtim_err_ireq_opertn_int O Indicates that the Distributed Translation Interface Master (DTIM) has
detected an illegal DTI-ATS invalidate request operation code. This is a
level interrupt. For more details, refer to the DTI "Interrupts and Error
Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.

dtim_err_ireq_to_int O Indicates that the Distributed Translation Interface Master (DTIM) has
timed out one or more DTI-ATS invalidate requests. The Endpoint
Translation Cache (ATC) has not returned one or more invalidate
completions within an expected timeframe. The outstanding invalidate
completion(s) are not expected to be received at this point in time. This
is a level interrupt. For more details, refer to the DTI "Interrupts and
Error Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.

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PCI Express SW Controller Databook Distributed Translation Interface Invalidate Request Timeout Signals

5.4 Distributed Translation Interface Invalidate Request Timeout Signals

- dtim_ireq_timeout
- dtim_ireq_timeout_sid
- dtim_ireq_timeout_itag

Table 5-4 Distributed Translation Interface Invalidate Request Timeout Signals

Port Name I/O Description

dtim_ireq_timeout O Indicates that the PCIe Invalidate Completion to a DTI-ATS Invalidate


Request has not been recieved within the expetced time window.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.

dtim_ireq_timeout_sid[(DTIM_ATS_SID_L O The lower 16 bits of the DTI-ATS Stream ID of the timed out Invalidate
WR_WD-1):0] Request. These bits represent the Bus, Device and Function Numbers
(BDF) of the target device finction.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: dtim_ireq_timeout

dtim_ireq_timeout_itag[(PCIE_ATS_INV_ O The PCIe Invalidate Request ITAG of the timed out Invalidate Request.
REQ_ITAG_WD-1):0] Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: dtim_ireq_timeout

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CXS Rx Interface Signals PCI Express SW Controller Databook

5.5 CXS Rx Interface Signals

cxsrxvalid - - cxsrxcrdgnt
cxsrxdata - - cxsrxactiveack
cxsrxcntl - - cxsrxdeacthint
cxsrxcrdrtn - - cxsrxcrdgntchk
cxsrxactivereq -
cxsrxdatachk -
cxsrxcntlchk -
cxsrxvalidchk -
cxsrxcrdrtnchk -

Table 5-5 CXS Rx Interface Signals

Port Name I/O Description

cxsrxvalid I Indicates that data flit is valid on CXS Receiver input.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: aux_clk_g,{core_clk}
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: not validated by any other signal

cxsrxdata[(CXSDATAFLITWIDTH-1):0] I CXS Receiver data bus.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: aux_clk_g,{core_clk}
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxsrxvalid is asserted

cxsrxcntl[(CXSCNTLWIDTH-1):0] I CXS Receiver control bus; contains information on packet start, end,
and errors.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: aux_clk_g,{core_clk}
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxsrxvalid is asserted

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PCI Express SW Controller Databook CXS Rx Interface Signals

Port Name I/O Description

cxsrxcrdgnt O CXS Receiver credit grant; grants a single credit for the Transmitter.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: cxsrxactiveack is asserted

cxsrxcrdrtn I CXS Receiver credit return; returns a single credit to the Receiver.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: cxsrxvalid is not asserted

cxsrxactivereq I CXS Receiver link activation or deactivation request.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: {aux_clk},{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: not validated by any other signal

cxsrxactiveack O CXS Receiver link activation or deactivation acknowledge.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: not validated by any other signal

cxsrxdeacthint O CXS Receiver request for link deactivation.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: not validated by any other signal

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CXS Rx Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

cxsrxdatachk[(CXSDATACHKWIDTH-1):0] I CXS Receiver data bus parity bits.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && ((CX_CXS_RX_DATACHECK > 0) ? 1 : 0)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxsrxvalid is asserted

cxsrxcntlchk[(CXSCNTLCHKWIDTH-1):0] I CXS Receiver control bus parity bits.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && ((CX_CXS_RX_DATACHECK > 0) ? 1 : 0)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxsrxvalid is asserted

cxsrxvalidchk[(CXSRXREPWIDTH-1):0] I CXS Receiver valid data replication.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && ((CX_CXS_RX_REPLICATION > 0) ? 1 : 0)
Synchronous To: CX_CXS_SYNCHRONOUS ? "core_clk" : "cxs_clk"
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: not validated by any other signal

cxsrxcrdrtnchk[(CXSRXREPWIDTH-1):0] I CXS Receiver credit return replication.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && ((CX_CXS_RX_REPLICATION > 0) ? 1 : 0)
Synchronous To: CX_CXS_SYNCHRONOUS ? "core_clk" : "cxs_clk"
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: not validated by any other signal

cxsrxcrdgntchk[(CXSRXREPWIDTH-1):0] O CXS Receiver credit grant replication.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && ((CX_CXS_RX_REPLICATION > 0) ? 1 : 0)
Synchronous To: CX_CXS_SYNCHRONOUS ? "core_clk" : "cxs_clk"
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: not validated by any other signal

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PCI Express SW Controller Databook CXS Tx Interface Signals

5.6 CXS Tx Interface Signals

cxstxcrdgnt - - cxstxvalid
cxstxactiveack - - cxstxdata
cxstxdeacthint - - cxstxcntl
cxstxcrdgntchk - - cxstxcrdrtn
- cxstxactivereq
- cxstxdatachk
- cxstxcntlchk
- cxstxvalidchk
- cxstxcrdrtnchk

Table 5-6 CXS Tx Interface Signals

Port Name I/O Description

cxstxvalid O Indicates that data flit is valid on CXS Transmitter output.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: not validated by any other signal

cxstxdata[(CXSDATAFLITWIDTH-1):0] O CXS Transmitter data bus.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxstxvalid is asserted

cxstxcntl[(CXSCNTLWIDTH-1):0] O CXS Transmitter control bus, contains information on packet start, end,
and errors.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxstxvalid is asserted

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CXS Tx Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

cxstxcrdgnt I CXS Transmitter credit grant; grants a single credit for the transmitter.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: cxstxactiveack is asserted

cxstxcrdrtn O CXS Transmitter credit return; returns a single credit to the receiver.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: cxstxvalid is not asserted

cxstxactivereq O CXS Transmitter link activation or deactivation request.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: not validated by any other signal

cxstxactiveack I CXS Transmitter link activation or deactivation acknowledge.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: not validated by any other signal

cxstxdeacthint I CXS Transmitter request for link deactivation.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: not validated by any other signal

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PCI Express SW Controller Databook CXS Tx Interface Signals

Port Name I/O Description

cxstxdatachk[(CXSDATACHKWIDTH-1):0] O CXS Transmitter data bus parity bits.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && ((CX_CXS_TX_DATACHECK > 0) ? 1 : 0)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxstxvalid is asserted

cxstxcntlchk[(CXSCNTLCHKWIDTH-1):0] O CXS Transmitter control bus parity bits.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && ((CX_CXS_TX_DATACHECK > 0) ? 1 : 0)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxstxvalid is asserted

cxstxvalidchk[(CXSTXREPWIDTH-1):0] O CXS Transmitter valid data replication.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && ((CX_CXS_TX_REPLICATION > 0) ? 1 : 0)
Synchronous To: CX_CXS_SYNCHRONOUS ? "core_clk" : "cxs_clk"
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: not validated by any other signal

cxstxcrdrtnchk[(CXSTXREPWIDTH-1):0] O CXS Transmitter credit return replication.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && ((CX_CXS_TX_REPLICATION > 0) ? 1 : 0)
Synchronous To: CX_CXS_SYNCHRONOUS ? "core_clk" : "cxs_clk"
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: not validated by any other signal

cxstxcrdgntchk[(CXSTXREPWIDTH-1):0] I CXS Transmitter credit grant replication.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && ((CX_CXS_TX_REPLICATION > 0) ? 1 : 0)
Synchronous To: CX_CXS_SYNCHRONOUS ? "core_clk" : "cxs_clk"
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: not validated by any other signal

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XALI0 Interface Signals PCI Express SW Controller Databook

5.7 XALI0 Interface Signals

client0_addr_align_en - - xadm_client0_halt
client0_tlp_byte_en -
client0_remote_req_id -
client0_cpl_byte_cnt -
client0_tlp_tc -
client0_tlp_attr -
client0_cpl_status -
client0_cpl_bcm -
client0_tlp_dv -
client0_tlp_eot -
client0_tlp_bad_eot -
client0_tlp_hv -
client0_tlp_fmt -
client0_tlp_type -
client0_tlp_td -
client0_tlp_ep -
client0_tlp_byte_len -
client0_tlp_addr -
client0_hdr_prot -
client0_tlp_tid -
client0_tlp_data -
client0_tlp_func_num -
client0_tlp_prfx -
client0_tlp_atu_bypass -

Table 5-7 XALI0 Interface Signals

Port Name I/O Description

client0_addr_align_en I When client0_addr_align_en is asserted, the controller performs


address alignment and generates the first and last byte enables based
on the address and number of bytes of the TLP requested from the
client interface. When client0_addr_align_en is de-asserted (always for
completions), the controller takes the first and last byte enables from
client0_tlp_byte_en and does not address-align the data. For more
details, see the "Transmit Address Alignment" section in the "Signal
Descriptions" chapter of the Databook. When you do not select the
Enable ECRC Support (CX_ECRC_ENABLE) option, and your
application is generating the ECRC, do not assert
client0_addr_align_en for TLPs that contain application-generated
ECRC. When the TLP from your application does not contain ECRC,
then your application can assert client0_addr_align_en to enable
address alignment.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

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PCI Express SW Controller Databook XALI0 Interface Signals

Port Name I/O Description

client0_tlp_byte_en[7:0] I Byte enables for the first and last dword of the TLP:
■ [3:0]: Byte enables for the first dword
■ [7:4]: Byte enables for the last dword
A TLP can have 'holes' between bytes when the TLP is less than eight
bytes (two dwords) long, according to the PCI Express Specification(not
all valid bytes need to be contiguous). However, a TLP is not allowed to
have holes between bytes when the TLP is more than eight bytes. Not
used (set to 0x0) when 'Transmit Address Alignment' is
(client0_addr_align_en =1 and GLOB_ADDR_ALIGN_EN =1). When
sending a message, your application asserts the message code onto
these signals.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted. Not valid when
client0_addr_align_en is asserted.

client0_remote_req_id[15:0] I Client0 requester ID to be used in the TLP header of a completion TLP.


The value must match the requester ID of the corresponding incoming
request:
■ [15:8]: Bus number
■ [7:3]: Device number
■ [2:0]: Function number
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

client0_cpl_byte_cnt[11:0] I The value to be used for the Byte Count field of a memory read
completion TLP. The value client0_cpl_byte_cnt indicates the number of
bytes remaining to be delivered for the request, as defined in the PCI
Express Specification.
■ 001h: 1 byte
■ FFFh: 4095 bytes
■ 000h: 4096 bytes
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted. Only used when XALI0 is
connected to a completer.

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Port Name I/O Description

client0_tlp_tc[2:0] I The value to be used for the Traffic Class (TC) field of the TLP header
(000b'111b) on XALI0.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

client0_tlp_attr[(ATTR_WD-1):0] I Attributes field for the TLP header


■ Bit 0: No Snoop
■ Bit 1: Relaxed Ordering
■ Width is three bits when CX_IDO_ENABLE =1
■ Width is two bits when CX_IDO_ENABLE =0
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

client0_cpl_status[2:0] I The value to be used in the completion Status field of a completion TLP
header on XALI0:
■ 000b: Successful completion
■ 001b: Unsupported request
■ 010b: Configuration request retry status
■ 100b: Completer abort
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted. Only used when XALI0 is
connected to a completer.

client0_cpl_bcm I Byte Count Modified field on XALI0.


Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

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Port Name I/O Description

client0_tlp_dv I Indicates that the TLP payload data client0_tlp_data is valid. Your
application must not assert client0_tlp_dv for TLPs that do not include a
payload, such as memory read requests. Your application must present
the first payload data the same cycle with the TLP header.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

client0_tlp_eot I Indicates the end of TLP payload data for a TLP that includes a payload.
For a TLP that does not include a payload (such as a memory read
request), your application must assert and de-assert client0_tlp_eot at
the same time as client0_tlp_hv. You must not assert it at any other time.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

client0_tlp_bad_eot I Indicates that the current TLP must be nullified. To nullify a TLP, your
application must assert client0_tlp_bad_eot in the same cycle as
client_tlp_eot. When client0_tlp_bad_eot is asserted, the controller
nullifies the TLP (inverts the LCRC and inserts EDB as the final framing
symbol in the transmitted TLP). Your application can use
client0_tlp_bad_eot to nullify a TLP because of a known error condition,
or to abort the current transaction when the current transaction is being
blocked (for example, due to lack of FC credits):
■ To cancel a request that has not been granted (xadm_client0_halt
has never been de-asserted for the transfer), the CLIENT PULL-
BACK feature from coreConsultant must be selected. In addition, the
following signals must be driven as follows. Assert
client0_tlp_bad_eot and client0_tlp_eot for one clock cycle while
xadm_client0_halt is asserted (indicating that the request has not
been granted), then de-assert client0_tlp_hv, client0_tlp_dv,
client0_tlp_bad_eot, and client0_tlp_eot to terminate the request.
Without the CLIENT_PULLBACK feature, your application has to
send the full packet and mark the EOT and BAD_EOT at the end.
With the CLIENT_PULLBACK feature, your application can mark
EOT and BAD_EOT when it realizes that it needs to nullify the TLP,
without having to present the full packet.
■ To cancel a request that is in progress (xadm_client0_halt has been
asserted for the transfer), assert client0_tlp_bad_eot and
client0_tlp_eot for one clock cycle while xadm_client0_halt is
de-asserted (indicating that the request has been granted), then
de-assert client0_tlp_hv, client0_tlp_dv, client0_tlp_bad_eot, and
client0_tlp_eot to terminate the request. In this case, the controller
nullifies the TLP as described above.
■ When the TLP is a one-cycle request (client0_tlp_hv and
client0_tlp_eot asserted in the same cycle) and client0_tlp_bad_eot
is also asserted, this request is ignored. Sending a nullified TLP is
not very useful because the link partner has to ignore it anyway. Your
application should realize that this request is nullified (in this case
ignored) and de-assert client0_tlp_hv and client0_tlp_eot while
keeping client0_tlp_bad_eot asserted.
■ Nullify Atomic Ops TLP is not supported.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_eot is asserted

client0_tlp_hv I Indicates that the TLP header data the TLP header ports is valid. The
header data must remain valid until client0_tlp_hv is de-asserted.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

client0_tlp_fmt[1:0] I The value to be used for the Format field of the TLP header on XALI0:
■ 00b: 3 dword header, no data
■ 01b: 4 dword header, no data
■ 10b: 3 dword header, with data
■ 11b: 4 dword header, with data
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

client0_tlp_type[4:0] I The value to be used for the Type field of the client0 TLP header, as
defined in the PCI Express Specification.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

client0_tlp_td I TLP Digest bit on XALI0. It is expected that the ECRC is already
present, and the controller forwards it unchanged. You should set this
input to 1.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

client0_tlp_ep I When asserted, the controller sets the Poisoned TLP (EP) bit in the TLP
header on XALI0.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

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Port Name I/O Description

client0_tlp_byte_len[12:0] I The number of bytes in the TLP Payload (not including ECRC). The
value should be in the range 0x0000 (0) to 0x1000 (4096)
When 'Transmit Address Alignment' is (client0_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), this must be the full byte length of the
request. When transmit alignment is off (client0_addr_align_en=0), bits
[1:0] must be set to '00'. The byte length value must be rounded up to
the next dword boundary. For example, when the request is five bytes
long, the value of bits [12:0] must be eight.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

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Port Name I/O Description

client0_tlp_addr[63:0] I The Address field for the TLP header. The TLP address can be 64 or 32
bits. When sending completions, the controller uses
client0_tlp_addr[6:0] for the Lower Address field of the completion TLP.
The bits in this address bus map directly to the address bits in the TLP
header. The third and fourth dwords of the header are mapped as
follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. The third dword
(bytes 8-11) =client0_tlp_addr[31:0]. Therefore, bits [7:0] are
mapped to byte 11 which is the lowest eight bits of the TLP header
address. For more details, see the 'Endianness' advanced informa-
tion chapter.
■ MEM (64-bit) / MSG have a 4-dword header. The third dword (bytes
8-11) =client0_tlp_addr[63:32]. The fourth dword (bytes 12-15)
=client0_tlp_addr[31:0]. Therefore, bits [7:0] are mapped to byte 15
which is the lowest eight bits of the TLP header address. For more
details, see the 'Endianness' advanced information chapter.
When sending a configuration request (DSP), client0_tlp_addr must
contain the following information:
■ [31:24]: Bus Number
■ [23:19]: Device Number
■ [18:16]: Function Number
■ [11:8]: Extended Register Number
■ [7:2]: Register Number
The base width of client0_tlp_addr is 64 bits. When 'Transmit Address
Alignment' is (client0_addr_align_en =1 and GLOB_ADDR_ALIGN_EN
=1), this address is the full byte address of the first enabled byte of the
request. That is, the address is byte-aligned. When transmit alignment
is off (client0_addr_align_en=0), bits [1:0] must be '00', that is, the
address must be dword-aligned.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

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Port Name I/O Description

client0_hdr_prot[(CLIENT_HDR_PROT_W I ECC or parity bits (protection code) for the XALI0 header. Your
D-1):0] application must calculate the protection code over all of the XALI0
header inputs in this order: client0_tlp_th, client0_tlp_st, client0_tlp_ph,
client0_tlp_ln, client0_tlp_func_num, client0_tlp_attr,
client0_addr_align_en, client0_tlp_byte_en, client0_remote_req_id,
client0_cpl_status, client0_cpl_bcm, client0_cpl_byte_cnt,
client0_tlp_tid, client0_tlp_byte_len, client0_tlp_ep, client0_tlp_td,
client0_tlp_tc, client0_tlp_type, client0_tlp_fmt, client0_tlp_addr[63:0].
Exists: (!(AMBA_INTERFACE!=0)) && (((CX_RASDP==0)? 0: 1))
Synchronous To: core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

client0_tlp_tid[(TAG_SIZE-1):0] I Tag field for the TLP header. Your application must provide a valid Tag
client0_tlp_tid for all posted and non-posted requests. The value of the
CX_MAX_TAG configuration option determines the maximum number of
outstanding Client requests. Your application is expected to manage the
Tag for every posted and non-posted request. For completions, the
client0_tlp_tid value must be the Tag from the corresponding request.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

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Port Name I/O Description

client0_tlp_data[(DW_W_PAR-1):0] I The data payload for the TLP. The data is in little endian format. The first
transmitted payload byte is in [7:0]. The base width of client0_tlp_data is
your application datapath width, which is automatically determined
according to the selected operating frequency and number of lanes.
■ For a 32-bit controller, the base width is 32 (client0_tlp_data[31:0])
■ For a 64-bit controller, the base width is 64 (client0_tlp_data[63:0])
■ For a 128-bit controller, the base width is 128 (client0_tlp_-
data[127:0])
■ For a 256-bit controller, the base width is 256(client0_tlp_-
data[255:0])
When 'Transmit Address Alignment' is (client0_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), the first enabled byte of the request
must be bits [7:0] of this data bus. The controller up-shifts the data in the
transmitted TLP based the lower two bits of the byte address. Your
application must append protection code bits to the most significant bits
of this bus when ECC or parity datapath protection is used.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_dv is asserted

client0_tlp_func_num[(PF_WD-1):0] I Indicates from which physical function (PF) the request is coming. The
controller uses client0_tlp_func_num to form the requester ID for
requests and the completer ID for completions. Function numbering
starts at '0'. For a single-function device, set client0_tlp_func_num to
000b.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: None,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

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Port Name I/O Description

xadm_client0_halt O The controller asserts xadm_client0_halt when it is not ready to process


a transaction. The header and payload input for Client0 must remain
unchanged while xadm_client0_halt is asserted. The conditions that
cause the controller to assert xadm_client0_halt include:
■ The XADM is busy servicing one of the other transmit client inter-
faces.
■ There are not enough Flow Control credits available to send the
requested TLP type (P, non-posted, or CPL).
■ The LTSSM is not ready.
■ A retry is in progress.
■ ECRC or LCRC insertion is in progress.
Note:xadm_client0_halt is asserted by default. For more details, see the
timing diagrams in "Signal Interfaces" chapter of the Databook.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

client0_tlp_prfx[(PRFX_DW-1):0] I TLP prefixes. The field [31:0] represents the first prefix to be
transmitted. The optional TLP prefixes are implemented as little endian.
Using the example of a controller with just one prefix (CX_NPRFX =1),
this means that client0_tlp_prfx[31:0] has prefix byte #0 in the lower byte
position of the dword client0_tlp_prfx[31:0]. That is, FMT =bits 7:5, and
Type =bits 4:0. Your application is responsible for passing Local and
End-End prefixes in the correct order for transmission. Local prefixes
must precede End-End prefixes. The controller passes along and
appends to the prefix, any protection codes it receives, when datapath
protection is enabled.
Exists: (!(AMBA_INTERFACE!=0)) && (CX_TLP_PREFIX_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

client0_tlp_atu_bypass I Internal ATU Bypass for XALI0. When set it indicates that this
transaction should not be processed by the internal address translation
unit
Exists: (!(AMBA_INTERFACE!=0)) &&
(CX_INTERNAL_ATU_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

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5.8 XALI1 Interface Signals

client1_addr_align_en - - xadm_client1_halt
client1_tlp_byte_en -
client1_remote_req_id -
client1_cpl_status -
client1_cpl_bcm -
client1_cpl_byte_cnt -
client1_tlp_dv -
client1_tlp_eot -
client1_tlp_bad_eot -
client1_tlp_hv -
client1_tlp_fmt -
client1_tlp_type -
client1_tlp_tc -
client1_tlp_td -
client1_tlp_ep -
client1_tlp_attr -
client1_tlp_byte_len -
client1_tlp_tid -
client1_tlp_addr -
client1_hdr_prot -
client1_tlp_data -
client1_tlp_func_num -
client1_tlp_prfx -
client1_tlp_atu_bypass -

Table 5-8 XALI1 Interface Signals

Port Name I/O Description

client1_addr_align_en I When client1_addr_align_en is asserted, the controller performs


address alignment and generates the first and last byte enables based
on the address and number of bytes of the TLP requested from the
client interface. When client1_addr_align_en is de-asserted (always for
completions), the controller takes the first and last byte enables from
client1_tlp_byte_en and does not address-align the data. For more
details, see the "Transmit Address Alignment" section in the "Signal
Descriptions" chapter of the Databook. When you do not select the
Enable ECRC Support (CX_ECRC_ENABLE) option, and your
application is generating the ECRC, do not assert
client1_addr_align_en for TLPs that contain application-generated
ECRC. When the TLP from your application does not contain ECRC,
then your application can assert client1_addr_align_en to enable
address alignment.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

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Port Name I/O Description

client1_tlp_byte_en[7:0] I Byte enables for the first and last dword of the TLP:
■ [3:0]: Byte enables for the first dword
■ [7:4]: Byte enables for the last dword
A TLP can have 'holes' between bytes when the TLP is less than eight
bytes (2 dwords) long, according to the PCI Express Specification(not
all valid bytes need to be contiguous). However, a TLP is not allowed to
have holes between bytes when the TLP is more than eight bytes. Not
used (set to 0x0) when 'Transmit Address Alignment' is
(client1_addr_align_en =1 and GLOB_ADDR_ALIGN_EN =1). When
sending a message, your application asserts the message code onto
these signals.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted. Not valid when
client1_addr_align_en is asserted.

client1_remote_req_id[15:0] I Client1 requester ID to be used in the TLP header of a completion TLP.


The value must match the requester ID of the corresponding incoming
request:
■ [15:8]: Bus number
■ [7:3]: Device number
■ [2:0]: Function number
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

client1_cpl_status[2:0] I The value to be used in the completion Status field of a completion TLP
header on XALI1:
■ 000b: Successful completion
■ 001b: Unsupported request
■ 010b: Configuration request retry status
■ 100b: Completer abort
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted. Only used when XALI1 is
connected to a completer.

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Port Name I/O Description

client1_cpl_bcm I Byte Count Modified field on XALI1.


Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

client1_cpl_byte_cnt[11:0] I The value to be used for the Byte Count field of a memory read
completion TLP. The value client1_cpl_byte_cnt indicates the number of
bytes remaining to be delivered for the request, as defined in the PCI
Express Specification:
■ 001h: 1 byte
■ FFFh: 4095 bytes
■ 000h: 4096 bytes
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted. Only used when XALI1 is
connected to a completer.

client1_tlp_dv I Indicates that the TLP payload data client1_tlp_data is valid. Your
application must not assert client1_tlp_dv for TLPs that do not include a
payload, such as memory read requests.
Your application must present the first payload data the same cycle with
the TLP header.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

client1_tlp_eot I Indicates the end of TLP payload data for a TLP that includes a payload.
For a TLP that does not include a payload (such as a memory read
request), your application must assert and de-assert client1_tlp_eot at
the same time as client1_tlp_hv. You must not assert it at any other time.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

client1_tlp_bad_eot I Indicates that the current TLP must be nullified. To nullify a TLP, your
application must assert client1_tlp_bad_eot in the same cycle as
client_tlp_eot. When client1_tlp_bad_eot is asserted, the controller
nullifies the TLP (inverts the LCRC and inserts EDB as the final framing
symbol in the transmitted TLP). Your application can use
client1_tlp_bad_eot to nullify a TLP because of a known error condition,
or to abort the current transaction when the current transaction is being
blocked (for example, due to lack of FC credits):
■ To cancel a request that has not been granted (xadm_client1_halt
has never been de-asserted for the transfer), the CLIENT PULL-
BACK feature from coreConsultant must be selected. In addition, the
following signals must be driven as follows. Assert
client1_tlp_bad_eot and client1_tlp_eot for one clock cycle while
xadm_client1_halt is asserted (indicating that the request has not
been granted), then de-assert client1_tlp_hv, client1_tlp_dv,
client1_tlp_bad_eot, and client1_tlp_eot to terminate the request.
Without the CLIENT_PULLBACK feature, your application has to
send the full packet and mark the EOT and BAD_EOT at the end.
With the CLIENT_PULLBACK feature, your application can mark
EOT and BAD_EOT when it realizes that it needs to nullify the TLP,
without having to present the full packet.
■ To cancel a request that is in progress (xadm_client1_halt has been
asserted for the transfer), assert client1_tlp_bad_eot and
client1_tlp_eot for one clock cycle while xadm_client1_halt is
de-asserted (indicating that the request has been granted), then
de-assert client1_tlp_hv, client1_tlp_dv, client1_tlp_bad_eot, and
client1_tlp_eot to terminate the request. In this case, the controller
nullifies the TLP as described above.
■ When the TLP is a one-cycle request (client1_tlp_hv and
client1_tlp_eot asserted in the same cycle) and client1_tlp_bad_eot
is also asserted, this request is ignored. Sending a nullified TLP is
not very useful because the link partner has to ignore it anyway. Your
application should realize that this request is nullified (in this case
ignored) and de-assert client1_tlp_hv and client1_tlp_eot while
keeping client1_tlp_bad_eot asserted.
■ Nullify Atomic Ops TLP is not supported.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_eot is asserted

client1_tlp_hv I Indicates that the TLP header data the TLP header ports is valid. The
header data must remain valid until client1_tlp_hv is de-asserted.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

client1_tlp_fmt[1:0] I The value to be used for the Format field of the TLP header on XALI1:
■ 00b: 3 dword header, no data
■ 01b: 4 dword header, no data
■ 10b: 3 dword header, with data
■ 11b: 4 dword header, with data
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

client1_tlp_type[4:0] I The value to be used for the Type field of the client1 TLP header, as
defined in the PCI Express Specification.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

client1_tlp_tc[2:0] I The value to be used for the Traffic Class (TC) field of the TLP header
(000b'111b) on XALI1.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

client1_tlp_td I TLP Digest bit on XALI1. It is expected that the ECRC is already
present, and the controller forwards it unchanged. You should set this
input to 1.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

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Port Name I/O Description

client1_tlp_ep I When asserted, the controller sets the Poisoned TLP (EP) bit in the TLP
header on XALI1.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

client1_tlp_attr[(ATTR_WD-1):0] I Attributes field for the TLP header


■ Bit 0: No Snoop
■ Bit 1: Relaxed Ordering
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

client1_tlp_byte_len[12:0] I The number of bytes in the TLP (not including ECRC). The value should
be in the range 0x0000 (0) to 0x1000 (4096)
When 'Transmit Address Alignment' is (client1_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), this must be the full byte length of the
request. When transmit alignment is off (client1_addr_align_en=0), bits
[1:0] must be set to '00'. The byte length value must be rounded up to
the next dword boundary. For example, when the request is five bytes
long, the value of bits [12:0] must be eight.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

client1_tlp_tid[(TAG_SIZE-1):0] I Tag field for the TLP header. Your application must provide a valid Tag
client1_tlp_tid for all posted and non-posted requests. The value of the
CX_MAX_TAG configuration option determines the maximum number of
outstanding Client requests. Your application is expected to manage the
Tag for every posted and non-posted request. For completions, the
client1_tlp_tid value must be the Tag from the corresponding request.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

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Port Name I/O Description

client1_tlp_addr[63:0] I The Address field for the TLP header. The TLP address can be 64 or 32
bits. When sending completions, the controller uses
client1_tlp_addr[6:0] for the Lower Address field of the completion TLP.
The bits in this address bus map directly to the address bits in the TLP
header. The third and fourth dwords of the header are mapped as
follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. Third dword (bytes
8-11) =client1_tlp_addr[31:0]. Therefore, bits [7:0] are mapped to
byte 11 which is the lowest eight bits of the TLP header address. For
more details, see the 'Endianness' advanced information chapter.
■ MEM (64-bit) / MSG have a 4-dword header. Third dword (bytes
8-11) =client1_tlp_addr[63:32]. Fourth dword (bytes 12-15)
=client1_tlp_addr[31:0]. Therefore, bits [7:0] are mapped to byte 15
which is the lowest eight bits of the TLP header address. For more
details, see the 'Endianness' advanced information chapter.
When sending (DSP) a configuration request, client1_tlp_addr must
contain the following information:
■ [31:24]: Bus Number
■ [23:19]: Device Number
■ [18:16]: Function Number
■ [11:8]: Extended Register Number
■ [7:2]: Register Number
The base width of client1_tlp_addr is 64 bits. When 'Transmit Address
Alignment' is (client1_addr_align_en =1 and GLOB_ADDR_ALIGN_EN
=1), this address is the full byte address of the first enabled byte of the
request. That is, the address is byte-aligned. When transmit alignment
is off (client1_addr_align_en=0), bits [1:0] must be '00', that is, the
address must be dword-aligned.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

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Port Name I/O Description

client1_hdr_prot[(CLIENT_HDR_PROT_W I ECC or parity bits (protection code) for the XALI1 header. Your
D-1):0] application must calculate the protection code over all of the XALI0
header inputs in this order: client1_tlp_th, client1_tlp_st, client1_tlp_ph,
client1_tlp_ln, client1_tlp_func_num, client1_tlp_attr,
client1_addr_align_en, client1_tlp_byte_en, client1_remote_req_id,
client1_cpl_status, client1_cpl_bcm, client1_cpl_byte_cnt,
client1_tlp_tid, client1_tlp_byte_len, client1_tlp_ep, client1_tlp_td,
client1_tlp_tc, client1_tlp_type, client1_tlp_fmt, client1_tlp_addr[63:0].
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED) &&
(((CX_RASDP==0)? 0: 1))
Synchronous To: core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

client1_tlp_data[(DW_W_PAR-1):0] I The data payload for the TLP. The data is in little endian format. The first
transmitted payload byte is in [7:0]. The base width of client1_tlp_data is
your application datapath width, which is automatically determined
according to the selected operating frequency and number of lanes.
■ For a 32-bit controller, the base width is 32 (client1_tlp_data[31:0])
■ For a 64-bit controller, the base width is 64 (client1_tlp_data[63:0])
■ For a 128-bit controller, the base width is 128 (client1_tlp_-
data[127:0])
■ For a 256-bit controller, the base width is 256(client1_tlp_-
data[255:0])
When 'Transmit Address Alignment' is (client1_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), the first enabled byte of the request
must be bits [7:0] of this data bus. The controller up-shifts the data in the
transmitted TLP based the lower two bits of the byte address. Your
application must append protection code bits to the most significant bits
of this bus when ECC or parity datapath protection is used.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_dv is asserted

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Port Name I/O Description

client1_tlp_func_num[(PF_WD-1):0] I Indicates from which physical function (PF) the request is coming. The
controller uses client1_tlp_func_num to form the requester ID for
requests and the completer ID for completions. Function numbering
starts at '0'. For a single-function device, set client1_tlp_func_num to
000b.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: None,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

xadm_client1_halt O The controller asserts xadm_client1_halt when it is not ready to process


a transaction. The header and payload input for client1 must remain
unchanged while xadm_client1_halt is asserted. The conditions that
cause the controller to assert xadm_client1_halt include:
■ The XADM is busy servicing one of the other transmit client inter-
faces.
■ There are not enough Flow Control credits available to send the
requested TLP type (P, non-posted, or CPL).
■ The LTSSM is not ready.
■ A retry is in progress.
■ ECRC or LCRC insertion is in progress.
Note:xadm_client1_halt is asserted by default. For more details, see the
timing diagrams in "Signal Interfaces" chapter of the Databook.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

client1_tlp_prfx[(PRFX_DW-1):0] I TLP prefixes. The field [31:0] represents the first prefix to be
transmitted. The optional TLP prefixes are implemented as little endian.
Using the example of a controller with just one prefix (CX_NPRFX =1),
this means that client1_tlp_prfx[31:0] has prefix byte #0 in the lower byte
position of the dword client1_tlp_prfx[31:0]. That is, FMT =bits 7:5, and
Type =bits 4:0. Your application is responsible for passing Local and
End-End prefixes in the correct order for transmission. Local prefixes
must precede End-End prefixes. The controller passes along and
appends to the prefix, any protection codes it receives, when datapath
protection is enabled.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED) &&
(CX_TLP_PREFIX_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted

client1_tlp_atu_bypass I Internal ATU Bypass for XALI1. When set it indicates that this
transaction should not be processed by the internal address translation
unit
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED) &&
(CX_INTERNAL_ATU_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

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5.9 XALI2 Interface Signals

client2_addr_align_en - - xadm_client2_halt
client2_tlp_byte_en -
client2_remote_req_id -
client2_cpl_status -
client2_cpl_bcm -
client2_cpl_byte_cnt -
client2_tlp_dv -
client2_tlp_eot -
client2_tlp_bad_eot -
client2_tlp_hv -
client2_tlp_fmt -
client2_tlp_type -
client2_tlp_tc -
client2_tlp_td -
client2_tlp_ep -
client2_tlp_attr -
client2_tlp_byte_len -
client2_tlp_tid -
client2_tlp_addr -
client2_hdr_prot -
client2_tlp_data -
client2_tlp_func_num -
client2_tlp_prfx -
client2_tlp_atu_bypass -

Table 5-9 XALI2 Interface Signals

Port Name I/O Description

client2_addr_align_en I When client2_addr_align_en is asserted, the controller performs


address alignment and generates the first and last byte enables based
on the address and number of bytes of the TLP requested from the
client interface. When client2_addr_align_en is de-asserted (always for
completions), the controller takes the first and last byte enables from
client2_tlp_byte_en and does not address-align the data. For more
details, see the "Transmit Address Alignment" section in the "Signal
Descriptions" chapter of the Databook. When you do not select the
Enable ECRC Support (CX_ECRC_ENABLE) option, and your
application is generating the ECRC, do not assert
client2_addr_align_en for TLPs that contain application-generated
ECRC. When the TLP from your application does not contain ECRC,
then your application can assert client2_addr_align_en to enable
address alignment.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

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Port Name I/O Description

client2_tlp_byte_en[7:0] I Byte enables for the first and last dword of the TLP:
■ [3:0]: Byte enables for the first dword
■ [7:4]: Byte enables for the last dword
A TLP can have 'holes' between bytes when the TLP is less than eight
bytes (2 dwords) long, according to the PCI Express Specification(not
all valid bytes need to be contiguous). However, a TLP is not allowed to
have holes between bytes when the TLP is more than eight bytes. Not
used (set to 0x0) when 'Transmit Address Alignment' is
(client2_addr_align_en =1 and GLOB_ADDR_ALIGN_EN =1). When
sending a message, your application asserts the message code onto
these signals.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted. Not valid when
client2_addr_align_en is asserted.

client2_remote_req_id[15:0] I Client2 requester ID to be used in the TLP header of a completion TLP.


The value must match the requester ID of the corresponding incoming
request:
■ [15:8]: Bus number
■ [7:3]: Device number
■ [2:0]: Function number
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

client2_cpl_status[2:0] I The value to be used in the completion Status field of a completion TLP
header:
■ 000b: Successful completion
■ 001b: Unsupported request
■ 010b: Configuration request retry status
■ 100b: Completer abort
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted. Only used when XALI2 is
connected to a completer.

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Port Name I/O Description

client2_cpl_bcm I Byte Count Modified field on XALI2.


Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

client2_cpl_byte_cnt[11:0] I The value to be used for the Byte Count field of a memory read
completion TLP. The value client2_cpl_byte_cnt indicates the number of
bytes remaining to be delivered for the request, as defined in the PCI
Express Specification:
■ 001h: 1 byte
■ FFFh: 4095 bytes
■ 000h: 4096 bytes
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted. Only used when XALI2 is
connected to a completer.

client2_tlp_dv I Indicates that the TLP payload data client2_tlp_data is valid. Your
application must not assert client2_tlp_dv for TLPs that do not include a
payload, such as memory read requests.
Your application must present the first payload data the same cycle with
the TLP header.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

client2_tlp_eot I Indicates the end of TLP payload data for a TLP that includes a payload.
For a TLP that does not include a payload (such as a memory read
request), your application must assert and de-assert client2_tlp_eot at
the same time as client2_tlp_hv. You must not assert it at any other time.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

client2_tlp_bad_eot I Indicates that the current TLP must be nullified. To nullify a TLP, your
application must assert client2_tlp_bad_eot in the same cycle as
client_tlp_eot. When client2_tlp_bad_eot is asserted, the controller
nullifies the TLP (inverts the LCRC and inserts EDB as the final framing
symbol in the transmitted TLP). Your application can use
client2_tlp_bad_eot to nullify a TLP because of a known error condition,
or to abort the current transaction when the current transaction is being
blocked (for example, due to lack of FC credits):
■ To cancel a request that has not been granted (xadm_client2_halt
has never been de-asserted for the transfer), the CLIENT PULL-
BACK feature from coreConsultant must be selected. In addition, the
following signals must be driven as follows. Assert
client2_tlp_bad_eot and client2_tlp_eot for one clock cycle while
xadm_client2_halt is asserted (indicating that the request has not
been granted), then de-assert client2_tlp_hv, client2_tlp_dv,
client2_tlp_bad_eot, and client2_tlp_eot to terminate the request.
Without the CLIENT_PULLBACK feature, your application has to
send the full packet and mark the EOT and BAD_EOT at the end.
With the CLIENT_PULLBACK feature, your application can mark
EOT and BAD_EOT when it realizes that it needs to nullify the TLP,
without having to present the full packet.
■ To cancel a request that is in progress (xadm_client2_halt has been
asserted for the transfer), assert client2_tlp_bad_eot and
client2_tlp_eot for one clock cycle while xadm_client2_halt is
de-asserted (indicating that the request has been granted), then
de-assert client2_tlp_hv, client2_tlp_dv, client2_tlp_bad_eot, and
client2_tlp_eot to terminate the request. In this case, the controller
nullifies the TLP as described above.
■ When the TLP is a one-cycle request (client2_tlp_hv and
client2_tlp_eot asserted in the same cycle) and client2_tlp_bad_eot
is also asserted, this request is ignored. Sending a nullified TLP is
not very useful because the link partner has to ignore it anyway. Your
application should realize that this request is nullified (in this case
ignored) and de-assert client2_tlp_hv and client2_tlp_eot while
keeping client2_tlp_bad_eot asserted.
■ Nullify Atomic Ops TLP is not supported.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_eot is asserted

client2_tlp_hv I Indicates that the TLP header data the TLP header ports is valid. The
header data must remain valid until client2_tlp_hv is de-asserted.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

client2_tlp_fmt[1:0] I The value to be used for the Format field of the TLP header:
■ 00b: 3 dword header, no data
■ 01b: 4 dword header, no data
■ 10b: 3 dword header, with data
■ 11b: 4 dword header, with data
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

client2_tlp_type[4:0] I The value to be used for the Type field of the client2 TLP header, as
defined in the PCI Express Specification.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

client2_tlp_tc[2:0] I The value to be used for the Traffic Class (TC) field of the TLP header
(000b'111b) on XALI2.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

client2_tlp_td I TLP Digest bit. It is expected that the ECRC is already present, and the
controller forwards it unchanged. You should set this input to 1.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

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Port Name I/O Description

client2_tlp_ep I When asserted, the controller sets the Poisoned TLP (EP) bit in the TLP
header on XALI2.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

client2_tlp_attr[(ATTR_WD-1):0] I Attributes field for the TLP header


■ Bit 0: No Snoop
■ Bit 1: Relaxed Ordering
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

client2_tlp_byte_len[12:0] I The number of bytes in the TLP (not including ECRC). The value should
be in the range 0x0000 (0) to 0x1000 (4096)
When 'Transmit Address Alignment' is (client2_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), this must be the full byte length of the
request. When transmit alignment is off (client2_addr_align_en=0), bits
[1:0] must be set to '00'. The byte length value must be rounded up to
the next dword boundary. For example, when the request is five bytes
long, the value of bits [12:0] must be eight.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

client2_tlp_tid[(TAG_SIZE-1):0] I Tag field for the TLP header. Your application must provide a valid Tag
client2_tlp_tid for all posted and non-posted requests. The value of the
CX_MAX_TAG configuration option determines the maximum number of
outstanding Client requests. Your application is expected to manage the
Tag for every posted and non-posted request. For completions, the
client2_tlp_tid value must be the Tag from the corresponding request.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

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Port Name I/O Description

client2_tlp_addr[63:0] I The Address field for the TLP header. The TLP address can be 64 or 32
bits. When sending completions, the controller uses
client2_tlp_addr[6:0] for the Lower Address field of the completion TLP.
The bits in this address bus map directly to the address bits in the TLP
header. The third and fourth dwords of the header are mapped as
follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. Third dword (bytes
8-11) =client2_tlp_addr[31:0]. Therefore, bits [7:0] are mapped to
byte 11 which is the lowest eight bits of the TLP header address. For
more details, see the 'Endianness' advanced information chapter.
■ MEM (64-bit) / MSG have a 4-dword header. Third dword (bytes
8-11) =client2_tlp_addr[63:32]. Fourth dword (bytes 12-15)
=client2_tlp_addr[31:0]. Therefore, bits [7:0] are mapped to byte 15
which is the lowest eight bits of the TLP header address. For more
details, see the 'Endianness' advanced information chapter.
When sending (DSP) a configuration request, client2_tlp_addr must
contain the following information:
■ [31:24]: Bus Number
■ [23:19]: Device Number
■ [18:16]: Function Number
■ [11:8]: Extended Register Number
■ [7:2]: Register Number
The base width of client2_tlp_addr is 64 bits. When 'Transmit Address
Alignment' is (client2_addr_align_en =1 and GLOB_ADDR_ALIGN_EN
=1), this address is the full byte address of the first enabled byte of the
request. That is, the address is byte-aligned. When transmit alignment
is off (client2_addr_align_en=0), bits [1:0] must be '00', that is, the
address must be dword-aligned.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

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XALI2 Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

client2_hdr_prot[(CLIENT_HDR_PROT_W I ECC or parity bits (protection code) for the XALI2 header. Your
D-1):0] application must calculate the protection code over all of the XALI0
header inputs in this order: client2_tlp_th, client2_tlp_st, client2_tlp_ph,
client2_tlp_ln, client2_tlp_func_num, client2_tlp_attr,
client2_addr_align_en, client2_tlp_byte_en, client2_remote_req_id,
client2_cpl_status, client2_cpl_bcm, client2_cpl_byte_cnt,
client2_tlp_tid, client2_tlp_byte_len, client2_tlp_ep, client2_tlp_td,
client2_tlp_tc, client2_tlp_type, client2_tlp_fmt, client2_tlp_addr[63:0].
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED) &&
(((CX_RASDP==0)? 0: 1))
Synchronous To: core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

client2_tlp_data[(DW_W_PAR-1):0] I The data payload for the TLP. The data is in little endian format. The first
transmitted payload byte is in [7:0]. The base width of client2_tlp_data is
your application datapath width, which is automatically determined
according to the selected operating frequency and number of lanes.
■ For a 32-bit controller, the base width is 32 (client2_tlp_data[31:0])
■ For a 64-bit controller, the base width is 64 (client2_tlp_data[63:0])
■ For a 128-bit controller, the base width is 128 (client2_tlp_-
data[127:0])
■ For a 256-bit controller, the base width is 256(client2_tlp_-
data[255:0])
When 'Transmit Address Alignment' is (client2_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), the first enabled byte of the request
must be bits [7:0] of this data bus. The controller up-shifts the data in the
transmitted TLP based the lower two bits of the byte address. Your
application must append protection code bits to the most significant bits
of this bus when ECC or parity datapath protection is used.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_dv is asserted

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PCI Express SW Controller Databook XALI2 Interface Signals

Port Name I/O Description

client2_tlp_func_num[(PF_WD-1):0] I Indicates from which physical function (PF) the request is coming. The
controller uses client2_tlp_func_num to form the requester ID for
requests and the completer ID for completions. Function numbering
starts at '0'. For a single-function device, set client2_tlp_func_num to
000b.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: None,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

xadm_client2_halt O The controller asserts xadm_client2_halt when it is not ready to process


a transaction. The header and payload input for client2 must remain
unchanged while xadm_client2_halt is asserted. The conditions that
cause the controller to assert xadm_client2_halt include:
■ The XADM is busy servicing one of the other transmit client inter-
faces.
■ There are not enough Flow Control credits available to send the
requested TLP type (P, non-posted, or CPL).
■ The LTSSM is not ready.
■ A retry is in progress.
■ ECRC or LCRC insertion is in progress.
Note:xadm_client2_halt is asserted by default. For more details, see the
timing diagrams in "Signal Interfaces" chapter of the Databook.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

client2_tlp_prfx[(PRFX_DW-1):0] I TLP prefixes. The field [31:0] represents the first prefix to be
transmitted. The optional TLP prefixes are implemented as little endian.
Using the example of a controller with just one prefix (CX_NPRFX =1),
this means that client2_tlp_prfx[31:0] has prefix byte #0 in the lower byte
position of the dword client2_tlp_prfx[31:0]. That is, FMT =bits 7:5, and
Type =bits 4:0. Your application is responsible for passing Local and
End-End prefixes in the correct order for transmission. Local prefixes
must precede End-End prefixes. The controller passes along and
appends to the prefix, any protection codes it receives, when datapath
protection is enabled.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED) &&
(CX_TLP_PREFIX_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted

client2_tlp_atu_bypass I Internal ATU Bypass for XALI2. When set it indicates that this
transaction should not be processed by the internal address translation
unit
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED) &&
(CX_INTERNAL_ATU_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted

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PCI Express SW Controller Databook XALI_CCIX Interface Signals

5.10 XALI_CCIX Interface Signals

ccix_tlp_hv - - xadm_ccix_tlp_halt
ccix_tlp_dv -
ccix_tlp_hdr -
ccix_tlp_data -
ccix_tlp_eot -
ccix_tlp_bad_eot -

Table 5-10 XALI_CCIX Interface Signals

Port Name I/O Description

ccix_tlp_hv I Indicates that the TLP header data in the TLP header ports is valid. The
header data must remain valid until ccix_tlp_hv is de-asserted.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: aux_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ccix_tlp_dv I Indicates that the TLP payload data ccix_tlp_data is valid. Your
application must not assert ccix_tlp_dv for TLPs that do not include a
payload.
Your application must present the first payload data the same cycle with
the TLP header.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ccix_tlp_hdr[(TX_HW_W_PAR-1):0] I Header for the TLP being presented in the CCIX interface.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: ccix_tlp_hv is asserted

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Port Name I/O Description

ccix_tlp_data[(DW_W_PAR-1):0] I Payload data in CCIX interfaces. Your application must not assert
ccix_tlp_dv for TLPs that do not include a payload.
Your application must present the first payload data the same cycle with
the TLP header.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

ccix_tlp_eot I Indicates the last segment of the TLP in the CCIX dedicated interface.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ccix_tlp_hv or ccix_tlp_dv is asserted

ccix_tlp_bad_eot I When asserted causes the TLP being sent to be nullified.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ccix_tlp_eot is asserted

xadm_ccix_tlp_halt O Halt the CCIX interface.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: not validated by any other signal

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PCI Express SW Controller Databook ADM adaptor Interface Signals

5.11 ADM adaptor Interface Signals

xadm_rfc_in - - xadm_xtlh_out
rtlh_radm_in - - radm_rfc_out
cx_pl_ltssm_emu_in - - cx_pl_ltssm_emu_out

Table 5-11 ADM adaptor Interface Signals

Port Name I/O Description

xadm_rfc_in[(XADM_RFC_IN_WD-1):0] I xadm input FC received from radm.


Exists: CX_ADM_ADAPTOR_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_xtlh_out[(XADM_XTLH_OUT_WD-1 O xadm transmits TLP traffic to radm.


):0] Exists: CX_ADM_ADAPTOR_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

rtlh_radm_in[(RTLH_RAMD_IN_WD-1):0] I radm receives TLP traffic from xadm.


Exists: CX_ADM_ADAPTOR_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_rfc_out[(RADM_RFC_OUT_WD-1): O radm output FC transmitted to xadm.


0] Exists: CX_ADM_ADAPTOR_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cx_pl_ltssm_emu_in[(LTSSM_EMU_IN_W I LTSSM emu input signals.


D-1):0] Exists: CX_ADM_ADAPTOR_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cx_pl_ltssm_emu_out[(LTSSM_EMU_OU O LTSSM emu output signals


T_WD-1):0] Exists: CX_ADM_ADAPTOR_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Bypass Interface Signals

5.12 Bypass Interface Signals

- radm_bypass_data
- radm_bypass_dwen
- radm_bypass_dv
- radm_bypass_hv
- radm_bypass_eot
- radm_bypass_dllp_abort
- radm_bypass_tlp_abort
- radm_bypass_ecrc_err
- radm_bypass_hdr_prot
- radm_bypass_fmt
- radm_bypass_type
- radm_bypass_tc
- radm_bypass_attr
- radm_bypass_reqid
- radm_bypass_tag
- radm_bypass_func_num
- radm_bypass_td
- radm_bypass_poisoned
- radm_bypass_dw_len
- radm_bypass_first_be
- radm_bypass_last_be
- radm_bypass_addr
- radm_bypass_bcm
- radm_bypass_cpl_last
- radm_bypass_cmpltr_id
- radm_bypass_byte_cnt
- radm_bypass_cpl_status
- radm_bypass_tlp_prfx

Table 5-12 Bypass Interface Signals

Port Name I/O Description

radm_bypass_data[(DW_W_PAR-1):0] O The payload data from the received TLP. The data is in little endian
format. The first received payload byte is in [7:0]. The controller
appends protection code bits to the most significant bits of this bus
when ECC or parity datapath protection is used.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_dv is asserted

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Port Name I/O Description

radm_bypass_dwen[(NW-1):0] O The databus dword enables identify the location of the last dword of the
TLP the data bus (radm_bypass_data). The width and usage of
radm_bypass_dwen depend the data width of the controller. For a 32-bit
controller, radm_bypass_dwen is not used. For a 64-bit controller, NW
=2. The radm_bypass_dwen[1:0] encoding is:
■ 01: Last dword at radm_bypass_data[31:0].
■ 11: Last dword at radm_bypass_data[63:32].
For a 128-bit controller, NW =4. The radm_bypass_dwen[3:0] encoding
is:
■ 0001: Last dword at radm_bypass_data[31:0].
■ 0011: Last dword at radm_bypass_data[63:32].
■ 0111: Last dword at radm_bypass_data[95:64].
■ 1111: Last dword at radm_bypass_data[127:96].
For a 256-bit controller, NW =8. The radm_bypass_dwen[7:0] encoding
is:
■ 00000001: Last dword at radm_bypass_data[31:0].
■ 00000011: Last dword at radm_bypass_data[63:32].
■ 00000111: Last dword at radm_bypass_data[95:64].
■ 00001111: Last dword at radm_bypass_data[127:96].
■ 00011111: Last dword at radm_bypass_data[159:128].
■ 00111111: Last dword at radm_bypass_data[191:160].
■ 01111111: Last dword at radm_bypass_data[223:192].
■ 11111111: Last dword at radm_bypass_data[255:224].
All other encodings are not generated by the controller.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_eot is asserted

radm_bypass_dv[(NHQ-1):0] O Indicates valid received payload data radm_bypass_data.


Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Bypass Interface Signals

Port Name I/O Description

radm_bypass_hv[(NHQ-1):0] O Indicates that the header and prefix information radm_bypass_hdr is


valid. The controller asserts radm_bypass_hv for one clock cycle. For
bypassed queues, your application must capture the header information
as soon as the radm_bypass_hv is asserted.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_bypass_eot[(NHQ-1):0] O Indicates the last cycle of valid payload data radm_bypass_data for the
received TLP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv or radm_bypass_dv is asserted

radm_bypass_dllp_abort[(NHQ-1):0] O Indicates to your application to drop the TLP on RBYP because of a


Data Link Layer error such as LCRC or otherwise. You can expect the
DLLP to be replayed. For more details, see the 'Advanced Error
Handling For Received TLPs' advanced information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_eot

radm_bypass_tlp_abort[(NHQ-1):0] O Indicates to your application to drop the TLP because of malformed TLP
on RBYP, ECRC error, or completion lookup failures (such as TAG or
requester ID (RID) mismatches). You should not expect the TLP to be
replayed. For more details, see the 'Advanced Error Handling For
Received TLPs' advanced information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_eot, radm_bypass_hv

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Port Name I/O Description

radm_bypass_ecrc_err[(NHQ-1):0] O Indicates to your application to drop the TLP because of an ECRC error
in the received TLP on RBYP. You should not expect the TLP to be
replayed. For more details, see the 'Advanced Error Handling For
Received TLPs' advanced information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_eot

radm_bypass_hdr_prot[((NHQ*RASDP_B O ECC or parity bits (protection code) generated by the controller for the
YPASS_HDR_PROT_WD)-1):0] TLP header (bypass mode). Your application must calculate the
protection code over all of the XALI0 header inputs in this order:
radm_bypass_ats, radm_bypass_th, radm_bypass_st,
radm_bypass_ph, radm_bypass_ln, radm_bypass_last_be,
radm_bypass_cpl_last, radm_bypass_poisoned, radm_bypass_td,
radm_bypass_addr, radm_bypass_first_be,
radm_bypass_io_req_in_range, radm_bypass_rom_in_range,
radm_bypass_in_membar_range, radm_bypass_dw_len,
radm_bypass_cpl_status, radm_bypass_func_num, radm_bypass_tag,
radm_bypass_reqid, radm_bypass_attr, radm_bypass_tc,
radm_bypass_type, radm_bypass_fmt.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2)) &&
(((CX_RASDP==0)? 0: 1))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_bypass_hv is asserted

radm_bypass_fmt[((NHQ*2)-1):0] O The Format field in the received TLP header on RBYP.


Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_type[((NHQ*5)-1):0] O The Type field in the received TLP header on RBYP.


Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

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PCI Express SW Controller Databook Bypass Interface Signals

Port Name I/O Description

radm_bypass_tc[((NHQ*3)-1):0] O The Traffic Class (TC) field in the received TLP header on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_attr[((NHQ*ATTR_WD)-1):0] O The Attributes field in the received TLP header on RBYP.


Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_reqid[((NHQ*16)-1):0] O The requester ID in the received TLP header on RBYP.


■ [15:8]: Bus number
■ [7:3]: Device number
■ [2:0]: Function number
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_tag[((NHQ*TAG_SIZE)-1):0] O The Tag field in the received TLP header on RBYP.


Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_func_num[((NHQ*PF_WD)- O The function number of the incoming TLP on RBYP. Function numbering
1):0] starts at '0'.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

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Port Name I/O Description

radm_bypass_td[(NHQ-1):0] O The TLP Digest (TD) bit in the received TLP header on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_poisoned[(NHQ-1):0] O The Poisoned (EP) bit in the received TLP header on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_dw_len[((NHQ*10)-1):0] O The Length field (length of TLP in dwords) in the received TLP header
on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_first_be[((NHQ*4)-1):0] O The first dword byte enable field in the received TLP header on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_last_be[((NHQ*4)-1):0] O The last dword byte enable field in the received TLP header on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

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PCI Express SW Controller Databook Bypass Interface Signals

Port Name I/O Description

radm_bypass_addr[((NHQ*FLT_Q_ADDR O The Address in the received TLP header on RBYP. The bits in this
_WIDTH)-1):0] address bus map directly to the address bits in the TLP header. The
third and fourth dwords of the header are mapped as follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. Then radm_by-
pass_addr[31:0] =Third dword (bytes 8-11). Therefore, bits [7:0] are
mapped to byte 11 which is the lowest eight bits of the TLP header
address. For more details, see the 'Endianness' advanced informa-
tion chapter.
■ MEM (64-bit) / MSG have a 4-dword header. Then radm_by-
pass_addr[63:32] =Third dword (bytes 8-11) and radm_by-
pass_addr[31:0] =Fourth dword (bytes 12-15). Therefore, bits [7:0]
are mapped to byte 15 which is the lowest eight bits of the TLP
header address. For more details, see the 'Endianness' advanced
information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_bcm[(NHQ-1):0] O Byte Count Modified (BCM) bit from the received TLP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_cpl_last[(NHQ-1):0] O Reserved
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

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Port Name I/O Description

radm_bypass_cmpltr_id[((NHQ*16)-1):0] O Completer ID field from the header of a received completion TLP on


RBYP.
■ [15:8]: Bus number
■ [7:3]: Device number
■ [2:0]: Function number
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_byte_cnt[((NHQ*12)-1):0] O Byte Count field from the received TLP.


Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_cpl_status[((NHQ*3)-1):0] O Completion Status field from the header of a received completion TLP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

radm_bypass_tlp_prfx[((NHQ*PRFX_W_P O Receive TLP prefixes. The field [31:0] represents the first prefix to be
AR)-1):0] received. The optional TLP prefixes are implemented as little endian.
Using the example of a controller with just one prefix (CX_NPRFX =1),
this means that radm_bypass_tlp_prfx[31:0] has prefix byte #0 in the
lower byte position of the dword radm_bypass_tlp_prfx[31:0]. That is,
FMT =bits 7:5, and Type =bits 4:0. If no prefix is present for a given TLP,
then that DW, including the FMT field is all zeros. The controller passes
along and appends to the prefix, any protection codes it receives, when
datapath protection is enabled.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2)) &&
(CX_TLP_PREFIX_ENABLE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted

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PCI Express SW Controller Databook RTRGT1 Interface Signals

5.13 RTRGT1 Interface Signals

trgt1_radm_halt - - radm_trgt1_dv
trgt1_radm_pkt_halt - - radm_trgt1_hv
- radm_trgt1_eot
- radm_trgt1_tlp_abort
- radm_trgt1_dllp_abort
- radm_trgt1_ecrc_err
- radm_trgt1_data
- radm_trgt1_tlp_prfx
- radm_trgt1_dwen
- radm_trgt1_hdr_prot
- radm_trgt1_fmt
- radm_trgt1_type
- radm_trgt1_tc
- radm_trgt1_attr
- radm_trgt1_reqid
- radm_trgt1_tag
- radm_trgt1_func_num
- radm_trgt1_td
- radm_trgt1_poisoned
- radm_trgt1_dw_len
- radm_trgt1_first_be
- radm_trgt1_last_be
- radm_trgt1_addr
- radm_trgt1_hdr_uppr_bytes
- radm_trgt1_hdr_uppr_bytes_valid
- radm_trgt1_cpl_status
- radm_trgt1_bcm
- radm_trgt1_byte_cnt
- radm_trgt1_cpl_last
- radm_trgt1_cmpltr_id
- radm_trgt1_vc
- radm_grant_tlp_type
- radm_trgt1_atu_sloc_match
- radm_trgt1_atu_cbuf_err

Table 5-13 RTRGT1 Interface Signals

Port Name I/O Description

trgt1_radm_halt I Flow control input signal. When trgt1_radm_halt is asserted, the


controller stops streaming the next valid data from the queue inside the
RADM. The data bus (radm_trgt1_data) remains unchanged while
trgt1_radm_halt is asserted.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

radm_trgt1_dv O Indicates that the received TLP data is valid on radm_trgt1_data. For
timing details, see the Receive Request Interface (TRGT1) section in
the Signal Interfaces chapter of the Databook.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_trgt1_hv O Indicates that the received TLP header (and prefix) is valid on the
corresponding radm_trgt1_* outputs. For timing details, see the Receive
Request Interface (TRGT1) section in the Signal Interfaces chapter of
the Databook.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_trgt1_eot O Indicates the last cycle of valid data for the received TLP.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv or radm_trgt1_dv is asserted

radm_trgt1_tlp_abort O Indicates to your application to drop the TLP because of malformed TLP
on TRGT1, ECRC error, or completion lookup failures (such as TAG or
requester ID (RID) mismatches). You should not expect the TLP to be
replayed. For more details, see the 'Advanced Error Handling For
Received TLPs' advanced information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_eot, radm_trgt1_hv

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PCI Express SW Controller Databook RTRGT1 Interface Signals

Port Name I/O Description

radm_trgt1_dllp_abort O Indicates to your application to drop the TLP on TRGT1 because of a


Data Link Layer error such as LCRC or otherwise. You can expect the
DLLP to be replayed. For more details, see the 'Advanced Error
Handling For Received TLPs' advanced information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_eot

radm_trgt1_ecrc_err O Indicates to your application to drop the TLP because of an ECRC error
in the received TLP on TRGT1. You should not expect the TLP to be
replayed. For more details, see the 'Advanced Error Handling For
Received TLPs' advanced information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_eot

radm_trgt1_data[(TRGT_DATA_WD-1):0] O Received TLP payload data from the upstream component to your
application client. The data is in little endian format. The first received
payload byte is in [7:0]. The controller appends protection code bits to
the most significant bits of this bus when ECC or parity datapath
protection is used.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_dv is asserted

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Port Name I/O Description

radm_trgt1_tlp_prfx[(PRFX_W_PAR-1):0] O Receive TLP prefixes. The field [31:0] represents the first prefix to be
received. The optional TLP prefixes are implemented as little endian.
Using the example of a controller with just one prefix (CX_NPRFX =1),
this means that radm_trgt1_tlp_prfx[31:0] has prefix byte #0 in the lower
byte position of the dword radm_trgt1_tlp_prfx[31:0]. That is, FMT =bits
7:5, and Type =bits 4:0. If no prefix is present for a given TLP, then that
DW, including the FMT field is all zeros. The controller passes along and
appends to the prefix, any protection codes it receives, when datapath
protection is enabled.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
(CX_TLP_PREFIX_ENABLE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

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PCI Express SW Controller Databook RTRGT1 Interface Signals

Port Name I/O Description

radm_trgt1_dwen[(NW-1):0] O The databus dword enables identify the location of the last dword of the
TLP the data bus (radm_trgt1_data). The width and usage of
radm_trgt1_dwen depend the data width of the controller. For a 32-bit
controller, radm_trgt1_dwen is not used.
For a 64-bit controller, NW =2. The radm_trgt1_dwen[1:0] encoding is:
■ 01: Last dword at radm_trgt1_data[31:0].
■ 11: Last dword at radm_trgt1_data[63:32].
For a 128-bit controller, NW =4. The radm_trgt1_dwen[3:0] encoding is:
■ 0001: Last dword at radm_trgt1_data[31:0].
■ 0011: Last dword at radm_trgt1_data[63:32].
■ 0111: Last dword at radm_trgt1_data[95:64].
■ 1111: Last dword at radm_trgt1_data[127:96].
For a 256-bit controller, NW =8. The radm_trgt1_dwen[7:0] encoding is:
■ 00000001: Last dword at radm_trgt1_data[31:0].
■ 00000011: Last dword at radm_trgt1_data[63:32].
■ 00000111: Last dword at radm_trgt1_data[95:64].
■ 00001111: Last dword at radm_trgt1_data[127:96].
■ 00011111: Last dword at radm_trgt1_data[159:128].
■ 00111111: Last dword at radm_trgt1_data[191:160].
■ 01111111: Last dword at radm_trgt1_data[223:192].
■ 11111111: Last dword at radm_trgt1_data[255:224].
For a 512-bit controller, NW =16. The radm_trgt1_dwen[15:0] encoding
is:
■ 00000001_11111111: Last dword at radm_trgt1_data[287:256].
■ 00000011_11111111: Last dword at radm_trgt1_data[319:288].
■ 00000111_11111111: Last dword at radm_trgt1_data[351:320].
■ 00001111_11111111: Last dword at radm_trgt1_data[383:352].
■ 00011111_11111111: Last dword at radm_trgt1_data[415:384].
■ 00111111_11111111: Last dword at radm_trgt1_data[447:416].
■ 01111111_11111111: Last dword at radm_trgt1_data[479:448].
■ 11111111_11111111: Last dword at radm_trgt1_data[511:480].
All other encodings are not generated by the controller.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_eot is asserted and NW > 1

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Port Name I/O Description

radm_trgt1_hdr_prot[(RASDP_TRGT1_H O ECC or parity bits (protection code) generated by the controller for the
DR_PROT_WD-1):0] TLP header. Your application must calculate the protection code over all
of the target1 header inputs in this order: radm_trgt1_hdr_uppr_bytes,
radm_trgt1_hdr_uppr_bytes_valid, radm_trgt1_ats, radm_trgt1_th,
radm_trgt1_st, radm_trgt1_ph, radm_trgt1_ln, radm_trgt1_last_be,
radm_trgt1_cpl_last, radm_trgt1_poisoned, radm_trgt1_td,
radm_trgt1_addr, radm_trgt1_first_be, radm_trgt1_io_req_in_range,
radm_trgt1_dw_len, radm_trgt1_cpl_status, radm_trgt1_func_num,
radm_trgt1_tag, radm_trgt1_reqid, radm_trgt1_attr, radm_trgt1_tc,
radm_trgt1_type, radm_trgt1_fmt.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
(((CX_RASDP==0)? 0: 1))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_trgt1_hv is asserted

radm_trgt1_fmt[1:0] O The Format field in the received TLP header on TRGT1.


Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_type[4:0] O The Type field in the received TLP header on TRGT1.


Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_tc[2:0] O The Traffic Class (TC) field in the received TLP header on TRGT1.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

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Port Name I/O Description

radm_trgt1_attr[(ATTR_WD-1):0] O The Attributes field in the received TLP header on TRGT1.


Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_reqid[15:0] O The requester ID in the received TLP header on TRGT1.


■ [15:8]: Bus number
■ [7:3]: Device number
■ [2:0]: Function number
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_tag[(TAG_SIZE-1):0] O The Tag field in the received TLP header on TRGT1.


Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_func_num[(PF_WD-1):0] O The function number of the incoming TLP on TRGT1. Function


numbering starts at '0'.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_td O The TLP Digest (TD) bit in the received TLP header on TRGT1.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

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Port Name I/O Description

radm_trgt1_poisoned O The Poisoned (EP) bit in the received TLP header on TRGT1.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_dw_len[9:0] O The Length field (length of TLP in dwords) in the received TLP header
on TRGT1.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_first_be[3:0] O The first dword byte enable field in the received TLP header on TRGT1.
When a TLP is a message, radm_trgt1_first_be is overlaid with
message_code[3:0]
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_last_be[3:0] O The last dword byte enable field in the received TLP header on TRGT1.
When a TLP is a message, radm_trgt1_last_be is overlaid with
message_code[7:4]
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

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PCI Express SW Controller Databook RTRGT1 Interface Signals

Port Name I/O Description

radm_trgt1_addr[(ADDR_WIDTH-1):0] O The Address in the received TLP header on TRGT1. The bits in this
address bus map directly to the address bits in the TLP header. The
third and fourth dwords of the header are mapped as follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. Then
radm_trgt1_addr[31:0] =Third dword (bytes 8-11). Therefore, bits
[7:0] are mapped to byte 11 which is the lowest eight bits of the TLP
header address. For more details, see the 'Endianness' advanced
information chapter.
■ MEM (64-bit) / MSG have a 4-dword header. Then
radm_trgt1_addr[63:32] =Third dword (bytes 8-11) and
radm_trgt1_addr[31:0] =Fourth dword (bytes 12-15). Therefore, bits
[7:0] are mapped to byte 15 which is the lowest eight bits of the TLP
header address. For more details, see the 'Endianness' advanced
information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_hdr_uppr_bytes[(ADDR_WIDT O The raw upper bytes in the received TLP header on TRGT1. The upper
H-1):0] bytes in the received TLP header on TRGT1. For a 3-dword header
these are bytes 8 to 11, for a 4-dword header they are bytes 8-15. When
radm_trgt1_hdr_uppr_bytes_valid is asserted, then
radm_trgt1_hdr_uppr_bytes has valid Msg data. These bytes of the TLP
header are mapped as follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. Then radm_trgt1_
hdr_uppr_bytes[31:0] = bytes 8-11. Therefore, bits [7:0] are mapped
to byte 8 of the TLP header.
■ MEM (64-bit) / MSG have a 4-dword header. Then radm_trgt1_
hdr_uppr_bytes[63:32] = bytes 12-15 and radm_trgt1_ hdr_uppr_-
bytes[31:0] = bytes 8-11. Therefore, bits [7:0] are mapped to byte 8
of the TLP header while bits 39-32 are mapped to byte 12, etc.
Note: For radm_trgt1_hdr_uppr_bytes[63:32] to exist,
FLT_Q_ADDR_WIDTH must have a value of 64. If 32<
FLT_Q_ADDR_WIDTH <64, then
radm_trgt1_hdr_uppr_bytes[FLT_Q_ADDR_WIDTH-1:32] =0; that is,
radm_trgt1_hdr_uppr_bytes[FLT_Q_ADDR_WIDTH-1:32] contains TLP
Header data only if FLT_Q_ADDR_WIDTH =64.
Your application can ensure FLT_Q_ADDR_WIDTH =64 by setting
VENDOR_MESSAGE_SUPPORT =1.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

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RTRGT1 Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

radm_trgt1_hdr_uppr_bytes_valid O Indicates that the transaction being presented on the TRGT1 interface
has been successfully translated in the iATU from a TLP received in the
PCIe controller. radm_trgt1_hdr_uppr_bytes has valid Msg data when
this signal is asserted.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
((CX_RADMQ_MODE==2)) && (CX_INTERNAL_ATU_ENABLE)
Synchronous To: None,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_cpl_status[2:0] O When the received TLP is a completion: completion Status field from the
header of a received completion TLP. When the received TLP is a
request: What the completion status for this request should be,
according to internal filtering rules.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted and completion is not in
bypass mode

radm_trgt1_bcm O Byte Count Modified (BCM) bit from the header of a received completion
TLP.
The BCM bit is not applicable for an endpoint device. However, the
controller does provide the value of the BCM bit radm_trgt1_bcm.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted and the completion is not in
bypass mode

radm_trgt1_byte_cnt[11:0] O Byte Count field from the header of a received completion TLP.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted and completion is not in
bypass mode

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PCI Express SW Controller Databook RTRGT1 Interface Signals

Port Name I/O Description

radm_trgt1_cpl_last O Reserved
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted and completion is not in
bypass mode

radm_trgt1_cmpltr_id[15:0] O Completer ID field from the header of a received completion TLP on


TRGT1.
■ [15:8]: Bus number
■ [7:3]: Device number
■ [2:0]: Function number
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted and completion is not in
bypass mode

radm_trgt1_vc[2:0] O Virtual Channel Number of a received completion TLP on TRGT1.


■ [2:0]: Virtual Channel number
Exists: (TRGT1_POPULATE) && ((CX_RADMQ_MODE==2))
Synchronous To: None,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted and completion is not in
bypass mode

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RTRGT1 Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

radm_grant_tlp_type[((NVC*3)-1):0] O Indicates that a particular VC and type transaction has been granted to
output from the receive queue. There is one bit for each TLP type for
each configured VC:
■ 0: Grant posted TLPs for VC0
■ 1: Grant non-posted TLPs for VC0
■ 2: Grant completion TLPs for VC0
■ 3: Grant posted TLPs for VC1
■ .......
■ up to the number of configured VCs.
This grant signal is a pulse. It is used together with trgt1_radm_pkt_halt
to control the amount of transactions that the controller's output queue
outputs.
Exists: ((AMBA_POPULATED==0 ||
CX_CCIX_INTERFACE_ENABLE==1)) && ((CX_RADMQ_MODE==2))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: The TLP type is in not in bypass mode

trgt1_radm_pkt_halt[((NVC*3)-1):0] I Halts the transfer of packets from individual queues. There is one bit of
trgt1_radm_pkt_halt for each TLP type for each configured VC:
■ 0: Halt posted TLPs for VC0
■ 1: Halt non-posted TLPs for VC0
■ 2: Halt completion TLPs for VC0
■ 3: Halt posted TLPs for VC1
■ up to the number of configured VCs.
For more details, see 'RTRGT1 Protocol Rules and Example
Transaction'.
Exists: ((AMBA_POPULATED==0 ||
CX_CCIX_INTERFACE_ENABLE==1)) && ((CX_RADMQ_MODE==2))
&& (TRGT1_POPULATE)
Synchronous To: aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: The TLP type is in not in bypass mode

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PCI Express SW Controller Databook RTRGT1 Interface Signals

Port Name I/O Description

radm_trgt1_atu_sloc_match[(ATU_IN_MIN O ATU Single Location match indication per ATU region. Set for 1 core_clk
1-1):0] period pulse when the ATU region matched a received VDM Single
Location Address translation.
Exists: ATU_IN_SINGLE_TRGT_ADDR_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

radm_trgt1_atu_cbuf_err[(ATU_IN_MIN1-1 O ATU Error indication per ATU region. Set for 1 core_clk period pulse
):0] when the ATU region matched received VDM size (payload + 3rd and
4th DW of Header) is greater than the programmed Circular Buffer
Increment size (CBUF_INCR) for Single Location Address translation.
Exists: ATU_IN_SINGLE_TRGT_ADDR_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted

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TRGT1_CCIX Interface Signals PCI Express SW Controller Databook

5.14 TRGT1_CCIX Interface Signals

ccix_radm_halt - - radm_ccix_dv
- radm_ccix_hv
- radm_ccix_data
- radm_ccix_hdr
- radm_ccix_dwen
- radm_ccix_eot
- radm_ccix_tlp_abort
- radm_ccix_dllp_abort

Table 5-14 TRGT1_CCIX Interface Signals

Port Name I/O Description

radm_ccix_dv O Indicates the data is valid in the CCIX receive data bus.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_ccix_hv O Indicates header is valid in the CCIX receive header bus.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_ccix_data[(TRGT_DATA_WD-1):0] O Data bus in the CCIX receive interface.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_ccix_dv is asserted

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PCI Express SW Controller Databook TRGT1_CCIX Interface Signals

Port Name I/O Description

radm_ccix_hdr[((CCIX_HDR_WD+CCIX_ O Header bus in the CCIX receive interface.


HDR_PROT_WD)-1):0] Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_ccix_hv is asserted

ccix_radm_halt I When asserted, this signal causes the controller to stop streaming
information in the CCIX receive interface.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: aux_clk_g,core_clk,{radm_clk_g}
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_ccix_dwen[(NW-1):0] O DWord enable for received CCIX data.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_ccix_dv is asserted

radm_ccix_eot O Signals the end of the TLP being delivered in the CCIX receive
interface.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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TRGT1_CCIX Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

radm_ccix_tlp_abort O Indication for the application to drop the TLP received in the CCIX
receive interface because of the malformed TLP or ECRC error.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: radm_ccix_hv, radm_ccix_eot

radm_ccix_dllp_abort O Indication for the application to drop the TLP received in the CCIX
receive interface because of the data link layer error such as LCRC.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: radm_ccix_eot

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PCI Express SW Controller Databook Clock and Reset (APM) Signals

5.15 Clock and Reset (APM) Signals

perst_n - - pm_req_sticky_rst
app_clk_req_n - - pm_req_core_rst
phy_clk_req_n - - pm_req_non_sticky_rst
ack_sticky_rst - - pm_sel_aux_clk
ack_core_rst - - pm_en_core_clk
ack_non_sticky_rst - - pm_req_phy_rst
ret_sticky_rst_n - - pm_req_retention_rst
ret_non_sticky_rst_n -
ret_core_rst_n -
ret_core_pl_rst_n -

Table 5-15 Clock and Reset (APM) Signals

Port Name I/O Description

perst_n I Indicates when the main power supply is within its tolerated voltage
range and is stable.
This signal is syncronized using aux_clk and can be driven/supplied
asynchronously to the controller in certain low-power modes.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

app_clk_req_n I Indicates that the application logic is ready to have reference clock
removed. In designs which support reference clock removal through
either L1 PM Sub-states or L1 CPM, the application should set this
signal to 1'b when it is ready to have reference clock removed. If the
application does not want to remove reference clock it should set this
signal to 1'b0.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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Clock and Reset (APM) Signals PCI Express SW Controller Databook

Port Name I/O Description

phy_clk_req_n I Acknowledge from the PHY that it is ready to have reference clock
removed. In designs that support L1 PM Sub-states or L1 CPM, there is
a handshake with the PHY prior to reference clock removal. This signal
should be connected to the acknoweldge signal from the PHY. If the
PHY does not want to remove the reference clock it should set this
signal to 1'b0.
This signal is syncronized using aux_clk and can be driven/supplied
asynchronously to the controller in certain low-power modes.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

pm_req_sticky_rst O Request from controller's PMC to the DWC_pcie_clkrst.v to assert the


sticky_rst_n input.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_req_core_rst O Request from controller's PMC to the DWC_pcie_clkrst.v to assert the


core_rst_n input.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_req_non_sticky_rst O Request from controller's PMC to the DWC_pcie_clkrst.v to assert the


non_sticky_rst_n input.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Clock and Reset (APM) Signals

Port Name I/O Description

pm_sel_aux_clk O This signal switches the source of aux_clk from core_clk to the low
speed clock.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_en_core_clk O This signal is used to gate off the core_clk in low power states.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_req_phy_rst O Request from controller's PMC to the DWC_pcie_clkrst.v to assert the


phy_rst_n input.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ack_sticky_rst I Acknowledgment from DWC_pcie_clkrst.v for the corresponding sticky


reset request. The sticky reset is applied by the clock and reset
generation logic.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ack_core_rst I Acknowledgment from DWC_pcie_clkrst.v for the corresponding


controller reset request. The controller reset is applied by the clock and
reset generation logic.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Clock and Reset (APM) Signals PCI Express SW Controller Databook

Port Name I/O Description

ack_non_sticky_rst I Acknowledgment from DWC_pcie_clkrst.v for the corresponding


non-sticky reset request. The non-sticky reset is applied by the clock
and reset generation logic.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_req_retention_rst O Request from controller's PMC to the DWC_pcie_clkrst.v to assert the


reset to modules containing L1 power gating retention registers. For
more details, see "Advanced Power Management and Power Domain
Gating" in the Power Management section, and the "Reset
Requirements" section in the Architecture chapter of the Databook.
Exists: CX_L1_PG_ENABLE
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ret_sticky_rst_n I Resets all sticky bit registers in the retention (L1 power gating) register
based modules of configuration register space. For more details, see
"Advanced Power Management and Power Domain Gating" in the
Power Management section, and the "Reset Requirements" section in
the Architecture chapter of the Databook.
Exists: CX_L1_PG_ENABLE
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

ret_non_sticky_rst_n I Resets all non-sticky bit registers in the retention (L1 power gating)
register based modules of configuration register space. For more
details, see "Advanced Power Management and Power Domain Gating"
in the Power Management section, and the "Reset Requirements"
section in the Architecture chapter of the Databook.
Exists: CX_L1_PG_ENABLE
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Clock and Reset (APM) Signals

Port Name I/O Description

ret_core_rst_n I Resets retention (L1 power gating) register based modules of the
controller logic. For more details, see "Advanced Power Management
and Power Domain Gating" in the Power Management section, and the
"Reset Requirements" section in the Architecture chapter of the
Databook. Asynchronous assertion with synchronous de-assertion.
Exists: CX_L1_PG_ENABLE
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

ret_core_pl_rst_n I Resets retention (L1 power gating) register based modules of the
controller logic for layer1. For more details, see "Advanced Power
Management and Power Domain Gating" in the Power Management
section, and the "Reset Requirements" section in the Architecture
chapter of the Databook. Asynchronous assertion with synchronous
de-assertion.
Exists: (CX_L1_PG_ENABLE) && (CX_FREQ_STEP_DL_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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Clock and Reset Signals PCI Express SW Controller Databook

5.16 Clock and Reset Signals

ret_pipe_clk - - en_aux_clk_g
ret_pipe_rst_n - - en_radm_clk_g
ret_core_clk_ug - - radm_idle
ret_core_pl_clk_ug - - training_rst_n
pipe_clk -
pipe_msgbus_rst_n -
cxs_clk -
cxs_rst_n -
core_clk -
ret_core_clk -
core_clk_ug -
core_pl_clk -
core_pl_clk_ug -
ret_core_pl_clk -
aux_clk -
aux_clk_g -
radm_clk_g -
pwr_rst_n -
sticky_rst_n -
non_sticky_rst_n -
core_rst_n -
pipe_rst_n -
core_pl_rst_n -
app_init_rst -
aux_clk_active -
slv_pwr_rst_n -
mstr_pwr_rst_n -
dbi_pwr_rst_n -

Table 5-16 Clock and Reset Signals

Port Name I/O Description

ret_pipe_clk I This clock is equivalent to pipe_clk but it is routed to modules being


retained in L1.2
Exists: ((CX_CPCIE_ENABLE)) && (CX_RET_PIPE_CLK_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ret_pipe_rst_n I Resets controller logic clocked on ret_pipe_clk. Reset logic should


assert ret_pipe_rst_n at same time as core_rst_n and deassert
synchronous to pipe_clk.
Exists: ((CX_CPCIE_ENABLE)) && (CX_RET_PIPE_CLK_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Clock and Reset Signals

Port Name I/O Description

ret_core_clk_ug I The ungated version of the primary clock input to the controller, for
modules retained during L1 power gating. The ret_core_clk_ug
frequency is the same as core_clk_ug.
Exists: ((CX_CPCIE_ENABLE)) && (CX_RET_CORE_CLK_UG_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ret_core_pl_clk_ug I The ungated version of the primary clock input to the controller for
physical layer, for modules retained during L1 power gating. The
ret_core_pl_clk_ug frequency is the same as core_pl_clk_ug.
Exists: ((CX_CPCIE_ENABLE)) &&
(CX_RET_CORE_PL_CLK_UG_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pipe_clk I PIPE clock from external PHY. Used by the controller to clock the PIPE.
The PHY TX PLL generates pipe_clk from the platform reference clock.
The PHY adapts and re-times RX data to pipe_clk. The PIPE clock rate
is 62.5 MHz, 125 MHz, 250 MHz, or 500 MHz, depending on datapath
configuration and symbol/datapath width at the PHY interface.
Exists: ((CX_CPCIE_ENABLE)) && (CX_FREQ_STEP_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pipe_msgbus_rst_n I Resets controller logic clocked on pipe_clk. Reset logic should assert
pipe_msgbus_rst_n at same time as phy_rst_n and deassert
synchronous to pipe_clk.
Exists: ((CX_CPCIE_ENABLE)) && (CX_PIPE51_SUPPORT)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Clock and Reset Signals PCI Express SW Controller Databook

Port Name I/O Description

cxs_clk I CXS Interface clock signal


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (!CX_CXS_SYNCHRONOUS)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cxs_rst_n I CXS Interface asynchronous active low reset signal


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (!CX_CXS_SYNCHRONOUS)
Synchronous To: None_as
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

core_clk I The gated version of the primary clock input to the controller. It is
assumed that all input signals except resets are synchronous to this
clock. Depending the controller configuration and Gen2/Gen3 mode, the
core_clk frequency is 62.5 MHz, 125 MHz, 250 MHz, or 500 MHz if
Base PCIe. You can gate this clock during the L1 and L2 low power
states.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ret_core_clk I The gated version of the primary clock input to the controller, for
modules retained during L1 power gating. The ret_core_clk frequency is
the same as core_clk. You can gate this clock during the L1 and L2 low
power states under the same conditions as core_clk.
Exists: CX_L1_PG_ENABLE
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Clock and Reset Signals

Port Name I/O Description

core_clk_ug I The ungated version of the primary clock input to the controller.
Depending the controller configuration and Gen2/Gen3 mode, the
core_clk_ug frequency is 62.5 MHz, 125 MHz, 250 MHz, or 500 MHz.
■ You must not gate this during the L1 and L2 low power states.
■ It is used in the PCIe controller to sample phy_mac_phystatus.
In Selectable PHY mode (M-PCIe), you must connect this signal to
core_clk.
Exists: (CX_S_CPCIE_MODE || CX_SEL_PHY_MODE )
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

core_pl_clk I The gated version of the primary clock input to the controller for physical
layer. It is assumed that all input signals except resets are synchronous
to this clock. Depending the controller configuration and Gen2/Gen3
mode, the core_clk frequency is 62.5 MHz, 125 MHz, 250 MHz, or 500
MHz if Base PCIe. You can gate this clock during the L1 and L2 low
power states.
Exists: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE )) &&
(CX_FREQ_STEP_DL_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

core_pl_clk_ug I The ungated version of the primary clock input to the controller for
physical layer. Depending the controller configuration and Gen2/Gen3
mode, the core_pl_clk_ug frequency is 62.5 MHz, 125 MHz, 250 MHz,
or 500 MHz.
■ You must not gate this during the L1 and L2 low power states.
■ It is used in the PCIe controller to sample phy_mac_phystatus.
In Selectable PHY mode (M-PCIe), you must connect this signal to
core_clk.
Exists: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE )) &&
(CX_FREQ_STEP_DL_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

ret_core_pl_clk I The gated version of the primary clock input to the controller for physical
layer, for modules retained during L1 power gating. The ret_core_pl_clk
frequency is the same as core_pl_clk. You can gate this clock during the
L1 and L2 low power states under the same conditions as core_plclk.
Exists: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE )) &&
(CX_FREQ_STEP_DL_EN) && (CX_L1_PG_ENABLE)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

aux_clk I Auxiliary clock to the PMC domain. The partitioning of the controller
enables some functions to operate aux_clk in certain power
management states. The PMC is partitioned to run aux_clk in L2 states,
if supported by your application. In normal operation, the aux_clk and
core_clk inputs are assumed to be equivalent and the physical design
implementation must assume they are the same in terms of clock tree
matching and skew. For power management enabled solutions, it is the
responsibility of your application designer to manage any clock
switching required to gate core_clk and switch aux_clk from the normal
operating frequency to the slower clock rate used in the low power
states.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

aux_clk_g I Gated version of aux_clk. Used in CDM.


Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

en_aux_clk_g O Enable signal used by DWC_pcie_clkrst.v to create aux_clk_g from


aux_clk.
Exists: Always
Synchronous To: None,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Clock and Reset Signals

Port Name I/O Description

radm_clk_g I Gated version of core_clk. Used in RADM.


Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

en_radm_clk_g O Enable signal used by DWC_pcie_clkrst.v to create radm_clk_g from


core_clk. The controller de-asserts the en_radm_clk_g output when
there is no Rx traffic, Rx queues and pre/post-queue pipelines are
empty, RADM completion LUT is empty, and there are no FLR actions
pending. You must set the RADM_CLK_GATING_EN field in the
CLOCK_GATING_CTRL_OFF register to enable this functionality;
otherwise the en_radm_clk_g output is always set to '1'.
Exists: Always
Synchronous To: aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_idle O RADM activity status signal. The controller creates the en_radm_clk_g
output by gating this signal with the output of the
RADM_CLK_GATING_EN field in the CLOCK_GATING_CTRL_OFF
register. For debug purposes only.
Exists: Always
Synchronous To: aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pwr_rst_n I Resets the PMC module. The pwr_rst_n signal is used as the 'cold
reset' applied to the controller power-up. It must be asserted
(asynchronously) following your application of auxiliary power or
following your application of main power if auxiliary power is not
available to the device. The pwr_rst_n input resets all registers in the
aux_clk domain, including sticky bits. It must be de-asserted
synchronously.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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Clock and Reset Signals PCI Express SW Controller Databook

Port Name I/O Description

sticky_rst_n I Resets all sticky bit registers in the configuration register space.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

non_sticky_rst_n I Resets all non-sticky bit registers in the configuration register space.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

core_rst_n I Resets the controller, except for the PMC module. Upon initial power-up,
core_rst_n is asserted in order to reset the non-auxiliary power domain
logic. Reset logic should assert core_rst_n whenever link_req_rst_not is
transitioned from high to low. It is recommended that you reset your
application logic together with the controller. Asynchronous assertion
with synchronous de-assertion.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

pipe_rst_n I Resets controller logic clocked on pipe_clk. Reset logic should assert
pipe_rst_n at same time as core_rst_n and deassert synchronous to
pipe_clk.
Exists: CX_FREQ_STEP_EN
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Clock and Reset Signals

Port Name I/O Description

core_pl_rst_n I Resets the controller, except for the PMC module. Upon initial power-up,
core_rst_n is asserted in order to reset the non-auxiliary power domain
logic. Reset logic should assert core_pl_rst_n whenever
link_req_rst_not is transitioned from high to low. It is recommended that
you reset your application logic together with the controller.
Asynchronous assertion with synchronous de-assertion.
Exists: CX_FREQ_STEP_DL_EN
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

app_init_rst I Request from your application to send a hot reset to the upstream port.
The hot reset request is sent when a single cycle pulse is applied to this
pin. In an upstream port, you should set this input to '0'.
Note: This signal is not used by the controller to set the SBR field in the
BRIDGE_CTRL_INT_PIN_INT_LINE_REG register. During the
transition from DL_Active to DL_inactive, assertion of app_init_rst signal
indicates a Surprise Down Error, but setting of SBR field in the
BRIDGE_CTRL_INT_PIN_INT_LINE_REG register through DBI does
not trigger a Surprise Down Error.
Exists: Always
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

training_rst_n O Hot reset from upstream component. When the controller LTSSM
receives two consecutive TS1 ordered sets with the hot_reset bit
asserted, it asserts training_rst_n for one clock cycle. This signal is only
kept for legacy purposes. You should use the link_req_rst_not signal to
reset the controller after a 'hot reset' request. For details hot reset, see
'Generating and Processing Hot Resets (Training Resets)' in the
Databook.
Exists: Always
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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Clock and Reset Signals PCI Express SW Controller Databook

Port Name I/O Description

aux_clk_active I Indicates that your external clock logic has switched the aux_clk input
from pipe_clk to the platform auxiliary clock.
Exists: Always
Synchronous To: aux_clk_g,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

slv_pwr_rst_n I pwr_rst_n signal de-asserted synchronous to the slv_aclk


Exists: CX_SLV_ISO_EN
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

mstr_pwr_rst_n I pwr_rst_n signal de-asserted synchronous to the mstr_aclk


Exists: CX_MSTR_ISO_EN
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

dbi_pwr_rst_n I pwr_rst_n signal de-asserted synchronous to the dbi_aclk


Exists: CX_DBI_ISO_EN
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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PCI Express SW Controller Databook DBI Interface Signals

5.17 DBI Interface Signals

dbi_addr - - lbc_dbi_ack
dbi_din - - lbc_dbi_dout
dbi_cs -
dbi_cs2 -
dbi_wr -

Table 5-17 DBI Interface Signals

Port Name I/O Description

dbi_addr[31:0] I Address of the configuration register for the current DBI access:
■ [31:19]: Not used
■ [18:16]: Function number
■ [15:12]: Not used
■ [11:2]: Register address, must be dword-aligned.
■ [1]: Not used
■ [0]: Target of DBI access: 0 to access internal register; 1 to access
external register the ELBI
You can use an address larger than 12 bits dbi_addr when you access
the ELBI interface instead of the Configuration Registers. You can use
up to 32 bits if the controller has been configured for a 32-bit ELBI
address width with the parameter CX_LBC_EXT_AW. For more details,
see 'Local Bus Controller (LBC) and Data Bus Interface (DBI)'.
Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: dbi_cs is asserted

dbi_din[31:0] I Write data bus to the selected configuration register.


Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: dbi_cs is asserted

dbi_cs I Chip select input to access the CDM or ELBI.


Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: aux_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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DBI Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

dbi_cs2 I Additional chip select that enables writing to BAR mask registers. To
write to a BAR mask register, your application must assert dbi_cs2 in
addition to dbi_cs.
Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: dbi_cs is asserted

dbi_wr[3:0] I Indicates the configuration register access type (read or write). For
writes, dbi_wr also indicates the byte enables:
■ 0000b: Read
■ 0001b: Write byte 0
■ 0010b: Write byte 1
■ 0100b: Write byte 2
■ 1000b: Write byte 3
■ 1111b: Write all bytes
Combinations of byte enables (for example, 0101b) are also valid.
Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: dbi_cs is asserted

lbc_dbi_ack O Indicates that the requested read or write operation to the selected
configuration register is complete. When accessing a non-existent or
Read-Only register, the signal is asserted for one clock cycle, and not
two cycles.
Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

lbc_dbi_dout[31:0] O Read data bus from the selected configuration register.


Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_dbi_ack is asserted

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PCI Express SW Controller Databook ELBI Interface Signals

5.18 ELBI Interface Signals

ext_lbc_ack - - lbc_ext_addr
ext_lbc_din - - lbc_ext_dout
- lbc_ext_cs
- lbc_ext_wr
- lbc_ext_rom_access
- lbc_ext_io_access
- lbc_ext_bar_num

Table 5-18 ELBI Interface Signals

Port Name I/O Description

ext_lbc_ack[(NF-1):0] I Indicates that the requested read or write operation to an external


register block is complete. There is no time interval requirement
between the request (when lbc_ext_cs is asserted) and the
acknowledgement (when ext_lbc_ack is asserted). However, to avoid a
lockup condition in the event that the register block never asserts
ext_lbc_ack, the external logic can implement a timeout mechanism.
The width of the ext_lbc_ack signal is equal to the number of functions
in your controller configuration (CX_NFUNC). That is, there is one
ext_lbc_ack bit for each configured function. This signal should never be
hard-wired to 1'b1, even if the ELBI is not being used. This signal should
only be high in response to lbc_ext_cs being asserted. Your application
must assert ext_lbc_ack for two clock cycles, except for an error
response (accessing a non-existent register or writing to a read-only
register), when ext_lbc_ack must be asserted for one clock cycle.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted.

ext_lbc_din[(((CX_LBC_NW*32)*NF)-1):0] I Data bus from the external register block. Depending on value of
CX_LBC_NW, there are 32/64/128 bits of ext_lbc_din for each function
in your controller configuration.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ext_lbc_ack is asserted

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ELBI Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

lbc_ext_addr[(LBC_EXT_AW-1):0] O Address bus to the external register block. The width of the address bus
is the value you select for the CX_LBC_EXT_AW parameter.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted

lbc_ext_dout[((CX_LBC_NW*32)-1):0] O Write data bus to the external register block, driven to all functions in a
multi-function configuration.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted

lbc_ext_cs[(NF-1):0] O The controller asserts lbc_ext_cs when a received TLP for a read or
write request has an address in the range of your application device, as
determined by the BAR configuration. The width of the lbc_ext_cs signal
is equal to the number of functions in your controller configuration
(CX_NFUNC). That is, there is one lbc_ext_cs bit for each configured
function. The controller de-asserts lbc_ext_cs only after the external
register block acknowledges completion of the access by asserting the
corresponding bit of ext_lbc_ack.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook ELBI Interface Signals

Port Name I/O Description

lbc_ext_wr[((4*CX_LBC_NW)-1):0] O Indicates when the external register access is a read or a write. For
writes, lbc_ext_wr also indicates the byte enables.
When CX_LBC_NW = 1:
■ 0000b: Read
■ 0001b: Write byte 0
■ 0010b: Write byte 1
■ 0100b: Write byte 2
■ 1000b: Write byte 3
■ 1111b: Write all bytes

When CX_LBC_NW = 2:
■ 00000000b: Read
■ 00000001b: Write byte 0
■ 00000010b: Write byte 1
■ 00000100b: Write byte 2
■ 00001000b: Write byte 3
■ 00010000b: Write byte 4
■ 00100000b: Write byte 5
■ 01000000b: Write byte 6
■ 10000000b: Write byte 7
■ 11111111b: Write all bytes
Combinations of byte enables (for example, 0011b) are also valid.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted

lbc_ext_rom_access O Indicates that the current ELBI access is for expansion ROM.
Exists: Always
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted

lbc_ext_io_access O Indicates that the current ELBI access is an I/O access.


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted

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ELBI Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

lbc_ext_bar_num[2:0] O The BAR number of the current ELBI access:


■ 000b: BAR 0
■ 001b: BAR 1
■ 010b: BAR 2
■ 011b: BAR 3
■ 100b: BAR 4
■ 101b: BAR 5
■ 110b is not used.
■ 111b is used to indicate a configuration access. This is designed for
an application with application-specific configuration registers such
as vendor capability. lbc_ext_bar_num is set to 3'b111 for all DBI
accesses.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted

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PCI Express SW Controller Databook CXS Rx FIFO RAM Signals

5.19 CXS Rx FIFO RAM Signals

cxs_rxram_doutb - - cxs_rxram_ena
- cxs_rxram_wea
- cxs_rxram_addra
- cxs_rxram_dina
- cxs_rxram_enb
- cxs_rxram_addrb
- cxs_rxram_addra_par
- cxs_rxram_addrb_par

Table 5-19 CXS Rx FIFO RAM Signals

Port Name I/O Description

cxs_rxram_ena O Port A Enable of CXS Receiver Buffer RAM.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cxs_rxram_wea O Port B Write Enable of CXS Receiver Buffer RAM.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: cxs_rxram_ena is asserted

cxs_rxram_addra[(CXS_RX_BUFF_ADDR O Port A Write Address of CXS Receiver Buffer.


W-1):0] Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: core_clk
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_rxram_ena and cxs_rxram_wea are asserted

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CXS Rx FIFO RAM Signals PCI Express SW Controller Databook

Port Name I/O Description

cxs_rxram_dina[(CXS_RX_BUFF_DATAW O Port A Write Data of CXS Receiver Buffer.


-1):0] Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: core_clk
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_rxram_ena and cxs_rxram_wea are asserted

cxs_rxram_enb O Port B Enable of CXS Receiver Buffer RAM.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cxs_rxram_addrb[(CXS_RX_BUFF_ADDR O Port B Read Address of CXS Receiver Buffer RAM.


W-1):0] Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: core_clk
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_rxram_enb is asserted

cxs_rxram_doutb[(CXS_RX_BUFF_DATA I Port B Read Data of CXS Receiver Buffer RAM.


W-1):0] Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: aux_clk,{core_clk}
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_rxram_enb is asserted

cxs_rxram_addra_par O Write Address Parity of CXS Receiver Buffer RAM.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_rxram_ena and cxs_rxram_wea are asserted

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PCI Express SW Controller Databook CXS Rx FIFO RAM Signals

Port Name I/O Description

cxs_rxram_addrb_par O Read Address Parity of CXS Receiver Buffer RAM.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_rxram_enb is asserted

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CXS Tx FIFO RAM Signals PCI Express SW Controller Databook

5.20 CXS Tx FIFO RAM Signals

cxs_txram_doutb - - cxs_txram_ena
- cxs_txram_wea
- cxs_txram_addra
- cxs_txram_dina
- cxs_txram_enb
- cxs_txram_addrb
- cxs_txram_addra_par
- cxs_txram_addrb_par

Table 5-20 CXS Tx FIFO RAM Signals

Port Name I/O Description

cxs_txram_ena O Port A Enable of CXS Transmitter Buffer RAM.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cxs_txram_wea O Port B Write Enable of CXS Transmitter Buffer RAM.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: cxs_txram_ena is asserted

cxs_txram_addra[(CXS_TX_BUFF_ADDR O Port A Write Address of CXS Transmitter Buffer.


W-1):0] Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: core_clk
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_txram_ena and cxs_txram_wea are asserted

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PCI Express SW Controller Databook CXS Tx FIFO RAM Signals

Port Name I/O Description

cxs_txram_dina[(CXS_TX_BUFF_DATAW- O Port A Write Data of CXS Transmitter Buffer.


1):0] Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_txram_ena and cxs_txram_wea are asserted

cxs_txram_enb O Port B Enable of CXS Transmitter Buffer RAM.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cxs_txram_addrb[(CXS_TX_BUFF_ADDR O Port B Read Address of CXS Transmitter Buffer RAM.


W-1):0] Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: core_clk
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_txram_enb is asserted

cxs_txram_doutb[(CXS_TX_BUFF_DATA I Port B Read Data of CXS Transmitter Buffer RAM.


W-1):0] Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_txram_enb is asserted

cxs_txram_addra_par O Write Address Parity of CXS Transmitter Buffer RAM.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_txram_ena and cxs_txram_wea are asserted

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CXS Tx FIFO RAM Signals PCI Express SW Controller Databook

Port Name I/O Description

cxs_txram_addrb_par O Read Address Parity of CXS Transmitter Buffer RAM.


Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE) && (CX_RAM_AT_TOP_IF) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxs_txram_enb is asserted

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PCI Express SW Controller Databook Receive Data Queue RAM Signals

5.21 Receive Data Queue RAM Signals

p_dataq_dataout - - p_dataq_addra
- p_dataq_addrb
- p_dataq_addra_par
- p_dataq_addrb_par
- p_dataq_err_synd
- p_dataq_err_addr
- p_dataq_ce
- p_dataq_ue
- p_dataq_datain
- p_dataq_ena
- p_dataq_enb
- p_dataq_wea

Table 5-21 Receive Data Queue RAM Signals

Port Name I/O Description

p_dataq_dataout[(RADM_Q_DATABITS_O I Read data from port B of the data queue buffer. The width of the read
-1):0] data bus is automatically set according to the datapath width and
number of VCs, as follows:
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_dataq_enb is asserted

p_dataq_addra[(RADM_PQ_D_ADDRBIT O Address to port A of the data queue buffer.


S-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_dataq_ena or p_dataq_wea is asserted

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Receive Data Queue RAM Signals PCI Express SW Controller Databook

Port Name I/O Description

p_dataq_addrb[(RADM_PQ_D_ADDRBIT O Address to port B of the data queue buffer. The width is the same as the
S-1):0] p_dataq_addra width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_dataq_enb is asserted

p_dataq_addra_par[(NDQ-1):0] O Parity for address to port A of the data queue buffer.


Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

p_dataq_addrb_par[(NDQ-1):0] O Parity for address to port B of the data queue buffer.


Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Receive Data Queue RAM Signals

Port Name I/O Description

p_dataq_err_synd[((NDQ*RASDP_DATAQ O Error syndrome from data queue RAM


_ERR_SYND_WD)-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

p_dataq_err_addr[(RADM_PQ_D_ADDRB O Error address from data queue RAM


ITS-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

p_dataq_ce[(NDQ-1):0] O Corrected error indication from data queue RAM


Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Receive Data Queue RAM Signals PCI Express SW Controller Databook

Port Name I/O Description

p_dataq_ue[(NDQ-1):0] O Uncorrectable error indication from data queue RAM


Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

p_dataq_datain[(RADM_Q_DATABITS-1): O Write data to port A of the data queue buffer. The width is the same as
0] the p_dataq_dataout width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: None,aux_clk_g,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_dataq_wea is asserted

p_dataq_ena[(RADM_Q_D_CTRLBITS-1): O Port A select to the data queue buffer. The controller asserts this at the
0] same time as p_dataq_wea.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Receive Data Queue RAM Signals

Port Name I/O Description

p_dataq_enb[(RADM_Q_D_CTRLBITS-1): O Port B read enable to the data queue buffer. Always '1' even when the
0] read port is idle.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

p_dataq_wea[(RADM_Q_D_CTRLBITS-1) O Port A write enable to the data queue buffer.


:0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Receive Formation Queue RAM Signals PCI Express SW Controller Databook

5.22 Receive Formation Queue RAM Signals

formqram_radm_doutb - - radm_formqram_addra
- radm_formqram_addra_par
- radm_formqram_ena
- radm_formqram_wea
- radm_formqram_dina
- radm_formqram_addrb
- radm_formqram_addrb_par
- radm_formqram_enb
- radm_formqram_err_addr
- radm_formqram_err_synd
- radm_formqram_ce
- radm_formqram_ue

Table 5-22 Receive Formation Queue RAM Signals

Port Name I/O Description

radm_formqram_addra[((NQW*RAM_PW) O Address buses to port A (write port) of the formation queue RAMs,
-1):0] concatenated from RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_ena or radm_formqram_wea is asserted

radm_formqram_addra_par[(NQW-1):0] O Parity bit for address buses to port A (write port) of the formation queue
RAMs, concatenated from RAM 0 to RAM
CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_ena or radm_formqram_wea is asserted

radm_formqram_ena[(NQW-1):0] O Port A selects to the formation queue RAMs, concatenated from RAM 0
to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Receive Formation Queue RAM Signals

Port Name I/O Description

radm_formqram_wea[(NQW-1):0] O Port A write enables to the formation queue RAMs, concatenated from
RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_formqram_dina[((NQW*RAM_WD)- O Write data to port A of the formation queue RAMs, concatenated from
1):0] RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_wea is asserted

radm_formqram_addrb[((NQW*RAM_PW) O Address buses to port B (read port) of the formation queue RAMs,
-1):0] concatenated from RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted

radm_formqram_addrb_par[(NQW-1):0] O Parity bit for address buses to port B (read port) of the formation queue
RAMs, concatenated from RAM 0 to RAM
CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted

radm_formqram_enb[(NQW-1):0] O Port B selects to the formation queue RAMs, concatenated from RAM 0
to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Receive Formation Queue RAM Signals PCI Express SW Controller Databook

Port Name I/O Description

formqram_radm_doutb[((NQW*RAM_WD) I Read data from port B of the formation queue RAMs, concatenated
-1):0] from RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted

radm_formqram_err_addr[((NQW*RAM_P O Logged error address buses to port B (read port) of the formation queue
W)-1):0] RAMs, concatenated from RAM 0 to RAM
CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted

radm_formqram_err_synd[((NQW*RASDP O Error syndrome for radm formation queue RAMs, concatenated from
_FORMQ_ERR_SYND_WD)-1):0] RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted

radm_formqram_ce[(NQW-1):0] O Corrected error indication from radm formation queue RAMs,


concatenated from RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted

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PCI Express SW Controller Databook Receive Formation Queue RAM Signals

Port Name I/O Description

radm_formqram_ue[(NQW-1):0] O Uncorrectable error indication from radm formation queue RAMs,


concatenated from RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted

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Receive Header Queue RAM Signals PCI Express SW Controller Databook

5.23 Receive Header Queue RAM Signals

p_hdrq_dataout - - p_hdrq_addra
- p_hdrq_addrb
- p_hdrq_addra_par
- p_hdrq_addrb_par
- p_hdrq_err_synd
- p_hdrq_err_addr
- p_hdrq_ce
- p_hdrq_ue
- p_hdrq_datain
- p_hdrq_ena
- p_hdrq_enb
- p_hdrq_wea

Table 5-23 Receive Header Queue RAM Signals

Port Name I/O Description

p_hdrq_dataout[(RADM_PQ_H_DATABIT I Read data from port B of the header queue buffer.


S_O-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_hdrq_enb is asserted

p_hdrq_addra[(RADM_PQ_H_ADDRBITS O Address to port A of the header queue buffer.


-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_hdrq_ena or p_hdrq_wea is asserted

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PCI Express SW Controller Databook Receive Header Queue RAM Signals

Port Name I/O Description

p_hdrq_addrb[(RADM_PQ_H_ADDRBITS O Address to port B of the header queue buffer. The width is the same as
-1):0] the p_hdrq_addra width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_hdrq_enb is asserted

p_hdrq_addra_par[(NHQ-1):0] O Parity for address to port A of the header queue buffer


Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

p_hdrq_addrb_par[(NHQ-1):0] O Parity for address to port B of the header queue buffer


Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

p_hdrq_err_synd[(RASDP_HDRQ_ERR_ O Error syndrome from header queue RAM


SYND_WD-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

p_hdrq_err_addr[(RADM_SBUF_HDRQ_ O Error address from header queue RAM


ERR_ADDR_WD-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

p_hdrq_ce[(NHQ-1):0] O Corrected error indication from header queue RAM


Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Receive Header Queue RAM Signals

Port Name I/O Description

p_hdrq_ue[(NHQ-1):0] O Uncorrectable error indication from header queue RAM


Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

p_hdrq_datain[(RADM_PQ_H_DATABITS- O Write data to port A of the header queue buffer. The width is the same
1):0] as the p_hdrq_dataout width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: None,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_hdrq_wea is asserted

p_hdrq_ena[(RADM_Q_H_CTRLBITS-1): O Port A select to the header queue buffer. The controller asserts this at
0] the same time as p_hdrq_wea.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

p_hdrq_enb[(RADM_Q_H_CTRLBITS-1): O Port B read enable to the header queue buffer. Always '1' even when the
0] read port is idle.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

p_hdrq_wea[(RADM_Q_H_CTRLBITS-1): O Port A write enable to the header queue buffer.


0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Transmit Retry Buffer RAM Signals

5.24 Transmit Retry Buffer RAM Signals

retryram_xdlh_data - - xdlh_retryram_addr
- xdlh_retryram_addr_par
- xdlh_retryram_err_synd
- xdlh_retryram_err_addr
- xdlh_retryram_ce
- xdlh_retryram_ue
- xdlh_retryram_data
- xdlh_retryram_we
- xdlh_retryram_en
- xdlh_retrysotram_err_synd
- xdlh_retrysotram_err_addr
- xdlh_retrysotram_ce
- xdlh_retrysotram_ue

Table 5-24 Transmit Retry Buffer RAM Signals

Port Name I/O Description

xdlh_retryram_addr[(RBUF_PW-1):0] O Address to the retry buffer RAM. The width of the address bus
(RBUF_PW) is automatically set as a function of the retry buffer depth,
which is automatically calculated, or set explicitly by you if you disable
autosizing.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: xdlh_retryram_we or xdlh_retryram_en is asserted

xdlh_retryram_addr_par O parity bit of Address to the retry buffer RAM.


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: xdlh_retryram_we or xdlh_retryram_en is asserted

xdlh_retryram_err_synd[(RASDP_RBUF_ O Error syndrome from retry RAM


ERR_SYND_WD-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: xdlh_retryram_we or xdlh_retryram_en is asserted

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Port Name I/O Description

xdlh_retryram_err_addr[(RBUF_PW-1):0] O Retry RAM address where a protection error has been detected
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: xdlh_retryram_ce or xdlh_retryram_ue is asserted

xdlh_retryram_ce O Corrected error indication from retry RAM


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xdlh_retryram_ue O Uncorrectable error indication from retry RAM


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xdlh_retryram_data[(RBUF_WIDTH-1):0] O Write data to the retry buffer RAM.


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: None,aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: xdlh_retryram_we is asserted

xdlh_retryram_we O Write enable to the retry buffer RAM.


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Transmit Retry Buffer RAM Signals

Port Name I/O Description

xdlh_retryram_en O Chip enable to the retry buffer RAM.


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

retryram_xdlh_data[(RBUF_WIDTH-1):0] I Read data from the retry buffer RAM. The width is the same as the
xdlh_retryram_data width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xdlh_retrysotram_err_synd[(RASDP_SOT O Error syndrome from retry SOT RAM


BUF_ERR_SYND_WD-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: xdlh_retrysotram_we or xdlh_retrysotram_en is asserted

xdlh_retrysotram_err_addr[(SOTBUF_PW- O Retry SOT RAM address where a protection error has been detected
1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: xdlh_retrysotram_ce or xdlh_retrysotram_ue is asserted

xdlh_retrysotram_ce O Corrected error indication from retry SOT RAM


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

xdlh_retrysotram_ue O Uncorrectable error indication from retry SOT RAM


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Transmit Retry SOT Buffer RAM Signals

5.25 Transmit Retry SOT Buffer RAM Signals

retrysotram_xdlh_data - - xdlh_retrysotram_waddr
- xdlh_retrysotram_raddr
- xdlh_retrysotram_waddr_par
- xdlh_retrysotram_raddr_par
- xdlh_retrysotram_data
- xdlh_retrysotram_we
- xdlh_retrysotram_en

Table 5-25 Transmit Retry SOT Buffer RAM Signals

Port Name I/O Description

xdlh_retrysotram_waddr[(SOTBUF_PW-1) O Write address for the SOT buffer RAM. The width of the address bus
:0] (SOTBUF_PW) is automatically set as a function of the SOT buffer
depth, which is automatically calculated.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: xdlh_retrysotram_we is asserted

xdlh_retrysotram_raddr[(SOTBUF_PW-1): O Read address for the SOT buffer RAM. The width of the address bus
0] (SOTBUF_PW) is automatically set as a function of the SOT buffer
depth, which is automatically calculated.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: xdlh_retrysotram_en is asserted

xdlh_retrysotram_waddr_par O Parity for SOT buffer RAM write address.


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

xdlh_retrysotram_raddr_par O Parity for SOT buffer RAM read address.


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xdlh_retrysotram_data[(SOTBUF_WD-1):0 O Write data to the SOT buffer RAM. The width of the write data bus is
] automatically set to the width of the retry buffer address bus. (Each
location in the SOT buffer is used to store a retry buffer address.)
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: None,aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: xdlh_retrysotram_we is asserted

xdlh_retrysotram_we O Write enable to the SOT buffer RAM.


Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xdlh_retrysotram_en O Read enable to the SOT buffer RAM. The controller asserts the SOT
buffer enable when replay is in progress and SOT read data is required.
This signal is low when the SOT buffer is not accessed, thus saving
power.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

retrysotram_xdlh_data[(SOTBUF_WD-1):0 I Read data from the SOT buffer RAM. The width is the same as the
] xdlh_retrysotram_data width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook MSI Interface Signals

5.26 MSI Interface Signals

ven_msi_req - - ven_msi_grant
ven_msi_func_num - - cfg_msi_en
ven_msi_tc - - cfg_msi_mask
ven_msi_vector - - cfg_msi_addr
cfg_msi_pending - - cfg_msi_data
- cfg_msi_64
- cfg_multi_msi_en
- cfg_msi_ext_data_en

Table 5-26 MSI Interface Signals

Port Name I/O Description

ven_msi_req I Request from your application to send an MSI when MSI is enabled.
When MSI-X is enabled instead of MSI, assertion of ven_msi_req
causes the controller to generate an MSI-X message. Once asserted,
ven_msi_req must remain asserted until the controller asserts
ven_msi_grant.
Exists: Always
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ven_msi_func_num[(PF_WD-1):0] I The function number of the MSI request. Function numbering starts at
'0'.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msi_req is asserted

ven_msi_tc[2:0] I Traffic Class of the MSI request, valid when ven_msi_req is asserted.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msi_req is asserted

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MSI Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

ven_msi_vector[4:0] I Used to modulate the lower five bits of the MSI Data register when
multiple message mode is enabled.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msi_req is asserted. Valid only when multiple
message mode is enabled for the device through the MSI Control
register.

ven_msi_grant O One-cycle pulse that indicates that the controller has accepted the
request to send an MSI. After asserting ven_msi_grant for one cycle,
the controller does not wait for ven_msi_req to be de-asserted then
reasserted to generate another MSI. When ven_msi_req remains
asserted after the controller asserts ven_msi_grant for one cycle, the
controller generates another MSI.
Exists: Always
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_msi_en[(NF-1):0] O Indicates that MSI is enabled (INTx message is not sent), one bit per
configured function.
Exists: Always
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_msi_mask[((32*NF)-1):0] O Contents of the Per Vector Mask register in the MSI Capability structure.
For each bit that is set, the function is prohibited from sending the
associated message.
Exists: MSI_PVM_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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PCI Express SW Controller Databook MSI Interface Signals

Port Name I/O Description

cfg_msi_pending[((32*NF)-1):0] I Indication from application about which functions have a pending


associated message. Used to determine the value of the Vector
Interrupt Pending register in the MSI Capability structure.
Exists: MSI_PVM_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

cfg_msi_addr[((64*NF)-1):0] O Contents of the MSI Lower 32 Bits and Upper 32 Bits Address registers
in the MSI Capability structure. There are 64 bits of cfg_msi_addr for
each configured function.
Exists: MSI_IO
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_msi_data[((32*NF)-1):0] O Contents of the MSI Data register in the MSI Capability structure. There
are 32 bits of cfg_msi_data for each configured function.
Exists: MSI_IO
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_msi_64[(NF-1):0] O The 64-bit Address Capable bit of the MSI Control register in the MSI
Capability structure, one bit for each configured function.
Exists: MSI_IO
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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MSI Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

cfg_multi_msi_en[((3*NF)-1):0] O The Multiple Message Enabled field of the MSI Control register in the
MSI Capability structure. There are 3 bits of cfg_multi_msi_en for each
configured function.
Exists: MSI_IO
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_msi_ext_data_en[(NF-1):0] O Indicates to application if extended message data for MSI is enabled or


not for each physical function.
Exists: MSI_IO
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook MSI-X Interface Signals

5.27 MSI-X Interface Signals

msix_addr - - cfg_msix_en
msix_data - - cfg_msix_func_mask
- cfg_msix_table_size
- cfg_msix_table_bir
- cfg_msix_table_offset
- cfg_msix_pba_bir
- cfg_msix_pba_offset

Table 5-27 MSI-X Interface Signals

Port Name I/O Description

msix_addr[63:0] I The address value for the MSI-X.


Exists: (MSIX_CAP_ENABLE) && (!MSIX_TABLE_EN)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msi_req is asserted

msix_data[31:0] I The data value for the MSI-X.


Exists: (MSIX_CAP_ENABLE) && (!MSIX_TABLE_EN)
Synchronous To: core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msi_req is asserted

cfg_msix_en[(NF-1):0] O The MSI-X Enable bit of the MSI-X Control register in the MSI-X
Capability structure. There is 1 bit of cfg_msix_en for each configured
function.
Exists: (MSIX_CAP_ENABLE) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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MSI-X Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

cfg_msix_func_mask[(NF-1):0] O The function Mask bit of the MSI-X Control register in the MSI-X
Capability structure. There is 1 bit of cfg_msix_func_mask for each
configured function.
Exists: (MSIX_CAP_ENABLE) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_msix_table_size[((11*NF)-1):0] O The MSI-X Table Size field of the MSI-X Control register in the MSI-X
Capability structure. There are 11 bits of cfg_msix_table_size for each
configured function.
Exists: (MSIX_CAP_ENABLE) && (MSIX_IO) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_msix_table_bir[((3*NF)-1):0] O Table BAR Indicator Register (BIR) field of the MSI-X Table Offset and
BIR register in the MSI-X Capability structure. There are 3 bits of
cfg_msix_table_bir for each configured function.
Exists: (MSIX_CAP_ENABLE) && (MSIX_IO) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_msix_table_offset[((29*NF)-1):0] O Table Offset field of the MSI-X Table Offset and BIR register in the
MSI-X Capability structure. There are 29 bits of cfg_msix_table_offset
for each configured function.
Exists: (MSIX_CAP_ENABLE) && (MSIX_IO) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook MSI-X Interface Signals

Port Name I/O Description

cfg_msix_pba_bir[((3*NF)-1):0] O PBA BIR field of the MSI-X PBA Offset and BIR register in the MSI-X
Capability structure. There are 3 bits of cfg_msix_pba_bir for each
configured function.
Exists: (MSIX_CAP_ENABLE) && (MSIX_IO) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_msix_pba_offset[((29*NF)-1):0] O PBA Offset field of the MSI-X PBA Offset and BIR register in the MSI-X
Capability structure. There are 29 bits of cfg_msix_pba_offset for each
configured function.
Exists: (MSIX_CAP_ENABLE) && (MSIX_IO) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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VMI Signals PCI Express SW Controller Databook

5.28 VMI Signals

ven_msg_fmt - - ven_msg_grant
ven_msg_type -
ven_msg_tc -
ven_msg_td -
ven_msg_ep -
ven_msg_attr -
ven_msg_len -
ven_msg_func_num -
ven_msg_tag -
ven_msg_code -
ven_msg_data -
ven_msg_req -

Table 5-28 VMI Signals

Port Name I/O Description

ven_msg_fmt[1:0] I The Format field for the vendor-defined Message TLP. Should be set to
0x1.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

ven_msg_type[4:0] I The Type field for the vendor-defined Message TLP.


Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

ven_msg_tc[2:0] I The Traffic Class field for the vendor-defined Message TLP.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

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PCI Express SW Controller Databook VMI Signals

Port Name I/O Description

ven_msg_td I The TLP Digest (TD) bit for the vendor-defined Message TLP, valid
when ven_msg_req is asserted.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

ven_msg_ep I The Poisoned TLP (EP) bit for the vendor-defined Message TLP.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

ven_msg_attr[(ATTR_WD-1):0] I The Attributes field for the vendor-defined Message TLP.


Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

ven_msg_len[9:0] I The Length field for the vendor-defined Message TLP (indicates length
of data payload in dwords).
Should be set to 0x0.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

ven_msg_func_num[(PF_WD-1):0] I Function Number for the vendor-defined Message TLP. Function


numbering starts at '0'.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

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VMI Signals PCI Express SW Controller Databook

Port Name I/O Description

ven_msg_tag[(TAG_SIZE-1):0] I Tag for the vendor-defined Message TLP.


Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

ven_msg_code[7:0] I The Message Code for the vendor-defined Message TLP.


Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

ven_msg_data[63:0] I Third and fourth dwords of the Vendor Defined Message header where:
■ Bytes 8-11 (third header dword) =ven_msg_data[63:32]
■ Bytes 12-15 (fourth header dword) =ven_msg_data[31:0], where
ven_msg_data[7:0] =byte 15
For more details, see the 'Endianness' advanced information chapter.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted

ven_msg_req I Request from your application to send a vendor-defined Message. Once


asserted, ven_msg_req must remain asserted until the controller
asserts ven_msg_grant.
Exists: Always
Synchronous To: aux_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ven_msg_grant O One-cycle pulse that indicates that the controller has accepted the
request to send the vendor-defined Message.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Power Budgeting Signals

5.29 Power Budgeting Signals

cfg_pwr_budget_data_reg - - cfg_pwr_budget_data_sel_reg
cfg_pwr_budget_func_num - - cfg_pwr_budget_sel

Table 5-29 Power Budgeting Signals

Port Name I/O Description

cfg_pwr_budget_data_reg[31:0] I New Data Register value. Data needs to be held.


Exists: PWR_BUDGET_CAP_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pwr_budget_func_num[(PF_WD-1):0] I Function # of data register above (because this capability is per


function). Function numbering starts at '0'.
Exists: PWR_BUDGET_CAP_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pwr_budget_data_sel_reg[7:0] O Contents of the Data Select Register.


Exists: PWR_BUDGET_CAP_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pwr_budget_sel[(NF-1):0] O One cycle pulse signal indicates new contents in Data Select Register.
Something changed the value of Data Select Register, so your
application should take a look at the new value and provide the updated
Data Register value corresponding to it.
Exists: PWR_BUDGET_CAP_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: AER Control Signals PCI Express SW Controller Databook

5.30 SII: AER Control Signals

app_dpc_triggered -
app_dpc_trig_en -
app_dpc_trig_status -

Table 5-30 SII: AER Control Signals

Port Name I/O Description

app_dpc_triggered I DPC triggered indication from application. A low to high transition


indicates that DPC has been triggered and by definition the Port is in
DPC. DPC is event triggered. It is expected that this signal is used to
update the corresponding DPC Status register bit field in the external
DPC capability.
Exists: CX_EXTDPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

app_dpc_trig_en[1:0] I DPC trigger Enable from the application and should be taken from the
corresponding external DPC Control register field, DPC Trigger Enable.
Encodings are:
■ 00b: DPC is disabled.
■ 01b: DPC is enabled and is triggered when the Downstream Port
detects an unmasked uncorrectable error or when the Downstream
Port receives an ERR_FATAL Message.
■ 10b: DPC is enabled and is triggered when the Downstream Port
detects an unmasked uncorrectable error or when the Downstream
Port receives an ERR_NONFATAL or ERR_FATAL Message.
■ 11b: Reserved.
Exists: CX_EXTDPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

app_dpc_trig_status I DPC trigger status from the application and should be taken from the
corresponding external DPC Status register field, DPC Trigger Status.
Exists: CX_EXTDPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: CCIX Configuration/Control/Status Signals

5.31 SII: CCIX Configuration/Control/Status Signals

ccix_tlp_disable - - pm_current_data_rate
- cfg_ccix_esm_enable
- cfg_ccix_esm_data_rate0
- cfg_ccix_esm_data_rate1
- cfg_ccix_opt_tlp_sup
- cfg_ccix_vc_resource
- cfg_ccix_opt_tlp_en
- cfg_ccix_tc_enable

Table 5-31 SII: CCIX Configuration/Control/Status Signals

Port Name I/O Description

pm_current_data_rate[1:0] O The current link operating rate.


■ 0: 2.5 GT/s signaling rate
■ 1: 5.0 GT/s signaling rate
■ 2: 8.0 GT/s signaling rate for PCIe mode or ESM data rate0 for ESM
mode
■ 3: 16.0 GT/s signaling rate for PCIe mode or ESM data rate1 for ESM
mode
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

cfg_ccix_esm_enable O Contents of the ESM Enable field of ESM Control Register.


Note: The DSP application must program (set or reset) this bit in the
remote USP first, before programming it locally.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_ESM_SUPPORT)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ccix_esm_data_rate0[6:0] O Contents of the ESM Data Rate0 field of ESM Control Register.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_ESM_SUPPORT)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: CCIX Configuration/Control/Status Signals PCI Express SW Controller Databook

Port Name I/O Description

cfg_ccix_esm_data_rate1[6:0] O Contents of the ESM Data Rate1 field of ESM Control Register.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_ESM_SUPPORT)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ccix_opt_tlp_sup O CCIX optimized TLP format supported field of CCIX Transaction Layer
Capabilities Register.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ccix_vc_resource[2:0] O CCIX VC Resource field of CCIX Transaction Layer Capabilities


Register.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

cfg_ccix_opt_tlp_en O Enable CCIX optimized TLP Generation and Reception CCIX


Transaction Layer Control Register.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ccix_tc_enable[7:0] O A bus that indicates which of the TCs are mapped to CCIX VC.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: CCIX Configuration/Control/Status Signals

Port Name I/O Description

ccix_tlp_disable I Disable the support of CCIX TLP. This is a boot strap signal and it needs
to be valid and static during reset.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE)
Synchronous To: core_clk,radm_clk_g,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: Configuration Information Signals PCI Express SW Controller Databook

5.32 SII: Configuration Information Signals

app_link_cap_mask - - cfg_10b_tag_req_en
cdm_reg_chk_test_en - - cfg_vf_pasid_en
- cfg_vf_pasid_execute_perm_en
- cfg_vf_pasid_priv_mode_en
- cfg_atomic_req_en
- cfg_atomic_egress_block
- cfg_obff_en
- cfg_ltr_m_en
- cfg_ltr_max_latency
- cfg_disable_ltr_clr_msg
- cfg_ari_fwd_en
- cfg_pwr_ind
- cfg_atten_ind
- cfg_pwr_ctrler_ctrl
- cfg_exp_rom_start
- cfg_exp_rom_limit
- cfg_bus_master_en
- cfg_mem_space_en
- cfg_max_rd_req_size
- cfg_ext_tag_en
- cfg_pm_no_soft_rst
- cfg_pbus_num
- cfg_pbus_dev_num
- cfg_bridge_crs_en
- cfg_vc_enable
- cfg_vc_struc_vc_id_map
- cfg_vc_id_vc_struc_map
- cfg_tc_enable
- cfg_tc_struc_vc_map
- cfg_mem_base
- cfg_mem_limit
- cfg_pref_mem_base
- cfg_pref_mem_limit
- cfg_io_limit_upper16
- cfg_io_base_upper16
- cfg_io_base
- cfg_io_limit
- cfg_io_space_en
- cfg_2ndbus_num
- cfg_subbus_num
- cfg_end2end_tlp_pfx_blck
- cfg_no_snoop_en
- cfg_relax_order_en
- cfg_ats_stu
- cfg_ats_cache_en
- cfg_acs_validation_en
- cfg_acs_at_blocking_en
- cfg_acs_p2p_req_redirect_en
- cfg_acs_p2p_compl_redirect_en
- cfg_acs_up_forward_en
- cfg_acs_p2p_egress_ctrl_en
- cfg_acs_p2p_direct_transl_en
- cfg_acs_egress_ctrl_vec
- acs_vf_p2p_req_redirect_en
- acs_vf_p2p_compl_redirect_en
- acs_vf_p2p_egress_ctrl_en
- acs_vf_p2p_direct_transl_en
- acs_vf_egress_ctrl_vec
- cfg_acs_func_grp_en

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PCI Express SW Controller Databook SII: Configuration Information Signals

- cfg_ari_func_grp
- cfg_vf_ari_func_grp
- cdm_reg_chk_logic_err
- cdm_reg_chk_cmp_err
- cdm_reg_chk_cmplt
- rbar_ctrl_update
- cfg_rbar_size
- vf_rbar_ctrl_update
- cfg_vf_rbar_size
- cfg_hp_slot_ctrl_access
- cfg_dll_state_chged_en
- cfg_cmd_cpled_int_en
- cfg_hp_int_en
- cfg_pre_det_chged_en
- cfg_mrl_sensor_chged_en
- cfg_pwr_fault_det_en
- cfg_atten_button_pressed_en
- if_timeout_status

Table 5-32 SII: Configuration Information Signals

Port Name I/O Description

cfg_10b_tag_req_en[(NF-1):0] O Contents of the PCIE_CAP_10BITS_TAG_REQ_EN field in the


DEVICE_CONTROL2_DEVICE_STATUS2_REG register.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_10BITS_TAG== 1 &&
CX_MAX_TAG > 255)? 1: 0)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_vf_pasid_en[(INT_NVF-1):0] O The value of the PASID Enable field in each VF PASID Control Register.
Exists: (CX_SRIOV_ENABLE) && (VF_PASID_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_vf_pasid_execute_perm_en[(INT_NV O The value of the Execute Permission Enable field in each VF PASID
F-1):0] Control Register.
Exists: (CX_SRIOV_ENABLE) && (VF_PASID_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_vf_pasid_priv_mode_en[(INT_NVF-1): O The value of the Privileged Mode Enable field in each VF PASID Control
0] Register.
Exists: (CX_SRIOV_ENABLE) && (VF_PASID_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_atomic_req_en[(NF-1):0] O The AtomicOp Requester Enable field (PCIE_CAP_ATOMIC_REQ_EN)


of the Device Control 2 register.
Exists: CX_ATOMIC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_atomic_egress_block[(NF-1):0] O The AtomicOp Egress Blocking field


(PCIE_CAP_ATOMIC_EGRESS_BLK) of the Device Control 2 register.
Exists: (CX_ATOMIC_ENABLE) && (CX_ATOMIC_ROUTING_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_obff_en[1:0] O The OBFF Enable field of the Device Control 2 register of function 0.
Exists: CX_OBFF_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ltr_m_en O The LTR Mechanism Enable field of the Device Control 2 register of
function 0.
Exists: CX_LTR_M_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Configuration Information Signals

Port Name I/O Description

cfg_ltr_max_latency[((32*NF)-1):0] O The concatenated contents of 'LTR Max No-Snoop Latency Register'


and 'LTR Max Snoop Latency Register'. The 'LTR Max Snoop Latency '
occupies the lower 16-bits.
Exists: CX_LTR_M_ENABLE
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_disable_ltr_clr_msg O Disable the autonomous generation of LTR clear message.


Exists: CX_LTR_M_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ari_fwd_en[(NF-1):0] O ARI Forwarding Enabled (DSP). Indicates that the port is ARI-aware
and that the Alternate Routing ID (ARI) Capability is enabled.
Exists: CX_ARI_FWD_CAP
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pwr_ind[((2*NF)-1):0] O Controls the system power indicator (from bits [9:8] of the Slot Control
register), per function:
■ 00b: Reserved
■ 01b: On
■ 10b: Blink
■ 11b: Off
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_atten_ind[((2*NF)-1):0] O Controls the system attention indicator (from bits [7:6] of the Slot Control
register), per function:
■ 00b: Reserved
■ 01b: On
■ 10b: Blink
■ 11b: Off
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pwr_ctrler_ctrl[(NF-1):0] O Controls the system power controller (from bit 10 of the Slot Control
register), per function:
■ 0: Power On
■ 1: Power Off
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_exp_rom_start[((32*NF)-1):0] O The starting address of expansion ROM. There are 32 bits of


cfg_exp_rom_start assigned to each configured function.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_exp_rom_limit[((32*NF)-1):0] O The end address of expansion ROM. There are 32 bits of


cfg_exp_rom_limit assigned to each configured function.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_bus_master_en[(NF-1):0] O Consult your hidden customer specific feature specification.


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_mem_space_en[(NF-1):0] O The state of the Memory Space Enable bit in the PCI-compatible
Command register. There is 1 bit of cfg_mem_space_en assigned to
each configured function.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_max_rd_req_size[((3*NF)-1):0] O The value of the Max_Read_Request_Size field in the Device Control


register. There are 3 bits of cfg_max_rd_req_size assigned to each
configured function.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ext_tag_en[(NF-1):0] O When enabled, controller supports up to 8-bit tag values.


Exists: Any DEFAULT_EXT_TAG_FIELD_SUPPORTED_n is 1
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pm_no_soft_rst[(NF-1):0] O This is the value of the No Soft Reset bit in the Power Management
Control and Status Register. When set, you should not reset any
controller registers when transitioning from D3hot to D0. Therefore, you
should not assert the non_sticky_rst_n and sticky_rst_n inputs.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_pbus_num[(BUSNUM_WD-1):0] O The primary bus number assigned to the function. The number of bits
depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN:
■ If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0, there are eight
bits of cfg_pbus_num ([7:0]), regardless of the number of functions.
■ If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =1, there are eight
bits of cfg_pbus_num for each configured function.
Exists: Always
Synchronous To: core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pbus_dev_num[(DEVNUM_WD-1):0] O The device number assigned to the function. The number of bits
depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN:
■ If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0, there are five
bits of cfg_pbus_dev_num ([4:0]), regardless of the number of func-
tions.
■ If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =1, there are five
bits of cfg_pbus_dev_num for each configured function.
Exists: Always
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_bridge_crs_en[(NF-1):0] O Bridge Configuration Retry Enable. Indicates the status of the Bridge
Configuration Retry Enable bit in the Device Control register. Applicable
only for PCI Express to PCI(-X) bridge devices
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

app_link_cap_mask[5:0] I Link Capability Mask. Masks the Link Capability that the controller has
been advertised. Allows your application to drive a bit mask for the value
in the "Link Mode Enable" field of the "Port Link Control Register" (Port
Logic register at address 0x710). The masked value is used by LTSSM
to determine which lanes to detect during the initial phase of training.
Typical value is 6'h3F.
Exists: Always
Synchronous To: None,perbitclk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_vc_enable[(NVC-1):0] O Configured VC Enable. Indicates the VC enable state for each


supported VC. NVC represents the number of supported VCs.
NoteVC0 is always supported and enabled.
Exists: VC_ENABLE
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_vc_struc_vc_id_map[((NVC*3)-1):0] O Configured Structural VC to VC Identifier Map. This bus provides the


mapping from the structural (physical) VC numbering scheme, that is,
the order in which the VCs are declared in the configuration space, to
the logical VC identifiers that are assigned by system software. To
obtain the logical ID, index this bus with the structural ID.For example,
■ Bits [2:0] return the logical ID for structural VC 0 and always equals
to 0.
■ Bits [5:3] return the logical ID for structural VC 1.
■ Etc.
Exists: VC_ENABLE
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_vc_id_vc_struc_map[23:0] O Configured VC Identifier to Structural VC Map. This bus provides the


mapping of the logical VC identifiers that are defined by the system, to
the structural (physical) VC numbering scheme. To obtain the structural
ID, index this bus with the logical ID. For example,
■ Bits [2:0] return the structural ID (position) for the VC assigned to VC
0 and always equals to 0.
■ Bits [5:3] return the structural ID (position) for the VC assigned to VC
1.
■ Etc.
When a given ID is not assigned, the bus returns 0.
Exists: VC_ENABLE
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

cfg_tc_enable[7:0] O Indicates the enabled TCs. TCn is enabled when bit[n] is 1.


Exists: VC_ENABLE
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_tc_struc_vc_map[23:0] O TC to Structural VC map.


■ Bits [2:0] return the structural VC number for the TC0 and always
equals to 0.
■ Bits [5:3] return the structural VC number for the TC1.
■ Etc.
Each structural VC[m] that this signal indicates is enabled by
cfg_vc_enable[m].
Exists: VC_ENABLE
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: No
Power Domain: PD_VAUX
Active State: N/A
Validated by: cfg_tc_struc_vc_map[3*n +: 3] is validated by
cfg_tc_enable[n].

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Port Name I/O Description

cfg_mem_base[((16*NF)-1):0] O Configured Memory Base register. The contents of the Memory Base
register from the PCIe type 1 configuration space. Memory and I/O
ranges are programmed in each downstream switch port to route
request packets.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_mem_limit[((16*NF)-1):0] O Configured Memory Limit register. The contents of the Memory Limit
register from the PCIe type 1 configuration space. Memory and I/O
ranges are programmed in each downstream switch port to route
request packets.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pref_mem_base[((64*NF)-1):0] O Configured Prefetchable Memory Base register. The contents of the


Prefetchable Memory Base register from the PCIe type 1 configuration
space. Memory and I/O ranges are programmed in each downstream
switch port to route request packets.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pref_mem_limit[((64*NF)-1):0] O Configured Prefetchable Memory Limit register. The contents of the


Prefetchable Memory Limit register from the PCIe type 1 configuration
space. Memory and I/O ranges are programmed in each downstream
switch port to route request packets.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_io_limit_upper16[((16*NF)-1):0] O Configured I/O Limit Upper 16 bits. The contents of the I/O Limit Upper
16 Bits register from the PCIe type 1 configuration space. Memory and
I/O ranges are programmed in each downstream switch port to route
request packets.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_io_base_upper16[((16*NF)-1):0] O Configured I/O Base Upper 16 bits. The contents of the I/O Base Upper
16 Bits register from the PCIe type 1 configuration space. Memory and
I/O ranges are programmed in each downstream switch port to route
request packets.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_io_base[((8*NF)-1):0] O Configured I/O Base register. The contents of the I/O Base register from
the PCIe type 1 configuration space. Memory and I/O ranges are
programmed in each downstream switch port to route request packets.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_io_limit[((8*NF)-1):0] O Configured I/O Base register. The contents of the I/O Limit register from
the PCIe type 1 configuration space. Memory and I/O ranges are
programmed in each downstream switch port to route request packets.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_io_space_en[(NF-1):0] O Configured I/O Space Enable. The contents of the I/O Space Enable bit
in the PCIe Type 1 configuration space. Memory and I/O ranges are
programmed in each downstream switch port to route request packets.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_2ndbus_num[((8*NF)-1):0] O Configured Secondary Bus Number. The secondary bus number


assigned to the device. When the host software detects the upstream
switch port, it assigns a secondary bus number. This bus number is then
used in configuration requests to detect the downstream ports. The
switch controller must see this so that it can route configuration
requests.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_subbus_num[((8*NF)-1):0] O Configured Subordinate Bus Number. When the switch controller


receives a configuration request from the upstream port, it must see the
secondary and subordinate bus number fields from the downstream
ports to route the request.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_end2end_tlp_pfx_blck[(NF-1):0] O The value of the End-End TLP Prefix Blocking field in the Device Control
2 register.
Exists: CX_TLP_PREFIX_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_no_snoop_en[(NF-1):0] O Contents of the "Enable No Snoop" field (PCIE_CAP_EN_NO_SNOOP)


in the "Device Control and Status" register
(DEVICE_CONTROL_DEVICE_STATUS) register.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_relax_order_en[(NF-1):0] O Contents of the "Enable Relaxed Ordering" field


(PCIE_CAP_EN_REL_ORDER) in the "Device Control and Status"
register (DEVICE_CONTROL_DEVICE_STATUS) register.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ats_stu[((5*NF)-1):0] O Contents of the "Smallest Translation Unit" field (ATU) in the


ATS_CAPABILITIES_CTRL_REG register.
Exists: CX_ATS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ats_cache_en[(NF-1):0] O Contents of the "Cache Enable" (ENABLE) field in the


ATS_CAPABILITIES_CTRL_REG register.
Exists: CX_ATS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_acs_validation_en O Contents of the "ACS Source Validation Enable (V)" field (ACS) in the
ACS_CAPABILITIES_CTRL_REG register. When set, the component
validates the Bus Number from the requester ID of upstream requests
against the secondary/subordinate Bus Numbers.
Exists: CX_ACS_ENABLE
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_acs_at_blocking_en O Contents of the "ACS Translation Blocking Enable (B)" field (ACS) in the
ACS_CAPABILITIES_CTRL_REG register. When set, the component
blocks all upstream memory requests whose Address Translation (AT)
field is not set to the default value.
Exists: CX_ACS_ENABLE
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_acs_p2p_req_redirect_en[(NF-1):0] O Contents of the "ACS P2P Request Redirect Enable (R)" field (ACS) in
the ACS_CAPABILITIES_CTRL_REG register. It determines when the
component redirects peer-to-peer requests upstream.
Exists: CX_ACS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_acs_p2p_compl_redirect_en[(NF-1):0] O Contents of the "ACS P2P Completion Redirect Enable (C)" field (ACS)
in the ACS_CAPABILITIES_CTRL_REG register. It determines when
the component redirects peer-to-peer completions upstream.
Exists: CX_ACS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_acs_up_forward_en O Contents of the "ACS Upstream Forwarding Enable (U)" field (ACS) in
the ACS_CAPABILITIES_CTRL_REG register. When set, the
component forwards upstream any request or completion TLPs it
receives, that were redirected upstream by a component lower in the
hierarchy.
Exists: CX_ACS_ENABLE
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_acs_p2p_egress_ctrl_en[(NF-1):0] O Contents of the "ACS P2P Egress Control Enable (E)" field (ACS) in the
ACS_CAPABILITIES_CTRL_REG register. It determines when to allow,
disallow, or redirect peer-to-peer requests.
Exists: CX_ACS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_acs_p2p_direct_transl_en[(NF-1):0] O Contents of the "ACS Direct Translated P2P Enable (T)" field (ACS) in
the ACS_CAPABILITIES_CTRL_REG register. It overrides the ACS
P2P Request Redirect and ACS P2P Egress Control mechanisms with
peer-to-peer Memory Requests whose Address Translation (AT) field
indicates a translated address.
Exists: CX_ACS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_acs_egress_ctrl_vec[((ACS_CTRL_V O Contents of the "ACS Egress Control" Register. The width is defined by
EC_WD*NF)-1):0] ACS_CTRL_VEC_WD, per-function. ACS_CTRL_VEC_WD is the
largest egress control vector size of all functions.
Exists: (CX_ACS_ENABLE) && ([<functionof>
CX_ACS_P2P_EGRESS_CTRL])
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

acs_vf_p2p_req_redirect_en[(INT_NVF-1) O Contents of the "ACS P2P Request Redirect Enable (R)" field (ACS) in
:0] the VF_ACS_CAPABILITIES_CTRL_REG register. It determines when
the component redirects peer-to-peer requests upstream.
Exists: (CX_ACS_ENABLE) && (VF_ACS_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

acs_vf_p2p_compl_redirect_en[(INT_NVF O Contents of the "ACS P2P Completion Redirect Enable (C)" field (ACS)
-1):0] in the VF_ACS_CAPABILITIES_CTRL_REG register. It determines
when the component redirects peer-to-peer completions upstream.
Exists: (CX_ACS_ENABLE) && (VF_ACS_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

acs_vf_p2p_egress_ctrl_en[(INT_NVF-1): O Contents of the "ACS P2P Egress Control Enable (E)" field (ACS) in the
0] VF_ACS_CAPABILITIES_CTRL_REG register. It determines when to
allow, disallow, or redirect peer-to-peer Requests.
Exists: (CX_ACS_ENABLE) && (VF_ACS_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

acs_vf_p2p_direct_transl_en[(INT_NVF-1) O Contents of the "ACS Direct Translated P2P Enable (T)" field (ACS) in
:0] the VF_ACS_CAPABILITIES_CTRL_REG register. It overrides the ACS
P2P Request Redirect and ACS P2P Egress Control mechanisms with
peer-to-peer memory requests whose Address Translation (AT) field
indicates a translated address.
Exists: (CX_ACS_ENABLE) && (VF_ACS_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

acs_vf_egress_ctrl_vec[((ACS_CTRL_VE O Contents of the "VF ACS Egress Control Vector" Register. The size
C_WD*INT_NVF)-1):0] ACS_CTRL_VEC_WD is the largest egress control vector size of all
functions.
Exists: (CX_ACS_ENABLE) && (VF_ACS_ENABLE) && ([<functionof>
CX_ACS_P2P_EGRESS_CTRL])
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_acs_func_grp_en[(NF-1):0] O ACS Function Group Enable, per-PF.


Exists: CX_ACS_FUNC_GRP
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ari_func_grp[((3*NF)-1):0] O ARI Function Group[2:0], per-PF.


Exists: CX_ACS_FUNC_GRP
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_vf_ari_func_grp[((3*INT_NVF)-1):0] O Contents of the "VF ARI Function Group [2:0]" settings, per VF.
Exists: VF_ACS_FUNC_GRP
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cdm_reg_chk_test_en I Signal to enter test mode in the Register Checking Logic. u_cdm_b is
not be written to when this signal is high. Allows a value to be written to
u_cdm to compare against the previous value in u_cdm_b
Exists: CX_CDM_REG_CHK_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cdm_reg_chk_logic_err O Signal to indicate that there is an Error in the Register Checking Logic.
Exists: CX_CDM_REG_CHK_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cdm_reg_chk_cmp_err O Signal to indicate that the register values read from both CDM's do not
match.
Exists: CX_CDM_REG_CHK_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cdm_reg_chk_cmplt O Signal to indicate that a Register Checking Sequence has Completed.


Exists: CX_CDM_REG_CHK_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

rbar_ctrl_update[(NF-1):0] O Indicates that a resizable BAR control register has been updated: 1 bit
per Physical function.
Exists: CX_RBARS_INCLUDED
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_rbar_size[((NF*(6*6))-1):0] O BAR size field from each of the resizable BAR control registers, per
function. For BARs that are not resizable the corresponding bits in
cfg_rbar_size are set to 0.
Exists: CX_RBARS_INCLUDED
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

vf_rbar_ctrl_update[(NF-1):0] O Indicates that a resizable VF BAR control register has been updated: 1
bit per Physical function.
Exists: (CX_RBARS_INCLUDED) && (CX_VF_RBARS_INCLUDED)
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_vf_rbar_size[((NF*(6*6))-1):0] O BAR size field from each of the resizable VF BAR control registers, per
function. For BARs that are not resizable, the corresponding bits in
cfg_vf_rbar_size are set to 0.
Exists: (CX_RBARS_INCLUDED) && (CX_VF_RBARS_INCLUDED)
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_hp_slot_ctrl_access[(NF-1):0] O Slot Control Accessed.


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_dll_state_chged_en[(NF-1):0] O Slot Control DLL State Change Enable.


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_cmd_cpled_int_en[(NF-1):0] O Slot Control Command Completed Interrupt Enable.


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_hp_int_en[(NF-1):0] O Slot Control Hot Plug Interrupt Enable.


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pre_det_chged_en[(NF-1):0] O Slot Control Presence Detect Changed Enable.


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_mrl_sensor_chged_en[(NF-1):0] O Slot Control MRL Sensor Changed Enable.


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_pwr_fault_det_en[(NF-1):0] O Slot Control Power Fault Detect Enable.


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_atten_button_pressed_en[(NF-1):0] O Slot Control Attention Button Pressed Enable.


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

if_timeout_status O Interface timeout status


Exists: CX_INTERFACE_TIMER_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Debug Signals

5.33 SII: Debug Signals

- rdlh_link_up
- rtlh_rfc_upd
- rtlh_rfc_data
- radm_q_not_empty
- radm_qoverflow
- cxpl_debug_info
- cxpl_debug_info_ei

Table 5-33 SII: Debug Signals

Port Name I/O Description

rdlh_link_up O Data link layer up/down indicator: This status from the flow control
initialization state machine indicates that flow control has been initiated
and the Data link layer is ready to transmit and receive packets. For
multi-VC designs, this signal indicates status for VC0 only.
■ 1: Link is up
■ 0: Link is down
Exists: Always
Synchronous To: aux_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

rtlh_rfc_upd[(RX_NDLLP-1):0] O Indicates that the controller received a flow control update DLLP. Used
for applications that implement flow Control outside the controller.
■ For the 32 and 64-bit versions of the controller, RX_NDLLP =1 and
the data from the flow control update DLLP is available rtlh_rfc_-
data[31:0].
■ For the 128-bit versions of the controller, RX_NDLLP =2 because it
is possible to receive two flow control update DLLPs in one clock
cycle. In this case, assertion of one bit indicates one flow control
update DLLP was received and assertion of both bits indicates two
flow control update DLLPs were received. Each bit corresponds to
one dword rtlh_rfc_data: bit [0] indicates valid data flow control
update data rtlh_rfc_data[31:0] and bit [1] indicates valid data flow
control update data rtlh_rfc_data[63:32]. The controller only asserts
rtlh_rfc_upd[1] when two flow control update DLLPs are received in
the same clock cycle.
■ For the 256-bit versions of the controller, RX_NDLLP =4 because it
is possible to receive four flow control update DLLPs in one clock
cycle. In this case, assertion of one bit indicates one flow control
update DLLP was received, assertion of two bits indicates two flow
control update DLLPs were received, and so on. Each bit corre-
sponds to one dword rtlh_rfc_data: bit [0] indicates valid data flow
control update data rtlh_rfc_data[31:0] and bit [3] indicates valid data
flow control update data rtlh_rfc_data[255:224]. The controller only
asserts add four bits when four flow control update DLLPs are
received in the same clock cycle.
Exists: Always
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

rtlh_rfc_data[((32*RX_NDLLP)-1):0] O The data from a received flow control update DLLP. The width and
contents of rtlh_rfc_data depend the value of RX_NDLLP which is
defined in the description of rtlh_rfc_upd.
Exists: Always
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: rtlh_rfc_upd is asserted

radm_q_not_empty[(NVC-1):0] O Level indicating that the receive queues contain TLP header/data.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High indicates data in queues
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Debug Signals

Port Name I/O Description

radm_qoverflow[(NVC-1):0] O Pulse indicating that one or more of the P/NP/CPL receive queues have
overflowed. There is a 1-bit indication for each configured virtual
channel. You can connect this output to your internal error reporting
mechanism.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High pulse indicates overflow
Validated by: Not validated by another signal

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Port Name I/O Description

cxpl_debug_info[63:0] O State of selected internal signals, for debugging purposes only:


■ [63]: smlh_scrambler_disable: Scrambling disabled for the link
■ [62]: smlh_link_disable: TSSM in DISABLE state. Link inoperable
■ [61]: smlh_link_in_training: LTSSM performing link training
■ [60]: smlh_ltssm_in_pollconfig: LTSSM is in Polling.Configuration
state
■ [59]: smlh_training_rst_n: LTSSM-negotiated link reset
■ [58:55]: 0000b: Reserved
■ [54]: mac_phy_txdetectrx_loopback: PIPE receiver detect/loopback
request (Reserved for M-PCIe)
■ [53]: mac_phy_txelecidle[0]: PIPE transmit electrical idle request
(RMMI TX_Burst[0](TX_Burst initiates a BURST) for M-PCIe)
■ [52]: mac_phy_txcompliance[0]: PIPE transmit compliance request
(RX Electrical Idle at internal PIPE I/F(from Rpa to Smlh module) for
M-PCIe)
■ [51]: app_init_rst: Application request to initiate training reset
■ [50:48]: 000b: Reserved
■ [47:40]: rmlh_ts_link_num: Link number advertised/confirmed by link
partner (Reserved for M-PCIe)
■ [39:38]: 00b: Reserved
■ [37]: xmtbyte_skip_sent: A skip ordered set has been transmitted
■ [36]: smlh_link_up: LTSSM reports PHY link up or LTSSM is in Loop-
back.Active for Loopback Master
■ [35]: smlh_inskip_rcv: Receiver reports skip reception (Reserved for
M-PCIe)
■ [34]: smlh_ts1_rcvd: TS1 training sequence received (pulse)
(Reserved for M-PCIe)
■ [33]: smlh_ts2_rcvd: TS2 training sequence received (pulse)
(Reserved for M-PCIe)
■ [32]: smlh_rcvd_lane_rev: Receiver detected lane reversal
(Reserved for M-PCIe)
■ [31:28]: smlh_ts_link_ctrl: Link control bits advertised by link partner
(Reserved for M-PCIe)
■ [27]: smlh_ts_lane_num_is_k237: Currently receiving k237 (PAD) in
place of lane number (Reserved for M-PCIe)
■ [26]: smlh_ts_link_num_is_k237: Currently receiving k237 (PAD) in
place of link number (Reserved for M-PCIe)
■ [25]: rmlh_rcvd_idle[0]: Receiver is receiving logical idle
■ [24]: rmlh_rcvd_idle[1]: 2n symbol is also idle (16bit PHY interface
only)
■ [23:8]: mac_phy_txdata: PIPE(RMMI for M-PCIe) Transmit data

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PCI Express SW Controller Databook SII: Debug Signals

Port Name I/O Description

cxpl_debug_info[63:0]...(cont.) O. ■ [7:6]: mac_phy_txdatak: PIPE(RMMI for M-PCIe) transmit K indica-


tion
■ [5:0]: smlh_ltssm_state: LTSSM current state. Encoding is same as
the dedicated smlh_ltssm_state output.
Exists: Always
Synchronous To:
None,aux_clk,aux_clk_g,perbitclk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cxpl_debug_info_ei[15:0] O State of selected internal signals in relation to electrical idle (EI) at the
receiver. The encoding of the bits is as follows:
Group 1(pulse) - information about received ordered sets:
■ [0]: EIOS detected
Group 2(level) - LTSSM is in one of the states that depend rxelecidle =0:
■ [1]: L1
■ [2]: L2
■ [3]: RxL0s
■ [4]: Disabled
■ [5]: Detect.Quiet
■ [6]: Polling.Active (Reserved for M-PCIe)
■ [7]: Polling.Compliance (Reserved for M-PCIe)
Group 3(level) - LTSSM is in one of the states that depend rxelecidle =1:
■ [8]: LTSSM is in a transitory state prior to L1 or L2
■ [9]: LTSSM is in a transitory state prior to Disabled
■ [10]: LTSSM is in Loopback.Active as a Slave at Gen1
■ [11]: LTSSM is in Polling.Active (Reserved for M-PCIe)
Group 4(pulse) - LTSSM state transitions with EI inferred:
■ [12]: LTSSM enters Recovery from L0 with EI inferred, first row in
base spec Table 4-11
■ [13]: LTSSM enters Recovery.Speed from Recovery.RcvrCfg with EI
inferred, second row in Table 4-11 of PCI Express Specifica-
tion(Reserved for M-PCIe)
■ [14]: EI inferred while LTSSM in Recovery.Speed, third/fourth rows
in base spec Table 4-11 (Reserved for M-PCIe)
■ [15]: EI inferred while LTSSM in Loopback.Active as a slave, fifth row
in base spec Table 4-11 (Reserved for M-PCIe)
Exists: Always
Synchronous To: perbitclk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: Diagnostic Control Signals PCI Express SW Controller Databook

5.34 SII: Diagnostic Control Signals

diag_ctrl_bus - - diag_status_bus

Table 5-34 SII: Diagnostic Control Signals

Port Name I/O Description

diag_ctrl_bus[2:0] I Diagnostic Control Bus


■ x01: Insert LCRC error by inverting the LSB of LCRC
■ x10: Insert ECRC error by inverting the LSB of ECRC
❑ The rising edge of these two signals ([1:0]) enable the controller
to assert an LCRC or ECRC to the packet that it currently being
transferred.
❑ When LCRC or ECRC error packets are transmitted by the
controller, the controller asserts diag_status_bus[lcrc_err_as-
serted] or diag_status_bus[ecrc_err_asserted] to report that the
requested action has been completed. This handshake between
control and status allows your application to control a specific
packet being injected with an CRC or ECRC error.
❑ The LCRC and ECRC errors are generated by simply inverting
the last bit of the LCRC or ECRC value.
■ 1xx: Select Fast Link Mode.
❑ Sets all internal LTSSM millisecond timers to Fast Mode for
speeding up simulation purposes. Forces the LTSSM training
(link initialization) to use shorter timeouts and to link up faster.
❑ The default scaling factor is 1024 for all internal timers. The
default scaling factor can be changed using the DEFAULT_-
FAST_LINK_SCALING_FACTOR parameter or through the
FAST_LINK_SCALING_FACTOR field in the TIMER_CTRL_-
MAX_FUNC_NUM_OFF register.
❑ Fast Link Mode can also be activated by setting the
FAST_LINK_MODE field in the PORT_LINK_CTRL_OFF
register.
❑ For more details, see the "Fast Link Simulation Mode" section in
the "Integrating the Controller with the PHY or Application RTL
or Verification IP" chapter of the User Guide.
Exists: DIAGNOSTIC_ENABLE
Synchronous To: aux_clk_g,perbitclk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

diag_status_bus[CX_DIAG_STATUS_BUS O Diagnostic Status Bus. Contains all of the important status signals from
_WD-1:0] each controller module. The individual diagnostic sub-buses and their
corresponding signals are listed below in the order from least significant
bit to most significant bit (with respect to the entire diagnostic bus
group). Therefore, diag_status_bus[0] is rtfcgen_incr_amt[0]. The
parameter macros will be replaced by actual parameter values in the
configured IP-XACT and coreConsultant report (DocBook XML and
HTML) files.
Data Link Layer Diagnostic Signals
■ rtfcgen_incr_amt[9*NHQ-1:0] = Payload flow control credits
consumed. NOTE: hdr credits consumed is always 1
■ rtfcgen_incr_enable[NHQ-1:0] = Header flow control credit
consumed
■ rtfcgen_fctype[2*NHQ-1:0] = Flow control type consumed (P=0,
NP=1, CPL=2)
■ rtcheck_rtfcgen_vc[3*NHQ-1:0] = Virtual channel of received TLP
■ xdlh_xtlh_halt = Layer2 is not accepting data to transmit this cycle
■ xtlh_xdlh_data[TRGT_DATA_PROT_WD+(NW*32)-1:0] = Transmit
data at the interface between Layer3 and Layer2. If RASDP is
enabled, includes the ECC or parity protection code bits.
■ xtlh_xdlh_badeot[NW-1:0] = Nullify this transmit TLP (invert CRC,
append EDB)
■ xtlh_xdlh_eot[NW-1:0] = Transmit End of TLP this cycle
■ xtlh_xdlh_sot[NW-1:0] = Transmit Start of TLP this cycle
■ ecrc_err_asserted = End-to-end CRC corrupted for this packet
■ lcrc_err_asserted = Link CRC corrupted for this packet
■ xmlh_xdlh_halt = PHY Layer not accepting data this cycle
■ xdlh_xmlh_data[32*NW-1:0] = Transmit packet payload (completely
framed)
■ xdlh_xmlh_sdp[NW-1:0] = Transmit Start of DLLP (per dword)
■ xdlh_xmlh_stp[NW-1:0] = Transmit Start of TLP (per dword)
■ xdlh_xmlh_eot[NW-1:0] = Transmit end of TLP/DLLP (per dword)
■ rdlh_xdlh_req_acknack_seqnum[11:0] = Sequence Number for
ACK/NAK DLLP
■ rdlh_xdlh_req2send_nack = DataLink Layer request to send NAK
■ rdlh_xdlh_req2send_ack_due2dup = Request to send ACK due to
duplicate TLP
■ rdlh_xdlh_req2send_ack = DataLink Layer request to send ACK
■ rdlh_xdlh_rcvd_acknack_seqnum[11:0] = Sequence number corre-
sponding to NAK/ACK

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Port Name I/O Description

diag_status_bus[CX_DIAG_STATUS_BUS O. ■ rdlh_xdlh_rcvd_ack = DataLink Layer received ACK DLLP


_WD-1:0]...(cont.) ■ rdlh_xdlh_rcvd_nack = DataLink Layer received NAK DLLP
■ cfg_link_retrain = Software programmed link retrain request
■ rtlh_req_link_retrain = Receive watchdog timer expired, retrain link
■ xdlh_smlh_start_link_retrain = vMax retries attempted, request to
retrain link
■ rdlh_rtlh_tlp_dv = Receive data interface from DLL to Transaction
Layer valid this cycle (rdlh_rtlh_*)
■ rdlh_rtlh_tlp_eot[NW-1:0] = End of TLP (per dword)
■ rdlh_rtlh_tlp_sot[NW-1:0] = Start of TLP (per dword)
MAC Layer Diagnostic Signals
■ rmlh_rdlh_pkt_data[32*NW-1:0] = Received packet payload
■ rmlh_rdlh_pkt_err[NW-1:0] = Physical Error detected (per dword)
■ rmlh_rdlh_pkt_dv = Receive data interface from PHY to DLL valid
this cycle (rmlh_rdlh_*)
■ rmlh_rdlh_pkt_edb[NW-1:0] = Packet terminated with EDB (per
dword)
■ rmlh_rdlh_pkt_end[NW-1:0] = DLLP/TLP ending (per dword)
■ rmlh_rdlh_tlp_start[NW-1:0] = DLLP starting (per dword)
■ rmlh_rdlh_dllp_start[NW-1:0] = MAC layer detected runt STP (per
dword)
■ rmlh_rdlh_nak[NW-1:0] = MAC layer detected runt STP (per dword)
■ rmlh_lanes_rcving[NL-1:0] = lanes active in link training
■ rmlh_rcvd_eidle_set = Received EIDLE ordered set, any active lane
■ rmlh_rcvd_idle1 = Logical Idle seen for 1+ symbols on all active
lanes
■ rmlh_rcvd_idle0 = Logical Idle seen for 8+ symbols on all active
lanes
■ smlh_rcvd_lane_rev = Receive logic detected logical lane reversal
■ rmlh_ts_link_num_is_k237 = Received Link number (lane 0) is PAD
(k237)
■ rmlh_deskew_alignment_err = Deskew logic overflow. Unable to
align lanes [level]
■ rmlh_ts_lane_num_is_k237 = Received lane number (lane 0) is PAD
(k237)
■ rmlh_ts2_rcvd = At least one active lane received TS2 this cycle
■ rmlh_ts1_rcvd = At least one active lane received TS1 this cycle
■ rmlh_ts_rcv_err = Assert when the received data is not an expected
TS symbol or SKP symbol or EIEOS symbol on Lane 0

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PCI Express SW Controller Databook SII: Diagnostic Control Signals

Port Name I/O Description

diag_status_bus[CX_DIAG_STATUS_BUS O.. ■ rmlh_inskip_rcv = Skip character is received this cycle


_WD-1:0]...(cont..) PM Diagnostic Bus
■ xadm_no_fc_credit[NVC-1:0] = No credits of any type are available
(per VC).
■ xadm_notlp_pending = No TLP transmit requests currently pending
(from internal or external clients).
■ xadm_had_enough_credit[NVC-1:0] = The controller has enough
transmit credits of each type (per VC) to meet the PM entry criteria.
■ xdlh_not_expecting_ack = All transmitted TLPs have been acknowl-
edged by the link partner.
■ xdlh_xmt_pme_ack = DataLink layer just transmitted a
PME_TO_ACK msg.
■ xdlh_nodllp_pending = There are no pending or in-progress packets
going to the PHY.
■ l1sub_state[2:0] = L1 FSM sub-state (Tied to 3'b000 when !CX_L1_-
SUBSTATES_ENABLE)
❑ 3'h0: idle state.

❑ 3'h1: wait for aux_clk_active.

❑ 3'h2: wait for pclkack.

❑ 3'h3: wait for clkreq.

❑ 3'h4: check clkreq_in_n is de-asserted for t_power_off time (only


for L1.2, reduces to one cycle for L1.1).
❑ 3'h5: L1 substate, turn off txcommonmode circuits (L1.2 only)
and rx electrical idle detection circuits.
❑ 3'h6: locally/remotely initiated exit, assert pclkreq, wait for
pclkack.
❑ 3'h7: wait for pclkack when aborting an attempt to enter state 5.

RADM Diagnostic Busses.


When RX_TLP =2 (256-bit configuration), there are two RADM
diagnostic busses because it is possible to receive two TLPs in one
clock cycle.
RADM Diagnostic Bus 0
The signals from unexpected_cpl_err to flt_q_header_destination are
only valid when form_filt_hv/form_filt_eot are asserted.
■ unexpected_cpl_err = Received a completion that was unexpected
■ cpl_ca_err = Received completion with CA status
■ cpl_ur_err = Received completion with UR status
■ flt_q_cpl_last = Final completion for the transaction
■ flt_q_cpl_abort = Current completion is being aborted (trashed)
■ cpl_mlf_err = Malformed completion

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Port Name I/O Description

diag_status_bus[CX_DIAG_STATUS_BUS O... ■ flt_q_header_cpl_status[2:0] = Indicates the filtering result for the


_WD-1:0]...(cont...) current RX request or the completion status for the current RX
received completion.
❑ 0: =Successful Completion (SC)

❑ 1: Unsupported request (UR)

❑ 2: Configuration Retry (CRS)

❑ 4: Completer abort (CA)

■ flt_q_header_destination[1:0] = Destination interface.


❑ 0: Drop

❑ 1: TRGT0

❑ 2: TRGT1

❑ 3: Reserved

■ form_filt_ecrc_err = This TLP had an ECRC error


■ form_filt_malform_tlp_err = This TLP is malformed
■ form_filt_dllp_err = This TLP has a DataLink Layer Error (for
example, LCRC)
■ form_filt_eot = End of TLP received this cycle
■ form_filt_dwen[NW-1:0] = Dword enables
■ form_filt_data[32*NW-1:0] = Packet data from receive Transaction
Layer
■ form_filt_dv = Packet is in payload stage
■ form_filt_hdr[127:0] = Header data (size of stored header is configu-
rable)
■ form_filt_hv = Information to the receive packet filter block is valid
RADM Diagnostic Bus 1
The signals from unexpected_cpl_err to flt_q_header_destination are
only valid when form_filt_hv/form_filt_eot are asserted.
■ unexpected_cpl_err = Received a completion that was unexpected
■ cpl_ca_err = Received completion with CA status
■ cpl_ur_err = Received completion with UR status
■ flt_q_cpl_last = Final completion for the transaction
■ flt_q_cpl_abort = Current completion is being aborted (trashed)
■ cpl_mlf_err = Malformed completion
■ flt_q_header_cpl_status[2:0] = Indicates the filtering result for the
current RX request or the completion status for the current RX
received completion.
❑ 0: =Successful Completion (SC)

❑ 1: Unsupported request (UR)

❑ 2: Configuration Retry (CRS)

❑ 4: Completer abort (CA)

■ flt_q_header_destination[1:0] = Destination interface.


❑ 0: Drop

❑ 1: TRGT0

❑ 2: TRGT1

❑ 3: Reserved

■ form_filt_ecrc_err = This TLP had an ECRC error


■ form_filt_malform_tlp_err = This TLP is malformed
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PCI Express SW Controller Databook SII: Diagnostic Control Signals

Port Name I/O Description

diag_status_bus[CX_DIAG_STATUS_BUS O... ■ form_filt_dllp_err = This TLP has a DataLink Layer Error (for
_WD-1:0]...(cont....) . example, LCRC)
■ form_filt_eot = End of TLP received this cycle
■ form_filt_dwen[NW-1:0] = Dword enables
■ form_filt_data[32*NW-1:0] = Packet data from receive Transaction
Layer
■ form_filt_dv = Packet is in payload stage
■ form_filt_hdr[127:0] = Header data (size of stored header is configu-
rable)
■ form_filt_hv = Information to the receive packet filter block is valid
RADM Diagnostic Dual Bus Selector.
■ form_filt_formation = Indicates which TLP was received first by the
controller for 256-bit configurations.
❑ 1: TLP #0 received first, see "RADM Diagnostic Bus 1"

❑ 0: TLP #1 received first, see "RADM Diagnostic Bus 0"

XADM Diagnostic Bus


■ active_grant[NCL+2-1:0] = Currently granted client (1-hot)
■ grant_ack[NCL+2-1:0] = This client has completed his request
(1-hot)
■ fc_cds_pass[(NCL+2)*NVC-1:0] = Credit check passed for each
request
■ arb_reqs[NCL+2-1:0] = Transmit requests from each client
CDM Diagnostic Bus
■ cfg_pbus_num[BUSNUM_WD-1:0] = Bus number; 8 bits per func-
tion when MULTI_DEVICE_AND_BUS_PER_FUNC_EN=1, else 8
bits in total.
■ cfg_pbus_dev_num[DEVNUM_WD-1:0] = Device number; 5 bits per
function when MULTI_DEVICE_AND_BUS_PER_FUNC_EN=1,
else 5 bits in total.
■ xdlh_replay_timeout_err = Retry timer expired [pulse]
■ xdlh_replay_num_rlover_err = Max retries exceeded [pulse]
■ rdlh_bad_dllp_err = Received DLLP with DataLink Layer error
[pulse]
■ rdlh_bad_tlp_err = Received TLP with DataLink Layer error [pulse]
■ rdlh_prot_err = DLLP protocol error (out of sequence DLLP) [pulse]
■ rtlh_fc_prot_err = Flow control protocol violation (watchdog timer)
[pulse]
■ rmlh_rcvd_err = Received PHY error this cycle [pulse]
■ int_xadm_fc_prot_err = Flow control update protocol violation (opt.
checks)
■ radm_cpl_timeout = An request failed to complete in the allotted time
■ radm_qoverflow[NVC-1:0] = Receive queue overflow. Normally
happens only when flow control advertisements are ignored

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SII: Diagnostic Control Signals PCI Express SW Controller Databook

Port Name I/O Description

diag_status_bus[CX_DIAG_STATUS_BUS O... ■ radm_unexp_cpl_err[NF-1:0] = Received an unexpected completion


_WD-1:0]...(cont.....) .. [pulse]
■ radm_rcvd_cpl_ur[NF-1:0] = Received a completion with UR status
■ radm_rcvd_cpl_ca[NF-1:0] = Received a completion with CA status
■ radm_rcvd_req_ca[NF-1:0] = Completer aborted request
■ radm_rcvd_req_ur[NF-1:0] = Received a request which device does
not support
■ radm_ecrc_err[NF-1:0] = Received a TLP with ECRC error
■ radm_mlf_tlp_err[NF-1:0] = Received a malformed TLP [pulse]
■ radm_rcvd_cpl_poisoned[NF-1:0] = Received a completion with
poisoned payload
■ radm_rcvd_wreq_poisoned[NF-1:0] = Received a write with
poisoned payload
■ cdm_lbc_ack[NF-1:0] = Local bus Acknowledge
■ lbc_cdm_wr[3:0] = Local bus Write enable (per byte)
■ lbc_cdm_cs[NF-1:0] = Local bus chip select
■ lbc_cdm_data[31:0] = Local bus Data
■ lbc_cdm_addr[31:0] = Local bus Address
■ cfg_sys_err_rc_cor = System Error caused by Correctable
Error.(One-clock-cycle pulse)(Tied 0 if not Root Complex)
■ cfg_sys_err_rc_nf = System Error caused by Non-Fatal
Error.(One-clock-cycle pulse)(Tied 0 if not Root Complex)
■ cfg_sys_err_rc_f = System Error caused by Fatal
Error.(One-clock-cycle pulse)(Tied 0 if not Root Complex)
Exists: DIAGNOSTIC_ENABLE
Synchronous To:
None,aux_clk,core_clk,perbitclk,radm_clk_g,ret_core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Electromechanical Signals

5.35 SII: Electromechanical Signals

sys_atten_button_pressed - - cfg_eml_control
sys_pre_det_state -
sys_mrl_sensor_state -
sys_pwr_fault_det -
sys_mrl_sensor_chged -
sys_pre_det_chged -
sys_cmd_cpled_int -
sys_eml_interlock_engaged -
nhp_pm_pme -

Table 5-35 SII: Electromechanical Signals

Port Name I/O Description

sys_atten_button_pressed[(NF-1):0] I Attention Button Pressed. Indicates that the system attention button was
pressed, sets the Attention Button Pressed bit in the Slot Status
Register. There is a separate sys_atten_button_pressed input bit for
each function in your controller configuration.
Exists: Always
Synchronous To: aux_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

sys_pre_det_state[(NF-1):0] I Presence Detect State. Indicates whether or not a card is present in the
slot:
■ 0: Slot is empty
■ 1: Card is present in the slot
There is a separate sys_pre_det_state input bit for each function in your
controller configuration.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

sys_mrl_sensor_state[(NF-1):0] I MRL Sensor State. Indicates the state of the manually-operated


retention latch (MRL) sensor:
■ 0: MRL is closed
■ 1: MRL is open
There is a separate sys_mrl_sensor_state input bit for each function in
your controller configuration.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

sys_pwr_fault_det[(NF-1):0] I Power Fault Detected. Indicates the power controller detected a power
fault at this slot. There is a separate sys_pwr_fault_det input bit for each
function in your controller configuration.
Exists: Always
Synchronous To: aux_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

sys_mrl_sensor_chged[(NF-1):0] I MRL Sensor Changed. Indicates that the state of MRL sensor has
changed. There is a separate sys_mrl_sensor_chged input bit for each
function in your controller configuration.
Exists: Always
Synchronous To: aux_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

sys_pre_det_chged[(NF-1):0] I Presence Detect Changed. Indicates that the state of card present
detector has changed. There is a separate sys_pre_det_chged input bit
for each function in your controller configuration.
Exists: Always
Synchronous To: aux_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Electromechanical Signals

Port Name I/O Description

sys_cmd_cpled_int[(NF-1):0] I Command completed Interrupt. Indicates that the Hot-Plug controller


completed a command. There is a separate sys_cmd_cpled_int input bit
for each function in your controller configuration.
Exists: Always
Synchronous To: aux_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

sys_eml_interlock_engaged[(NF-1):0] I System Electromechanical Interlock Engaged. Indicates whether the


system electromechanical interlock is engaged and controls the state of
the Electromechanical Interlock Status bit in the Slot Status register.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_eml_control[(NF-1):0] O Electromechanical Interlock Control. The state of the Electromechanical


Interlock Control bit in the Slot Control register.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

nhp_pm_pme[(NF-1):0] I Native Hot-Plug Event. Enables your application to notify the controller
of a native Hot-Plug event (applicable only in D1, D2, or D3hot). The
controller wakes up the device upon detecting a rising edge
nhp_pm_pme.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: FRS/DRS Messaging Signals PCI Express SW Controller Databook

5.36 SII: FRS/DRS Messaging Signals

app_drs_ready - - cfg_drs_msi
app_pf_frs_ready - - cfg_up_drs_to_frs
- pf_frs_grant

Table 5-36 SII: FRS/DRS Messaging Signals

Port Name I/O Description

app_drs_ready I Defers DRS messaging when set to '0'.


Exists: CX_RN_DRS_SUPPORTED
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_drs_msi[(NF-1):0] O DRS Message Received Interrupt Pulse. The DSP controller asserts the
cfg_drs_msi output when all of the following are true:
■ It receives a DRS message
■ PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CON-
TROL_LINK_STATUS_REG is 2'b01
■ MSI or MSI-X is enabled
Exists: CX_RN_DRS_SUPPORTED
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_up_drs_to_frs[(NF-1):0] O DRS to FRS Pulse. The DSP controller asserts the cfg_up_drs_to_frs
output and sends an FRS message with the reason code set to 'DRS
Message Received' when:
■ It receives a DRS message, and
■ PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CON-
TROL_LINK_STATUS_REG is 2'b10
Exists: (CX_RN_DRS_SUPPORTED) &&
(CX_RN_FRS_SUPPORTED)
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: FRS/DRS Messaging Signals

Port Name I/O Description

app_pf_frs_ready[(NF-1):0] I Defers FRS messaging when set to '0'.


Exists: CX_RN_FRS_SUPPORTED
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pf_frs_grant[(NF-1):0] O Indicator of when an FRS message for this function has been scheduled
for transmission.
Exists: CX_RN_FRS_SUPPORTED
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High (One clock pulse)
Validated by: app_pf_frs_ready asserted

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SII: General Core Control Signals PCI Express SW Controller Databook

5.37 SII: General Core Control Signals

rx_lane_flip_en - - cfg_vf_bme
tx_lane_flip_en - - cxs_ltssm_enable
app_sris_mode -
phy_type -
app_ltssm_enable -
device_type -
app_req_retry_en -
app_pf_req_retry_en -
app_dbi_ro_wr_disable -

Table 5-37 SII: General Core Control Signals

Port Name I/O Description

rx_lane_flip_en I Performs manual lane reversal for receive lanes. For use when
automatic lane reversal does not occur because lane 0 is not detected.
In most cases, rx_lane_flip_en should be wired to a static value at the
chip level. For more details, see 'Lane Reversal and Broken Lanes'. This
signal is only used in Conventional PCIe mode. When in M-PCIe mode,
mpcie_rx_lane_flip_en is used.
Exists: CX_LANE_FLIP_CTRL_EN
Synchronous To:
aux_clk,aux_clk_g,core_clk_ug,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

tx_lane_flip_en I Performs manual lane reversal for transmit lanes. For use when
automatic lane reversal does not occur because lane 0 is not detected.
In most cases, tx_lane_flip_en should be wired to a static value at the
chip level. For more details, see 'Lane Reversal and Broken Lanes'. This
signal is only used in Conventional PCIe mode. When in M-PCIe mode,
mpcie_tx_lane_flip_en is used.
Exists: CX_LANE_FLIP_CTRL_EN
Synchronous To:
aux_clk,aux_clk_g,core_clk_ug,pipe_clk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: General Core Control Signals

Port Name I/O Description

cfg_vf_bme[(INT_NVF-1):0] O Bus master enable bit from the Control Register in the PCI header of
each VF. Each bit field corresponds to one of the NVF virtual functions.
You can use the cfg_start_vfi output signal or the VF Index in 'Bus
Numbering Overview' index the corresponding bit field for a particular
VF.
Exists: (CX_SRIOV_ENABLE) && (INTERNAL_VF_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

app_sris_mode I SRIS operating mode:


■ 0b: non-SRIS mode
■ 1b: SRIS mode
Exists: CX_SRIS_SUPPORT
Synchronous To: aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_type I Indicates the PCIe operating mode of the controller. When you configure
the controller to support both Conventional PCIe and M-PCIe modes by
choosing the Selectable PHY setting (CX_PCIE_MODE =2), then you
must indicate to the controller which mode to operate in.
■ 1'b0: Conventional PCIe Mode.
■ 1'b1: M-PCIe mode
You have to completely reset the controller after you change this input.
The result is undefined if this signal is changed without reset.
Exists: CX_PCIE_MODE == DUAL_CMPCIE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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SII: General Core Control Signals PCI Express SW Controller Databook

Port Name I/O Description

app_ltssm_enable I Driven low by your application after cold, warm or hot reset to hold the
LTSSM in the Detect state until your application is ready for the link
training to begin. When your application has finished reprogramming the
controller configuration registers using the DBI, it asserts
app_ltssm_enable to allow the LTSSM to continue link establishment.
Can also be used to delay hot resetting of the controller until you have
read out any register status.
Cold Reset
■ Optionally hold LTSSM and delay link training, so that you can repro-
gram some registers through DBI.
❑ Set app_ltssm_enable =0 before your application de-asserts
Power-On Reset (power_up_rst_n). Best way is to set app_ltss-
m_enable =0 at power-up or at assertion of core_rst_n.
❑ Wait for de-assertion of core_rst_n, sticky_rst_n, and non_-
sticky_rst_n.
❑ Write any register through DBI.

❑ Set app_ltssm_enable =1.

❑ Link training starts.

Hot Reset (Link Down Reset)


■ Optionally delay reset of the controller, so that you can read some
registers through DBI.
❑ Set app_ltssm_enable =0 immediately (combinatorially) upon
falling edge of smlh_req_rst_not.
❑ Keep app_ltssm_enable =0 until bridge finishes "flushing mode".

❑ Read any register through DBI.

❑ Set app_ltssm_enable =1.

❑ Reset of controller begins (sticky_rst is not asserted).

■ Optionally hold LTSSM and delay link training, so that you can repro-
gram some registers through DBI.
❑ Set app_ltssm_enable =0 immediately (combinatorially) upon
falling edge of core_rst_n.
❑ Write any register through DBI.

❑ Set app_ltssm_enable =1.

❑ Link training starts.

■ Note:For Hot Reset, you can do both or either of the above (delay
reset and/or delay link training). If you do both, you must do in order
presented.
Note:You must only de-assert this signal using one of the recommended
timings described in the "Reset Requirements" section in the
Architecture chapter of the Databook

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PCI Express SW Controller Databook SII: General Core Control Signals

Port Name I/O Description

app_ltssm_enable...(cont.) I. . To do otherwise (that is, de-assert it outside of the Detect LTSSM


state) causes the controller to be reset and the LTSSM moves
immediately back to the Detect state. This transition is outside of the
PCIe Specification and it might cause a PIPE protocol violation.
Exists: Always
Synchronous To: aux_clk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cxs_ltssm_enable O CXS Reset Controller LTSSM enable


Exists: CX_CXS_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

device_type[3:0] I Device/port type. Indicates the specific type of this PCI Express
function. It is also used to set the 'Device/Port Type' field of the 'PCI
Express Capabilities Register'. The controller uses this input to
determine the operating mode of the controller at run time. Defined
encodings are:
■ 4'b0101: Upstream port of switch
■ 4'b0110: downstream port of switch
All other encodings (including those for PCI/PCI-X bridges and RC
Integrated endpoint) are not supported. If CX_CROSSLINK_ENABLE is
defined and when smlh_crosslink_active is '1' then the value
device_type is modified as follows before being used internally in the
controller:
■ if device_type =4'b0101 then device_type =4'b0110
■ if device_type =4'b0110 then device_type =4'b0101
Exists: Always
Synchronous To:
aux_clk,aux_clk_g,radm_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

app_req_retry_en I Provides a capability to defer incoming configuration requests until


initialization is complete. When app_req_retry_en is asserted, the
controller completes incoming configuration requests with a
configuration request retry status. Other incoming requests are not
affected. When the Readiness Notification mechanism is supported,
DRS messaging is blocked when app_req_retry_en=1. When
app_req_retry_en=0 and app_drs_ready=1, the controller
autonomously transmits a DRS message when the link transitions from
DL_Down to DL_Up.
Exists: Always
Synchronous To: radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High (for CRS)
Validated by: Not validated by another signal

app_pf_req_retry_en[(NF-1):0] I Provides a per Physical Function (PF) capability to defer incoming


configuration requests until initialization is complete. When
app_pf_req_retry_en is asserted for a certain PF, the controller
completes incoming configuration requests with a configuration request
retry status; other incoming requests are not affected. When
app_req_retry_en is also asserted, the controller completes incoming
configuration requests with a configuration request retry status for ALL
PFs and VFs, regardless of the status of
app_pf_req_retry_en/app_vf_req_retry_en. When the Readiness
Notification mechanism is supported, DRS messaging is blocked when
app_pf_req_retry_en =1 for at least one PF. The same applies when
app_pf_req_retry_en =0 for all PFs, but app_req_retry_en is asserted.
When app_pf_req_retry_en =0 for a certain PF, and app_req_retry_en
=0, and app_drs_ready =1, the controller autonomously transmits a
DRS message when the link transitions from DL_Down to DL_Up.
Exists: Always
Synchronous To: radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High (for CRS)
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: General Core Control Signals

Port Name I/O Description

app_dbi_ro_wr_disable I DBI Read-only Write Disable


■ 0: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is
read-write.
■ 1: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is
forced to 0 and is read-only.
Exists: !CX_PL_REG_DISABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: General Messaging Reception Signals PCI Express SW Controller Databook

5.38 SII: General Messaging Reception Signals

upstream_surprise_down - - radm_vendor_msg
- radm_msg_payload
- radm_msg_req_id
- cfg_send_cor_err
- cfg_send_nf_err
- cfg_send_f_err
- surprise_down_err
- cfg_br_ctrl_serren

Table 5-38 SII: General Messaging Reception Signals

Port Name I/O Description

radm_vendor_msg[(FX_TLP-1):0] O One-cycle pulse that indicates the controller received a vendor-defined


message. The controller makes the message header available the
radm_msg_payload output. When FX_TLP > 1 and when two messages
of the same type are received in the same clock cycle (back-to-back),
then both bits are asserted.
Exists: Always
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: General Messaging Reception Signals

Port Name I/O Description

radm_msg_payload[((FX_TLP*64)-1):0] O Received message header information.


When a vendor-defined or ltr messageis received (radm_vendor_msg=1
or radm_ltr_msg=1), the controller maps radm_msg_payload to the Rx
TLP header dwords as follows:
When RX_TLP =1
■ [31:0] = bytes 12-15 (4th dword), where [7:0] =byte 15
■ [63:32] = bytes 8-11 (3rd dword)
When RX_TLP >1 and radm_vendor_msg[1:0] ={01}
■ [31:0] = bytes 12-15 (4th dword) of 1st Message, where [7:0] =byte
15
■ [63:32] = bytes 8-11 (3rd dword)
■ [127:96] = 'X'
When RX_TLP >1 and radm_vendor_msg[1:0] ={10}
■ [95:64] = bytes 12-15 (4th dword) of 1st Message, where [7:0] =byte
15
■ [127:96] = bytes 8-11 (3rd dword)
■ [63:0] = 'X'
When RX_TLP >1 and radm_vendor_msg[1:0] =11
■ [31:0] = bytes 12-15 (4th dword) of 2nd Message, where [7:0] =byte
15
■ [63:32] = bytes 8-11 (3rd dword)
■ [95:64] = bytes 12-15 (4th dword) of 1st Message, where [7:0] =byte
15
■ [127:96] = bytes 8-11 (3rd dword)
When any other type of message is received, the controller maps
radm_msg_payload to the Rx TLP header dwords as follows:
When RX_TLP =1
■ [31:0] = DW Data of Message
■ [63:32] = '0'
When RX_TLP >1 and radm_vendor_msg[1:0] ={01||10}
■ [31:0] = DW Data of 2nd Message
■ [63:32] = '0'
■ [127:96] = 'X'
When RX_TLP >1 and radm_vendor_msg[1:0] =11
■ [31:0] = DW Data of 2nd Message
■ [63:32] = '0'
■ [95:64] = DW Data of 1st Message
■ [127:96] = '0'
For more details, see "Routing of Received Messages" and the
"Endianness" chapters.
Exists: Always
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Any of {radm_vendor_msg, radm_msg_ltr,
radm_msg_unlock, radm_nonfatal_err, radm_fatal_err,
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SII: General Messaging Reception Signals PCI Express SW Controller Databook

Port Name I/O Description

radm_msg_req_id[((FX_TLP*16)-1):0] O The requester ID of the received Message.


■ [15:8]: Bus number
■ [7:3]: Device number
■ [2:0]: Function number
Exists: Always
Synchronous To: aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Any of {radm_vendor_msg, radm_msg_ltr,
radm_msg_unlock, radm_nonfatal_err, radm_fatal_err,
radm_correctable_err, radm_pm_pme, radm_pm_to_ack,
radm_pm_turnoff,, radm_msg_obff, radm_msg_idle,
radm_msg_cpu_active} is asserted

cfg_send_cor_err[(NF-1):0] O Send Correctable Error. The controller detected a correctable error at its
receive path. This error signal is designed to allow the switch to report
its detect receive error from the downstream port to the upstream port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_send_nf_err[(NF-1):0] O Send Non-Fatal Error. The controller detected a non-fatal error at its
receive path. This error signal is designed to allow the switch to report
its detect receive error from the downstream port to the upstream port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_send_f_err[(NF-1):0] O Send Fatal Error. The controller detected a fatal error at its receive path.
This error signal is designed to allow the switch to report its detect
receive error from the downstream port to the upstream port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

upstream_surprise_down I Indicates that a surprise down event is occurring upstream.


Exists: SURPRISE_LINK_DOWN_SUPPORTED
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

surprise_down_err[(NF-1):0] O Indicates that a surprise down event is occurring in the controller.


Exists: SURPRISE_LINK_DOWN_SUPPORTED
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_br_ctrl_serren[(NF-1):0] O PF's SERR# Enable registers value in Bridge Control Register of Type1
Header. You can use this value to control forwarding of ERR_COR,
ERR_NONFATAL, and ERR_FATAL from secondary to primary.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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5.39 SII: Interrupt Signals

sys_int - - cfg_vpd_int
xal_xmt_cpl_ca - - cfg_pcie_cap_int_msg_num
xal_rcvd_cpl_ca - - radm_inta_asserted
xal_rcvd_cpl_ur - - radm_intb_asserted
dp_inta - - radm_intc_asserted
dp_intb - - radm_intd_asserted
dp_intc - - radm_inta_deasserted
dp_intd - - radm_intb_deasserted
- radm_intc_deasserted
- radm_intd_deasserted
- hp_pme
- hp_int
- hp_msi
- cfg_link_auto_bw_int
- cfg_link_auto_bw_msi
- cfg_bw_mgt_int
- cfg_bw_mgt_msi
- cfg_link_eq_req_int
- assert_inta_grt
- assert_intb_grt
- assert_intc_grt
- assert_intd_grt
- deassert_inta_grt
- deassert_intb_grt
- deassert_intc_grt
- deassert_intd_grt
- cfg_int_pin
- cfg_int_disable
- cfg_safety_corr
- cfg_safety_uncorr

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Table 5-39 SII: Interrupt Signals

Port Name I/O Description

cfg_vpd_int[(NF-1):0] O This pin is set as a one cycle pulse to notify your application to read the
VPD registers. The sequence of events for a VPD read cycle is:
■ The controller sends a request (single-cycle pulse of the cfg_vpd_int
signal) to your application to read or write vital product data.
■ Your application reads the VPD Control and Capabilities register.
■ The VPD Flag (bit 31) is set to '0' indicating a read request. Your
application fetches four bytes of data from the VPD Address location
and transfers this to the VPD Data register.
■ Your application sets the VPD Flag bit to '1' indicating the request is
complete.
The sequence of events for a VPD write cycle is:
■ The controller sends a request (single-cycle pulse of the cfg_vpd_int
signal) to your application to read or write vital product data.
■ Your application reads the VPD Control and Capabilities register.
■ The VPD Flag (bit 31) is set to '1' indicating a write request. Your
application reads the VPD Data register and transfers this to the
location specified by the VPD Address register.
■ Your application sets the VPD Flag bit to '0' indicating the request is
complete.
Exists: VPD_CAP_ENABLE
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High (pulse)
Validated by: Not validated by another signal.

sys_int[(NF-1):0] I When sys_int goes from low to high, the controller generates an
Assert_INTx Message. When sys_int goes from high to low, the
controller generates a Deassert_INTx Message.
There is a separate sys_int input bit for each function in your controller
configuration. The Interrupt Pin register for the corresponding function
determines which INTx Message the controller generates (INTA, INTB,
INTC, or INTD). Legacy and native PCIe devices capable of generating
an interrupt must support both Assert_INTx/Deassert_INTx and MSI or
MSI-X. sys_int is intended to generate a message that emulates the
legacy PCI Interrupts.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_pcie_cap_int_msg_num[((NF*5)-1):0] O From bits [13:9] of the PCI Express Capabilities register, used when MSI
or MSI-X is enabled. Assertion of hp_msi or cfg_pme_msi along with a
value cfg_pcie_cap_int_msg_num is equivalent to the controller
receiving an MSI with the cfg_pcie_cap_int_msg_num value as the MSI
vector.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_inta_asserted O One-clock-cycle pulse that indicates that the controller received an


Assert_INTA Message from the downstream device.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_intb_asserted O One-clock-cycle pulse that indicates that the controller received an


Assert_INTB Message from the downstream device.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_intc_asserted O One-clock-cycle pulse that indicates that the controller received an


Assert_INTC Message from the downstream device.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

radm_intd_asserted O One-clock-cycle pulse that indicates that the controller received an


Assert_INTD Message from the downstream device.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_inta_deasserted O One-clock-cycle pulse that indicates that the controller received a


Deassert_INTA Message from the downstream device.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_intb_deasserted O One-clock-cycle pulse that indicates that the controller received a


Deassert_INTB Message from the downstream device.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_intc_deasserted O One-clock-cycle pulse that indicates that the controller received a


Deassert_INTC Message from the downstream device.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_intd_deasserted O One-clock-cycle pulse that indicates that the controller received a


Deassert_INTD Message from the downstream device.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

hp_pme[(NF-1):0] O The controller asserts hp_pme when all of the following conditions are
true:
■ The PME Enable bit in the Power Management Control and Status
register is set to 1.
■ Any bit in the Slot Status register transitions from 0 to 1 and the asso-
ciated event notification is enabled in the Slot Control register.
The controller does not check if the PM state is D1, D2, or D3hot. It is up
to your application to check the value pm_dstate to make sure the
device is in D1, D2, or D3hot. There is one bit of hp_pme for each
configured function. The controller pulses the hp_pme output only when
any hot plug status bit changes from 0 to 1 (as is hp_msi). hp_int stays
asserted as long as the status bit is set. In addition, it asserts hp_pme
only if PME is enabled, but it does not matter if hot-plug interrupts are
enabled.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (pulse)
Validated by: Not validated by another signal

hp_int[(NF-1):0] O The controller asserts hp_int when all of the following conditions are
true:
■ The INTx Assertion Disable bit in the Command register is 0.
■ Hot-Plug interrupts are enabled in the Slot Control register.
■ Any bit in the Slot Status register is equal to 1, and the associated
event notification is enabled in the Slot Control register.
There is one bit of hp_int for each configured function.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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Port Name I/O Description

hp_msi[(NF-1):0] O The controller asserts hp_msi (as a one-cycle pulse) when the logical
AND of the following conditions transitions from false to true:
■ MSI or MSI-X is enabled.
■ Hot-Plug interrupts are enabled in the Slot Control register.
■ Any bit in the Slot Status register transitions from 0 to 1 and the asso-
ciated event notification is enabled in the Slot Control register.
There is one bit of hp_int for each configured function. The controller
pulses the hp_msi output only when any of the hot plug status bits
change from 0 to 1 (as is hp_pme).
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (pulse)
Validated by: Not validated by another signal

cfg_link_auto_bw_int O The controller asserts cfg_link_auto_bw_int when all of the following


conditions are true:
■ The INTx assertion disable bit in the Command register is 0, and
■ The Link Autonomous Bandwidth Interrupt Enable bit in the Link
Control register is set to 1, and
■ The Link Autonomous Bandwidth Interrupt Status bit in the Link
Status register is set to 1.
The cfg_link_auto_bw_msi output is a pulse signal (only asserted for
one clock cycle); but cfg_link_auto_bw_int is a level signal. For
upstream port: Reserved.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_link_auto_bw_msi O The controller sets this pin when following conditions are true:
■ MSI or MSI-X is enabled.
■ The Link Autonomous Bandwidth Status register (Link Status
register bit 15) is updated.
■ The Link Autonomous Bandwidth Interrupt Enable (Link Control
register bit 11) is set.
The controller does not check if the associated MSI vector (asserted
cfg_pcie_cap_int_msg_num) is unmasked. It is up to the application to
check whether the vector is masked or unmasked. For upstream port:
Reserved. <ct:CX_IS_EP>Reserved.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (pulse)
Validated by: Not validated by another signal

cfg_bw_mgt_int O The controller asserts cfg_bw_mgt_int when all of the following


conditions are true:
■ The INTx Assertion Disable bit in the Command register is 0, and
■ The Bandwidth Management Interrupt Enable bit in the Link Control
register is set to 1, and
■ The Bandwidth Management Interrupt Status bit in the Link Status
register is set to 1.
The cfg_bw_mgt_msi output is a pulse signal (only asserted for one
clock cycle); but cfg_bw_mgt_int is a level signal.
For upstream port: Reserved.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_bw_mgt_msi O The controller sets this pin when following conditions are true:
■ MSI or MSI-X is enabled.
■ The Link Bandwidth Management Status register (Link Control
Status register bit 14) is updated
■ The Link Bandwidth Management Interrupt Enable (Link Control
register bit 10) is set.
reuse-pragma beginAttr Description This pin is set as a notification
when the Link Bandwidth Management Status register (Link Status
register bit 14) is updated and the Link Bandwidth Management
Interrupt Enable (Link Control register bit 10) is set and in addition the
msi or msix aare enabled . This bit is not applicable to, and is reserved,
for endpoint devices and upstream ports of Switches.
For upstream port: Reserved. <ct:CX_IS_EP>Reserved.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (pulse)
Validated by: Not validated by another signal

cfg_link_eq_req_int O Interrupt indicating to your application that the Link Equalization


Request bit in the Link Status 2 Register has been set and the Link
Equalization Request Interrupt Enable (Link Control 3 Register bit 1) is
set.
Exists: (CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

xal_xmt_cpl_ca[(NF-1):0] I Transmitted completion with CA Status (DSP). A one-clock-cycle pulse


asserted when the controller transmits a completion with CA status for a
request it received.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

xal_rcvd_cpl_ca[(NF-1):0] I Received completion with CA Status (DSP). A one-clock-cycle pulse


asserted when the controller receives a completion with CA status in
response to a request from the controller.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xal_rcvd_cpl_ur[(NF-1):0] I Received completion with UR Status (DSP). A one-clock-cycle pulse


asserted when the controller receives a completion with UR status in
response to a request from the controller.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

dp_inta I INTA From downstream port. Indicates to an upstream port the state of
your application logic's "Virtual Interrupt" wire. When legacy interrupts
are enabled, a rising edge this signal causes the upstream port to send
an Assert_INTA message; a falling edge causes the port to send a
Deassert_INTA message.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

dp_intb I INTB From downstream port. Indicates to an upstream port the state of
your application logic's "Virtual Interrupt" wire. When legacy interrupts
are enabled, a rising edge this signal causes the upstream port to send
an Assert_INTB message; a falling edge causes the port to send a
Deassert_INTB message.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

dp_intc I INTC From downstream port. Indicates to an upstream port the state of
your application logic's "Virtual Interrupt" wire. When legacy interrupts
are enabled, a rising edge this signal causes the upstream port to send
an Assert_INTC message; a falling edge causes the port to send a
Deassert_INTC message.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

dp_intd I INTD From downstream port. Indicates to an upstream port the state of
your application logic's "Virtual Interrupt" wire. When legacy interrupts
are enabled, a rising edge this signal causes the upstream port to send
an Assert_INTD message; a falling edge causes the port to send a
Deassert_INTD message.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

assert_inta_grt O The signal assert_inta_grt is a one-clock-cycle pulse that indicates that


the controller sent an Assert_INTA Message to the upstream device.
Exists: CX_SYS_INT_GRANT_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: N/A

assert_intb_grt O The signal assert_intb_grt is a one-clock-cycle pulse that indicates that


the controller sent an Assert_INTB Message to the upstream device.
Exists: CX_SYS_INT_GRANT_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: N/A

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Port Name I/O Description

assert_intc_grt O The signal assert_intc_grt is a one-clock-cycle pulse that indicates that


the controller sent an Assert_INTC Message to the upstream device.
Exists: CX_SYS_INT_GRANT_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: N/A

assert_intd_grt O The signal assert_intd_grt is a one-clock-cycle pulse that indicates that


the controller sent an Assert_INTD Message to the upstream device.
Exists: CX_SYS_INT_GRANT_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: N/A

deassert_inta_grt O The signal deassert_inta_grt is a one-clock-cycle pulse that indicates


that the controller sent an Deassert_INTA Message to the upstream
device.
Exists: CX_SYS_INT_GRANT_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: N/A

deassert_intb_grt O The signal deassert_intb_grt is a one-clock-cycle pulse that indicates


that the controller sent an Deassert_INTB Message to the upstream
device.
Exists: CX_SYS_INT_GRANT_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: N/A

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Port Name I/O Description

deassert_intc_grt O The signal deassert_intc_grt is a one-clock-cycle pulse that indicates


that the controller sent an Deassert_INTC Message to the upstream
device.
Exists: CX_SYS_INT_GRANT_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: N/A

deassert_intd_grt O The signal deassert_intd_grt is a one-clock-cycle pulse that indicates


that the controller sent an Deassert_INTD Message to the upstream
device.
Exists: CX_SYS_INT_GRANT_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: N/A

cfg_int_pin[((8*NF)-1):0] O The cfg_int_pin indicates the configured value for the Interrupt Pin
Register field in the BRIDGE_CTRL_INT_PIN_INT_LINE register.
Exists: CX_SYS_INT_GRANT_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: N/A

cfg_int_disable[(NF-1):0] O When high a functions ability to generate INTx messages is Disabled


Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_safety_corr O The controller asserts cfg_safety_corr when a PCIe protocol correctable


error or a Data Path protection correctable error is indicated and the
associated mask for that event is not set.
Exists: CX_AUTOMOTIVE_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_safety_uncorr O The controller asserts cfg_safety_uncorr when any of the internal safety
mechanisms reports an uncorrectable error and the associated mask for
that event is not set.
Exists: CX_AUTOMOTIVE_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Link Reset/Status Signals

5.40 SII: Link Reset/Status Signals

- smlh_link_up
- smlh_req_rst_not
- link_req_rst_not
- cfg_link_dis

Table 5-40 SII: Link Reset/Status Signals

Port Name I/O Description

smlh_link_up O PHY Link up/down indicator:


■ 1: Link is up
■ 0: Link is down
Exists: Always
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

smlh_req_rst_not O Early version of the link_req_rst_not signal. For more details, see the
'Warm and Hot Resets' section in the Architecture chapter of the
Databook.
Exists: Always
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: Low (high-to-low transition )
Validated by: Not validated by another signal

link_req_rst_not O Reset request because the link has gone down or the controller
received a hot-reset request. A low level indicates that the controller is
requesting external logic to reset the controller because the PHY link is
down. For more details, see the "Hot Reset" section in the Architecture
chapter of the Databook.
Exists: Always
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_link_dis O The controller asserts cfg_link_dis when Link Disable bit in the Link
Control register is set to 1. The cfg_link_dis output is a level signal.
For upstream port: Reserved.
Exists: SNPS_RSVDPARAM_33
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: LTR Message Generation Signals

5.41 SII: LTR Message Generation Signals

app_ltr_msg_req - - app_ltr_msg_grant
app_ltr_msg_latency - - app_ltr_latency
app_ltr_msg_func_num -

Table 5-41 SII: LTR Message Generation Signals

Port Name I/O Description

app_ltr_msg_req I Indicates that your application is requesting to send an LTR message.


Once asserted, app_ ltr_msg_req must remain asserted until the
controller asserts app_ltr_msg_grant.
Exists: CX_LTR_M_ENABLE
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_ltr_msg_grant O Indicates that the controller has accepted your request to send an LTR
message.
Exists: CX_LTR_M_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_ltr_msg_req is asserted

app_ltr_msg_latency[31:0] I LTR message that your application is requesting to send. The message
format is defined in the PCI Express Specification.
Exists: CX_LTR_M_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_ltr_msg_req is asserted

app_ltr_msg_func_num[(PF_WD-1):0] I Function number in your application that is requesting to send an LTR


message. Function numbering starts at '0'.
Exists: CX_LTR_M_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_ltr_msg_req is asserted

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SII: LTR Message Generation Signals PCI Express SW Controller Databook

Port Name I/O Description

app_ltr_latency[31:0] O The current LTR values reported and in-use by the downstream device.
■ For a downstream device, when LTR is disabled, or when any func-
tion is directed to a non-D0 state, if a device had previously reported
one or both latency fields with the Requirement bit set, the applica-
tion must send a new LTR Message with both Requirement bits
clear.
■ For an upstream device, it reflects the captured LTR values from
received LTR message, one clock cycle after the controller asserts
the radm_msg_ltr output. When RX_TLP > 1 and when two
messages of the same type are received in the same clock cycle,
then this output reflects the second captured message.
For more details, see 'Port Logic Registers: Latency Tolerance
Reporting (LTR) Registers'.
Exists: CX_LTR_M_ENABLE
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: For a downstream device, not validated by another signal

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PCI Express SW Controller Databook SII: LTR Message Reception Signals

5.42 SII: LTR Message Reception Signals

- radm_msg_ltr

Table 5-42 SII: LTR Message Reception Signals

Port Name I/O Description

radm_msg_ltr O One-clock-cycle pulse that indicates that the controller received an LTR
message. The controller makes the message header available the
radm_msg_payload output. It is also available the app_ltr_latency
output. When RX_TLP > 1 and when two messages of the same type
are received in the same clock cycle (back-to-back), then no separate
indication is given for the second message.
Exists: CX_LTR_M_ENABLE
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: Miscellaneous Signals PCI Express SW Controller Databook

5.43 SII: Miscellaneous Signals

- cfg_2nd_reset

Table 5-43 SII: Miscellaneous Signals

Port Name I/O Description

cfg_2nd_reset O Secondary Bus Reset. Indicates that your application has requested this
downstream port to start Link hot reset. This signal is asserted when
your application writes to the Secondary Bus Reset field (bit 6) of the
Bridge Control Register (Offset 0x3E) in the Type 1 Configuration Space
header. Setting this bit triggers a hot reset the corresponding PCI
Express port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: OBFF Message Generation Signals

5.44 SII: OBFF Message Generation Signals

app_obff_idle_msg_req - - app_obff_msg_grant
app_obff_obff_msg_req -
app_obff_cpu_active_msg_req -

Table 5-44 SII: OBFF Message Generation Signals

Port Name I/O Description

app_obff_msg_grant O Indicates that the controller has accepted your request to generate an
OBFF message. Only usable in a downstream port
Exists: CX_OBFF_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: any of app_obff_*msg_req are asserted

app_obff_idle_msg_req I Request from your application to generate an 'IDLE' OBFF message.


Only usable in a downstream port.
Exists: CX_OBFF_ENABLE
Synchronous To: core_clk,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_obff_obff_msg_req I Request from your application to generate an 'OBFF' OBFF message.


Only usable in a downstream port.
Exists: CX_OBFF_ENABLE
Synchronous To: core_clk,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_obff_cpu_active_msg_req I Request from your application to generate a 'CPU Active' OBFF


message. Only usable in a downstream port.
Exists: CX_OBFF_ENABLE
Synchronous To: core_clk,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: OBFF Message Reception Signals PCI Express SW Controller Databook

5.45 SII: OBFF Message Reception Signals

- radm_msg_idle
- radm_msg_obff
- radm_msg_cpu_active

Table 5-45 SII: OBFF Message Reception Signals

Port Name I/O Description

radm_msg_idle O One-clock-cycle pulse that indicates that the controller received an


'IDLE' OBFF message. When RX_TLP > 1 and when two messages of
the same type are received in the same clock cycle (back-to-back), then
no separate indication is given for the second message. Only usable in
an upstream port
Exists: CX_OBFF_ENABLE
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_msg_obff O One-clock-cycle pulse that indicates that the controller received an


'OBFF' OBFF message. When RX_TLP > 1 and when two messages of
the same type are received in the same clock cycle (back-to-back), then
no separate indication is given for the second message. Only usable in
an upstream port
Exists: CX_OBFF_ENABLE
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_msg_cpu_active O One-clock-cycle pulse that indicates that the controller received a 'CPU
Active' OBFF message. When RX_TLP > 1 and when two messages of
the same type are received in the same clock cycle (back-to-back), then
no separate indication is given for the second message. Only usable in
an upstream port
Exists: CX_OBFF_ENABLE
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: PM, Unlock, and Error Messages Signals

5.46 SII: PM, Unlock, and Error Messages Signals

apps_pm_xmt_turnoff - - radm_msg_unlock
app_unlock_msg - - radm_correctable_err
all_dwsp_rcvd_toack_msg - - radm_nonfatal_err
- radm_fatal_err
- radm_pm_pme
- radm_pm_to_ack
- radm_pm_turnoff
- pm_req_dwsp_turnoff

Table 5-46 SII: PM, Unlock, and Error Messages Signals

Port Name I/O Description

apps_pm_xmt_turnoff I Request from your application to generate a PM_Turn_Off message.


You must assert this signal for one clock cycle. The controller does not
return an acknowledgment or grant signal. You must not pulse the same
signal again, until the previous message has been transmitted.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_unlock_msg I Request from your application to generate an Unlock message. You


must assert this signal for one clock cycle. The controller does not
return an acknowledgment or grant signal. You must not pulse the same
signal again, until the previous message has been transmitted.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_msg_unlock O One-cycle pulse that indicates that the controller received an Unlock
message. When RX_TLP > 1 and when two messages of the same type
are received in the same clock cycle (back-to-back), then no separate
indication is given for the second message.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: PM, Unlock, and Error Messages Signals PCI Express SW Controller Databook

Port Name I/O Description

radm_correctable_err O One-clock-cycle pulse that indicates that the controller received an


ERR_COR message. The controller makes the message header
available the radm_msg_payload output.
Exists: Always
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_nonfatal_err O One-clock-cycle pulse that indicates that the controller received an


ERR_NONFATAL message.
Exists: Always
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_fatal_err O One-clock-cycle pulse that indicates that the controller received an


ERR_FATAL message.
Exists: Always
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_pm_pme O One-clock-cycle pulse that indicates that the controller received a


PM_PME message.
Exists: Always
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

radm_pm_to_ack O One-clock-cycle pulse that indicates that the controller received a


PME_TO_Ack message. Upstream port: Reserved.
Exists: Always
Synchronous To: aux_clk,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: PM, Unlock, and Error Messages Signals

Port Name I/O Description

radm_pm_turnoff O One-clock-cycle pulse that indicates that the controller received a PME
Turnoff message. When RX_TLP > 1 and when two messages of the
same type are received in the same clock cycle (back-to-back), then no
indication is given for the second message.
Exists: Always
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

all_dwsp_rcvd_toack_msg I All downstream ports received PME Turnoff Acknowledge. Indicates to


an upstream switch port that all downstream switch ports have received
a PME_TO_Ack message. When configured as an upstream switch
port, the controller generates a PME_TO_Ack message to the upstream
device when all_dwsp_rcvd_toack_msg is asserted. You must assert
this signal for one clock cycle. The controller does not return an
acknowledgment or grant signal. You must not pulse the same signal
again, until the previous message has been transmitted.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_req_dwsp_turnoff O Request downstream port PME Turn Off. Asserted by upstream switch
port when it has received a PME_Turn_Off message from the upstream
device. Your application can:
■ Respond to pm_req_dwsp_turnoff assertion by generating
PME_Turn_Off messages to all downstream ports, or
■ Ignore pm_req_dwsp_turnoff and, instead of generating a
PME_Turn_Off message in response to pm_req_dwsp_turnoff, pass
the received PME_Turn_Off message through to the downstream
ports.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: Power Management Signals PCI Express SW Controller Databook

5.47 SII: Power Management Signals

outband_pwrup_cmd - - pm_curnt_state
apps_pm_xmt_pme - - smlh_ltssm_state
sys_aux_pwr_det - - wake
app_req_entr_l1 - - local_ref_clk_req_n
app_ready_entr_l23 - - pm_dstate
app_req_exit_l1 - - pm_pme_en
app_xfer_pending - - pm_linkst_in_l0s
all_dwsp_in_l1 - - pm_linkst_in_l1
all_dwsp_in_rl0s - - pm_linkst_in_l2
upsp_in_rl0s - - pm_linkst_l2_exit
one_dwsp_exit_l1 - - pm_master_state
one_dwsp_exit_l23 - - pm_slave_state
clkreq_in_n - - pm_l1sub_state
app_clk_pm_en - - pm_status
test_bypass_lp - - aux_pm_en
ack_en_vmain - - pm_linkst_in_l1sub
app_l1_pwr_off_en - - cfg_l1sub_en
save_state_ack - - pm_en_vmain_n
restore_state_ack - - pm_en_vmain
app_l1sub_disable - - pm_save_state_req
- pm_restore_state_req
- pm_req_iso_vmain_to_vaux
- pm_req_slv_iso
- pm_req_mstr_iso
- pm_req_dbi_iso
- pm_l1_entry_started

Table 5-47 SII: Power Management Signals

Port Name I/O Description

outband_pwrup_cmd[(NF-1):0] I Wake Up. If PME is enabled and PME support is configured for current
PMCSR D-state asserting this signal causes the controller to wake from
either L1 or L2 state. When the controller has transitioned back to the L0
state it transmits a PME message and set the PME_Status. There is a
separate outband_pwrup_cmd input bit for each function in your
controller configuration. This port is functionally identical to
apps_pm_xmt_pme. Upon receiving the PME message the root
complex should clear the PME_Status and change the D-state back to
D0.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Power Management Signals

Port Name I/O Description

apps_pm_xmt_pme[(NF-1):0] I Wake Up. If PME is enabled and PME support is configured for current
PMCSR D-state asserting this signal causes the controller to wake from
either L1 or L2 state. When the controller has transitioned back to the L0
state it transmits a PME message and set the PME_Status. Upon
receiving the PME message the root complex should clear the
PME_Status and change the D-state back to D0.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

sys_aux_pwr_det I Auxiliary Power Detected. Used to report to the host software that
auxiliary power (Vaux) is present.
Exists: Always
Synchronous To: aux_clk_g,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_curnt_state[2:0] O Indicates the current power state. The pm_curnt_state output is


intended for debugging purposes, not for system operation.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: Power Management Signals PCI Express SW Controller Databook

Port Name I/O Description

smlh_ltssm_state[5:0] O Current state of the LTSSM. Encoding is defined as follows:


■ 6'h00: S_DETECT_QUIET
■ 6'h01: S_DETECT_ACT
■ 6'h02: S_POLL_ACTIVE
■ 6'h03: S_POLL_COMPLIANCE
■ 6'h04: S_POLL_CONFIG
■ 6'h05: S_PRE_DETECT_QUIET
■ 6'h06: S_DETECT_WAIT
■ 6'h07: S_CFG_LINKWD_START
■ 6'h08: S_CFG_LINKWD_ACEPT
■ 6'h09: S_CFG_LANENUM_WAI
■ 6'h0A: S_CFG_LANENUM_ACEPT
■ 6'h0B: S_CFG_COMPLETE
■ 6'h0C: S_CFG_IDLE
■ 6'h0D: S_RCVRY_LOCK
■ 6'h0E: S_RCVRY_SPEED
■ 6'h0F: S_RCVRY_RCVRCFG
■ 6'h10: S_RCVRY_IDLE
■ 6'h11: S_L0
■ 6'h12: S_L0S
■ 6'h13: S_L123_SEND_EIDLE
■ 6'h14: S_L1_IDLE
■ 6'h15: S_L2_IDLE
■ 6'h16: S_L2_WAKE
■ 6'h17: S_DISABLED_ENTRY
■ 6'h18: S_DISABLED_IDLE
■ 6'h19: S_DISABLED
■ 6'h1A: S_LPBK_ENTRY
■ 6'h1B: S_LPBK_ACTIVE
■ 6'h1C: S_LPBK_EXIT
■ 6'h1D: S_LPBK_EXIT_TIMEOUT
■ 6'h1E: S_HOT_RESET_ENTRY
■ 6'h1F: S_HOT_RESET
■ 6'h20: S_RCVRY_EQ0
■ 6'h21: S_RCVRY_EQ1
■ 6'h22: S_RCVRY_EQ2
■ 6'h23: S_RCVRY_EQ3
Exists: Always
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Power Management Signals

Port Name I/O Description

wake O Wake Up. Wake up from power management unit. The controller
generates wake to request the system to restore power and clock when
a wakeup event has been detected such as apps_pm_xmt_pme or
outband_pwrup_cmd. The wake signal is an active high signal and its
rising edge should be detected to drive the WAKE# the connector.
Assertion of wake could be for a single clock cycle or multiple clock
cycles.
Not used in downstream port.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

local_ref_clk_req_n O This signal may be connected to the CLKREQ# driver to negotiate entry
into L1 sub-states. When this signal is set to 1 the controller is
requesting entry into L1 sub-states and CLKREQ# may be de-asserted.
For an Upstream port this signal is also used to request reference clock
removal when Clock Power Management is enabled. This signal should
only be set to 1 if the PHY is also ready for reference clock removal, the
input phy_clk_req_n is a handshake from the PHY, which when set to 1
indicates that the PHY is ready for reference clock removal.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

pm_dstate[((3*NF)-1):0] O The current power management D-state of the function:


■ 000b: D0
■ 001b: D1
■ 010b: D2
■ 011b: D3
■ 100b: Uninitialized
■ Other values: Not applicable
There are 3 bits of pm_dstate for each configured function.
Exists: Always
Synchronous To: aux_clk_g,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

pm_pme_en[(NF-1):0] O PME Enable bit in the PMCSR. There is 1 bit of pm_pme_en for each
configured function.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_linkst_in_l0s O Power management is in L0s state. Indicates in L0_STALL state when


M-PCIe
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_linkst_in_l1 O Power management is in L1 state.


Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_linkst_in_l2 O Power management is in L2 state.


Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_linkst_l2_exit O Power management is exiting L2 state. Not applicable for downstream


port.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Power Management Signals

Port Name I/O Description

pm_master_state[(PM_MST_WD-1):0] O Power management master FSM state.


Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_slave_state[(PM_SLV_WD-1):0] O Power management slave FSM state.


Exists: Always
Synchronous To: None,perbitclk,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_l1sub_state[2:0] O Power management L1 sub-states FSM state.


Exists: CX_L1_SUBSTATES_ENABLE
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_status[(NF-1):0] O PME Status bit from the PMCSR. There is 1 bit of pm_status for each
configured function.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

aux_pm_en[(NF-1):0] O Auxiliary Power Enable bit in the Device Control register. There is 1 bit
of aux_pm_en for each configured function.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

app_req_entr_l1 I Application request to Enter L1 ASPM state. The app_req_entr_l1


signal is for use by applications that need to control L1 entry instead of
using the L1 entry timer as defined in the PCI Express Specification. It is
only effective when L1 is enabled. The controller latches this request
when in L0 or L0s; to be acted upon later.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High Pulse
Validated by: Not validated by another signal

app_ready_entr_l23 I Application Ready to Enter L23. Indication from your application that it is
ready to enter the L23 state. The app_ready_entr_l23 signal is provided
for applications that must control L23 entry (in case certain tasks must
be performed before going into L23). The controller delays sending
PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes
active. When this signal has been asserted by the application, it must be
kept asserted until L2 entry has completed. Hardwire to 1 for
applications that do not require this feature.
Note:The controller ignores this input in a downstream port.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_req_exit_l1 I Application request to Exit L1. Request from your application to exit L1.
It is only effective when L1 is enabled.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

app_xfer_pending I Indicates that your application has transfers pending and prevents the
controller from entering L1. If the entry into L1 is already in progress,
assertion of app_xfer_pending causes an exit from L1. This is a level
signal used to inform the controller about the state of external queues
and pipeline stages that contain transactions to be transmitted by the
controller. The controller uses this information to determine when to
enter/exit L1. When this signal is asserted, it indicates that there are
transactions outside the controller that the controller needs to transmit.
When de-asserted, it indicates that there are no transactions outside the
controller. The controller responds to an assertion on this signal as
follows:
■ Upstream Ports: Prevents generation of requests to enter L1. Trig-
gers exit if already in L1.
■ Downstream Ports: Triggers exit if already in L1.
You can instruct the controller to exit L1 by asserting either or both of
app_xfer_pending and app_req_exit_l1. The controller only samples
app_req_exit_l1 when the controller is already in the L1 state.
Exists: Always
Synchronous To: aux_clk_g,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

all_dwsp_in_l1 I All downstream ports in L1. Indicates to an upstream switch port that all
downstream switch ports are in the L1 state.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

all_dwsp_in_rl0s I Receive Side of All downstream ports in L0s. Indicates to an upstream


switch port that the receive side of all downstream switch ports are in
the L0s state.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

upsp_in_rl0s I Receive Side of upstream port in L0s. Indicates to a downstream switch


port that the receive side of the upstream switch port is in the L1 state.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

one_dwsp_exit_l1 I Downstream port Exiting L1. Indicates to an upstream switch port that
one or more downstream switch ports is exiting the L1 state.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

one_dwsp_exit_l23 I Downstream port Exiting L23. Indicates to an upstream switch port that
one or more downstream switch ports is exiting the L2 or L3 state.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

clkreq_in_n I Status of the CLKREQ# bidirectional CMOS board-level signal. Used by


the controller to determine when to enter and exit L1 Substates when
using the CLKREQ#-based mechanism. For more details, see 'L1
Substates'.
This signal is syncronized using aux_clk and can be driven/supplied
asynchronously to the controller in certain low-power modes.
Exists: CX_L1_SUBSTATES_ENABLE
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Power Management Signals

Port Name I/O Description

pm_linkst_in_l1sub O Power management is in L1 substate. Indicates when the link has


entered L1 substates. It is used in DWC_pcie_clkrst.v (see 'Clock
Generation and Gating Design Example') to ensure that the switching
back of aux_clk from AUXCLK to PCLK occurs only after L1 substates
have been exited. For L1.2 this signal is deasserted at the end of the
L1.2.Exit state, after the t_power_on constraint has been satisfied.
External logic can use the transition high to low on this signal to initiate
REFCLK restore.
Exists: CX_L1_SUBSTATES_ENABLE
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_l1sub_en O Indicates that any of the L1 Substates are enabled in the L1 Substates
Control 1 Register. Could be used by your application in a downstream
port to determine when not to drive CLKREQ# such as when L1
Substates are not enabled.
Exists: CX_L1_SUBSTATES_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_clk_pm_en I Clock PM feature enabled by application. Used to inhibit the


programming of the Clock PM in Link Control Register. For more details,
see 'L1 with Clock PM (L1 with REFCLK removal/PLL Off)'.
Exists: Always
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

test_bypass_lp I Test mode override of isolation enable.


Exists: CX_ENHANCED_PM_EN
Synchronous To: dbi_aclk,dbi_aclk_ug,slv_aclk,slv_aclk_ug,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

ack_en_vmain I Acknowledge from power switch responsible for autonomous


power-gating in L1.2. The application must set this signal to 0 when
pm_en_vmain is set to 0 by the controller to request power-gating in
L1.2. The application must set this signal to 1 when pm_en_vmain is
set to 1 by the controller to request power to be restored.
This signal is syncronized using aux_clk and can be driven/supplied
asynchronously to the controller in certain low-power modes.
Exists: (CX_ENHANCED_PM_EN) && (CX_L1_PG_ENABLE)
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_l1_pwr_off_en I Application permits to gate power to parts of the controller in L1 state.


Exists: CX_ENHANCED_PM_EN
Synchronous To: None,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

save_state_ack I Application acknowledges that state retention (L1 power gating) task is
completed.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

restore_state_ack I Application acknowledges that saved state has been restored after
power-up.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Power Management Signals

Port Name I/O Description

pm_en_vmain_n O Active Low Enable for power switch supplying PD_VMAIN. This signal
will be set to 1 when the controller is requesting power to be gated in
L1.2. The application must set the acknowledge ack_en_vmain to 0
when power has been gated. The controller will set this signal to 0
when it is requesting power to be restored, the application should set
ack_en_vmain to 1 when it has restored power. For more details, see
"Advanced Power Management and Power Domain Gating" in the
Power Management section of the Databook.
Exists: (CX_ENHANCED_PM_EN) && (CX_PSW_EN_ACTIVE_LOW)
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

pm_en_vmain O Active High Enable for power switch supplying PD_VMAIN. This signal
will be set to 0 when the controller is requesting power to be gated in
L1.2. The application must set the acknowledge ack_en_vmain to 0
when power has been gated. The controller will set this signal to 1
when it is requesting power to be restored, the application should set
ack_en_vmain to 1 when it has restored power. For more details, see
"Advanced Power Management and Power Domain Gating" in the
Power Management section of the Databook.
Exists: (CX_ENHANCED_PM_EN) && (!CX_PSW_EN_ACTIVE_LOW)
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_save_state_req O Request which can be used by your application to store any data which
needs to be retained during L1 power gating. For more details, see
"Advanced Power Management and Power Domain Gating" in the
Power Management section of the Databook.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

pm_restore_state_req O Request which can be used by your application to restore any data
which has been retained prior to L1 power gating. For more details, see
"Advanced Power Management and Power Domain Gating" in the
Power Management section of the Databook.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_req_iso_vmain_to_vaux O Request from PMC to enable isolation on VMAIN to VAUX boundary.


For more details, see "Advanced Power Management and Power
Domain Gating" in the Power Management section of the Databook.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_req_slv_iso O Request from PMC to enable isolation on AXI slave output signals. For
more details, see "Advanced Power Management and Power Domain
Gating" in the Power Management section of the Databook.
Exists: CX_SLV_ISO_EN
Synchronous To: slv_aclk_ug
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_req_mstr_iso O Request from PMC to enable isolation on AXI master output signals. For
more details, see "Advanced Power Management and Power Domain
Gating" in the Power Management section of the Databook.
Exists: CX_MSTR_ISO_EN
Synchronous To: mstr_aclk_ug
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Power Management Signals

Port Name I/O Description

pm_req_dbi_iso O Request from PMC to enable isolation on AXI DBI slave output signals.
For more details, see "Advanced Power Management and Power
Domain Gating" in the Power Management section of the Databook.
Exists: CX_DBI_ISO_EN
Synchronous To: dbi_aclk_ug
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_l1sub_disable I The application can set this input to 1'b1 to prevent entry to L1
Sub-states. This pin is used to gate the L1 sub-state enable bits from
the L1 PM Substates Control 1 Register.
Exists: CX_APP_L1SUB_CONTROL
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pm_l1_entry_started O L1 entry process is in progress.


Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: Precision Time Management Signals PCI Express SW Controller Databook

5.48 SII: Precision Time Management Signals

ptm_sw_dn_context_valid - - ptm_context_valid
ptm_sw_dn_local_clock - - ptm_responder_rdy_to_validate
cfg_ptm_sw_dn_enable - - ptm_local_clock
cfg_ptm_sw_dn_responder_capable - - cfg_ptm_sw_up_enable
ptm_external_master_strobe - - cfg_ptm_sw_up_responder_capable
ptm_external_master_time - - ptm_trigger_allowed
ptm_auto_update_signal - - ptm_updating
ptm_manual_update_pulse - - ptm_clock_updated
- ptm_clock_correction
- ptm_req_response_timeout
- ptm_req_dup_rx
- ptm_req_replay_tx

Table 5-48 SII: Precision Time Management Signals

Port Name I/O Description

ptm_context_valid O Context Valid.


Exists: CX_PTM_ENABLE
Synchronous To: core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ptm_responder_rdy_to_validate O PTM Responder Ready to Validate.


Exists: CX_PTM_ENABLE
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ptm_local_clock[63:0] O Local Clock value.


Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Context Valid

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PCI Express SW Controller Databook SII: Precision Time Management Signals

Port Name I/O Description

ptm_sw_dn_context_valid I PTM "Requester Context is Valid" indication to downstream port.


Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ptm_sw_dn_local_clock[63:0] I Local Clock value into Downstream Switch.


Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Context Valid

cfg_ptm_sw_up_enable O PTM Enable from upstream port.


Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ptm_sw_up_responder_capable O PTM Responder Capable from upstream port indication to downstream


port.
Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ptm_sw_dn_enable I PTM Enable into downstream port.


Exists: CX_PTM_ENABLE
Synchronous To: radm_clk_g,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

cfg_ptm_sw_dn_responder_capable I PTM Responder Capable into downstream port.


Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ptm_external_master_strobe I PTM External Master Time Strobe.


Exists: (CX_PTM_ENABLE) &&
(CX_PTM_EXTERNAL_MASTER_TIME)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ptm_external_master_time[63:0] I PTM External Master Time.


Exists: (CX_PTM_ENABLE) &&
(CX_PTM_EXTERNAL_MASTER_TIME)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ptm_auto_update_signal I Indicates that the controller should update the PTM Requester Context
and Clock automatically every 10ms.
Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (Level)
Validated by: Not validated by another signal

ptm_manual_update_pulse I Indicates that the controller should update the PTM Requester Context
and Clock now.
Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (Pulse)
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Precision Time Management Signals

Port Name I/O Description

ptm_trigger_allowed O Indicates that a PTM Requester manual update trigger is allowed.


Exists: CX_PTM_ENABLE
Synchronous To: aux_clk,core_clk,ret_core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ptm_updating O Indicates that a PTM update is in progress.


Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ptm_clock_updated O Indicates that the controller has updated the Local Clock.
Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (Pulse)
Validated by: Not validated by another signal

ptm_clock_correction[63:0] O Amount by which Local Clock has been corrected.


Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

ptm_req_response_timeout O PTM Requester Response Timeout. Single-cycle pulse indicating 100us


timeout occurred while waiting for a PTM Response or PTM ResponseD
message.
Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

ptm_req_dup_rx O PTM Requester Duplicate Received. Single-cycle pulse indicating PTM


Requester received a duplicate TLP while,
■ PTM Requester is in the process of updating PTM local clock, or
■ Following calculation of the update, when the PTM context is valid
Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (Pulse)
Validated by: Not validated by another signal

ptm_req_replay_tx O PTM Requester Replay Sent. Single-cycle pulse indicating PTM


Requester detected a TLP replay being sent when ResponseD
messages are in use while,
■ PTM Requester is in the process of updating PTM local clock, or
■ Following calculation of the update, when the PTM context is valid
Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: RAS Data Protection Signals

5.49 SII: RAS Data Protection Signals

- cfg_rasdp_error_mode

Table 5-49 SII: RAS Data Protection Signals

Port Name I/O Description

cfg_rasdp_error_mode O Indication from the controller that it has entered RASDP error mode.The
controller enters RASDP error mode (if the ERROR_MODE_EN register
field =1) upon detection of the first uncorrectable error. During this
mode, Rx TLPs that are forwarded to your application are not
guaranteed to be correct; you must discard them. For more details, see
the RAS Data Protection (DP) section in the Controller Operations
chapter of the Databook.
Exists: (!(AMBA_INTERFACE!=0)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: Receive Control/CPL Timeout Signals PCI Express SW Controller Databook

5.50 SII: Receive Control/CPL Timeout Signals

app_ph_ca -
app_pd_ca -
app_nph_ca -
app_npd_ca -
app_cplh_ca -
app_cpld_ca -

Table 5-50 SII: Receive Control/CPL Timeout Signals

Port Name I/O Description

app_ph_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that posted header credits have been
returned. In implementations where your application is responsible for
queuing the receive data (such as in bypass mode), your application
must pulse the app_ph_ca input each time your application consumes a
posted header credit so that the controller can update the number of
posted header credits available. There is 1 bit of app_ph_ca assigned to
each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_pd_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that posted data credits have been returned.
In implementations where your application is responsible for queuing
the receive data (such as in bypass mode), your application must pulse
the app_pd_ca input each time your application consumes a posted
data credit so that the controller can update the number of posted data
credits available. Your application must assert app_pd_ca once for each
packet, even if the packet contains less than 16 bytes (1 credit) of data.
There is 1 bit of app_pd_ca assigned to each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Receive Control/CPL Timeout Signals

Port Name I/O Description

app_nph_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that non-posted header credits have been
returned. In implementations where your application is responsible for
queuing the receive data (such as in bypass mode), your application
must pulse the app_nph_ca input each time your application consumes
a non-posted header credit so that the controller can update the number
of non-posted header credits available. There is 1 bit of app_nph_ca
assigned to each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_npd_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that non-posted data credits have been
returned. In implementations where your application is responsible for
queuing the receive data (such as in bypass mode), your application
must pulse the app_npd_ca input each time your application consumes
a non-posted data credit so that the controller can update the number of
non-posted data credits available. Your application must assert
app_npd_ca once for each packet, even if the packet contains less than
16 bytes (1 credit) of data. There is 1 bit of app_npd_ca assigned to
each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_cplh_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that completion header credits have been
returned. In implementations where your application is responsible for
queuing the receive data (such as in bypass mode), your application
must pulse the app_cplh_ca input each time your application consumes
a completion header credit so that the controller can update the number
of completion header credits available. There is 1 bit of app_cplh_ca
assigned to each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: Receive Control/CPL Timeout Signals PCI Express SW Controller Databook

Port Name I/O Description

app_cpld_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that completion data credits have been
returned. In implementations where your application is responsible for
queuing the receive data (such as in bypass mode), your application
must pulse the app_cpld_ca input each time your application consumes
a completion data credit so that the controller can update the number of
completion data credits available. Your application must assert
app_cpld_ca once for each packet, even if the packet contains less than
16 bytes (1 credit) of data. There is 1 bit of app_cpld_ca assigned to
each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Transmit Control Signals

5.51 SII: Transmit Control Signals

app_hdr_valid - - pm_xtlh_block_tlp
app_hdr_log - - app_parity_errs
app_tlp_prfx_log - - xadm_ph_cdts
app_err_bus - - xadm_pd_cdts
app_err_advisory - - xadm_nph_cdts
app_err_func_num - - xadm_npd_cdts
app_crd_cpl_grant - - xadm_cplh_cdts
app_crd_msg_grant - - xadm_cpld_cdts
- xadm_crd_msg_h_req
- xadm_crd_msg_d_req
- xadm_crd_cpl_h_req
- xadm_crd_cpl_d_req
- xadm_crd_msg_vc
- xadm_crd_cpl_vc
- xadm_crd_msg_consumed
- xadm_crd_cpl_consumed
- xadm_hcdt_consumed
- xadm_dcdt_consumed
- xadm_data_credit

Table 5-51 SII: Transmit Control Signals

Port Name I/O Description

pm_xtlh_block_tlp O Indicates that your application must stop generating new outgoing
request TLPs due to the current power management state. Your
application can continue to generate completion TLPs. For more details,
see "Outbound TLP Blocking In USP". This output is not used in a
downstream switch port.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: Transmit Control Signals PCI Express SW Controller Databook

Port Name I/O Description

app_parity_errs[2:0] O Indicates that the controller detected a datapath parity error, one bit for
each of the following parity errors:
■ app_parity_errs[0]: Parity error at front end of the transmit datapath.
■ app_parity_errs[1]: Parity error at back end of the transmit datapath.
■ app_parity_errs[2]: Parity error the receive datapath.
The app_parity_errs signals are one-cycle pulses that indicate the
associated parity error occurred; they do not indicate which packet
contained the parity error. A suggested usage of the app_parity_errs
signals is to register each bit and to provide a control to turn off system
notification of parity errors. By doing so, your application can choose to
only respond to the first detection of a parity error. The controller
performs transmit and receive datapath parity if data path protection is
selected.
Exists: APP_PAR_ERR_OUT_EN
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_ph_cdts[((NVC*HCRD_WD)-1):0] O The amount of posted header buffer space currently available at the
receiver at the other end of the link (in units of posted header credits).
The controller maintains the current number of credits xadm_ph_cdts as
the receiver continues to send UpdateFC DLLPs and your application
uses credits by sending new TLPs to be transmitted. There are eight
bits of xadm_ph_cdts assigned to each configured virtual channel. Only
needed if you want your application to check available credits before
submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

xadm_pd_cdts[((NVC*DCRD_WD)-1):0] O The amount of posted data buffer space currently available at the
receiver at the other end of the link (in units of posted data credits). The
controller maintains the current number of credits xadm_pd_cdts as the
receiver continues to send UpdateFC DLLPs and your application uses
credits by sending new TLPs to be transmitted. There are twelve bits of
xadm_pd_cdts assigned to each configured virtual channel. Only
needed if you want your application to check available credits before
submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_nph_cdts[((NVC*HCRD_WD)-1):0] O The amount of non-posted header buffer space currently available at the
receiver at the other end of the link (in units of non-posted header
credits). The controller maintains the current number of credits
xadm_nph_cdts as the receiver continues to send UpdateFC DLLPs
and your application uses credits by sending new TLPs to be
transmitted. There are eight bits of xadm_nph_cdts assigned to each
configured virtual channel. Only needed if you want your application to
check available credits before submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_npd_cdts[((NVC*DCRD_WD)-1):0] O The amount of non-posted data buffer space currently available at the
receiver at the other end of the link (in units of non-posted data credits).
The controller maintains the current number of credits xadm_npd_cdts
as the receiver continues to send UpdateFC DLLPs and your
application uses credits by sending new TLPs to be transmitted. There
are twelve bits of xadm_npd_cdts assigned to each configured virtual
channel. Only needed if you want your application to check available
credits before submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

xadm_cplh_cdts[((NVC*HCRD_WD)-1):0] O The amount of completion header buffer space currently available at the
receiver at the other end of the link (in units of completion header
credits). The controller maintains the current number of credits
xadm_cplh_cdts as the receiver continues to send UpdateFC DLLPs
and your application uses credits by sending new TLPs to be
transmitted. There are eight bits of xadm_cplh_cdts assigned to each
configured virtual channel. Only needed if you want your application to
check available credits before submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_cpld_cdts[((NVC*DCRD_WD)-1):0] O The amount of completion data buffer space currently available at the
receiver at the other end of the link (in units of completion data credits).
The controller maintains the current number of credits xadm_cpld_cdts
as the receiver continues to send UpdateFC DLLPs and your
application uses credits by sending new TLPs to be transmitted. There
are twelve bits of xadm_cpld_cdts assigned to each configured virtual
channel. Only needed if you want your application to check available
credits before submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_hdr_valid I One-clock-cycle pulse indicating that the data app_hdr_log,


app_err_bus, app_err_func_num, and app_tlp_prfx_log is valid.
Exists: APP_RETURN_ERR_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Transmit Control Signals

Port Name I/O Description

app_hdr_log[127:0] I The header of the TLP that contained the error indicated app_err_bus,
valid when 1. app_hdr_valid is asserted. For Corrected Internal and
Uncorrectable Internal errors (app_err_bus[10:9]),and receiver Overflow
(app_err_bus[1]), the header information this input is not logged by the
controller. 2. app_dpc_err_valid is asserted. The header of the TLP that
contained the error indicated on app_dpc_err_bus. When DPC RP PIO
exgtensions are supported, it is used to update DPC RP PIO Header
Log Register.
Exists: APP_RETURN_ERR_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_hdr_valid or app_dpc_err_valid is asserted

app_tlp_prfx_log[127:0] I End-End TLP prefixes of the TLP that contained an error. Valid when 1.
app_hdr_valid is asserted. The header of the TLP that contained the
error indicated on app_err_bus. For Corrected Internal and
Uncorrectable Internal errors (app_err_bus[10:9]),and receiver Overflow
(app_err_bus[1]), the header information this input is not logged by the
controller. 2. app_dpc_err_valid is asserted. The header of the TLP that
contained the error indicated on app_dpc_err_bus. When DPC RP PIO
exgtensions are supported, it is used to update DPC RP PIO Header
Log Register.
Exists: (APP_RETURN_ERR_EN) && (CX_TLP_PREFIX_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_hdr_valid is asserted

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Port Name I/O Description

app_err_bus[(ERR_BUS_WD-1):0] I The type of error that your application detected. The controller combines
the values the app_err_bus bits with the internally-detected error signals
to set the corresponding bit in the Uncorrectable or Correctable Error
Status Registers:
■ app_err_bus[0]: Malformed TLP
■ app_err_bus[1]: Receiver Overflow
■ app_err_bus[2]: Unexpected completion
■ app_err_bus[3]: Completer abort
■ app_err_bus[4]: Completion Timeout
■ app_err_bus[5]: Unsupported request
■ app_err_bus[6]: ECRC Check Failed
■ app_err_bus[7]: Poisoned TLP received
■ app_err_bus[8]: AtomicOp Egress Blocked: only valid when
CX_ATOMIC_ROUTING_EN =1
■ app_err_bus[9]: Uncorrectable Internal Error
■ app_err_bus[10]: Corrected Internal Error
■ app_err_bus[11]: TLP Prefix Blocked Error Status: only valid when
CX_NPRFX >0
■ app_err_bus[12]: ACS Violation: only valid when CX_ACS_ENABLE
=1
For more details, see 'Application Error Reporting Interface'.
Exists: APP_RETURN_ERR_EN
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_hdr_valid is asserted

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PCI Express SW Controller Databook SII: Transmit Control Signals

Port Name I/O Description

app_err_advisory I Indicates that your application error is an advisory error. Your application
should assert app_err_advisory under either of the following conditions:
■ The controller is configured to mask completion timeout errors, your
application is reporting a completion timeout error app_err_bus, and
your application intends to resend the request. In such cases the
error is an advisory error, as described in PCI Express Specification.
When your application does not intend to resend the request, then
your application must keep app_err_advisory de-asserted when
reporting a completion timeout error.
■ The controller is configured to forward poisoned TLPs to your appli-
cation and your application is going to treat the poisoned TLP as a
normal TLP, as described in PCI Express Specification. Upon receipt
of a poisoned TLP, your application must report the error app_er-
r_bus, and either assert app_err_advisory (to indicate an advisory
error) or de-assert app_err_advisory (to indicate that your applica-
tion is dropping the TLP).
For more details, see the PCI Express Specification to determine when
an application error is an advisory error.
Exists: APP_RETURN_ERR_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_hdr_valid is asserted

app_err_func_num[(PF_WD-1):0] I The number of the function that is reporting the error indicated
app_err_bus, valid when app_hdr_valid is asserted. Correctable and
Uncorrected Internal errors (app_err_bus[10:9]) are not function
specific, and are recorded for all physical functions, regardless of the
value this bus. Function numbering starts at '0'.
Exists: APP_RETURN_ERR_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_hdr_valid is asserted

app_crd_cpl_grant I Application grants the use of credits for internally generated


completions.
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

app_crd_msg_grant I Application grants the use of credits for internally generated messages.
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_crd_msg_h_req O The controller requests app for grant to send internally generated msg
(consuming header credit).
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_crd_msg_d_req O The controller requests app for grant to send internally generated msg
(consuming data credit).
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_crd_cpl_h_req O The controller requests app for grant to send internally generated cpl
(consuming header credit).
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_crd_cpl_d_req O The controller requests app for grant to send internally generated cpl
(consuming data credit).
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: Transmit Control Signals

Port Name I/O Description

xadm_crd_msg_vc[2:0] O Indicates the VC id for the msg request.


Exists: APP_CREDIT_CTRL
Synchronous To: None
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

xadm_crd_cpl_vc[2:0] O Indicates the VC id for the cpl request.


Exists: APP_CREDIT_CTRL
Synchronous To: None
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

xadm_crd_msg_consumed O Indicates the granted MSG has been consumed.


Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_crd_cpl_consumed O Indicates the granted CPL has been consumed.


Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_hcdt_consumed[((3*NVC)-1):0] O Indicates header credits have been consumed.


■ Bit 2 indicates Posted
■ Bit 1 indicates Non-posted
■ Bit 0 indicates Completion
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

xadm_dcdt_consumed[((3*NVC)-1):0] O Indicates data credits have been consumed.


■ Bit 2 indicates Posted
■ Bit 1 indicates Non-posted
■ Bit 0 indicates Completion
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

xadm_data_credit[8:0] O Indicates how many data credits have been consumed.


Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: xadm_dcdt_consumed

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PCI Express SW Controller Databook Common PIPE Signals

5.52 Common PIPE Signals

phy_mac_rxelecidle - - mac_phy_powerdown
phy_mac_phystatus - - mac_phy_txdata
phy_mac_rxdata - - mac_phy_txdatak
phy_mac_rxdatak - - mac_phy_elasticbuffermode
phy_mac_rxvalid - - mac_phy_txdatavalid
phy_mac_rxstatus - - mac_phy_txdetectrx_loopback
phy_mac_rxstandbystatus - - mac_phy_txelecidle
phy_cfg_status - - mac_phy_txcompliance
phy_mac_rxdatavalid - - mac_phy_rxpolarity
phy_mac_pclkack_n - - mac_phy_width
- mac_phy_serdes_arch
- mac_phy_rxwidth
- mac_phy_pclk_rate
- mac_phy_cclk_rate
- mac_phy_plclk_rate
- mac_phy_rxstandby
- cfg_phy_control
- mac_phy_pclkreq_n
- mac_phy_rxelecidle_disable
- mac_phy_txcommonmode_disable
- mac_phy_asyncpowerchangeack

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Common PIPE Signals PCI Express SW Controller Databook

Table 5-52 Common PIPE Signals

Port Name I/O Description

mac_phy_powerdown[(PDWN_WIDTH-1): O Power control bits that drive the PHY power state. This signal is shared
0] by all the lanes of the PHY. so you must fan out this signal (through your
power-down controller block) to all the corresponding lanes of the PHY.
Power states (with the corresponding link states and L1 Substates) are
as follows:
■ 0000: P0 (L0): normal
■ 0001: P0s (L0s): low recovery time, power saving.
■ 0010: P1 (L1): longer recovery time, additional power saving.
■ 0011: P2 (L2): lowest power state.
The following encodings are used when CX_L1_SUBSTATES_ENABLE
=CX_PIPE43_SUPPORT =1. You can specify the encodings using
CX_PIPE43_P1CPM_ENCODING, CX_PIPE43_P1_1_ENCODING,
and CX_PIPE43_P1_2_ENCODING parameters.
■ CX_PIPE43_P1CPM_ENCODING: P1.CPM (L1 Substates L1.0):
PHY specific powerdown state, instructs PHY to turn off PCLK.
Controller stays in this state until PHY asserts phy_mac_phystatus
back.
■ CX_PIPE43_P1_1_ENCODING: P1.1 (L1 Substates L1.1): PHY
specific powerdown state, instructs PHY to disable Receiver Elec-
trical Idle detection logic. If CX_PIPE43_ASYNC_HS_BYPASS is
not set, controller stays in this state until the asynchronous power-
down change handshake completes.
■ CX_PIPE43_P1_2_ENCODING: P1.2 (L1 Substates L1.2): PHY
specific powerdown state, instructs PHY to disable Receiver Elec-
trical Idle detection logic and Transmitter Common Mode logic.
When CX_PIPE43_ASYNC_HS_BYPASS is not set, the controller
stays in this state until the asynchronous powerdown change hand-
shake completes.
This is a 4-bit output to support PIPE 4.3 version. When your PHY is not
PIPE 4.3 compliant, use the lower bits for connection; the controller
drives the MSB bits to '0'.
The following encoding is used when CX_P2NOBEACON_ENABLE =1
and PHY_INTEROP_CTRL_OFF.P2NOBEACON_ENABLE =1.
■ CX_PIPE43_P2NOBEACON_ENCODING: P2.NoBeacon: When
CX_P2NOBEACON_ENABLE =1, mac_phy_powerdown drives
P2.NoBeacon encoding instead of P2 encoding, when the link goes
to L2. To configure P2.NoBeacon encoding use
CX_PIPE43_P2NOBEACON_ENCODING parameter. The default
value of this parameter is 4'b1111.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: None,perbitclk,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Common PIPE Signals

Port Name I/O Description

phy_mac_rxelecidle[(NL-1):0] I Indicates receiver detection of an Electrical Idle for each lane. This can
be signaled asynchronously by the PHY macro.
■ Bit 0 corresponds to lane 0
■ Bit 1 corresponds to lane 1
■ and so on, up to the maximum number of lanes.
You can set a DFT control point to force this controller input to '1' during
scan mode to make the pc_rxelecidle register in the rxeidle_squelch
module scannable.
This signal is syncronized using aux_clk and can be driven/supplied
asynchronously to the controller in certain low-power modes.
Exists: ((CX_CPCIE_ENABLE)) && (!CX_ADM_ADAPTOR_ENABLE)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_phystatus[(NL-1):0] I Communicates completion of PHY functions, including power


management transitions, receiver detection, speed change, and EQ
evaluation at Gen3 rate. The core_clk should not be shut off before the
PHY acknowledges the state change with PHYstatus.
This signal is syncronized using aux_clk and can be driven/supplied
asynchronously to the controller in certain low-power modes.
Exists: (CX_CPCIE_ENABLE)
Synchronous To:
aux_clk,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Common PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

phy_mac_rxdata[(PIPE_DATA_WD-1):0] I Parallel received data.


For Original PIPE architecture,
■ Bits 7:0 correspond to the first symbol of lane 0.
■ Bits 15:8 correspond to the second symbol of lane 0 (16-bit PHY
interface) or the single symbol of lane 1 (8-bit PHY interface).
■ Bits 23:16 correspond to the third symbol of lane 0 (32-bit PHY inter-
face) or the single symbol of lane 2 (8-bit PHY interface) or the first
symbol of lane 1 (16-bit PHY interface).
■ Bits 31:24 correspond to the fourth symbol of lane 0 (32-bit PHY
interface) or the single symbol of lane 3 (8-bit PHY interface) or the
second symbol of lane 1 (16-bit PHY interface).
The remaining bits continue similarly.
For SerDes architecture,
■ Bits 9:0 correspond to the first symbol of lane 0.
■ Bits 19:10 correspond to the second symbol of lane 0 (20-bit PHY
interface) or the single symbol of lane 1 (10-bit PHY interface).
■ Bits 29:20 correspond to the third symbol of lane 0 (40-bit PHY inter-
face) or the single symbol of lane 2 (10-bit PHY interface) or the first
symbol of lane 1 (20-bit PHY interface).
■ Bits 39:30 correspond to the fourth symbol of lane 0 (40-bit PHY
interface) or the single symbol of lane 3 (10-bit PHY interface) or the
second symbol of lane 1 (20-bit PHY interface).
The remaining bits continue similarly. For 128b/130b encoded data at
Gen3 speed or higher, only 8 bits out of each 10-bit slice are used, e.g.
[7:0] represent byte 0, [9:8] are reserved, [17:10] represent byte 1, and
[19:18] are reserved, etc.
Bit 0 is the first bit received via link.
Exists: (CX_CPCIE_ENABLE)
Synchronous To:
aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: phy_mac_rxvalid is asserted, per lane. In SerDes
architecture, phy_mac_rxdata is not validated by another signal.

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PCI Express SW Controller Databook Common PIPE Signals

Port Name I/O Description

phy_mac_rxdatak[((NL*PHY_NB)-1):0] I Control (K character) indicator bits for received data:


■ Bit 0 corresponds to the first symbol of lane 0.
■ Bit 1 corresponds to the second symbol of lane 0 (16-bit PHY inter-
face) or the single symbol of lane 1 (8-bit PHY interface).
■ Bit 2 corresponds to the third symbol of lane 0 (32-bit PHY interface)
or the single symbol of lane 2 (8-bit PHY interface) or the first symbol
of lane 1 (16-bit PHY interface).
■ Bits 3 corresponds to the fourth symbol of lane 0 (32-bit PHY inter-
face) or the single symbol of lane 3 (8-bit PHY interface) or the
second symbol of lane 1 (16-bit PHY interface).
The remaining bits continue similarly.
Exists: ((CX_CPCIE_ENABLE)) && (!SNPS_RSVDPARAM_26)
Synchronous To:
aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High indicates control symbol, low indicates data symbol.
Validated by: phy_mac_rxvalid is asserted, per lane

phy_mac_rxvalid[(NL-1):0] I Indicates symbol lock and valid data for each lane. Bit 0 corresponds to
lane 0.
For SerDes architecture, this is used to indicate that the recovered clock
is stable.
Exists: (CX_CPCIE_ENABLE)
Synchronous To:
aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Common PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

phy_mac_rxstatus[((NL*3)-1):0] I Receive status and error codes for each lane. Bits 2:0 correspond to
lane 0; bits 5:3 correspond to lane 1, and so on, up to the maximum
number of lanes. Encoding is as follows:
■ 000: Received data OK
■ 001: A SKP set has been added. For Gen1/2, a SKP set is one byte.
For Gen3, a SKP set is four bytes.
■ 010: A SKP set has been removed. For Gen1/2: A SKP set is one
byte. For Gen3: A SKP set is four bytes
■ 011: Receiver detected
■ 100: Decode error. For Gen1/2, this indicates detection of an 8b/10b
decode error. For Gen3, this indicates detection of a 128b/130b
decode error.
■ 101: Elastic buffer overflow
■ 110: Elastic buffer underflow
■ 111: Receive disparity error. The controller does not report disparity
errors at Gen3 speed.
The controller supports Bare COM. When the PHY removes SKP
symbols it assigns phy_mac_rxstatus[2:0] = 3'b010 aligned to COM for
Gen1/2 rate or to phy_mac_rxstartblock=1 for Gen3/4 rate at the same
clock cycle.
For SerDes architecture, the only status applicable to SerDes
architecture is 'Receiver detected' (0x3).
Exists: (CX_CPCIE_ENABLE)
Synchronous To:
aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_rxstandbystatus[(NL-1):0] I The PHY uses this signal to indicate its RxStandby state.
■ 0: Active
■ 1: Standby
The Synopsys controller uses this signal only when
CX_RXSTANDBY_CONTROL[6] =1. Contact your PHY vendor for
guidelines on how to properly configure the RxStandby behavior. Refer
to the User Guide for guidelines on how to configure this parameter for
each supported Synopsys PHY.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Common PIPE Signals

Port Name I/O Description

phy_cfg_status[31:0] I Input bus that can optionally be used to read PHY status. The
phy_cfg_status bus maps to the PHY Status register
(PHY_STATUS_REG). For specific bit usage, see 'PHY Status
Register'.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_txdata[(PIPE_DATA_WD-1):0] O Parallel data for transmission:


For Original PIPE architecture,
■ Bits 7:0 correspond to the first symbol of lane 0.
■ Bits 15:8 correspond to the second symbol of lane 0 (16-bit PHY
interface) or the single symbol of lane 1 (8-bit PHY interface).
■ Bits 23:16 correspond to the third symbol of lane 0 (32-bit PHY inter-
face) or the single symbol of lane 2 (8-bit PHY interface) or the first
symbol of lane 1 (16-bit PHY interface).
■ Bits 31:24 correspond to the fourth symbol of lane 0 (32-bit PHY
interface) or the single symbol of lane 3 (8-bit PHY interface) or the
second symbol of lane 1 (16-bit PHY interface).
The remaining bits continue similarly.
For SerDes architecture,
■ Bits 9:0 correspond to the first symbol of lane 0.
■ Bits 19:10 correspond to the second symbol of lane 0 (20-bit PHY
interface) or the single symbol of lane 1 (10-bit PHY interface).
■ Bits 29:20 correspond to the third symbol of lane 0 (40-bit PHY inter-
face) or the single symbol of lane 2 (10-bit PHY interface) or the first
symbol of lane 1 (20-bit PHY interface).
■ Bits 39:30 correspond to the fourth symbol of lane 0 (40-bit PHY
interface) or the single symbol of lane 3 (10-bit PHY interface) or the
second symbol of lane 1 (20-bit PHY interface).
The remaining bits continue similarly. For 128b/130b encoded data at
Gen3 speed or higher, only 8 bits out of each 10-bit slice are used, e.g.
[7:0] represent byte 0, [9:8] are reserved, [17:10] represent byte 1, and
[19:18] are reserved, etc.
Bit 0 is the first bit to be transmitted via link.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: mac_phy_txelecidle is de-asserted, per lane

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Common PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

mac_phy_txdatak[((NL*PHY_NB)-1):0] O Control (K character) indicator bits for transmitted data:


■ Bit 0 corresponds to the first symbol of lane 0.
■ Bit 1 corresponds to the second symbol of lane 0 (16-bit PHY inter-
face) or the single symbol of lane 1 (8-bit PHY interface).
■ Bit 2 corresponds to the third symbol of lane 0 (32-bit PHY interface)
or the single symbol of lane 2 (8-bit PHY interface) or the first symbol
of lane 1 (16-bit PHY interface).
■ Bits 3 corresponds to the fourth symbol of lane 0 (32-bit PHY inter-
face) or the single symbol of lane 3 (8-bit PHY interface) or the
second symbol of lane 1 (16-bit PHY interface).
The remaining bits continue similarly.
Exists: ((CX_CPCIE_ENABLE)) && (!SNPS_RSVDPARAM_26)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High indicates control symbol, low indicates data symbol.
Validated by: mac_phy_txelecidle is de-asserted, per lane

mac_phy_elasticbuffermode O Selects Elasticity Buffer operating mode. 0: Nominal Half Full Buffer
mode 1: Nominal Empty Buffer Mode
Exists: ((CX_CPCIE_ENABLE)) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,{None},{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_txdatavalid[(NL-1):0] O This signal allows the PCIe controller to instruct the PHY to ignore the
data interface for one or two clock cycles. A value of one indicates that
the data is valid and should be used. The PCIe controller asserts this
output during mac_phy_txelecidle.
Note: If your PHY does not support the mac_phy_txdatavalid signal you
can leave this pin unconnected.
Exists: (CX_CPCIE_ENABLE)
Synchronous To:
None,aux_clk,aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Common PIPE Signals

Port Name I/O Description

mac_phy_txdetectrx_loopback[(NL-1):0] O Combined loopback and transmit detect control, as per PIPE


specification. Note: mac_phy_txdetectrx_loopback[0] may be connected
to PHYs that share mac_phy_txdetectrx_loopback between their lanes
only when the PHY asserts phystatus on all lanes, in the same clock
cycle, for receiver's detection.
For SerDes architecture, this signal is only used for receiver detection.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_txelecidle[((NL*PHY_TXEI_WD) O Forces transmit output to Electrical Idle for each lane which it is
-1):0] asserted.
For PIPE4.4 or below, bit 0 corresponds to lane 0. Bit 1 corresponds to
lane 1, and so on, up to the maximum number of lanes.
For PIPE5.1 Original PIPE architecture, only bit 0 is used for lane 0 and
bit 1:3 are reserved. Only bit 4 is used for lane 1 and bit 5:7 are
reserved. The remaining bits continue similarly.
For PIPE5.1 and SerDes architecture, one bit is required per two
symbols of interface data. For example, for an eight symbol wide
interface, bit 0 would apply to symbols 0 and 1, bit 1 would apply to
symbols 2 and 3, bit 2 would apply to symbols 4 and 5, bit 3 would apply
to symbol 6 and 7 of lane 0. For narrower interfaces, unused bits of this
signal are reserved.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_txcompliance[(NL-1):0] O Sets the running disparity to negative. Used when transmitting


compliance pattern. Bit 0 corresponds to lane 0; bit 1 corresponds to
lane 1, and so on, up to the maximum number of lanes.
Exists: ((CX_CPCIE_ENABLE)) && (!SNPS_RSVDPARAM_26)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

mac_phy_rxpolarity[(NL-1):0] O Directs the PHY to perform a polarity inversion the received data the
specified lanes. Bit 0 corresponds to lane 0; bit 1 corresponds to lane 1,
and so on, up to the maximum number of lanes.
■ 1: Polarity inversion
■ 0: No polarity inversion
Exists: ((CX_CPCIE_ENABLE)) && (!(CX_PIPE51_SUPPORT))
Synchronous To:
aux_clk,aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_width[(WIDTH_WIDTH-1):0] O Controls the PIPE datapath width.


For SerDes architecture, this applys only to the transmit side and
mac_phy_rxwidth controls the receive side.
For Original PIPE architecture,
■ 0: 8 bits
■ 1: 16 bits
■ 2: 32 bits
■ 3: 64 bits
■ 4: 128 bits
For SerDes architecture,
■ 0: 10 bits
■ 1: 20 bits
■ 2: 40 bits
■ 3: 80 bits
■ 4: 160 bits
Exists: (CX_CPCIE_ENABLE)
Synchronous To: None,aux_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_serdes_arch O This signal indicates whether SerDes architecture is enabled.


Exists: ((CX_CPCIE_ENABLE)) && (CX_PIPE51_SUPPORT)
Synchronous To: CX_FREQ_STEP_EN ? "pipe_clk" : "core_clk"
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Common PIPE Signals

Port Name I/O Description

mac_phy_rxwidth[(WIDTH_WIDTH-1):0] O This signal is only used in the SerDes architecture. Controls the PIPE
receive datapath width.
■ 0: 10 bits
■ 1: 20 bits
■ 2: 40 bits
■ 3: 80 bits
■ 4: 160 bits
Exists: ((CX_CPCIE_ENABLE)) && (SNPS_RSVDPARAM_26)
Synchronous To: CX_FREQ_STEP_EN ? "pipe_clk" : "core_clk"
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_pclk_rate[(P_R_WD-1):0] O Controls the PIPE PCLK rate


■ 0: 62.5 MHz
■ 1: 125 MHz
■ 2: 250 MHz
■ 3: 500 MHz
■ 4: 1000 MHz
■ 5: 2000 MHz
■ 6: Reserved
■ 7: Reserved
■ 8: 625 MHz if CX_CCIX_ESM_SUPPORT = 1
■ 9: 781.25 MHz if CX_CCIX_ESM_SUPPORT = 1
■ A: 1250 MHz if CX_CCIX_ESM_SUPPORT = 1
■ B: 1562.5 MHz if CX_CCIX_ESM_SUPPORT = 1
■ C: 156.25MHz if CX_CCIX_ESM_SUPPORT = 1
■ D: 195.31MHz if CX_CCIX_ESM_SUPPORT = 1
■ E: 312.5MHz if CX_CCIX_ESM_SUPPORT = 1
■ F: 390.62MHz if CX_CCIX_ESM_SUPPORT = 1
Exists: (CX_CPCIE_ENABLE)
Synchronous To:
None,aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Common PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

mac_phy_cclk_rate[2:0] O Controls clock frequency ratio between the core_clk and the
core_pl_clk.
■ 0: Reserved
■ 1: 1:1
■ 2: 1:2
■ 3: 1:4
■ 4: 1:8
■ 5: 1:16
■ 6: Reserved
■ 7: Reserved
Exists: ((CX_CPCIE_ENABLE)) && (CX_FREQ_STEP_DL_EN)
Synchronous To: CX_FREQ_STEP_EN ? "pipe_clk" : "core_clk"
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_plclk_rate[2:0] O Controls clock frequency ratio between the core_pl_clk and the
pipe_clk.
■ 0: 2:1
■ 1: 1:1
■ 2: 1:2
■ 3: 1:4
■ 4: 1:8
■ 5: 1:16
■ 6: Reserved
■ 7: Reserved
Exists: ((CX_CPCIE_ENABLE)) && (CX_FREQ_STEP_DL_EN)
Synchronous To: CX_FREQ_STEP_EN ? "pipe_clk" : "core_clk"
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Common PIPE Signals

Port Name I/O Description

mac_phy_rxstandby[(NL-1):0] O Determines if the PHY RX is active when the PHY is in P0 or P0s.


■ 0: Active
■ 1: Standby
The controller asserts the signal as follows:
■ if Reset
mac_phy_rxstandby = CX_RXSTANDBY_DEFAULT;
■ else if CX_RXSTANDBY_CONTROL[0] =1 & receiving EIOS &
subsequent T TX-IDLE-MIN
mac_phy_rxstandby = 1;
Note: In Loopback.Active state as Slave at Gen2 data rate or above,
EIOS(s) indicates four EIOSs. In the other cases, EIOS(s) indicates
one EIOS.
■ else if CX_RXSTANDBY_CONTROL[1] =1 & for the duration of rate
change (from one cycle before rate signal change to receiving all
active lanes' PhyStatus for the rate change request)
mac_phy_rxstandby = 1;
■ else if CX_RXSTANDBY_CONTROL[2] =1 & the lane is inactive
when LTSSM exiting from Configuration.Idle state
mac_phy_rxstandby =1;
■ else if CX_RXSTANDBY_CONTROL[3] =1 & mac_phy_powerdown
=(P1 || P2)
mac_phy_rxstandby =1;
■ else if CX_RXSTANDBY_CONTROL[4] =1 & LTSSM is in RxL0s.Idle
state
mac_phy_rxstandby =1;
■ else if CX_RXSTANDBY_CONTROL[5] =1 & LTSSM moves from L0
state to Recovery state by Inferring Electrical Idle
mac_phy_rxstandby =1;
■ else if phy_mac_rxelecidle =0
mac_phy_rxstandby =0;
■ else
mac_phy_rxstandby =mac_phy_rxstandby.
■ If CX_RXSTANDBY_CONTROL[6] =1
❑ controller checks phy_mac_rxstandbystatus =0 before changing
mac_phy_rxstandby from '0' to '1'.
❑ controller checks phy_mac_rxstandbystatus =1 before changing
mac_phy_rxstandby from '1' to '0'.
The behavior of this signal is controlled by the
CX_RXSTANDBY_CONTROL and CX_RXSTANDBY_DEFAULT
configuration parameters.
Contact your PHY vendor for guidelines on how to properly configure
the RxStandby behavior.

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Common PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

mac_phy_rxstandby[(NL-1):0]...(cont.) O.
Refer to the User Guide for guidelines on how to configure this
parameter for each supported Synopsys Phy
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_rxdatavalid[(NL-1):0] I This signal allows a PHY to indicate valid data on the PIPE interface. A
value of '1' indicates that the data is valid and should be used. If your
PHY does not support this signal, then set it to '1'. You should set this
signal at the different link rates as follows:
■ Gen1: If data pacing is enabled in this mode, then toggle every other
or fourth clock, else '1'
■ Gen2: If data pacing is enabled in this mode, then toggle every other
or fourth clock, else '1'
■ Gen3: '1' except for regular de-assertion for 128b/130b
encoding/decoding
For more details, see the "Data Pacing (DP) Support" section in the
Product Overview chapter of the Databook. Clock tolerance
compensation is normally done by inserting or removing SKIP symbols
from a SKIP ordered set (OS). The controller also supports a
non-standard clock tolerance compensation mode at Gen3 speed. In
this mode SKIP OS's can be left unaltered in length. Clock tolerance
compensation is then achieved by modulating the period of de-assertion
of phy_mac_rxdatavalid. Therefore this input might be de-asserted
anywhere within a block (and not only at the end of a block), and the low
pulses can be up to two cycles long.
Exists: ((CX_CPCIE_ENABLE)) && (!CX_ADM_ADAPTOR_ENABLE)
&& (!SNPS_RSVDPARAM_26)
Synchronous To:
None,aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Common PIPE Signals

Port Name I/O Description

cfg_phy_control[31:0] O Output bus that can optionally be used for additional PHY control
purposes. The cfg_phy_control bus maps to the PHY Control register
(PHY_CONTROL_REG). For specific bit usage, see PHY Control
Register.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_pclkreq_n[1:0] O Request PCLK removal:


■ 00: Do not request PCLK removal
■ 01: Request PCLK removal for executing L1 with Clock PM
■ 10: Request PCLK removal for executing L1 substates
■ 11: Request PCLK removal for executing L1 substates with Clock
PM
When mac_phy_pclkreq_n[1:0] transitions to a non-zero value, the
signal is held constant until phy_mac_pclkack_n =1. Similarly, when
mac_phy_pclkreq_n[1:0] transitions back to a zero value the signal is
held constant until phy_mac_pclkack_n=0.
Exists: !CX_PIPE43_SUPPORT
Synchronous To: None,perbitclk,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

phy_mac_pclkack_n I PCLK removal request acknowledge.


■ 1: PCLK is removed, PHY is ready for REFCLK removal
■ 0: PCLK is active
This signal is syncronized using aux_clk and can be driven/supplied
asynchronously to the controller in certain low-power modes.
Exists: (CX_L1_SUBSTATES_ENABLE) && (!CX_PIPE43_SUPPORT)
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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Common PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

mac_phy_rxelecidle_disable O Instructs the PHY to disable the receiver Electrical Idle detection logic.
For more details, see 'L1 Substates'.
Exists: CX_L1_SUBSTATES_ENABLE
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_txcommonmode_disable O Instructs the PHY to disable the transmitter Common Mode logic. For
more details, see 'L1 Substates'.
Exists: CX_L1_SUBSTATES_ENABLE
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_asyncpowerchangeack O Acknowledgement of asynchronous phy_mac_phystatus feedback for


powerdown change complete in P1.1 or P1.2 state. The
acknowledgment handshake mechanism is:
■ PHY asserts phy_mac_phystatus asynchronously when it completes
P1.1 or P1.2 powerdown change.
■ MAC asserts mac_phy_asyncpowerchangeack when it detects
phy_mac_phystatus high.
■ PHY de-asserts phy_mac_phystatus asynchronously after it detects
mac_phy_asyncpowerchangeack high.
■ MAC de-asserts mac_phy_asyncpowerchangeack when it detects
phy_mac_phystatus low.
Exists: (CX_PIPE43_SUPPORT) &&
(!CX_PIPE43_ASYNC_HS_BYPASS)
Synchronous To: None,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Gen2/3-Only PIPE Signals

5.53 Gen2/3-Only PIPE Signals

- mac_phy_rate
- mac_phy_txdeemph
- mac_phy_txmargin
- mac_phy_txswing
- cfg_hw_auto_sp_dis

Table 5-53 Gen2/3-Only PIPE Signals

Port Name I/O Description

mac_phy_rate[(RATE_WIDTH-1):0] O Controls the link signaling rate.


■ 0: Use 2.5 GT/s signaling rate
■ 1: Use 5.0 GT/s signaling rate
■ 2: Use 8.0 GT/s signaling rate for PCIe mode or ESM data rate0 (8.0
GT/s or 16.0 GT/s) for ESM mode
■ 3: Use 16.0 GT/s signaling rate for PCIe mode or ESM data rate1
(20.0 GT/s or 25.0 GT/s) for ESM mode
■ 3: Use 16.0 GT/s signaling rate
■ 4: Use 32.0 GT/s signaling rate
PIPE implementations that only support 2.5GT/s signaling rate do not
implement this signal. This bus is one bit wide for a Gen2 configured
controller. It is two bits wide for a Gen3 configured controller and 3 bits
for Gen5 configured controller.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 2) : CX_S_CPCIE_MODE ?
(CX_GEN2_MODE != GEN2_DISABLED) : 0))
Synchronous To: aux_clk,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Gen2/3-Only PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

mac_phy_txdeemph[(TX_DEEMPH_WD-1 O For Gen2 configurations, this two bits wide output selects transmitter
):0] de-emphasis as follows:
■ 00: -6 dB de-emphasis at 5GT/s
■ 01: -3.5 dB de-emphasis at 5GT/s
■ 10: No de-emphasis.
Note:This is the only possible value when PIPE is configured for low
swing (mac_phy_txswing == 1) as per base specification Sect.
4.3.3.6
For Gen3 configurations at Gen3 speed, this (NL*18)-bit output conveys
the transmitter equalization coefficients where:
■ [5:0]: C-1 (Pre-cursor)
■ [11:6]: C0 (Cursor)
■ [17:12]: C+1 (Post-cursor). If your PHY has assigned mac_phy_tx-
deemph[17:0] as {C-1, C0, C+1}, then you must swap C-1 and C+1
to match the mapping of these fields in the controller.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 2) : CX_S_CPCIE_MODE ?
(CX_GEN2_MODE != GEN2_DISABLED) : 0)) &&
(!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Gen2/3-Only PIPE Signals

Port Name I/O Description

mac_phy_txmargin[2:0] O Selects transmitter voltage levels:


■ 000: Normal operating range
■ 001: 800-1200 mV for Full swing* or 400-700mV for Half swing
■ 010: Required and vendor defined
■ 011: Required and vendor defined
■ 100: Required and 200-400 mV for Full swing* or 100-200 mV for
Half swing* if the last value or vendor defined
■ 101: Optional and 200-400 mV for Full swing* or 100-200 mV for Half
swing* if the last value or vendor defined or Reserved if no other
values supported
■ 110: Optional and 200-400 mV for Full swing* or 100-200 mV for Half
swing* if the last value or vendor defined or Reserved if no other
values supported
■ 111: optional and 200-400 mV for Full swing* or 100-200 mV for Half
swing* if the last value or Reserved if no other values supported
*PIPE2 implementations that only support 2.5GT/s signaling rate do not
implement this signal.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 2) : CX_S_CPCIE_MODE ?
(CX_GEN2_MODE != GEN2_DISABLED) : 0)) &&
(!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

mac_phy_txswing O Controls the PHY transmitter voltage swing level:


■ 0: Full swing
■ 1: Low swing
The controller drives this output from the 'Config PHY Tx Swing' bit in
the 'Link Width and Speed Change Control Register'. Implementation of
this signal is optional.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 2) : CX_S_CPCIE_MODE ?
(CX_GEN2_MODE != GEN2_DISABLED) : 0)) &&
(!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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Gen2/3-Only PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

cfg_hw_auto_sp_dis O Autonomous speed disable. Used in downstream ports only.


Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 2) : CX_S_CPCIE_MODE ?
(CX_GEN2_MODE != GEN2_DISABLED) : 0))
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Gen3-Only Equalization PIPE Signals

5.54 Gen3-Only Equalization PIPE Signals

phy_mac_dirfeedback - - smlh_ltssm_state_rcvry_eq
phy_mac_fomfeedback - - mac_phy_rxpresethint
phy_mac_local_tx_pset_coef - - mac_phy_fs
phy_mac_local_tx_coef_valid - - mac_phy_lf
- mac_phy_local_pset_index
- mac_phy_getlocal_pset_coef
- mac_phy_rxeqinprogress
- mac_phy_invalid_req
- mac_phy_rxeqeval
- mac_phy_dirchange

Table 5-54 Gen3-Only Equalization PIPE Signals

Port Name I/O Description

smlh_ltssm_state_rcvry_eq O This status signal is asserted during all Recovery Equalization states.
Exists: (CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_rxpresethint[((NL*RX_PSET_W O Provides the RX equalization preset hint for the receiver.


D)-1):0] Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!CX_PIPE51_SUPPORT)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_fs[((NL*TX_FS_WD)-1):0] O Provides the FS value advertised by the link partner.


Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Port Name I/O Description

mac_phy_lf[((NL*TX_FS_WD)-1):0] O Provides the LF value advertised by the link partner.


Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_dirfeedback[((NL*DIRFEEDBAC I Provides the link equalization evaluation feedback in the Direction


K_WD)-1):0] Change format. Feedback is provided for each coefficient:
■ [1:0]: C-1
■ [3:2]: C0
■ [5:4]: C+1
The feedback value for each coefficient is encoded as follows:
■ 00: No change
■ 01: Increment by 1
■ 10: Decrement by 1
■ 11: Reserved
The feedback C0 is ignored by the PCIe controller. You should hardwire
this input to a constant value when you are not using Direction Change.
This signal is only used at the 8.0 GT/s signaling rate.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: phy_mac_phystatus is pulsed, per lane

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PCI Express SW Controller Databook Gen3-Only Equalization PIPE Signals

Port Name I/O Description

phy_mac_fomfeedback[((NL*FOMFEEDB I Provides the link equalization evaluation feedback in the Figure of Merit
ACK_WD)-1):0] (FOM) format. The value is encoded as an integer from 0 to 255. You
should hardwire this input to a constant value when you are not using
FOM. This signal is only used at the 8.0 GT/s signaling rate.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: phy_mac_phystatus is pulsed, per lane

phy_mac_local_tx_pset_coef[((NL*TX_CO I These are the coefficients post-mapping from the preset the
EF_WD)-1):0] mac_phy_local_pset_index after a request
mac_phy_getlocal_pset_coef.
■ [5:0]: C-1
■ [11:6]: C0
■ [17:12]: C+1
The controller reflects these values mac_phy_txdeemph when it wants
to apply this preset. You must externally tie-off this input when
CX_GEN3_EQ_PSET_COEF_MAP_MODE ='Programmable Table' ||
'Dynamic MAC'.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: phy_mac_local_tx_coef_valid

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Port Name I/O Description

phy_mac_local_tx_coef_valid[(NL-1):0] I Single pulse indicating that the phy_mac_local_tx_pset_coef bus


correctly represents the coefficients values mapped from the preset the
mac_phy_local_pset_index bus You must externally tie-off this input
when CX_GEN3_EQ_PSET_COEF_MAP_MODE ='Programmable
Table' || 'Dynamic MAC'.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_local_pset_index[((NL*PSET_ID O The TX equalization preset that the MAC wants the PHY to convert into
_WD)-1):0] coefficients. For more details, see mac_phy_getlocal_pset_coef
description. You can leave this output unconnected when
CX_GEN3_EQ_PSET_COEF_MAP_MODE ='Programmable Table' ||
'Dynamic MAC'. For ESM mode the ESM data rata0 corresponds to
PCIe mode 8 GT/s and the ESM data rate1 corresponds to PCIe mode
16 GT/s.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_getlocal_pset_coef[(NL-1):0] O Single pulse used by MAC to request the PHY to perform a


preset-to-co- efficient mapping, from preset mac_phy_local_pset_index,
to coefficients phy_mac_local_tx_pset_coef. You can leave this output
unconnected when CX_GEN3_EQ_PSET_COEF_MAP_MODE
='Programmable Table' || 'Dynamic MAC'.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Gen3-Only Equalization PIPE Signals

Port Name I/O Description

mac_phy_rxeqinprogress[(NL-1):0] O This status signal is asserted and remains asserted for the duration of
Recovery.Equalization Phase2 when the PCIe controller is the USP
(Phase3 when DSP).
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_invalid_req[(NL-1):0] O Indicates that the Link Evaluation feedback requested a link partner TX
EQ setting that was out of range. The controller asserts this signal when
it detects an out-of-range error. It remains asserted until the next time
mac_phy_rxeqeval asserts.
Note: If your PHY requires mac_phy_invalid_req to follow the same
timing protocol as mac_phy_rxeqeval, you must program
GEN3_RELATED_OFF[23] register field to '1'.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_rxeqeval[(NL-1):0] O The PHY starts evaluation of the far end transmitter TX EQ settings
while this signal is held high by the controller.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Gen3-Only Equalization PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

mac_phy_dirchange[(NL-1):0] O Indicates the PHY to perform Figure Of Merit or Direction Change


evaluation. 0: when mac_phy_rxeqeval = 1, the PHY performs Figure
Of Merit 1: when mac_phy_rxeqeval = 1, the PHY performs Direction
Change
Note: If your PHY does not support the mac_phy_dirchange signal you
can leave this pin unconnected.
Note: If your PHY supports mac_phy_dirchange signal, then your PHY
must drive phy_mac_dirfeedback signal value to 0 when
mac_phy_dirchange = 0.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE)))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Gen3-Only Equalization V7 Signals

5.55 Gen3-Only Equalization V7 Signals

phy_mac_v7_txeq_fs - - mac_phy_v7_rxeq_preset
phy_mac_v7_txeq_lf - - mac_phy_v7_rxeq_lffs
phy_mac_v7_rxeq_done - - mac_phy_v7_txeq_control
phy_mac_v7_rxeq_adapt_done - - mac_phy_v7_rxeq_control
phy_mac_v7_txeq_done - - mac_phy_v7_txeq_preset
phy_mac_v7_txeq_coeff - - mac_phy_v7_txeq_deemph
phy_mac_v7_rxeq_new_txcoeff - - mac_phy_v7_rxeq_txpreset
phy_mac_v7_rxeq_lffs_sel -

Table 5-55 Gen3-Only Equalization V7 Signals

Port Name I/O Description

phy_mac_v7_txeq_fs[(TX_FS_WD-1):0] I TX Equalization Full Swing. Value based on characteristics of TX driver.


For Gen3 only.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_v7_txeq_lf[(TX_FS_WD-1):0] I TX Equalization Low Frequency. Value based on characteristics of TX


driver. For Gen3 only.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_v7_rxeq_preset[((NL*RX_PSET O RX Equalization Preset. For Gen3 only.


_WD)-1):0] Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: pipe_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Gen3-Only Equalization V7 Signals PCI Express SW Controller Databook

Port Name I/O Description

mac_phy_v7_rxeq_lffs[((NL*TX_FS_WD)- O RX Equalization Remote Transmitter Low Frequency / Full Swing. For


1):0] Gen3 only.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: pipe_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_v7_rxeq_done[(NL-1):0] I RX Equalization Done for mac_phy_v7_rxeq_control. Must set


mac_phy_v7_rxeq_control back to 00b when phy_mac_v7_rxeq_done
== 1b detected.
■ 0b: RX equalization not done
■ 1b: RX equalization done
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_v7_rxeq_adapt_done[(NL-1):0] I RX Equalization Adaptation Done for mac_phy_v7_rxeq_control == 10b


and 11b.
■ if both phy_mac_v7_rxeq_adapt_done == 1b and phy_mac_v7_rx-
eq_done == 1b, then RX equalization is successfully done.
■ if phy_mac_v7_rxeq_adapt_done == 0b and phy_mac_v7_rxeq_-
done == 1b, then perform RX equalization again.
■ 0b: RX equalization not done
■ 1b: RX equalization done
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Gen3-Only Equalization V7 Signals

Port Name I/O Description

phy_mac_v7_txeq_done[(NL-1):0] I TX Equalization Done for mac_phy_v7_txeq_control. Must set


mac_phy_v7_txeq_control back to 00b when phy_mac_v7_txeq_done
== 1b detected. For Gen3 only.
■ 0b: TX equalization not done
■ 1b: TX equalization done
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_v7_txeq_coeff[((NL*TX_COEF_ I TX Equalization Coefficient. Display the current coefficient on TX driver.


WD)-1):0] For Gen3 only.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: phy_mac_txeq_done

phy_mac_v7_rxeq_new_txcoeff[((NL*TX_ I RX Equalization New TX Coefficient. Valid only when


COEF_WD)-1):0] phy_mac_v7_rxeq_done == 1b.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: phy_mac_rxeq_done

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Port Name I/O Description

phy_mac_v7_rxeq_lffs_sel[(NL-1):0] I RX Equalization Remote Transmitter Low Frequency / Full Swing


Select. This signal serves two indications. (1) Full swing or low
frequency. (2) Coefficient or preset. When phy_mac_rxeq_done = 0b,
then mac_phy_v7_rxeq_lffs is either indicating low frequency or full
swing:
■ 0b: Full swing
■ 1b: Low frequency
When phy_mac_rxeq_done = 1b, then phy_mac_v7_rxeq_new_txcoeff
is either indicating coefficient or preset:
■ 0b: Coefficients
■ 1b: Preset
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: phy_mac_rxeq_done

mac_phy_v7_txeq_control[((NL*2)-1):0] O TX Equalization Control. Must set back to 00b when


phy_mac_v7_txeq_done = 1b detected. For Gen3 only.
■ 00b: Idle
■ 01b: Tx Preset
■ 10b: Tx Coefficients
■ 11b: Tx Query
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: pipe_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Gen3-Only Equalization V7 Signals

Port Name I/O Description

mac_phy_v7_rxeq_control[((NL*2)-1):0] O RX Equalization Control. Must set back to 00b when


phy_mac_rxeq_done = 1b detected. For Gen3 only.
■ 00b: Idle
■ 01b: Rx Preset
■ 10b: Rx Margining, for Rx EQ phase 2/3
■ 11b: Rx Adaptation, for Rx EQ phase 2/3 bypass
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: pipe_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_v7_txeq_preset[((NL*TX_PSET O TX Equalization Preset. Use when mac_phy_v7_txeq_control == 01b.


_WD)-1):0] For Gen3 only.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: pipe_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_v7_txeq_deemph[((NL*TX_CRS O TX Equalization De-Emphasis. Use when mac_phy_v7_txeq_control ==


R_WD)-1):0] 10b. 3 consecutive PCLK cycles are required to register the new 18-bit
TX coefficient. For Gen3 only.
■ 1st cycle for pre-cursor
■ 2nd cycle for main-cursor
■ 3rd cycle for post-cursor
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: pipe_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Gen3-Only Equalization V7 Signals PCI Express SW Controller Databook

Port Name I/O Description

mac_phy_v7_rxeq_txpreset[((NL*TX_PSE O RX Equalization Remote Transmitter Preset. For Gen3 only.


T_WD)-1):0] Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& (!PHY_IS_PIPE && PHY_IS_V7)
Synchronous To: pipe_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Gen3-Only PIPE Signals

5.56 Gen3-Only PIPE Signals

phy_mac_rxstartblock - - mac_phy_txsyncheader
phy_mac_rxsyncheader - - mac_phy_txstartblock
phy_mac_localfs - - mac_phy_encodedecodebypass
phy_mac_locallf - - mac_phy_blockaligncontrol

Table 5-56 Gen3-Only PIPE Signals

Port Name I/O Description

mac_phy_txsyncheader[((NL*2)-1):0] O At 8.0 GT/s this is used by the PCIe controller MAC to tell the PHY the
value of the Sync header in the current 130b block.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
(!SNPS_RSVDPARAM_26)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_txstartblock[(NL-1):0] O Only used at the 8.0 GT/s signaling rate. This signal allows the PCIe
controller MAC to indicate (to the PHY) the starting cycle
mac_phy_txdata for a 128b block.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
(!SNPS_RSVDPARAM_26)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Gen3-Only PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

mac_phy_encodedecodebypass O Controls if the PHY does encode and decode operations.


■ 0: Encode/decode performed normally by the PHY
■ 1: Encode/decode bypassed
Support of this signal is optional for a PHY. The Synopsys controller
always sets this output to 0.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,{None}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_blockaligncontrol O Enable EIEOS detection in the PHY. EIEOS detection is one of the
mechanisms used to control the block aligner in the PHY. The PCIe
controller uses this signal at the 8.0 GT/s signaling rate to disable the
PHY from searching for a new block alignment. The PHY should ignore
this signal in Gen3 loopback slave mode. This output is a level signal
and not a pulse. It is not time-sensitive, so you can re-register it if
required.
Note:For Virtex-7 GTX PHY configurations, EIOS detection is not used
and this Block Align Control output directs the PHY to perform internal
sync header detection and re-alignment.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
(!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Gen3-Only PIPE Signals

Port Name I/O Description

phy_mac_rxstartblock[((NL*PHY_RXSB_ I Only used at the 8.0 GT/s signaling rate. This signal allows the PHY to
WD)-1):0] indicate (to the PCIe controller MAC) the starting cycle phy_mac_rxdata
for a 128b block. The starting byte for a 128b block must always start
with Bit 0 of the data interface.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
(!SNPS_RSVDPARAM_26)
Synchronous To:
aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_rxsyncheader[((NL*PHY_RXSH I At 8.0 GT/s this is used by the PHY to tell the PCIe controller MAC the
_WD)-1):0] value of the Sync header in the current 130b block.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
(!SNPS_RSVDPARAM_26)
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_localfs[((NL*TX_FS_WD)-1):0] I At 8.0 GT/s rate, it is the Local FS value advertised by the local PHY.
This signal is driven to a constant value following the first speed change
to Gen3. You must externally tie-off this input when
CX_GEN3_EQ_PSET_COEF_MAP_MODE ='Programmable Table'.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Gen3-Only PIPE Signals PCI Express SW Controller Databook

Port Name I/O Description

phy_mac_locallf[((NL*TX_FS_WD)-1):0] I At 8.0 GT/s rate, it is the Local LF value advertised by the local PHY.
This signal is driven to a constant value following the first speed change
to Gen3. You must externally tie-off this input when
CX_GEN3_EQ_PSET_COEF_MAP_MODE ='Programmable Table'.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Gen4-Only Margining Signals

5.57 Gen4-Only Margining Signals

app_margining_ready -
app_margining_software_ready -

Table 5-57 Gen4-Only Margining Signals

Port Name I/O Description

app_margining_ready I Margining Ready. Indicates when the PHY or Margining software is


ready to accept margining commands. This signal is reflected in
Margining Ready field of Margining Port Status register. If the PHY can
accept margining commands when the current link speed is 16GT/s,
you can set this signal to a fixed value of '1'. For Synopsys Gen4 PHYs,
this signal should be tied to '1'.
Exists: ((CX_CPCIE_ENABLE)) && (CX_GEN4_MODE !=
GEN4_DISABLED)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

app_margining_software_ready I Margining Software Ready. Indicates that the required margining


software has performed the required initialization when margining is
partially implemented using Device Driver software. This signal is
reflected in Margining Software Ready field of Margining Port Status
register. If MARGINING_USES_DRIVER_SOFTWARE field of
Margining Port Capabilities Register is '0', you can set this signal to a
fixed value of '0'. For Synopsys Gen4 PHYs, this signal should be tied to
'0'.
Exists: ((CX_CPCIE_ENABLE)) && (CX_GEN4_MODE !=
GEN4_DISABLED)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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Gen4-Only PIPE Signals PCI Express SW Controller Databook

5.58 Gen4-Only PIPE Signals

phy_mac_messagebus - - mac_phy_messagebus
phy_mac_pbus - - mac_phy_mbus

Table 5-58 Gen4-Only PIPE Signals

Port Name I/O Description

mac_phy_messagebus[((NL*8)-1):0] O PIPE Compliant MAC driven message bus commands to PHY.


Exists: ((CX_CPCIE_ENABLE)) && ((CX_GEN4_SPEED &&
CX_PIPE44_SUPPORT) || CX_PIPE51_SUPPORT)
Synchronous To: aux_clk,core_clk_ug,{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_messagebus[((NL*8)-1):0] I PIPE Compliant PHY driven message bus commands to MAC.


Exists: ((CX_CPCIE_ENABLE)) && ((CX_GEN4_SPEED &&
CX_PIPE44_SUPPORT) || CX_PIPE51_SUPPORT)
Synchronous To: core_clk_ug,{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

mac_phy_mbus[((NL*8)-1):0] O Synopsys Specific Interface MAC driven Command/Address/Data Bus


for RBI write operation into PHY register.
Exists: ((CX_CPCIE_ENABLE)) && (CX_GEN4_SPEED &&
(!CX_PIPE44_SUPPORT && !CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,core_clk_ug,{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_mac_pbus[((NL*8)-1):0] I Synopsys Specific Interface PHY driven Command/Address/Data Bus


for RBI write operation into MAC register.
Exists: ((CX_CPCIE_ENABLE)) && (CX_GEN4_SPEED &&
(!CX_PIPE44_SUPPORT && !CX_PIPE51_SUPPORT))
Synchronous To: core_clk_ug,{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SerDes PIPE Signals

5.59 SerDes PIPE Signals

pipe_rx_clk -
pipe_rx_rst_n -

Table 5-59 SerDes PIPE Signals

Port Name I/O Description

pipe_rx_clk[(NL-1):0] I RxCLK from external PHY. This clock signal is recovered clock used for
RxData in the SerDes architecture.
Exists: ((CX_CPCIE_ENABLE)) && (SNPS_RSVDPARAM_26)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

pipe_rx_rst_n[(NL-1):0] I Resets controller logic clocked on pipe_rx_clk. Reset logic should


assert pipe_rx_rst_n at same time as core_rst_n and deassert them
synchronous to corresponding pipe_rx_clk.
Exists: ((CX_CPCIE_ENABLE)) && (SNPS_RSVDPARAM_26)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

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Crosslink Signals PCI Express SW Controller Databook

5.60 Crosslink Signals

app_crosslink_time - - smlh_crosslink_active
- smlh_crosslink_time_request

Table 5-60 Crosslink Signals

Port Name I/O Description

app_crosslink_time[7:0] I Crosslink timeout value provided by your application.


Exists: CX_CROSSLINK_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

smlh_crosslink_active O Indicates a change from upstream to downstream or downstream to


upstream.
Exists: CX_CROSSLINK_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

smlh_crosslink_time_request O A pulse indicating the controller needs a new random crosslink timeout
value supplied the app_crosslink_time signal.
Exists: CX_CROSSLINK_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook Peer-to-Peer Signals

5.61 Peer-to-Peer Signals

client0_app_dev_id - - radm_bypass_rsvd
client0_hdr_rsvd - - radm_trgt1_rsvd
client1_app_dev_id -
client1_hdr_rsvd -
client2_app_dev_id -
client2_hdr_rsvd -

Table 5-61 Peer-to-Peer Signals

Port Name I/O Description

client0_app_dev_id[15:0] I Used to provide peer-to-peer traffic completer ID for completion TLPs or


requester ID for request TLPs.
Exists: (!(AMBA_INTERFACE!=0)) && (CX_P2P_ENABLE==1 ||
CC_DEVICE_TYPE==CC_SW)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: client0_tlp_hv is asserted

client0_hdr_rsvd[14:0] I Used to provide header reserved fields for the TLP being presented to
the client0 interface. The input bits are mapped to the TLP header
reserved fields as follows:
■ [14] .....................DWORD2 Byte11, bit[7]
■ [13:12] ................DWORD2 Byte11, bits[1:0] for 32-bit address TLP;
DWORD3 Byte15, bits[1:0] for 64-bit address TLP
■ [11:8] ..................DWORD2 Byte10, bits[7:4]
■ [7:6] ....................DWORD0 Byte2, bits[3:2]
■ [5] .......................DWORD0 Byte1, bit[7]
■ [4:1] ....................DWORD0 Byte1, bits[3:0]
■ [0] .......................DWORD0 Byte0, bit[7]
Exists: (!(AMBA_INTERFACE!=0)) && (CX_P2P_ENABLE==1 ||
CC_DEVICE_TYPE==CC_SW)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: client0_tlp_hv is asserted

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Peer-to-Peer Signals PCI Express SW Controller Databook

Port Name I/O Description

client1_app_dev_id[15:0] I Provides the same information as client0_app_dev_id but for client1.


Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED) &&
(CX_P2P_ENABLE==1 || CC_DEVICE_TYPE==CC_SW)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: client1_tlp_hv is asserted

client1_hdr_rsvd[14:0] I Provides the same information as client0_hdr_rsvd but for the client1
interface.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED) &&
(CX_P2P_ENABLE==1 || CC_DEVICE_TYPE==CC_SW)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: client1_tlp_hv is asserted

client2_app_dev_id[15:0] I Provides the same information as client0_app_dev_id but for client2.


Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED) &&
(CX_P2P_ENABLE==1 || CC_DEVICE_TYPE==CC_SW)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: client2_tlp_hv is asserted

client2_hdr_rsvd[14:0] I Provides the same information as client0_hdr_rsvd but for the client2
interface.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED) &&
(CX_P2P_ENABLE==1 || CC_DEVICE_TYPE==CC_SW)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: client2_tlp_hv is asserted

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PCI Express SW Controller Databook Peer-to-Peer Signals

Port Name I/O Description

radm_bypass_rsvd[((NHQ*15)-1):0] O Used to output header reserved fields of TLPs presented the bypass
interface. The bit mapping is the same as client0_hdr_rsvd.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2)) &&
(CX_P2P_ENABLE==1 || CC_DEVICE_TYPE==CC_SW)
Synchronous To: aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_bypass_hv is asserted

radm_trgt1_rsvd[14:0] O Used to output header reserved fields of TLPs presented the target1
interface. The bit mapping is the same as client0_hdr_rsvd.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
(CX_P2P_ENABLE==1 || CC_DEVICE_TYPE==CC_SW)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_trgt1_hv is asserted

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RAS D.E.S. Event Counter RAM Signals PCI Express SW Controller Databook

5.62 RAS D.E.S. Event Counter RAM Signals

cdm_ras_des_ec_ram_dataout - - cdm_ras_des_ec_ram_addra
- cdm_ras_des_ec_ram_addrb
- cdm_ras_des_ec_ram_datain
- cdm_ras_des_ec_ram_wea
- cdm_ras_des_ec_ram_ena
- cdm_ras_des_ec_ram_enb

Table 5-62 RAS D.E.S. Event Counter RAM Signals

Port Name I/O Description

cdm_ras_des_ec_ram_addra[(RASDES_ O Port A write address for the RAM in RAS D.E.S. event counter register.
EC_RAM_ADDR_WIDTH-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_ec_ram_wea &amp;
cdm_ras_des_ec_ram_ena are asserted

cdm_ras_des_ec_ram_addrb[(RASDES_ O Port B read address for the RAM in RAS D.E.S. event counter register.
EC_RAM_ADDR_WIDTH-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_ec_ram_enb is asserted

cdm_ras_des_ec_ram_datain[(RASDES_ O Port A write data to the RAM in RAS D.E.S. event counter register.
EC_RAM_DATA_WIDTH-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_ec_ram_wea &amp;
cdm_ras_des_ec_ram_ena are asserted

cdm_ras_des_ec_ram_wea O Port A write enable for the RAM in RAS D.E.S. event counter register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook RAS D.E.S. Event Counter RAM Signals

Port Name I/O Description

cdm_ras_des_ec_ram_ena O Port A access enable for the RAM in RAS D.E.S. event counter register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cdm_ras_des_ec_ram_enb O Port B access enable for the RAM in RAS D.E.S. event counter register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cdm_ras_des_ec_ram_dataout[(RASDES I Port B read data from the RAM that used in RAS D.E.S. event counter
_EC_RAM_DATA_WIDTH-1):0] register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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RAS D.E.S. Event Counters Debug Signals PCI Express SW Controller Databook

5.63 RAS D.E.S. Event Counters Debug Signals

- cdm_ras_des_ec_info_common
- cdm_ras_des_ec_info_i (for i = 0; i <=
CX_NL)

Table 5-63 RAS D.E.S. Event Counters Debug Signals

Port Name I/O Description

cdm_ras_des_ec_info_common[(RASDES O Common event signal bus that is used in RAS D.E.S. event counters
_EC_INFO_CM-1):0] ■ [170:167]: rtlh_rx_ccix_tlp_evt: Pulse: Rx CCIX TLP
■ [166:165]: xtlh_tx_ccix_tlp_evt: Pulse: Tx CCIX TLP
■ [164:161]: rtlh_rx_tlpwprefix_evt: Pulse: Rx TLP with Prefix
■ [160:157]: rtlh_rx_atmcop_evt: Pulse: Rx Atomic
■ [156:153]: rtlh_rx_msg_evt: Pulse: Rx Message TLP
■ [152:149]: rtlh_rx_cplwd_evt: Pulse: Rx Completion w data
■ [148:145]: rtlh_rx_cplwod_evt: Pulse: Rx Completion wo data
■ [144:141]: rtlh_rx_iord_evt: Pulse: Rx IO Read
■ [140:137]: rtlh_rx_iowr_evt: Pulse: Rx IO Write
■ [136:133]: rtlh_rx_cfgrd_evt: Pulse: Rx Config Read
■ [132:129]: rtlh_rx_cfgwr_evt: Pulse: Rx Config Write
■ [128:125]: rtlh_rx_memrd_evt: Pulse: Rx Memory Read
■ [124:121]: rtlh_rx_memwr_evt: Pulse: Rx Memory Write
■ [120:119]: xtlh_tx_tlpwprefix_evt: Pulse: Tx TLP with Prefix
■ [118:117]: xtlh_tx_atmcop_evt: Pulse: Tx AtomicOp
■ [116:115]: xtlh_tx_msg_evt: Pulse: Tx Message
■ [114:113]: xtlh_tx_cplwd_evt: Pulse: Tx Completion w data
■ [112:111]: xtlh_tx_cplwod_evt: Pulse: Tx Completion wo data
■ [110:109]: xtlh_tx_iord_evt: Pulse: Tx IO Read
■ [108:107]: xtlh_tx_iowr_evt: Pulse: Tx IO Write
■ [106:105]: xtlh_tx_cfgrd_evt: Pulse: Tx Config Read
■ [104:103]: xtlh_tx_cfgwr_evt: Pulse: Tx Config Write
■ [102:101]: xtlh_tx_memrd_evt: Pulse: Tx Memory Read
■ [100:99]: xtlh_tx_memwr_evt: Pulse: Tx Memory Write
■ [98:95]: rdlh_duplicate_tlp_err_pertlp: Pulse: Rx Duplicate TLP
■ [94]: xtlh_xadm_restore_enable: Pulse: Tx Nullified TLP
■ [93:90]: rdlh_nulified_tlp_err_pertlp : Pulse: Rx Nullified TLP
■ [89:82]: rtlh_rcvd_ufc_perdllp: Pulse: Rx Update FC DLLP
■ [81:74]: rdlh_rcvd_ack_perdllp: Pulse: Rx Ack DLLP
■ [73]: xdlh_update_fc_sent: Pulse: Tx Update FC DLLP
■ [72]: xdlh_ack_sent: Pulse: Tx Ack DLLP
■ [71]: smlh_lwd_change: Pulse: Link width Change
■ [70]: smlh_spd_change: Pulse: Speed Change
■ [69]: smlh_in_l23: Level: L2 Entry

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PCI Express SW Controller Databook RAS D.E.S. Event Counters Debug Signals

Port Name I/O Description

cdm_ras_des_ec_info_common[(RASDES O. ■ [68]: pm_in_l1_abort: Level: L1.2 abort


_EC_INFO_CM-1):0]...(cont.) ■ [67]: pm_in_l1_cpm: Level: L1 Clock PM (L1 with REFCLK
removal/PLL Off)
■ [66]: pm_in_l1_short: Level: L1 short duration
■ [65]: pm_in_l12: Level: L1.2 Entry
■ [64]: pm_in_l11: Level: L1.1 Entry
■ [63]: smlh_in_l1: Level: L1 Entry
■ [62]: pm_asnak: Level: ASPM L1 reject
■ [61]: smlh_in_rl0s: Level: Rx L0s Entry
■ [60]: smlh_in_l0s: Level: Tx L0s Entry
■ [59]: smlh_l1_to_recovery: Pulse: L1 to Recovery Entry
■ [58]: smlh_l0_to_recovery: Pulse: L0 to Recovery Entry
■ [57:56]: cfg_cpl_timeout[1:0]: Pulse: Completion Timeout
■ [55:52]: cfg_ca_tlp: Pulse: Completer Abort
■ [51:48]: cfg_ur_tlp: Pulse: Unsupported Request
■ [47:44]: cfg_ecrc_tlp_err: Pulse: ECRC Error
■ [43:40]: cfg_poisned_tlp: Pulse: Poisoned TLP
■ [39]: rtlh_req_link_retrain: Level: FC Timeout
■ [38]: xdlh_retry_req: Pulse: Retry TLP
■ [37]: xdlh_nak_sent: Pulse: Tx Nak DLLP
■ [36:29]: rdlh_rcvd_nack_perdllp: Pulse: Rx Nak DLLP
■ [28]: xdlh_replay_timeout_err: Pulse: Replay Timeout
■ [27]: xdlh_replay_num_rlover_err: Pulse: Replay_Num Rollover
■ [26:19]: rdlh_bad_dllp_err_perdllp: Pulse: BAD DLLP
■ [18:15]: rdlh_lcrc_tlp_err_pertlp : Pulse: LCRC Error
■ [14:11]: rdlh_bad_tlp_err_pertlp : Pulse: BAD TLP
■ [10]: rmlh_deskew_alignment_err: Level: Deskew Error
■ [9]: rmlh_framing_err: Pulse: Framing Error
■ [8]: smlh_timeout_nfts: Level: FTS Timeout
■ [7]: smlh_rx_rcvry_req: Level: Rx Recovery Request
■ [6]: rmlh_rcvd_err: Pulse: Receiver Error
■ [5]: smlh_eidle_inferred_in_l0: Level: Detect EI Infer
■ [4]: Reserved (fixed "0")
■ [3]: Reserved (fixed "0")
■ [2]: Reserved (fixed "0")
■ [1]: Reserved (fixed "0")
■ [0]: Reserved (fixed "0")
Exists: (CX_RAS_DES_EC_ENABLE) &&
(CX_RAS_DES_DBGIO_ENABLE)
Synchronous To:
None,aux_clk,aux_clk_g,perbitclk,radm_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by:

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Port Name I/O Description

cdm_ras_des_ec_info_common[(RASDES O.. Not validated by another signal


_EC_INFO_CM-1):0]...(cont..)

cdm_ras_des_ec_info_i[(RASDES_EC_IN O Laneievent signal bus that is used in RAS D.E.S. event counters.
FO_PL-1):0] ■ [12]: |rmlh_deskew_ctlskp_err[i*5+4:i*5+3]: Pulse: Margin CRC and
(for i = 0; i <= CX_NL) Parity Error
■ [11]: rmlh_deskew_ctlskp_err[i*5+2]: Pulse: 2nd Retimer Parity Error
■ [10]: rmlh_deskew_ctlskp_err[i*5+1]: Pulse: 1st Retimer Parity Error
■ [9]: rmlh_deskew_ctlskp_err[i*5]: Pulse: CTL SKP OS Data Parity
Error
■ [8]: rmlh_ebuf_rxskipremoved: Pulse: EBUF SKP Del
■ [7]: rmlh_ebuf_rxskipadded: Pulse: EBUF SKP Add
■ [6]: rmlh_rxvalid_deasserted: Pulse: Rx Valid de-assertion
■ [5]: rmlh_sync_header_err: Pulse: SYNC Header Error
■ [4]: rmlh_skp_parity_err: Pulse: SKP OS Parity Error
■ [3]: rmlh_phy_rxdisperror: Pulse: Running Disparity Error
■ [2]: rmlh_phy_rxcodeerror: Pulse: Decode Error
■ [1]: rmlh_ebuf_rxunderflow: Pulse: EBUF underrun
■ [0]: rmlh_ebuf_rxoverflow: Pulse: EBUF Overflow
Exists: (CX_RAS_DES_EC_ENABLE) &&
(CX_RAS_DES_DBGIO_ENABLE)
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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PCI Express SW Controller Databook RAS D.E.S. Silicon Debug Internal Signals

5.64 RAS D.E.S. Silicon Debug Internal Signals

app_ras_des_sd_hold_ltssm - - cdm_ras_des_sd_info_common
- cdm_ras_des_sd_info_i (for i = 0; i <=
CX_NL)
- cdm_ras_des_sd_info_vi (for i = 0; i <=
CX_NVC)

Table 5-64 RAS D.E.S. Silicon Debug Internal Signals

Port Name I/O Description

app_ras_des_sd_hold_ltssm I Hold and release LTSSM. For as long as this signal is '1', thecontroller
stays in the current LTSSM.
Exists: CX_RAS_DES_SD_ENABLE
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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RAS D.E.S. Silicon Debug Internal Signals PCI Express SW Controller Databook

Port Name I/O Description

cdm_ras_des_sd_info_common[(RASDES O Common debug signal bus that is used in RAS D.E.S. silicon debug
_SD_INFO_CM-1):0] ■ [78]: init_eq_pending_g4: Level: Equalization sequence Gen5
■ [77:75]: l1sub_state: Level: L1 sub state
■ [74]: init_eq_pending_g4: Level: Equalization sequence Gen4
■ [73]: init_eq_pending: Level: Equalization sequence Gen3
■ [72:61]: xdlh_curnt_seqnum [11:0]: Level: Tx TLP SEQ#
■ [60:49]: rdlh_curnt_rx_ack_seqnum[11:0]: Level: Rx ACK SEQ#
■ [48]: rdlh_vc0_initfc2_status: Level: Init-FC Flag2 VC0
■ [47]: rdlh_vc0_initfc1_status: Level: Init-FC Flag1 VC0
■ [46:45]: rdlh_dlcntrl_state [1:0]: Level: DLCM
■ [44:37]: latched_ts_nfts[7:0]: Level: Latched NFTS
■ [36:34]: ltssm_powerdown[1:0]: Level: PIPE: Power Down
■ [33:18]: smlh_ltssm_variable [15:0]: Level: LTSSM Variable
■ [17]: pm_pme_resend_flag: Pulse: PME Re-Send flag
■ [16]: smlh_lane_reversed: Level: Lane Reversal Operation
■ [15:9]: rmlh_framing_err_ptr[6:0]: Pulse: 1st Framing Error Pointer
■ [8:5]: pm_slave_state[3:0]: Level: PM Internal State (Slave)
■ [4:0]: pm_master_state[4:0]: Level: PM Internal State (Master)
Exists: (CX_RAS_DES_SD_ENABLE) &&
(CX_RAS_DES_DBGIO_ENABLE)
Synchronous To:
None,aux_clk,core_clk,perbitclk,ret_core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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PCI Express SW Controller Databook RAS D.E.S. Silicon Debug Internal Signals

Port Name I/O Description

cdm_ras_des_sd_info_i[(RASDES_SD_IN O Laneidebug signal bus that is used in RAS D.E.S. silicon debug
FO_PL-1):0] ■ [204:203]: eq_convergence_sts_g5 [1:0]: Level: Equalization
(for i = 0; i <= CX_NL) convergence information Gen5
■ [202]: eqpa_violate_rule_123_g5[2]: Level: Rule C Violation Event
Status Gen5
■ [201]: eqpa_violate_rule_123_g5[1]: Level: Rule B Violation Event
Status Gen5
■ [200]: eqpa_violate_rule_123_g5[0]: Level: Rule A Violation Event
Status Gen5
■ [199]: mac_cdm_ras_des_reject_rtx_g5: Level: Receive Reject
Coefficient Event status Gen5
■ [198:191]: phy_cdm_ras_des_fomfeedback_g5: Level: Current
Figure of Merit Gen5
■ [190:185]: mac_cdm_ras_des_coef_ltx_g5[5:0]: Level: Current
Local Transmitter Pre Cursor coefficient Gen5
■ [184:179]: mac_cdm_ras_des_coef_ltx_g5[11:6]: Level: Current
Local Transmitter Cursor coefficient Gen5
■ [178:173]: mac_cdm_ras_des_coef_ltx_g5[17:12]: Level: Current
Local Transmitter Post Cursor coefficient Gen5
■ [172:167]: mac_cdm_ras_des_coef_rtx_g5[5:0]: Level: Current
Remote Transmitter Pre Cursor coefficient Gen5
■ [166::161]: mac_cdm_ras_des_coef_rtx_g5[11:6]: Level: Current
Remote Transmitter Cursor coefficient Gen5
■ [160:155]: mac_cdm_ras_des_coef_rtx_g5[17:12]: Level: Current
Remote Transmitter Post Cursor coefficient Gen5
■ [154:149]: mac_cdm_ras_des_lf_g5: Level: Remote Device LF
Gen5
■ [148:143]: mac_cdm_ras_des_fs_g5: Level: Remote Device FS
Gen5
■ [142:141]: eq_convergence_sts_g4 [1:0]: Level: Equalization
convergence information Gen4
■ [140]: eqpa_violate_rule_123_g4[2]: Level: Rule C Violation Event
Status Gen4
■ [139]: eqpa_violate_rule_123_g4[1]: Level: Rule B Violation Event
Status Gen4
■ [138]: eqpa_violate_rule_123_g4[0]: Level: Rule A Violation Event
Status Gen4
■ [137]: mac_cdm_ras_des_reject_rtx_g4: Level: Receive Reject
Coefficient Event status Gen4
■ [136:129]: phy_cdm_ras_des_fomfeedback_g4: Level: Current
Figure of Merit Gen4
■ [128:126]: 3'b000: Reserved
■ [125:120]: mac_cdm_ras_des_coef_ltx_g4[5:0]: Level: Current
Local Transmitter Pre Cursor coefficient Gen4

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RAS D.E.S. Silicon Debug Internal Signals PCI Express SW Controller Databook

Port Name I/O Description

...(cont.) O. ■ [119:114]: mac_cdm_ras_des_coef_ltx_g4[11:6]: Level: Current


Local Transmitter Cursor coefficient Gen4
■ [113:108]: mac_cdm_ras_des_coef_ltx_g4[17:12]: Level: Current
Local Transmitter Post Cursor coefficient Gen4
■ [107:102]: mac_cdm_ras_des_coef_rtx_g4[5:0]: Level: Current
Remote Transmitter Pre Cursor coefficient Gen4
■ [101:96]: mac_cdm_ras_des_coef_rtx_g4[11:6]: Level: Current
Remote Transmitter Cursor coefficient Gen4
■ [95:90]: mac_cdm_ras_des_coef_rtx_g4[17:12]: Level: Current
Remote Transmitter Post Cursor coefficient Gen4
■ [89:84]: mac_cdm_ras_des_lf_g4: Level: Remote Device LF Gen4
■ [83:78]: mac_cdm_ras_des_fs_g4: Level: Remote Device FS Gen4
■ [77:76]: eq_convergence_sts [1:0]: Level: Equalization convergence
information Gen3
■ [75]: eqpa_violate_rule_123[2]: Level: Rule C Violation Event Status
Gen3
■ [74]: eqpa_violate_rule_123[1]: Level: Rule B Violation Event Status
Gen3
■ [73]: eqpa_violate_rule_123[0]: Level: Rule A Violation Event Status
Gen3
■ [72]: mac_cdm_ras_des_reject_rtx: Level: Receive Reject Coeffi-
cient Event status Gen3
■ [71:64]: phy_cdm_ras_des_fomfeedback: Level: Current Figure of
Merit Gen3
■ [63:61]: mac_cdm_ras_des_pset_lrx: Level: Current Local Receiver
Preset Hint Gen3
■ [60:55]: mac_cdm_ras_des_coef_ltx[5:0]: Level: Current Local
Transmitter Pre Cursor coefficient Gen3
■ [54:49]: mac_cdm_ras_des_coef_ltx[11:6]: Level: Current Local
Transmitter Cursor coefficient Gen3
■ [48:43]: mac_cdm_ras_des_coef_ltx[17:12]: Level: Current Local
Transmitter Post Cursor coefficient Gen3
■ [42:37]: mac_cdm_ras_des_coef_rtx[5:0]: Level: Current Remote
Transmitter Pre Cursor coefficient Gen3
■ [36:31]: mac_cdm_ras_des_coef_rtx[11:6]: Level: Current Remote
Transmitter Cursor coefficient Gen3
■ [30:25]: mac_cdm_ras_des_coef_rtx[17:12]: Level: Current Remote
Transmitter Post Cursor coefficient Gen3
■ [24:19]: mac_cdm_ras_des_lf: Level: Remote Device LF Gen3
■ [18:13]: mac_cdm_ras_des_fs: Level: Remote Device FS Gen3

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PCI Express SW Controller Databook RAS D.E.S. Silicon Debug Internal Signals

Port Name I/O Description

...(cont..) O.. ■ [12:5]: rmlh_deskew_fifo_ptr: Level: Deskew Pointer


■ [4]: mac_phy_rxpolarity: Level: PIPE: RxPolarity
■ [3]: latched_rxdetected: Level: PIPE: Detect Lane
■ [2]: phy_mac_rxvalid_rxburst: Level: PIPE: RxValid/RxBurst
■ [1]: phy_mac_rxelec_rxh8exit: Level: PIPE: RxElecIdle/RxHi-
bern8ExitType1
■ [0]: mac_phy_txelec_txburst: Level: PIPE: TxElecIdle/TxBurst
Exists: (CX_RAS_DES_SD_ENABLE) &&
(CX_RAS_DES_DBGIO_ENABLE)
Synchronous To: None,aux_clk_g,perbitclk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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RAS D.E.S. Silicon Debug Internal Signals PCI Express SW Controller Databook

Port Name I/O Description

cdm_ras_des_sd_info_vi[(RASDES_SD_I O VCidebug signal bus that is used in RAS D.E.S. silicon debug.
NFO_PV-1):0] ■ [239:228]: rtlh_fc_allctd_cpld: Level: Credit Allocated (CD) VCn
(for i = 0; i <= CX_NVC)
■ [227:220]: rtlh_fc_allctd_cplh: Level: Credit Allocated (CH) VCn
■ [219:208]: rtlh_fc_allctd_npd: Level: Credit Allocated (ND) VCn
■ [207:200]: rtlh_fc_allctd_nph: Level: Credit Allocated (NH) VCn
■ [199:188]: rtlh_fc_allctd_pd: Level: Credit Allocated (PD) VCn
■ [187:180]: rtlh_fc_allctd_ph: Level: Credit Allocated (PH) VCn
■ [179:168]: rtlh_fc_rcvd_cpld: Level: Credit Received (CD) VCn
■ [167:160]: rtlh_fc_rcvd_cplh: Level: Credit Received (CH) VCn
■ [159:148]: rtlh_fc_rcvd_npd: Level: Credit Received (ND) VCn
■ [147:140]: rtlh_fc_rcvd_nph: Level: Credit Received (NH) VCn
■ [139:128]: rtlh_fc_rcvd_pd: Level: Credit Received (PD) VCn
■ [127:120]: rtlh_fc_rcvd_ph: Level: Credit Received (PH) VCn
■ [119:108]: xadm_fc_limit_cpld: Level: Credit Limit (CD) VCn
■ [107:100]: xadm_fc_limit_cplh: Level: Credit Limit (CH) VCn
■ [99:88]: xadm_fc_limit_npd: Level: Credit Limit (ND) VCn
■ [87:80]: xadm_fc_limit_nph: Level: Credit Limit (NH) VCn
■ [79:68]: xadm_fc_limit_pd: Level: Credit Limit (PD) VCn
■ [67:60]: xadm_fc_limit_ph: Level: Credit Limit (PH) VCn
■ [59:48]: xadm_fc_cnsmd_cpld: Level: Credit Consumed (CD) VCn
■ [47:40]: xadm_fc_cnsmd_cplh: Level: Credit Consumed (CH) VCn
■ [39:28]: xadm_fc_cnsmd_npd: Level: Credit Consumed (ND) VCn
■ [27:20]: xadm_fc_cnsmd_nph: Level: Credit Consumed (NH) VCn
■ [19:8]: xadm_fc_cnsmd_pd: Level: Credit Consumed (PD) VCn
■ [7:0]: xadm_fc_cnsmd_ph: Level: Credit Consumed (PH) VCn
Exists: (CX_RAS_DES_SD_ENABLE) &&
(CX_RAS_DES_DBGIO_ENABLE) && (Always)
Synchronous To: aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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PCI Express SW Controller Databook RAS D.E.S. Time-Based Analysis Debug Signals

5.65 RAS D.E.S. Time-Based Analysis Debug Signals

app_ras_des_tba_ctrl - - cdm_ras_des_tba_info_common

Table 5-65 RAS D.E.S. Time-Based Analysis Debug Signals

Port Name I/O Description

cdm_ras_des_tba_info_common[(RASDE O Common event signal status bus used in RAS D.E.S. time based
S_TBA_INFO_CM-1):0] analysis. Indicates the internal signals that are used in the time-based
analysis . The results are in TIME_BASED_ANALYSIS_DATA_REG.
Each bit indicates the state that the controller stays in. All signals are
level sensitive unless otherwise indicated.
■ [6]: smlh_link_in_training: Config/Recovery
■ [5]: pm_in_l12: L1.2
■ [4]: pm_in_l11: L1.1
■ [3]: smlh_in_l1: L1
■ [2]: smlh_in_l0: L0
■ [1]: smlh_in_rl0s: Rx L0s
■ [0]: smlh_in_l0s: Tx L0s
Exists: (CX_RAS_DES_TBA_ENABLE) &&
(CX_RAS_DES_DBGIO_ENABLE)
Synchronous To: None,aux_clk,perbitclk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: See description.
Validated by: Not validated by another signal

app_ras_des_tba_ctrl[1:0] I Controls the start/end of time based analysis. You must only set the pins
to the required value for the duration of one clock cycle. This signal must
be 2'b00 while the TIMER_START field in
TIME_BASED_ANALYSIS_CONTROL_REG register is controlled by
the DBI interface or the accesses from the wire side.
■ 2'b00: No action
■ 2'b01: Start
■ 2'b10: End. This setting is only used when the TIME_BASED_DU-
RATION_SELECT field of TIME_BASED_ANALYSIS_CON-
TROL_REG is set to "manual control".
■ 2'b11: Reserved
These pins also set the contents of the TIMER_START field in
TIME_BASED_ANALYSIS_CONTROL_REG register.
Exists: CX_RAS_DES_TBA_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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RAS D.E.S. Time-Based Analysis RAM Signals PCI Express SW Controller Databook

5.66 RAS D.E.S. Time-Based Analysis RAM Signals

cdm_ras_des_tba_ram_dataout - - cdm_ras_des_tba_ram_addra
- cdm_ras_des_tba_ram_addrb
- cdm_ras_des_tba_ram_datain
- cdm_ras_des_tba_ram_wea
- cdm_ras_des_tba_ram_ena
- cdm_ras_des_tba_ram_enb

Table 5-66 RAS D.E.S. Time-Based Analysis RAM Signals

Port Name I/O Description

cdm_ras_des_tba_ram_addra[(RASDES_ O Port A write address for the RAM in RAS D.E.S. time based analysis
TBA_RAM_ADDR_WIDTH-1):0] register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_tba_ram_wea &amp;
cdm_ras_des_tba_ram_ena are asserted

cdm_ras_des_tba_ram_addrb[(RASDES_ O Port B read address for the RAM in RAS D.E.S. time based analysis
TBA_RAM_ADDR_WIDTH-1):0] register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_tba_ram_enb is asserted

cdm_ras_des_tba_ram_datain[(RASDES_ O Port A write data for the RAM in RAS D.E.S. time based analysis
TBA_RAM_DATA_WIDTH-1):0] register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_tba_ram_wea &amp;
cdm_ras_des_tba_ram_ena are asserted

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PCI Express SW Controller Databook RAS D.E.S. Time-Based Analysis RAM Signals

Port Name I/O Description

cdm_ras_des_tba_ram_wea O Port A write enable for the RAM in RAS D.E.S. time based analysis
register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cdm_ras_des_tba_ram_ena O Port A access enable for the RAM in RAS D.E.S. time based analysis
register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cdm_ras_des_tba_ram_enb O Port B access enable for the RAM in RAS D.E.S. time based analysis
register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cdm_ras_des_tba_ram_dataout[(RASDES I Port B read data from the RAM that used in RAS D.E.S. time based
_TBA_RAM_DATA_WIDTH-1):0] analysis register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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Configuration Intercept Interface (CII) Signals PCI Express SW Controller Databook

5.67 Configuration Intercept Interface (CII) Signals

cii_lbc_halt - - lbc_cii_hv
cii_lbc_override_en - - lbc_cii_hdr_poisoned
cii_lbc_override_data - - lbc_cii_hdr_type
- lbc_cii_hdr_first_be
- lbc_cii_hdr_tag
- lbc_cii_hdr_req_id
- lbc_cii_hdr_addr
- lbc_cii_hdr_bus_num
- lbc_cii_hdr_dev_num
- lbc_cii_hdr_func_num
- lbc_cii_dv
- lbc_cii_data

Table 5-67 Configuration Intercept Interface (CII) Signals

Port Name I/O Description

lbc_cii_hv O Indicates that the header information outputs and lbc_cii_dv signal of
CII are valid. For more details, see the "Advanced LBC and DBI Usage"
advanced information chapter in the Databook.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

lbc_cii_hdr_poisoned O The Poisoned (EP) bit in the received TLP header on CII.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

lbc_cii_hdr_type[4:0] O The Type field in the received TLP header on CII. Only the following TLP
Type can be appeared on CII.
■ 00100b: Configuration Read/Write Type0
■ 00101b: Configuration Read/Write Type1 (SRIOV configuration
only)
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

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PCI Express SW Controller Databook Configuration Intercept Interface (CII) Signals

Port Name I/O Description

lbc_cii_hdr_first_be[3:0] O The first dword byte enable field in the received TLP header on CII.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

lbc_cii_hdr_tag[(TAG_SIZE-1):0] O The Tag field in the received TLP header on CII.


Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

lbc_cii_hdr_req_id[15:0] O The requester ID in the received TLP header on CII.


■ [15:8]: Bus number
■ [7:3]: Device number
■ [2:0]: Function number
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

lbc_cii_hdr_addr[11:0] O The Register Address in the received TLP header on CII.


■ [11:8]: Extended Register Number[3:0]
■ [7:2]: Register Number[5:0]
■ [1:0]: Reserved
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

lbc_cii_hdr_bus_num[7:0] O The Bus number in the received TLP header on CII.


Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

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Configuration Intercept Interface (CII) Signals PCI Express SW Controller Databook

Port Name I/O Description

lbc_cii_hdr_dev_num[4:0] O The Device number in the received TLP header on CII.


Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

lbc_cii_hdr_func_num[(PF_WD-1):0] O Identifies the targeted controller physical function (PF).


Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

lbc_cii_dv O Indicates that the data information outputs of CII are valid. This signal is
asserted only for a configuration Write request.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

lbc_cii_data[31:0] O Received TLP payload data from the link partner to your application
client. The data is in little endian format. The first received payload byte
is in [7:0].
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_dv is asserted

cii_lbc_halt I Flow control input signal. When cii_lbc_halt is asserted, the controller
halts processing of CFG requests for the CDM and ELBI configuration
spaces. For more details, see the "Advanced LBC and DBI Usage"
advanced information chapter in the Databook.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

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PCI Express SW Controller Databook Configuration Intercept Interface (CII) Signals

Port Name I/O Description

cii_lbc_override_en I Override enable. When your application logic asserts this input, the
controller overrides the CfgWr payload or CfgRd completion using the
data supplied by your application logic on cii_lbc_override_data. For
more details, see the "Advanced LBC and DBI Usage" advanced
information chapter in the Databook.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

cii_lbc_override_data[31:0] I Override data.


■ CfgWr: override write data to CDM register with data supplied by
your application logic on cii_lbc_override_data.
■ CfgRd: override data payload of the completion TLP with data
supplied by your application logic on cii_lbc_override_data.
For more details, see the "Advanced LBC and DBI Usage" advanced
information chapter in the Databook.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted

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EXTSRIOV: PF Registers Value for VF Function Signals PCI Express SW Controller Databook

5.68 EXTSRIOV: PF Registers Value for VF Function Signals

- cfg_reg_serren
- cfg_cor_err_rpt_en
- cfg_nf_err_rpt_en
- cfg_f_err_rpt_en

Table 5-68 EXTSRIOV: PF Registers Value for VF Function Signals

Port Name I/O Description

cfg_reg_serren[(NF-1):0] O PF's SERR# Enable registers value in Command Register of Type0


Header, for setting error status registers of external VFs.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_cor_err_rpt_en[(NF-1):0] O PF's Correctable Error Reporting Enable registers value in Device


Control Register of PCIe Capability, for sending ERR_MSG of external
VFs.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_nf_err_rpt_en[(NF-1):0] O PF's Non-Fatal Error Reporting Enable registers value in Device Control
Register of PCIe Capability, for sending ERR_MSG of external VFs.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_f_err_rpt_en[(NF-1):0] O PF's Fatal Error Reporting Enable registers value in Device Control
Register of PCIe Capability, for sending ERR_MSG of external VFs.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook PHY Register Bus Interface Signals

5.69 PHY Register Bus Interface Signals

app_hold_phy_rst - - en_phy_reg_clk_g
phy_reg_clk_ug - - phy_cr_para_wr_en
phy_reg_clk_g - - phy_cr_para_rd_en
phy_reg_rst_n - - phy_cr_para_addr
phy_cr_para_ack - - phy_cr_para_wr_data
phy_cr_para_rdata -

Table 5-69 PHY Register Bus Interface Signals

Port Name I/O Description

app_hold_phy_rst I Set this signal to one before the de-assertion of power on reset to hold
the PHY in reset. This can be used to configure your PHY. Synopsys
PHYs can be configured through the PHY Viewport if desired. Please tie
this port to zero if your design does not need this feature.
Exists: Always
Synchronous To: aux_clk_g,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

phy_reg_clk_ug I Ungated clock for the PHY register interface. This clock should be
always active when you need to access the PHY registers through the
PHY register bus interface(PRBI). The maximum frequency of the clock
is 100 MHz.
Note:For Synopsys PHYs supporting Control Register (CR) Parallel
Interface, this signal should not be connected to the PHY if the PHY
registers are accessed through the PRBI. You should connect
phy_reg_clk_g to the PHY.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: N/A
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

phy_reg_clk_g I This clock is gated by en_phy_reg_clk_g for the PHY Register Bus
Interface.
Note:For Synopsys PHYs supporting Control Register (CR) Parallel
Interface, this clock should be used as cr_para_clk.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: N/A
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal

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PHY Register Bus Interface Signals PCI Express SW Controller Databook

Port Name I/O Description

en_phy_reg_clk_g O Enable phy_reg_clk_g. phy_reg_clk_g should be active while this signal


is 1.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: phy_reg_clk_ug
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_reg_rst_n I Reset for the phy_reg_clk_ug/phy_reg_clk_g domain. The reset logic


should assert phy_reg_rst_n at the same time as sticky_rst_n and
deassert synchronous to phy_reg_clk_ug. /
Note:For Synopsys PHYs supporting Control Register (CR) Parallel
Interface, this signal should not be connected to the PHY.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal

phy_cr_para_ack[(PHY_VPT_NUM-1):0] I Control Register (CR) Read/Write acknowledgment. This signal


indicates the completion of a CR parallel read/write access.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: phy_reg_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_cr_para_rdata[((PHY_VPT_NUM*PH I Control Register (CR) read data.


Y_VPT_DATA)-1):0] Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: phy_reg_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: phy_cr_para_ack

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PCI Express SW Controller Databook PHY Register Bus Interface Signals

Port Name I/O Description

phy_cr_para_wr_en[(PHY_VPT_NUM-1):0 O Control Register (CR) write enable. When this signal is asserted, data
] on phy_cr_para_wr_data is written to the address referenced on
phy_cr_para_addr. This signal is asserted for a single cycle.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: phy_reg_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_cr_para_rd_en[(PHY_VPT_NUM-1):0 O Control Register (CR) read enable. When this signal is asserted, data is
] read from the address referenced on phy_cr_para_addr and provided
on phy_cr_para_rd_data. This signal is asserted for a single cycle.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: phy_reg_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

phy_cr_para_addr[15:0] O Control Register (CR) Read/Write address.


Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: phy_reg_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: (|phy_cr_para_wr_en) || (|phy_cr_para_rd_en)

phy_cr_para_wr_data[(PHY_VPT_DATA-1 O Control Register (CR) write data.


):0] Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: phy_reg_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: |phy_cr_wr_en

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SII: ATS Capability Signals PCI Express SW Controller Databook

5.70 SII: ATS Capability Signals

- cfg_vf_ats_stu
- cfg_vf_ats_cache_en

Table 5-70 SII: ATS Capability Signals

Port Name I/O Description

cfg_vf_ats_stu[((5*INT_NVF)-1):0] O ATS status for VFs


Exists: VF_ATS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_vf_ats_cache_en[(INT_NVF-1):0] O ATS cache en


Exists: VF_ATS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: BDF Signals

5.71 SII: BDF Signals

app_dev_num -
app_bus_num -

Table 5-71 SII: BDF Signals

Port Name I/O Description

app_dev_num[4:0] I Device number. Your application must drive this signal to set the device
number in the Requester ID for RC port and Switch DSP port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

app_bus_num[7:0] I Bus number. Your application must drive this signal to set the bus
number in the Requester ID for RC port and Switch DSP port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: DPC Signals PCI Express SW Controller Databook

5.72 SII: DPC Signals

app_dpc_rp_busy - - core_in_dpc
app_dpc_err_valid - - cfg_dpc_int_msg_num
app_dpc_err_bus - - cfg_dpc_rp_ext_dpc
app_dpc_impspec_log - - cfg_dpc_poison_tlp_egr_blk_support
app_flush_ack - - cfg_dpc_sw_trig_support
- cfg_dpc_rp_pio_log_size
- cfg_dpc_dl_active_err_cor_support
- cfg_dpc_trig_en
- cfg_dpc_cpl_cntrl
- cfg_dpc_int_en
- cfg_dpc_err_cor_en
- cfg_dpc_poison_tlp_egr_block_en
- cfg_dpc_sw_trigger
- cfg_dpc_dl_active_err_cor_en
- rstctl_core_flush_req

Table 5-72 SII: DPC Signals

Port Name I/O Description

app_dpc_rp_busy I DPC Root Port Busy . When Set, it indicates that the Root Port is busy
with internal activity. DPC is event triggered. Used to update the
corresponding DPC Status register field.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

app_dpc_err_valid I One-clock-cycle pulse indicating that the data in app_dpc_err_src_id,


app_hdr_log, app_err_bus, app_dpc_impspec_log and
app_tlp_prfx_log is valid for DPC capabilities registers.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: DPC Signals

Port Name I/O Description

app_dpc_err_bus[5:0] I The type of error that your application detected which triggered DPC.
The controller uses app_dpc_err_bus to set the corresponding bits in
the RP PIO Status Register:
■ app_dpc_err_bus[0]: Configuration Request
■ app_dpc_err_bus[1]: I/O Request
■ app_dpc_err_bus[2]: Memory Request
■ app_dpc_err_bus[3]: received UR Completion
■ app_dpc_err_bus[4]: received CA Completion
■ app_dpc_err_bus[5]: Completion Timeout
Used to update DPC RP PIO Status Registe
Exists: (CX_DPC_ENABLE) && (CX_DPC_RP_PIO_EXTNS)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

app_dpc_impspec_log[31:0] I Root Port Programmed I/O Implementation-specific information


associated with the recorded error which triggered Downstream Port
Containment. Used to update DPC RP PIO ImpSpec Log Register.
Exists: (CX_DPC_ENABLE) && (CX_RP_PIO_IMPSPEC)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

core_in_dpc O PCIe Controller core is in Downstream Port Containment mode.


Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

cfg_dpc_int_msg_num[4:0] O DPC Interrupt Message Number. Indicates which MSI/MSI-X vector is


used for the interrupt message generated in association with the DPC
Capability structure.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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SII: DPC Signals PCI Express SW Controller Databook

Port Name I/O Description

cfg_dpc_rp_ext_dpc O RP Extensions for DPC. If Set, this bit indicates that a Root Port
supports a defined set of DPC Extensions that are specific to Root
Ports.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

cfg_dpc_poison_tlp_egr_blk_support O Poisoned TLP Egress Blocking Supported. If Set, this bit indicates that
the Root Port or Switch Downstream Port supports the ability to block
the transmission of a poisoned TLP from its Egress Port.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

cfg_dpc_sw_trig_support O DPC Software Triggering Supported. If Set, this bit indicates that a Root
Port or Switch Downstream Port supports the ability for software to
trigger DPC.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

cfg_dpc_rp_pio_log_size[3:0] O RP PIO Log Size. This field indicates how many DWORDs are allocated
for the RP PIO log registers comprised by the RP PIO Header Log, the
RP PIO ImpSpec Log and RP PIO TLP Prefix Log.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: DPC Signals

Port Name I/O Description

cfg_dpc_dl_active_err_cor_support O DL_Active ERR_COR Signaling Supported. If Set, this bit indicates that
the Root Port or Switch Downstream Port supports the ability to signal
with ERR_COR when the Link transitions to the DL_Active state.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

cfg_dpc_trig_en[1:0] O DPC Trigger Enable.


Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

cfg_dpc_cpl_cntrl O DPC Completion Control.


Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

cfg_dpc_int_en O DPC Interrupt Enable.


Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

cfg_dpc_err_cor_en O DPC ERR_COR Enable


Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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SII: DPC Signals PCI Express SW Controller Databook

Port Name I/O Description

cfg_dpc_poison_tlp_egr_block_en O DPC Poisoned TLP Egress Blocking Enable.


Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

cfg_dpc_sw_trigger O DPC Software Trigger


Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

cfg_dpc_dl_active_err_cor_en O DPC DL_Active ERR_COR Enable


Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

app_flush_ack I Application Flush Acknowledge . When set, application acknowledges


that new requests are stalled and all pending transfers in the pipeline
have completed.
Exists: (!AXI_RADM_SEG_BUF_ENABLE &&
FLUSH_CNTRL_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

rstctl_core_flush_req O Flush request after LTSSM has been directed to DISABLE state.
Exists: (!AXI_RADM_SEG_BUF_ENABLE &&
FLUSH_CNTRL_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: TLP Bypass Internal Error Reporting Signals

5.73 SII: TLP Bypass Internal Error Reporting Signals

- cfg_uncor_internal_err_sts
- cfg_rcvr_overflow_err_sts
- cfg_fc_protocol_err_sts
- cfg_mlf_tlp_err_sts
- cfg_surprise_down_er_sts
- cfg_dl_protocol_err_sts
- cfg_ecrc_err_sts
- cfg_corrected_internal_err_sts
- cfg_replay_number_rollover_err_sts
- cfg_replay_timer_timeout_err_sts
- cfg_bad_dllp_err_sts
- cfg_bad_tlp_err_sts
- cfg_rcvr_err_sts

Table 5-73 SII: TLP Bypass Internal Error Reporting Signals

Port Name I/O Description

cfg_uncor_internal_err_sts O Indication from the controller that the controller has detected an
Uncorrectable Internal Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_rcvr_overflow_err_sts O Indication from the controller that the controller has detected an
Receiver Overflow Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_fc_protocol_err_sts O Indication from the controller that the controller has detected an Flow
Control Protocol Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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SII: TLP Bypass Internal Error Reporting Signals PCI Express SW Controller Databook

Port Name I/O Description

cfg_mlf_tlp_err_sts O Indication from the controller that the controller detected an Malformed
TLP Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_surprise_down_er_sts O Indication from the controller that the controller detected an Surprise
Down Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_dl_protocol_err_sts O Indication from the controller that the controller detected an Data Link
Protocol Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_ecrc_err_sts O Indication from the controller that the controller detected an ECRC
Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_corrected_internal_err_sts O Indication from the controller that the controller detected an Corrected
Internal Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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PCI Express SW Controller Databook SII: TLP Bypass Internal Error Reporting Signals

Port Name I/O Description

cfg_replay_number_rollover_err_sts O Indication from the controller that the controller detected an


REPLAY_NUMBER Rollover Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_replay_timer_timeout_err_sts O Indication from the controller that the controller detected an Replay
Timer Timeout.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_bad_dllp_err_sts O Indication from the controller that the controller detected an Bad DLLP
Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_bad_tlp_err_sts O Indication from the controller that the controller detected an Bad TLP
Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

cfg_rcvr_err_sts O Indication from the controller that the controller detected an Receiver
Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal

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Parameter Descriptions PCI Express SW Controller Databook

6
Parameter Descriptions

This chapter details all the configuration parameters. You can use the coreConsultant GUI configuration
reports to determine the complete configuration state of the controller. Some expressions might refer to
TCL functions or procedures (sometimes identified as <functionof>) that coreConsultant uses to make
calculations. The exact formula used by these TCL functions is not provided in this chapter. However, when
you configure the controller in coreConsultant, all TCL functions and parameters are evaluated completely;
and the resulting values are displayed where appropriate in the coreConsultant GUI reports.
The parameter descriptions in this chapter include the Enabled: attribute which indicates the values
required to be set on other parameters before you can change the value of this parameter.

These tables define all of the configuration options for this component.
■ “Main Features Config Parameters” on page 633
■ “Basic Features Config / PCIe Basic Features Config Parameters” on page 637
■ “Basic Features Config / Common Basic Features Config Parameters” on page 649
■ “DMA Configuration Parameters” on page 657
■ “Basic AXI Config Parameters” on page 659
■ “Basic AXI Config / PCIe TAGs and AXI IDs Parameters” on page 666
■ “Basic AXI Config / PCIe and AHB TAGs Parameters” on page 668
■ “Device-Wide Optional Non-PCIe Config Parameters” on page 669
■ “Advanced AXI Config / Advanced AHB Config Parameters” on page 696
■ “Advanced AXI Config / Advanced AXI Config Parameters” on page 699
■ “Device-Wide PCIe Features and Capabilities Config / MSI/MSI-X Capability Parameters” on page
703
■ “Device-Wide PCIe Features and Capabilities Config / PCIe Capability Parameters” on page 705
■ “Device-Wide PCIe Features and Capabilities Config / PF Extended Capabilities Parameters” on page
714
■ “Device-Wide PCIe Features and Capabilities Config / VC Capability Parameters” on page 718
■ “Device-Wide PCIe Features and Capabilities Config / Slot ID Capability Parameters” on page 719

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PCI Express SW Controller Databook Parameter Descriptions

■ “Device-Wide PCIe Features and Capabilities Config / AtomicOp Support Options Parameters” on
page 720
■ “Device-Wide PCIe Features and Capabilities Config / Readiness Support Options Parameters” on
page 722
■ “Device-Wide PCIe Features and Capabilities Config / Lightweight Notification Support Options
Parameters” on page 725
■ “Device-Wide PCIe Features and Capabilities Config / Other Optional PCIe Features Parameters” on
page 726
■ “Device-Wide PCIe Features and Capabilities Config / SR-IOV Related Features Parameters” on page
728
■ “Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities Parameters” on page
730
■ “Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability Parameters”
on page 738
■ “Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability / L1
Substates Capability Register Defaults Parameters” on page 740
■ “Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support Parameters” on page 741
■ “Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support / PASID Capability
Register Defaults Parameters” on page 742
■ “Device-Wide PCIe Features and Capabilities Config / Precision Time Management Support Options
Parameters” on page 743
■ “Device-Wide PCIe Features and Capabilities Config / Secondary PCIe Extended Capability Param-
eters” on page 744
■ “Device-Wide PCIe Features and Capabilities Config / CCIX Transport DVSEC Parameters” on page
746
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Express Capability
Parameters” on page 749
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / MSI-X Register Config-
uration (PF0) Parameters” on page 750
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Advanced Error
Register Configuration Parameters” on page 752
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / TLP Processing Hints
Register Configuration (PF0) Parameters” on page 753
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ATS Register Config-
uration (PF0) Parameters” on page 754
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ACS Register Config-
uration (PF0) Parameters” on page 755
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Lightweight Notifica-
tion Configuration (PF0) Parameters” on page 758
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Readiness Configura-
tion (PF0) Parameters” on page 759
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Power Management
Register Configuration Parameters” on page 762

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■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Register Configu-
ration Parameters” on page 764
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Register Configu-
ration / PF0 PCI Register Defaults Parameters” on page 767
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / BAR Setup For Phys-
ical Function 0 (PF0) Parameters” on page 769
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / SR-IOV Register
Configuration PF0 Parameters” on page 789
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Virtual Function BARs
for PF0 Parameters” on page 791
■ “Advanced RAM Config Parameters” on page 799
■ “Advanced PHY Config / General Options Parameters” on page 811
■ “Advanced PHY Config / PHY Timing Parameters” on page 814
■ “Advanced PHY Config / Gen3 PHY Equalization Config Parameters” on page 816
■ “Advanced PHY Config / Gen4 PHY Equalization Config Parameters” on page 821
■ “Advanced PHY Config / Gen5 PHY Equalization Config Parameters” on page 825
■ “Advanced PHY Config / PHY Lane Margining Config Parameters” on page 829
■ “Advanced PHY Config / PHY Message Bus Config Parameters” on page 832
■ “Advanced Transmit Config Parameters” on page 833
■ “Advanced Pipeline Config Parameters” on page 839
■ “Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters” on page 847
■ “Advanced Buffer Config / Segmented-Buffer Options Parameters” on page 850
■ “Advanced Buffer Config / Ordering Rules Configuration (Segmented-Buffer) Parameters” on page
851
■ “Advanced Buffer Config / Receive Serialization Queue Parameters” on page 852
■ “Advanced RX Queue Credit and Size Config / Cplq_Mng Calculator Parameters” on page 853
■ “Advanced RX Queue Credit and Size Config / VC 0 Parameters” on page 855
■ “Advanced RX Queue Credit and Size Config / VC 1 Parameters” on page 861
■ “Advanced RAS Config Parameters” on page 868
■ “Memory Map Parameters” on page 870
■ “Automotive Features Selection Parameters” on page 872
■ “CXS Configuration Parameters” on page 873

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PCI Express SW Controller Databook Main Features Config Parameters

6.1 Main Features Config Parameters


Table 6-1 Main Features Config Parameters

Label Description

Core Type

Device Type Select the Device Type of the PCIe controller. You can choose among: EP : Endpoint
port, RC : Root complex port, DM : Dual Mode port (pin-selectable EP/RC port), and
SW : Switch port (pin-selectable upstream/downstream switch port). This selection
must be in line with your current license key.
Values:
■ EP (0)
■ RC (1)
■ DM (2)
■ SW (3)
■ NOT_SET (99)
Default Value: 99 (NOT_SET)
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CC_DEVICE_TYPE

PCIe EP Device Type Select the EP Device Type. You can choose between EP and EP_LEGACY.
Values:
■ PCIE_EP (0x0)
■ PCIE_EP_LEGACY (0x1)
Default Value: PCIE_EP
Enabled: CC_DEVICE_TYPE==CC_EP
Parameter Name: CX_EP_DEVICE_TYPE

PCIe Modes Supported You can configure the controller to support Conventional PCIe or M-PCIe. You can also
configure the controller to support both Conventional PCIe and M-PCIe modes by
choosing the Selectable PHY setting.
Values:
■ Single Conventional PCIe (0)
■ Single M-PCIe (1)
■ Selectable PHY (2)
Default Value: Single Conventional PCIe
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_PCIE_MODE

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Label Description

AXI Bridge

AMBA Enable Use the AXI bridge to interface to your application. For more details, see the
Databook. Additional configuration panes will become visible when you set the
AMBA_INTERFACE configuration parameter.
Values:
■ None (0)
■ Rsvd (1)
■ AXI3 (2)
■ AXI4 (3)
Default Value: None
Enabled: (!(CC_DEVICE_TYPE==CC_SW))
Parameter Type: Feature Setting
Parameter Name: AMBA_INTERFACE

ACE Lite Interface Enables ACE Lite.


Values: 0, 1
Default Value: 0
Enabled: AMBA_INTERFACE==3
Parameter Type: Feature Setting
Parameter Name: CC_ACELITE_ENABLE

Embedded DMA

DMA Enable Enable the embedded DMA controller. For more information, see the 'DMA' chapter of
the Databook. An additional configuration pane will become visible when you set the
CC_DMA_ENABLE configuration parameter.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (!(CC_DEVICE_TYPE==CC_SW))
Parameter Type: Feature Setting
Parameter Name: CC_DMA_ENABLE

Multifunction

Number of Functions Number of (physical) functions to support (in EP mode). There is a complete set of all
of the 'Function/BAR Configuration Parameters' parameters for each of the
CX_NFUNC functions. The additional configuration panes for each additional function
will become visible when you set the CX_NFUNC configuration parameter to a value
greater than 1. CX_ARI_ENABLE must be 1 when you have more than 8 functions.
Values: 1, ..., 32
Default Value: 1
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Feature Setting
Parameter Name: CX_NFUNC

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PCI Express SW Controller Databook Main Features Config Parameters

Label Description

Support ARI Alternate Routing ID (ARI) Capability enable. For more details, see the Databook.
Values:
■ false (0)
■ true (1)
Default Value: CX_SRIOV_ENABLE
Enabled: ((CC_DEVICE_TYPE==CC_EP || CC_DEVICE_TYPE==CC_DM) &&
!CX_SRIOV_ENABLE)
Parameter Type: Feature Setting
Parameter Name: CX_ARI_ENABLE

Individual Bus Number Per Determines if all functions use the same bus number (of function #0) or if they use the
Function individual bus numbers assigned to them by host software. Determines the size of the
cfg_pbus_num and cfg_pbus_dev_num buses: one set of bits for all functions or
separate bit-fields for each configured function. Not applicable when
CX_ARI_ENABLE=1.
■ True: Use individual bus numbers
■ False: Use same bus number
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW &&
CX_ARI_ENABLE!=1 && CX_NW<8
Parameter Type: Feature Setting
Parameter Name: MULTI_DEVICE_AND_BUS_PER_FUNC_EN

CCIX Features

Support CCIX Transport Protocol Configure the controller to support CCIX Transport Protocol.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_CCIX_ENABLE

Support ESM Mode Specifies if the PHY supports ESM (20.0 GT/s and 25 GT/s) Mode.
Values:
■ false (0)
■ true (1)
Default Value: CX_CCIX_ENABLE==1
Enabled: CX_CCIX_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CCIX_ESM_SUPPORT

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Label Description

Support CCIX TLP Interface Specifies if CCIX Interface and optimized TLP is supported.
Values:
■ false (0)
■ true (1)
Default Value: CX_CCIX_ENABLE==1
Enabled: CX_CCIX_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CCIX_INTERFACE_ENABLE

Support CXS Interface Configure the controller to support CXS Interface. The controller does not support
CXS Interface for switch device.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_CCIX_INTERFACE_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_ENABLE

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PCI Express SW Controller Databook Basic Features Config / PCIe Basic Features Config Parameters

6.2 Basic Features Config / PCIe Basic Features Config Parameters


Table 6-2 Basic Features Config / PCIe Basic Features Config Parameters

Label Description

Phy Type

Phy Selection Select the type of PHY you are using. PHYs are instantiated outside the core,
interfacing through the standard PIPE I/F. You must select the "Custom PHY" option
and follow the configuration guidelines presented in the section "Integrating the
controller with the PHY" in the User Guide.
A PHY simulation-only model is also supplied by Synopsys. This block cannot be
implemented and it is provided for simulation purposes only. You might temporarily use
this for simulation purposes until you receive a simulation model from your PHY
vendor. Note that different PHY models may have different configuration requirements.
Please review your configuration settings when switching between the example PHY
and the PHY model provided by your PHY vendor.
Values:
■ Example PIPE PHY (8)
■ Custom PHY (7)
Default Value: Example PIPE PHY
Enabled: (!(CX_PCIE_MODE == SINGLE_MPCIE))
Parameter Type: Feature Setting
Parameter Name: PHY_TYPE

Max PCIe Speed Maximum supported link speed that the controller supports.
Values:
■ Gen1 (2.5GT/s) (1)
■ Gen2 (5.0GT/s) (2)
■ Gen3 (8.0GT/s) (3)
■ Gen4 (16.0GT/s) (4)
■ Gen5 (32.0GT/s) (5)
Default Value: Gen1 (2.5GT/s)
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_MAX_PCIE_SPEED

Core-Phy Combination Read Only parameter to indicate PHY-MAC combination is supported or not
Values:
■ Not Supported (0)
■ Supported (1)
Default Value: function_of (CX_MAX_PCIE_SPEED CX_MAC_SMODE_GEN1
CX_MAC_SMODE_GEN2 CX_MAC_SMODE_GEN3 CX_MAC_SMODE_GEN4
CX_MAC_SMODE_GEN5 CX_PHY_SMODE_GEN1 CX_PHY_SMODE_GEN2
CX_PHY_SMODE_GEN3 CX_PHY_SMODE_GEN4 CX_PHY_SMODE_GEN5)
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_MAC_PHY_FREQ_VALID

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Label Description

Core Gen1 Freq/Width MAC Gen1 Frequency/Width Mode


Values:
■ g1_1s (250Mhz) (1)
■ g1_2s (125Mhz) (2)
■ g1_4s (62.5Mhz) (4)
Default Value: g1_2s (125Mhz)
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_MAC_SMODE_GEN1

Phy Gen1 Freq/Width PHY Gen1 Frequency/Width Mode


Values:
■ g1_1s (250Mhz) (1)
■ g1_2s (125Mhz) (2)
■ g1_4s (62.5Mhz) (4)
■ g1_1s_dp (500Mhz) (102)
■ g1_2s_dp (250Mhz) (202)
Default Value: g1_2s (125Mhz)
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SMODE_GEN1

Core Gen2 Freq/Width MAC Gen2 Frequency/Width Mode


Values:
■ Disabled (0)
■ g2_1s (500Mhz) (1)
■ g2_2s (250Mhz) (2)
■ g2_4s (125Mhz) (4)
Default Value: (CX_MAX_PCIE_SPEED>=2) ? 2 : 0
Enabled: CX_MAX_PCIE_SPEED>=2
Parameter Type: Feature Setting
Parameter Name: CX_MAC_SMODE_GEN2

Phy Gen2 Freq/Width PHY Gen2 Frequency/Width Mode


Values:
■ Disabled (0)
■ g2_1s (500Mhz) (1)
■ g2_2s (250Mhz) (2)
■ g2_4s (125Mhz) (4)
■ g2_2s_dp (500Mhz) (202)
Default Value: (CX_MAX_PCIE_SPEED>=2) ? 2 : 0
Enabled: CX_MAX_PCIE_SPEED>=2
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SMODE_GEN2

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Label Description

Core Gen3 Freq/Width MAC Gen3 Frequency/Width Mode


Values:
■ Disabled (0)
■ g3_1s (1000Mhz) (1)
■ g3_2s (500Mhz) (2)
■ g3_4s (250Mhz) (4)
■ g3_8s (125Mhz) (8)
■ g3_16s (62.5Mhz) (16)
Default Value: (CX_MAX_PCIE_SPEED<3) ? 0 : (CX_MAC_SMODE_GEN1==1) &&
(CX_MAC_SMODE_GEN2==1) ? 1 : (CX_MAC_SMODE_GEN1==2) &&
(CX_MAC_SMODE_GEN2==2) ? 2 : (CX_MAC_SMODE_GEN1==4) &&
(CX_MAC_SMODE_GEN2==4) ? 4 : (CX_MAC_SMODE_GEN1==1) &&
(CX_MAC_SMODE_GEN2==2) ? 4 : (CX_MAC_SMODE_GEN1==2) &&
(CX_MAC_SMODE_GEN2==4) ? 8 : 2
Enabled: CX_MAX_PCIE_SPEED>=3
Parameter Type: Feature Setting
Parameter Name: CX_MAC_SMODE_GEN3

Phy Gen3 Freq/Width PHY Gen3 Frequency/Width Mode


Values:
■ Disabled (0)
■ g3_1s (1000Mhz) (1)
■ g3_2s (500Mhz) (2)
■ g3_4s (250Mhz) (4)
■ g3_8s (125Mhz) (8)
■ g3_16s (62.5Mhz) (16)
Default Value: (CX_MAX_PCIE_SPEED>=3) ? 2 : 0
Enabled: CX_MAX_PCIE_SPEED>=3
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SMODE_GEN3

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Label Description

Core Gen4 Freq/Width MAC Gen4 Frequency/Width Mode


Values:
■ Disabled (0)
■ g4_2s (1000Mhz) (2)
■ g4_4s (500Mhz) (4)
■ g4_8s (250Mhz) (8)
■ g4_16s (125Mhz) (16)
Default Value: (CX_MAX_PCIE_SPEED<4) ? 0 : (CX_MAC_SMODE_GEN1==2) &&
(CX_MAC_SMODE_GEN2==2) ? 2 : (CX_MAC_SMODE_GEN1==4) &&
(CX_MAC_SMODE_GEN2==4) ? 4 : (CX_MAC_SMODE_GEN1==1) &&
(CX_MAC_SMODE_GEN2==2) ? 8 : (CX_MAC_SMODE_GEN1==2) &&
(CX_MAC_SMODE_GEN2==4) ? 16 : 2
Enabled: CX_MAX_PCIE_SPEED>=4
Parameter Type: Feature Setting
Parameter Name: CX_MAC_SMODE_GEN4

Phy Gen4 Freq/Width PHY Gen4 Frequency/Width Mode


Values:
■ Disabled (0)
■ g4_2s (1000Mhz) (2)
■ g4_4s (500Mhz) (4)
■ g4_8s (250Mhz) (8)
■ g4_16s (125Mhz) (16)
Default Value: (CX_MAX_PCIE_SPEED>=4) ? 2 : 0
Enabled: CX_MAX_PCIE_SPEED>=4
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SMODE_GEN4

Core Gen5 Freq/Width MAC Gen5 Frequency/Width Mode


Values:
■ Disabled (0)
■ g5_2s (2000Mhz) (2)
■ g5_4s (1000Mhz) (4)
■ g5_8s (500Mhz) (8)
■ g5_16s (250Mhz) (16)
Default Value: (CX_MAX_PCIE_SPEED<5) ? 0 : (CX_MAC_SMODE_GEN1==2) &&
(CX_MAC_SMODE_GEN2==2) ? 2 : (CX_MAC_SMODE_GEN1==4) &&
(CX_MAC_SMODE_GEN2==4) ? 4 : (CX_MAC_SMODE_GEN1==1) &&
(CX_MAC_SMODE_GEN2==2) ? 8 : (CX_MAC_SMODE_GEN1==2) &&
(CX_MAC_SMODE_GEN2==4) ? 16 : 2
Enabled: CX_MAX_PCIE_SPEED>=5
Parameter Type: Feature Setting
Parameter Name: CX_MAC_SMODE_GEN5

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Label Description

Phy Gen5 Freq/Width PHY Gen5 Frequency/Width Mode


Values:
■ Disabled (0)
■ g5_2s (2000Mhz) (2)
■ g5_4s (1000Mhz) (4)
■ g5_8s (500Mhz) (8)
■ g5_16s (250Mhz) (16)
Default Value: (CX_MAX_PCIE_SPEED>=5) ? 2 : 0
Enabled: CX_MAX_PCIE_SPEED>=5
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SMODE_GEN5

CCIX ESM0 Speed CCIX ESM0 Speed


Values:
■ Disabled (0)
■ 8.0GT/s, 16.0GT/s (1)
Default Value: (CX_CCIX_ESM_SUPPORT) ? 1 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_CCIX_ESM0_SPEED

CCIX ESM1 Speed CCIX ESM1 Speed


Values:
■ Disabled (0)
■ 20.0GT/s, 25.0GT/s (1)
Default Value: (CX_CCIX_ESM_SUPPORT) ? 1 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_CCIX_ESM1_SPEED

Core CCIX ESM0 Freq/Width MAC CCIX ESM0 Frequency/Width Mode


Values:
■ Disabled (0)
■ ccix3_2s (500Mhz/1000Mhz) (2)
■ ccix3_4s (250Mhz/500Mhz) (4)
■ ccix3_8s (125Mhz/250Mhz) (8)
■ ccix3_16s (62.5Mhz/125Mhz) (16)
Default Value: (CX_CCIX_ESM_SUPPORT) ? CX_MAC_SMODE_GEN3 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_MAC_SMODE_ESM0

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Label Description

Phy CCIX ESM0 Freq/Width PHY CCIX ESM0 Frequency/Width Mode


Values:
■ Disabled (0)
■ ccix3_2s (500Mhz/1000Mhz) (2)
■ ccix3_4s (250Mhz/500Mhz) (4)
■ ccix3_8s (125Mhz/250Mhz) (8)
■ ccix3_16s (62.5Mhz/125Mhz) (16)
Default Value: (CX_CCIX_ESM_SUPPORT) ? CX_PHY_SMODE_GEN3 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SMODE_ESM0

Core CCIX ESM1 Freq/Width MAC CCIX ESM1 Frequency/Width Mode


Values:
■ Disabled (0)
■ ccix4_2s (1250Mhz/1562.5Mhz) (2)
■ ccix4_4s (625Mhz/781.25Mhz) (4)
■ ccix4_8s (312.5Mhz/390.625Mhz) (8)
■ ccix4_16s (156.25Mhz/195.3125Mhz) (16)
Default Value: (CX_CCIX_ESM_SUPPORT) ? CX_MAC_SMODE_GEN4 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_MAC_SMODE_ESM1

Phy CCIX ESM1 Freq/Width PHY CCIX ESM1 Frequency/Width Mode


Values:
■ Disabled (0)
■ ccix4_2s (1250Mhz/1562.5Mhz) (2)
■ ccix4_4s (625Mhz/781.25Mhz) (4)
■ ccix4_8s (312.5Mhz/390.625Mhz) (8)
■ ccix4_16s (156.25Mhz/195.3125Mhz) (16)
Default Value: (CX_CCIX_ESM_SUPPORT) ? CX_PHY_SMODE_GEN4 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SMODE_ESM1

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PCI Express SW Controller Databook Basic Features Config / PCIe Basic Features Config Parameters

Label Description

Maximum Link Width Maximum number of lanes that the controller supports. For full details of what
combinations of modes, frequencies and link widths are supported for each core, see
Table 1-1 in the "Frequency, Speed, and Width Support" section in the Product
Overview chapter of the Databook. This parameter becomes a read-only parameter
and takes the same value as the maximum of {CM_TXNL, CM_RXNL} if Single
M-PCIe or Selectable PHY modes are enabled.
Values:
■ x1 (1)
■ x2 (2)
■ x4 (4)
■ x8 (8)
■ x16 (16)
Default Value: (CX_S_CPCIE_MODE) ? 4 : (CM_TXNL_GUI > CM_RXNL_GUI) ?
CM_TXNL_GUI : CM_RXNL_GUI
Enabled: ((CX_PCIE_MODE == SINGLE_CPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_NL

Phy Rx multi-bit startblock Enables PIPE Rx multi-bit startblock Mode for 8s/16s.
When disabled and PIPE width is 8s/16s, the Controller only accepts 64-bit-aligned
SKP-OS in Gen3/4/5 speed.
When enabled and PIPE width is 8s/16s, the Controller can accept 32-bit-aligned
SKP-OS in Gen3/4/5 Speed. Possible SKP-OS length is 32/64/96/128/160/192/224-bit
considering two retimers on the link.
Values:
■ Disabled (0)
■ Enabled (1)
Default Value: (((CX_PHY_FREQ == FREQ_125) && (CX_PHY_GEN2_MODE ==
GEN2_DF) && (CX_PHY_GEN3_MODE == GEN3_DW) && (CX_PHY_GEN4_MODE
== GEN4_DW) && (CX_PHY_INTERFACE == V7_INTERFACE)) ? 1 : 0==1) ? 1 : 0
Enabled: (CX_MAX_PCIE_SPEED>=3 && (CX_PHY_SMODE_GEN3>=8 ||
CX_PHY_SMODE_GEN4>=8 || CX_PHY_SMODE_GEN5>=8))
Parameter Type: Feature Setting
Parameter Name: CX_PIPERX_MULTI_BLOCK

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Label Description

Freq Step (b/w PHY and Core) If this automatically-derived parameter is defined, then a module called freq_step
(workspace/src/common/freq_step.v) is placed in between the PIPE I/O and the core's
internal pip interface. This module steps up/down the signals to/from the pipe
interface. For example, the controller can run at 62.5 MHz (4 symbols per clock) and
the pipe can run at 250 MHz (1 symbol per clock). This read-only parameter is derived
automatically. For more details, see 'Frequency, Speed and Width Support' in the
Product Overview chapter of Databook.
Values:
■ No (0)
■ Yes (1)
Default Value: (CX_MAC_SMODE_GEN1 != CX_PHY_SMODE_GEN1) ||
(CX_MAC_SMODE_GEN2 != CX_PHY_SMODE_GEN2) ||
(CX_MAC_SMODE_GEN3 != CX_PHY_SMODE_GEN3) ||
(CX_MAC_SMODE_GEN4 != CX_PHY_SMODE_GEN4) ||
(CX_MAC_SMODE_GEN5 != CX_PHY_SMODE_GEN5) ||
(CX_PIPERX_MULTI_BLOCK==1)
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_FREQ_STEP_EN

Freq Step (b/w PL and DL) Specifies if the controller supports for frequency step module between the Physical
Layer and the DataLink Layer.
Values:
■ No (0)
■ Yes(1:1) (1)
■ Yes(1:2) (2)
■ Yes(1:4) (4)
Default Value: No
Enabled: SNPS_RSVDPARAM_15
Parameter Name: CX_FREQ_STEP_DL

Datapath Width (PL) Specifies the width of the datapath in dwords. Displayed in bits. This read-only
parameter is derived automatically as CX_NL * CX_NB , rounded up to 1, 2, 4, or 8.
For more details, see the "Frequency, Speed, and Width Support" section in the
Product Overview chapter of the Databook. For the definition of CX_NB, see the
description of "Core PIPE Lane Width" (CX_PIPE_WIDTH_).
Values:
■ 32-bit (1)
■ 64-bit (2)
■ 128-bit (4)
■ 256-bit (8)
■ 512-bit (16)
Default Value: [calc_get_datapath CX_NB CX_NL]
Enabled: Always
Parameter Name: CX_PL_NW

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Label Description

Datapath Width (DL/TL/ADM) Specifies the width of the datapath in dwords. Displayed in bits. This read-only
parameter is derived automatically as CX_NL * CX_DL_NB , rounded up to 1, 2, 4, or
8. For more details, see the "Frequency, Speed, and Width Support" section in the
Product Overview chapter of the Databook. For the definition of CX_NB, see the
description of "Core PIPE Lane Width" (CX_PIPE_WIDTH_).
Values:
■ 32-bit (1)
■ 64-bit (2)
■ 128-bit (4)
■ 256-bit (8)
■ 512-bit (16)
Default Value: [calc_get_datapath CX_DL_NB CX_NL]
Enabled: Always
Parameter Name: CX_NW

PIPE Spec

PIPE Version Options Select PIPE Version.


■ PIPE 4.2
■ PIPE 4.3
❑ Use mac_phy_powerdown signal for L1 substate/L1.CPM transition

❑ Use Synopsys specific Message Bus Interface for Lane Margining

■ PIPE 4.4.1
❑ Use mac_phy_powerdown signal for L1 substate/L1.CPM transition

❑ Use 5-bit LocalPresetIndex encoding for Gen4 data rate

❑ Use Message Bus Interface for Lane Margining for Gen4 data rate

■ PIPE 5.1.1
❑ Use mac_phy_powerdown signal for L1 substate/L1.CPM transition

❑ Use PIPE Low Pin Count Interface

❑ PIPE SerDes Architecture is not supported in this release

❑ PCLK as PHY input is not supported in this release

Contact your PHY vendor for guidelines on PIPE Spec Version. Refer to the User
Guidefor guidelines on how to configure this parameter for Synopsys PHYs.
Values:
■ PIPE4.2 and below (0)
■ PIPE4.3 (1)
■ PIPE4.4.1 (2)
■ PIPE5.1.1 (3)
Default Value: (CX_GEN5_SPEED || CX_CCIX_ESM_SUPPORT) ? 2 :
[<functionof>]
Enabled: CX_S_CPCIE_MODE || CX_SEL_PHY_MODE
Parameter Type: Feature Setting
Parameter Name: CX_PIPE_VER

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Label Description

PCIe Basespec 4.0 Feature

Physical Layer features Enables the following PCIe Base Spec 4.0 features.
■ EIEOS Format change
■ LTSSM change for Retimer
■ Fault isolation
■ SKP OS format change
■ Compliance Pattern Update
■ Physical Layer 16GT/s Capability register
Values: 0, 1
Default Value: CX_GEN4_MODE != GEN4_DISABLED
Enabled: 0
Parameter Name: CX_GEN4_SPEC07

Lane Margining Enable Enable Lane Margining feature


Values: 0, 1
Default Value: CX_GEN4_SPEC07
Enabled: 0
Parameter Name: CX_GEN4_SPEC07_RM

Max number of Retimer Specifies maximum number of Retimers that can be present in your system. This
setting impacts default buffer size of Retry, SOT buffer and Receive queue.
Values: 0x0, 0x1, 0x2
Default Value: ((CX_GEN4_MODE != GEN4_DISABLED)==1) ? 2 : 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_MAX_RETIMER

Total Retimer Latency (Symbol Specifies total round trip Latency of Retimer. The default value is calculated from
times) CX_MAX_RETIMER setting and reference Retimer latency table in PCIe Base Spec.
This setting impacts retry buffer auto-sizing and default credits of Receive queue. If
you know Latency value of Retimer in your system, you should adjust the value.
Otherwise, use the default setting.
Values: 0, ..., 2048
Default Value: [<functionof> CX_MAX_RETIMER CX_SRIS_SUPPORT
CX_MAX_MTU CX_GEN5_SPEED CX_GEN4_SPEED CX_GEN3_SPEED
CX_GEN2_SPEED]
Enabled: Always
Parameter Name: CX_RETIMER_LATENCY

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Label Description

Data Link Feature Enabled The Data Link Feature Capability is an optional Extended Capability that is required for
Downstream Ports that support 16.0 GTs. It is optional in other Downstream Ports. It is
optional in Functions associated with an Upstream Port. It is not applicable in
Functions that are not associated with a Port (e.g. Root Complex Integrated Endpoints,
Root Complex Event Collectors). Ports that implement this protocol contain the Data
Link Feature Extended Capability as described in Section 7.37 of the PCIe
Specification 4.0.
Values:
■ false (0)
■ true (1)
Default Value: CX_GEN4_SPEED || FC_SCALE_EN
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: DL_FEATURE_EN

Scaled Flow Control Enabled Link performance can be affected when there are insufficient flow control credits
available to account for the Link round trip time. This effect becomes more noticeable
at higher Link speeds and the limitation of 127 header credits and 2047 data credits
can limit performance. The Scaled Flow Control mechanism is designed to address
this limitation. Scaled Flow control is described in Section 3.4.2 of the PCIe
Specification 4.0.
Values:
■ false (0)
■ true (1)
Default Value: CX_GEN4_MODE != GEN4_DISABLED
Enabled: (!(CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Feature Setting
Parameter Name: FC_SCALE_EN

10-Bit Tag Configure the controller to support the extended tag range using a 10-bit tag field.
Values: 0, 1
Default Value: (((CX_GEN4_SPEED_VALUE == 1) || (CX_MAX_TAG > 255) ||
(CX_REMOTE_MAX_TAG > 255)) && (AMBA_INTERFACE != 1))? 1: 0
Enabled: AMBA_INTERFACE != 1 && CX_GEN4_SPEED_VALUE == 0
Parameter Type: Feature Setting
Parameter Name: CX_10BITS_TAG

PCIe Basespec 5.0 Feature

Support Equalization bypass to When enabled, the controller supports Equalization bypass to highest rate.
highest rate Values: 0x0, 0x1
Default Value: CX_MAX_PCIE_SPEED >= 5
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Feature Setting
Parameter Name: CX_SKIP_LOWER_RATE_EQ

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Label Description

Support No Equalization Needed When enabled, the controller supports No Equalization Needed. Contact your PHY
vendor for the value that you should use.
Values: 0x0, 0x1
Default Value: 0x0
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Feature Setting
Parameter Name: CX_NO_EQ_NEEDED

Request Transmitter Precode When enabled, the controller will request the remote transmitter to use Precoding by
setting the Precoding Request bit in the EQ TS it transmits prior to entry to
Recovery.Speed.
Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_MAX_PCIE_SPEED >= 5
Enabled: CX_MAX_PCIE_SPEED >= 5
Parameter Type: Register Default Setting
Parameter Name: CX_DEFAULT_TX_PRECODE_REQ

Default Value for Gen5 Loopback Default value for Loopback to do Equalization at Gen5 rate.
EQ Values: 0x0, 0x1
Default Value: CX_MAX_PCIE_SPEED >= 5
Enabled: CX_MAX_PCIE_SPEED >= 5
Parameter Type: Feature Setting
Parameter Name: CX_DEFAULT_GEN5_EQ_FOR_LOOPBACK

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PCI Express SW Controller Databook Basic Features Config / Common Basic Features Config Parameters

6.3 Basic Features Config / Common Basic Features Config Parameters


Table 6-3 Basic Features Config / Common Basic Features Config Parameters

Label Description

PCIe Automotive Support

Automotive safety package Automotive safety package


Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_AUTOMOTIVE_ENABLE

PCIe Max Payload

PCIe Max Payload Supported The largest packet payload (Maximum Transfer Unit) that the device will support.
Specified in bytes and not dwords. This is distinct from the maximum operating
payload (Max_Payload_Size) which may be set by software. This value is used to set
memory sizes and places other restrictions on the size of structures. The device will
support any valid payload size equal to or smaller than the value specified here.
Values: 128, 256, 512, 1024, 2048, 4096
Default Value: 256
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_MAX_MTU

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Label Description

Simultaneous Outstanding Requests

Max Outbound NP Requests Specifies the maximum number of simultaneous outbound PCIe non-posted requests
in total for all functions. The default value is sufficient for typical endpoint applications.
This is used to size:
■ the Receive 'Completion Timeout Look-Up Table'
■ the completion Header Queue RAM when you configure completions in
store-and-forward or cut-through modes
The controller can always accept 8-bit tags (IDs 0 to 255) from the PCIe wire or your
application, regardless of the value of this parameter.
Note:The value range in the GUI is displayed as CX_MAX_TAG+1. The actual
parameter value in the RTL represents the maximum tag number because the tags are
numbered 0 to CX_MAX_TAG
Values:
■ 2 (1)
■ 4 (3)
■ 8 (7)
■ 16 (15)
■ 32 (31)
■ 64 (63)
■ 128 (127)
■ 256 (255)
■ 512 (511)
■ 768 (767)
Default Value: RECOMMENDED_TAGS
Enabled: ((CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Performance Setting
Parameter Name: CX_MAX_TAG

Address Translation

Internal Address Translation Unit Enables the instantiation of the internal address translation unit (iATU). Refer to
'Internal Address Translation (iATU)' section of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_INTERNAL_ATU_ENABLE

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Label Description

Number of Outbound Address Specifies the number of address regions to be mapped by the internal Address
Translation Regions Translation Unit in the outbound direction. Refer to 'Internal Address Translation (iATU)'
section of the Databook.
Values: 0, ..., 256
Default Value: 2
Enabled: CX_INTERNAL_ATU_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ATU_NUM_OUTBOUND_REGIONS

Number of Inbound Address Specifies the number of address regions to be mapped by the internal Address
Translation Regions Translation Unit in the inbound direction. Refer to 'Internal Address Translation (iATU)'
section of the Databook.
Values: 0, ..., 256
Default Value: 2
Enabled: CX_INTERNAL_ATU_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ATU_NUM_INBOUND_REGIONS

Minimum size of an Address Specifies the minimum size of an address translation region. For example, if set to 64
Translation Region kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address
regions are aligned on 64 kB boundaries. Smaller Regions require more levels of
decode logic. Refer to 'Internal Address Translation (iATU)' section of the Databook.
Values:
■ 4k (4096)
■ 8k (8192)
■ 16k (16384)
■ 32k (32768)
■ 64k (65536)
Default Value: 64k
Enabled: CX_INTERNAL_ATU_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ATU_MIN_REGION_SIZE

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Label Description

Maximum size of an Address Specifies the maximum allowable size of an Address Translation Region in iATU for
Translation Region both inbound and outbound TLPs. This parameter determines the number of
programmable bits in the iATU Upper Limit Address Register for both inbound and
outbound. For more information, refer to 'Internal Address Translation (iATU)' section
of the Databook.
Values:
■ 4G (0)
■ 8G (1)
■ 16G (2)
■ 32G (3)
■ 64G (4)
■ 128GB (5)
■ 256GB (6)
■ 512GB (7)
■ 1TB (8)
■ 2TB (9)
■ 4TB (10)
■ 8TB (11)
■ 16TB (12)
■ 32TB (13)
■ 64TB (14)
■ 128TB (15)
■ 256TB (16)
■ 512TB (17)
■ 1PB (18)
■ 2PB (19)
■ 4PB (20)
■ 8PB (21)
■ 16PB (22)
■ 32PB (23)
■ 64PB (24)
■ 128PB (25)
■ 256PB (26)
■ 512PB (27)
■ 1EB (28)
■ 2EB (29)
■ 4EB (30)
■ 8EB (31)
■ 16EB (32)
Default Value: 4G
Enabled: CX_INTERNAL_ATU_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ATU_MAX_REGION_SIZE

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PCI Express SW Controller Databook Basic Features Config / Common Basic Features Config Parameters

Label Description

Receive Queue (VC0)

Receive Posted Queue Mode The queue mode for the posted TLP receive queue for VC0.
(VC0) ■ Bypass: There is no receive queue in this mode, your application must be able to
accept all traffic as back-pressure is disabled in the mode.
■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
■ Cut-through: TLPs are stored into queue and presented to your application at the
same time it is being stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
■ Cut Thru (0x2)
■ Bypass (0x4)
Default Value: Store/Fwd
Enabled: (!(CX_NW>=8 && CX_RADMQ_MODE!=2))
Parameter Type: Feature Setting
Parameter Name: RADM_P_QMODE_VC0

Receive Non-Posted Queue The queue mode for the non-posted TLP receive queue for VC0.
Mode (VC0) ■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
Default Value: CX_RADMQ_MODE==0 ? RADM_P_QMODE_VC0 : 1
Enabled: (CX_RADMQ_MODE!=0 && !(CX_NW>=8 && CX_RADMQ_MODE!=2))
Parameter Type: Feature Setting
Parameter Name: RADM_NP_QMODE_VC0

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Label Description

Receive Completions Queue The queue mode for the completion tlp receive queue for VC0.
Mode (VC0) ■ Bypass: There is no receive queue in this mode, your application must be able to
accept all traffic as back-pressure is disabled in the mode.
■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
■ Cut-through: TLPs are stored into queue and presented to your application at the
same time it is being stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
■ Cut Thru (0x2)
■ Bypass (0x4)
Default Value: (CC_DEVICE_TYPE==CC_SW || CX_NW>=8) ? 1 : 4
Enabled: (!(CX_NW>=8 && CX_RADMQ_MODE!=2))
Parameter Type: Feature Setting
Parameter Name: RADM_CPL_QMODE_VC0

Completion Queue Management Enable the NP throttle that halts the client interface if there is not enough space for the
Feature CPL in the RADM_CPLQ.
Values: 0, 1
Default Value: (CC_DEVICE_TYPE!=CC_SW) && !(CX_P2P_ENABLE) &&
TRGT1_POPULATE && (RADM_CPL_QMODE_VC0<4)
Enabled: ((CC_DEVICE_TYPE!=CC_SW) && TRGT1_POPULATE &&
(RADM_CPL_QMODE_VC0<4))
Parameter Type: Feature Setting
Parameter Name: CX_CPLQ_MANAGEMENT_ENABLE

Technology

FPGA Select this option if you are implementing the controller in an FPGA. This will add the
required pipelining (and corresponding logic to control pipelined logic) to enable the
synthesis tool to meet FPGA timing. For more details, see the 'Synthesizing the Core
for an FPGA' section of the User Guidefor details on FPGA implementation.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: DWC_PCIE_FPGA

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PCI Express SW Controller Databook Basic Features Config / Common Basic Features Config Parameters

Label Description

Use External RAMs Determines if RAMs are instantiated internally, or RAM top-level interface is added for
connection of external RAM modules. External RAM might be preferable if you are
doing RAM layout separately. For more details, see the 'RAM Requirements' section in
the Architecture chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: DWC_PCIE_FPGA ? 0 :1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RAM_AT_TOP_IF

RAM Type Selects the type of RAM when internal RAM is used.
■ Simple: Customer-supplied simple synchronous RAM.
■ DesignWare: Synopsys DesignWare Library Synthesizable flip-flop based SRAM
for sizes up to 256 X 256.
■ FPGA RAM: FPGA RAM resources.
For details on RAM locations and how to integrate the RAM modules, see the 'RAM
Requirements' section in the Architecture chapter of the Databook.
■ Only applicable when CX_RAM_AT_TOP_IF is 0 (Internal)
■ Forced to FPGA RAM when FPGA is 1
Values:
■ Simple (0)
■ DesignWare (1)
■ FPGA RAM (2)
Default Value: DWC_PCIE_FPGA ? 2 : 0
Enabled: !DWC_PCIE_FPGA && !CX_RAM_AT_TOP_IF
Parameter Type: Feature Setting
Parameter Name: CX_RAM_TYPE

Individual Pipeline Control Enable independent control of inter-module pipelines to trade-off latency and gates for
ease of timing closure. Additional configuration panes will become visible when you
set this parameter.
Values:
■ Disable (0)
■ Enable (1)
Default Value: Disable
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_CUSTOM_PIPELINING

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Label Description

Technology Speed The speed of the target technology relative to the clock frequency and architecture.
Possible values are SLOW or FAST. When you have selected "Individual Pipeline
Control" (CX_CUSTOM_PIPELINING set to "1"), then this parameter sets the default
for many of the individual inter-module pipeline enabling parameters to "1" when
CX_TECHNOLOGY is SLOW. This parameter is forced to SLOW when you are using
an FPGA (DWC_PCIE_FPGA parameter set to "1"). An ASIC technology might be
FAST if running at 125 MHz, but the SLOW setting might be needed to meet timing at
250 MHz in an x8/x16 architecture.
Values:
■ SLOW (0x0)
■ FAST (0x2)
Default Value: DWC_PCIE_FPGA ? 0 : 2
Enabled: !DWC_PCIE_FPGA || (CX_CUSTOM_PIPELINING==0)
Parameter Type: Performance Setting
Parameter Name: CX_TECHNOLOGY

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PCI Express SW Controller Databook DMA Configuration Parameters

6.4 DMA Configuration Parameters


Table 6-4 DMA Configuration Parameters

Label Description

Basic Features

Number of DMA Write Channels Number of write channels implemented in the DMA logic. A DMA write copies data
from your local application to the remote link partner. For more information, see the
'DMA' chapter of the Databook.
Values: 1, 2, 3, 4, 5, 6, 7, 8
Default Value: 2
Enabled: CC_DMA_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_NUM_DMA_WR_CHAN

Number of DMA Read Channels Number of read channels implemented in the DMA logic. A DMA read copies data
from the remote link partner to your local application. For more information, see the
'DMA' chapter of the Databook.
Values: 1, 2, 3, 4, 5, 6, 7, 8
Default Value: 2
Enabled: CC_DMA_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_NUM_DMA_RD_CHAN

Advanced Features

Number of DMA Read PCIe Tags Specifies how many of the CX_MAX_TAG+1 PCIe tags are reserved for DMA MRd
generation.
■ CC_NUM_DMA_RD_TAG of the CX_MAX_TAG+1 tags are reserved for use by
the DMA controller (and are no longer available to your application) for generation
of non-posted DMA traffic. These are in the number range CX_MAX_TAG +1
-CC_NUM_DMA_RD_TAG to CX_MAX_TAG.
■ The remaining CX_MAX_TAG +1 - CC_NUM_DMA_RD_TAG tags are assigned to
non-DMA transfers. These are in the number range 0 to CX_MAX_TAG
-CC_NUM_DMA_RD_TAG.
This parameter is also used to size the DMA Read buffer. The minimum value for
CX_MAX_TAG is "3" when DMA is enabled.
Values: 2, 4, 8, 16, 32, 64, 128
Default Value: (CX_MAX_TAG==3) ? 2 : (CX_MAX_TAG==7) ? 4 :
(CX_MAX_TAG==15) ? 8 : (CX_MAX_TAG==31) ? 16 : (CX_MAX_TAG==63) ? 32 :
(CX_MAX_TAG==127) ? 64 : (CX_MAX_TAG>=255) ? 128 : 2
Enabled: CC_DMA_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_NUM_DMA_RD_TAG

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Label Description

DMA Handshake Enable Enable DMA Handshake feature. The Handshake feature is available for each DMA
Write/Read channel. For more information, see the 'DMA' chapter of the Databook
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DMA_ENABLE
Parameter Name: CC_DMA_HSHAKE

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PCI Express SW Controller Databook Basic AXI Config Parameters

6.5 Basic AXI Config Parameters


Table 6-5 Basic AXI Config Parameters

Label Description

AXI General and Data/Address

Support Slave Wrap Bursts Enable support of wrapping bursts at the AXI bridge slave. For more details, see the
"Supported AXI Burst Operations" section in the "AXI Bridge Module" chapter of the
Databook.
Values: 0, 1
Default Value: 0
Enabled: AMBA_INTERFACE>=2
Parameter Type: Feature Setting
Parameter Name: CC_SLV_WRAP_ENABLE

Max Number of Outstanding AXI Specifies the maximum number of outstanding AXI Slave NP Write Requests.
Slave NP Write Requests To enable P writes to pass NP writes (and avoid deadlocks by allowing peer-to-peer
posted traffic to flow freely through the RC); the controller uses a "Slave Non-Posted
Write Set-Aside Buffer" to offload the NP writes from the AXI Write Channel when NP
reads are stalled. Offloading NP writes thereby avoids blocking of P on the AXI Write
Channel. You configure the maximum number of offloaded NP writes using this
parameter.
Values: 2, 4, 8, 16, 32, 64
Default Value: 32
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Feature Setting
Parameter Name: CC_SLV_NUM_OUTSTND_CPU_WR_REQ

Master Address Width Specifies the width of the AXI master address bus (excluding parity bits [AXI only] if
any)
Values:
■ 32 (32)
■ 64 (64)
Default Value: CC_DTIM_ENABLE ? 64 : (AHB_POPULATED ?
SLAVE_BUS_ADDR_WIDTH : 32)
Enabled: (MASTER_POPULATED && (AXI_POPULATED || AHB_POPULATED))
Parameter Type: Feature Setting
Parameter Name: MASTER_BUS_ADDR_WIDTH

Master Data Width Specifies the width of the AXI master databus (excluding parity bits [AXI only] if any)
Values: 32, 64, 128, 256, 512
Default Value: AHB_POPULATED ? SLAVE_BUS_DATA_WIDTH :
PCIE_CORE_DATA_BUS_WD
Enabled: MASTER_POPULATED
Parameter Type: Feature Setting
Parameter Name: MASTER_BUS_DATA_WIDTH

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Label Description

Slave Address Width Specifies the width of the AXI slave address bus (excluding parity bits [AXI only] if any)
Values:
■ 32 (32)
■ 64 (64)
Default Value: CC_DTIM_ENABLE ? 64 : 32
Enabled: (SLAVE_POPULATED && (AXI_POPULATED || AHB_POPULATED))
Parameter Type: Feature Setting
Parameter Name: SLAVE_BUS_ADDR_WIDTH

Slave Data Width Specifies the width of the AXI slave data bus (excluding parity bits [AXI only] if any).
Values: 32, 64, 128, 256, 512
Default Value: CX_NW * 32
Enabled: SLAVE_POPULATED
Parameter Type: Feature Setting
Parameter Name: SLAVE_BUS_DATA_WIDTH

Integrated MSI Reception Module Instantiate the iMSI-RX: Integrated MSI Receiver in the AXI bridge to detect and
Enable terminate inbound MSI TLPs. For more details, see the Interrupt section in the
"Controller Operations" chapter of the Databook.
Values: 0, 1
Default Value: 0
Enabled: ((CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_DM) &&
AMBA_INTERFACE!=0)
Parameter Type: Feature Setting
Parameter Name: CX_MSI_CTRL_ENABLE

AXI MSI Controller FIFO Depth AXI MSI interrupt controller FIFO depth. Number of maximum interrupt vectors AXI
MSI controller can hold before halting the target interface.
Values: 2, 3, 4, 5
Default Value: 2
Enabled: ((CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_DM) &&
CX_MSI_CTRL_EN)
Parameter Type: Feature Setting
Parameter Name: CX_MSI_CTRL_FIFO_DEPTH

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Label Description

AXI Clocking

Asynchronous AHB Clock Include asynchronous clock crossing circuitry in AHB bridge. The AHB bridge
assumes that hclk is asynchronous to core_clk and it implements the appropriate clock
crossings using pre-existing FIFOs and inserting extra FIFOs when necessary.
■ When your AHB clock is synchronous to core_clk then you can eliminate all unnec-
essary clock crossing circuitry by unsetting this parameter.
■ When you are using a dynamic frequency controller (Gen/Gear 2/3), the frequency
of core_clk changes across speed modes. In this case, your AHB clock cannot be
synchronous to core_clk and you cannot set AHB_CLK_DIFF_ENABLE to "0".
■ In addition, M-PCIe mode doesn't support synchronous core_clk and bridge clock
frequencies because the M-PCIe core_clk frequency regularly changes between
rate A and B frequencies.
Values: 0, 1
Default Value: AMBA_INTERFACE==1
Enabled: AMBA_INTERFACE==1
Parameter Type: Feature Setting
Parameter Name: AHB_CLK_DIFF_ENABLE

Asynchronous AXI Slave Clock Include slave asynchronous clock crossing circuitry in AXI bridge. The AXI bridge
assumes that slv_aclk and dbislv_aclk are asynchronous to core_clk and it
implements the appropriate clock crossings using pre-existing FIFOs and inserting
extra FIFOs when necessary.
■ When your AXI clocks are synchronous to core_clk then you can eliminate all
unnecessary clock crossing circuitry by unsetting the SLV_CLK_DIFF_ENABLE
configuration parameter.
■ When you are using a dynamic frequency Gen/Gear 2/3 core, the frequency of
core_clk changes across speed modes. In this case, your AXI clock cannot be
synchronous to core_clk and you cannot set SLV_CLK_DIFF_ENABLE to "0".
■ In addition, M-PCIe mode doesn't support synchronous core_clk and bridge clock
frequencies because the M-PCIe core_clk frequency regularly changes between
rate A and B frequencies.
Values: 0, 1
Default Value: (AXI_POPULATED && SLAVE_POPULATED) ||
AHB_CLK_DIFF_ENABLE
Enabled: AXI_POPULATED && SLAVE_POPULATED
Parameter Type: Feature Setting
Parameter Name: SLV_CLK_DIFF_ENABLE

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Label Description

Asynchronous AXI Master Clock Include master asynchronous clock crossing circuitry in AXI bridge. The AXI bridge
assumes that mstr_aclk is asynchronous to core_clk and it implements the appropriate
clock crossings using pre-existing FIFOs and inserting extra FIFOs when necessary.
■ When your AXI clock is synchronous to core_clk then you can eliminate all unnec-
essary clock crossing circuitry by unsetting the MSTR_CLK_DIFF_ENABLE config-
uration parameter.
■ When you are using a dynamic frequency Gen/Gear 2/3 core, the frequency of
core_clk changes across speed modes. In this case, your AXI clock cannot be
synchronous to core_clk and you cannot set MSTR_CLK_DIFF_ENABLE to "0".
■ In addition, M-PCIe mode doesn't support synchronous core_clk and bridge clock
frequencies because the M-PCIe core_clk frequency regularly changes between
rate A and B frequencies.
Values: 0, 1
Default Value: (AXI_POPULATED && MASTER_POPULATED) ||
AHB_CLK_DIFF_ENABLE
Enabled: AXI_POPULATED && MASTER_POPULATED
Parameter Type: Feature Setting
Parameter Name: MSTR_CLK_DIFF_ENABLE

AXI Slave Max Payload

Slave Interface Burst Length Specifies the maximum burst length (in beats) of an AXI transfer at the slave interface.
An application master may execute any burst up to a maximum byte size given by
CC_SLV_BURST_LEN * (CC_SLV_BUS_DATA_WIDTH / 8) bytes. This parameter
controls the default size of the slave request decomposer Data RAM inside the AXI
bridge based on the maximum MemWr transfer size. This parameter uses the unit of
burst beat.
Values: 8, 16, 32, 64, 128, 256
Default Value: (AHB_POPULATED && (SLAVE_BUS_DATA_WIDTH==32))? 32 : 16
Enabled: SLAVE_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_SLV_BURST_LEN

AHB/AXI Slave MTU Slave Maximum Transfer Unit. The application master (at the AXI Slave Interface) must
not request or write more than CC_SLV_MTU bytes in a single AXI burst. This value is
used to set memory sizes in the bridge (slave request decomposer data FIFO and
slave response composer). This parameter is derived automatically as
CC_SLV_BURST_LEN * (SLAVE_BUS_DATA_WIDTH / 8) and is read-only.
Values: -2147483648, ..., 2147483647
Default Value: ((CC_SLV_BURST_LEN*SLAVE_BUS_DATA_WIDTH/8) > 4096) ?
4096 : (CC_SLV_BURST_LEN*SLAVE_BUS_DATA_WIDTH/8)
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CC_SLV_MTU

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Label Description

AXI Master Max Payload

Master Interface Burst Length Specifies the maximum burst length (in beats) of an AXI transfer at the master
interface.
■ A value < MASTER_BUS_DATA_WIDTH/8 forces MSTR_FIXED_SIZE_EN-
ABLE=1 because the master cannot produce a sufficiently long burst of bytes.
Therefore the master uses dword access and not byte access for narrow or NCBE
reads; which means that such accesses to non-prefetchable memory might result
in corrupting not-to-be-read data.
■ A value of 8 also forces MSTR_FIXED_SIZE_ENABLE=1.
AXI Note:The value of 8 is only possible if MASTER_BUS_DATA_WIDTH > 32
because the minimum allowable master burst transfer size (CC_MSTR_MTU) is 64
bytes.
Values: 8, 16, 32, 64, 128, 256
Default Value: 16
Enabled: (MASTER_POPULATED && !(AHB_POPULATED &&
(CC_MSTR_BURST_TYPE == 0)))
Parameter Type: Performance Setting
Parameter Name: CC_MSTR_BURST_LEN

AHB/AXI Master MTU Master Maximum Transfer Unit. The bridge master will not request or write more than
CC_MSTR_MTU bytes in a single AXI burst. This parameter is derived automatically
as max. {64, CC_MSTR_BURST_LEN * (MASTER_BUS_DATA_WIDTH / 8) } and is
read-only.
Values: 64, ..., 4096
Default Value: ((CC_MSTR_BURST_LEN*MASTER_BUS_DATA_WIDTH/8) >= 64) ?
(CC_MSTR_BURST_LEN*MASTER_BUS_DATA_WIDTH/8) : 64
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CC_MSTR_MTU

Master Page Boundary Bit Specifies an address page boundary of 128, 256, 512, 1K, 2K or 4K (bytes).
■ The AXI bridge ensures that the inbound request will not cross the selected page
boundary when driven onto the AXI master interface.
■ The Master Page Boundary (CC_MSTR_PAGE_BOUNDARY_BYTES) is calcu-
lated as 2 ^ (CC_MSTR_PAGE_BOUNDARY_PW-1).
■ For more details, see "Decomposition" in the Databook.
Note:The Master Page Boundary { 2 ^ (CC_MSTR_PAGE_BOUNDARY_PW-1) } must
be >= max{ CC_MSTR_MTU , CC_MSTR_RD_REQ_SIZE}
Values: 8, ..., 13
Default Value: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3)) ? 13 : 11
Enabled: MASTER_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_MSTR_PAGE_BOUNDARY_PW

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Label Description

Master Page Boundary For more details, see description of Master Page Boundary Bit
(CC_MSTR_PAGE_BOUNDARY_PW).
Note:This parameter is derived automatically as 2 ^
(CC_MSTR_PAGE_BOUNDARY_PW-1) and is read-only.
Values: -2147483648, ..., 2147483647
Default Value: [calc_inv_log2 [<functionof> CC_MSTR_PAGE_BOUNDARY_PW -1]]
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CC_MSTR_PAGE_BOUNDARY_BYTES

PCIe Max Payload

PCIe Max Payload Supported This parameter is a read-only reflection of the CX_MAX_MTU parameter.
Values: 0, ..., 65535
Default Value: CX_MAX_MTU
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_MAX_MTU_

AXI DBI

Dedicated DBI Slave Enable Enables the AXI Slave DBI interface. For more details, see the "Local Bus Controller
(LBC)" section of the Databook.
Values: 0, 1
Default Value: AMBA_POPULATED && !SHARED_DBI_ENABLED
Enabled: AMBA_POPULATED && !SHARED_DBI_ENABLED
Parameter Type: Feature Setting
Parameter Name: DBI_4SLAVE_POPULATED

Shared DBI Slave Enable Indicates that the slave interface for PCIe outbound traffic is also used for DBI access.
For more details, see the "Local Bus Controller (LBC)" section in the "Controller
Operations" chapter of the Databook. >Note:Valid for AXI only but cannot be enabled
in EP/DM when (CX_ARI_ENABLE=1 or CX_SRIOV_ENABLE=1)
Values: 0, 1
Default Value: 0
Enabled: (AXI_POPULATED && (!CX_AMBA_ARI_OR_IOV ||
SLAVE_BUS_ADDR_WIDTH_IS_64))
Parameter Type: Feature Setting
Parameter Name: SHARED_DBI_ENABLED

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Label Description

DBI Slave Address Width Specifies the width of the dedicated DBI slave address bus. This is a read-only
parameter.
Values:
■ 32 (32)
■ 33 (33)
Default Value: CX_ARI_ENABLE ? 33 : 32
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CC_DBI_SLV_BUS_ADDR_WIDTH

DBI Slave Data Width Specifies the width of the dedicated DBI slave databus.
Values: 32, 64, 128
Default Value: 32
Enabled: ((AMBA_INTERFACE==1))
Parameter Type: Feature Setting
Parameter Name: CC_DBI_SLV_BUS_DATA_WIDTH

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Basic AXI Config / PCIe TAGs and AXI IDs Parameters PCI Express SW Controller Databook

6.6 Basic AXI Config / PCIe TAGs and AXI IDs Parameters
Table 6-6 Basic AXI Config / PCIe TAGs and AXI IDs Parameters

Label Description

Slave

Max Outbound NP Requests This parameter is a read-only reflection of the CX_MAX_TAG parameter.
Values:
■ 2 (1)
■ 4 (3)
■ 8 (7)
■ 16 (15)
■ 32 (31)
■ 64 (63)
■ 128 (127)
■ 256 (255)
■ 512 (511)
■ 768 (767)
Default Value: CX_MAX_TAG
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_MAX_TAG_

AHB/AXI Slave Tags The maximum number of non-posted AXI requests issued to the bridge slave that are
outstanding at one time over the PCIe link. For more details, see "Outbound Bridge
Tag Management" in the "AXI Bridge Module" chapter of the Databook.
■ For AXI, the default value is CX_MAX_TAG+1. Note that CX_MAX_TAG
represents the number of PCIe TAGs minus 1.
■ When DMA is enabled, the default value for AXI is (CX_MAX_TAG +1)/2.
AHB Note:This parameter is derived automatically and is read-only.
Values: 2, 4, 8, 16, 32, 64, 128, 256
Default Value: ((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=2)) ? 2 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=4)) ? 4 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=8)) ? 8 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=16)) ? 16 :
(CC_DMA_ENABLE_VALUE==1) ? ((CX_MAX_TAG==3) ? 2 : (CX_MAX_TAG==7) ?
4 : (CX_MAX_TAG==15) ? 8 : (CX_MAX_TAG==31) ? 16 : (CX_MAX_TAG==63) ? 32
: (CX_MAX_TAG==127) ? 64 : (CX_MAX_TAG>=255) ? 128 : 2) :
((CX_MAX_TAG<=255) ? CX_MAX_TAG + 1 : 256)
Enabled: SLAVE_POPULATED && (AHB_ENABLED==0)
Parameter Type: Performance Setting
Parameter Name: CC_MAX_SLV_TAG

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Label Description

High Priority Master

AXI High Priority Master IDs Represents the maximum number of AXI master IDs and the maximum number of
outstanding NP transactions the AXI High Priority master can handle. This value must
be smaller than CC_MAX_MSTR_TAGS_AXI. The Low Priority master will handle
(CC_MAX_MSTR_TAGS_AXI-CC_MAX_MSTRH_TAGS_AXI). NOTE: This parameter
is only visible when High Priority Master is enabled.
Values: 1, ..., (CC_MAX_MSTR_TAGS_AXI-1)
Default Value: CC_MAX_MSTR_TAGS_AXI/2
Enabled: CC_HP_MASTER
Parameter Type: Performance Setting
Parameter Name: CC_MAX_MSTRH_TAGS_AXI

Master

AXI Master IDs Represents the maximum number of AXI master IDs and the maximum number of
outstanding NP transactions the AXI bridge can handle. It is used to size the master
completion RAM which can be large if CC_MAX_MSTR_TAGS_AXI is large. You
should set CC_MAX_MSTR_TAGS_AXI to the minimum number of outstanding AXI
requests that are required to saturate the AXI bus and/or supply the throughput
required by the core. If decomposition occurs, the number of simultaneously
outstanding AXI requests is larger than this value. For more details, see the 'Inbound
Bridge Tag Management' section in the AXI Bridge chapter of the Databook. This
parameter is used to size the master ID busses with the value
log2{CC_MAX_MSTR_TAGS_AXI}.
Values: 2, 4, 8, 16, 32, 64, 128, 256
Default Value: 32
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Performance Setting
Parameter Name: CC_MAX_MSTR_TAGS_AXI

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Basic AXI Config / PCIe and AHB TAGs Parameters PCI Express SW Controller Databook

6.7 Basic AXI Config / PCIe and AHB TAGs Parameters


Table 6-7 Basic AXI Config / PCIe and AHB TAGs Parameters

Label Description

Slave

Max Outbound NP Requests This parameter is a read-only reflection of the CX_MAX_TAG parameter.
Values:
■ 2 (1)
■ 4 (3)
■ 8 (7)
■ 16 (15)
■ 32 (31)
■ 64 (63)
■ 128 (127)
■ 256 (255)
■ 512 (511)
■ 768 (767)
Default Value: CX_MAX_TAG
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_MAX_TAG_

AHB/AXI Slave Tags The maximum number of non-posted AXI requests issued to the bridge slave that are
outstanding at one time over the PCIe link. For more details, see "Outbound Bridge
Tag Management" in the "AXI Bridge Module" chapter of the Databook.
■ For AXI, the default value is CX_MAX_TAG+1. Note that CX_MAX_TAG
represents the number of PCIe TAGs minus 1.
■ When DMA is enabled, the default value for AXI is (CX_MAX_TAG +1)/2.
AHB Note:This parameter is derived automatically and is read-only.
Values: 2, 4, 8, 16, 32, 64, 128, 256
Default Value: ((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=2)) ? 2 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=4)) ? 4 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=8)) ? 8 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=16)) ? 16 :
(CC_DMA_ENABLE_VALUE==1) ? ((CX_MAX_TAG==3) ? 2 : (CX_MAX_TAG==7) ?
4 : (CX_MAX_TAG==15) ? 8 : (CX_MAX_TAG==31) ? 16 : (CX_MAX_TAG==63) ? 32
: (CX_MAX_TAG==127) ? 64 : (CX_MAX_TAG>=255) ? 128 : 2) :
((CX_MAX_TAG<=255) ? CX_MAX_TAG + 1 : 256)
Enabled: SLAVE_POPULATED && (AHB_ENABLED==0)
Parameter Type: Performance Setting
Parameter Name: CC_MAX_SLV_TAG

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PCI Express SW Controller Databook Device-Wide Optional Non-PCIe Config Parameters

6.8 Device-Wide Optional Non-PCIe Config Parameters


Table 6-8 Device-Wide Optional Non-PCIe Config Parameters

Label Description

Application Interface Options

Target Completion LUT Enable Enable the Target Completion Lookup Table to be connected internally between the
RTRGT1 and XALI0/1/2 interfaces. This feature provides two functions:
■ The application does not need to provide certain TLP header information when
transmitting completions on XALI0/1/2 because the controller stores and tracks the
information in the internal Target Completion Lookup Table.
■ When the application has not generated a completion for an incoming request
within the required time interval, then the Target Completion Timeout indicates that
a Timeout has occurred.
The Target Completion Lookup Table (and Target Completion Timeout event) should
not be confused with the Completion Lookup table (and Completion Timeout event)
described in 'Received Completion TLP Processing' in the Databook. For more details,
see the 'Target Completion Lookup Table' section of the "Signal Interfaces" chapter of
the Databook. The size of the this LUT is controlled using the 'Max Forwarded NP
Requests' (CX_REMOTE_MAX_TAG) parameter.Note:This feature is not available if
Peer-to-Peer support is enabled.Note:When the AXI bridge is used
(AMBA_INTERFACE=1, 2 or 3) or when DMA is enabled, the Target Completion
Lookup Table is automatically activated.
Values:
■ false (0)
■ true (1)
Default Value: (CC_DMA_ENABLE) ? 1 : (AMBA_POPULATED) ? 1 : 0
Enabled: ((TRGT1_POPULATE==1 && !(CC_DMA_ENABLE) &&
CC_DEVICE_TYPE!=CC_SW && CX_P2P_ENABLE==0 &&
AMBA_POPULATED==0))
Parameter Type: Feature Setting
Parameter Name: TRGT_CPL_LUT_EN

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Label Description

Max Forwarded NP Requests The function depends on the nature of the application interface.
■ AXI:You should leave this parameter at its default value.
■ Native core:Specifies the maximum number of received non-posted requests that
the controller will forward to your application at one time, when the Target Comple-
tion LUT (TRGT_CPL_LUT_EN) is enabled. The default value is sufficient for
typical applications. It does not control the number of non-posted requests that the
controller can receive and buffer from the PCIe wire, which is controlled by flow
control credits.
Values:
■ 2_Tags (1)
■ 4_Tags (3)
■ 8_Tags (7)
■ 16_Tags (15)
■ 32_Tags (31)
■ 64_Tags (63)
■ 128_Tags (127)
■ 256_Tags (255)
■ 512_Tags (511)
■ 1024_Tags (1023)
Default Value: CC_HP_MASTER ? CC_MAX_MSTR_TAGS_AXI-1
:AHB_POPULATED ? 1 : (AXI_POPULATED ? CC_MAX_MSTR_TAGS - 1 :
((CX_MAX_TAG == 767) ? 1023 : CX_MAX_TAG))
Enabled: ((AMBA_POPULATED) ? 0 : (TRGT_CPL_LUT_EN))
Parameter Type: Performance Setting
Parameter Name: CX_REMOTE_MAX_TAG

Enable Address Alignment When enabled (and input client*_addr_align_en input is asserted), the controller
supports address alignment and generates the first and last byte enables (FBE, LBE)
based on the address and number of bytes of the TLP requested from the client
interface. When CX_ECRC_EN is not set, GLOB_ADDR_ALIGN_EN should normally
be disabled. However, if your application requires this to be enabled, then the address
alignment pin (client0/1/2_addr_align_en) should only be high for those TLPs without
ECRC. For TLPs with ECRC that are being transmitted by the Application, the address
alignment pin (client0/1/2_addr_align_en) should be de-asserted for that TLP. For
more information, see 'Transmit Address Alignment' section in the "Signal
Descriptions" chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: !AMBA_POPULATED && CX_P2P_ENABLE==0
Parameter Type: Feature Setting
Parameter Name: GLOB_ADDR_ALIGN_EN

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PCI Express SW Controller Databook Device-Wide Optional Non-PCIe Config Parameters

Label Description

Byte Count Storage Determines whether or not to store the byte count in the receive completion LUT. If the
controller does not a receive a completion for each request, then the completion
timeout mechanism will terminate the request. It will also indicate on the
radm_timeout_cpl_len[11:0] output port, the number of bytes remaining to be
delivered when the completion timed out. When the byte count is not stored in the LUT,
the controller is unable to detect when it is receiving a completion with an incorrect
byte count field. Therefore completions with incorrect byte count will be treated as valid
completions instead of being treated as unexpected completions. The controller will
not detect missing completions and the receive completion LUT will not timeout.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_CPL_LUT_STORE_BYTE_CNT

Application Return CRD Enable Include optional top-level ports for the application to update the Flow Control credits
counters. The optional ports are the app_*_ca ports on the SII (see 'System
Information Interface (SII)' section of the "Signal Descriptions" chapter Databookfor
more details).
Note:The application is not expected to return completion credits since completion
credits are infinite according to the PCI Express 3.1 Specification.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: APP_RETURN_CRD_EN

Lane/Link Options

Enable Manual Lane Flip Include support for manual lane flip. For more information, see the 'Lane Reversal'
(Conventional PCIe) chapter in the Databook. Include the tx_lane_flip_en and rx_lane_flip_en inputs to
manually control TX/RX Lane Reversal. M-PCIe doesn't support this feature.
Values:
■ false (0)
■ true (1)
Default Value: ((CX_LANE_REVERSE || CX_GEN5_SPEED) && CX_NL > 1) ? 1 : 0
Enabled: (!(CX_PCIE_MODE == SINGLE_MPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_LANE_FLIP_CTRL_EN

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Label Description

Enable Auto Lane Flip and Include support for auto lane flip and reversal. When you set this parameter, the
Reversal controller implements logic to:
■ flip the lanes autonomously in Detect LTSSM state when lane0 is not detected, and
■ reverse the lanes autonomously in Configuration LTSSM state when logical lane0
receives TS ordered sets with lane number different from '0'.
For more information, see the description of the AUTO_LANE_FLIP_CTRL_EN
register in the Register Descriptionsdocument and 'Lane Reversal' chapter in the
Databook.
Values:
■ false (0)
■ true (1)
Default Value: (CX_LANE_FLIP_CTRL_EN) ? 1 : 0
Enabled: CX_LANE_FLIP_CTRL_EN
Parameter Type: Feature Setting
Parameter Name: CX_AUTO_LANE_FLIP_CTRL_EN

Enable Partial Auto Lane Flip and Enables support for partial auto flipping or reversal of the lanes.
Reversal ■ Full flip or reversal: Lane0 is connected to Lane NL-1.
■ Partial flip or reversal: Lane0 is connected to either Lane NL/2-1 or Lane NL/4-1 or
Lane NL/8-1 etc.
For more information, see the 'Lane Reversal' chapter in the Databook.
Values:
■ Full (0)
■ Full or Partial (1)
■ Full and Partial (2)
Default Value: (CX_LANE_REVERSE) ? 2 : 1
Enabled: CX_AUTO_LANE_FLIP_CTRL_EN
Parameter Type: Feature Setting
Parameter Name: CX_AUTO_LANE_FLIP_MUX_ARCH

Enable Forced Lane Flip When this parameter is set to true, and FORCE_LANE_FLIP field of
GEN2_CTRL_OFF register is set to 1, you can forcefully connect the physical lane
specified in LANE_UNDER_TEST field of GEN2_CTRL_OFF register to logical Lane0
of the controller after reset. Only the physical lane specified in LANE_UNDER_TEST
can be flipped to logical Lane0, starting from Detect LTSSM state. That is, only x1 can
be formed, all the other physical lanes are turned off.
Values:
■ false (0)
■ true (1)
Default Value: CX_LANE_FLIP_CTRL_EN
Enabled: CX_LANE_FLIP_CTRL_EN
Parameter Type: Feature Setting
Parameter Name: CX_FORCE_LANE_FLIP_EN

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PCI Express SW Controller Databook Device-Wide Optional Non-PCIe Config Parameters

Label Description

Default Link Number Default Link Number value that the Upstream Device advertises to the Downstream
Link partner over the TS sequence. It is also the default value for the Link Number field
in the 'Port Force Link Register'. This register is used to force the link to the state
specified by the Link State field through a link re-negotiation. For more details, see the
Registers chapter of the Databook. M-PCIe doesn't have this feature. M-PCIe doesn't
support this feature.
Values: 0x0, ..., 0xff
Default Value: 0x4
Enabled: CX_CPCIE_ENABLE && CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_LINK_NUM

Upconfigure Support Default value for the UPCONFIGURE_SUPPORT field in the


MULTI_LANE_CONTROL_OFF register. You must set the
UPCONFIGURE_SUPPORT field in MULTI_LANE_CONTROL_OFF so that the
controller advertises '1' in the Upconfigure Capability bit of the TS2 OS. This allows
you to upsize or downsize the link width through Configuration state without bringing
the link down.
For more details, see the "Link Establishment" section in the "Controller Operations"
chapter of the Databook.
Values: 0x0, 0x1
Default Value: (CX_CPCIE_ENABLE && (CX_NL > 1)) ? 1 : 0
Enabled: ((CX_S_MPCIE_MODE) ? 0 : (CX_NL > 1))
Parameter Type: Feature Setting
Parameter Name: DEFAULT_UPCONFIGURE_SUPPORT

Lane Deskew Options

Disable Lane Deskew Disable the deskewing mechanism. Disable the deskewing mechanism only if
connecting to a multi-Lane PHY that implements Lane-to-Lane deskewing. For more
details, see the "Lane Deskew" chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_NL == 1
Enabled: ((CX_NL > 1))
Parameter Type: Feature Setting
Parameter Name: CX_DESKEW_DISABLE

Deskew Fifo Depth for C-PCIe Specifies the depth of fifos used in the deskew logic for C-PCIe. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 2, ..., 25
Default Value:

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Label Description

Deskew Fifo Depth for C-PCIe (CX_CCIX_ESM_SUPPORT == 1) && (CX_MAX_PCIE_SPEED == 5) && (CX_NB ==
...(cont.) 4) ? 14 : (CX_CCIX_ESM_SUPPORT == 1) && (CX_NB == 2) ? 22 :
(CX_CCIX_ESM_SUPPORT == 1) && (CX_NB == 4) ? 13 :
(CX_CCIX_ESM_SUPPORT == 1) && (CX_NB == 16) ? 12 :
(CX_MAX_PCIE_SPEED == 5) && (CX_NB == 4) ? 14 : (CX_MAX_PCIE_SPEED ==
5) && (CX_NB == 8) ? 12 : (CX_MAX_PCIE_SPEED == 4) &&
(CX_GEN4_DYNAMIC_WIDTH == 1) && (CX_NB == 16) ? 12 :
(CX_MAX_PCIE_SPEED == 4) && (CX_GEN4_DYNAMIC_WIDTH == 1) && (CX_NB
== 8 ) ? 14 : (CX_MAX_PCIE_SPEED == 4) && (CX_GEN4_DYNAMIC_FREQ == 1)
&& (CX_NB == 4 ) ? 12 : (CX_MAX_PCIE_SPEED == 4) &&
(CX_GEN4_DYNAMIC_FREQ == 1) && (CX_NB == 2 ) ? 20 :
(CX_MAX_PCIE_SPEED == 3) && (CX_GEN3_DYNAMIC_WIDTH == 1) && (CX_NB
== 8 ) ? 12 : (CX_MAX_PCIE_SPEED == 3) && (CX_GEN3_DYNAMIC_WIDTH == 1)
&& (CX_NB == 4 ) ? 14 : (CX_MAX_PCIE_SPEED == 3) &&
(CX_GEN3_DYNAMIC_FREQ == 1) && (CX_NB == 4 ) ? 11 :
(CX_MAX_PCIE_SPEED == 3) && (CX_GEN3_DYNAMIC_FREQ == 1) && (CX_NB
== 2 ) ? 12 : (CX_MAX_PCIE_SPEED == 3) && (CX_GEN3_DYNAMIC_FREQ == 1)
&& (CX_NB == 1 ) ? 19 : (CX_MAX_PCIE_SPEED == 2) &&
(CX_GEN2_DYNAMIC_WIDTH == 1) && (CX_NB == 4 ) ? 12 :
(CX_MAX_PCIE_SPEED == 2) && (CX_GEN2_DYNAMIC_WIDTH == 1) && (CX_NB
== 2 ) ? 14 : (CX_MAX_PCIE_SPEED == 2) && (CX_GEN2_DYNAMIC_FREQ == 1)
&& (CX_NB == 4 ) ? 11 : (CX_MAX_PCIE_SPEED == 2) &&
(CX_GEN2_DYNAMIC_FREQ == 1) && (CX_NB == 2 ) ? 12 :
(CX_MAX_PCIE_SPEED == 2) && (CX_GEN2_DYNAMIC_FREQ == 1) && (CX_NB
== 1 ) ? 14 : (CX_MAX_PCIE_SPEED == 1) && (CX_GEN2_MODE ==
GEN2_DISABLED) && (CX_NB == 4 ) ? 11 : (CX_MAX_PCIE_SPEED == 1) &&
(CX_GEN2_MODE == GEN2_DISABLED) && (CX_NB == 2 ) ? 12 :
(CX_MAX_PCIE_SPEED == 1) && (CX_GEN2_MODE == GEN2_DISABLED) &&
(CX_NB == 1 ) ? 14 : 14
Enabled: (!(CX_PCIE_MODE == SINGLE_MPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_DESKEW_DEPTH_CPCIE

+ Gen1 Wire Skew (Lrx-skew ns) This is read-only parameter to indicate how much wire skew for Gen1 speed your
deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: 20
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_GEN1_NS

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Label Description

+ Gen2 Wire Skew (Lrx-skew ns) This is read-only parameter to indicate how much wire skew for Gen2 speed your
deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 2) :
CX_S_CPCIE_MODE ? (CX_GEN2_MODE != GEN2_DISABLED) : 0)==1) ? 8 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_GEN2_NS

+ Gen3 Wire Skew (Lrx-skew ns) This is read-only parameter to indicate how much wire skew for Gen3 speed your
deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0)==1) ? 6 : 0
Enabled: CX_GEN3_SPEED==1 && SNPS_RSVDPARAM_32==1
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_GEN3_NS

+ Gen4 Wire Skew (Lrx-skew ns) This is read-only parameter to indicate how much wire skew for Gen4 speed your
deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: ((CX_GEN4_MODE != GEN4_DISABLED)==1) ? 5 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_GEN4_NS

+ Gen5 Wire Skew (Lrx-skew ns) This is read-only parameter to indicate how much wire skew for Gen5 speed your
deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: ((CX_MAX_PCIE_SPEED >= 5)==1) ? 5 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_GEN5_NS

+ CCIX ESM 20G Wire Skew This is read-only parameter to indicate how much wire skew for CCIX ESM 20G speed
(Lrx-skew ns) your deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details,
see the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: (CX_CCIX_ESM_SUPPORT==1) ? 4 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_CCIX20G_NS

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Label Description

+ CCIX ESM 25G Wire Skew This is read-only parameter to indicate how much wire skew for CCIX ESM 25G speed
(Lrx-skew ns) your deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details,
see the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: (CX_CCIX_ESM_SUPPORT==1) ? 4 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_CCIX25G_NS

+ Gen1 PHY Skew (pipe_clk This is read-only parameter to indicate how much PHY skew for Gen1 speed your
cycles) deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 ) ? 0 :
(CX_SKEW_PIPEIF_GEN1_PCLK - CX_WIRE_SKEW_GEN1_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_GEN1_PCLK

+ Gen2 PHY Skew (pipe_clk This is read-only parameter to indicate how much PHY skew for Gen2 speed your
cycles) deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 || CX_GEN2_SPEED==0 )
? 0 : (CX_SKEW_PIPEIF_GEN2_PCLK - CX_WIRE_SKEW_GEN2_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_GEN2_PCLK

+ Gen3 PHY Skew (pipe_clk This is read-only parameter to indicate how much PHY skew for Gen3 speed your
cycles) deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 || CX_GEN3_SPEED==0 )
? 0 : (CX_SKEW_PIPEIF_GEN3_PCLK - CX_WIRE_SKEW_GEN3_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_GEN3_PCLK

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Label Description

+ Gen4 PHY Skew (pipe_clk This is read-only parameter to indicate how much PHY skew for Gen4 speed your
cycles) deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 || CX_GEN4_SPEED==0 )
? 0 : (CX_SKEW_PIPEIF_GEN4_PCLK - CX_WIRE_SKEW_GEN4_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_GEN4_PCLK

+ Gen5 PHY Skew (pipe_clk This is read-only parameter to indicate how much PHY skew for Gen5 speed your
cycles) deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 || CX_GEN5_SPEED==0 )
? 0 : (CX_SKEW_PIPEIF_GEN5_PCLK - CX_WIRE_SKEW_GEN5_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_GEN5_PCLK

+ CCIX ESM 20G PHY Skew This is read-only parameter to indicate how much PHY skew for CCIX ESM 20G speed
(pipe_clk cycles) your deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details,
see the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 ||
CX_CCIX_ESM_SUPPORT==0 ) ? 0 : (CX_SKEW_PIPEIF_CCIX20G_PCLK -
CX_WIRE_SKEW_CCIX20G_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_CCIX20G_PCLK

+ CCIX ESM 25G PHY Skew This is read-only parameter to indicate how much PHY skew for CCIX ESM 25G speed
(pipe_clk cycles) your deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details,
see the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 ||
CX_CCIX_ESM_SUPPORT==0 ) ? 0 : (CX_SKEW_PIPEIF_CCIX25G_PCLK -
CX_WIRE_SKEW_CCIX25G_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_CCIX25G_PCLK

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Label Description

+ Margin for Deskew Buffer This is read-only parameter to indicate how much margin your deskew buffer setting
Setting (CX_DESKEW_DEPTH_CPCIE) has. For more details, see the "Lane Deskew"
chapter of the Databook.
Values: 0, ..., 10
Default Value: 1
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_SKEW_MAC_MARGIN_CORECLK

Layer 1/2 Options

Default Gen1/2 Replay Timer Default value for the 'Timer Modifier for Replay Timer' field in the 'Timer Control and
Adjustment Max Function Number' register. Each increment in this value increases the replay timer
by 64. For more details, see the 'Transmit Replay' section of the Controller Operations
chapter in the Databook.This parameter is for conventional PCIe mode.
Values: 0x0, ..., 0x1f
Default Value:
((CX_MAX_NFTS*4)/CX_NB)+(CX_CPCIE_INTERNAL_DELAY*3))/64 +
(((((CX_MAX_NFTS*4)/CX_NB)+(CX_CPCIE_INTERNAL_DELAY*3))%64) ? 1 : 0
Enabled: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE ))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_REPLAY_ADJ

Default Gen3/4/5 Replay Timer Default value (in Gen3/4/5 mode) for the 'Timer Modifier for Replay Timer' field in the
Adjustment 'Timer Control and Max Function Number' register at Gen3/4/5 speed. Must consider
an EIEOS is transmitted after every 32 FTS. Each increment in this value increases
the replay timer by 256. For more details, see the 'Transmit Replay' section of the
Controller Operations chapter in the Databook. M-PCIe doesn't support this feature.
Values: 0x0, ..., 0x1f
Default Value: ((CX_MAX_NFTS*65)/(CX_NB*1024)) +
((CX_MAX_NFTS*65)/(CX_NB*32768)) + ((CX_CPCIE_INTERNAL_DELAY*3)/256) +
3
Enabled: CX_GEN3_SPEED == 1 && CX_CPCIE_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_REPLAY_ADJ

Default FC Watch Dog Disable Default value of the Disable FC Watchdog Timer bit of the 'Symbol Timer Register and
Filter Mask 1' Register, in the 'Registers' section of the Databook.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: DEFAULT_FC_WATCH_DOG_DISABLE

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Label Description

Cfg Directed Speed Change Enables the controller to initiate a Gen1 -> Gen2 and Gen2 -> Gen3 speed change
after the link is initialized. Only applicable for Gen2 or Gen3 configured cores. This is
the default value of the "Directed Speed Change" field of the "Link width and Speed
Change Control" register. M-PCIe doesn't support this feature.
Values: 0, 1
Default Value: 0
Enabled: ((CX_S_MPCIE_MODE) ? 0 : CX_GEN2_SPEED)
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN2_SPEED_CHANGE

Power Gating

Power Gating/UPF Support Enables support for power gating using the UPF flow.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CX_CPCIE_ENABLE || SNPS_RSVDPARAM_9 ||
!CM_SNPS_MPHY_ENABLE) && !(AMBA_INTERFACE==1))
Parameter Type: Feature Setting
Parameter Name: CX_ENHANCED_PM_EN

Power Gating/PHY Support Enable power gating support in the PHY. When setting this parameter the PHY UPF
will be read in during PHY interoperability testing. If using a third party PHY, you need
to setup the PHY UPF following the guidelines provided in the User Guide, "Integrating
the controller with the PHY".
Values:
■ false (0)
■ true (1)
Default Value: CX_ENHANCED_PM_EN
Enabled: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE ))
Parameter Type: Feature Setting
Parameter Name: CX_PHY_ENHANCED_PM_EN

VAUX Available Indicates that VAUX power domain is available in L2 when VMAIN is removed.
Values: 0, 1
Default Value: 0
Enabled: CX_ENHANCED_PM_EN || CX_PHY_ENHANCED_PM_EN
Parameter Type: Feature Setting
Parameter Name: CX_EXISTS_VAUX

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Label Description

PHY L2 Power Gating Enable Indicates that power gating is supported in the PHY in L2
Values: 0, 1
Default Value: CX_L2_PG_EN
Enabled: CX_PHY_ENHANCED_PM_EN && CX_EXISTS_VAUX
Parameter Type: Feature Setting
Parameter Name: CX_PHY_L2_PG_EN

PHY L1 Power Gating Enable Enable support for power-gating L1 sub-states (L1.2) in C-PCIe PHY.
Values: 0, 1
Default Value: CX_L12_PG_EN
Enabled: ((CX_PHY_ENHANCED_PM_EN) && (CX_L1_SUBSTATES_ENABLE))
Parameter Type: Feature Setting
Parameter Name: CX_PHY_L1_PG_EN

L2 Power Gating Enable Indicates that power gating in L2 is supported


Values: 0, 1
Default Value: (CX_EXISTS_VAUX) ? 1 : 0
Enabled: CX_EXISTS_VAUX
Parameter Type: Feature Setting
Parameter Name: CX_L2_PG_EN

L1 Power Gating Enable Enable support for power-gating L1 sub-states (L1.2) in C-PCIe or L1 in M-PCIe. If you
want to disable L1 power gating in real-time, set app_l1_pwr_off_en =0.
Values: 0, 1
Default Value: 0
Enabled: ((CX_ENHANCED_PM_EN) && (CX_L1_SUBSTATES_ENABLE ||
CX_MPCIE_ENABLE))
Parameter Type: Feature Setting
Parameter Name: CX_L12_PG_EN

L1 Power Gating Mode Select always-on power islands or retention registers for L1 power gating. If you want
to disable L1 power gating, set app_l1_pwr_off_en =0.
Values:
■ Power Islands (0)
■ Retention Registers (1)
Default Value: Power Islands
Enabled: (CX_L12_PG_EN && (CX_L1_SUBSTATES_ENABLE ||
CX_MPCIE_ENABLE))
Parameter Type: Feature Setting
Parameter Name: CX_L1_RETENTION

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Label Description

L1 Retention Register Type This parameter determines the type of retention register inferred in the UPF file for L1
power gating.
Values:
■ Single Pin Retention (1)
■ Balloon Retention (2)
Default Value: Balloon Retention
Enabled: CX_L1_RETENTION
Parameter Type: Feature Setting
Parameter Name: CX_RETENTION_TYPE

L2 Level Shifter Enable Enable level shifting on the boundary between VAUX and VMAIN power domains
Values: 0, 1
Default Value: 0
Enabled: CX_ENHANCED_PM_EN && CX_L2_PG_EN
Parameter Type: Feature Setting
Parameter Name: CX_LEVEL_SHIFT_EN

Power Switch Enable Polarity Determine the polarity and naming of the power switch enable output.
■ 0: pm_en_vmain_n
■ 1: pm_en_vmain
Values:
■ LOW (0)
■ HIGH (1)
Default Value: LOW
Enabled: CX_L12_PG_EN
Parameter Type: Feature Setting
Parameter Name: CX_PSW_EN_ACTIVE_LOW

Save/Restore M-PHY Registers Enable saving/restoring of M-PHY registers during L1 power removal when M-PHY
power is off.
Values: 0, 1
Default Value: (CX_MPCIE_ENABLE && CX_ENHANCED_PM_EN &&
CM_SNPS_MPHY_ENABLE && SNPS_RSVDPARAM_9) ? 1 : 0
Enabled: CX_ENHANCED_PM_EN && CX_MPCIE_ENABLE &&
SNPS_RSVDPARAM_9
Parameter Type: Feature Setting
Parameter Name: CM_STORE_MPHY_ATTR_ENABLE

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Label Description

Power Switch Acknowledge If this bit is set to 0 the power management logic will wait for the power switch
Handhshake after PERST# acknowledge to be deasserted after PERST# is asserted. If this bit is set to 1 the
power management logic does not check the power switch acknowledge after
PERST# is asserted.
Values: 0, 1
Default Value: 0
Enabled: CX_L2_PG_EN
Parameter Type: Feature Setting
Parameter Name: CX_VMAIN_ACK_CTRL_RST_VALUE

ASPM Options

L1 Entry Latency Default value for the L1 Entrance Latency of the 'Ack Frequency and L0-L1 ASPM
Control' register. For more details, see the Registers section of the Databook. The
default value is acceptable unless a Custom or Generic PHY is used.
Values:
■ 1 us (0x0)
■ 2 us (0x1)
■ 4 us (0x2)
■ 8 us (0x3)
■ 16 us (0x4)
Default Value: 8 us
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L1_ENTR_LATENCY

L0S Entry Latency Default value for the L0s Entrance Latency field of the 'Ack Frequency and L0-L1
ASPM Control' register. For more details, see the Registers section of the Databook.
The default value is acceptable unless a Custom or Generic PHY is used. In M-PCIe,
this parameter is applicable to the STALL state in L0.
Values:
■ 1 us (0x0)
■ 2 us (0x1)
■ 3 us (0x2)
■ 4 us (0x3)
■ 5 us (0x4)
■ 6 us (0x5)
■ 7 us (0x6)
■ also 7us (0x7)
Default Value: 4 us
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L0S_ENTR_LATENCY

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Label Description

Enable ASPM L1 Timeout Enable the ASPM L1 timer so that the controller will automatically go to L1 when the
timer expires and the conditions in the PCI Express 3.1 Specificationare met. If you
disable the APSM L1 timer, the application can request L1 entry by asserting
app_req_entr_l1. The ASPM L1 timer should be larger than the L0s timer. Otherwise,
ASPM L0s and L1 timeout may not function properly.
Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_PL_MODE != 1
Enabled: CX_PL_MODE != 1
Parameter Type: Feature Setting
Parameter Name: CX_ASPM_TIMEOUT_ENTR_L1_EN

Error Detection

Enable ECRC Support Include the ECRC generation and checking hardware. This is distinct from the
software control that may be used to enable or disable ECRC.When disabled, ECRC
checking and insertion logic will not be included in the controller in order to reduce
gates. This is especially important for large architectures, in which these blocks can
consume timing margin as well as area. May be disabled for smaller gate size if the
controller is placed in a system where it's guaranteed that received TLPs don't contain
ECRC andyour application does not transmit ECRC from the application (client)
interfaces.
Values:
■ false (0)
■ true (1)
Default Value: CX_ADM_ADAPTOR_ENABLE==1 ? 0 : 1
Enabled: (TRGT1_POPULATE && !(AMBA_POPULATED) && !(CC_DMA_ENABLE))
Parameter Type: Feature Setting
Parameter Name: CX_ECRC_ENABLE

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Label Description

Enable ECRC Stripping Include ECRC stripping hardware. If enabled, the controller strips ECRC from all
incoming packets. The controller always strips the ECRC when you have selected the
AHB/AXI bridge module, or when DMA controller is selected. The controller never
strips the ECRC when you enable CX_P2P_ENABLE.
Values:
■ false (0)
■ true (1)
Default Value: !(TRGT1_POPULATE) || (CX_RAM_PROTECTION_MODE==2 &&
CX_RADMQ_MODE!=2) || (CX_ECRC_ENABLE && CC_DEVICE_TYPE!=CC_SW
&& !(CX_P2P_ENABLE)) || (( (RADM_NP_QMODE_VC0==2) ||
(RADM_NP_QMODE_VC1==2) || (RADM_NP_QMODE_VC2==2) ||
(RADM_NP_QMODE_VC3==2) || (RADM_NP_QMODE_VC4==2) ||
(RADM_NP_QMODE_VC5==2) || (RADM_NP_QMODE_VC6==2) ||
(RADM_NP_QMODE_VC7==2)) && (ARC_WIDTH==32)) ||
CX_CPLQ_MANAGEMENT_ENABLE
Enabled: (TRGT1_POPULATE && !(AMBA_POPULATED) && !(CC_DMA_ENABLE)
&& !(CC_DEVICE_TYPE==CC_SW) && !(CX_P2P_ENABLE) &&
!(CX_RAM_PROTECTION_MODE==2 && CX_RADMQ_MODE!=2) && !( (
(RADM_NP_QMODE_VC0==2) || (RADM_NP_QMODE_VC1==2) ||
(RADM_NP_QMODE_VC2==2) || (RADM_NP_QMODE_VC3==2) ||
(RADM_NP_QMODE_VC4==2) || (RADM_NP_QMODE_VC5==2) ||
(RADM_NP_QMODE_VC6==2) || (RADM_NP_QMODE_VC7==2)) &&
(ARC_WIDTH==32)) || CX_CPLQ_MANAGEMENT_ENABLE )
Parameter Type: Feature Setting
Parameter Name: CX_ECRC_STRIP_ENABLE

Extra Interface Options

Include 3rd Client Interface Determines whether to include top-level ports for the optional third application transmit
client interface (XALI2).
Values:
■ false (0)
■ true (1)
Default Value: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3)) ? 1 : 0
Enabled: (!(AMBA_INTERFACE!=0))
Parameter Type: Feature Setting
Parameter Name: CLIENT2_POPULATED

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Label Description

Enable Diagnostic Bus Enables routing of diag_status_bus and diag_ctrl_bus signals to the SII interface. For
more details, see 'SII: Diagnostic Control Signals' in the "Signal Descriptions" chapter
of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: CX_RAS_DES_ENABLE
Enabled: !CX_RAS_DES_ENABLE
Parameter Type: Feature Setting
Parameter Name: DIAGNOSTIC_ENABLE

Application Error Reporting Determines whether to include input ports for application-detected error reporting. For
more details, see the "Application Error Reporting Interface" section on the " Advanced
Error Handling For Received TLPs" chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: CX_DPC_ENABLE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: APP_RETURN_ERR_EN

LBC-ELBI-DBI Advanced Options

DBI ReadOnly Write Enable Default value of the DBI Read-Only Write Enable port logic register. For more details,
see the "Register Configuration Space" chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_DBI_RO_WR_EN

Disable Port Logic wire side write When set will disable write access to port logic space from the wire.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_PL_WIRE_WR_DISABLE

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Label Description

ELBI Address Bus Width Defines the width of the ELBI address bus for the Local Bus Controller (LBC). Only
12-bits are needed to access the 4KB (1K DWORDS) of the PCI Express
Configuration space per function. However, in order to access more than 4 KB of ELBI
register space, the default value of CX_LBC_EXT_AW can be increased up to a
maximum of 32. Refer to 'Local Bus Controller (LBC)' section in the Architecture
chapter of the Databook.
Values: 12, ..., (FLT_Q_ADDR_WIDTH<=32) ? FLT_Q_ADDR_WIDTH : 32
Default Value: 32
Enabled: ((CC_DEVICE_TYPE!=CC_RC))
Parameter Type: Feature Setting
Parameter Name: CX_LBC_EXT_AW

ELBI Data Bus Width Defines the width of the ELBI databus for the Local Bus Controller (LBC) in dwords.
There are 32 or 64 bits of ext_lbc_din for each function in your controller configuration.
(128 bits is planned for future release).
Values:
■ 32-bit (1)
■ 64-bit (2)
Default Value: 32-bit
Enabled: ((CC_DEVICE_TYPE!=CC_RC))
Parameter Type: Feature Setting
Parameter Name: CX_LBC_NW

DBI Full Access with BAR and Provide support to allow DBI full access with BAR number and function number.
Function Number Setting the DBI_MULTI_FUNC_BAR_EN configuration parameter allows the DBI
interface to direct an access to a particular BAR#. This helps the ELBI application logic
to fully decode an access to the ELBI space when multiple BARs have been mapped
to RTRGT0 and need to be accessed via the DBI. By default,
DBI_MULTI_FUNCT_BAR_EN is set to 0, indicating a single BAR at the ELBI. Refer to
'Local Bus Controller (LBC)' section in the Architecture chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: MSIX_TABLE_EN
Enabled: ((CC_DEVICE_TYPE!=CC_RC) && (CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Feature Setting
Parameter Name: DBI_MULTI_FUNC_BAR_EN

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Label Description

Application Configuration This configuration parameter is deprecated and should no longer be used. Specifies
Register Address the default value of register CONFIG_LIMIT_REG. It specifies a limit above which
incoming configuration requests will be routed to the destination interface defined by
TARGET_ABOVE_CONFIG_LIMIT. The CONFIG_LIMIT parameter is normally set to
a limit that divides the core's configuration space registers from the application's
configuration space registers. The controller LBC module uses this limit to direct a
configuration request to the CDM or ELBI/RTRGT1. The application must set a proper
value based on its extended configuration registers. For more details, see the 'Local
Bus Controller (LBC)' section in the Controller Operations chapter of the Databook.
■ This value indicates a DWORD address and not a byte address.
■ The default setting of 0x3FF corresponds to the 4K upper limit of configuration
space and so TRGT0 will consume all CFG transactions by default.
CONFIG_LIMIT must be set to a value lower than this is have an effect.
Normally, you would never set this to less than 0xD00 which is the top of the Synopsys
Port Logic register space. Note: Superseded by the Configuration Intercept
Controller(CIC) interface, enabled when CX_CONFIG_INTERCEPT_ENABLE=1. The
CIC provides a much more flexible way for the application to control routing of
configuration transactions.
Values: 0x0, ..., 0x3ff
Default Value: 0x3ff
Enabled: CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: CONFIG_LIMIT

Application Configuration Specifies the default value of register TARGET_ABOVE_CONFIG_LIMIT. Target


Register Location interface destination for configuration requests with an address greater than
CONFIG_LIMIT. Normally you would set this to '1' (ELBI).
Values:
■ ELBI (1)
■ Target_1 (2)
Default Value: TRGT1_POPULATE==1 ? 2 : 1
Enabled: TRGT1_POPULATE==1 && CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: TARGET_ABOVE_CONFIG_LIMIT

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Label Description

Memory Map Port Logic Enables routing of memory (non-CFG) transactions to the port logic (PL) configuration
Registers registers. This is memory mapping of the PL register space. PL registers (which by
default are accessed by CFG requests) can also (at the same time) be accessed by
MEM requests through the use of the ENABLE_MEM_MAP_PL_REG,
PL_FUNC_NUM and PL_BAR_NUM configuration parameters. These can be used to
map the PL registers to any BAR of any function. All MEM requests that match
PL_BAR_NUM (when ENABLE_MEM_MAP_PL_REG=1) and whose address offset is
in the range 0x700-0x8FF will be routed to the PL registers. The BAR corresponding to
PL_BAR_NUM must also be mapped/assigned to RTRGT0. For more details, see the
"Local Bus Controller (LBC)" section in the "Controller Operations" chapter of the
Databook.
Values: 0, 1
Default Value: 0
Enabled: CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: ENABLE_MEM_MAP_PL_REG

Port Logic Function Indicates which function is used to map the Port Logic configuration registers into
memory space. For more details, see the ENABLE_MEM_MAP_PL_REG parameter.
Values: 0, ..., 7
Default Value: 0
Enabled: ENABLE_MEM_MAP_PL_REG==1
Parameter Type: Feature Setting
Parameter Name: PL_FUNC_NUM

Port Logic BAR Indicates which BAR is used to map the Port Logic configuration registers into memory
space. For more details, see the ENABLE_MEM_MAP_PL_REG parameter.
Values:
■ BAR0 (0)
■ BAR1 (1)
■ BAR2 (2)
■ BAR3 (3)
■ BAR4 (4)
■ BAR5 (5)
Default Value: BAR0
Enabled: ENABLE_MEM_MAP_PL_REG==1
Parameter Type: Feature Setting
Parameter Name: PL_BAR_NUM

Port Logic Register Address Limit Indicates the limit address for BAR matched memory mapped Port Logic configuration
registers.
Values: 2304, ..., 3104
Default Value: 3104
Enabled: ENABLE_MEM_MAP_PL_REG==1
Parameter Type: Feature Setting
Parameter Name: PL_LIMIT

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Label Description

Configuration Intercept Enable Enables Configuration Intercept feature. Allows your application logic to modify the
behavior of Rx CFG requests that are accessing the core's internal registers. For more
details, see the "Advanced LBC and DBI Usage" chapter in the Databook. This is an
advanced feature that is only required in exceptional applications.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: CX_CONFIG_INTERCEPT_ENABLE

Memory Map ATU UNROLL Enables routing of memory (non-CFG) transactions to the Unroll ATU configuration
Registers registers. Unroll registers can be accessed by MEM requests through the use of the
ENABLE_MEM_MAP_UNROLL_ATU_REG, UNROLL_FUNC_NUM and
UNROLL_BAR_NUM configuration parameters. These can be used to map the
UNROLL registers to any BAR of any function. All MEM requests that match
UNROLL_BAR_NUM (when ENABLE_MEM_MAP_UNROLL_ATU_REG=1) and
whose address offset is in the range
UNROLL_ATU_OFFSET_BAR-UNROLL_ATU_OFFSET_BAR+UNROLL_ATU_SIZE
will be routed to the UNROLL registers. The BAR corresponding to
UNROLL_BAR_NUM must also be mapped/assigned to RTRGT0. For more details,
see the "Local Bus Controller (LBC)" section in the "Controller Operations" chapter of
the Databook.
Values: 0, 1
Default Value: 0
Enabled: CC_DEVICE_TYPE!=CC_RC && CX_INTERNAL_ATU_ENABLE &&
CC_UNROLL_ENABLE
Parameter Type: Feature Setting
Parameter Name: ENABLE_MEM_MAP_UNROLL_ATU_REG

Offset BAR address for ATU Indicates the offset BAR address to allocate the UNROLL ATU configuration registers
UNROLL Registers into memory space.
Values: 0x0, ..., 0xffffffffffffffff
Default Value: 0x1200
Enabled: ENABLE_MEM_MAP_UNROLL_ATU_REG==1
Parameter Type: Feature Setting
Parameter Name: UNROLL_ATU_OFFSET_BAR

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Label Description

Memory Map DMA UNROLL Enables routing of memory (non-CFG) transactions to the Unroll DMA configuration
Registers registers. Unroll DMA registers can be accessed by MEM requests through the use of
the ENABLE_MEM_MAP_UNROLL_DMA_REG, UNROLL_FUNC_NUM and
UNROLL_BAR_NUM configuration parameters. These can be used to map the
UNROLL registers to any BAR of any function. All MEM requests that match
UNROLL_BAR_NUM (when ENABLE_MEM_MAP_UNROLL_DMA_REG=1) and
whose address offset is in the range
UNROLL_DMA_OFFSET_BAR-UNROLL_DMA_OFFSET_BAR+UNROLL_DMA_SIZ
E will be routed to the UNROLL registers. The BAR corresponding to
UNROLL_BAR_NUM must also be mapped/assigned to RTRGT0. For more details,
see the "Local Bus Controller (LBC)" section in the "Controller Operations" chapter of
the Databook.
Values: 0, 1
Default Value: 0
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DMA_ENABLE &&
CC_UNROLL_ENABLE
Parameter Type: Feature Setting
Parameter Name: ENABLE_MEM_MAP_UNROLL_DMA_REG

Offset BAR address for DMA Indicates the offset BAR address to allocate the UNROLL DMA configuration registers
UNROLL Registers into memory space.
Values: 0x0, ..., 0xffffffffffffffff
Default Value: 0x1000
Enabled: ENABLE_MEM_MAP_UNROLL_DMA_REG
Parameter Type: Feature Setting
Parameter Name: UNROLL_DMA_OFFSET_BAR

UNROLL Function Indicates which function is used to map the Unroll configuration registers into memory
space. For more details, see the ENABLE_MEM_MAP_UNROLL_ATU_REG or
ENABLE_MEM_MAP_UNROLL_DMA_REG parameter.
Values: 0, ..., 7
Default Value: 0
Enabled: ENABLE_MEM_MAP_UNROLL_ATU_REG==1 ||
ENABLE_MEM_MAP_UNROLL_DMA_REG==1
Parameter Type: Feature Setting
Parameter Name: UNROLL_FUNC_NUM

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Label Description

UNROLL BAR Indicates which BAR is used to map the UNROLL configuration registers into memory
space. For more details, see the ENABLE_MEM_MAP_UNROLL_ATU_REG or
ENABLE_MEM_MAP_UNROLL_DMA_REG parameter.
Values:
■ BAR0 (0)
■ BAR1 (1)
■ BAR2 (2)
■ BAR3 (3)
■ BAR4 (4)
■ BAR5 (5)
Default Value: BAR0
Enabled: ENABLE_MEM_MAP_UNROLL_ATU_REG==1 ||
ENABLE_MEM_MAP_UNROLL_DMA_REG==1
Parameter Type: Feature Setting
Parameter Name: UNROLL_BAR_NUM

Receive Filter Options

Number of Address Bits Passed Indicates the number of address bits that are passed through the receive queues and
to the Application are sent to the application on the RTRGT1 interface (radm_trgt1_addr).
■ DM/RC: The default is 64. the minimum number of bits allowed is normally 32.
■ SW: The default is 64 and the parameter is read-only.
■ EP: The default is 64 when VENDOR_MESSAGE_SUPPORT |
DEFAULT_TARGET | ((CX_INTERNAL_ATU_ENABLE | ADDR_TRANSLA-
TION_SUPPORT_EN) & CX_CLIENT_PAR_MODE !=0 ), otherwise 32. The
minimum number of bits allowed is normally 32.
Values: 26, ..., 64
Default Value: (VENDOR_MESSAGE_SUPPORT || DEFAULT_TARGET ||
(CC_DEVICE_TYPE!=CC_EP) || ADDR_TRANSLATION_SUPPORT_EN &&
(CX_CLIENT_PAR_MODE!=0 || ECC_PROTECTION_EN!=0)) ? 64 : 32
Enabled: !(VENDOR_MESSAGE_SUPPORT || DEFAULT_TARGET ||
(CC_DEVICE_TYPE==CC_SW) || ADDR_TRANSLATION_SUPPORT_EN &&
(CX_CLIENT_PAR_MODE!=0 || ECC_PROTECTION_EN!=0))
Parameter Type: Feature Setting
Parameter Name: FLT_Q_ADDR_WIDTH

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Label Description

Application Receives Full When you want to route the third header dword of received messages to your
Message Header application interface (RRTRGT1 or AXI bridge master interface), then you must
manually set FLT_Q_ADDR_WIDTH to 64 bits, or set this parameter to "1". Setting this
parameter to "1" forces FLT_Q_ADDR_WIDTH to 64 bits. This adds gates and makes
some RAMs wider. The complete message header is always routed to the SII interface
regardless of this parameter setting.
Values:
■ false (0)
■ true (1)
Default Value: CX_CCIX_INTERFACE_ENABLE
Enabled: CC_DEVICE_TYPE==CC_EP
Parameter Type: Feature Setting
Parameter Name: VENDOR_MESSAGE_SUPPORT

Terminate Received Messages Drop message TLPs and do not pass them to the application on RTRGT1. The
controller processes received messages and decodes the header before sending it to
the application logic on the System Information Interface (SII). By default, received
messages are dropped silently and not passed to the application on RTRGT1. To have
all decoded messages also sent to the application then do not set this parameter.
■ True: Discard message after decoding
■ False: Pass message TLP to application on RTRGT1
Note: When The "Receive Posted Queue Mode" is Bypass (RADM_P_QMODE_VC0
= 0x4), received messages are not dropped and are always passed to the application
irrespective of the setting of this parameter.
For more details, see "Routing of Received Messages to SII and optionally to
Application" in the "Message Reception" section in the Controller Operations chapter
of the Databook. Your application can override the value of this option at runtime by
writing to the 'Symbol Timer Register and Filter Mask Register 1'. These registers
allow you to override any decisions (regarding MSG routing) made at configuration
time by the FLT_DROP_MSG, DEFAULT_FILTER_MASK_1 and
DEFAULT_FILTER_MASK_2 configuration parameters.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: FLT_DROP_MSG

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Label Description

Receive Filter Rule Mask Default value for Filter Mask Register 1 ('Symbol Timer Register and Filter Mask
Register 1 Register 1'). This register is used to set the number of symbol times to wait between
transmitting SKP ordered sets, and also to mask the RADM Filtering and Error
Handling Rules. There are several mask bits used to turn off the filtering and error
handling rules. For more details, see the 'Receive Filtering' section in Controller
Operations chapter of the Databook.
Values: 0x0, ..., 0xffff
Default Value: (FLT_DROP_MSG ? 0 : 0x2000) | (CX_SRIOV_ENABLE ? 0x0008 : 0)
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_FILTER_MASK_1

Receive Filter Rule Mask Default value for 'Filter Mask Register 2'. This register is used to mask the RADM
Register 2 Filtering and Error Handling Rules. There are several mask bits used to turn off the
filtering and error handling rules. For more details, see the 'Receive Filtering' section in
Controller Operations chapter of the Databook.
Values: 0x0, ..., 0xffffffff
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_FILTER_MASK_2

Mask Completion Timeout Errors Mask detection of completion timeout errors. When selected, the controller will not
automatically report completion timeout errors. Your application must check for
completion timeouts and report them using the app_err_bus input signal on the
application error return interface. The 'Application Error Reporting'
(APP_RETURN_ERR_EN) parameter must be enabled to activate the application
error return interface.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: APP_RETURN_ERR_EN==1
Parameter Type: Feature Setting
Parameter Name: CPL_TIMEOUT_ERR_MASK

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Label Description

Enable Optional Checks Adds optional protocol checks including byte enable and flow control. Violations of the
byte enable check (Section 2.2.5 of the PCIe Specification) and the address/length
check (Section 2.2.7 of the PCIe Specification) will be treated as malformed TLPs.
Also, violations of the various flow control checks will result in a Flow Control Protocol
Error (FCPE). Flow control checks are described in Section 2.6.1 of the PCIe
Specification.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: ENABLE_OPTIONAL_CHECKS

Receive Errored-TLP Forwarding Options

Forward Errored-TLPs To Forward all incoming I/O or MEM requests with UR/CA/CRS status to your application.
Application By default, all such requests are dropped in store-and-forward mode (after
corresponding error reporting). A completion with UR status will be generated for
non-posted requests. For more details, see the description of the DEFAULT_TARGET
port logic register. See also the "ECRC Handling" and "Request TLP Routing Rules" in
the "Receive Routing" sections in the "Controller Operations" chapter of the Databook.
■ When you set this parameter, you should also set CX_MASK_UR_CA_4_TRGT1
■ This parameter sets the default value of the DEFAULT_TARGET field in the
MISC_CONTROL_1_OFF port logic register.
■ This parameter only applies to EP, DM in EP mode, or SW in USP mode. It does
not apply to a DSP.
Values:
■ Drop (0x0)
■ Forward (0x1)
Default Value: Drop
Enabled: TRGT1_POPULATE==1 && CC_DEVICE_TYPE!=CC_RC
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_TARGET

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Label Description

Suppress Errors for Forwarded Suppress error logging, Error Message generation, and CPL generation (for
Unsupported Requests non-posted requests) for requests TLPs with UR filtering status that you have chosen
to forward to the application (when you set the DEFAULT_TARGET field). For more
details, refer to the description of the UR_CA_MASK_4_TRGT1 field, "ECRC
Handling" and "Request TLP Routing Rules" in the "Receive Routing" section in the
"Controller Operations" chapter of the Databook.
■ This parameter sets the default value of the UR_CA_MASK_4_TRGT1 field in the
MISC_CONTROL_1_OFF port logic register.
■ You should set this if you have set the DEFAULT_TARGET parameter to '1'.
■ This parameter only applies to EP, or DM in EP mode. It does not apply to a DSP.
Values:
■ Report_UR_ERR (0x0)
■ Suppress_UR_ERR (0x1)
Default Value: Report_UR_ERR
Enabled: CC_DEVICE_TYPE!=CC_SW && CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: CX_MASK_UR_CA_4_TRGT1

Indicate ECRC Error Using Passes the ECRC error notification to your application on the corresponding
Application I/O radm_<trgt1|cpl|byp>_ecrc_err output. Otherwise the controller will not assert the
output when it receives a TLP with an ECRC error.
■ This parameter is only used for queues configured in cut-through or
store-and-forward mode. It does not apply to bypass mode.
■ The default setting of this parameter is sufficient for most applications. For more
details, see the 'Error Detection For Received TLPs' section in the 'Controller Oper-
ations' chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_RADMQ_MODE==2 && AMBA_INTERFACE==0
Parameter Type: Feature Setting
Parameter Name: ECRC_ERR_PASS_THROUGH

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6.9 Advanced AXI Config / Advanced AHB Config Parameters


Table 6-9 Advanced AXI Config / Advanced AHB Config Parameters

Label Description

General Options

AHB Endianness Mode Selection Selects Endianness for the AHB interface.
■ Little: Static Little Endian
■ Big: Static Big Endian
■ Dynamic: Pin Selectable
For more details, see 'Endianess Support' in the AHB section of the Databook.
Values:
■ Little (0)
■ Big (1)
■ Dynamic (2)
Default Value: Little
Enabled: AMBA_INTERFACE==1
Parameter Type: Feature Setting
Parameter Name: AHB_ENDIANNESS

Advanced Slave Options

Number Masters connected to Indicates the number of AHB masters that access the PCIe bridge slave. This is used
Slave to determine the number of internal bridge tags to support SPLIT_RETRY response.
For more details, see the AHB section of the Databook.
Note:AHB only.
Values: 4, 8, 16
Default Value: 4
Enabled: AHB_POPULATED && SLAVE_POPULATED && SPLIT_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CC_SLV_NUM_MASTERS

AHB Slave Response Mode Selects Normal or SPLIT-RETRY response for the AHB slave interface. When the
normal data slave is configured for SPLIT-RETRY response mode, the dedicated DBI
slave (if present) will still operate in NORMAL response mode by keeping
dbi_hready_resp low. For more details, see the AHB section of the Databook.
Note:There is no SPLIT-RETRY support for the DBI slave.
Values:
■ Normal (0)
■ SPLIT_RETRY (1)
Default Value: Normal
Enabled: AMBA_INTERFACE==1
Parameter Type: Feature Setting
Parameter Name: CC_RESPONSE_MODE

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Label Description

AHB Slave Enables an immediate error response from the slave and DBI slave for an illegal AHB
access. For more details see the slv_hresp signal description in the Databook. If the
parameter RETURN_ERR_RESP is set then the bridge slave interface will perform
immediate error checking on the slave interface protocol signals (slv_hsize, slv_haddr,
slv_req_misc_info[25:22]) and return an ERROR status on slv_hresp immediately. It
will not transmit the outbound request TLP. The following two checks are done:
■ HSIZE check. For example, for a data width of 32-bits you will get an immediate
ERROR response if slv_hsize is not 0,1 or 2.
■ CFG & I/O transfers are checked for byte enable, hsize and address alignment.
For more details, see the "Zero-Byte Transfers Over the AHB Bridge (Flush
Semantics)2 section of the Databook. The recommended setting for this parameter is
"True".
Values:
■ False (0)
■ True (1)
Default Value: True
Enabled: AHB_POPULATED && SLAVE_POPULATED
Parameter Type: Feature Setting
Parameter Name: RETURN_ERR_RESP

Advanced Master Options

AHB Master Burst Type Specifies whether the master interface will generate defined
(SINGLE/INCR4/INCR8/INCR16) or undefined length INCR bursts. For more details,
see the AHB section of the Databook. Value range:
■ 0 : Fixed (Defined Length)
■ 1 : Unspecified (Undefined Length)
Note:AHB only.
Values:
■ Fixed (0)
■ Unspecified (1)
Default Value: Unspecified
Enabled: MASTER_POPULATED && AHB_POPULATED
Parameter Type: Feature Setting
Parameter Name: CC_MSTR_BURST_TYPE

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Label Description

Master Request's DATA FIFO Specifies AHB Master Request Data FIFO Queue depth in words. The word width is
Queue Depth either CC_CORE_DATA_BUS_WD+1 or CC_MSTR_BUS_DATA_WIDTH+1. The
default value is sufficient for most applications.
Values: -2147483648, ..., 2147483647
Default Value: (MASTER_POPULATED) ? (MASTER_BUS_DATA_WIDTH >
PCIE_CORE_DATA_BUS_WD ?
((AMBA_DECOMPOSER_DEF_DEPTH_FACTOR*CC_MSTR_MTU)/(CC_MSTR_N
W*4)+2) :
((AMBA_DECOMPOSER_DEF_DEPTH_FACTOR*CC_MSTR_MTU)/(CX_NW*4)+2))
:4
Enabled: AHB_POPULATED && MASTER_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_RADMX_DECOMPOSER_DATAQ_DP

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6.10 Advanced AXI Config / Advanced AXI Config Parameters


Table 6-10 Advanced AXI Config / Advanced AXI Config Parameters

Label Description

Distributed Translation Interface Master (DTIM)

DTIM Enable Enables the Root Ports Distributed Translation Interface Master (DTIM). The DTI
Master interfaces to an external Memory Management Unit (MMU). The MMU
provides address translation functions for the memory accessing PCIe AXI masters.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_DM) &&
MASTER_POPULATED
Parameter Type: Feature Setting
Parameter Name: CC_DTIM_ENABLE

Root Port ID The Root Port ID determines the upper 16-bits of the PCIe DTIM Stream ID (SID).
Values: 0x0, ..., 0xffff
Default Value: 0xffff
Enabled: CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_ROOT_PORT_ID

DTIM Translation Request This parameter indicates the maximum number of translation request tokens
Tokens Requested requested by the DTI Master, i.e. the maximum number of DTI-ATS translation
requests outstanding at any point in time. It is used to flow control the number of
outstanding translation requests sent by the DTI Master AXI4-Stream Master.
Values: 1, ..., 256
Default Value: 32
Enabled: CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_DTIM_NUM_TRANS_TOKENS_REQUESTED

DTIM Invalidate Request Tokens This parameter indicates the maximum number of invalidate request tokens granted by
Granted the DTI Master, i.e. the maximum number of DTI-ATS invalidate requests outstanding
at any point in time. It is used to determine the depth of the DTI Master AXI4-Stream
Slave Request queue.
Values: 4, 8, 16
Default Value: 16
Enabled: CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_DTIM_NUM_INV_TOKENS_GRANTED

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Label Description

DTIM PCIe Max Num The maximum number of outstanding PCIe invalidate requests that can be sent on the
Outstanding Invalidate Requests wire. The theoretical maximum is 32 requests per BDF.
Values: 16, 32, 64, 128, 256
Default Value: 32
Enabled: CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_DTIM_PCIE_MAX_NUM_INV_REQ

Advanced Slave Options

AXI Slave ID Width Specifies the width of the AXI slave interface ID bus. You can increase or decrease
CC_SLV_BUS_ID_WIDTH but your application master must never issue more than
CC_MAX_SLV_TAG different AXI ID's (for non-posted requests) because the bridge is
still only configured to handle CC_MAX_SLV_TAG different AXI ID's.
CC_SLV_BUS_ID_WIDTH sets the width of each entry in the Slave Response
Application-Tag Look Up Table, but it does not determine the number of available
TAGs. Default value is ceil [log2{CC_MAX_SLV_TAG}]. For more details, see
"Increasing Size of AXI Slave ID Bus" in the AXI chapter of the Databook.)
Values: 1, ..., 32
Default Value: [calc_log2 CC_MAX_SLV_TAG]
Enabled: SLAVE_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_SLV_BUS_ID_WIDTH

AXI Slave Multiple Requests per Enable support for multiple request per AXI ID on the AXI Slave
ID Enable Values: 0, 1
Default Value: 1
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Feature Setting
Parameter Name: CC_AXI_SLV_MULTIPLE_REQ_PER_ID_EN

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PCI Express SW Controller Databook Advanced AXI Config / Advanced AXI Config Parameters

Label Description

Advanced Master Options

AXI Master Fixed Size Transfer Specifies that the AXI master interface will (under certain conditions) do a single
Enable bus-wide access when doing narrow read transfers rather than multiple byte-wide
accesses. When you set CC_MSTR_BURST_LEN to <
MASTER_BUS_DATA_WIDTH/8, then MSTR_FIXED_SIZE_ENABLE=1 because the
master cannot produce a sufficiently long burst of bytes. Therefore the master uses
dword access and not byte access for narrow or NCBE reads; which means that such
accesses to non-prefetchable memory might result in corrupting not-to-be-read data.
For more details on this and other restrictions, see the description of the
CC_MSTR_BURST_LEN parameter and the 'Supported AXI Transfer Sizes' section in
the AXI chapter of the Databook.
Values: 0, 1
Default Value: (((CC_MSTR_BURST_LEN==8) &&
(MASTER_BUS_DATA_WIDTH==64)) || (CC_MSTR_BURST_LEN <
MASTER_BUS_DATA_WIDTH/8)) ? 1 : 0
Enabled: (AXI_POPULATED && MASTER_POPULATED &&
!((CC_MSTR_BURST_LEN==8) && (MASTER_BUS_DATA_WIDTH==64)))
Parameter Type: Performance Setting
Parameter Name: MSTR_FIXED_SIZE_ENABLE

AXI Master Sub Bus Size Read Specifies that the master performs a narrow read transfer in one beat when the PCIe
Enable request size is a power of two and the AXI address is AXI transfer-size aligned. For
more details, see "Supported AXI Transfer Sizes" section of the Databook.
Note:AXI only.
Values: 0, 1
Default Value: 0
Enabled: AXI_POPULATED && MASTER_POPULATED
Parameter Type: Performance Setting
Parameter Name: MSTR_SUB_BUS_SIZE_READ_ENABLE

AXI Master Sub Bus Size Write Specifies that the master performs a narrow write transfer in one beat when the PCIe
Enable request size is a power of two and the AXI address is AXI transfer-size aligned. For
more details, see "Supported AXI Transfer Sizes" section of the Databook.
Note:AXI only.
Values: 0, 1
Default Value: 0
Enabled: AXI_POPULATED && MASTER_POPULATED
Parameter Type: Performance Setting
Parameter Name: MSTR_SUB_BUS_SIZE_WRITE_ENABLE

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Label Description

AXI Master NCBE Read Specifies that the master does not decompose NCBE read requests into a stream of
Decompose Disable single-byte requests. For more details, see 'Non Contiguous Byte Enable (NCBE)
Support' section of the Databook.
■ 0: Enables read NCBE decomposition into single-byte requests.
■ 1: Disables read NCBE decomposition into single-byte requests.
Values: 0, 1
Default Value: !MSTR_SUB_BUS_SIZE_READ_ENABLE &&
MSTR_FIXED_SIZE_ENABLE
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_AXI_NCBE_NODECOMP

AXI Master Read Response Enable support for interleaved read responses on the AXI Master
Interleaving Enable Values: 0, 1
Default Value: 1
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Feature Setting
Parameter Name: CX_AXI_MSTR_RD_RSP_INTERLEAVING_EN

Inbound Posted Tracker

Inbound Posted Tracker Enable Enables Inbound Posted Tracker. Allows P to pass P on multi-VC configuration. Allows
RO CPL and NP ordering disabling features.
Values: 0, 1
Default Value: CC_HP_MASTER
Enabled: AMBA_INTERFACE > 1
Parameter Type: Feature Setting
Parameter Name: CC_IB_WREQ_PTRK_EN

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / MSI/MSI-X Capability

6.11 Device-Wide PCIe Features and Capabilities Config / MSI/MSI-X Capability


Parameters
Table 6-11 Device-Wide PCIe Features and Capabilities Config / MSI/MSI-X Capability Parameters

Label Description

MSI/MSI-X

MSI Capability Include the MSI capability structure.


Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: MSI_CAP_ENABLE

MSI PVM Support Support MSI Capability Per Vector Masking


Values:
■ false (0)
■ true (1)
Default Value: MSI_CAP_ENABLE && CX_SRIOV_ENABLE &&
CC_DEVICE_TYPE!=CC_RC
Enabled: !CX_SRIOV_ENABLE && MSI_CAP_ENABLE &&
CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: MSI_PVM_EN

MSI IO Enable Include optional top-level ports for MSI, as listed in 'Message Signaled Interrupt (MSI)
Interface' section of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: MSI_CAP_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: MSI_IO

Default Multiple MSI Capability Default value for the Multiple Message Capable field in the 'MSI Control Register'.
Values: 0x0, ..., 0x5
Default Value: 0x0
Enabled: MSI_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_MULTI_MSI_CAPABLE

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Label Description

Default Extended Message Data Default value for the Extended Message Data Capable field in the 'MSI Control
for MSI Capability Register'.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: MSI_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_EXT_MSI_DATA_CAPABLE

MSI-X Capability Include the MSI-X capability structure.


Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: MSIX_CAP_ENABLE

Enable Integrated MSI-X Implements the MSI-X generation logic with the data/address table and PBA in the
Generation Module core. For more details, see the Interrupts section in the "Controller Operations" chapter
of the Databook. Not available when Extensible Virtual Function
(CX_EXTENSIBLE_VFUNC) is enabled.
Values: 0, 1
Default Value: 0
Enabled: (((CC_DEVICE_TYPE==CC_EP) || (CC_DEVICE_TYPE==CC_DM)) &&
!CX_EXTENSIBLE_VFUNC)
Parameter Name: MSIX_TABLE_EN

MSI-X IO Enable Include optional top-level ports for MSI-X, as listed in the 'MSI-X Interface' section of
the Databook. If included, the MSI-X ports are used only when the controller is
operating as an upstream port.
Values:
■ false (0x0)
■ true (0x1)
Default Value: MSIX_CAP_ENABLE
Enabled: MSIX_CAP_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: MSIX_IO

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / PCIe Capability Parameters

6.12 Device-Wide PCIe Features and Capabilities Config / PCIe Capability


Parameters
Table 6-12 Device-Wide PCIe Features and Capabilities Config / PCIe Capability Parameters

Label Description

PCIe Capability

CRS Software Visibility Default Default value for the CRS Software Visibility bit in the Root Capabilities Register.
Values: 0x0, 0x1
Default Value: 0x1
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_CRS_SW_VISIBILITY_CAP

ASPM Latencies

L0S Exit Latency Default value for the L0s Exit Latency field in the 'Link Capabilities Register'. M-PCIe
doesn't use this parameter.
Values:
■ Less than 64ns (0x0)
■ 64ns to less than 128ns (0x1)
■ 128ns to less than 256ns (0x2)
■ 256ns to less than 512ns (0x3)
■ 512ns to less than 1us (0x4)
■ 1us to less than 2us (0x5)
■ 2us to 4us (0x6)
■ More than 4us (0x7)
Default Value: [calc_cal_nfts ((CX_GEN2_SPEED==1) ? ((DEFAULT_GEN2_N_FTS
> CX_MAX_NFTS_TMP) ? DEFAULT_GEN2_N_FTS : CX_MAX_NFTS_TMP) :
CX_MAX_NFTS_TMP) ]
Enabled: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE ))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L0S_EXIT_LATENCY

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Label Description

L0S Exit Latency (Common Default value for the L0s Exit Latency field in the 'Link Capabilities Register', when
Clock) common clock is used. Common Clock operation cannot be fully enabled (through the
Common Clock Configuration field of the Link Control register) unless you observe the
following configuration parameter relationships:
■ CX_NFTS != CX_COMM_NFTS
■ DEFAULT_L0S_EXIT_LATENCY != DEFAULT_COMM_L0S_EXIT_LATENCY
■ DEFAULT_L1_EXIT_LATENCY != DEFAULT_COMM_L1_EXIT_LATENCY
M-PCIe doesn't use this parameter.
Values:
■ Less than 64ns (0x0)
■ 64ns to less than 128ns (0x1)
■ 128ns to less than 256ns (0x2)
■ 256ns to less than 512ns (0x3)
■ 512ns to less than 1us (0x4)
■ 1us to less than 2us (0x5)
■ 2us to 4us (0x6)
■ More than 4us (0x7)
Default Value: [calc_cal_nfts CX_COMM_NFTS ]
Enabled: SLOT_CLK_CONFIG && CX_CPCIE_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_COMM_L0S_EXIT_LATENCY

L1 Exit Latency Default value for the L1 Exit Latency field in the 'Link Capabilities Register'. This
parameter represents a characteristic of the PHY being used. It measures the total
time from when the controller initiates a transition from P1 to P0 until the PHY begins
providing valid receive data to the core. This parameter is for conventional PCIe mode
only.
Values:
■ Less than 1us (0x0)
■ 1us to less than 2us (0x1)
■ 2us to less than 4us (0x2)
■ 4us to less than 8us (0x3)
■ 8us to less than 16us (0x4)
■ 16us to less than 32us (0x5)
■ 32us to 64us (0x6)
■ More than 64us (0x7)
Default Value: 32us to 64us
Enabled: CX_S_CPCIE_MODE || CX_SEL_PHY_MODE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L1_EXIT_LATENCY

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Label Description

L1 Exit Latency (common clk) Default value for the L1 Exit Latency field in the 'Link Capabilities Register', when
common clock is used. It measures the total time from when the controller initiates a
transition from P1 to P0 until the PHY begins providing valid receive data to the core.
Common Clock operation cannot be fully enabled (through the Common Clock
Configuration field of the Link Control register) unless you observe the following
configuration parameter relationships:
■ CX_NFTS != CX_COMM_NFTS
■ DEFAULT_L0S_EXIT_LATENCY != DEFAULT_COMM_L0S_EXIT_LATENCY
■ DEFAULT_L1_EXIT_LATENCY != DEFAULT_COMM_L1_EXIT_LATENCY
This parameter is for Conventional PCIe mode only.
Values:
■ Less than 1us (0x0)
■ 1us to less than 2us (0x1)
■ 2us to less than 4us (0x2)
■ 4us to less than 8us (0x3)
■ 8us to less than 16us (0x4)
■ 16us to less than 32us (0x5)
■ 32us to 64us (0x6)
■ More than 64us (0x7)
Default Value: 32us to 64us
Enabled: CX_CPCIE_ENABLE && SLOT_CLK_CONFIG
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_COMM_L1_EXIT_LATENCY

Use Platform Reference Clock Default value for the Slot Clock Configuration bit in the Link Status register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: SLOT_CLK_CONFIG

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Label Description

Active State Link PM Support Default value for the Active State Link PM Support field in the Link Capabilities
register. When SRIS is supported, L0s is not supported and must not be advertised in
the Capability register. M-PCIe doesn't use the L0s state, and therefore bit[0] of the
Active State Link PM Support field is hardwired to "0" even when you select any value
here.
Values:
■ No ASPM Support (0)
■ L0s Supported (1)
■ L1 Supported (2)
■ L0s and L1 Supported (3)
Default Value: ((CX_SRIS_SUPPORT && !CX_ADM_ADAPTOR_ENABLE)? 2 :
(CX_ADM_ADAPTOR_ENABLE)) ? 0 : 3
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: AS_LINK_PM_SUPT

Endpoint L0s Acceptable Latency Default value for the Endpoint L0s Acceptable Latency field in the 'Device Capabilities
Register'. This should be >= DEFAULT_L0S_EXIT_LATENCY (or
DEFAULT_COMM_L0S_EXIT_LATENCY), and you must ensure that there is sufficient
buffering in your EP for this latency setting. M-PCIe doesn't use this feature.
Values:
■ Less than 64ns (0x0)
■ 64ns to less than 128ns (0x1)
■ 128ns to less than 256ns (0x2)
■ 256ns to less than 512ns (0x3)
■ 512ns to less than 1us (0x4)
■ 1us to less than 2us (0x5)
■ 2us to 4us (0x6)
■ More than 4us (0x7)
Default Value: More than 4us
Enabled: CX_CPCIE_ENABLE && CC_DEVICE_TYPE!=CC_RC &&
CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_EP_L0S_ACCPT_LATENCY

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Label Description

Endpoint L1 Acceptable Latency Default value for the Endpoint L1 Acceptable Latency field in the 'Device Capabilities
Register.' This should be >= DEFAULT_L1_EXIT_LATENCY (or
DEFAULT_COMM_L1_EXIT_LATENCY), and you must ensure that there is sufficient
buffering in your EP for this latency setting. This parameter is for conventional PCIe
mode only.
Values:
■ Less than 1us (0x0)
■ 1us to less than 2us (0x1)
■ 2us to less than 4us (0x2)
■ 4us to less than 8us (0x3)
■ 8us to less than 16us (0x4)
■ 16us to less than 32us (0x5)
■ 32us to 64us (0x6)
■ More than 64us (0x7)
Default Value: More than 64us
Enabled: CX_CPCIE_ENABLE && CC_DEVICE_TYPE!=CC_RC &&
CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_EP_L1_ACCPT_LATENCY

ASPM Optionality Compliance Software uses this bit to determine whether to enable ASPM or whether to run ASPM
compliance tests
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: ASPM_OPTIONALITY_COMPLIANCE

Misc

Port Number Default value for the Port Number field in the Link Capabilities Register.
Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: PORT_NUM

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Label Description

RCB Support Support the ability of configuration software to indicate the Read Completion Boundary
value.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: CC_DEVICE_TYPE==CC_EP || CC_DEVICE_TYPE==CC_DM
Parameter Type: Register Default Setting
Parameter Name: CX_RCB_SUPPORT

Slot Control

Physical Slot Number Default value for the Physical Slot Number field in the Slot Capabilities Register.
Values: 0x0, ..., 0x1fff
Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_PHY_SLOT_NUM

Slot Power Limit Scale Default value for the Slot Power Limit Scale field in the Slot Capabilities Register.
Values:
■ "1.0x" (0x0)
■ "0.1x" (0x1)
■ "0.01x" (0x2)
■ "0.001x" (0x3)
Default Value: "1.0x"
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SET_SLOT_PWR_LIMIT_SCALE

Slot Power Limit Value Default value for the Slot Power Limit Value field in the Slot Capabilities Register.
Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SET_SLOT_PWR_LIMIT_VAL

Slot is Hot-Plug Capable Default value for the Hot-Plug Capable bit in the Slot Capabilities Register. When set
indicates that this slot is capable of supporting
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_HP_CAPABLE

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Label Description

Slot Support Hot-Plug Surprise Default value for the Hot-Plug Surprise bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_HP_SURPRISE

Disable Hot-Plug Software Default value for the No Command Complete Support bit in the Slot Capabilities
Notification Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_NO_CC_SUPPORT

Electromechanical Interlock Default value for the Electromechanical Interlock Present bit in the Slot Capabilities
Implemented Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_EML_PRESENT

Slot Power Indicator Present Default value for the Power Indicator Present bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_PWR_IND_PRESENT

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Label Description

Slot Attention Indicator Present Default value for the Attention Indicator Present bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_ATTEN_IND_PRESENT

Slot MRL Sensor Present Default value for the MRL Sensor Present bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_MRL_SENSOR_PRESENT

Slot Power Controller Present Default value for the Power Controller Present bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_PWR_CTRL_PRESENT

Slot Attention Button Present Default value for the Attention Button Present bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_ATTEN_BUTTON_PRESENT

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Label Description

Surprise Down

Surprise Down Error Reporting Adds optional protocol check capability for Surprise Down Error Reporting.
Enabled Downstream Ports that are Surprise Down Error Reporting Capable (Section 7.8.6 of
the PCIe Specification) must treat this transition from DL_Active to DL_Inactive as a
Surprise Down error, except in the cases presented in (Section 3.2.1 of the PCIe
Specification) where this error detection is blocked.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Feature Setting
Parameter Name: SURPRISE_LINK_DOWN_SUPPORTED

Clock PM

Clock PM Support Default value for the Clock Power Management bit in the Link Capabilities Register.
Values: 0x0, 0x1
Default Value: 0x0
Enabled: (CX_PIPE_VER==0 && CX_L1_SUBSTATES_ENABLE==0) ? 0 : 1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_CLK_PM_CAP

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6.13 Device-Wide PCIe Features and Capabilities Config / PF Extended Capa-


bilities Parameters
Table 6-13 Device-Wide PCIe Features and Capabilities Config / PF Extended Capabilities Parameters

Label Description

PF Extended Capabilities

Advanced Error Reporting (AER) Support PCI Express Advanced Error Reporting. Required if ECRC or ARI are
Enable enabled. If you want to disable this parameter, you must first disable
CX_ECRC_ENABLE and CX_ARI_ENABLE.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: CX_ECRC_ENABLE==0 && CX_ARI_ENABLE==0
Parameter Type: Feature Setting
Parameter Name: AER_ENABLE

Serial Number Capability Include Device Serial Number capability structure.


Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: SERIAL_CAP_ENABLE

+ Device Serial Number (1st DW) Specifies the first 32 bits of the device serial number
Values: 0x0, ..., 0xffffffff
Default Value: 0x0
Enabled: SERIAL_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_SN_DW1

+ Device Serial Number (2nd Specifies the second 32 bits of the device serial number
DW) Values: 0x0, ..., 0xffffffff
Default Value: 0x0
Enabled: SERIAL_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_SN_DW2

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Label Description

Power Budget Capability Include Power Budgeting capability structure


Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: PWR_BUDGET_CAP_ENABLE

+ Power Budget System Default value for the System Allocated bit in the Power Budget Capability register.
Allocated Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: PWR_BUDGET_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_PWR_BUDGET_SYS_ALLOC

Address Translation Services Support PCI-SIG ATS (address translation services) and allow your application to
Support use/set the Address Type (AT) field and No Write (NW) fields of the TLP header. For
more details, see the 'PCI-SIG Address Translation Services (ATS)' section of the
Databook. For generic application<->system address translation, see the 'Address
Translation Services (ATS)' section of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: CC_DTIM_ENABLE
Enabled: (CC_DEVICE_TYPE!=CC_SW) && !CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ATS_ENABLE

+ Page Request Services Values:


Support ■ false (0)
■ true (1)
Default Value: CC_DTIM_ENABLE
Enabled: (CX_ATS_ENABLE==1) && !CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_PRS_ENABLE

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Label Description

Access Control Services Support Support PCI-SIG ACS (Access Control Services) and allow your application to use/set
the access control mechanism. For more details, see the Access Control Services
chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CC_DEVICE_TYPE!=CC_EP) || (CX_SRIOV_ENABLE || (CX_NFUNC >
1) ))
Parameter Type: Feature Setting
Parameter Name: CX_ACS_ENABLE

+ ACS Function Groups Support Values:


■ false (0)
■ true (1)
Default Value: CX_ACS_ENABLE && CX_SRIOV_ENABLE
Enabled: CX_ACS_ENABLE && CX_ARI_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_FUNC_GRP

Latency Tolerance Reporting Support the Latency Tolerance Reporting Mechanism. For more details see the
(LTR) "Messages" section in the "Controller Operations" chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting.
Parameter Name: CX_LTR_M_ENABLE

TLP Processing Hints Support TLP Processing Hints. For more details, see the TLP Processing Hints
section in the Core Operations chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_SW
Parameter Type: Feature Setting.
Parameter Name: CX_TPH_ENABLE

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Label Description

Dynamic Power Allocation (DPA) Function:Support the Dynamic Power Allocation (DPA) capability.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ( (CC_DEVICE_TYPE!=CC_RC) && (CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Feature Setting
Parameter Name: CX_DPA_ENABLE

+ DPA Maximum Substate Function:The default value of the maximum substate number which is the total
number of supported substates minus one. A value of 0 indicates support for one
substate. This value represents the maximum configurable value of the Substate_Max
field in the DPA Capability register. A write to this register field through the DBI will not
be able to alter this to a larger value.
Values: 0x0, ..., 0x1f
Default Value: 0x1f
Enabled: ((CC_DEVICE_TYPE!=CC_RC) && (CC_DEVICE_TYPE!=CC_SW) &&
CX_DPA_ENABLE)
Parameter Type: Feature Setting
Parameter Name: DEFAULT_DPA_SUBSTATE_MAX

ARI Forwarding When set, Alternate Routing ID (ARI) Forwarding is supported and the ARI Forwarding
Supported field in the PCIe Device Capabilities 2 Register is set.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Feature Setting
Parameter Name: CX_ARI_FWD_CAP

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Device-Wide PCIe Features and Capabilities Config / VC Capability Parameters PCI Express SW Controller Databook

6.14 Device-Wide PCIe Features and Capabilities Config / VC Capability Param-


eters
Table 6-14 Device-Wide PCIe Features and Capabilities Config / VC Capability Parameters

Label Description

Virtual Channel Capability

Number of Virtual Channels The number of Virtual Channels (VCs) to be supported. The controller supports up to
eight VCs.
Values: 1, 2, 3, 4, 5, 6, 7, 8
Default Value: 1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_NVC

Virtual Channel Support Support PCIe virtual channel Capability (required if there are multiple VCs).
Values:
■ false (0x0)
■ true (0x1)
Default Value: (CX_NVC==1) ? 0 : 1
Enabled: ((CX_NVC==1))
Parameter Type: Feature Setting
Parameter Name: VC_ENABLE

VC Arbitration Capability Default value for the VC Arbitration Capability field in the Port VC Capability Register
2.
Values: 0x0, ..., 0xf
Default Value: 0x1
Enabled: ((VC_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_VC_ARB_32

Low Priority Extended VC Count Default value for the Low Priority Extended VC Count field in the Port VC Capability
Register 1.
Values: 0x0, ..., CX_NVC
Default Value: 0x0
Enabled: (((VC_ENABLE==1)))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_LOW_PRI_EXT_VC_CNT

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / Slot ID Capability Parameters

6.15 Device-Wide PCIe Features and Capabilities Config / Slot ID Capability


Parameters
Table 6-15 Device-Wide PCIe Features and Capabilities Config / Slot ID Capability Parameters

Label Description

Slot ID Capability

Slot ID Capability Slot ID Capability structure enable


Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE==CC_SW
Parameter Type: Feature Setting
Parameter Name: SLOT_CAP_ENABLE

Slot First In Chassis Default value for the "First In Chassis" field in the Slot Numbering Capabilities
Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: ((SLOT_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: FIRST_IN_CHASSIS

Slot Number Default value for the "Add-In Card Slots Provided" field in the Slot Numbering
Capabilities Register.
Values: 0x0, ..., 0x1f
Default Value: 0x0
Enabled: SLOT_CAP_ENABLE==1
Parameter Name: SLOT_NUM

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Device-Wide PCIe Features and Capabilities Config / AtomicOp Support Options Parameters PCI Express SW Controller Databook

6.16 Device-Wide PCIe Features and Capabilities Config / AtomicOp Support


Options Parameters
Table 6-16 Device-Wide PCIe Features and Capabilities Config / AtomicOp Support Options Parameters

Label Description

AtomicOp Support Options

Atomic Ops Support Atomic Ops.


Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: !AMBA_POPULATED && !CC_DMA_ENABLE
Parameter Type: Feature Setting.
Parameter Name: CX_ATOMIC_ENABLE

AtomicOp Routing Supported Support routing of Atomic Ops. Applicable to DSP.


Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_ATOMIC_ENABLE && (CC_DEVICE_TYPE!=CC_EP)
Enabled: !AMBA_POPULATED && (CC_DEVICE_TYPE!=CC_EP) &&
CX_ATOMIC_ENABLE
Parameter Type: Feature Setting.
Parameter Name: CX_ATOMIC_ROUTING_EN

32-bit AtomicOp Completer Support Completion of Atomic Ops with a 32-bit operand size.
Support Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_ATOMIC_ENABLE
Enabled: !AMBA_POPULATED && CX_ATOMIC_ENABLE
Parameter Type: Feature Setting.
Parameter Name: CX_ATOMIC_32_CPL_EN

64-bit AtomicOp Completer Support Completion of Atomic Ops with a 64-bit operand size.
Support Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_ATOMIC_ENABLE
Enabled: !AMBA_POPULATED && CX_ATOMIC_ENABLE
Parameter Type: Feature Setting.
Parameter Name: CX_ATOMIC_64_CPL_EN

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / AtomicOp Support Options

Label Description

128-bit CAS Completer Support Support Completion of Compare and Swap Atomic Ops with a 128-bit operand size.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: !AMBA_POPULATED && CX_ATOMIC_ENABLE
Parameter Type: Feature Setting.
Parameter Name: CX_ATOMIC_128_CAS_EN

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Device-Wide PCIe Features and Capabilities Config / Readiness Support Options Parameters PCI Express SW Controller Databook

6.17 Device-Wide PCIe Features and Capabilities Config / Readiness Support


Options Parameters
Table 6-17 Device-Wide PCIe Features and Capabilities Config / Readiness Support Options Parameters

Label Description

General Options

Support Immediate Readiness Enable Immediate Readiness support in the core. When you set the Immediate
Readiness bit in the PCI header Status Register, the function is configuration-ready.
Software is exempt from all requirements to delay configuration accesses following any
type of reset or exit from low-power states. The function will always respond to a valid
configuration request targeting the function with a completion indicating successful
completion status, and not CRS. For more details, see Readiness Notifications in the
Controller Operations chapter of the Databook.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RN_IMM_EN

RTR Capability Supported Enable Readiness Time Reporting support in the core. RTR provides an optional
mechanism for describing the time required for a device or function to become
configuration-ready. Software is permitted to issue requests to the device or function
(following any type of reset or exit from low-power states) after waiting for the time
advertised in this capability and need not wait for the (longer) times required
elsewhere. The function will then respond to a valid configuration request targeting the
function with a completion indicating successful completion status, and not CRS. For
more details, see Readiness Notifications in the Controller Operations chapter of the
Databook.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RN_RTR_EN

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / Readiness Support Options

Label Description

FRS/DRS Options

Function Readiness Status (FRS) Enable FRS support in the core. FRS provides an optional mechanism for messaging
Support the host software when a function has become configuration-ready. The controller
autonomously sends a Vendor-Defined Type 1 Message (VDM) with no payload
following reset or exit from low-power states. Software is permitted to issue requests to
the function (following any type of reset or exit from low-power states) after receiving
an FRS message from this function and need not wait for the (longer) times required
elsewhere. The function will then respond to a valid configuration request targeting the
function with a completion indicating successful completion status, and not CRS. For
more details, see Readiness Notifications in the Controller Operations chapter of the
Databook.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RN_FRS_SUPPORTED

Device Readiness Status (DRS) Enable DRS support in the core. DRS provides an optional mechanism for messaging
Support the host software when a device has become configuration-ready. The controller
autonomously sends a Vendor-Defined Type 1 Message (VDM) with no payload
following reset or exit from low-power states. Software is permitted to issue requests to
the device (following any type of reset or exit from low-power states) after receiving an
DRS message from this device and need not wait for the (longer) times required
elsewhere. The device will then respond to a valid configuration request targeting the
device with a completion indicating successful completion status, and not CRS. For
more details, see Readiness Notifications in the Controller Operations chapter of the
Databook.
Values: 0, 1
Default Value: CX_RN_FRS_SUPPORTED==1
Enabled: CX_RN_FRS_SUPPORTED==0
Parameter Type: Feature Setting
Parameter Name: CX_RN_DRS_SUPPORTED

FRS Queue Max Depth Sets the maximum FRS queue depth in root ports (Must be at least 4 for greater than
128 bit Datapath Width).
Values: 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800
Default Value: 0x8
Enabled: (CX_RN_FRS_SUPPORTED==1 && (CC_DEVICE_TYPE==CC_RC ||
CC_DEVICE_TYPE==CC_DM))
Parameter Type: Performance Setting
Parameter Name: CX_RN_FRS_QUEUE_MAX_DEPTH

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Label Description

FRS Queue Interrupt Message Default for the FRS_INT_MESSAGE_NUMBER field in the FRSQ_CAP_OFF register.
Number Values: 0, ..., 31
Default Value: 0
Enabled: (CX_RN_FRS_SUPPORTED==1 && (CC_DEVICE_TYPE==CC_RC ||
CC_DEVICE_TYPE==CC_DM))
Parameter Type: Register Default Setting
Parameter Name: CX_RN_FRS_INT_MSG_NUM

FRS Queue Interrupt Enable Default for the FRS_INTERRUPT_ENABLE field in the
FRSQ_CONTROL_FRSQ_STATUS_OFF register.
Values: 0, 1
Default Value: 0
Enabled: (CX_RN_FRS_SUPPORTED==1 && (CC_DEVICE_TYPE==CC_RC ||
CC_DEVICE_TYPE==CC_DM))
Parameter Type: Register Default Setting
Parameter Name: CX_RN_FRS_INT_ENABLE

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / Lightweight Notification

6.18 Device-Wide PCIe Features and Capabilities Config / Lightweight Notifica-


tion Support Options Parameters
Table 6-18 Device-Wide PCIe Features and Capabilities Config / Lightweight Notification Support Options
Parameters

Label Description

Lightweight Notification Support Options

Lightweight Notification Enable When enabled, the controller supports the Lightweight Notification capability.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (CC_DEVICE_TYPE!=CC_SW && (AMBA_INTERFACE!=1) &&
CX_RADMQ_MODE==2)
Parameter Name: CX_LN_ENABLE

Lightweight Notification Lightweight Notification System Cache Line Size (RC).


Completer Cacheline Size Values: 0, ..., 2
Default Value: 0
Enabled: CX_LN_ENABLE && (CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE
== CC_DM)
Parameter Name: CX_LN_COMPLETER_CACHELINE_SIZE

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Device-Wide PCIe Features and Capabilities Config / Other Optional PCIe Features Parameters PCI Express SW Controller Databook

6.19 Device-Wide PCIe Features and Capabilities Config / Other Optional PCIe
Features Parameters
Table 6-19 Device-Wide PCIe Features and Capabilities Config / Other Optional PCIe Features Parameters

Label Description

Other Optional PCIe Features

ID Based Ordering Support ID Based Ordering (IDO). The controller does not perform any additional
ordering when ID-based ordering (IDO) is enabled. Your application is expected to do
any IDO.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (CC_DEVICE_TYPE!=CC_SW) && !AHB_POPULATED
Parameter Type: Feature Setting.
Parameter Name: CX_IDO_ENABLE

Completion Timeout Ranges Support Completion Timeout Ranges. For more details, see 'Completion Timeout
Enable Range' section in the 'Controller Operations' chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Feature Setting
Parameter Name: CX_CPL_TO_RANGES_ENABLE

Vital Product Data (VPD) Include Vital Product Data (VPD) capability structure
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: VPD_CAP_ENABLE

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Label Description

Optimized Buffer Flush/Fill Type Indicates if the device supports Optimized Buffer Flush/Fill (OBFF) using the WAKE#
Supported signal, messages or both.
Values:
■ Not Supported (0)
■ OBFF Messages Only (1)
■ WAKE# Signalling Only (2)
■ WAKE# Signalling and OBFF Messages (3)
Default Value: Not Supported
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_OBFF_SUPPORT

Enable Crosslink Support Enables support for the controller to negotiate a crosslink, with a switch from EP to RC
and RC to EP. When a port negotiates a crosslink connection, the port changes its
behavior from a downstream port to an upstream port and visa versa. Crosslink is
supported only in DM and SW cores because these products support both upstream
and downstream ports. For more details, see Databook. M-PCIe doesn't support this
feature.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (CX_CPCIE_ENABLE && (CC_DEVICE_TYPE==CC_DM ||
CC_DEVICE_TYPE==CC_SW))
Parameter Type: Feature Setting
Parameter Name: CX_CROSSLINK_ENABLE

Peer-to-peer Support Support peer-to-peer transactions in RC. For more details, see 'Peer-to-Peer Support
(P2P)' in the Databook.
Values: 0, 1
Default Value: 0
Enabled: ((CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_DM) &&
(AMBA_INTERFACE==0) && (CC_DMA_ENABLE==0))
Parameter Type: Feature Setting
Parameter Name: CX_P2P_ENABLE

SRIS Support When enabled, the controller implements logic for Separate Reference Clocks with
Independent SSC (SRIS). Gen5 port must support SRIS/non-SRIS mode selection
mechanism.
Values:
■ false (0)
■ true (1)
Default Value: CX_MAX_PCIE_SPEED >= 5
Enabled: (!(CX_PCIE_MODE == SINGLE_MPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_SRIS_SUPPORT

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Device-Wide PCIe Features and Capabilities Config / SR-IOV Related Features Parameters PCI Express SW Controller Databook

6.20 Device-Wide PCIe Features and Capabilities Config / SR-IOV Related


Features Parameters
Table 6-20 Device-Wide PCIe Features and Capabilities Config / SR-IOV Related Features Parameters

Label Description

SR-IOV Related Features

Support SR-IOV SR-IOV Capability enable. For more details, see the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CC_DEVICE_TYPE==CC_EP || CC_DEVICE_TYPE==CC_DM))
Parameter Type: Feature Setting
Parameter Name: CX_SRIOV_ENABLE

Function Level Reset Support Enables controller support for Function Level Reset (FLR). For more details, see the
Databook.
Values:
■ false (0)
■ true (1)
Default Value: CX_SRIOV_ENABLE
Enabled: ((CC_DEVICE_TYPE==CC_EP || CC_DEVICE_TYPE==CC_DM) &&
!CX_SRIOV_ENABLE)
Parameter Type: Feature Setting
Parameter Name: CX_FLR_ENABLE

Number of Virtual Functions. Read-only parameter that specifies the total number of virtual functions supported by
the controller. When CX_EXTENSIBLE_VFUNC=1, it is the total of both internal VFs
and external VFs.
Values: 2, ..., SNPS_RSVDPARAM_24
Default Value: Sum(CX_MAX_VF_i, i=0..CX_NFUNC-1)
Enabled: false
Parameter Name: CX_NVFUNC

External Virtual Function Enables the Extensible Virtual function which allows you to implement VFs capability
Registers registers in your application logic. For more details, see the SRIOV section in the
Controller Operations chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_EXTENSIBLE_VFUNC

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / SR-IOV Related Features

Label Description

Number of (Internal) Virtual The total number of VF registers implemented internally in the controller.
Functions. ■ Normally, this is a read-only parameter that specifies the total number of virtual
functions supported by the controller.
■ When CX_EXTENSIBLE_VFUNC=1, it is a writable parameter that specifies the
total number of virtual functions implemented internally in the controller. Internal
VFs are mapped from the lowest function number; that is, PF0_VF1.
For more details, see the SR-IOV section in the Controller Operations chapter of the
Databook.
Values: 0, ..., SNPS_RSVDPARAM_23
Default Value: CX_EXTENSIBLE_VFUNC ? 0 : CX_NVFUNC
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_INTERNAL_NVFUNC

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Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities Parameters PCI Express SW Controller Databook

6.21 Device-Wide PCIe Features and Capabilities Config / VF Extended Capa-


bilities Parameters
Table 6-21 Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities Parameters

Label Description

VF Capabilities/Features

Header Log Shared amongst VFs Header Log Sharing amongst VF of a PF


of a PF Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_AER_EN==1 && !CX_EXTENSIBLE_VFUNC
Parameter Type: Feature Setting.
Parameter Name: VF_HDR_LOG_SHARED

VF Shared Header Log Depth per VF Shared Header Log Depth


each PF Values: 0x2, 0x4, 0x8, 0x10, 0x20
Default Value: 0x2
Enabled: VF_HDR_LOG_SHARED
Parameter Type: Feature Setting.
Parameter Name: VF_HDR_LOG_SHARED_DEPTH

VF Individual Header Log Depth VF Header Log Depth


Values: 0x1, 0x2, 0x4
Default Value: 0x1
Enabled: VF_HDR_LOG_SHARED==0 && VF_AER_EN
Parameter Type: Feature Setting.
Parameter Name: VF_HDR_LOG_DEPTH

Virtual Function Dependency Enables support for VF dependency link. Valid only if CX_NFUNC >1.
Link Support Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && (CX_NFUNC > 1)
Parameter Type: Feature Setting
Parameter Name: CX_VF_DEPENDENCY_LINK_SUPP

VF Power Management Enable Power Management Capability for virtual functions. Not available if Extensible
Capability Virtual Function (CX_EXTENSIBLE_VFUNC) is enabled.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && !CX_EXTENSIBLE_VFUNC
Parameter Type: Feature Setting
Parameter Name: VF_PM_CAP_ENABLE

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Label Description

VF AER Capability Enable AER Capability for virtual functions.


Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && AER_ENABLE && INTERNAL_VF_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_AER_ENABLE

VF TPH Capability Include VF TPH Capability structure


Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_TPH_ENABLE && INTERNAL_VF_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_TPH_ENABLE_VALUE

VF ATS Capability Include VF ATS Capability structure


Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_ATS_ENABLE && INTERNAL_VF_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_ATS_ENABLE

VF TPH Steering Tag Table Size TLP Processing Hints Steering Tag Table Size for virtual functions.
■ All Virtual functions have the same table size set by this parameter.
■ Software reads this field to determine the ST Table Size N, which is encoded as
N-1. For example, a returned value of 00000000011 indicates a table size of 4.
■ There is an upper limit of 64 entries when the ST Table is located in the TPH
Requester Capability structure.
Values: 1, ..., 2048
Default Value: 1
Enabled: (VF_TPH_ENABLE && (TPH_ST_TABLE_LOC_0 != 0))
Parameter Type: Feature Setting
Parameter Name: VF_TPH_ST_TABLE_SIZE

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Label Description

VF TPH Steering Tag Table Size TLP Processing Hints Steering Tag Table Size for external virtual functions.
■ All Virtual functions have the same table size set by this parameter.
■ Software reads this field to determine the ST Table Size N, which is encoded as
N-1. For example, a returned value of 00000000011 indicates a table size of 4.
■ There is an upper limit of 64 entries when the ST Table is located in the TPH
Requester Capability structure.
Values: 1, ..., 2048
Default Value: 1
Enabled: (EXT_VF_TPH_ENABLE && (TPH_ST_TABLE_LOC_0 != 0))
Parameter Type: Feature Setting
Parameter Name: EXT_VF_TPH_ST_TABLE_SIZE

VF ACS Capability (Device-Wide) Enable Access Control Services for VFs.


Values: 0, 1
Default Value: CX_ACS_ENABLE==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Enabled: CX_ACS_ENABLE==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: VF_ACS_ENABLE

VF ACS Function Groups ACS Function Group Support for VFs


(Device-Wide) Values: 0, 1
Default Value: VF_ACS_ENABLE==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1 && CX_ACS_FUNC_GRP==1
Enabled: VF_ACS_ENABLE==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1 && CX_ACS_FUNC_GRP==1
Parameter Type: Feature Setting
Parameter Name: VF_ACS_FUNC_GRP

VF MSI/MSI-X Capabilities

VF MSI Capability Enable MSI Capability for virtual functions.


Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && INTERNAL_VF_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MSI_CAP_ENABLE

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities

Label Description

VF MSI-X Capability Enable MSI-X Capability for virtual functions.


Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_SRIOV_ENABLE && (CX_INTERNAL_NVFUNC != 0)
Enabled: CX_SRIOV_ENABLE && INTERNAL_VF_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MSIX_CAP_ENABLE

VF MSI-X Table BIR (PF#i) Default value for the Table BAR Indicator Register (BIR) field in the VF MSI-X Table
(for n = 0; n <= CX_NFUNC-1) Offset and BIR Register. Indicates which BAR is used to map the MSI-X Table into
memory space.
Values:
■ BAR0 (0x0)
■ BAR1 (0x1)
■ BAR2 (0x2)
■ BAR3 (0x3)
■ BAR4 (0x4)
■ BAR5 (0x5)
Default Value: BAR0
Enabled: VF_MSIX_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_MSIX_TABLE_BIR_n

VF MSI-X Table Offset (PF#i) Default value for the Table Offset field in the VF MSI-X Table Offset and BIR Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1fffffff
Default Value: 0x0
Enabled: ((VF_MSIX_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: VF_MSIX_TABLE_OFFSET_n

VF MSI-X PBA BIR (PF#i) Default value for the Pending Bit Array (PBA) BAR Indicator Register (BIR) field in the
(for n = 0; n <= CX_NFUNC-1) VF MSI-X PBA Offset and BIR Register. Indicates which BAR is used to map the
MSI-X PBA into memory space.
Values:
■ BAR0 (0x0)
■ BAR1 (0x1)
■ BAR2 (0x2)
■ BAR3 (0x3)
■ BAR4 (0x4)
■ BAR5 (0x5)
Default Value: BAR0
Enabled: VF_MSIX_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_MSIX_PBA_BIR_n

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Label Description

VF MSI-X PBA Offset (PF#i) Default value for the PBA Offset field in the VF MSI-X PBA Offset and BIR Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1fffffff
Default Value: 0x0
Enabled: ((VF_MSIX_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: VF_MSIX_PBA_OFFSET_n

VF Readiness Capabilities

VF RTR Capability (Device-Wide) Enable Readiness Time Reporting for VF's


Values: 0, 1
Default Value: CX_RN_RTR_EN==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Enabled: CX_RN_RTR_EN==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: VF_RTR_ENABLE

VF Immediate Readiness Enable Immediate Readiness support for VFs in the core. When you set the
Support Immediate Readiness bit in the PCI header Status Register, the function is
configuration-ready. Software is exempt from all requirements to delay configuration
accesses following any type of reset or exit from low-power states. The function will
always respond to a valid configuration request targeting the function with a
completion indicating successful completion status, and not CRS. For more details,
see Readiness Notifications in the Controller Operations chapter of the Databook.
Values: 0, 1
Default Value: CX_RN_IMM_EN==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Enabled: CX_RN_IMM_EN==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: VF_IMM_ENABLE

VF Lightweight Notification Capabilities

VF Lightweight Notification When enabled, controller supports Lightweight Notification Capability for VFs.
Enable Values: 0, 1
Default Value: CX_LN_ENABLE==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Enabled: CX_LN_ENABLE==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Parameter Name: VF_LN_ENABLE

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities

Label Description

VF Features

VF Stride Always 1 Enable logic optimization when you never use a VF stride greater than one. For more
details, see the Single Root I/O Virtualization (SR-IOV) section in the Databook. You
should enable this parameter when possible to save gates and ease timing closure.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE
Parameter Type: Performance Setting
Parameter Name: CX_VF_STRIDE_ALWAYS_ONE

Programmable VF allocation Enable programmable allocation of VFs to PFs. For more details, see the
Programmable Virtual Function Allocation section in the Databook. You should disable
this parameter when you do not need it, to save gates and ease timing closure.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: DYNAMIC_VF_ENABLE

External VF Capabilities (Extensible IOV only)

External VF RTR Capability Readiness Time Reporting Capability external for virtual functions.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC && CX_RN_RTR_EN
Parameter Type: Feature Setting
Parameter Name: EXT_VF_RTR_ENABLE

External VF ACS Capability Enable Access Control Services for external virtual functions. This parameter cannot
be enabled in this version.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: EXT_VF_ACS_ENABLE

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Label Description

External VF Lightweight Lightweight Notification Capability for external virtual functions.


Notification Capability Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC && CX_LN_ENABLE
Parameter Type: Feature Setting
Parameter Name: EXT_VF_LN_ENABLE

External VF Immediate Readiness Time Reporting Capability for external virtual functions.
Readiness Capability Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC && CX_RN_IMM_EN
Parameter Type: Feature Setting
Parameter Name: EXT_VF_IMM_ENABLE

External VF MSI Capability MSI Capability for external virtual functions.


Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC
Parameter Type: Feature Setting
Parameter Name: EXT_VF_MSI_CAP_ENABLE

External VF MSI-X Capability MSIX Capability for external virtual functions.


Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC
Enabled: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC
Parameter Type: Feature Setting
Parameter Name: EXT_VF_MSIX_CAP_ENABLE

External VF AER Capability AER Capability for external virtual functions.


Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC && AER_ENABLE
Parameter Type: Feature Setting
Parameter Name: EXT_VF_AER_ENABLE

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities

Label Description

External VF TPH Capability TPH Capability for external virtual functions.


Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC &&
CX_TPH_ENABLE
Parameter Type: Feature Setting
Parameter Name: EXT_VF_TPH_ENABLE_VALUE

External VF ATS Capability ATS Capability for external virtual functions.


Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC &&
CX_ATS_ENABLE
Parameter Type: Feature Setting
Parameter Name: EXT_VF_ATS_ENABLE

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Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability Parameters PCI Express SW Controller Databook

6.22 Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM


Capability Parameters
Table 6-22 Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability Parameters

Label Description

L1 Substates Capability

L1 Substates Support Enable support for L1 substates. For more details, see the Power Management section
of the Databook. M-PCIe doesn't support this feature.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE ))
Parameter Type: Feature Setting
Parameter Name: CX_L1_SUBSTATES_ENABLE

Configure Other Register Select here if you want to configure the defaults for the L1 substates capability register.
Defaults An extra window will appear under this page. To access it, click the plus/minus symbol
in the hierarchy view on the left panel. This is optional but not usually recommended.
You can also change these register defaults using the DBI before (or after) the link
comes up.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_L1_SUBSTATES_DEFAULTS_VISIBLE

L1 Substates/L1.CPM Transition Options

L1 Substate signaling This is read-only parameter to indicate whether the core uses mac_phy_powerdown
signal for L1-Substate transition or uses legacy side-band interface signals. You can
change the setting by CX_PIPE_VER parameter located in "Basic Feature Config".
Values:
■ Side band (0)
■ PowerDown (1)
Default Value: CX_PIPE_VER>=1
Enabled: SNPS_RSVDPARAM_25
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_SUPPORT

Bypass Asynchronous Power Bypass the handshake between phystatus and AsyncPowerChangeAck in P1.1 or
Change Handshake P1.2 powerdown state when your PHY vendor does not support it.
Values: 0, 1
Default Value: 0
Enabled: CX_PIPE43_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_ASYNC_HS_BYPASS

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM

Label Description

P1.CPM Encoding Powerdown state encoding on the mac_phy_powerdown[3:0] output for P1.CPM.
Contact your PHY vendor for the value that you should use.
Values: 0x0, ..., 0xf
Default Value: 0x4
Enabled: CX_PIPE43_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P1CPM_ENCODING

P1.1 Encoding Powerdown state encoding on the mac_phy_powerdown[3:0] output for P1.1. Contact
your PHY vendor for the value that you should use.
Values: 0x4, ..., 0xf
Default Value: 0x5
Enabled: CX_PIPE43_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P1_1_ENCODING

P1.2 Encoding Powerdown state encoding on the mac_phy_powerdown[3:0] output for P1.2. Contact
your PHY vendor for the value that you should use.
Values: 0x4, ..., 0xf
Default Value: 0x6
Enabled: CX_PIPE43_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P1_2_ENCODING

P1.CPM Entry Sequence Specifies P1.CPM Entry sequence. Contact your PHY vendor for the sequence that
you should use.
■ 0: P0 -> P1 -> P1.CPM
■ 1: P0 -> P1.CPM
Values: 0, 1
Default Value: 0
Enabled: CX_PIPE43_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P0_P1CPM

P1.1 and P1.2 Exit Sequence Specifies P1.1 and P1.2 Exit sequence. Contact your PHY vendor for the sequence
that you should use.
■ 0: P1.1(P1.2) -> P1
■ 1: P1.1(P1.2) -> P1.CPM -> P1
Values: 0, 1
Default Value: 0
Enabled: CX_PIPE43_SUPPORT && CX_L1_SUBSTATES_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P1CPM_P1

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Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability / L1 Substates Capability Register Defaults Parameters PCI

6.23 Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM


Capability / L1 Substates Capability Register Defaults Parameters
Table 6-23 Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability / L1
Substates Capability Register Defaults Parameters

Label Description

L1 Substates Capability Register Defaults

Default Aux Clock Frequency The frequency (in MHz) of the aux_clk that is supplied by the application during low
[MHz] power states. This parameter is used to set the default value of the Auxiliary Clock
Frequency Control Port Logic Register
Values: 1, ..., 1000
Default Value: 10
Enabled: CX_L1_SUBSTATES_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_AUX_CLK_FREQ

Default Port Common Mode Default value of the Port Common_Mode_Restore_Time field in the L1 Substates
Restore Time [us] Capability register. For downstream ports, it is also the default value of the Common
Mode Restore Time field in the L1 Substates Control 1 register.
Values: 0, ..., 255
Default Value: 10
Enabled: CX_L1_SUBSTATES_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L1SUB_PORT_T_COMM_MODE

Default Port Power ON Time Default value of the Port T_POWER_ON Scale field in the L1 Substates Capability
Scale register.
Values:
■ 2 us (0x0)
■ 10 us (0x1)
■ 100 us (0x2)
Default Value: 2 us
Enabled: CX_L1_SUBSTATES_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L1SUB_PORT_T_POWER_ON_SCALE

Default Port Power ON Time Default value of the Port T_POWER_ON Value field in the L1 Substates Capability
Value register.
Values: 0, ..., 31
Default Value: 5
Enabled: CX_L1_SUBSTATES_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L1SUB_PORT_T_POWER_ON_VALUE

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support

6.24 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support
Parameters
Table 6-24 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support Parameters

Label Description

TLP Prefix Support

Number of Prefixes The number of TLP Prefixes that the controller supports. When CX_NPRFX is greater
than zero, then each function in the PCIe controller supports the extended FMT field in
TLP prefixes and headers. When CX_NPRFX is zero, then the extended FMT field is
not supported. Range: 0-8 (excluding 1,2,3 as a switch support that supports prefixes
must support up to four End-End TLP Prefixes).
Values: 0, 1, 2, 3, 4, 5, 6, 7
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting.
Parameter Name: CX_NPRFX

Support PASID Support the PASID capability for untranslated addresses.


Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (CX_TLP_PREFIX_ENABLE && (CC_DEVICE_TYPE!=CC_RC) &&
(CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Feature Setting.
Parameter Name: CX_PASID_ENABLE

Support PRG PASID Prefix Any PRG Response Message with PASID capability for untranslated addresses, is
required to have a PASID TLP Prefix.
Values: 0, 1
Default Value: 0
Enabled: CX_PASID_ENABLE
Parameter Type: Feature Setting.
Parameter Name: CX_PRG_PASID_REQUIRED

Configure Other Register Select here if you want to configure the defaults for the PASID capability register. An
Defaults extra window will appear under this page. To access it, click the plus/minus symbol in
the hierarchy view on the left panel. This is optional but not usually recommended. You
can also change these register defaults using the DBI before (or after) the link comes
up.
Values: 0, 1
Default Value: 0
Enabled: (CX_PASID_ENABLE && (CC_DEVICE_TYPE!=CC_RC) &&
(CC_DEVICE_TYPE!=CC_SW))
Parameter Name: CX_PASID_DEFAULTS_VISIBLE

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6.25 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support /
PASID Capability Register Defaults Parameters
Table 6-25 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support / PASID Capability
Register Defaults Parameters

Label Description

PASID Capability Register Defaults

Default Max PASID Width The default value for the width of the PASID field supported by the endpoint.
■ n indicates support for PASID values 0 through (2^n)-1.
■ 0 indicates support for a single PASID.
■ 20 indicates support for all PASID values (20 bits).
Values: 0, ..., 20
Default Value: 0
Enabled: (CX_PASID_ENABLE && (CC_DEVICE_TYPE!=CC_RC) &&
(CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_MAX_PASID_WDTH

Default Privileged Mode Support The default value for Privileged Mode Supported.
■ 1: Endpoint supports operating in Privileged and Non-Privileged modes, and
supports sending requests that have the Privileged Mode Requested bit Set.
■ 0: Endpoint will never Set the Privileged Mode Requested bit.
Values: 0, 1
Default Value: 1
Enabled: (CX_PASID_ENABLE && (CC_DEVICE_TYPE!=CC_RC) &&
(CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_PRVLGD_MODE_SPPRT

Default Execute Permission The default value for Execute Permission Supported.
Support ■ 1: Endpoint supports sending TLPs that have the Execute Requested bit Set.
■ 0: Endpoint will never Set the Execute Requested bit.
Values: 0, 1
Default Value: 1
Enabled: (CX_PASID_ENABLE && (CC_DEVICE_TYPE!=CC_RC) &&
(CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_EXCT_PRMSSN_SPPRT

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / Precision Time Management

6.26 Device-Wide PCIe Features and Capabilities Config / Precision Time


Management Support Options Parameters
Table 6-26 Device-Wide PCIe Features and Capabilities Config / Precision Time Management Support Options
Parameters

Label Description

Precision Time Management Support Options

Precision Time Measurement When enabled, the core supports the Precision Time Measurement capability.
Enable Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CX_PCIE_MODE == SINGLE_CPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_PTM_ENABLE

PTM External Master Time When enabled, the PTM local clock may be updated via an External Master Time
input.
Values:
■ false (0)
■ true (1)
Default Value: (CC_DEVICE_TYPE==CC_EP) ? 0 : 1
Enabled: CX_PTM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_PTM_EXTERNAL_MASTER_TIME

PTM Local Clock Granularity Set Local Clock Granularity for PTM.
Values: 0x0, ..., 0xff
Default Value: (CX_PTM_ROOT_CAPABLE==0) ? 0 : (CX_FREQ == FREQ_500) ?
2: (CX_FREQ == FREQ_250) ? 4 : (CX_FREQ == FREQ_125) ? 8 : (CX_FREQ ==
FREQ_62_5) ? 16 : 32
Enabled: CX_PTM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_PTM_LOCAL_CLK_GRAN

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Device-Wide PCIe Features and Capabilities Config / Secondary PCIe Extended Capability Parameters PCI Express SW Controller Databook

6.27 Device-Wide PCIe Features and Capabilities Config / Secondary PCIe


Extended Capability Parameters
Table 6-27 Device-Wide PCIe Features and Capabilities Config / Secondary PCIe Extended Capability
Parameters

Label Description

Gen3 EQ Control Register

USP 8G Rx Preset Hint Upstream Port 8.0 GT/s Receiver Preset Hint
Values: 0x0, ..., 0x7
Default Value: 0x7
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_USP_RX_PRESET_HINT0

USP 8G Tx Preset Upstream Port 8.0 GT/s Transmitter Preset


Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_USP_TX_PRESET0

DSP 8G Rx Preset Hint Downstream Port 8.0 GT/s Receiver Preset Hint
Values: 0x0, ..., 0x7
Default Value: 0x7
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_DSP_RX_PRESET_HINT0

DSP 8G Tx Preset Downstream Port 8.0 GT/s Transmitter Preset


Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_DSP_TX_PRESET0

Gen4 EQ Control Register

USP 16G Rx Preset Hint Upstream Port 16.0 GT/s Receiver Preset Hint
Values: 0x0, ..., 0x7
Default Value: 0x7
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_USP_16G_RX_PRESET_HINT0

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / Secondary PCIe Extended

Label Description

USP 16G Tx Preset Upstream Port 16.0 GT/s Transmitter Preset


Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_USP_16G_TX_PRESET0

DSP 16G Rx Preset Hint Downstream Port 16.0 GT/s Receiver Preset Hint
Values: 0x0, ..., 0x7
Default Value: 0x7
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_DSP_16G_RX_PRESET_HINT0

DSP 16G Tx Preset Downstream Port 16.0 GT/s Transmitter Preset


Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_DSP_16G_TX_PRESET0

Gen5 EQ Control Register

USP 32G Tx Preset Upstream Port 32.0 GT/s Transmitter Preset


Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_USP_32G_TX_PRESET0

DSP 32G Tx Preset Downstream Port 32.0 GT/s Transmitter Preset


Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_DSP_32G_TX_PRESET0

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Device-Wide PCIe Features and Capabilities Config / CCIX Transport DVSEC Parameters PCI Express SW Controller Databook

6.28 Device-Wide PCIe Features and Capabilities Config / CCIX Transport


DVSEC Parameters
Table 6-28 Device-Wide PCIe Features and Capabilities Config / CCIX Transport DVSEC Parameters

Label Description

CCIX Transport DVSEC

USP 20GT/s Transmitter Preset Upstream Port 20GT/s Transmitter Preset


Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_ESM_USP_TX_PRESET_20G0

USP 25GT/s Transmitter Preset Upstream Port 25GT/s Transmitter Preset


Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_ESM_USP_TX_PRESET_25G0

DSP 20GT/s Transmitter Preset Downstream Port 20GT/s Transmitter Preset


Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_ESM_DSP_TX_PRESET_20G0

DSP 25GT/s Transmitter Preset Downstream Port 25GT/s Transmitter Preset


Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_ESM_DSP_TX_PRESET_25G0

ESM Quick EQ Timeout Specifies the quick EQ time


Values:
■ Quick EQ is not Supported (0)
■ 8ms/16ms (1)
■ 24ms/32ms (2)
■ 50ms/58ms (3)
■ 100ms/108ms (4)
■ 200ms/208ms (5)
Default Value: Quick EQ is not Supported
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_CX_CCIX_ESM_QUICK_EQ_TIME

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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / CCIX Transport DVSEC

Label Description

ESM re-calibration is needed Specifies if ESM re-calibration is needed after ESM Data Rate is updated
after ESM Data Rate is updated Values:
■ Not needed (0)
■ Needed (1)
Default Value: Not needed
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_CX_CCIX_ESM_RECAL_NEEDED

ESM Calibration Time Specifies the maximum calibration time


Values:
■ 10us (0)
■ 50us (1)
■ 100us (2)
■ 500us (3)
■ 1ms (4)
■ 5ms (5)
■ 10ms (6)
■ 50ms (7)
Default Value: 10us
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_CX_CCIX_ESM_CAL_TIME

ESM Reach Length for ESM Data Specifies the reach length for ESM Data Rate1
Rate1 Values:
■ Short Reach(SR) (0)
■ Long Reach(LR) (1)
■ SR and LR (2)
Default Value: Short Reach(SR)
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_CX_CCIX_ESM_REACH_LENGTH

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Label Description

ESM Extended EQ2 timeout for Specifies the ESM Extended EQ Phase2 timeout value for USP ESM Data Rate1
USP Values:
■ 24ms/32ms (0)
■ 50ms/58ms (1)
■ 100ms/108ms (2)
■ 200ms/208ms (3)
■ 400ms/408ms (4)
■ 600ms/608ms (5)
Default Value: 24ms/32ms
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_CX_CCIX_ESM_EXT_EQ2_USP_TIMEOUT

ESM Extended EQ3 timeout for Specifies the ESM Extended EQ Phase3 timeout value for DSP ESM Data Rate1
DSP Values:
■ 24ms/32ms (0)
■ 50ms/58ms (1)
■ 100ms/108ms (2)
■ 200ms/208ms (3)
■ 400ms/408ms (4)
■ 600ms/608ms (5)
Default Value: 24ms/32ms
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_CX_CCIX_ESM_EXT_EQ3_DSP_TIMEOUT

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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI

6.29 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / PCI Express Capability Parameters
Table 6-29 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Express Capability
Parameters

Label Description

PCI Express Capability

PCIe Capabilities Interrupt Default value for the Interrupt Message Number field in the PCI Express Capabilities
Message Number (PF#i) Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1f
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: PCIE_CAP_INT_MSG_NUM_n

Is Port Connected to Slot (PF#i) Indicates that the PCI Express link associated with this Port is connected to a slot.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_IMPLEMENTED_n

Support No-Snoop (PF#i) Default value for the Enable No Snoop bit in the Device Control Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_NO_SNOOP_SUPPORTED_n

Enable Root RCB (PF#i) Default value for the Read Completion Boundary (RCB) bit in the Link Control
(for n = 0; n <= CX_NFUNC-1) Register.
Values:
■ 64-bytes (0x0)
■ 128-bytes (0x1)
Default Value: 64-bytes
Enabled: CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_DM
Parameter Type: Register Default Setting
Parameter Name: ROOT_RCB_n

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6.30 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / MSI-X Register Configuration (PF0) Parameters
Table 6-30 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / MSI-X Register
Configuration (PF0) Parameters

Label Description

MSI-X Register Configuration (PF0)

MSI-X Table Size (PF#i) Default value for the MSI-X Table Size field in the MSI-X Control Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x7ff
Default Value: 0x0
Enabled: MSIX_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: MSIX_TABLE_SIZE_n

MSI-X Table BIR (PF#i) Default value for the Table BAR Indicator Register (BIR) field in the MSI-X Table Offset
(for n = 0; n <= CX_NFUNC-1) and BIR Register.
Values:
■ BAR0 (0x0)
■ BAR1 (0x1)
■ BAR2 (0x2)
■ BAR3 (0x3)
■ BAR4 (0x4)
■ BAR5 (0x5)
Default Value: BAR0
Enabled: MSIX_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: MSIX_TABLE_BIR_n

MSI-X Table Offset (PF#i) Default value for the Table Offset field in the MSI-X Table Offset and BIR Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1fffffff
Default Value: 0x0
Enabled: ((MSIX_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: MSIX_TABLE_OFFSET_n

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Label Description

MSI-X PBA BIR (PF#i) Default value for the Pending Bit Array (PBA) BIR field in the MSI-X PBA Offset and
(for n = 0; n <= CX_NFUNC-1) BIR Register.
Values:
■ BAR0 (0x0)
■ BAR1 (0x1)
■ BAR2 (0x2)
■ BAR3 (0x3)
■ BAR4 (0x4)
■ BAR5 (0x5)
Default Value: BAR0
Enabled: ((MSIX_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: MSIX_PBA_BIR_n

MSI-X PBA Offset (PF#i) Default value for the PBA Offset field in the MSI-X PBA Offset and BIR Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1fffffff
Default Value: 0x0
Enabled: ((MSIX_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: MSIX_PBA_OFFSET_n

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Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Advanced Error Register Configuration Parameters PCI Express SW

6.31 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / Advanced Error Register Configuration Parameters
Table 6-31 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Advanced Error
Register Configuration Parameters

Label Description

Advanced Error Register Configuration

Default ECRC Check Capability Default value for the ECRC Check Capable bit in the Advanced Capabilities and
(PF#i) Control Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: (CX_ECRC_ENABLE==1) ? 1 : 0
Enabled: CX_ECRC_ENABLE==1 && AER_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_ECRC_CHK_CAP_n

Default ECRC Generation Default value for the ECRC Generation Capability bit in the Advanced Capabilities and
Capability (PF#i) Control Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: (CX_ECRC_ENABLE==1) ? 1 : 0
Enabled: CX_ECRC_ENABLE==1 && AER_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_ECRC_GEN_CAP_n

Advanced Error Interrupt Default value for the Advanced Error Interrupt Message Number field of the Root Error
Message Number (PF#i) Status Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1f
Default Value: 0x0
Enabled: AER_ENABLE==1 && CC_DEVICE_TYPE!=CC_EP &&
CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: AER_INT_MSG_NUM_n

AER Header Log Depth (PF#i) AER Header log depth.


(for n = 0; n <= CX_NFUNC-1) Values: 0x1, 0x2, 0x4
Default Value: 0x1
Enabled: AER_ENABLE==1
Parameter Type: Feature Setting.
Parameter Name: CX_HDR_LOG_DEPTH_n

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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / TLP

6.32 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / TLP Processing Hints Register Configuration (PF0) Parameters
Table 6-32 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / TLP Processing Hints
Register Configuration (PF0) Parameters

Label Description

TLP Processing Hints Register Configuration (PF0)

Interrupt Vector Mode Support TLP Processing Hints supports Interrupt Vector Mode. If set indicates that the function
(PF#i) supports the Interrupt Vector Mode of operation.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_TPH_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: TPH_IVEC_n

Device Specific Mode Support TLP Processing Hints supports Device Specific Mode. If set indicates that the function
(PF#i) supports the Device Specific Mode of operation.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_TPH_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: TPH_DS_n

Steering Tag Table Location TLP Processing Hints Steering Tag Table Location. Value indicates if and where the
(PF#i) ST Table is located.
(for n = 0; n <= CX_NFUNC-1) Values:
■ Not Present (0)
■ TPH Requester Capability Structure (1)
■ MSI-X Table Structure (2)
Default Value: Not Present
Enabled: (CX_TPH_ENABLE==1 && (TPH_DS_0 || TPH_IVEC_0))
Parameter Type: Feature Setting
Parameter Name: TPH_ST_TABLE_LOC_n

Steering Tag Table Size (PF#i) TLP Processing Hints Steering Tag Table Size. Software reads this field to determine
(for n = 0; n <= CX_NFUNC-1) the ST Table Size N, which is encoded as N-1. For example, a returned value of
00000000011 indicates a table size of 4.
Values: 1, ..., 2048
Default Value: 1
Enabled: (CX_TPH_ENABLE==1 && (TPH_ST_TABLE_LOC_0 != 0))
Parameter Type: Feature Setting
Parameter Name: TPH_ST_TABLE_SIZE_n

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Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ATS Register Configuration (PF0) Parameters PCI Express SW Controller

6.33 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / ATS Register Configuration (PF0) Parameters
Table 6-33 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ATS Register
Configuration (PF0) Parameters

Label Description

ATS Register Configuration (PF0)

ATS Invalidate Queue Depth The number of Invalidate Requests that the Function can accept before putting
(PF#i) backpressure on the upstream connection. A value of 0 indicates the function can
(for n = 0; n <= CX_NFUNC-1) accept 32 Invalidate requests.
Values: 0, ..., 31
Default Value: 0
Enabled: CX_ATS_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: ATS_INV_Q_DPTH_n

ATS Smallest Translation Unit This value indicates to the Function the minimum number of 4096-byte blocks that is
(PF#i) indicated in a Translation Completion or Invalidate Request. This is a power of 2
(for n = 0; n <= CX_NFUNC-1) multiplier and the number of blocks is 2^STU. A value of 0 indicates 1 block and a
value of 31 indicates 2^31 blocks (or 8 TB total).
Values: 0, ..., 31
Default Value: 0
Enabled: CX_ATS_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: ATS_STU_n

ATS Global Invalidate Supported This is the default value (after reset) of the Global Invalidate Supported bit field in the
ATS Capability register. If set, the function supports Invalidation Requests that have
the Global Invalidate bit set. If clear, the function ignores the Global Invalidate bit in all
Invalidate Requests. This bit is 0b if the function does not support the PASID TLP
Prefix.
Values: 0x0, 0x1
Default Value: 0x0
Enabled: CX_ATS_ENABLE && CX_PASID_ENABLE
Parameter Type: Feature Setting
Parameter Name: DEFAULT_ATS_GLOBAL_INVAL_SPPRT

PRS Outstanding Capacity (PF#i) Register default for PRS Outstanding Capacity in PF0. For more details, see the
(for n = 0; n <= CX_NFUNC-1) PRS_OUTSTANDING_CAPACITY field in the PRS_REQ_CAPACITY_REG register.
Values: 0x0, ..., 0xffffffff
Default Value: 0x1
Enabled: (CX_PRS_ENABLE==1) && (CC_DEVICE_TYPE != CC_SW) &&
(CC_DEVICE_TYPE != CC_RC)
Parameter Type: Register Default Setting
Parameter Name: CX_PRS_OUTSTANDING_CAPACITY_VALUE_n

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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ACS

6.34 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / ACS Register Configuration (PF0) Parameters
Table 6-34 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ACS Register
Configuration (PF0) Parameters

Label Description

ACS Source Validation This is the default value (after reset) of the ACS Source Validation bit field in the ACS
Supported (PF0) Capability register in PF0. A value of 1, indicates that the component implements ACS
Source Validation.
Values: 0x0, 0x1
Default Value: CC_DEVICE_TYPE!=CC_EP
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_SRC_VALID

ACS Translation Blocking This is the default value (after reset) of the ACS Translation Blocking bit field in the
Supported (PF0) ACS Capability register in PF0. A value of 1, indicates that the component implements
ACS Translation Blocking.
Values: 0x0, 0x1
Default Value: CC_DEVICE_TYPE!=CC_EP
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_AT_BLOCK

ACS P2P Request Redirect This is the default value (after reset) of the ACS P2P Request Redirect bit field in the
(PF#i) ACS Capability register in PF0. A value of 1, indicates that the component implements
(for n = 0; n <= CX_NFUNC-1) ACS P2P Request Redirect.
Values: 0x0, 0x1
Default Value: 0x1
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_P2P_REQ_REDIRECT_n

ACS P2P Completion Redirect This is the default value (after reset) of the ACS P2P Completion Redirect bit field in
(PF#i) the ACS Capability register in PF0. A value of 1, indicates that the component
(for n = 0; n <= CX_NFUNC-1) implements ACS P2P Completion Redirect.
Values: 0x0, 0x1
Default Value: 0x1
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_P2P_COMPL_REDIRECT_n

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Label Description

ACS Upstream Forwarding This is the default value (after reset) of the ACS Upstream Forwarding bit field in the
Supported (PF0) ACS Capability register in PF0. A value of 1, indicates that the component implements
ACS Upstream Forwarding.
Values: 0x0, 0x1
Default Value: CC_DEVICE_TYPE!=CC_EP
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_UP_FORWARD

ACS P2P Egress Control (PF#i) This is the default value (after reset) of the ACS P2P Egress Control bit field in the
(for n = 0; n <= CX_NFUNC-1) ACS Capability register in PF0. A value of 1, indicates that the component implements
ACS P2P Egress Control.
Values: 0x0, 0x1
Default Value: 0x1
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_P2P_EGRESS_CTRL_n

ACS Direct Translated P2P This is the default value (after reset) of the ACS Direct Translated P2P bit field in the
(PF#i) ACS Capability register in PF0. A value of 1, indicates that the component implements
(for n = 0; n <= CX_NFUNC-1) ACS Direct Translated P2P.
Values: 0x0, 0x1
Default Value: CC_DEVICE_TYPE==CC_SW || ((CC_DEVICE_TYPE==CC_DM ||
CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_EP) &&
(CX_ATS_ENABLE==1))
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_P2P_DIRECT_TRANSL_n

ACS Egress Control Vector Size This is the default value (after reset) of the Egress Control Vector Size field in the ACS
(PF#i) Capability register in PF0. Encodes 01h-FFh directly indicate the number of applicable
(for n = 0; n <= CX_NFUNC-1) bits in the Egress Control Vector; the encoding 00h indicates 256 bits.
Values: 0x0, ..., 0xff
Default Value: CC_DEVICE_TYPE==CC_SW || CC_DEVICE_TYPE==CC_RC) ?
0x4 : (CX_ACS_FUNC_GRP ? 0x8 : ((CX_NFUNC > 1 || CX_SRIOV_ENABLE) ?
CX_NFUNC : 0x4)
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_EGRESS_CTRL_SIZE_n

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Label Description

Upstream Port ACS Egress This determines the default value of the read only bits in the Upstream Port Egress
Control Vector Mask (PF#i) Control Vector (after reset) in PF0. Set bits to 1 to indicate Read Only.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
Default Value: [<functionof> CX_ACS_FUNC_GRP 0]
Enabled: (CX_ACS_ENABLE && (CC_DEVICE_TYPE==CC_EP ||
CC_DEVICE_TYPE==CC_DM))
Parameter Type: Feature Setting
Parameter Name: CX_ACS_UP_EGRESS_CTRL_MASK_n

Downstream Port ACS Egress This determines the default value of the read only bits in the Downstream Port Egress
Control Vector Mask (PF#i) Control Vector (after reset) in PF0. Set bits to 1 to indicate Read Only.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
Default Value: 0x1
Enabled: CX_ACS_ENABLE && CC_DEVICE_TYPE!=CC_EP
Parameter Type: Feature Setting
Parameter Name: CX_ACS_DW_EGRESS_CTRL_MASK_n

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Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Lightweight Notification Configuration (PF0) Parameters PCI Express SW

6.35 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / Lightweight Notification Configuration (PF0) Parameters
Table 6-35 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Lightweight
Notification Configuration (PF0) Parameters

Label Description

Lightweight Notification Configuration (PF0)

LN Registration Max Default This parameter sets the default of the LNR_REGISTRATION_MAX field in the
(PF#i) LNR_CAP_OFF register for PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1f
Default Value: 0x0
Enabled: CX_LN_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: CX_LN_REG_MAX_VALUE_n

LNR-128 Supported Default This parameter sets the default of the LNR_128_SUPPORTED field in the
(PF#i) LNR_CAP_OFF register for PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: CX_LN_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: CX_LN_128_SUPPORTED_VALUE_n

LNR-64 Supported Default (PF#i) This parameter sets the default of the LNR_64_SUPPORTED field in the
(for n = 0; n <= CX_NFUNC-1) LNR_CAP_OFF register for PF0.
Values: 0x0, 0x1
Default Value: 0x0
Enabled: CX_LN_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: CX_LN_64_SUPPORTED_VALUE_n

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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) /

6.36 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / Readiness Configuration (PF0) Parameters
Table 6-36 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Readiness
Configuration (PF0) Parameters

Label Description

Immediate Readiness Configuration (PF0)

Immediate Readiness (PF#i) Enable Immediate Readiness support in the controller for PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_IMM_EN==1
Enabled: CX_RN_IMM_EN==1
Parameter Type: Feature Setting
Parameter Name: CX_RN_IMM_VALUE_n

Immediate Readiness D0 (PF#i) Enable Immediate Readiness on Return to D0 support in the controller for PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_IMM_EN==1
Enabled: CX_RN_IMM_EN==1
Parameter Type: Feature Setting
Parameter Name: CX_RN_IMM_D0_VALUE_n

Readiness Time Reporting Configuration (PF0)

RTR Valid (PF#i) Register default for RTR Valid field in PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_RTR_EN==1
Enabled: CX_RN_RTR_EN==1
Parameter Type: Register Default Setting
Parameter Name: CX_RN_RTR_VALID_n

RTR DL Up Time (PF#i) Register default for RTR DL Up Time field in PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: 0x0
Enabled: CX_RN_RTR_EN==1
Parameter Type: Register Default Setting
Parameter Name: CX_RN_RTR_DL_UP_VALUE_n

RTR Reset Time (PF#i) Register default for RTR Reset Time field in PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: 0x0
Enabled: CX_RN_RTR_EN==1
Parameter Type: Register Default Setting
Parameter Name: CX_RN_RTR_RESET_VALUE_n

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Label Description

RTR D3hot to D0 Time (PF#i) Register default for RTR D3hot to D0 Time field in PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x80a
Default Value: 0x0
Enabled: CX_RN_RTR_EN==1
Parameter Type: Register Default Setting
Parameter Name: CX_RN_RTR_D3D0_VALUE_n

RTR FLR Time (PF#i) Register default for RTR FLR Time field in PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: 0x0
Enabled: CX_RN_RTR_EN==1 && CX_FLR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: CX_RN_RTR_FLR_VALUE_n

VF RTR Valid (PF#i) Register default for RTR Valid field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_RTR_VALID_0 && VF_RTR_ENABLE
Enabled: VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_RN_RTR_VALID_n

VF Reset Time (PF#i) Register default for RTR Reset Time field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: CX_RN_RTR_RESET_VALUE_0
Enabled: VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_RN_RTR_RESET_VALUE_n

VF D3hot to D0 Time (PF#i) Register default for RTR D3hot to D0 Time field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x80a
Default Value: CX_RN_RTR_D3D0_VALUE_0
Enabled: VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_RN_RTR_D3D0_VALUE_n

VF FLR Time (PF#i) Register default for RTR FLR Time field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: CX_RN_RTR_FLR_VALUE_0
Enabled: VF_RTR_ENABLE==1 && CX_FLR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_RN_RTR_FLR_VALUE_n

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Label Description

External VF RTR Valid (PF#i) Register default for RTR Valid field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_RTR_VALID_0 && EXT_VF_RTR_ENABLE
Enabled: EXT_VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: EXT_VF_RN_RTR_VALID_n

External VF Reset Time (PF#i) Register default for RTR Reset Time field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: CX_RN_RTR_RESET_VALUE_0
Enabled: EXT_VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: EXT_VF_RN_RTR_RESET_VALUE_n

External VF D3hot to D0 Time Register default for RTR D3hot to D0 Time field in PF0 VFs.
(PF#i) Values: 0x0, ..., 0x80a
(for n = 0; n <= CX_NFUNC-1) Default Value: CX_RN_RTR_D3D0_VALUE_0
Enabled: EXT_VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: EXT_VF_RN_RTR_D3D0_VALUE_n

External VF FLR Time (PF#i) Register default for RTR FLR Time field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: CX_RN_RTR_FLR_VALUE_0
Enabled: EXT_VF_RTR_ENABLE==1 && CX_FLR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: EXT_VF_RN_RTR_FLR_VALUE_n

FRS Messaging Configuration (PF0)

FRS Supported (PF#i) Function Readiness Status messaging supported for function PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_FRS_SUPPORTED==1
Enabled: CX_RN_FRS_SUPPORTED==1
Parameter Type: Feature Setting
Parameter Name: CX_RN_FRS_VALUE_n

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Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Power Management Register Configuration Parameters PCI Express SW

6.37 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / Power Management Register Configuration Parameters
Table 6-37 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Power Management
Register Configuration Parameters

Label Description

Power Management Register Configuration

PME Support (PF#i) Default value for the PME_Support field in the Power Management Capabilities
(for n = 0; n <= CX_NFUNC-1) Register.
Values: 0x0, ..., 0x1f
Default Value: 0x1b
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: PME_SUPPORT_n

D1 Support (PF#i) Default value for the D1 Support bit in the Power Management Capabilities Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: D1_SUPPORT_n

D2 Support (PF#i) Default value for the D2 Support bit in the Power Management Capabilities Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: D2_SUPPORT_n

Device Specific Initialization Default value for the Device Specific Initialization (DSI) bit in the Power Management
(PF#i) Capabilities Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEV_SPEC_INIT_n

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Label Description

Auxiliary Current (PF#i) Default value for the Aux Current field in the Power Management Capabilities Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ 0mA (0x0)
■ 55mA (0x1)
■ 100mA (0x2)
■ 160mA (0x3)
■ 220mA (0x4)
■ 270mA (0x5)
■ 320mA (0x6)
■ 375mA (0x7)
Default Value: 375mA
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: AUX_CURRENT_n

No Reset on D3hot->D0 Default value for the No Soft Reset bit in the Power Management Control and Status
Transition (PF#i) Register. When set, you should not reset any controller registers when transitioning
(for n = 0; n <= CX_NFUNC-1) from D3hot to D0. Therefore, you should not assert the non_sticky_rst_n and
sticky_rst_n inputs.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_NO_SOFT_RESET_n

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6.38 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / PCI Register Configuration Parameters
Table 6-38 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Register
Configuration Parameters

Label Description

PCI Register Configuration

Device Identification Number Default value for the Device ID field in the Device ID and Vendor ID Register.
(PF#i) Values: 0x0, ..., 0xffff
(for n = 0; n <= CX_NFUNC-1) Default Value: 0xabcd
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_DEVICE_ID_n

Vendor Identification Number Default value for the Vendor ID field in the Device ID and Vendor ID Register.
(PF#i) Values: 0x0, ..., 0xffff
(for n = 0; n <= CX_NFUNC-1) Default Value: 0x16c3
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_VENDOR_ID_n

Device Revision Number (PF#i) Default value for the Revision ID field in the Revision ID Register
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xff
Default Value: 0x1
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_REVISION_ID_n

Subsystem Device ID (PF#i) Default value for the Subsystem ID field in the Subsystem ID and Subsystem Vendor
(for n = 0; n <= CX_NFUNC-1) ID Register.
Values: 0x0, ..., 0xffff
Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: SUBSYS_DEV_ID_n

Subsystem Vendor ID (PF#i) Default value for the Subsystem Vendor ID field in the Subsystem ID and Subsystem
(for n = 0; n <= CX_NFUNC-1) Vendor ID Register.
Values: 0x0, ..., 0xffff
Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: SUBSYS_VENDOR_ID_n

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Label Description

Include ROM BAR (PF#i) Include the expansion ROM BAR registers.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: ROM_BAR_ENABLED_n

ROM BAR Mask (PF#i) Determines the default of the Expansion ROM BAR Mask register.
(for n = 0; n <= CX_NFUNC-1) ■ The BAR Mask register specifies which bits of the Expansion ROM BAR are
non-writable by host software, which determines the size of the BAR.
■ The maximum value for ROM_MASK_N is 0xFFFFFF because the maximum
space that can be claimed by an Expansion ROM BAR is 16 MB.
■ For example: 32'hFFFF =BAR size of 2^16.
Values: 0x7ff, ..., 0xffffff
Default Value: 0xffff
Enabled: ROM_BAR_ENABLED_n==1
Parameter Type: Register Default Setting
Parameter Name: ROM_MASK_n

Programmable ROM BAR Mask Determines if the Expansion ROM BAR Mask register is writable by application
(PF#i) software. If writing to a Expansion ROM BAR Mask register is enabled, your
(for n = 0; n <= CX_NFUNC-1) application can write to the Expansion ROM BAR Mask register through the DBI by
asserting dbi_cs2 in addition to dbi_cs.
Values: 0x0, 0x1
Default Value: 0x0
Enabled: ROM_BAR_ENABLED_n==1
Parameter Type: Feature Setting
Parameter Name: ROM_MASK_WRITABLE_n

Specify ROM BAR Target Direct incoming requests that pass filtering and match the Expansion ROM BAR to
Interface (PF#i) either RTRGT0 or RTRGT1.
(for n = 0; n <= CX_NFUNC-1) ■ For example, setting ROM_FUNC0_BAR0_TARGET_MAP to 1 maps all incoming
requests for the Expansion ROM BAR of function 0 to RTRGT1.
■ If TRGT1_POPULATE =0 (no RTRGT1 interface), then the map-by-BAR parame-
ters have no effect; all requests that pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: ROM_BAR_ENABLED_n==1 && TRGT1_POPULATE==1
Parameter Type: Feature Setting
Parameter Name: ROM_FUNCn_TARGET_MAP

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Label Description

Configure Other PCI Register Select here if you want to configure the defaults for the other PCI Standard Header
Defaults (PF#i) registers. An extra window will appear under this page. To access it, click the
(for n = 0; n <= CX_NFUNC-1) plus/minus symbol in the hierarchy view on the left panel. This is optional but not
usually recommended. You can also change these register defaults using the DBI
before (or after) the link comes up.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_PCI_HEADER_DEFAULTS_VISIBLE_n

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6.39 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / PCI Register Configuration / PF0 PCI Register Defaults Parameters
Table 6-39 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Register
Configuration / PF0 PCI Register Defaults Parameters

Label Description

PF0 PCI Register Defaults

Base Class Code (PF#i) Default value for the Base Class Code field in the Class Code Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: BASE_CLASS_CODE_n

Sub Class Code (PF#i) Default value for the Subclass Code field in the Class Code Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: SUB_CLASS_CODE_n

Programming Interface Code Default value for the Programming Interface field in the Class Code Register.
(PF#i) Values: 0x0, ..., 0xff
(for n = 0; n <= CX_NFUNC-1) Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: IF_CODE_n

CardBus CIS Address Pointer Default value for the CardBus CIS Pointer Register.
(PF#i) Values: 0x0, ..., 0xffff
(for n = 0; n <= CX_NFUNC-1) Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: CARDBUS_CIS_PTR_n

Interrupt Pin (PF#i) Default value for the Interrupt Pin Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ None (0x0)
■ INTA (0x1)
■ INTB (0x2)
■ INTC (0x3)
■ INTD (0x4)
Default Value: INTA
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: INT_PIN_MAPPING_n

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Label Description

IO Address Decode (PF#i) Default value for the 32-Bit I/O Space bit in the I/O Base and I/O Limit Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ 16-bit (0x0)
■ 32-bit (0x1)
Default Value: CC_DEVICE_TYPE==CC_SW
Enabled: (!(CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW))
Parameter Type: Register Default Setting
Parameter Name: IO_DECODE_32_n

Memory Address Decode (PF#i) Default value for the 64-Bit Memory Addressing bit in the Prefetchable Memory Base
(for n = 0; n <= CX_NFUNC-1) and Limit Register.
Values:
■ 32-bit (0x0)
■ 64-bit (0x1)
Default Value: CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW ||
CC_DEVICE_TYPE==CC_DM
Enabled: CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW ||
CC_DEVICE_TYPE==CC_DM
Parameter Type: Register Default Setting
Parameter Name: MEM_DECODE_64_n

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6.40 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / BAR Setup For Physical Function 0 (PF0) Parameters
Table 6-40 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / BAR Setup For
Physical Function 0 (PF0) Parameters

Label Description

BAR_0 / BAR_1

Include BAR_0 (PF#i) Include the BAR0 registers.


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: (CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW) ? 0 :
1
Enabled: !(CC_DEVICE_TYPE==CC_RC)
Parameter Type: Feature Setting
Parameter Name: BAR0_ENABLED_n

BAR_0 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: Memory
Enabled: BAR0_ENABLED_n==1
Parameter Type: Register Default Setting
Parameter Name: MEM0_SPACE_DECODER_n

BAR_0 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR0_ENABLED_n==1 && MEM0_SPACE_DECODER_n==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE0_n

BAR_0 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: (MEM0_SPACE_DECODER_0==1 || BAR0_ENABLED_0==0) ? 0 : 2
Enabled: BAR0_ENABLED_n==1 && MEM0_SPACE_DECODER_n==0
Parameter Type: Register Default Setting
Parameter Name: BAR0_TYPE_n

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Label Description

BAR_0 Sizing Scheme (PF#i) BAR0 Sizing Scheme


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the BAR mask value using the BARn_MASK_N configuration
parameter. You cannot change it in hardware.
■ Programmable Mask: You set the BAR mask value using the BARn_MASK_N
configuration parameter. You can change it in hardware by writing to the Mask
Register through the local DBI (only). Increases the register count.
■ Resizable BAR: Resizable BAR feature as defined in the PCIe Specification. You
can change the 'Supported Resource Sizes' field in the Control Register through
the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: BAR0_ENABLED_n==1
Parameter Type: Feature Setting
Parameter Name: BAR0_SIZING_SCHEME_n

RBAR0 Usable Resource Sizes Indicates usable resource sizes for BAR0.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR0 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: CX_BAR0_RESIZABLE_n==1
Parameter Type: Feature Setting
Parameter Name: CX_BAR0_RESOURCE_AVAIL_n

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Label Description

BAR_0 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffffffffffff
Default Value: CX_BAR0_RESIZABLE_n==1 ? [pcie_cc_bar_mask
CX_BAR0_RESOURCE_AVAIL_n] : MEM0_SPACE_DECODER_n==1 ? 0xFF :
0xFFFFF
Enabled: BAR0_ENABLED_n==1 && MEM0_SPACE_DECODER_n==0 &&
CX_BAR0_RESIZABLE_n==0
Parameter Type: Register Default Setting
Parameter Name: BAR0_MASK_n

Specify Target Interface for Direct incoming Requests that pass filtering and match BAR_0 to either RTRGT0 or
BAR_0 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR0_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: BAR0_ENABLED_n==1 && TRGT1_POPULATE==1
Parameter Type: Feature Setting
Parameter Name: MEM_FUNCn_BAR0_TARGET_MAP

Include BAR_1 (PF#i) Include the BAR1 registers.


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR0_TYPE_0==0 && CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: BAR1_ENABLED_n

BAR_1 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: Memory
Enabled: BAR1_ENABLED_0==1
Parameter Type: Register Default Setting
Parameter Name: MEM1_SPACE_DECODER_n

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Label Description

BAR_1 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR1_ENABLED_0==1 && MEM1_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE1_n

BAR_1 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: BAR1_TYPE_n

BAR_1 Sizing Scheme (PF#i) BAR1 Sizing Scheme


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the BAR mask value using the BARn_MASK_N configuration
parameter. You cannot change it in hardware.
■ Programmable Mask: You set the BAR mask value using the BARn_MASK_N
configuration parameter. You can change it in hardware by writing to the Mask
Register through the local DBI (only). Increases the register count.
■ Resizable BAR: Resizable BAR feature as defined in the PCIe Specification. You
can change the 'Supported Resource Sizes' field in the Control Register through
the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: BAR1_ENABLED_0==1
Parameter Type: Feature Setting
Parameter Name: BAR1_SIZING_SCHEME_n

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Label Description

RBAR1 Usable Resource Sizes Indicates usable resource sizes for BAR1.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR1 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfff0
Default Value: 0x10
Enabled: CX_BAR1_RESIZABLE_0==1
Parameter Type: Register Default Setting
Parameter Name: CX_BAR1_RESOURCE_AVAIL_n

BAR_1 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffff
Default Value: CX_BAR1_RESIZABLE_0==1 ? [calc_bar_mask
CX_BAR1_RESOURCE_AVAIL_0] : MEM1_SPACE_DECODER_0==1 ? 0xFF :
0xFFFF
Enabled: BAR1_ENABLED_0==1 && MEM1_SPACE_DECODER_0==0 &&
CX_BAR1_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR1_MASK_n

Specify Target Interface for Direct incoming requests that pass filtering and match BAR_1 to either RTRGT0 or
BAR_1 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR1_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR1 of function 0 to RTRGT1. If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: ((BAR1_ENABLED_0==1 && TRGT1_POPULATE==1) &&
CC_DEVICE_TYPE!=CC_RC)
Parameter Type: Register Default Setting
Parameter Name: MEM_FUNCn_BAR1_TARGET_MAP

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Label Description

VF BAR_0 Sizing Scheme (PF#i) VF BAR0 Sizing Scheme.


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the VF BAR mask value using the VF_BARn_MASK_N config-
uration parameter. You cannot change it in hardware.
■ Programmable Mask: You set the VF BAR mask value using the
VF_BARn_MASK_N configuration parameter. You can change it in hardware by
writing to the Mask Register through the local DBI (only). Increases the register
count.
■ VF Resizable BAR: VF Resizable BAR feature as defined in the PCIe Specification.
You can change the 'Supported Resource Sizes' field in the Control Register
through the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ VF Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: VF_BAR0_ENABLED_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR0_SIZING_SCHEME_n

VF RBAR0 Usable Resource Indicates usable resource sizes for VF BAR0.


Sizes (PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that VF BAR0 will operate correctly with the VF BAR
sized to either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: VF_BAR0_RESIZABLE_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR0_RESOURCE_AVAIL_n

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Label Description

VF BAR_1 Sizing Scheme (PF#i) VF BAR1 Sizing Scheme.


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the VF BAR mask value using the VF_BARn_MASK_N config-
uration parameter. You cannot change it in hardware.
■ Programmable Mask: You set the VF BAR mask value using the
VF_BARn_MASK_N configuration parameter. You can change it in hardware by
writing to the Mask Register through the local DBI (only). Increases the register
count.
■ VF Resizable BAR: VF Resizable BAR feature as defined in the PCIe Specification.
You can change the 'Supported Resource Sizes' field in the Control Register
through the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ VF Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: VF_BAR1_ENABLED_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR1_SIZING_SCHEME_n

VF BAR_2 Sizing Scheme (PF#i) VF BAR2 Sizing Scheme.


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the VF BAR mask value using the VF_BARn_MASK_N config-
uration parameter. You cannot change it in hardware.
■ Programmable Mask: You set the VF BAR mask value using the
VF_BARn_MASK_N configuration parameter. You can change it in hardware by
writing to the Mask Register through the local DBI (only). Increases the register
count.
■ VF Resizable BAR: VF Resizable BAR feature as defined in the PCIe Specification.
You can change the 'Supported Resource Sizes' field in the Control Register
through the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ VF Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: VF_BAR2_ENABLED_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR2_SIZING_SCHEME_n

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Label Description

VF BAR_3 Sizing Scheme (PF#i) VF BAR3 Sizing Scheme.


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the VF BAR mask value using the VF_BARn_MASK_N config-
uration parameter. You cannot change it in hardware.
■ Programmable Mask: You set the VF BAR mask value using the
VF_BARn_MASK_N configuration parameter. You can change it in hardware by
writing to the Mask Register through the local DBI (only). Increases the register
count.
■ VF Resizable BAR: VF Resizable BAR feature as defined in the PCIe Specification.
You can change the 'Supported Resource Sizes' field in the Control Register
through the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ VF Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: VF_BAR3_ENABLED_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR3_SIZING_SCHEME_n

VF BAR_4 Sizing Scheme (PF#i) VF BAR4 Sizing Scheme.


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the VF BAR mask value using the VF_BARn_MASK_N config-
uration parameter. You cannot change it in hardware.
■ Programmable Mask: You set the VF BAR mask value using the
VF_BARn_MASK_N configuration parameter. You can change it in hardware by
writing to the Mask Register through the local DBI (only). Increases the register
count.
■ VF Resizable BAR: VF Resizable BAR feature as defined in the PCIe Specification.
You can change the 'Supported Resource Sizes' field in the Control Register
through the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ VF Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: VF_BAR4_ENABLED_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR4_SIZING_SCHEME_n

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Label Description

VF BAR_5 Sizing Scheme (PF#i) VF BAR5 Sizing Scheme.


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the VF BAR mask value using the VF_BARn_MASK_N config-
uration parameter. You cannot change it in hardware.
■ Programmable Mask: You set the VF BAR mask value using the
VF_BARn_MASK_N configuration parameter. You can change it in hardware by
writing to the Mask Register through the local DBI (only). Increases the register
count.
■ VF Resizable BAR: VF Resizable BAR feature as defined in the PCIe Specification.
You can change the 'Supported Resource Sizes' field in the Control Register
through the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ VF Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: VF_BAR5_ENABLED_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR5_SIZING_SCHEME_n

BAR_2 / BAR_3

Include BAR_2 (PF#i) Include the BAR2 registers.


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: (CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW) ? 0 :
1
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Feature Setting
Parameter Name: BAR2_ENABLED_n

BAR_2 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: Memory
Enabled: BAR2_ENABLED_0==1
Parameter Type: Register Default Setting
Parameter Name: MEM2_SPACE_DECODER_n

BAR_2 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR2_ENABLED_0==1 && MEM2_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE2_n

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Label Description

BAR_2 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: BAR2_ENABLED_0==1 && MEM2_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR2_TYPE_n

BAR_2 Sizing Scheme (PF#i) BAR2 Sizing Scheme


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the BAR mask value using the BARn_MASK_N configuration
parameter. You cannot change it in hardware.
■ Programmable Mask: You set the BAR mask value using the BARn_MASK_N
configuration parameter. You can change it in hardware by writing to the Mask
Register through the local DBI (only). Increases the register count.
■ Resizable BAR: Resizable BAR feature as defined in the PCIe Specification. You
can change the 'Supported Resource Sizes' field in the Control Register through
the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: BAR2_ENABLED_0==1
Parameter Type: Feature Setting
Parameter Name: BAR2_SIZING_SCHEME_n

RBAR2 Usable Resource Sizes Indicates usable resource sizes for BAR2.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR2 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: CX_BAR2_RESIZABLE_0==1
Parameter Type: Register Default Setting
Parameter Name: CX_BAR2_RESOURCE_AVAIL_n

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Label Description

BAR_2 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffffffffffff
Default Value: CX_BAR2_RESIZABLE_0==1 ? [calc_bar_mask
CX_BAR2_RESOURCE_AVAIL_0] : MEM2_SPACE_DECODER_0==1 ? 0xFF :
0xFFFFF
Enabled: BAR2_ENABLED_0==1 && MEM2_SPACE_DECODER_0==0 &&
CX_BAR2_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR2_MASK_n

Specify Target Interface for Direct incoming requests that pass filtering and match BAR_2 to either RTRGT0 or
BAR_2 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR2_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR2 of function 0 to RTRGT1. If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: BAR2_ENABLED_0==1 && TRGT1_POPULATE==1
Parameter Type: Feature Setting
Parameter Name: MEM_FUNCn_BAR2_TARGET_MAP

Include BAR_3 (PF#i) Include the BAR3 registers.


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR2_TYPE_0==0
Parameter Type: Feature Setting
Parameter Name: BAR3_ENABLED_n

BAR_3 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: Memory
Enabled: BAR3_ENABLED_0==1
Parameter Type: Register Default Setting
Parameter Name: MEM3_SPACE_DECODER_n

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Label Description

BAR_3 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR3_ENABLED_0==1 && MEM3_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE3_n

BAR_3 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: BAR3_TYPE_n

BAR_3 Sizing Scheme (PF#i) BAR3 Sizing Scheme


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the BAR mask value using the BARn_MASK_N configuration
parameter. You cannot change it in hardware.
■ Programmable Mask: You set the BAR mask value using the BARn_MASK_N
configuration parameter. You can change it in hardware by writing to the Mask
Register through the local DBI (only). Increases the register count.
■ Resizable BAR: Resizable BAR feature as defined in the PCIe Specification. You
can change the 'Supported Resource Sizes' field in the Control Register through
the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: BAR3_ENABLED_0==1
Parameter Type: Feature Setting
Parameter Name: BAR3_SIZING_SCHEME_n

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Label Description

RBAR3 Usable Resource Sizes Indicates usable resource sizes for BAR3.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR3 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfff0
Default Value: 0x10
Enabled: CX_BAR3_RESIZABLE_0==1
Parameter Type: Register Default Setting
Parameter Name: CX_BAR3_RESOURCE_AVAIL_n

BAR_3 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffff
Default Value: CX_BAR3_RESIZABLE_0==1 ? [calc_bar_mask
CX_BAR3_RESOURCE_AVAIL_0] : MEM3_SPACE_DECODER_0==1 ? 0xFF :
0xFFFF
Enabled: BAR3_ENABLED_0==1 && MEM3_SPACE_DECODER_0==0 &&
CX_BAR3_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR3_MASK_n

Specify Target Interface for Direct incoming requests that pass filtering and match BAR_3 to either RTRGT0 or
BAR_3 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR3_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR3 of function 0 to RTRGT1.If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: BAR3_ENABLED_0==1 && TRGT1_POPULATE==1
Parameter Type: Register Default Setting
Parameter Name: MEM_FUNCn_BAR3_TARGET_MAP

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Label Description

VF RBAR2 Usable Resource Indicates usable resource sizes for VF BAR2.


Sizes (PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that VF BAR2 will operate correctly with the VF BAR
sized to either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: VF_BAR2_RESIZABLE_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR2_RESOURCE_AVAIL_n

BAR_4 / BAR_5

Include BAR_4 (PF#i) Include the BAR4 registers.


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: (CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW) ? 0 :
1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: BAR4_ENABLED_n

BAR_4 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: CC_DEVICE_TYPE!=CC_RC && BAR4_ENABLED_0==1
Enabled: BAR4_ENABLED_0==1
Parameter Type: Register Default Setting
Parameter Name: MEM4_SPACE_DECODER_n

BAR_4 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR4_ENABLED_0==1 && MEM4_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE4_n

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Label Description

BAR_4 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: BAR4_ENABLED_0==1 && MEM4_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR4_TYPE_n

BAR_4 Sizing Scheme (PF#i) BAR4 Sizing Scheme


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the BAR mask value using the BARn_MASK_N configuration
parameter. You cannot change it in hardware.
■ Programmable Mask: You set the BAR mask value using the BARn_MASK_N
configuration parameter. You can change it in hardware by writing to the Mask
Register through the local DBI (only). Increases the register count.
■ Resizable BAR: Resizable BAR feature as defined in the PCIe Specification. You
can change the 'Supported Resource Sizes' field in the Control Register through
the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: BAR4_ENABLED_0==1
Parameter Type: Feature Setting
Parameter Name: BAR4_SIZING_SCHEME_n

RBAR4 Usable Resource Sizes Indicates usable resource sizes for BAR4.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR4 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: CX_BAR4_RESIZABLE_0==1
Parameter Type: Register Default Setting
Parameter Name: CX_BAR4_RESOURCE_AVAIL_n

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Label Description

BAR_4 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffffffffffff
Default Value: CX_BAR4_RESIZABLE_0==1 ? [calc_bar_mask
CX_BAR4_RESOURCE_AVAIL_0] : MEM4_SPACE_DECODER_0==1 ? 0xFF :
0xFFF
Enabled: BAR4_ENABLED_0==1 && MEM4_SPACE_DECODER_0==0 &&
CX_BAR4_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR4_MASK_n

Specify Target Interface for Direct incoming requests that pass filtering and match BAR_4 to either RTRGT0 or
BAR_4 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR4_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR4 of function 0 to RTRGT1. If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: BAR4_ENABLED_0==1 && TRGT1_POPULATE==1
Parameter Type: Feature Setting
Parameter Name: MEM_FUNCn_BAR4_TARGET_MAP

Include BAR_5 (PF#i) Include the BAR5 registers.


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR4_TYPE_0==0
Parameter Type: Feature Setting
Parameter Name: BAR5_ENABLED_n

BAR_5 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: Memory
Enabled: BAR5_ENABLED_0==1
Parameter Type: Register Default Setting
Parameter Name: MEM5_SPACE_DECODER_n

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Label Description

BAR_5 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR5_ENABLED_0==1 && MEM5_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE5_n

BAR_5 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: BAR5_TYPE_n

BAR_5 Sizing Scheme (PF#i) BAR5 Sizing Scheme


(for n = 0; n <= CX_NFUNC-1) ■ Fixed Mask: You set the BAR mask value using the BARn_MASK_N configuration
parameter. You cannot change it in hardware.
■ Programmable Mask: You set the BAR mask value using the BARn_MASK_N
configuration parameter. You can change it in hardware by writing to the Mask
Register through the local DBI (only). Increases the register count.
■ Resizable BAR: Resizable BAR feature as defined in the PCIe Specification. You
can change the 'Supported Resource Sizes' field in the Control Register through
the local DBI (only).
Values:
■ Fixed Mask (0x0)
■ Programmable Mask (0x1)
■ Resizable BAR (0x2)
Default Value: Fixed Mask
Enabled: BAR5_ENABLED_0==1
Parameter Type: Feature Setting
Parameter Name: BAR5_SIZING_SCHEME_n

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Label Description

RBAR5 Usable Resource Sizes Indicates usable resource sizes for BAR5.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR5 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfff0
Default Value: 0x10
Enabled: CX_BAR5_RESIZABLE_0==1
Parameter Type: Register Default Setting
Parameter Name: CX_BAR5_RESOURCE_AVAIL_n

BAR_5 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffff
Default Value: CX_BAR5_RESIZABLE_0==1 ? [calc_bar_mask
CX_BAR5_RESOURCE_AVAIL_0] : MEM5_SPACE_DECODER_0==1 ? 0xFF :
0xFFFF
Enabled: BAR5_ENABLED_0==1 && MEM5_SPACE_DECODER_0==0 &&
CX_BAR5_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR5_MASK_n

Specify Target Interface for Direct incoming requests that pass filtering and match BAR_5 to either RTRGT0 or
BAR_5 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR5_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR5 of function 0 to RTRGT1. If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: BAR5_ENABLED_0==1 && TRGT1_POPULATE==1
Parameter Type: Feature Setting
Parameter Name: MEM_FUNCn_BAR5_TARGET_MAP

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Label Description

VF RBAR4 Usable Resource Indicates usable resource sizes for VF BAR4.


Sizes (PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that VF BAR4 will operate correctly with the VF BAR
sized to either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: VF_BAR4_RESIZABLE_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR4_RESOURCE_AVAIL_n

VF RBAR1 Usable Resource Indicates usable resource sizes for VF BAR1.


Sizes (PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that VF BAR1 will operate correctly with the VF BAR
sized to either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: VF_BAR1_RESIZABLE_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR1_RESOURCE_AVAIL_n

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Label Description

VF RBAR3 Usable Resource Indicates usable resource sizes for VF BAR3.


Sizes (PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that VF BAR3 will operate correctly with the VF BAR
sized to either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: VF_BAR3_RESIZABLE_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR3_RESOURCE_AVAIL_n

VF RBAR5 Usable Resource Indicates usable resource sizes for VF BAR5.


Sizes (PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that VF BAR5 will operate correctly with the VF BAR
sized to either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: VF_BAR5_RESIZABLE_n==1
Parameter Type: Feature Setting
Parameter Name: VF_BAR5_RESOURCE_AVAIL_n

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6.41 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / SR-IOV Register Configuration PF0 Parameters
Table 6-41 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / SR-IOV Register
Configuration PF0 Parameters

Label Description

SR-IOV Register Configuration PF0

Number of Virtual Functions Number of virtual functions supported for this physical function. Default value of the
(PF#i) InitialVFs field in the SR-IOV Capability registers. When Extensible Virtual Function
(for n = 0; n <= CX_NFUNC) (CX_EXTENSIBLE_VFUNC) is enabled, this parameter indicates the total of both
internal VFs and external VFs.
Values: 0x0, ..., SNPS_RSVDPARAM_24
Default Value: 0x2
Enabled: CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_MAX_VF_n

Virtual Function Dependency Specifies the 8-bit VF dependency link for the PF. Valid only if CX_NFUNC>1 and
Link (PF#i) CX_VF_DEPENDENCY_LINK_SUPP=1.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: CX_VF_DEPENDENCY_LINK_SUPP && CX_SRIOV_ENABLE &&
(CX_NFUNC > 1)
Parameter Type: Feature Setting
Parameter Name: CX_VF_DEPENDENCY_LINK_n

First VF Offset with ARI (PF#i) Specifies the Routing ID offset of the first VF in this physical function in an ARI capable
(for n = 0; n <= CX_NFUNC-1) hierarchy. When CX_VF_STRIDE_ALWAYS_ONE=1 this parameter is disabled
because it is not used.
Values: 0x0, ..., 0xffff
Default Value: (CX_NFUNC>=17) ? 32 : (CX_NFUNC>=9) ? 16 : (CX_NFUNC>=5) ?
8 : (CX_NFUNC>=3) ? 4 : CX_NFUNC
Enabled: CX_SRIOV_ENABLE && !CX_VF_STRIDE_ALWAYS_ONE
Parameter Type: Register Default Setting
Parameter Name: FIRST_VF_OFFSET_ARI_CAP_HIER1_n

First VF Offset without ARI (PF#i) Specifies the Routing ID offset of the first VF in this physical function in a non-ARI
(for n = 0; n <= CX_NFUNC-1) capable hierarchy. When CX_VF_STRIDE_ALWAYS_ONE=1 this parameter is
disabled because it is not used.
Values: 0x0, ..., 0xffff
Default Value: 0x100
Enabled: CX_SRIOV_ENABLE && !CX_VF_STRIDE_ALWAYS_ONE
Parameter Type: Register Default Setting
Parameter Name: FIRST_VF_OFFSET_ARI_CAP_HIER0_n

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Label Description

VF Stride with ARI (PF#i) Specifies the Routing ID stride from one VF to the next one in this physical function in
(for n = 0; n <= CX_NFUNC-1) an ARI capable hierarchy
Values: 0x0, ..., 0xffff
Default Value: CX_VF_STRIDE_ALWAYS_ONE) ? 1 : ((CX_NFUNC>=17) ? 32 :
(CX_NFUNC>=9) ? 16 : (CX_NFUNC>=5) ? 8 : (CX_NFUNC>=3) ? 4 : CX_NFUNC
Enabled: CX_SRIOV_ENABLE && !CX_VF_STRIDE_ALWAYS_ONE
Parameter Type: Register Default Setting
Parameter Name: VF_STRIDE_ARI_CAP_HIER1_n

VF Stride without ARI (PF#i) Specifies the Routing ID offset from one VF to the next one in this physical function in
(for n = 0; n <= CX_NFUNC-1) a non-ARI capable hierarchy
Values: 0x0, ..., 0xffff
Default Value: (CX_VF_STRIDE_ALWAYS_ONE) ? 0x0001 : 0x0100
Enabled: CX_SRIOV_ENABLE && !CX_VF_STRIDE_ALWAYS_ONE
Parameter Type: Register Default Setting
Parameter Name: VF_STRIDE_ARI_CAP_HIER0_n

Virtual Function Device Specifies the 16-bit virtual function Device ID for this physical function. It may be
Identification Number (PF#i) different from the physical function's.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xffff
Default Value: CX_DEVICE_ID_0
Enabled: CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: CX_VF_DEVICE_ID_n

Virtual Function Supported Page Specifies the 32-bit supported page sizes for virtual functions for the physical function.
Sizes (PF#i) Values: 0x553, ..., 0xffff
(for n = 0; n <= CX_NFUNC-1) Default Value: 0x553
Enabled: CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: CX_VF_SUPP_PAGE_SIZE_n

ARI Capable Hierarchy Only present in PF0. Read Only Zero in other PFs. Specifies if ARI Capable Hierarchy
Preserved (PF#i) bit is preserved across certain power state transitions
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_SRIOV_ENABLE
Enabled: CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: CX_ARI_CAP_HIER_PRSVD_n

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6.42 Per-Function PCIe Capabilities and BAR Config / Physical Function 0


(PF0) / Virtual Function BARs for PF0 Parameters
Table 6-42 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Virtual Function BARs
for PF0 Parameters

Label Description

Virtual Function BAR_0 / BAR_1 for PF0

Include VF BAR_0 (PF#i) Include the VF BAR0 registers .


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: (CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW) ? 0 :
1
Enabled: (CC_DEVICE_TYPE!=CC_RC) && CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_BAR0_ENABLED_n

PF#i VF BAR_0 is Prefetchable Virtual Function BAR0 Memory Prefetchable. When set indicates VF BAR0 Memory
(for n = 0; n <= CX_NFUNC-1) BAR is a prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR0_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE0_n

PF#i VF BAR_0 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: (VF_BAR0_ENABLED_0==0) ? 0 : 2
Enabled: VF_BAR0_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_BAR0_TYPE_n

PF#i VF BAR_0 Mask Virtual Function BAR0 Mask. Determines the default of the VF BAR Mask register. The
(for n = 0; n <= CX_NFUNC-1) VF BAR Mask register specifies which bits of the VF BAR are non-writable by host
software, which determines the size of the BAR.
Values: 0xff, ..., 0xffffffffffffffff
Default Value: VF_BAR0_RESIZABLE_0==1?[calc_bar_mask
VF_BAR0_RESOURCE_AVAIL_0]:(VF_BAR0_TYPE_0==0 ? 0xFFFF : 0xFFFFF)
Enabled: VF_BAR0_ENABLED_0==1 && CX_SRIOV_ENABLE &&
VF_BAR0_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR0_MASK_n

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Label Description

Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_0 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Note:This feature is not applicable for RC.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: ((VF_BAR0_ENABLED_0==1 && TRGT1_POPULATE==1) &&
CC_DEVICE_TYPE!=CC_RC) && CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MEM_FUNCn_BAR0_TARGET_MAP

Include VF BAR_1 (PF#i) Include the VF BAR1 registers .


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: (VF_BAR0_TYPE_0==0) && (CC_DEVICE_TYPE!=CC_RC) &&
CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_BAR1_ENABLED_n

PF#i VF BAR_1 is Prefetchable Virtual Function BAR1 Memory Prefetchable. When set indicates VF BAR1 Memory
(for n = 0; n <= CX_NFUNC-1) BAR is a prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR1_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE1_n

PF#i VF BAR_1 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR1_TYPE_n

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Label Description

PF#i VF BAR_1 Mask Virtual Function BAR1 Mask. Determines the default of the VF BAR Mask register. The
(for n = 0; n <= CX_NFUNC-1) VF BAR Mask register specifies which bits of the VF BAR are non-writable by host
software, which determines the size of the BAR
Values: 0xff, ..., 0xffffffff
Default Value: VF_BAR1_RESIZABLE_0==1?[calc_bar_mask
VF_BAR1_RESOURCE_AVAIL_0]: 0xFFFF
Enabled: VF_BAR1_ENABLED_0==1 && CX_SRIOV_ENABLE &&
VF_BAR1_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR1_MASK_n

Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_1 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Note:This feature is not applicable for RC.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: ((VF_BAR1_ENABLED_0==1 && TRGT1_POPULATE==1) &&
CC_DEVICE_TYPE!=CC_RC) && CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MEM_FUNCn_BAR1_TARGET_MAP

Virtual Function BAR_2 / BAR_3 for PF0

Include VF BAR_2 (PF#i) Include the VF BAR2 registers .


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: (CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW) ? 0 :
1
Enabled: CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_BAR2_ENABLED_n

PF#i VF BAR_2 is Prefetchable BAR2 Memory Prefetchable. When set indicates VF BAR2 Memory BAR is a
(for n = 0; n <= CX_NFUNC-1) prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR2_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE2_n

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Label Description

PF#i VF BAR_2 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: VF_BAR2_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_BAR2_TYPE_n

Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_2 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: VF_BAR2_ENABLED_0==1 && TRGT1_POPULATE==1 &&
CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_MEM_FUNCn_BAR2_TARGET_MAP

Include VF BAR_3 (PF#i) Include the VF BAR3 registers .


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR2_TYPE_0==0 && CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_BAR3_ENABLED_n

PF#i VF BAR_3 is Prefetchable Virtual Function BAR3 Memory Prefetchable. When set indicates VF BAR3 Memory
(for n = 0; n <= CX_NFUNC-1) BAR is a prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR3_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE3_n

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Label Description

PF#i VF BAR_3 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR3_TYPE_n

PF#i VF BAR_3 Mask Virtual Function BAR3 Mask. Determines the default of the VF BAR Mask register. The
(for n = 0; n <= CX_NFUNC-1) VF BAR Mask register specifies which bits of the VF BAR are non-writable by host
software, which determines the size of the BAR
Values: 0xff, ..., 0xffffffff
Default Value: VF_BAR3_RESIZABLE_0==1?[calc_bar_mask
VF_BAR3_RESOURCE_AVAIL_0]: 0xFFFF
Enabled: VF_BAR3_ENABLED_0==1 && CX_SRIOV_ENABLE &&
VF_BAR3_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR3_MASK_n

Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_3 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: VF_BAR3_ENABLED_0==1 && TRGT1_POPULATE==1 &&
CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MEM_FUNCn_BAR3_TARGET_MAP

Virtual Function BAR_4 / BAR_5 for PF0

Include VF BAR_4 (PF#i) Include the VF BAR4 registers .


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: (CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW) ? 0 :
1
Enabled: CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_BAR4_ENABLED_n

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Label Description

PF#i VF BAR_4 is Prefetchable Virtual Function BAR4 Memory Prefetchable. When set indicates VF BAR4 Memory
(for n = 0; n <= CX_NFUNC-1) BAR is a prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR4_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE4_n

PF#i VF BAR_4 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: VF_BAR4_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_BAR4_TYPE_n

PF#i VF BAR_4 Mask Virtual Function BAR4 Mask. Determines the default of the VF BAR Mask register. The
(for n = 0; n <= CX_NFUNC-1) VF BAR Mask register specifies which bits of the VF BAR are non-writable by host
software, which determines the size of the BAR
Values: 0xff, ..., 0xffffffffffffffff
Default Value: VF_BAR4_RESIZABLE_0==1?[calc_bar_mask
VF_BAR4_RESOURCE_AVAIL_0]: 0xFFF
Enabled: VF_BAR4_ENABLED_0==1 && CX_SRIOV_ENABLE &&
VF_BAR4_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR4_MASK_n

Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_4 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: VF_BAR4_ENABLED_0==1 && TRGT1_POPULATE==1 &&
CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MEM_FUNCn_BAR4_TARGET_MAP

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Label Description

Include VF BAR_5 (PF#i) Include the VF BAR5 registers .


(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR4_TYPE_0==0 && CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_BAR5_ENABLED_n

PF#i VF BAR_5 is Prefetchable Virtual Function BAR5 Memory Prefetchable. When set indicates VF BAR5 Memory
(for n = 0; n <= CX_NFUNC-1) BAR is a prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR5_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE5_n

PF#i VF BAR_5 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR5_TYPE_n

PF#i VF BAR_5 Mask Virtual Function BAR5 Mask. Determines the default of the VF BAR Mask register. The
(for n = 0; n <= CX_NFUNC-1) VF BAR Mask register specifies which bits of the VF BAR are non-writable by host
software, which determines the size of the BAR
Values: 0xff, ..., 0xffffffff
Default Value: VF_BAR5_RESIZABLE_0==1?[calc_bar_mask
VF_BAR5_RESOURCE_AVAIL_0]: 0xFFFF
Enabled: VF_BAR5_ENABLED_0==1 && CX_SRIOV_ENABLE &&
VF_BAR5_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR5_MASK_n

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Label Description

Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_5 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: VF_BAR5_ENABLED_0==1 && TRGT1_POPULATE==1 &&
CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MEM_FUNCn_BAR5_TARGET_MAP

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PCI Express SW Controller Databook Advanced RAM Config Parameters

6.43 Advanced RAM Config Parameters


Table 6-43 Advanced RAM Config Parameters

Label Description

RAM Timing

Single Port RAM Read Access Specifies the single port RAM read access time. Used by the synthesis.
Time [ps] Values: -2147483648, ..., 2147483647
Default Value: 800
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: RAM1P_RD_ACCESS

Single Port RAM Address/Data Specifies the single port RAM data setup. Used by the synthesis".
Setup Time [ps] Values: -2147483648, ..., 2147483647
Default Value: 350
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: RAM1P_ADDR_SU

Dual Port RAM Read Access Specifies the dual port RAM read access time. Used by the synthesis.
Time [ps] Values: -2147483648, ..., 2147483647
Default Value: 600
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: RAM2P_RD_ACCESS

Dual Port RAM Address/Data Specifies the dual port RAM data setup. Used by the synthesis.
Setup Time [ps] Values: -2147483648, ..., 2147483647
Default Value: 350
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: RAM2P_ADDR_SU

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Label Description

RAM Architecture

Single-port RAM model There are two possible architectures for the single-port RAMs used in the PCIe core:
architecture a) with a registered read port data output and b) with a registered read port address
input. coreConsultant will use this parameter to select the architecture used in the
single-port RAM models. It has no effect on the RTL implementation. Note: when
DesignWare RAMs are selected only registered read port data architecture is
supported for single-port RAMs
■ 0: Registered read port data output RAM model
■ 1: Registered read port address input RAM model
Values:
■ Registered Read Port Data Output (0)
■ Registered Read Port Address Input (1)
Default Value: Registered Read Port Data Output
Enabled: !(CX_RAM_TYPE==1)
Parameter Type: Feature Setting
Parameter Name: RAM1P_ARCH

Dual-port RAM model There are two possible architectures for the dual-port RAMs used in the PCIe core: a)
architecture with a registered read port data output and b) with a registered read port address
input. coreConsultant will use this parameter to select the architecture used in the
dual-port RAM models. It has no effect on the RTL implementation.
■ 0: Registered read port data output RAM model
■ 1: Registered read port address input RAM model
Values:
■ Registered Read Port Data Output (0)
■ Registered Read Port Address Input (1)
Default Value: Registered Read Port Data Output
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RAM2P_ARCH

RAM Output Registering/Retiming

Receive Queue RAM Output Specifies if a pipeline is inserted for the Receive Data/Header Queue RAM output
Pipeline signals.
This is a read-only signal for informational purposes. A non-optional read data retiming
register is always inserted on the RAM outputs.
Values:
■ No (0)
■ Yes (1)
Default Value: Yes
Enabled: 0
Parameter Type: Performance Setting
Parameter Name: CX_RAMQRAM_REGOUT_

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PCI Express SW Controller Databook Advanced RAM Config Parameters

Label Description

SOT RAM Output Pipeline Specifies if a pipeline is inserted for the SOT RAM output signals.
Values:
■ No (0)
■ Yes (1)
Default Value: ((CX_MAX_CORECLK_FREQ >= 500) && CX_RASDP > 0) ||
(CX_MAX_CORECLK_FREQ > 500)
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_RETRYSOTRAM_REGOUT

Retry RAM Output Pipeline Specifies if a pipeline is inserted for the Retry RAM output signals.
Values:
■ No (0)
■ Yes (1)
Default Value: ((CX_MAX_CORECLK_FREQ >= 500) && CX_RASDP > 0) ||
(CX_MAX_CORECLK_FREQ > 500)
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_RETRYRAM_REGOUT

RAM Read Data Latency

RADM Receive Queue RAM Specifies the Receive Queue Header and Data RAM read cycle latency. The controller
Read Cycle Latency samples the read data CX_RADM_RAM_RD_LATENCY clock cycles after the read
address is valid at the Header/Data RADM RAM interface.
Note:The RAM read data is always retimed/registered.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_RADMQ_MODE==2
Parameter Type: Performance Setting
Parameter Name: CX_RADM_RAM_RD_LATENCY

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Label Description

Receive Serialization Queue Specifies the Receive Serialization Queue RAM read cycle latency. The controller
RAM Read Cycle Latency samples the read data CX_RADM_FORMQ_RAM_RD_LATENCY clock cycles after
the read address is valid at the RADM FORMQ RAM interface.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_NW==16
Parameter Type: Performance Setting
Parameter Name: CX_RADM_FORMQ_RAM_RD_LATENCY

Retry RAM Read Cycle Latency Specifies the Retry RAM read cycle latency. The controller samples the read data
CX_RETRY_RAM_RD_LATENCY clock cycles after the read address is valid. The
default of '1' corresponds to the typical read cycle access time for synchronous
memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
Default Value: 1 Cycle
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_RETRY_RAM_RD_LATENCY

SOT RAM Read Cycle Latency Specifies the Retry SOT RAM read cycle latency. The controller samples the read data
CX_RETRY_SOT_RAM_RD_LATENCY clock cycles after the read address is valid.
The default of '1' corresponds to the typical read cycle access time for synchronous
memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
Default Value: 1 Cycle
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_RETRY_SOT_RAM_RD_LATENCY

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PCI Express SW Controller Databook Advanced RAM Config Parameters

Label Description

AXI Master Completion Buffer Specifies the MCB RAM read cycle latency. The controller samples the read data
RAM Read Latency CC_MSTR_CPL_SEG_BUF_RAM_RD_LATENCY clock cycles after the read address
is valid. The default of '1' corresponds to the typical read cycle access time for
synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_MSTR_CPL_SEG_BUF_RAM_RD_LATENCY

AXI Slave Completion Composer Specifies the AXI Slave Completion Composer RAM read cycle latency. The controller
RAM Read Latency samples the read data CC_OB_CCMP_DATA_RAM_RD_LATENCY clock cycles after
the read address is valid. The default of '1' corresponds to the typical read cycle
access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Performance Setting
Parameter Name: CC_OB_CCMP_DATA_RAM_RD_LATENCY

AXI Slave Completion Composer Specifies the AXI Slave Completion Composer CDC RAM read cycle latency. The
CDC RAM Read Latency controller samples the read data CC_OB_CPL_C2A_CDC_RAM_RD_LATENCY clock
cycles after the read address is valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: SLV_CLK_DIFF_ENABLE && SLAVE_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_OB_CPL_C2A_CDC_RAM_RD_LATENCY

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Label Description

AXI Slave Posted Decomposer Specifies the AXI Slave Posted Decomposer RAM read cycle latency. The controller
RAM Read Latency samples the read data CC_OB_PDCMP_RAM_RD_LATENCY clock cycles after the
read address is valid. The default of '1' corresponds to the typical read cycle access
time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_OB_PDCMP_RAM_RD_LATENCY

AXI Slave Non-Posted Specifies the AXI Slave Non-Posted decomposer RAM read cycle latency. The
decomposer RAM Read Latency controller samples the read data CC_OB_NPDCMP_RAM_RD_LATENCY clock
cycles after the read address is valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_OB_NPDCMP_RAM_RD_LATENCY

AXI Slave Non-Posted Write Specifies the AXI Slave Non-Posted Write Set-Aside Buffer read cycle latency. The
Set-Aside Buffer Read Latency controller samples the read data CC_SLV_NPW_SAB_RAM_RD_LATENCY clock
cycles after the read address is valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_SLV_NPW_SAB_RAM_RD_LATENCY

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Label Description

AXI Master Completion Buffer Specifies the AXI Master Completion Buffer CDC RAM read cycle latency. The
CDC RAM Read Latency controller samples the read data CC_MSTR_CPL_A2C_CDC_RAM_RD_LATENCY
clock cycles after the read address is valid. The default of '1' corresponds to the typical
read cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_IB_MCPL_CDC_RAM_RD_LATENCY

AXI Inbound Read Request CDC Specifies the AXI Inbound Read Request CDC RAM read cycle latency. The controller
RAM Read Latency samples the read data CC_IB_RD_REQ_CDC_RAM_RD_LATENCY clock cycles
after the read address is valid. The default of '1' corresponds to the typical read cycle
access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: SLV_CLK_DIFF_ENABLE && SLAVE_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_IB_RD_REQ_CDC_RAM_RD_LATENCY

AXI Inbound Write Request CDC Specifies the AXI Inbound Write Request CDC RAM read cycle latency. The controller
RAM Read Latency samples the read data CC_IB_WR_REQ_CDC_RAM_RD_LATENCY clock cycles
after the read address is valid. The default of '1' corresponds to the typical read cycle
access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: SLV_CLK_DIFF_ENABLE && SLAVE_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_IB_WR_REQ_CDC_RAM_RD_LATENCY

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Label Description

AXI Inbound Write Posted Specifies the AXI Inbound Write Posted Request Tracker RAM read cycle latency. The
Request Tracker RAM Read controller samples the read data CC_IB_WR_REQ_PTRK_RAM_RD_LATENCY clock
Latency cycles after the read address is valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Performance Setting
Parameter Name: CC_IB_WR_REQ_PTRK_RAM_RD_LATENCY

DTIM AXI Stream Slave Request Specifies the DTIM AXI Stream Slave Request Queue RAM read cycle latency. The
Queue RAM Read Cycle Latency controller samples the read data CX_DTIM_REQQ_RAM_RD_LATENCY clock cycles
after the read address is valid at the DTIM AXI Stream Slave Request Queue RAM
interface.
Note:The RAM read data is always retimed/registered.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CC_DTIM_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_DTIM_REQQ_RAM_RD_LATENCY

MSIX Table RAM Read Cycle Specifies the internal MSIX table RAM read cycle latency. The controller samples the
Latency read data CX_MSIX_TABLE_RAM_RD_LATENCY clock cycles after the read address
is valid at the MSIX table RAM interface.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MSIX_TABLE_EN==1
Parameter Type: Performance Setting
Parameter Name: CX_MSIX_TABLE_RAM_RD_LATENCY

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Label Description

eDMA Read engine Linked List Specifies the RAM latency of the eDMA Linked List Controller of the Read engine. The
Controller RAM Read Cycle controller samples the read data CC_IF_RDCTRL_LL_RAM_LATENCY clock cycles
Latency after the read address been valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_RDCTRL_LL_RAM_LATENCY

eDMA Write engine Linked List Specifies the RAM latency of the eDMA Linked List Controller of the Write engine. The
Controller RAM Read Cycle controller samples the read data CC_IF_WRCTRL_LL_RAM_LATENCY clock cycles
Latency after the read address been valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_WRCTRL_LL_RAM_LATENCY

eDMA Write engine Pre-Fetched Specifies the RAM latency of the eDMA Pre-Fetched Descriptor Queue of the Write
Descriptor Queue RAM Read engine. The controller samples the read data
Cycle Latency CC_IF_WRCTX_LLQ_OVERLAY_RAM_LATENCY clock cycles after the read
address been valid. The default of '1' corresponds to the typical read cycle access time
for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_WRCTX_LLQ_OVERLAY_RAM_LATENCY

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Label Description

eDMA Read engine Pre-Fetched Specifies the RAM latency of the eDMA Pre-Fetched Descriptor Queue of the Read
Descriptor Queue RAM Read engine. The controller samples the read data
Cycle Latency CC_IF_RDCTX_LLQ_OVERLAY_RAM_LATENCY clock cycles after the read address
been valid. The default of '1' corresponds to the typical read cycle access time for
synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_RDCTX_LLQ_OVERLAY_RAM_LATENCY

eDMA Read engine Memory Specifies the RAM latency of the eDMA Memory Read Context LUT of the Read
Read Context LUT RAM Read engine. The controller samples the read data CC_IF_RD_CTXC2W_RAM_LATENCY
Cycle Latency clock cycles after the read address been valid. The default of '1' corresponds to the
typical read cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_RD_CTXC2W_RAM_LATENCY

eDMA Write engine Memory Specifies the RAM latency of the eDMA Memory Read Context LUT of the Write
Read Context LUT RAM Read engine. The controller samples the read data CC_IF_WR_CTXC2W_RAM_LATENCY
Cycle Latency clock cycles after the read address been valid. The default of '1' corresponds to the
typical read cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_WR_CTXC2W_RAM_LATENCY

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Label Description

eDMA Read engine Memory Specifies the RAM latency of the eDMA Memory Write Context LUT of the Read
Write Context LUT RAM Read engine. The controller samples the read data CC_IF_RD_CTXSTSH_RAM_LATENCY
Cycle Latency clock cycles after the read address been valid. The default of '1' corresponds to the
typical read cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_RD_CTXSTSH_RAM_LATENCY

eDMA Write engine Memory Specifies the RAM latency of the eDMA Memory Write Context LUT of the Write
Write Context LUT RAM Read engine. The controller samples the read data
Cycle Latency CC_IF_WR_CTXSTSH_RAM_LATENCY clock cycles after the read address been
valid. The default of '1' corresponds to the typical read cycle access time for
synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_WR_CTXSTSH_RAM_LATENCY

eDMA Read engine MSI setup Specifies the RAM latency of the MSI setup of the Read engine. The controller
RAM Read Cycle Latency samples the read data CC_IF_RD_MSI_RAM_LATENCY clock cycles after the read
address been valid. The default of '1' corresponds to the typical read cycle access time
for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_RD_MSI_RAM_LATENCY

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Label Description

eDMA Write engine MSI setup Specifies the RAM latency of the MSI setup of the Write engine. The controller
RAM Read Cycle Latency samples the read data CC_IF_WR_MSI_RAM_LATENCY clock cycles after the read
address been valid. The default of '1' corresponds to the typical read cycle access time
for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_WR_MSI_RAM_LATENCY

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PCI Express SW Controller Databook Advanced PHY Config / General Options Parameters

6.44 Advanced PHY Config / General Options Parameters


Table 6-44 Advanced PHY Config / General Options Parameters

Label Description

General Options

Elasticity Buffer Mode Determines Elasticity Buffer Mode. Contact your PHY vendor for the value that you
should use. Only applicable to configurations not using a Frequency Step.
Values:
■ Nominal Half Full Buffer Mode (0)
■ Nominal Empty Buffer Mode (1)
Default Value: [<functionof>] && (CX_FREQ_STEP_EN==0 ||
CX_PIPERX_MULTI_BLOCK==1) && CX_GEN3_SPEED
Enabled: (CX_CPCIE_ENABLE==1 && (CX_FREQ_STEP_EN==0 ||
CX_PIPERX_MULTI_BLOCK==1) && CX_GEN3_SPEED)
Parameter Type: Feature Setting
Parameter Name: CX_PIPE_HYBRID_MODE

Selectable De-emphasis Selectable De-emphasis. Only for Gen2 downstream ports operating at 5 GT/s. This
bit selects the level of de-emphasis the link operates at. M-PCIe doesn't support this
feature.
Values:
■ -6 dB (0x0)
■ -3.5 dB (0x1)
Default Value: -6 dB
Enabled: CX_GEN2_SPEED==1 && CX_CPCIE_ENABLE &&
CC_DEVICE_TYPE!=CC_EP
Parameter Type: Feature Setting
Parameter Name: SEL_DE_EMPHASIS

Max PCLK frequency (MHz) Frequency (in MHz) of the max_pclk output clock from the PHY. Contact your PHY
vendor for the value that you should use.
Values:
■ MaxPclk not available (0)
■ 250 MHz (250)
■ 500 MHz (500)
■ 1 GHz (1000)
■ 2 GHz (2000)
■ 4 GHz (4000)
Default Value: MaxPclk not available
Enabled: Always
Parameter Name: CX_PHY_MAX_PCLK_FREQ_MHZ

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Label Description

RxStandby Control

RxStandby Signal Default Default value of RxStandby signal (mac_phy_rxstandby) on all lanes after reset.
Note: Contact your PHY vendor for guidelines on how to properly configure the
RxStandby behavior. Refer to the User Guidefor guidelines on how to configure this
parameter for Synopsys PHYs.
Values:
■ 0 (0x0)
■ 1 (0x1)
Default Value: PHY_TYPE==CC_GENERIC_PHY
Enabled: CX_CPCIE_ENABLE && PHY_TYPE!=CC_GENERIC_PHY
Parameter Type: Feature Setting
Parameter Name: CX_RXSTANDBY_DEFAULT

RxStandby Signal Operation Bits 0..5 determine if the controller asserts the RxStandby signal
Control (mac_phy_rxstandby) in the indicated condition.
Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake.
■ [0]: Rx EIOS and subsequent T TX-IDLE-MIN
■ [1]: Rate Change
■ [2]: Inactive lane for upconfigure/downconfigure
■ [3]: PowerDown=P1,P1.CPM,P1.1,P1.2 or P2 (When CX_PIPE43_SUPPORT==1,
this bit must be set to 0)
■ [4]: RxL0s.Idle
■ [5]: EI Infer in L0
■ [6]: Execute RxStandby/RxStandbyStatus Handshake
Note: Contact your PHY vendor for guidelines on how to properly configure the
RxStandby behavior. Refer to the User Guidefor guidelines on how to configure this
parameter for Synopsys PHYs.
Values: 0x0, ..., 0x7f
Default Value: (PHY_TYPE==CC_GENERIC_PHY) ? 0x7F :
(SNPS_RSVDPARAM_26) ? 0x7F : 0x44
Enabled: CX_CPCIE_ENABLE && PHY_TYPE!=CC_GENERIC_PHY
Parameter Type: Feature Setting
Parameter Name: CX_RXSTANDBY_CONTROL

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PCI Express SW Controller Databook Advanced PHY Config / General Options Parameters

Label Description

Synopsys PHY Features

PHY Register Viewport and Enables PHY register viewport and PRBI/CRPI for Synpsys PHY. The controller
PRBI/CRPI. implements the PHY register viewport in its Port Logic register space, and the Register
Bus Interface (PRBI) which communicates with the Phy's Control Register Parallel
Interface (CRPI), to enable access to registers in the PHY. The PHY registers can be
indirectly written to and read from through a configuration wire access or local DBI
access. This feature can be used with Synopsys PHYs that have the Control Register
Parallel Interface and not for PIPE Message Bus Interface. For more details, see "PHY
Port Logic Registers" in the "Register Module, LBC, and DBI" section in the Controller
Operations chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: !(CX_PL_REG_DISABLE) && CX_CPCIE_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_PHY_VIEWPORT_ENABLE

P2.NoBeacon Enable Enable support for P2.NoBeacon. When this parameter is set, mac_phy_powerdown
drives P2.NoBeacon encoding, instead of P2 encoding, when the link goes to L2.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_PIPE_VER>=1
Parameter Type: Feature Setting
Parameter Name: CX_P2NOBEACON_ENABLE

P2.CPM Encoding Powerdown state encoding on the mac_phy_powerdown[3:0] output for P2.NoBeacon.
Contact your PHY vendor for the value that you should use.
Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: CX_P2NOBEACON_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P2NOBEACON_ENCODING

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Advanced PHY Config / PHY Timing Parameters PCI Express SW Controller Databook

6.45 Advanced PHY Config / PHY Timing Parameters


Table 6-45 Advanced PHY Config / PHY Timing Parameters

Label Description

PHY Timing

Number of Fast Training (NFTS) Specifies the number of Fast Training Sequences the controller advertises during link
Sequences training. This is used to inform the link partner of the cores ability to recover
synchronization after a low power state. This number should come from your PHY
vendor. This parameter sets the default value of the N_FTS field of the 'Ack Frequency
and L0-L1 ASPM Control Register' in the Register section of the Databook. M-PCIe
doesn't use this parameter.
Values: 1, ..., 255
Default Value: ((CX_MAX_PCIE_SPEED==1) ? CX_PHY_NB_GEN1 :
(CX_MAX_PCIE_SPEED==2) ? CX_PHY_NB_GEN2 : (CX_MAX_PCIE_SPEED==3)
? CX_PHY_NB_GEN3 : (CX_MAX_PCIE_SPEED==4) ? CX_PHY_NB_GEN4 :
(CX_MAX_PCIE_SPEED==5) ? CX_PHY_NB_GEN5 : CX_PHY_NB_GEN5>8) ? 32 :
15
Enabled: CX_S_CPCIE_MODE || CX_SEL_PHY_MODE
Parameter Type: Register Default Setting
Parameter Name: CX_NFTS

NFTS when using common clock Specifies the number of Fast Training Sequences (NFTS) the controller advertises
during link training, when common clock configuration is set.
This parameter sets the default value of the 'Common Clock N_FTS' field of the 'Ack
Frequency and L0-L1 ASPM Control Register' in the Register section of the Databook.
Common Clock operation cannot be fully enabled (through the Common Clock
Configuration field of the Link Control register) unless you observe the following
configuration parameter relationships:
■ CX_NFTS != CX_COMM_NFTS
■ DEFAULT_L0S_EXIT_LATENCY != DEFAULT_COMM_L0S_EXIT_LATENCY
■ DEFAULT_L1_EXIT_LATENCY != DEFAULT_COMM_L1_EXIT_LATENCY
Default value is set automatically unless Custom PHY or Sample PHY is used. M-PCIe
doesn't use this parameter.
Values: 1, ..., 255
Default Value: CX_NFTS
Enabled: CX_CPCIE_ENABLE && SLOT_CLK_CONFIG
Parameter Type: Register Default Setting
Parameter Name: CX_COMM_NFTS

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PCI Express SW Controller Databook Advanced PHY Config / PHY Timing Parameters

Label Description

NFTS Sequences at 5 Gb/s Specifies the number of Fast Training Sequences (NFTS) the controller advertises
during link training when running at Gen 2 speed. This is used to inform the link
partner the cores ability to recover synchronization after a low power state. This
number should come from your PHY vendor. This parameter is for Conventional PCIe
mode only; M-PCIe doesn't use this parameter.
Values: 0, ..., 255
Default Value: CX_NFTS
Enabled: (CX_CPCIE_ENABLE && (CX_GEN2_SPEED == 1))
Parameter Type: Feature Setting
Parameter Name: DEFAULT_GEN2_N_FTS

PHY Tx Delay PHY Transmitter delay in clock cycles. This must be specified by your PHY provider
and is the (worst case) delay in PIPE clock cycles from the PIPE interface to the TX
Phy serial pins. This parameter in conjunction with 'PHY Rx Delay' is used to calculate
the delay in getting an ACK DLLP back from the link partner, for a TLP sent by your
core. It is then used to calculate the size of the Retry Buffer. This parameter is for
Conventional PCIe mode only; M-PCIe doesn't use this parameter.
Values: 0, ..., 500
Default Value: 6
Enabled: CX_S_CPCIE_MODE || CX_SEL_PHY_MODE
Parameter Type: Feature Setting
Parameter Name: CX_PHY_TX_DELAY_PHY

PHY Rx Delay PHY Receiver delay in clock cycles. This must be specified by your PHY provider and
is the (worst case) delay in PIPE clock cycles from the RX Phy serial pins to the PIPE
interface. This parameter in conjunction with 'PHY Tx Delay' is used to calculate the
delay in getting an ACK DLLP back from the link partner, for a TLP sent by your
controller It is then used to calculate the size of the Retry Buffer. This parameter is for
Conventional PCIe mode only ; M-PCIe doesn't use this parameter.
Values: 0, ..., 500
Default Value: 14
Enabled: CX_S_CPCIE_MODE || CX_SEL_PHY_MODE
Parameter Type: Feature Setting
Parameter Name: CX_PHY_RX_DELAY_PHY

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Advanced PHY Config / Gen3 PHY Equalization Config Parameters PCI Express SW Controller Databook

6.46 Advanced PHY Config / Gen3 PHY Equalization Config Parameters


Table 6-46 Advanced PHY Config / Gen3 PHY Equalization Config Parameters

Label Description

General Config

Gen3 controller as EQ Master When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the
Asserts RxEqEval for PHY to do PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset
Rx adaptation and Evaluation request.
Regardless of Rx TS1s Detection This is the default of the RXEQ_RGRDLESS_RXTS field in GEN3_RELATED_OFF
when in Gen3 mode.
Values:
■ No (0)
■ Yes (1)
Default Value: Yes
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_RXEQ_RGRDLESS_RXTS

Gen3 EQ Include Initial FOM Gen3 EQ Include Initial FOM. Include or not the FOM feedback from the initial preset
evaluation performed in the EQ Master, when finding the highest FOM among all
preset evaluations.
■ 0: Do not include
■ 1: Include
This is the default of the GEN3_EQ_FOM_INC_INITIAL_EVAL field in
GEN3_EQ_CONTROL_OFF when in Gen3 mode.
Values: 0, 1
Default Value: 0
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FOM_INC_INITIAL_EVAL

Gen3 EQ Preset Request Vector Gen3 EQ Preset Request Vector. Requesting of Presets during the initial part of the
EQ Master Phase. Encoding scheme is as follows:
■ Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase.
■ Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase.
This is the default of the GEN3_EQ_PSET_REQ_VEC field in
GEN3_EQ_CONTROL_OFF when in Gen3 mode. You must contact your PHY vendor
to ensure 24 ms timeout does not occur in presets (FOM) requests in EQ master
phase.
Values: 0x0, ..., 0x7ff
Default Value: 0x59f
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_PSET_REQ_VEC

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PCI Express SW Controller Databook Advanced PHY Config / Gen3 PHY Equalization Config Parameters

Label Description

Gen3 EQ Feedback Mode Gen3 EQ Feedback Mode.


■ 0000b: Direction Change. Figure Of Merit method is also used by setting "Preset
Request Vector".
■ 0001b: Figure Of Merit. Only Figure Of Merit method is used.
■ 0010b: Reserved
■ ...... Reserved
■ 1111b: Reserved
This is the default of the GEN3_EQ_FB_MODE field in GEN3_EQ_CONTROL_OFF
when in Gen3 mode.
Values:
■ Direction Change (0)
■ Figure Of Merit (1)
Default Value: CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FB_MODE

Gen3 EQ Master Phase Exit Gen3 EQ Master Phase Exit Mode After 24 ms Timeout
Mode ■ 0b: Exit to Recovery.Speed state
■ 1b: Exit to EQ Phase 3 for USP controller or Recovery.RcvrLock state for DSP core
This is the default of the GEN3_EQ_PHASE23_EXIT_MODE field in
GEN3_EQ_CONTROL_OFF when in Gen3 mode. Setting to '1b' affects Direction
Change EQ Feedback Mode. EQ requests for Figure Of Merit mode complete before
24 ms timeout. See DEFAULT_GEN3_EQ_PSET_REQ_VEC for more.
Values:
■ To Recovery.Speed (0)
■ To EQ 3 for USP or to Recovery.RcvrLock for DSP (1)
Default Value: To Recovery.Speed
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_PHASE23_EXIT_MODE

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Label Description

Programmable Table Mode

Gen3/Gen4/Gen5 EQ Presets to For Gen3/Gen4/Gen5 equalization, there are three possible implementations for the
Coefficients Mapping Modes mapping of presets to coefficients:
■ Dynamic PHY: The coefficients are dynamically mapped in the PHY.
■ Dynamic MAC: The coefficients are dynamically mapped in the MAC.
■ Programmable Table: The coefficients are programmed in a table by your applica-
tion.
The coefficients obtained from a preset are then used to drive the
mac_phy_txdeemph[17:0] output in the transmit path of the relevant port.
Note:Gen3 and Gen4 cannot use different mapping modes.
Values:
■ Dynamic PHY (0)
■ Dynamic MAC (1)
■ Programmable Table (2)
Default Value: Dynamic PHY
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Feature Setting
Parameter Name: CX_GEN3_EQ_PSET_COEF_MAP_MODE

Gen3 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local FS Value Table, this parameter is used to set the default local Full Swing (FS) value for Gen3
data rate. The FS value is specific to the PHY implementation. It is needed by the
controller because it is advertised during Gen3 equalization Phase 1, and it is used to
determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section 4.2.3.1 of the PCI Express Base Specification, Rev 3.0. This is
the default of the GEN3_EQ_LOCAL_FS field in GEN3_EQ_LOCAL_FS_LF_OFF
when in Gen3 mode.
Values: 12, ..., 63
Default Value: 48
Enabled: CX_GEN3_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_LOCAL_FS

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PCI Express SW Controller Databook Advanced PHY Config / Gen3 PHY Equalization Config Parameters

Label Description

Gen3 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local LF Value Table, this parameter is used to set the default local Low Frequency (LF) value for
Gen3 data rate. The LF value is specific to the PHY implementation. It is needed by
the controller because it is advertised during Gen3 equalization Phase1, and it is used
to determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section 4.2.3.1 of the PCI Express Base Specification, Rev 3.0. This is
the default of the GEN3_EQ_LOCAL_LF field in GEN3_EQ_LOCAL_FS_LF_OFF
when in Gen3 mode.
Values: 0, ..., 63
Default Value: 24
Enabled: CX_GEN3_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_LOCAL_LF

Coefficient Convergence Mode

Gen3 EQ Coefficient When enabled the controller implements additional logic for checking that the fine
Convergence Support tuning process of the remote transmitter that is executed during Phase 2 (when
controller is USP) or Phase 3 (core is DSP) is converging toward a stable point. This
setting is both for Gen3 and Gen4. Gen3 and Gen4 cannot have different settings.
Values:
■ false (0)
■ true (1)
Default Value: CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Feature Setting
Parameter Name: CX_GEN3_EQ_COEF_CONV_SUPPORTED

Gen3 EQ Coefficient When Equalization Convergence Support


Convergence Queue Depth (CX_GEN3_EQ_COEF_CONV_SUPPORTED) is enabled , this parameter provides
the depth of the queue used to store the coefficients in use by the remote transmitter in
successive evaluation cycles. The queue is used to check if the successive coefficient
values are converging toward a stable value. This setting is both for Gen3 and Gen4.
Gen3 and Gen4 cannot have different setting.
Values: 2, ..., 16
Default Value: 2
Enabled: (CX_GEN3_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Feature Setting
Parameter Name: CX_GEN3_EQ_COEFQ_DEPTH

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Label Description

Gen3 EQ Convergence Window Gen3 EQ Convergence Window Aperture for C+1. Post-cursor coefficients maximum
Aperture for C+1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen3 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN3_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA

Gen3 EQ Convergence Window Gen3 EQ Convergence Window Aperture for C-1. Pre-cursor coefficients maximum
Aperture for C-1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen3 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN3_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA

Gen3 EQ Convergence Window Gen3 EQ Convergence Window Depth. Number of consecutive evaluations
Depth considered in Phase 2/3 when determining if optimal coefficients have been found.
This is the default of the GEN3_EQ_FMDC_N_EVALS field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen3 mode.
Values: 0, ..., 16
Default Value: 2
Enabled: (CX_GEN3_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FMDC_N_EVALS

Gen3 EQ Minimum Time (in ms) Gen3 EQ Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in
To Remain in EQ Master Phase EQ Master phase for at least this amount of time, before starting to check for
convergence of the coefficients. This is the default of the
GEN3_EQ_FMDC_T_MIN_PHASE23 field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen3 mode.
Values: 0, ..., 24
Default Value: 0
Enabled: (CX_GEN3_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FMDC_T_MIN_PHASE23

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PCI Express SW Controller Databook Advanced PHY Config / Gen4 PHY Equalization Config Parameters

6.47 Advanced PHY Config / Gen4 PHY Equalization Config Parameters


Table 6-47 Advanced PHY Config / Gen4 PHY Equalization Config Parameters

Label Description

General Config

Gen4 controller as EQ Master When set to '1', the controller as Gen4 EQ master asserts RxEqEval to instruct the
Asserts RxEqEval for PHY to do PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset
Rx Adaptation and Evaluation request.
Regardless of Rx TS1s Detection This is the default of the RXEQ_RGRDLESS_RXTS field in GEN3_RELATED_OFF
when in Gen4 mode.
Values:
■ No (0)
■ Yes (1)
Default Value: Yes
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_RXEQ_RGRDLESS_RXTS

Gen4 EQ Include Initial FOM Gen4 EQ Include Initial FOM. Include or not the FOM feedback from the initial preset
evaluation performed in the EQ Master, when finding the highest FOM among all
preset evaluations.
■ 0: Do not include
■ 1: Include
This is the default of the GEN3_EQ_FOM_INC_INITIAL_EVAL field in
GEN3_EQ_CONTROL_OFF when in Gen4 mode.
Values: 0, 1
Default Value: 0
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FOM_INC_INITIAL_EVAL

Gen4 EQ Preset Request Vector Gen4 EQ Preset Request Vector. Requesting of Presets during the initial part of the
EQ Master Phase. Encoding scheme is as follows:
■ Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase.
■ Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase.
This is the default of the GEN3_EQ_PSET_REQ_VEC field in
GEN3_EQ_CONTROL_OFF when in Gen4 mode. You must contact your PHY vendor
to ensure 24 ms timeout does not occur in presets (FOM) requests in EQ master
phase.
Values: 0x0, ..., 0x7ff
Default Value: 0x59f
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_PSET_REQ_VEC

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Label Description

Gen4 EQ Feedback Mode Gen4 EQ Feedback Mode.


■ 0000b: Direction Change. Figure Of Merit method is also used by setting "Preset
Request Vector".
■ 0001b: Figure Of Merit. Only Figure Of Merit method is used.
■ 0010b: Reserved
■ ...... Reserved
■ 1111b: Reserved
This is the default of the GEN3_EQ_FB_MODE field in GEN3_EQ_CONTROL_OFF
when in Gen4 mode.
Values:
■ Direction Change (0)
■ Figure Of Merit (1)
Default Value: CX_GEN4_MODE != GEN4_DISABLED
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FB_MODE

Gen4 EQ Master Phase Exit Gen4 EQ Master Phase Exit Mode After 24 ms Timeout
Mode ■ 0b: Exit to Recovery.Speed state
■ 1b: Exit to EQ Phase 3 for USP controller or Recovery.RcvrLock state for DSP core
This is the default of the GEN3_EQ_PHASE23_EXIT_MODE field in
GEN3_EQ_CONTROL_OFF when in Gen4 mode. Setting to '1b' affects Direction
Change EQ Feedback Mode. EQ requests for Figure Of Merit mode complete before
24 ms timeout. See DEFAULT_GEN4_EQ_PSET_REQ_VEC for more.
Values:
■ To Recovery.Speed (0)
■ To EQ 3 for USP or to Recovery.RcvrLock for DSP (1)
Default Value: To Recovery.Speed
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_PHASE23_EXIT_MODE

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PCI Express SW Controller Databook Advanced PHY Config / Gen4 PHY Equalization Config Parameters

Label Description

Programmable Table Mode

Gen4 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local FS Value Table, this parameter is used to set the default local Full Swing (FS) value for Gen4
data rate. The FS value is specific to the PHY implementation. It is needed by the
controller because it is advertised during Gen4 equalization Phase 1, and it is used to
determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section TBD of the PCI Express Base Specification, Rev 4.0. This is the
default of the GEN3_EQ_LOCAL_FS field in GEN3_EQ_LOCAL_FS_LF_OFF when
in Gen4 mode.
Values: 12, ..., 63
Default Value: 48
Enabled: CX_GEN4_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_LOCAL_FS

Gen4 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local LF Value Table, this parameter is used to set the default local Low Frequency (LF) value for
Gen4 data rate. The LF value is specific to the PHY implementation. It is needed by
the controller because it is advertised during Gen4 equalization Phase1, and it is used
to determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section TBD of the PCI Express Base Specification, Rev 4.0. This is the
default of the GEN3_EQ_LOCAL_LF field in GEN3_EQ_LOCAL_FS_LF_OFF when in
Gen4 mode.
Values: 0, ..., 63
Default Value: 24
Enabled: CX_GEN4_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_LOCAL_LF

Coefficient Convergence Mode

Gen4 EQ Convergence Window Gen4 EQ Convergence Window Aperture for C+1. Post-cursor coefficients maximum
Aperture for C+1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen4 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN4_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FMDC_MAX_POST_CUSROR_DELTA

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Label Description

Gen4 EQ Convergence Window Gen4 EQ Convergence Window Aperture for C-1. Pre-cursor coefficients maximum
Aperture for C-1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen4 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN4_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FMDC_MAX_PRE_CUSROR_DELTA

Gen4 EQ Convergence Window Gen4 EQ Convergence Window Depth. Number of consecutive evaluations
Depth considered in Phase 2/3 when determining if optimal coefficients have been found.
This is the default of the GEN3_EQ_FMDC_N_EVALS field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen4 mode.
Values: 0, ..., 16
Default Value: 2
Enabled: (CX_GEN4_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FMDC_N_EVALS

Gen4 EQ Minimum Time (in ms) Gen4 EQ Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in
To Remain in EQ Master Phase EQ Master phase for at least this amount of time, before starting to check for
convergence of the coefficients. This is the default of the
GEN3_EQ_FMDC_T_MIN_PHASE23 field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen4 mode.
Values: 0, ..., 24
Default Value: 0
Enabled: (CX_GEN4_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FMDC_T_MIN_PHASE23

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PCI Express SW Controller Databook Advanced PHY Config / Gen5 PHY Equalization Config Parameters

6.48 Advanced PHY Config / Gen5 PHY Equalization Config Parameters


Table 6-48 Advanced PHY Config / Gen5 PHY Equalization Config Parameters

Label Description

General Config

Gen5 controller as EQ Master When set to '1', the controller as Gen5 EQ master asserts RxEqEval to instruct the
Asserts RxEqEval for PHY to do PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset
Rx Adaptation and Evaluation request.
Regardless of Rx TS1s Detection This is the default of the RXEQ_RGRDLESS_RXTS field in GEN3_RELATED_OFF
when in Gen5 mode.
Values:
■ No (0)
■ Yes (1)
Default Value: Yes
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_RXEQ_RGRDLESS_RXTS

Gen5 EQ Include Initial FOM Gen5 EQ Include Initial FOM. Include or not the FOM feedback from the initial preset
evaluation performed in the EQ Master, when finding the highest FOM among all
preset evaluations.
■ 0: Do not include
■ 1: Include
This is the default of the GEN3_EQ_FOM_INC_INITIAL_EVAL field in
GEN3_EQ_CONTROL_OFF when in Gen5 mode.
Values: 0, 1
Default Value: 0
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FOM_INC_INITIAL_EVAL

Gen5 EQ Preset Request Vector Gen5 EQ Preset Request Vector. Requesting of Presets during the initial part of the
EQ Master Phase. Encoding scheme is as follows:
■ Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase.
■ Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase.
This is the default of the GEN3_EQ_PSET_REQ_VEC field in
GEN3_EQ_CONTROL_OFF when in Gen5 mode. You must contact your PHY vendor
to ensure 24 ms timeout does not occur in presets (FOM) requests in EQ master
phase.
Values: 0x0, ..., 0x7ff
Default Value: 0x59f
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_PSET_REQ_VEC

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Label Description

Gen5 EQ Feedback Mode Gen5 EQ Feedback Mode.


■ 0000b: Direction Change. Figure Of Merit method is also used by setting "Preset
Request Vector".
■ 0001b: Figure Of Merit. Only Figure Of Merit method is used.
■ 0010b: Reserved
■ ...... Reserved
■ 1111b: Reserved
This is the default of the GEN3_EQ_FB_MODE field in GEN3_EQ_CONTROL_OFF
when in Gen5 mode.
Values:
■ Direction Change (0)
■ Figure Of Merit (1)
Default Value: CX_MAX_PCIE_SPEED >= 5
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FB_MODE

Gen5 EQ Master Phase Exit Gen5 EQ Master Phase Exit Mode After 24 ms Timeout
Mode ■ 0b: Exit to Recovery.Speed state
■ 1b: Exit to EQ Phase 3 for USP controller or Recovery.RcvrLock state for DSP core
This is the default of the GEN3_EQ_PHASE23_EXIT_MODE field in
GEN3_EQ_CONTROL_OFF when in Gen5 mode. Setting to '1b' affects Direction
Change EQ Feedback Mode. EQ requests for Figure Of Merit mode complete before
24 ms timeout. See DEFAULT_GEN5_EQ_PSET_REQ_VEC for more.
Values:
■ To Recovery.Speed (0)
■ To EQ 3 for USP or to Recovery.RcvrLock for DSP (1)
Default Value: To Recovery.Speed
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_PHASE23_EXIT_MODE

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PCI Express SW Controller Databook Advanced PHY Config / Gen5 PHY Equalization Config Parameters

Label Description

Programmable Table Mode

Gen5 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local FS Value Table, this parameter is used to set the default local Full Swing (FS) value for Gen5
data rate. The FS value is specific to the PHY implementation. It is needed by the
controller because it is advertised during Gen5 equalization Phase 1, and it is used to
determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section TBD of the PCI Express Base Specification, Rev 5.0. This is the
default of the GEN3_EQ_LOCAL_FS field in GEN3_EQ_LOCAL_FS_LF_OFF when
in Gen5 mode.
Values: 12, ..., 63
Default Value: 48
Enabled: CX_GEN5_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_LOCAL_FS

Gen5 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local LF Value Table, this parameter is used to set the default local Low Frequency (LF) value for
Gen5 data rate. The LF value is specific to the PHY implementation. It is needed by
the controller because it is advertised during Gen5 equalization Phase1, and it is used
to determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section TBD of the PCI Express Base Specification, Rev 5.0. This is the
default of the GEN3_EQ_LOCAL_LF field in GEN3_EQ_LOCAL_FS_LF_OFF when in
Gen5 mode.
Values: 0, ..., 63
Default Value: 24
Enabled: CX_GEN5_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_LOCAL_LF

Coefficient Convergence Mode

Gen5 EQ Convergence Window Gen5 EQ Convergence Window Aperture for C+1. Post-cursor coefficients maximum
Aperture for C+1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen5 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN5_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FMDC_MAX_POST_CUSROR_DELTA

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Label Description

Gen5 EQ Convergence Window Gen5 EQ Convergence Window Aperture for C-1. Pre-cursor coefficients maximum
Aperture for C-1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen5 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN5_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FMDC_MAX_PRE_CUSROR_DELTA

Gen5 EQ Convergence Window Gen5 EQ Convergence Window Depth. Number of consecutive evaluations
Depth considered in Phase 2/3 when determining if optimal coefficients have been found.
This is the default of the GEN3_EQ_FMDC_N_EVALS field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen5 mode.
Values: 0, ..., 16
Default Value: 2
Enabled: (CX_GEN5_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FMDC_N_EVALS

Gen5 EQ Minimum Time (in ms) Gen5 EQ Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in
To Remain in EQ Master Phase EQ Master phase for at least this amount of time, before starting to check for
convergence of the coefficients. This is the default of the
GEN3_EQ_FMDC_T_MIN_PHASE23 field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen5 mode.
Values: 0, ..., 24
Default Value: 0
Enabled: (CX_GEN5_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FMDC_T_MIN_PHASE23

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PCI Express SW Controller Databook Advanced PHY Config / PHY Lane Margining Config Parameters

6.49 Advanced PHY Config / PHY Lane Margining Config Parameters


Table 6-49 Advanced PHY Config / PHY Lane Margining Config Parameters

Label Description

Lane Margining

Number of Time Steps from Number of time steps from default (MNumTimingSteps). This is an implementation
Default (MNumTimingSteps) specific parameter specified in PCI Express Base Specification. Contact your PHY
vendor for the value that you should use.
Values: 6, ..., 63
Default Value: 6
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_NUM_TIMING_STEPS

Offset from Default at Maximum Offset from default at maximum step value (MMaxTimingOffset). This is an
Step Value (MMaxTimingOffset) implementation specific parameter specified in PCI Express Base Specification.
Contact your PHY vendor for the value that you should use.
Values: 0, ..., 50
Default Value: 20
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_MAX_TIMING_OFFSET

Number of Voltage Steps from Number of voltage steps from default (MNumVoltageSteps). This is an implementation
Default (MNumVoltageSteps) specific parameter specified in PCI Express Base Specification. Contact your PHY
vendor for the value that you should use.
Values: 32, ..., 127
Default Value: 32
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_NUM_VOLTAGE_STEPS

Offset from Default at Maximum Offset from default at maximum step value as percentage of one volt
Step Value as Percentage of One (MMaxVoltageOffset). This is an implementation specific parameter specified in PCI
Volt (MMaxVoltageOffset) Express Base Specification. Contact your PHY vendor for the value that you should
use.
Values: 0, ..., 50
Default Value: 5
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_MAX_VOLTAGE_OFFSET

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Advanced PHY Config / PHY Lane Margining Config Parameters PCI Express SW Controller Databook

Label Description

The Ratio of Bits Tested to Bits The ratio of bits tested to bits received during voltage margining
Received During Voltage (MSamplingRateVoltage). This is an implementation specific parameter specified in
Margining PCI Express Base Specification. Contact your PHY vendor for the value that you
(MSamplingRateVoltage) should use. Note that if MIndErrorSampler = 0, the core always reports
MSamplingRateVoltage=0x3F regardless of this parameter value when the core
receives Report MSamplingRateVoltage Command from System Software.
Values: 0, ..., 63
Default Value: 0
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_SAMPLE_RATE_VOLTAGE

The Ratio of Bits Tested to Bits The ratio of bits tested to bits received during timing margining
Received During Timing (MSamplingRateTiming). This is an implementation specific parameter specified in
Margining PCI Express Base Specification. Contact your PHY vendor for the value that you
(MSamplingRateTiming) should use. Note that if MIndErrorSampler = 0, the core always reports
MSamplingRateTiming=0x3F regardless of this parameter value when the core
receives Report MSamplingRateTiming Command from System Software.
Values: 0, ..., 63
Default Value: 0
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_SAMPLE_RATE_TIMING

Voltage Margining Supported Voltage margining is supported (MVoltageSupported). This is an implementation


(MVoltageSupported) specific parameter specified in PCI Express Base Specification. Contact your PHY
vendor for the value that you should use.
Values: 0, 1
Default Value: 1
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_VOLTAGE_SUPPORTED

Independent Left/Right Timing Independent left/right timing margin supported (MIndLeftRightTiming). This is an
Margin Supported implementation specific parameter specified in PCI Express Base Specification.
(MIndLeftRightTiming) Contact your PHY vendor for the value that you should use.
Values: 0, 1
Default Value: 1
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_IND_LEFT_RIGHT_TIMING

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PCI Express SW Controller Databook Advanced PHY Config / PHY Lane Margining Config Parameters

Label Description

Independent Up and Down Independent up and down voltage margining supported (MIndUpDownVoltage). This is
Voltage Margining Supported an implementation specific parameter specified in PCI Express Base Specification.
(MIndUpDownVoltage) Contact your PHY vendor for the value that you should use.
Values: 0, 1
Default Value: 1
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_IND_UP_DOWN_VOLTAGE

Independent Error Sampler Indicates Error sampler is independent (MIndErrorSampler). This is an implementation
(MIndErrorSampler) specific parameter specified in PCI Express Base Specification. Contact your PHY
vendor for the value that you should use.
Values: 0, 1
Default Value: 1
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_IND_ERROR_SAMPLER

Sample Reporting Method Indicates whether a sample frequency is supported (1) or a sample count is supported
(MSampleReportingMethod) (0) (MSampleReportingMethod). This is an implementation specific parameter
specified in PCI Express Base Specification. Contact your PHY vendor for the value
that you should use. Note that if MIndErrorSampler = 0, the core always reports
MSampleReportingMethod=1 regardless of this parameter value when the core
receives Report Margin Control Capabilities Command from System Software.
Values: 0, 1
Default Value: 0
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_SAMPLE_REPORTING_METHOD

Maximum Number of Lanes that Maximum number of lanes minus 1 that can be margined at the same time
can be Margined at the Same (MMaxLanes). This is an implementation specific parameter specified in PCI Express
Time (MMaxLanes) Base Specification. Contact your PHY vendor for the value that you should use.
Values: 0, ..., 31
Default Value: 1
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_MAXLANES

Margining Uses Driver Software Default value of Margining Uses Driver Software. This is an implementation specific
parameter specified in PCI Express Base Specification. Contact your PHY vendor for
the value that you should use.
Values: 0, 1
Default Value: 0
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_MARGINING_USES_DRIVER_SOFTWARE

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Advanced PHY Config / PHY Message Bus Config Parameters PCI Express SW Controller Databook

6.50 Advanced PHY Config / PHY Message Bus Config Parameters


Table 6-50 Advanced PHY Config / PHY Message Bus Config Parameters

Label Description

Message Bus

RX Message Bus Write Buffer Default value of RX Message Bus Write Buffer Depth. This is an implementation
Depth specific parameter specified in PIPE Specification. Contact your PHY vendor for the
value that you should use.
Values: 0, ..., 15
Default Value: (CX_PIPE51_SUPPORT) ? 5 : (CX_PIPE44_SUPPORT) ? 2 : 0
Enabled: (CX_GEN4_SPEED && CX_PIPE44_SUPPORT) || CX_PIPE51_SUPPORT
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH

TX Message Bus Min Write Default value of TX Message Bus Minimum Write Buffer Depth. This is an
Buffer Depth implementation specific parameter specified in PIPE Specification. Contact your PHY
vendor for the value that you should use.
Values: 0, ..., 8
Default Value: (CX_PIPE51_SUPPORT) ? 5 : (CX_PIPE44_SUPPORT) ? 2 : 0
Enabled: (CX_GEN4_SPEED && CX_PIPE44_SUPPORT) || CX_PIPE51_SUPPORT
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH

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PCI Express SW Controller Databook Advanced Transmit Config Parameters

6.51 Advanced Transmit Config Parameters


Table 6-51 Advanced Transmit Config Parameters

Label Description

Advanced Transmit Config

CX_BLOCK_VDM_TLP Block transmit of VDM Messages when in a non-D0 state. For more details, see the
'Power Management' section of the Architecture chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_BLOCK_VDM_TLP

Block CCIX Transmit Interface Block outbound transactions on CCIX interface when in low power modes. For more
details, see the 'Power Management' section of the Architecture chapter of the
Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: AMBA_INTERFACE==0 && CC_DEVICE_TYPE!=CC_RC &&
CX_CCIX_INTERFACE_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: CX_CCIX_BLOCK_NEW_TLP

General Config

Block Client 0 Interface Block outbound transactions on XALI0 when in low power modes. For more details,
see the 'Power Management' section of the Architecture chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_CLIENT0_BLOCK_NEW_TLP

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Advanced Transmit Config Parameters PCI Express SW Controller Databook

Label Description

Block Client 1 Interface Block outbound transactions on XALI1 when in low power modes. For more details,
see the 'Power Management' section of the Architecture chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_CLIENT1_BLOCK_NEW_TLP

Block Client 2 Interface Block outbound transactions on XALI2 when in low power modes. For more details,
see the 'Power Management' section of the Architecture chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_CLIENT2_BLOCK_NEW_TLP

Populate ports for available credit Include top-level ports to provide available credit information to the application. For
buses more details, see 'SII: Transmit Control Signals' section of the Databook. This
parameter enables the population of output ports for application monitoring of run-time
available credit information for VCn buses:
■ xadm_ph_cdts [NVC*8-1:0] : available VC0-VCn header posted credits
■ xadm_nph_cdts [NVC*8-1:0] : available VC0-VCn header non-posted credits
■ xadm_cplh_cdts [NVC*8-1:0] : available VC0-VCn header completion credits
■ xadm_pd_cdts [NVC*12-1:0] : available VC0-VCn data posted credits
■ xadm_npd_cdts [NVC*12-1:0] : available VC0-VCn data non-posted credits
■ xadm_cpld_cdts [NVC*12-1:0] : available VC0-VCn data completion credits
Information for lower order VCs is presented on the lower-order bits.
Values: 0, 1
Default Value: 0
Enabled: ((AMBA_INTERFACE==0))
Parameter Type: Feature Setting
Parameter Name: XADM_CRD_EN

Client Interface TLP pullback Enable the transmit clients to cancel a TLP that is currently submitted for transmission.
feature Values:
■ false (0)
■ true (1)
Default Value: (CC_DMA_ENABLE && (AMBA_INTERFACE!=0)) ? 1 : 0
Enabled: ((AMBA_INTERFACE==0))
Parameter Type: Feature Setting
Parameter Name: CLIENT_PULLBACK

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PCI Express SW Controller Databook Advanced Transmit Config Parameters

Label Description

VC-Based Transmit Arbitration

Transmit Client Arbitration Selects the arbitration method for transmitted TLPs, as described in the "Transmit TLP
Scheme Arbitration" section of the Databook.
■ 0: VC Based. Provides a VC based programmable weighted round robin arbitration
(WRR) using two different arbitration methods for the two groups of VCs.
■ 1: Round Robin (RR). Provides round robin arbitration between the three transmit
clients. This is the default method.
■ 2: Strict Priority. Provides strict priority between the three transmit clients. XALI0 is
lowest, XALI1 is higher, XALI2 (if implemented) is highest.
You can only change this parameter when CX_NVC >1.
Values:
■ VC Based (0)
■ Round Robin (1)
■ Strict Priority (2)
Default Value: Round Robin
Enabled: CX_NVC > 1
Parameter Type: Feature Setting
Parameter Name: CX_XADM_ARB_MODE

Enable LPVC WRR Weights Determines whether the WRR arbitration VC weight values in VC Transmit Arbitration
Writable Register 1 and VC Transmit Arbitration Register 2 (in the register section of the
Databook) are writable through the DBI.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: CX_LPVC_WRR_WEIGHT_WRITABLE

VC ID #0 Weight WRR Weighting for VC ID #0. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0xf
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC0

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Advanced Transmit Config Parameters PCI Express SW Controller Databook

Label Description

VC ID #1 Weight WRR Weighting for VC ID #1. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC1

VC ID #2 Weight WRR Weighting for VC ID #2. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC2

VC ID #3 Weight WRR Weighting for VC ID #3. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC3

VC ID #4 Weight WRR Weighting for VC ID #4. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC4

VC ID #5 Weight WRR Weighting for VC ID #5. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC5

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PCI Express SW Controller Databook Advanced Transmit Config Parameters

Label Description

VC ID #6 Weight WRR Weighting for VC ID #6. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC6

VC ID #7 Weight WRR Weighting for VC ID #7. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC7

Transmit Completion

Compare Completion Credit Enable the controller to compare the actual size of a requested Completion (as
opposed to a maximum size Completion) against available Completion credits before
transmitting the Completion. This parameter saves gates and improves timing when
set to false.
■ Typically, an EP must have enough buffer space to receive all CPL data before it
sends a MRd transaction. Therefore, an RC may assume infinite CPL credits.
■ There is no need to compare the CPL length with available CPL credits. Therefore,
setting this parameter to false can save gate count by eliminating the compare
logic.
■ If a PCIe device has specific or more strict requirement for checking a peer compo-
nents CplD buffer capability, it sets a threshold that at least 8 CplD credits are avail-
able before a PCIe device can transmit a CPLD.
Values: 0, 1
Default Value: 1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CPL_LEN_CMP_ENABLE

Transmit Posted

Compare Posted Credit Enable the controller to compare the size of a requested posted payload length against
available posted credits before transmitting the posted TLP.
Values: 0, 1
Default Value: 1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: P_LEN_CMP_ENABLE

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Advanced Transmit Config Parameters PCI Express SW Controller Databook

Label Description

Application Credit Control

Populate ports to allow the Application credit control. For more details, see 'SII: Transmit Control Signals' section
application to control credit usage of the Databook. This parameter enables the application to control credits used
from internal MSG/CPL internally by the controller for internally generated MSG/CPL.
Values: 0, 1
Default Value: 0
Enabled: ((AMBA_INTERFACE==0) && (CX_CCIX_INTERFACE_ENABLE==0))
Parameter Type: Feature Setting
Parameter Name: APP_CREDIT_CTRL

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PCI Express SW Controller Databook Advanced Pipeline Config Parameters

6.52 Advanced Pipeline Config Parameters


Table 6-52 Advanced Pipeline Config Parameters

Label Description

Pipeline Latencies

RDLH TLP Extract Input Input pipeline stage to RDLH TLP extraction module
Values:
■ 0 (0)
■ 1 (1)
Default Value: 1
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RDLH_REGIN

Miscellaneous Pipeline Enables

CRC Pipeline Depth - XTLH CRC Pipeline Latency value for xtlh. This value represents the number of pipeline
stages needed to calculate and compare ECRC. core supported latencies: 1,2
Values:
■ 1 (1)
■ 2 (2)
Default Value: 1 + ((CX_NW > 1) ? ((CX_TECHNOLOGY == 0) || ((CX_GEN4_MODE
== GEN4_DF) && CX_NW==16) || (CX_MAX_CORECLK_FREQ > 500)) : 0)
Enabled: CX_CUSTOM_PIPELINING && (CX_NW > 1)
Parameter Name: CX_CRC_LATENCY_XTLH

CRC Pipeline Depth - RTLH CRC Pipeline Latency value for rtlh. This value represents the number of pipeline
stages needed to calculate and compare ECRC. core supported latencies: 1,2
Values:
■ 1 (1)
■ 2 (2)
Default Value: 1 + ((CX_NW > 1) ? ((CX_TECHNOLOGY == 0) || ((CX_GEN4_MODE
== GEN4_DF) && CX_NW==16) || (CX_MAX_CORECLK_FREQ > 500)) : 0)
Enabled: CX_CUSTOM_PIPELINING && (CX_NW > 1)
Parameter Name: CX_CRC_LATENCY_RTLH

CRC Pipeline Depth - XDLH CRC Pipeline Latency value for xdlh. This value represents the number of pipeline
stages needed to calculate and compare LCRC. core supported latencies: 1,2
Values:
■ 1 (1)
■ 2 (2)
Default Value: 1 + ((CX_NW > 1) ? ((CX_TECHNOLOGY == 0) || ((CX_GEN4_MODE
== GEN4_DF) && CX_NW==16) || ((CX_MAX_CORECLK_FREQ >= 500) &&
CX_RASDP > 0) || (CX_MAX_CORECLK_FREQ > 500)) : 0)
Enabled: CX_CUSTOM_PIPELINING && (CX_NW > 1)
Parameter Name: CX_CRC_LATENCY_XDLH

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Advanced Pipeline Config Parameters PCI Express SW Controller Databook

Label Description

CRC Pipeline Depth - RDLH CRC Pipeline Latency value for rdlh. This value represents the number of pipeline
stages needed to calculate and compare LCRC. core supported latencies: 1,2
Values:
■ 1 (1)
■ 2 (2)
Default Value: 1 + ((CX_NW > 1) ? ((CX_TECHNOLOGY == 0) || ((CX_GEN4_MODE
== GEN4_DF) && CX_NW==16) || (CX_MAX_CORECLK_FREQ > 500)) : 0)
Enabled: CX_CUSTOM_PIPELINING && (CX_NW > 1)
Parameter Name: CX_CRC_LATENCY_RDLH

LTSSM This parameter adds selected pipelines in the LTSSM, providing trade-off of latency
and gates for ease of timing closure. This parameter is for Conventional PCIe mode
only; M-PCIe doesn't use this parameter.
Values: 0, 1
Default Value: (CX_TECHNOLOGY == 0) && !CX_MPCIE_ENABLE
Enabled: CX_CUSTOM_PIPELINING && !CX_MPCIE_ENABLE
Parameter Type: Performance Setting
Parameter Name: CX_SMLH_PIPELINE_LTSSM

Retry Buffer Retry Buffer Pipeline Latency value. This value represents the number of pipeline
stages used in retry buffer, providing trade-off of latency and gates for ease of timing
closure.
Values: 0, 1
Default Value: (CX_TECHNOLOGY == 0) || ((CX_GEN2_MODE == 0) &&
(CX_FREQ == 1) && (ARC_WIDTH < 128))
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_XDLH_PIPELINE_RBUF

Transmit Flow Control Transmit Flow Control Calculations Pipeline Enable, providing trade-off of latency and
Calculations gates for ease of timing closure.
Values: 0, 1
Default Value: (CX_TECHNOLOGY == 0) || ((CX_GEN2_MODE == 0) &&
(CX_FREQ == 1) && (ARC_WIDTH == 32))
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_XADM_FC_PIPELINE

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PCI Express SW Controller Databook Advanced Pipeline Config Parameters

Label Description

Intermodule Pipeline Enables

Receive Serialization Queue Inserts a pipeline at the Receive Serialization Queue RAM write interface.
Write Pipeline Values: 0, 1
Default Value: CX_TECHNOLOGY==0 || (CX_MAX_CORECLK_FREQ >= 1000) ||
(CX_RASDP_EN && ((CX_GEN2_MODE==GEN2_DF && CX_FREQ==FREQ_250)
|| (CX_GEN3_MODE==GEN3_DF && CX_FREQ==FREQ_125) ||
(CX_GEN4_MODE==GEN4_DF && CX_FREQ==FREQ_62_5)))
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RADM_FORMQ_WR_REGOUT

Receive MAC Layer (RML) Specifies insertion of register pipeline at the inputs of RMLH Packet finder, providing
Packet Finder Input trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ([<functionof> CX_NB CX_NL] >= 128) ? (CX_GEN3_MODE == 0) ? 1
: ((CX_TECHNOLOGY == 0) ? 1 : 0) : 0
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RMLH_PKT_FINDER_REGIN

Receive MAC Layer (RML) PIPE Specifies insertion of register pipeline at the outputs of RMLH PIPE, providing trade-off
Output of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: (CX_MPCIE_ENABLE) ? 1 : (CX_TECHNOLOGY == 2) ? ((((CX_NB
== 1) || (CX_GEN2_SPEED)) & (CX_NL > 1)) ? 1:0) : 1
Enabled: CX_CUSTOM_PIPELINING && !CX_MPCIE_ENABLE
Parameter Type: Performance Setting
Parameter Name: CX_RMLH_PIPE_REGOUT

Receive MAC Layer (RML) Specifies insertion of register pipeline at the Input of Deskew, providing trade-off of
Deskew Input latency and gates for ease of timing closure.
Values: 0, 1
Default Value: 0
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RMLH_DESKEW_REGIN

Receive Data Link Layer (RDL) Specifies insertion of register pipeline at the outputs of RDLH TLP Extract, providing
TLP Extract Output trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0)) ? 1 : ((((CX_NB == 1) ||
(CX_2ND_SPEED)) & (CX_NL > 4)) ? 1: 0)
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RDLH_TLP_EXTRACT_REGOUT

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Advanced Pipeline Config Parameters PCI Express SW Controller Databook

Label Description

Receive Transaction Layer (RTL) Insert a pipeline at the output of the Receive Transaction Layer TLP extraction module.
TLP Extraction Values: 0, 1
Default Value: 1
Enabled: CX_RTLH_SIMPLE_EXTRACT && CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RTLH_TLP_EXTRACT_REGOUT

Receive Transaction Layer (RTL) Specifies insertion of a local register pipeline for Flow Control credit check calculation
TLP FC credit check in the Receive Transaction Layer TLP check module for ease of timing closure.
Values: 0, 1
Default Value: (CX_TECHNOLOGY == 0) || (CX_MAX_CORECLK_FREQ > 781)) &&
(CX_NW==16) && (CX_RASDP>2
Enabled: CX_RTLH_SIMPLE_EXTRACT && CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RTLH_FC_CHECK_REGOUT

Receive Header and Data Queue Insert a pipeline at the Receive Header and Data Queue RAM Write interfaces.
Write RAM Outputs Values: 0, 1
Default Value: CX_TECHNOLOGY==0 || (CX_MAX_CORECLK_FREQ > 500)
Enabled: CX_RADMQ_MODE==2 && CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RADM_RAM_WR_REGOUT

Receive Input Queue Manager Specifies insertion of register pipeline at the output of the receive queue input queue
Output manager before the receive queue RAM inputs, providing trade-off of latency and
gates for ease of timing closure.
Values: 0, 1
Default Value: 1
Enabled: CX_RADMQ_MODE==2
Parameter Type: Performance Setting
Parameter Name: CX_RADM_INQ_MGR_REGOUT

Transmit Transaction Layer (XTL) Specifies insertion of register pipeline at the outputs of XTLH, providing trade-off of
Output latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ((CX_ECRC_ENABLE == 1) || ((CX_RASDP > 0) && (CX_NW <= 2)))
? 1 : ((((CX_NB == 1) || (CX_2ND_SPEED)) & (CX_NL > 1)) ? 1: 0)
Enabled: (CX_CUSTOM_PIPELINING && !CX_ECRC_ENABLE &&
!((CX_RASDP>0) && (CX_NW <= 2)))
Parameter Type: Performance Setting
Parameter Name: CX_XTLH_CTRL_REGOUT

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PCI Express SW Controller Databook Advanced Pipeline Config Parameters

Label Description

Transmit Data Link Layer (XDL) Specifies insertion of register pipeline at the outputs of XDLH, providing trade-off of
Output latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0)) ? 1 : 1
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_XDLH_TLP_REGOUT

Transmit MAC Layer (XML) PIPE Specifies insertion of register pipeline at the outputs of XMLH PIPE, providing trade-off
Output of latency and gates for ease of timing closure. For M-PCIe, applies to the Layer1 to
PIPE RMMI adapter interface.
Values: 0, 1
Default Value: (CX_MPCIE_ENABLE)? 0 : ((CX_TECHNOLOGY == 0)) ? 1 : 0
Enabled: CX_CUSTOM_PIPELINING && !CX_MPCIE_ENABLE
Parameter Type: Performance Setting
Parameter Name: CX_XMLH_PIPE_REGOUT

Transmit MAC Layer (XML) Specifies insertion of register pipeline at the outputs of XMLH Precoding, providing
Precoding Output trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0)) ? 0 : 0
Enabled: CX_CUSTOM_PIPELINING && !CX_MPCIE_ENABLE &&
CX_GEN5_SPEED
Parameter Type: Performance Setting
Parameter Name: CX_XMLH_PRECODING_REGOUT

Error Log Output Specifies insertion of register pipeline at the Outputs Error Log, providing trade-off of
latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0) || (CX_SRIOV_ENABLE &&
CX_NVFUNC>32)) ? 1 : 0
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_ERROR_LOG_REGOUT

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Label Description

Receive Filter To Receive Queue Specifies insertion of register pipeline between receive filter and receive queue input
manager, providing trade-off of latency and gates for ease of timing closure.
Values: 0, ..., 2
Default Value: (CX_INTERNAL_ATU_ENABLE &&
((CX_ATU_NUM_INBOUND_REGIONS > 32 ) || (CX_RASDP!=0 &&
CX_MAX_CORECLK_FREQ > 500))) ? 2 :
ADDR_TRANSLATION_SUPPORT_EN||SATA_CAP_ENABLE||CX_GEN3_DYNAMIC
_FREQ
Enabled: (CX_CUSTOM_PIPELINING==1 &&
(ADDR_TRANSLATION_SUPPORT_EN==0 && SATA_CAP_ENABLE==0 ||
CX_INTERNAL_ATU_ENABLE))
Parameter Type: Performance Setting
Parameter Name: CX_FLT_Q_REGOUT

Radm_bypass pipeline Specifies insertion of register pipeline in the radm_bypass interface, providing trade-off
of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: CX_RASDP > 0) || (CX_MAX_CORECLK_FREQ > 500) ||
(CX_INTERNAL_ATU_ENABLE && AMBA_INTERFACE==0
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_RADM_BYPASS_REGOUT

XADM Hdr/Data Align To Output Specifies insertion of register pipeline before XADM output formation providing
Formation trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: (CX_INTERNAL_ATU_ENABLE &&
CX_ATU_NUM_OUTBOUND_REGIONS > 32) || (CX_RAS_DES_EINJ_ENABLE)
Enabled: CX_CUSTOM_PIPELINING==1
Parameter Type: Performance Setting
Parameter Name: CX_XADM_FORMATION_REGIN

Pfvf_to_vfindex To RADM Filter Specifies insertion of a local register pipeline for the pfvf_to_vfindex output in the
Output RADM_FILTER providing area trade off for ease of timing closure.
Values: 0, 1
Default Value: CX_CRC_LATENCY_RTLH && CX_SRIOV_ENABLE &&
CX_NVFUNC>32
Enabled: CX_CRC_LATENCY_RTLH && CX_SRIOV_ENABLE
Parameter Type: Performance Setting
Parameter Name: VFINDEX_CALC_REGOUT

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PCI Express SW Controller Databook Advanced Pipeline Config Parameters

Label Description

Rid_to_pfvf Inputs Specifies insertion of register pipeline for the rid_to_pfvf module inputs in the
RADM_FILTER and RADM_CPL_LUT blocks, providing trade-off of latency and gates
for ease of timing closure.
Values: 0, 1
Default Value: CX_SRIOV_ENABLE && DWC_PCIE_FPGA
Enabled: CX_CUSTOM_PIPELINING==1 && CX_SRIOV_ENABLE
Parameter Type: Performance Setting
Parameter Name: CX_RID_REGIN

Rid_to_pfvf Outputs Specifies insertion of register pipeline for the rid_to_pfvf module output in the
RADM_FILTER and RADM_CPL_LUT blocks, providing trade-off of latency and gates
for ease of timing closure.
Values: 0, 1
Default Value: CX_SRIOV_ENABLE || RADM_VFINDEX_REGOUT
Enabled: CX_CUSTOM_PIPELINING==1 && CX_ARI_ENABLE &&
!RADM_VFINDEX_REGOUT
Parameter Type: Performance Setting
Parameter Name: CX_RID_REGOUT

Vendor MSI Interface Inputs Specifies insertion of an input register pipeline for the Vendor MSI interface
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0) || (CX_SRIOV_ENABLE ==1)) ? 1 : 0
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_VEN_MSI_REGIN

Application Error Return Interface Specifies insertion of an input register pipeline for the Application Error Return
Inputs interface
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0) || (CX_SRIOV_ENABLE ==1) ||
(CX_MAX_CORECLK_FREQ > 500)) ? 1 : 0
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_APP_ERR_REGIN

Lane Flip RX Input Specifies insertion of register pipeline at the inputs of Lane Flip block signals from
PHY, providing trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: (CX_MAX_CORECLK_FREQ >= 500)
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_LANEFLIP_RX_REGIN

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Label Description

Lane Flip TX Output Specifies insertion of register pipeline at the outputs of Lane Flip block signals to PHY,
providing trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: (CX_MAX_CORECLK_FREQ >= 500)
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_LANEFLIP_TX_REGOUT

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PCI Express SW Controller Databook Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters

6.53 Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters
Table 6-53 Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters

Label Description

General Configuration

Enable Auto Size of Retry Buffer Enable or disable automatic size calculation for the retry buffer.:
■ True: Enable Auto Size: The sizes of the retry buffer and SOT buffer are automati-
cally calculated based on the "Maximum Payload Size Supported value", the link
width, and device latencies.
■ False: Disable Auto Size: Automatic buffer sizing is disabled. The value that you
enter for Retry Buffer Depth (CX_RBUF_DEPTH) directly sets the depth of the retry
buffer.
For more details, see the "Transmit Replay" section of the "Architecture" chapter of the
Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RBUF_AUTOSIZE

Internal Delay / Link Partner Read-only parameter that indicates the sum of the MAC/PHY delays, used for retry
Delay buffer auto-sizing, AckNak Timer adjustment and replay timer adjustment.
Values: 0, ..., 2048
Default Value: (CX_S_CPCIE_MODE) ? CX_CPCIE_INTERNAL_DELAY :
(CX_S_MPCIE_MODE) ? CM_MPCIE_INTERNAL_DELAY :
(CX_CPCIE_INTERNAL_DELAY > CM_MPCIE_INTERNAL_DELAY) ?
CX_CPCIE_INTERNAL_DELAY : CM_MPCIE_INTERNAL_DELAY
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_INTERNAL_DELAY

Total Retimer Latency (Symbol Read-only parameter that indicate total round trip Latency of Retimer calculated from
times) CX_MAX_RETIMER setting and reference Retimer latency table in PCIe Base Spec,
used for retry buffer auto-sizing.
Values: -2147483648, ..., 2147483647
Default Value: CX_RETIMER_LATENCY
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RETIMER_LATENCY2

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Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters PCI Express SW Controller Databook

Label Description

Retry Buffer Configuration

Retry Buffer Depth The depth of the retry buffer. When retry buffer auto-sizing is enabled
(CX_RBUF_AUTOSIZE), "Retry Buffer Depth" is read-only and indicates the
automatically calculated depth of the retry buffer. When retry buffer auto-sizing is
disabled, "Retry Buffer Depth" is the user-specified depth of the retry buffer. Note that
if the autosize feature is disabled, then the minimum value specified must be large
enough to allow normal operation. The default value is the automatically calculated
value. For more details, see the 'Transmit Replay' section of the Architecture chapter of
the Databook.
Values: SNPS_RSVDPARAM_30, ..., 4294967295
Default Value: [calc_rbuf_depth CX_DL_NB CX_NL CX_MAX_MTU
CX_ECRC_ENABLE CX_TLP_PREFIX_ENABLE_VALUE CX_NPRFX
CX_INTERNAL_DELAY CX_MAX_L0S_LTIME CX_GEN5_SPEED
CX_GEN4_SPEED CX_GEN3_SPEED CX_5GTS_SPEED
CX_RETIMER_LATENCY]
Enabled: ((!CX_RBUF_AUTOSIZE))
Parameter Type: Feature Setting
Parameter Name: CX_RBUF_DEPTH

Retry Buffer Width Read-only parameter that indicates the width of the retry buffer.
Values: 34, ..., 686
Default Value: RBUF_PROT_WD + [calc_rbuf_width CX_DL_NB CX_NL
CX_TLP_PREFIX_ENABLE CX_GEN3_SPEED]
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RBUF_WIDTH

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PCI Express SW Controller Databook Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters

Label Description

SOT Buffer Configuration

Minimum SOT Depth When retry buffer auto-sizing is enabled, the value displayed here corresponds to the
number of minimum-sized TLPs (3 DWORDs) that can reside in the retry buffer.
■ The 'Start Of TLP (SOT)' buffer stores the starting address of each unacknowl-
edged TLP stored in the retry buffer.
■ The SOT buffer requires one entry for each TLP that can be stored in the retry
buffer.
■ The selected retry buffer size determines the size of the SOT buffer.
■ The actual SOT buffer depth is a combination of the value displayed here and the
additional requirements that the actual SOT buffer depth must be at least 32 and
must be a power of 2.
When retry buffer auto-sizing is disabled, 'Minimum SOT Depth' is the user-specified
depth of the SOT buffer.
■ The selected size must allow the retry buffer to store the maximum number of
shortest TLPs (3 DWORDs).
■ The actual SOT buffer depth (SOTBUF_DEPTH) is calculated by adjusting
CX_SOTBUF_DEPTH to be at least 32, and rounding up to the next power-of-2.
For more details, see the 'Transmit Replay' section of the 'Architecture' chapter of the
Databook.
Values: -2147483648, ..., 2147483647
Default Value: [calc_sot_depth CX_DL_NB CX_NL CX_MAX_MTU
CX_ECRC_ENABLE CX_TLP_PREFIX_ENABLE_VALUE CX_NPRFX
CX_INTERNAL_DELAY CX_MAX_L0S_LTIME CX_GEN5_SPEED
CX_GEN4_SPEED CX_GEN3_SPEED CX_5GTS_SPEED
CX_RETIMER_LATENCY]
Enabled: ((CX_RBUF_AUTOSIZE==0))
Parameter Type: Feature Setting
Parameter Name: CX_SOTBUF_DEPTH

SOT Buffer Depth Read-only parameter that indicates the depth of the SOT buffer.
Values: 32, ..., 4294967295
Default Value: [calc_sotbuf_depth CX_DL_NB CX_NL CX_MAX_MTU
CX_ECRC_ENABLE CX_TLP_PREFIX_ENABLE_VALUE CX_NPRFX
CX_INTERNAL_DELAY CX_MAX_L0S_LTIME CX_RBUF_AUTOSIZE
CX_SOTBUF_DEPTH CX_GEN5_SPEED CX_GEN4_SPEED CX_GEN3_SPEED
CX_5GTS_SPEED CX_RETIMER_LATENCY]
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: SOTBUF_DEPTH

SOT Buffer Width Read-only parameter that indicates the width of the SOT buffer.
Values: 0, ..., 4294967295
Default Value: CX_RAS_EN ? ( CX_RAS_SOTBUF_PROT_WD +[calc_log2
CX_RBUF_DEPTH] ) : [calc_log2 CX_RBUF_DEPTH]
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: SOTBUF_WIDTH

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Advanced Buffer Config / Segmented-Buffer Options Parameters PCI Express SW Controller Databook

6.54 Advanced Buffer Config / Segmented-Buffer Options Parameters


Table 6-54 Advanced Buffer Config / Segmented-Buffer Options Parameters

Label Description

Segmented-Buffer Options

Receive VC Arbitration The VC arbitration scheme for sending received TLPs to your application.
■ Strict Priority: Higher number VC IDs have higher priority
■ Round Robin: Round robin arbitration between VCs
Notes:
■ This parameter is only applicable when CX_NVC > 1.
■ It is possible to change the VC Arbitration Scheme (during device setup by soft-
ware) by writing to the VC_ORDERING_RX_Q field in the VC0_P_RX_Q_C-
TRL_OFF register.
Values:
■ Round Robin (0x0)
■ Strict Priority (0x1)
Default Value: Round Robin
Enabled: CX_RADMQ_MODE==2
Parameter Type: Register Default Setting
Parameter Name: CX_RADM_STRICT_VC_PRIORITY

Enable Dynamic FC Credit Enable your application to update the advertised FC credit values by writing to the VC0
Adjustment Posted Receive Queue Control port logic register.
Values:
■ false (0)
■ true (1)
Default Value: FC_SCALE_EN
Enabled: CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: CX_DYNAMIC_FC_CREDIT

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PCI Express SW Controller Databook Advanced Buffer Config / Ordering Rules Configuration (Segmented-Buffer)

6.55 Advanced Buffer Config / Ordering Rules Configuration


(Segmented-Buffer) Parameters
Table 6-55 Advanced Buffer Config / Ordering Rules Configuration (Segmented-Buffer) Parameters

Label Description

Ordering Rules Configuration (Segmented-Buffer)

Support Relaxed Ordering Allows completions to be sent to your application out of order. For more details, see
Receive Queues in the Architecture chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RELAXED_ORDER_SUPPORT

Ordering Rules Specifies the ordering scheme for sending received TLPs to the application:
■ 0: Strict Priority: The priority order is Posted, then Completion, then Non-Posted
■ 1: PCI Ordering Rules: The arbitration is according to the ordering rules in the PCI
Express 3.1 Specification.
For more details, see the "Native Core Receive Ordering Schemes" section in the
"Advanced Ordering Information" appendix of the Databook. It is possible to change
the ordering rules used (by software) by writing to the appropriate queue control
register 'TLP Type Ordering'.
Values:
■ Strict Priority (0x0)
■ PCIe Ordering Rules (0x1)
Default Value: PCIe Ordering Rules
Enabled: CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: CX_RADM_ORDERING_RULES

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Advanced Buffer Config / Receive Serialization Queue Parameters PCI Express SW Controller Databook

6.56 Advanced Buffer Config / Receive Serialization Queue Parameters


Table 6-56 Advanced Buffer Config / Receive Serialization Queue Parameters

Label Description

Receive Serialization Queue

Enable Receive Serialization The Receive Serialization Queue Size Configuration feature applies to 512-bit data
Queue Size Configuration width configurations and allows the size of the serialization queue to be adjusted while
maintaining throughput at the application interface.
Values: 0, 1
Default Value: 0
Enabled: CX_NW==16
Parameter Type: Feature Setting
Parameter Name: RX_SERIALIZATION_Q_CTRL

Queue Size (% of the available This is the size of the serialization queue relative to the storage capacity of the credit
TLP buffer space ) queues expressed as a percentage of credit queue size. The serialisation queue
margin is excluded.
Values: 0, ..., 100
Default Value: CX_NW==16 ? [<functionof> CX_RADM_RXQ_NUM_QDWS >
CX_RADM_SERQ_OPT_AF_NUM_QDWS] ? [<functionof> [<functionof>
CX_RADM_SERQ_OPT_AF_NUM_QDWS_PER_RAM*100]
CX_RADM_RXQ_NUM_QDWS_PER_SERQ_RAM] : 100 : 1
Enabled: RX_SERIALIZATION_Q_CTRL
Parameter Type: Feature Setting
Parameter Name: CX_RADM_SERQ_TO_RXQ_SIZE_RATIO

Queue Size (Bytes) Receive Serialization Queue size expressed in Bytes (additional control bits, parity
bits, etc. are not considered)
Values: -2147483648, ..., 2147483647
Default Value:
(CX_RADM_SERQ_AF_NUM_QDWS_PER_RAM*CX_RADM_SERQ_NUM_RAMS)*
16
Enabled: Always
Parameter Name: CX_RADM_SERQ_AF_NUM_BYTES

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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / Cplq_Mng Calculator Parameters

6.57 Advanced RX Queue Credit and Size Config / Cplq_Mng Calculator Param-
eters
Table 6-57 Advanced RX Queue Credit and Size Config / Cplq_Mng Calculator Parameters

Label Description

Completion Queue Size dependant parameters

Round Trip Latency[ns] Specifies your expected Round Trip Latency in ns. Includes:
■ Local Controller and PHY latencies
■ Remote Controller and PHY latencies
■ Retimers
■ Response time of the remote side
Values: 0, ..., 65535
Default Value: 500
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: ROUND_TRIP_LATENCY

TLP Efficiency[%] Specifies the TLP Efficiency in %. Smaller payload has less data efficiency
(Data/(Hdr+Data)) and therefore requires less data buffer.
Values: 0, ..., 65535
Default Value: 100*CX_MAX_MTU/(CX_MAX_MTU+20)
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: TLP_EFFICIENCY

Recommended Number of TAGs for the Critial Request Size

Critical Request size[bytes] Specifies the smallest request size for which you want to maintain throughput. Used to
calculate the recommended number of TAGs
(CPLQ_MNG_DDP/MIN_RD_REQ_SIZE). Recommended size equal to or greater
than 64 bytes.
Values: 32, 64, 128, 256, 512, 1024, 2048, 4096
Default Value: 64
Enabled: Always
Parameter Name: MIN_RD_REQ_SIZE

Recommended number of TAGs Recommended number of TAGs based on Latency and Critical Request Size
specified.
Values: 0, ..., 65535
Default Value: [<functionof> CPLQ_MNG_DDP MIN_RD_REQ_SIZE]
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: RECOMMENDED_TAGS

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Label Description

Completion Queue Size

Header Completion Queue Specifies the size of the Completion Data Queue/RAM in hdr units without the
size[Hdr] overhead needed by the Queue logic. Derived from the number of TAGs. Does not
account for all possible split completions scenarios.
Values: 0, ..., 65535
Default Value: 2*(CX_MAX_TAG+1)
Enabled: CX_CPLQ_MANAGEMENT_ENABLE
Parameter Type: Feature Setting
Parameter Name: CPLQ_MNG_HDP

Data Completion Queue Specifies the size of the Completion Data Queue/RAM in bytes without the overhead
size[bytes] needed by the Queue logic. This is a recommendation based on your bandwidth, max
TLP size and expected latency. The Completion Queue Management feature can
result in throttling of outbound read request. It is your responsibility to guarantee
sufficient completion queue buffer to meet your performance requirements.
Values: 0, ..., 65535
Default Value: [<functionof> CX_MAX_PCIE_SPEED CX_NL
ROUND_TRIP_LATENCY TLP_EFFICIENCY CX_APP_RD_REQ_SIZE CX_NW
RADM_CPL_QMODE_VC0]
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CPLQ_MNG_DDP

Completion Queue Depth

Header Completion Queue Specifies the depth of the completion header queue including overhead for queue
Depth[Hdr/CX_NHQ] logic.
Values: 0, ..., 65535
Default Value: RADM_CPLQ_HDP_VC0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CPLQ_MNG_TOTAL_HDP

Data Completion Queue Specifies the depth of the completion data queue including overhead for queue logic.
Depth[NW] Values: 0, ..., 65535
Default Value: RADM_CPLQ_DDP_VC0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CPLQ_MNG_TOTAL_DDP

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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / VC 0 Parameters

6.58 Advanced RX Queue Credit and Size Config / VC 0 Parameters


Table 6-58 Advanced RX Queue Credit and Size Config / VC 0 Parameters

Label Description

Posted Queue Advertised Credits

Hdr Scale Factor Initial VC0 Posted header scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HSCALE_VC0

Hdr Credits The number of posted TLP header credits to advertise for VC0.
Values: 0, ..., 127
Default Value: RADM_P_QMODE_VC0==4 ? 0 : CX_CALC_HDEPTH / CX_HSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HCRD_VC0

Data Scale Factor Initial VC0 Posted data scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_DSCALE == 16) ? 3 : (CX_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DSCALE_VC0

Data Credits The number posted TLP data credits to advertise for VC0.
Values: 0, ..., 2047
Default Value: RADM_P_QMODE_VC0 ==4 ? 0 : CX_CALC_DDEPTH /
CX_DSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DCRD_VC0

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Advanced RX Queue Credit and Size Config / VC 0 Parameters PCI Express SW Controller Databook

Label Description

Non-Posted Queue Advertised Credits

Hdr Scale Factor Initial VC0 Non-Posted header scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HSCALE_VC0

Hdr Credits The number non-posted TLP header credits to advertise for VC0.
Values: 1, ..., 127
Default Value: (CX_CALC_HDEPTH==0) ? 1 : CX_CALC_HDEPTH / CX_HSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HCRD_VC0

Data Scale Factor Initial VC0 Non-Posted data scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_NP_DSCALE == 16) ? 3 : (CX_NP_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DSCALE_VC0

Data Credits The number non-posted TLP data credits to advertise for VC0.
Values: 1, ..., 2047
Default Value: (CX_NP_CALC_DDEPTH==0) ? 1 : CX_NP_CALC_DDEPTH /
CX_NP_DSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DCRD_VC0

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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / VC 0 Parameters

Label Description

Completion Queue Advertised Credits

Hdr Scale Factor Initial VC0 Completion header scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HSCALE_VC0

Hdr Credits The number completion TLP header credits to advertise for VC0.
Values: 0, ..., 127
Default Value: (RADM_CPL_QMODE_VC0==4 || CC_DEVICE_TYPE!=CC_SW) ? 0
: CX_CALC_HDEPTH / CX_HSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HCRD_VC0

Data Scale Factor Initial VC0 Completion data scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_DSCALE == 16) ? 3 : (CX_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DSCALE_VC0

Data Credits The number of completion TLP data credits to advertise for VC0.
Values: 0, ..., 2047
Default Value: (RADM_CPL_QMODE_VC0==4 || CC_DEVICE_TYPE!=CC_SW) ? 0
: CX_CALC_DDEPTH / CX_DSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DCRD_VC0

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Advanced RX Queue Credit and Size Config / VC 0 Parameters PCI Express SW Controller Databook

Label Description

Additional VC 0 Options

Max Outbound Read Request This parameter is used to set the depth of the receive completion data queue
For Buffered CPLs (CX_CPLQ_DDP_VC*) when completions are in store-and-forward or cut-through
modes, and completion credits are infinite.
■ It is the maximum individualMRd size that your application makes.
■ For more details, see the Receive Queues section in the Architecture chapter of the
Databook.
Values: 32, 64, 128, 256, 512, 1024, 2048, 4096
Default Value: !AMBA_POPULATED ? CX_MAX_MTU : (CC_DMA_ENABLE ?
CX_MAX_APP_RD_REQ_SIZE_AMBA_DMA : CC_SLV_MTU)
Enabled: !AMBA_POPULATED && (RADM_CPL_QMODE_VC0!=4)
Parameter Name: CX_APP_RD_REQ_SIZE

Posted Buffer Depth

Hdr Specifies the depth of the Posted Header Queue/RAM. The number of entries in the
Posted Header buffer for VC0. This option is read-only if the queue is bypassed. Note:
for 256-bit configurations this depth corresponds to one half of the total header storage
capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: (RADM_P_QMODE_VC0==4) ? (CX_RADMQ_MODE==2) ?
RADM_SEG_BUF_MIN_DPT : 0 : [<functionof> CX_RADMQ_MODE
RADM_PQ_HCRD_VC0 RADM_NPQ_HCRD_VC0 RADM_CPLQ_HCRD_VC0
RADM_CPL_QMODE_VC0 CX_NHQ CUT_THROUGH_INVOLVED CX_MAX_TAG
CX_APP_RD_REQ_SIZE CX_RCB RADM_PQ_HSCALE_VC0]
Enabled: RADM_P_QMODE_VC0!=4 && RADM_DEPTH_DECOUPLE_VC0==1
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HDP_VC0

Data Specifies the depth of the Posted Data Queue/RAM. The number of entries in the
Posted Data buffer for VC0. This option is read-only if the queue is bypassed. Note: for
256-bit configurations this depth corresponds to one half of the total data storage
capacity for this particular queue type; for 512-bit configurations this depth
corresponds to one quarter of the total data storage capacity for this particular queue
type.
Values: 0, ..., 65535
Default Value: RADM_P_QMODE_VC0==4 ? (CX_RADMQ_MODE==2) ?
RADM_SEG_BUF_MIN_DPT : 0 : [<functionof> CX_RADMQ_MODE
RADM_PQ_HCRD_VC0 RADM_PQ_DCRD_VC0 RADM_NPQ_HCRD_VC0
RADM_NPQ_DCRD_VC0 RADM_CPLQ_HDP_VC0 RADM_CPLQ_DCRD_VC0
RADM_CPL_QMODE_VC0 CX_NW CX_NHQ CC_DEVICE_TYPE CC_SW
CX_ECRC_STRIP_ENABLE RADM_SEG_BUF_CT_DPT_ADJ CX_MAX_TAG
CX_APP_RD_REQ_SIZE RADM_PQ_DSCALE_VC0 RADM_PQ_HSCALE_VC0]
Enabled: RADM_P_QMODE_VC0!=4 && RADM_DEPTH_DECOUPLE_VC0==1
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DDP_VC0

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Label Description

Non-Posted Buffer Depth

Hdr Specifies the depth of the Non-Posted Header Queue/RAM. The number of entries in
the Non-Posted Header buffer for VC0. Note: for 256-bit configurations this depth
corresponds to one half of the total header storage capacity for this particular queue
type.
Values: 0, ..., 65535
Default Value: (CX_RADMQ_MODE==0 || RADM_NP_QMODE_VC0==4) ?
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 : [<functionof>
CX_RADMQ_MODE RADM_NPQ_HCRD_VC0 CUT_THROUGH_INVOLVED
CX_NHQ RADM_NPQ_HSCALE_VC0]
Enabled: CX_RADMQ_MODE!=0 && RADM_NP_QMODE_VC0!=4 &&
RADM_DEPTH_DECOUPLE_VC0==1
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HDP_VC0

Data Specifies the depth of the Non-Posted Data Queue/RAM. The number of entries in the
Non-Posted Data buffer for VC0. Note: for 256-bit configurations this depth
corresponds to one half of the total data storage capacity for this particular queue type;
for 512-bit configurations this depth corresponds to one quarter of the total data
storage capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: (CX_RADMQ_MODE==0 || RADM_NP_QMODE_VC0==4) ?
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 : [<functionof> 0
CX_RADMQ_MODE RADM_NPQ_HCRD_VC0 RADM_NPQ_DCRD_VC0
CUT_THROUGH_INVOLVED CX_NW CX_NHQ CC_DEVICE_TYPE CC_SW
CX_ECRC_STRIP_ENABLE RADM_NPQ_DSCALE_VC0
RADM_NPQ_HSCALE_VC0]
Enabled: CX_RADMQ_MODE!=0 && RADM_NP_QMODE_VC0!=4 &&
RADM_DEPTH_DECOUPLE_VC0==1
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DDP_VC0

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Label Description

Completion Buffer Depth

Hdr Specifies the depth of the Completion Header Queue/RAM. The number of entries in
the Completion Header buffer for VC0. This option is read-only for all DMA and/or
AMBA configs and also if the queue is bypassed. Note: for 256-bit configurations this
depth corresponds to one half of the total header storage capacity for this particular
queue type.
Values: 0, ..., 65535
Default Value: (CX_RADMQ_MODE==0 || RADM_CPL_QMODE_VC0==4) ?
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 : [<functionof>
CX_CPLQ_MANAGEMENT_ENABLE CPLQ_MNG_HDP CX_RADMQ_MODE
RADM_CPLQ_HCRD_VC0 CUT_THROUGH_INVOLVED CX_NHQ CX_MAX_TAG
CX_APP_RD_REQ_SIZE CX_RCB RADM_CPLQ_HSCALE_VC0]
Enabled: (AMBA_INTERFACE == 0 && CC_DMA_ENABLE == 0) &&
CX_RADMQ_MODE!=0 && RADM_CPL_QMODE_VC0!=4 &&
(RADM_DEPTH_DECOUPLE_VC0==1 || RADM_CPLQ_HCRD_VC0 == 0)
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HDP_VC0

Data Specifies the depth of the Completion Data Queue/RAM. The number of entries in the
Completion Data buffer for VC0. This option is read-only for all DMA and/or AMBA
configs and also if the queue is bypassed. Note: for 256-bit configurations this depth
corresponds to one half of the total data storage capacity for this particular queue type;
for 512-bit configurations this depth corresponds to one quarter of the total data
storage capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: (CX_RADMQ_MODE==0 || RADM_CPL_QMODE_VC0==4) ?
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 : [<functionof>
CX_CPLQ_MANAGEMENT_ENABLE CPLQ_MNG_DDP CX_RADMQ_MODE
RADM_CPLQ_HDP_VC0 RADM_CPLQ_DCRD_VC0 CUT_THROUGH_INVOLVED
CX_NHQ CX_NW CX_MAX_TAG CX_APP_RD_REQ_SIZE CC_DEVICE_TYPE
CC_SW CX_ECRC_STRIP_ENABLE RADM_SEG_BUF_CT_DPT_ADJ
RADM_CPLQ_DSCALE_VC0 RADM_CPLQ_HSCALE_VC0]
Enabled: (AMBA_INTERFACE == 0 && CC_DMA_ENABLE == 0) &&
CX_RADMQ_MODE!=0 && RADM_CPL_QMODE_VC0!=4 &&
(RADM_DEPTH_DECOUPLE_VC0==1 || RADM_CPLQ_DCRD_VC0 == 0)
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DDP_VC0

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6.59 Advanced RX Queue Credit and Size Config / VC 1 Parameters


Table 6-59 Advanced RX Queue Credit and Size Config / VC 1 Parameters

Label Description

Posted Queue Mode and Advertised Credits

P Q Mode (VC#i) The queue mode for the posted tlp receive queue for VC1.
(for n = 1; n <= CX_NVC) ■ Bypass: There is no receive queue in this mode, your application must be able to
accept all traffic as back-pressure is disabled in the mode.
■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
■ Cut-through: TLPs are stored into queue and presented to your application at the
same time it is being stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
■ Cut Thru (0x2)
■ Bypass (0x4)
Default Value: RADM_P_QMODE_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_P_QMODE_VCn

P Header Scaling Factor (VC#i) Initial VC1 Posted header scaling factor to advertise Flow Control credit width.
(for n = 1; n <= CX_NVC) Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HSCALE_VCn

P Data Scaling Factor (VC#i) Initial VC1 Posted data scaling factor to advertise Flow Control credit width.
(for n = 1; n <= CX_NVC) Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_DSCALE == 16) ? 3 : (CX_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DSCALE_VCn

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Label Description

P Header Credits (VC#i) Specifies the # of Posted Hdr Credits to Advertise.


(for n = 1; n <= CX_NVC) Values: 0, ..., 127
Default Value: CX_NVC<=1 || RADM_P_QMODE_VC1==4 ? 0 :
RADM_PQ_HCRD_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HCRD_VCn

P Data Credits (VC#i) Specifies the # of Posted Data Credits to Advertise. One data credit = 128 bits of data
(for n = 1; n <= CX_NVC) Values: 0, ..., 2047
Default Value: CX_NVC<=1 || RADM_P_QMODE_VC1==4 ? 0 :
RADM_PQ_DCRD_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DCRD_VCn

Non-Posted Queue Mode and Advertised Credits

NP Q Mode (VC#i) The queue mode for the non-posted TLP receive queue for VC1.
(for n = 1; n <= CX_NVC) ■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
Default Value: RADM_NP_QMODE_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_NP_QMODE_VCn

NP Header Scaling Factor (VC#i) Initial VC1 Non-Posted header scaling factor to advertise Flow Control credit width.
(for n = 1; n <= CX_NVC) Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HSCALE_VCn

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Label Description

NP Data Scaling Factor (VC#i) Initial VC1 Non-Posted data scaling factor to advertise Flow Control credit width.
(for n = 1; n <= CX_NVC) Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_NP_DSCALE == 16) ? 3 : (CX_NP_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DSCALE_VCn

NP Header Credits (VC#i) Specifies the # of Non-Posted Hdr Credits to Advertise.


(for n = 1; n <= CX_NVC) Values: 1, ..., 127
Default Value: CX_NVC<=1 ? 1 : RADM_NPQ_HCRD_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HCRD_VCn

NP Data Credits (VC#i) Specifies the # of Non-Posted Data Credits to Advertise. One data credit = 128 bits of
(for n = 1; n <= CX_NVC) data
Values: 1, ..., 2047
Default Value: CX_ATOMIC_ENABLE ? (CX_NVC<=1) ? 1 :
RADM_NPQ_DCRD_VC0 : (RADM_NPQ_DSCALE_VC0 > 1) ? 512 : 1
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DCRD_VCn

Completion Queue Mode and Advertised Credits

CPL Q Mode (VC#i) The queue mode for the completion tlp receive queue for VC1.
(for n = 1; n <= CX_NVC) ■ Bypass: There is no receive queue in this mode, your application must be able to
accept all traffic as back-pressure is disabled in the mode.
■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
■ Cut-through: TLPs are stored into queue and presented to your application at the
same time it is being stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
■ Cut Thru (0x2)
■ Bypass (0x4)
Default Value: RADM_CPL_QMODE_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_CPL_QMODE_VCn

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Advanced RX Queue Credit and Size Config / VC 1 Parameters PCI Express SW Controller Databook

Label Description

CPL Header Scaling Factor Initial VC1 Completion header scaling factor to advertise Flow Control credit width.
(VC#i) Values:
(for n = 1; n <= CX_NVC)
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HSCALE_VCn

CPL Data Scaling Factor (VC#i) Initial VC1 Completion data scaling factor to advertise Flow Control credit width.
(for n = 1; n <= CX_NVC) Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_DSCALE == 16) ? 3 : (CX_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DSCALE_VCn

CPL Header Credits (VC#i) Specifies the # of Completion Hdr Credits to Advertise.
(for n = 1; n <= CX_NVC) Values: 0, ..., 127
Default Value: (CX_NVC<=1 || RADM_CPL_QMODE_VC1==4) ? 0 :
RADM_CPLQ_HCRD_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HCRD_VCn

CPL Data Credits (VC#i) Specifies the # of Completion Data Credits to Advertise. One data credit = 128 bits of
(for n = 1; n <= CX_NVC) data
Values: 0, ..., 2047
Default Value: (CX_NVC<=1 || RADM_CPL_QMODE_VC1==4) ? 0 :
RADM_CPLQ_DCRD_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DCRD_VCn

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Label Description

Posted Buffer Depth

P Header Queue Depth (VC#i) Specifies the depth of the Posted Header Queue/RAM. The number of entries in the
(for n = 1; n <= CX_NVC) Posted Header buffer for VC1. This option is read-only if the queue is bypassed. Note:
for 256-bit configurations this depth corresponds to one half of the total header storage
capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_P_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof>
CX_RADMQ_MODE RADM_PQ_HCRD_VC1 CX_NHQ
CUT_THROUGH_INVOLVED RADM_PQ_HSCALE_VC1]
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2 && RADM_P_QMODE_VC1!=4
&& RADM_DEPTH_DECOUPLE_VC1==1
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HDP_VCn

P Data Queue Depth (VC#i) Specifies the depth of the Posted Data Queue/RAM. The number of entries in the
(for n = 1; n <= CX_NVC) Posted Data buffer for VC1. This option is read-only if the queue is bypassed. Note: for
256-bit configurations this depth corresponds to one half of the total data storage
capacity for this particular queue type; for 512-bit configurations this depth
corresponds to one quarter of the total data storage capacity for this particular queue
type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_P_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof>
RADM_PQ_HCRD_VC1 RADM_PQ_DCRD_VC1 CX_NW CX_NHQ
CC_DEVICE_TYPE CC_SW CX_ECRC_STRIP_ENABLE
RADM_SEG_BUF_CT_DPT_ADJ RADM_PQ_DSCALE_VC1
RADM_PQ_HSCALE_VC1]
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2 && RADM_P_QMODE_VC1!=4
&& RADM_DEPTH_DECOUPLE_VC1==1
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DDP_VCn

Non-Posted Buffer Depth

NP Header Queue Depth (VC#i) Specifies the depth of the Non-Posted Header Queue/RAM. The number of entries in
(for n = 1; n <= CX_NVC) the Non-Posted Header buffer for VC1. Note: for 256-bit configurations this depth
corresponds to one half of the total header storage capacity for this particular queue
type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_NP_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof>
CX_RADMQ_MODE RADM_NPQ_HCRD_VC1 CUT_THROUGH_INVOLVED
CX_NHQ RADM_NPQ_HSCALE_VC1]
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2 && RADM_NP_QMODE_VC1!=4
&& RADM_DEPTH_DECOUPLE_VC1==1
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HDP_VCn

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Label Description

NP Data Queue Depth (VC#i) Specifies the depth of the Non-Posted Data Queue/RAM. The number of entries in the
(for n = 1; n <= CX_NVC) Non-Posted Data buffer for VC1. Note: for 256-bit configurations this depth
corresponds to one half of the total data storage capacity for this particular queue type;
for 512-bit configurations this depth corresponds to one quarter of the total data
storage capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_NP_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof> 1
CX_RADMQ_MODE RADM_NPQ_HCRD_VC1 RADM_NPQ_DCRD_VC1
CUT_THROUGH_INVOLVED CX_NW CX_NHQ CC_DEVICE_TYPE CC_SW
CX_ECRC_STRIP_ENABLE RADM_NPQ_DSCALE_VC1
RADM_NPQ_HSCALE_VC1]
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2 && RADM_NP_QMODE_VC1!=4
&& RADM_DEPTH_DECOUPLE_VC1==1
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DDP_VCn

Completion Buffer Depth

CPL Header Queue Depth (VC#i) Specifies the depth of the Completion Header Queue/RAM. The number of entries in
(for n = 1; n <= CX_NVC) the Completion Header buffer for VC1. This option is read-only for all DMA and/or
AMBA configs and also if the queue is bypassed. Note: for 256-bit configurations this
depth corresponds to one half of the total header storage capacity for this particular
queue type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_CPL_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof>
CX_CPLQ_MANAGEMENT_ENABLE CPLQ_MNG_HDP CX_RADMQ_MODE
RADM_CPLQ_HCRD_VC1 CUT_THROUGH_INVOLVED CX_NHQ CX_MAX_TAG
CX_APP_RD_REQ_SIZE CX_RCB RADM_CPLQ_HSCALE_VC1]
Enabled: (AMBA_INTERFACE == 0 && CC_DMA_ENABLE == 0) && CX_NVC>1 &&
CX_RADMQ_MODE==2 && RADM_CPL_QMODE_VC1!=4 &&
(RADM_DEPTH_DECOUPLE_VC1==1 || RADM_CPLQ_HCRD_VC1 == 0)
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HDP_VCn

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Label Description

CPL Data Queue Depth (VC#i) Specifies the depth of the Completion Data Queue/RAM. The number of entries in the
(for n = 1; n <= CX_NVC) Completion Data buffer for VC1. This option is read-only for all DMA and/or AMBA
configs and also if the queue is bypassed. Note: for 256-bit configurations this depth
corresponds to one half of the total data storage capacity for this particular queue type;
for 512-bit configurations this depth corresponds to one quarter of the total data
storage capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_CPL_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof>
CX_CPLQ_MANAGEMENT_ENABLE CPLQ_MNG_DDP CX_RADMQ_MODE
RADM_CPLQ_HDP_VC1 RADM_CPLQ_DCRD_VC1 CUT_THROUGH_INVOLVED
CX_NHQ CX_NW CX_MAX_TAG CX_APP_RD_REQ_SIZE CC_DEVICE_TYPE
CC_SW CX_ECRC_STRIP_ENABLE RADM_SEG_BUF_CT_DPT_ADJ
RADM_CPLQ_DSCALE_VC1 RADM_CPLQ_HSCALE_VC1]
Enabled: (AMBA_INTERFACE == 0 && CC_DMA_ENABLE == 0) && CX_NVC>1 &&
CX_RADMQ_MODE==2 && RADM_CPL_QMODE_VC1!=4 &&
(RADM_DEPTH_DECOUPLE_VC1==1 || RADM_CPLQ_DCRD_VC1 == 0)
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DDP_VCn

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Advanced RAS Config Parameters PCI Express SW Controller Databook

6.60 Advanced RAS Config Parameters


Table 6-60 Advanced RAS Config Parameters

Label Description

RAS DES (Debug/Statistics/Error Injection)

RAS D.E.S feature enable Enables RAS D.E.S functions (debug functions, error injection and statistical analysis).
Values:
■ false (0)
■ true (1)
Default Value: (CX_AUTOMOTIVE_ENABLE==1)? 1: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RAS_DES_ENABLE

- Event Counter Enables RAS D.E.S event counters.


Values:
■ false (0)
■ true (1)
Default Value: CX_RAS_DES_ENABLE
Enabled: CX_RAS_DES_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_RAS_DES_EC_ENABLE

- Time Based Analysis Enables RAS D.E.S time based analysis function.
Values:
■ false (0)
■ true (1)
Default Value: CX_RAS_DES_ENABLE
Enabled: CX_RAS_DES_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_RAS_DES_TBA_ENABLE

- Error Injection Enables RAS D.E.S error injection function.


Values:
■ false (0)
■ true (1)
Default Value: CX_RAS_DES_ENABLE
Enabled: CX_RAS_DES_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_RAS_DES_EINJ_ENABLE

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PCI Express SW Controller Databook Advanced RAS Config Parameters

Label Description

- Silicon Debug Enables RAS D.E.S silicon debug function.


Values:
■ false (0)
■ true (1)
Default Value: CX_RAS_DES_ENABLE
Enabled: CX_RAS_DES_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_RAS_DES_SD_ENABLE

- Debug Signals Enable Determines whether to include the debug signals that provide RAS D.E.S. feature
information in top-level ports.
Values:
■ false (0)
■ true (1)
Default Value: CX_RAS_DES_ENABLE
Enabled: CX_RAS_DES_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_RAS_DES_DBGIO_ENABLE

RAS DP (Data Protection)

Datapath Protection Enable Select datapath protection features.


(ECC/Parity) Values:
■ None (0)
■ Parity (8-bit Even) (1)
■ Parity (8-bit Odd) (2)
■ ECC: With Error Correction (3)
■ ECC: No Error Correction (4)
Default Value: (CX_AUTOMOTIVE_ENABLE==1)? 2: 0
Enabled: CX_RADMQ_MODE==2
Parameter Name: CX_RASDP

RAM Protection Enable (ECC) Select RAM ECC protection.


RAM ECC protection is always selected when you have enabled datapath protection
(CX_RASDP >0).
Single-bit RAM ECC correction is always enabled unless you disable single-bit
datapath ECC correction (CX_RASDP =4).
Values: 0, 1
Default Value: (CX_RASDP==0)? 0: 1
Enabled: (CX_RADMQ_MODE==2)? ((CX_RASDP==0 && AMBA_INTERFACE==0
&& CC_DMA_ENABLE==0)? 1: 0): 0
Parameter Name: CX_RASDP_RAM_PROT

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Memory Map Parameters PCI Express SW Controller Databook

6.61 Memory Map Parameters


Table 6-61 Memory Map Parameters

Label Description

Memory Map

Memory Map Position The register map of an upstream port (as determined by device_type[3:0]) is different
to that of a downstream port. When generating DocBook XML or HTML register
reports, coreConsultant uses this parameter to determine which memory map to
generate. This parameter has no effect on the RTL implementation.
■ 0: Upstream Port
■ 1: Downstream Port
Values:
■ Upstream Port (0)
■ Downstream Port (1)
Default Value: (CC_DEVICE_TYPE==CC_RC) || (CC_DEVICE_TYPE==CC_DM) ||
(CC_DEVICE_TYPE==CC_SW)
Enabled: ((CC_DEVICE_TYPE==CC_SW || CC_DEVICE_TYPE==CC_DM))
Parameter Name: CX_MEMORY_MAP_POSITION

Memory Map View Specifies the current memory map view. There are two buses that can access the
controller's register space: DBI and WIRE (over PCIe protocol). The register map as
perceived from the remote link partner (wire view) is different to that of the local
application (DBI view). For example, many registers that are RO over the wire are also
RW over the DBI. When generating DocBook XML or HTML register reports,
coreConsultant uses this parameter to determine which memory map view to
generate. This parameter has no effect on the RTL implementation.
■ 0: DBI
■ 1: WIRE
■ 2: DBI2
Values:
■ DBI (0)
■ WIRE (1)
■ DBI2 (2)
Default Value: DBI
Enabled: Always
Parameter Name: CX_MEMORY_MAP_VIEW

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Label Description

Memory Map Unroll View Specifies whether to generate unroll (that is, iATU and DMA registers only) DocBook
XML or HTML register reports or not. coreConsultant uses this parameter to determine
whether to generate the unroll (that is, iATU and DMA registers only) register report or
not. This parameter has no effect on the RTL implementation.
■ 0: NO_UNROLL
■ 1: UNROLL
Values:
■ NO_UNROLL (0)
■ UNROLL (1)
Default Value: NO_UNROLL
Enabled: (CC_UNROLL_ENABLE && (CX_MEMORY_MAP_VIEW <2))
Parameter Name: CX_UNROLL_VIEW

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Automotive Features Selection Parameters PCI Express SW Controller Databook

6.62 Automotive Features Selection Parameters


Table 6-62 Automotive Features Selection Parameters

Label Description

Enable CDM Register Checking

CDM Register Checking Enable When enabled, the core contains CDM Register Checking feature.
Values:
■ false (0)
■ true (1)
Default Value: (CX_AUTOMOTIVE_ENABLE==1)? 1: 0
Enabled: ((CX_PCIE_MODE == SINGLE_CPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_CDM_REG_CHK_EN

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PCI Express SW Controller Databook CXS Configuration Parameters

6.63 CXS Configuration Parameters


Table 6-63 CXS Configuration Parameters

Label Description

CXS Generic Config

CXS Synchronous Design If set to True, this parameter results in a CXS implementation using a single clock
domain. The PCIe IP clock (core_clk) is used to drive CXS interface.
Values:
■ false (0)
■ true (1)
Default Value: CX_CXS_DATAFLITWIDTH==CX_CXS_CCIXDATAWIDTH
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_SYNCHRONOUS

CXS Synchronous Design Specifies the maximum operating frequency of CXS Controller (MHz). The default
value is the Core and CXS Data Flit width ratio of the Core clock frequency.
Values: -2147483648, ..., 2147483647
Default Value:
int((CX_CXS_CCIXDATAWIDTH*1.0/CX_CXS_DATAFLITWIDTH)*CX_MAX_COREC
LK_FREQ)
Enabled: CX_CXS_ENABLE && !CX_CXS_SYNCHRONOUS
Parameter Type: Feature Setting
Parameter Name: CX_CXS_FREQUENCY

CXS Data Flit Width Configures CXS Data Flit Width (maps to CXSDATAFLITWIDTH in CXS specification).
Values: 256, 512, 1024
Default Value: (((CX_NW == 16) ? 512 : (CX_NW == 8) ? 256 : 128)==512) ? 512 :
256
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_DATAFLITWIDTH

CXS Maximum Packets per Flit Maximum number of packets that can be present in a single flit of data (maps to
CXSMAXPKTPERFLIT in CXS specification).
Values: 2, 3, 4
Default Value: (CX_CXS_DATAFLITWIDTH==256) ? 2 : 4
Enabled: (CX_CXS_ENABLE && (CX_CXS_DATAFLITWIDTH>256))
Parameter Type: Feature Setting
Parameter Name: CX_CXS_MAXPKTPERFLIT

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Label Description

CXS Receiver Continuous Data If set to True, this receiver requires that after a packet is started it is completed in
consecutive cycles if enough credits are available (maps to CXSCONTINUOUSDATA
in CXS specification).
Note:Once this parameter is set to True, this attribute may not be overwritten through
CXS Receiver configuration register.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RX_CONTINUOUSDATA

CXS Transmitter Continuous If set to True, this transmitter will not begin a packet until it can deliver the complete
Data packet in consecutive cycles as long as credits are available (maps to
CXSCONTINUOUSDATA in CXS specification).
Note:This parameter only sets the Store-Forward mode default value in CXS
Transmitter configuration register which may be overwritten later.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_TX_CONTINUOUSDATA

CXS Receiver Error Full Packet If set to True, this receiver requires that the length of every packet (including packets
ending with EndError) match the packet length specified in the packet header (maps to
CXSERRORFULLPKT in CXS specification).
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RX_ERRORFULLPKT

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Label Description

CXS Transmitter Error Full Packet If set to True, if this transmitter is unable to complete a packet and must end the packet
with an EndError indication, the transmitter will send the number of bytes specified in
the packet header before ending the packet (maps to CXSERRORFULLPKT in CXS
specification).
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_CXS_TX_ERRORFULLPKT

CXS Datapath Protection Config

CXS Receiver Data Check Configures data check support on CXSRXDATA, CXSRXCNTL (maps to
CXSDATACHECK in CXS specification): 0 - None 1 - Odd Parity; 1 bit per byte on
CXSDATA and 1 bit for CXSCNTL 2 - SECDED: ECC on a 64-bit granularity; 8 bits per
64 bits of data and 8 bits for CXSCNTL (zero extended to 64 bits) The default value of
this parameter is derived from CX_RASDP setting.
Values:
■ None (0)
■ Odd Parity (1)
■ SECDED (2)
Default Value: (CX_CXS_ENABLE && (CX_RASDP > 0)) ? (CX_RASDP-1) : 0
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RX_DATACHECK

CXS Transmitter Data Check Configures data check support on CXSTXDATA, CXSTXCNTL (maps to
CXSDATACHECK in CXS specification): 0 - None 1 - Odd Parity; 1 bit per byte on
CXSDATA and 1 bit for CXSCNTL 2 - SECDED: ECC on a 64-bit granularity; 8 bits per
64 bits of data and 8 bits for CXSCNTL (zero extended to 64 bits) The default value of
this parameter is derived from CX_RASDP setting.
Values:
■ None (0)
■ Odd Parity (1)
■ SECDED (2)
Default Value: (CX_CXS_ENABLE && (CX_RASDP > 0)) ? (CX_RASDP-1) : 0
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_TX_DATACHECK

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Label Description

CXS Receiver Signal Replication Signal replication on CXSRXVALID, CXSRXCRDGNT, CXSRXCRDRTN (maps to
CXSREPLICATION in CXS specification). Duplicate: CXSRXVALIDCHK,
CXSRXCRDGNTCHK, and CXSRXCRDRTNCHK are each single bit signals
duplicating the value of the corresponding control signal. Triplicate:
CXSRXVALIDCHK, CXSRXCRDGNTCHK, and CXSRXCRDRTNCHK are each
two-bit signals with each of the 2 bits having the same value as the corresponding
control signal.
Values:
■ None (0)
■ Duplicate (1)
■ Triplicate (2)
Default Value: None
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RX_REPLICATION

CXS Transmitter Signal Signal replication on CXSTXVALID, CXSTXCRDGNT, CXSTXCRDRTN (maps to


Replication CXSREPLICATION in CXS specification). Duplicate: CXSTXVALIDCHK,
CXSTXCRDGNTCHK, and CXSTXCRDRTNCHK are each single bit signals
duplicating the value of the corresponding control signal. Triplicate:
CXSTXVALIDCHK, CXSTXCRDGNTCHK, and CXSTXCRDRTNCHK are each two-bit
signals with each of the 2 bits having the same value as the corresponding control
signal.
Values:
■ None (0)
■ Duplicate (1)
■ Triplicate (2)
Default Value: None
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_CXS_TX_REPLICATION

CXS Controller Config

CXS Receiver Credits Configures the number of CXS Receiver credits.


Values: 1, ..., 15
Default Value: 15
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RX_CREDITS

CXS Transmitter Deactivation CXS Transmitter Deactivation Timer


Timer Values: 0, ..., 65535
Default Value: 0
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_TX_DEACT_TIMER_VALUE

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Label Description

CXS Transmitter Output Register Enable output register on CXS Transmitter Data/Control bus outputs.
Enable Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_TX_OUTPUT_REG

CXS Controller RAM Config

CXS RX/TX FIFO RAM Read CXS RX/TX FIFO RAM Read Latency.
Latency Values: 1, 2
Default Value: 1
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RAM_READ_LATENCY

CXS RX/TX FIFO RAM Pipeline Enable pipeline register on CXS RX/TX FIFO RAM output.
Enable Values:
■ false (0)
■ true (1)
Default Value: (CX_CXS_RAM_READ_LATENCY > 1) ? 0 : 1
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RAM_PIPELINE_ENABLE

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Cache Coherent Interconnect for Accelerators (CCIX) PCI Express SW Controller Databook

7
Cache Coherent Interconnect for Accelerators

(CCIX)

This section discusses the CCIX PCIe controller. The following topics are discussed:
■ “CCIX PCIe Controller Overview” on page 879
■ “CCIX PCIe Controller Operation” on page 884

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7.1 CCIX PCIe Controller Overview


The CCIX PCIe controller enables hardware accelerators to use memory shared with multiple processors in
a cache coherent manner. CCIX’s coherence protocol can be carried across PCIe links. The existing PCIe
controller implementation is extended with logic to implement CCIX Transport. CCIX Transport comprises
of CCIX and PCIe Transaction Layers, PCIe Data link Layer, and CCIX Physical Layer.

Figure 7-1 CCIX Application

Application Application CPU or


Logic Registers EEPROM

Application (Native or
Interfaces AXI)

DWC PCIe Controller

Application Dependent Application Dependent


part of the part of the
CCIX Application

CCIX Transaction Layer PCIe Transaction Layer

CCIX PCIe
Transaction Layer Transaction Layer

PCIe Data Link Layer

CCIX
Physical Layer(MAC)
Physical Layer(MAC)

PHY Interface (PIPE)


CLK/RST
PIPE-Compliant PHY

Customer Logic
PCIe Protocol PCI Express Link
Synopsys Implementation (PCIe)
CCIX Protocol
Synopsys Implementation (CCIX)

7.1.1 Configuring the CCIX PCIe Controller


The configuration parameters relevant to the CCIX are described in Table 7-64.

Table 7-64 CCIX Configuration Parameters

Parameter Name Parameter Label Value Range Default

CX_CCIX_ENABLE CCIX Protocol Supported 1, 0 0

7.1.2 CCIX PCIe Controller Features


■ All non-optional features of the CCIX Transport Specification.
■ Optional CCIX Extended Speed Mode (ESM) feature to extend the supported data rates to 20.0
GT/s and 25.0 GT/s.

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■ CCIX Transport DVSEC containing CCIX specific Control and Status Registers (CSRs) for CCIX
Physical, Data Link and Transaction Layers.

7.1.3 CCIX PCIe Controller Limitations


■ Native PCIe controller data path width must be greater than or equal to 128 bits.
■ AMBA bridge is supported for single master channel architecture (CC_HP_MASTER =0) only.
■ TX Interface
❑ TLPs using the traffic class (TC) dedicated to CCIX cannot be sent on the transmit client interfaces
(XALI0/1/2).
❑ The CCIX PCIe controller does not check for TLP errors; it forwards the TLP to your application
as presented on the CCIX interface. This is consistent with the behavior of the transmit client inter-
faces (XALI0/1/2).
❑ The CCIX PCIe controller does not check whether the TLP payload size is less than PCIe Max
Payload Supported (CX_MAX_MTU) or not. Exceeding this limit may overflow the retry buffer,
resulting in data corruption. This is consistent with the behavior of the transmit client interfaces
(XALI0/1/2).
❑ ECRC pass through is not supported, so your application must not forward TLPs with ECRC to
XALI_CCIX.
■ RX Interface
❑ Bypass mode is not supported for receive posted CCIX VC queue.
❑ The received CCIX VDM1 is forwarded when the function number in the Transaction ID matches
the implemented functions.
❑ The received CCIX Optimized TLPs are forwarded even if the FLR of any PF/VF is initiated.
❑ The received CCIX Compatible TLPs are discarded when the target function is under FLR.
❑ ECRC error pass through is not supported, so TLPs with ECRC error are not forwarded to
TRGT1_CCIX.
■ Lane Margining at Receiver is not supported at 16.0 GT/s of ESM Data Rate0.
■ Arbitration between CCIX transmit interface XALI_CCIX and XALI0/1/2 is fixed; XALI_CCIX inter-
face gets priority over XALI0/1/2 interfaces.
■ The value of MISC_CONTROL_1_OFF register fields DEFAULT_TARGET and UR_CA_MASK_4_TRGT1
affect the filter rules only when ccix_tlp_disable =1. When ccix_tlp_disable =0, the CCIX
PCIe controller considers DEFAULT_TARGET =0 and UR_CA_MASK_4_TRGT1 =0, irrespective of the
value set for these fields.
■ The CCIX VC does not advertise the infinite Completion Header / Data credits in Switch (SW) port
(CC_DEVICE_TYPE ==CC_SW).
■ RASDES
❑ Event Counter
■ The result of Group 7 (Layer3 non-error) is incorrect if the counters are enabled while Enable
Optimized TLP Generation and Reception bit is 1.
■ The group 0-6 works correctly.
❑ Time Based Analysis

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■ The analysis must be disabled while the link is in the ESM mode.
■ The result of Group 1 (Throughput) is incorrect if the analysis is enabled while Enable Opti-
mized TLP Generation and Reception bit is 1.
■ The group 0 works correctly.
❑ Error Injection
■ Error Injection Control 6 (Packet Error) cannot insert errors into the TLPs transmitted from the
XALI_CCIX interface.
■ The CCIX PCIe controller does not implement CCIX Protocol DVSEC registers. You must implement
them externally.
❑ If the device type is RC, they should be connected directly to the application’s interconnect.
❑ If the device type is not RC, they can be connected to the ELBI.
❑ Regardless of the device type, the PCI capability list must be updated through the DBI read only
write feature to write the offset of the CCIX Protocol DVSEC. For more information on DBI read
only write feature, see “Writing to Read-Only Registers” on page 103).

7.1.4 Frequency, Speed, and Width Support


Before the link training is initiated your application must configure:
■ CCIX_VDM_VID field in the CIX_CTRL_OFF register (configures the Vendor ID field for CCIX VDM1
TLPs)
■ CCIX_DVSEC_VID field in the CCIX_TP_HDR1_OFF register (configures the Vendor ID register for
DVSEC when this register is written using DBI. For more information on writing to Read-Only regis-
ters over DBI, see “Writing to Read-Only Registers” on page 103)
A CCIX device must support one of two PHY Types:
■ PCI Express 4.0, or
■ Extended Data Rate (EDR)
You can configure PHY type using CX_CCIX_ESM_SUPPORT parameter.

Table 7-65 CCIX PHY Types and Operating Modes

PHY Type PCIe Express Mode ESM Mode CCIX Speed Mode

2.5 GT/s Not Applicable CCIX Speed1

5.0 GT/s Not Applicable CCIX Speed2


PCI Express 4.0
8.0 GT/s Not Applicable CCIX Speed3
(CX_CCIX_ESM_SUPPORT=0)
16.0 GT/s Not Applicable CCIX Speed4

32.0 GT/s Not Applicable GEN5_Speed

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PHY Type PCIe Express Mode ESM Mode CCIX Speed Mode

2.5 GT/s 2.5 GT/s CCIX Speed1

5.0 GT/s 5.0 GT/s CCIX Speed2

Extended Data Rate (EDR) ESM Data Rate0


8.0 GT/s CCIX Speed3
(CX_CCIX_ESM_SUPPORT=1) 8.0 GT/s or 16.0 GT/s

ESM Data Rate1


16.0 GT/s 16.0 GT/s or 20.0 GT/s or CCIX Speed4
25.0 GT/s

Table 7-66 Supported Controller Configurations

Maxb Link Width (for


each controllerc
CCIX CCIX CCIX CCIX Gen5 Datapath width)
core_clk @ CCIX Speed Speed1 Speed2 Speed3 Speed4 Speed
{1,2,3,4} Modea Mode Mode Mode Mode 128-bit 256-bit 512-bit

125,
250,
(500 or 1000), ccix1_2s ccix2_2s_df ccix3_2s_df ccix4_2s_df NA x8 x16 NA
(1000 or 1250
or 1562.5)
CCIX ESM 62.5, 125,
20/25 (250 or 500),
Configuration (500 or 625 or ccix1_4s ccix2_4s_df ccix3_4s_df ccix4_4s_df NA x4 x8 x16
781.25)

125, 250,
(250 or 500),
ccix_2s ccix_2s ccix_4s ccix_4s g5_4s x4 x8 x16
(500 or 625 or
781.25), 1000

a. The ccix value indicates the CCIX speed mode. The s value indicates the number of 8-bit symbols processed per clock cycle per
lane by the CCIX PCIe controller PIPE interface, in the indicated speed mode. df indicates dynamic frequency.
b. The value in each cell indicates the maximum link width supported. You can configure the controller with a link width up to this
value, and coreConsultant automatically calculates the datapath width.
c. For license scheme information, see the “Checking License Requirements” section in the DWC PCI Express Controller Installation
Guide.

Table 7-67 indicates the supported controller PHY combinations.

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Table 7-67 Supported Controller PHY Combinations

PHY

ccix1_2s
ccix1_2s ccix1_4s ccix1_1s ccix2_2s
ccix2_2s ccix2_4s ccix2_1s ccix3_4s
ccix3_2s ccix3_4s ccix3_4s ccix4_4s
Controller ccix4_2s ccix4_4s ccix4_4s g5_4s

ccix1_2s
ccix2_2s
ccix3_2s
ccix4_2s

ccix1_4s
ccix2_4s
ccix3_4s
ccix4_4s

ccix1_2s
ccix2_2s
ccix3_4s
ccix4_4s
g5_4s

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7.2 CCIX PCIe Controller Operation


This section describes the CCIX PCI controller operation. The following topics are discussed in this section:
■ “CCIX Extended Speed Mode Overview”
■ “PIPE Interface” on page 887
■ “CCIX Transaction Layer Receiver Operation” on page 890

7.2.1 CCIX Extended Speed Mode Overview


The following topics are discussed in this section:
■ “Initial Speed Change Sequence”
■ “ESM Equalization (EQ)” on page 886
■ “Quick Equalization (EQ) Redo” on page 886
■ “Software Equalization (EQ) Redo” on page 887
■ “Polling.Compliance Testing” on page 887
■ “LTSSM Enhancements to Support ESM Operation” on page 887

7.2.1.1 Initial Speed Change Sequence

The initial speed change sequence to attain ESM data rate is as follows:
1. PCIe compliant phase
a. Physical Link is fully compliant to PCI Express Base Specification, Revision 4.0, Version 1.0.
b. Initial transition to LTSSM L0 state operating at 16.0 GT/s data rate.
c. Link-Up to DL_Active state and Flow Control Initialization is complete.
2. Software based discovery and PHY Calibration in L1 state
a. Your application probes the ESM Data Rate Capabilities of the link partner to determine data rates
and configures the ESM Data Rate 0/1 (ESM_DATA_RATE0/ESM_DATA_RATE1) fields of the ESM
Control register (ESM_CNTL_REG).
b. Your application transitions the link to 2.5 GT/s data rate.
c. Your application probes the ESM Data Rate Capabilities of the link partner to determine the Link
Reach Target and configures the Link Reach Target (LINK_REACH_TARGET) of the controller. Based
on the value of LINK_REACH_TARGET, the ESM Extended Equalization Phase3 Timeout (ESM_EX-
T_EQ3_DSP_TIMEOUT)and ESM Extended Equalization Phase2 Timeout (ESM_EXT_EQ2_USP_-
TIMEOUT) fields of the ESM Control register are programmed.
d. Your application queries ESM Mandatory Data Rate Capabilities and ESM Optional Data Rate
Capabilities registers of the link partner, and sets the selected data rates into the Rate Capabilities
of the link partner to determine data rates and configures the ESM Data Rate 0/1 (ESM_-
DATA_RATE0/ESM_DATA_RATE1) fields of the ESM Control register (ESM_CNTL_REG).
e. Your application sets ESM Perform Calibration (ESM_PERFORM_CAL) field of ESM Control Register
for the link partner as well as the controller.
f. Your application drives link to L1 state using L1-PM mechanism.
g. MAC requests PHY calibration on all lanes using the M2P_MessageBus.

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h. PHY performs calibration and acknowledges the calibration complete on all the non-turn-off lanes
to MAC using the P2M_MessageBus.
i. MAC collects the calibration complete on all the non-turn-off lanes. If it is back on all the
non-turn-off lanes, the controller sets the Calibration Complete field (ESM_CALIB_CMPLT) of ESM
status register (ESM_STAT_REG) to 1.
j. Your application drives an exit from L1 state, using the L1-PM mechanism, after the predeter-
mined
ESM Calibration Time has expired.
k. On exit from L1 state, your application must check the Calibration Complete field (ESM_CALIB_C-
MPLT) of the ESM status register (ESM_STAT_REG) on both sides of the link.
i. If ESM_CALIB_CMPLT =0, ESM transition is discontinued and the remaining steps are not
performed.
ii. If ESM_CALIB_CMPLT =1, your application must set the ESM Enable (ESM_ENABLE) field of the
ESM Control register (ESM_CNTL_REG) for both the link partners.
3. Link transition to selected ESM Data Rates
a. Your application sets Target Link Speed and Link Retrain on DSP.
b. In this step, Data Rate change occurs based on PCI Express LTSSM.

Only PCIE_CAP_MAX_LINK_SPEED field of the Link Capabilities register determines the


Note maximum link speed of the port. The physical layer ESM mode indicated by
ESM_MODE_SUPPORT field of the CCIX_TP_CAP_TP_HDR2_OFF register, or ESM Data Rate set
in the ESM Mandatory Data Rate Capability register (ESM_MNDTRY_RATE_CAP_OFF), do not
determine the maximum link speed of the port.
You must set the parameter CX_MAX_PCIE_SPEED or PCIE_CAP_MAX_LINK_SPEED field of the
Link Capabilities register appropriately to support the maximum link speed for both PCIe mode
as well as ESM mode.

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Figure 7-2 Initial Speed Change Sequence


Step Number: #2-c #2-d #2-e #2-f #2-j #2-k #3-a

Perform Calibration

Link Reach Target SR LR


Transport
DVSEC ESM Data Rate0 0x00 (No Speed) 0x03 (8.0GT/s)
8.0 or 16.0 GT/s
ESM Control
ESM Data Rate1
20.0 or 25.0 GT/s 0x00 (No Speed) 0x0C (25GT/s)

ESM Enable 0 (PCIe mode) 1 (ESM mode)

PCI Express Target Link Speed 0001: 2.5GT/s 0100: ESM Data Rate1
Capability
Link Retrain
Link Control

Transport ESM Calibration Complete 0 1


DVSEC
ESM Current Data Rate 0: ESM Inactive 1: 2.5GT/s 3: 8.0GT/s 0xC: 25.0GT/s
ESM Status

MAC LTSSM L0 L1 Rec L0 Rec Rec.Speed Rec.EQ Rec L0 Rec Rec.Speed Rec.EQ Rec L0

Calibration State Active


PHY

Rate[1:0] 00b: 2.5GT/s 10b: 8.0GT/s 11b: 25GT/s

PowerDown[3:0] P0 P1 P0

PIPE Phystatus

Reach ESM ESM Calibrati ESM


M2P_MessageBus[7:0] Target Rate0 Rate1 on Req
AK
Enable

Calib ration
P2M_MessageBus[7:0] AK AK AK AK
Complete
AK

Link Link 2.5GT/s EI 2.5GT/s EI 8.0GT/s EI 25.0 GT/s

7.2.1.2 ESM Equalization (EQ)

■ If the PHY is Long Reach Capable, that is, CCIX_TP_CAP_REG.ESM_REACH_LENGTH =01b, the
controller uses the ESM Extended Timeout value (ESM_EXT_EQ3_DSP_TIMEOUT/ESM_EXT_EQ2_US-
P_TIMEOUT) in the ESM Control Register as the EQ fine tuning time. For all other values of
ESM_REACH_LENGTH, the controller uses the PCIe specification defined timeout value as the EQ fine
tuning time. After timeout, the controller moves to Recovery.Speed LTSSM state.
■ Your application must clear the Quick Equalization Timeout Select (QUICK_EQ_TIMEOUT) field in the
ESM Control register (ESM_CNTL_REG) if the ESM Data Rate1 is achieved after Hot Reset.

7.2.1.3 Quick Equalization (EQ) Redo

Your application can drive quick EQ by performing the following steps (the quick EQ redo has higher
priority than the link reach target):
■ Ensure that the link is in ESM Data Rate1.
■ Probe the ESM Quick Equalization value of the link partner.
■ Initiate a Hot Reset.
■ Set QUICK_EQ_TIMEOUT value in ESM_CNTL_REG register.

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PCI Express SW Controller Databook PIPE Interface

The link performs a quick EQ redo (if the QUICK_EQ_TIMEOUT is not 0) by using the quick EQ timeout
(ESM_QUICK_EQ_TIMEOUT) value in the EQ phase 2/3 at ESM Data Rate1.

7.2.1.4 Software Equalization (EQ) Redo

Your application can drive EQ redo by using Perform EQ (PERFORM_EQ) field of PCIe Link Control 3
(LINK_CONTROL3_REG) register.

7.2.1.5 Polling.Compliance Testing

Your application can drive Polling.Compliane by performing the following steps:


■ linkup to DL_ACTIVE at PCIe Gen1 rate.
■ Set Enter Compliance, Enter Modified Compliance, or Compliance Receive for the link partners,
depending on test scenario requirements.
■ Set ESMRate0, ESMRate1, Target Link Speed for both the link partners.
■ Set Link Reach Target for both the link partners.
■ Set ESMCompliance and ESMEnable for both the link partners.
■ Sets Hot Reset on DSP.
■ Link performs calibration in Detect.Quiet state and then moves to Polling.Compliance state after cali-
bration.
■ Link performs compliance test after the speed changes to the highest ESM Rate.
■ Clear ESMCompliance and ESMEnable fields and set Target Link Speed to Gen1 rate.
■ Drive Polling.Compliance exit and linkup to Gen1 rate.
■ Clear all Compliance test related settings in both the link partners.

7.2.1.6 LTSSM Enhancements to Support ESM Operation

■ Extended EIEOS format used for ESM Data Rate1 (20.0/25.0 GT/s).
■ Control SKP OS format used for ESM Data Rate1 (20.0/25.0 GT/s) and ESM Data Rate0 (16.0 GT/s).
■ PCI Express 8.0 GT/s LTSSM rules reused for ESM Data Rate0.
■ PCI Express 16.0 GT/s LTSSM rules reused for ESM Data Rate1.

7.2.2 PIPE Interface


The following topics are discussed in this section:
■ “PIPE Interface Enhancements to Support ESM Operation”
■ “Calibration in P1/L1 state” on page 888
■ “Calibration in Detect.Quiet State for Polling.Compliance Testing” on page 889
■ “PIPE Message Bus Enhancements to Support ESM Data Rate” on page 889

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PIPE Interface PCI Express SW Controller Databook

7.2.2.1 PIPE Interface Enhancements to Support ESM Operation

This section describes PIPE Specification for PCI Express, Version 4.4.1 enhancements for supporting ESM
operation.
■ The controller provides ESM Data Rate information through PIPE message bus.
❑ When the value of ESM Data Rate0/1 (ESM_DATA_RATE0/ESM_DATA_RATE1) or ESM Enable
(ESM_ENABLE) fields in the ESM_CNTL_REG register changes, the controller generates a write trans-
action to the PHY to update this information.
❑ For more information, see “PIPE Message Bus Enhancements to Support ESM Data Rate” on page
889.
■ Calibration handshake in L1 state is done through PIPE message bus. For more information, see “Cali-
bration in P1/L1 state” on page 888.
■ Link Reach Target can be Long Reach (LR) or Short Reach (SR).
■ PCIe rate change protocol is used for ESM Operation.

7.2.2.2 Calibration in P1/L1 state

Your application can drive Calibration in L1 state by performing the following steps.
1. Disable ASPM and L1 substates on both USP and DSP when link enters Gen1 rate.
2. Read the maximum of ESM Calibration Time values from CCIX Transport Capabilities Register on DSP
and USP as the upper limit time for calibration.
3. Set ESM Perform Calibration to initiate calibration.
4. Drive the Link to L1 state using L1-PM mechanism.
5. The controller generates write transaction to set Calibration Request field through PIPE message bus
6. The PHY generates Write Ack command to the controller.
7. The PHY optionally performs calibration for upcoming ESM Data rates.
8. The PHY can turn off PCLK after Step 6.
9. PCLK must be turned on only after the PHY completes the calibration.
10. The PHY generates write transaction to set Calibration Complete through PIPE message bus. If PHY
does not need calibration, your application must set Calibration Complete for the PIPE.
11. The controller generates Write Ack command to the PHY.
12. Your application drives the link to exit L1 using L1-PM mechanism after ESM Calibration timeout.

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PCI Express SW Controller Databook PIPE Interface

Figure 7-3 Calibration in P1 State


ESM CalibrationTime

MAC LTSSM L0 L1 Rec L0

ESM Perform Calibration Bit

Active
PHY Cal ibrati on Stat e

PCLK Active Can be turned off Active

Rate[1:0] 00b: 2.5GT/s

PowerDown[3:0] P0 P1 P0

Phystatus
PIPE
Calibrati
M2P_MessageB us[7:0] on Req
AK

Calibration
P2M_MessageB us[7:0] AK
Complete

7.2.2.3 Calibration in Detect.Quiet State for Polling.Compliance Testing

1. Initial linkup to DL_Active at PCIe Gen1 rate


2. SW sets ESMRate0, ESMRate1, ESMCompliance, and ESMEnable in DSP and USP
3. SW sets Hot Reset in DSP and the link moves to Detect.Quiet state
4. After Hot Reset and the port is in P1 pwerdown mode, MAC writes Calibration Request to PHY
through Messgage Bus and PHY performs calibration
5. PHY writes Calibration Complete back to MAC through Message Bus after the calibration completion
a.If PHY does not write Calibration Complete back to MAC after ESMCalibrationTimeout, the MAC
exits the calibration autonomously and clears the PHY's calibration bit through Message Bus
6. MAC drives LTSSM transition to the next Detect.Active state

7.2.2.4 PIPE Message Bus Enhancements to Support ESM Data Rate

Table 7-68 describes the PHY register enhancements and Table 7-69 describes the MAC register
enhancements to support ESM Data Rate.

Table 7-68 PIPE Message BUS: PHY Registers

Register Register Bit Allowed


Address Name Field Bit Field Name Attribute Description Command

[7] Reserved N/A


ESM
0xF00 Rate for ESM operation WC
Rate0 [6:0] ESM Data Rate0 Level
for 1st ESM rate

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CCIX Transaction Layer Receiver Operation PCI Express SW Controller Databook

Register Register Bit Allowed


Address Name Field Bit Field Name Attribute Description Command

[7] Reserved N/A


ESM
0xF01 Rate for ESM operation WC
Rate1 [6:0] ESM Data Rate1 Level
for 2nd ESM rate

[7:2] Reserved N/A

ESM ESM Calibration Controller request to the


0xF02 [1] 1-cycle WC
Control request PHY to calibrate for ESM

[0] ESM Enable Level Enable ESM operation

ESM [7:6] Reserved N/A


Link
0xF03 ESM Extended EQ2/3 WC
Reach [0] ESM Long Reach Level
Target timeout values

Table 7-69 PIPE Message BUS: MAC Registers

Register Register Bit Allowed


Address Name Field Bit Field Name Attribute Description Command

[7:1] Reserved N/A


ESM
0xF00 ESM Calibration Calibration complete WC
Status [0] 1-cycle
Complete indication

7.2.3 CCIX Transaction Layer Receiver Operation


The following topics are discussed in this section:
■ “Error Detection”
■ “Rx VC Arbitration” on page 891

7.2.3.1 Error Detection

Different error detection rules apply to TLPs received on the PCIe VC and on CCIX VC. Traffic Class (TC)
label on received TLPs is used to steer the traffic either to PCIe VC or CCIX VC. To switch between PCIe
compatible TLP format and CCIX optimized TLP format use CCIX_EN_OPT_TLP_GEN_RECPT field of the
CCIX_TL_CNTL_REG register. CCIX TLPs are processed as per the CCIX Transport Specification, good CCIX
TLPs are passed to the CCIX TRGT1 interface.

Optimized TLPs with Length[6:0] <2


Note
According to the CCIX specification, all TLPs in CCIX optimized TLP format must have Length
[6:0] in the range 02H <= Length [6:0] <= 7FH. The controller behavior is undefined when
TLPs in CCIX optimized TLP format with Length[6:0] <2 are received.

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7.2.3.2 Rx VC Arbitration

The ordering between the CCIX VC and the PCIe VC is achieved using TRGT1 packet Grant/Halt signals
(radm_grant_tlp_type/trgt1_radm_pkt_halt).
■ radm_grant_tlp_type indicates the type of TLP received, CCIX TLP (both the PCIe Compatible
TLP/CCIX Optimized TLPs) or PCIe TLP. trgt1_radm_pkt_halt[cfg_ccix_vc_re-
source*3+:1] controls the CCIX VC and PCIe VC arbitration. For more information on the usage of
the TRGT1 Packet Grant/Halt signals, see “TRGT1 Packet Grant and Halt” on page 291.
■ While the CCIX TLPs are being forwarded to your application through the TRGT1_CCIX interface, the
RTRGT1 interface does not forward the TLPs to your application. Similarly, TRGT1_CCIX never
forwards the TLPs to your application while TLPs are being forwarded to your application through
RTRGT1 interface. Therefore, halting of the TRGT1_CCIX interface by ccix_radm_halt or RTRGT1
interface by trgt1_radm_halt affects the bandwidth of both the interfaces.
■ radm_grant_tlp_type[cfg_ccix_vc_resource*3+1+:2] is never asserted when the
Non-Posted / Completion buffers on the CCIX VC are in the store-and-forward mode.
■ If the AMBA bridge is enabled, trgt1_radm_pkt_halt[cfg_ccix_vc_resource*3+:1] must be
controlled by your application. The other bits of trgt1_radm_pkt_halt must be 0.

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Embedded EndPoint (Switch DSP Integrated EndPoint) PCI Express SW Controller Databook

8
Embedded EndPoint (Switch DSP Integrated

EndPoint)

This section describes the Embedded EndPoint solution provided by Synopsys which is currently available
through Statement of Work (SoW) flow. The following topics are discussed:
■ “Overview” on page 893
■ “Advantages of Embedded EndPoint Solution Over Pipe Connected EndPoint” on page 895
■ “Embedded EndPoint Delivery Flow” on page 896

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PCI Express SW Controller Databook Overview

8.1 Overview
Embedded EndPoint or Switch DSP integrated EndPoint is a complete solution which consists of PCIe
Switch DSP connected to PCIe EndPoint using glue logic (bypassing the need to have a physical link
between the Switch DSP and EndPoint), clock and reset logic, RAMs, and merged synthesis constraints.

Figure 8-4 Embedded EndPoint


Embedded EndPoint

EP Subsystem SW Subsystem

EP SW
(dwc_pcie_ctl) (dwc_pcie_ctl)

EP SW
Clock and Clock and
Reset Reset

EP RAMs SW RAMs

You can re-purpose the Embedded EndPoint solution to work with different designs and different
architectures. Figure 8-5 describes a scenario in which the same Embedded EndPoint solution can be
re-used to connect to SATA AHCI, Giga Ethernet, and NVMe Controller.

Figure 8-5 Embedded EndPoint Usage Scenario


AXI

PCIe Gen3 Root


PHY x8 Complex
PIPE

PIPE

Switch Switch
USP USP

Switch Fabric

Switch
Embedded Embedded Embedded
DSP
EndPoint EndPoint EndPoint
PIPE

PCIe Gen3
AXI

AXI

AXI

PHY x1

SATA Giga NVMe


AHCI Ethernet Controller

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Overview PCI Express SW Controller Databook

Features
■ Full Multifunction Support
■ Supported PCIe controller features
❑ All the PCIe controller supported datapath widths
❑ Native/AXI interface
❑ SR-IOV
❑ Embedded DMA
❑ MSIX
❑ FLR
❑ LTR
❑ AER
■ Most of the application layer controller features can be supported without modifications

Architecture
Figure 8-6 describes the Embedded EndPoint architecture.

Figure 8-6 Embedded EndPoint Architecture


CLIENT 0/1/2 TRGT 0/1

DWC_pcie_ctl

XADM RADM

XADM Internal Bus RADM Internal Bus

CXPL EMULATION
Downstream Port

CXPL EMULATION
Upstream Port

RADM Internal Bus XADM Internal Bus

RADM XADM

DWC_pcie_ctl

TRGT 0/1 CLIENT 0/1/2

The CXPL emulation module connects the downstream port and upstream port XADM and RADM
modules and emulates the PCIe layers and PHY. The RADM and XADM modules are the same as the ones
present in EndPoint and Switch products.

Power Management
■ PCIe controller power management is supported for Embedded EndPoints as well.
■ ASPM support is under development.

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PCI Express SW Controller Databook Advantages of Embedded EndPoint Solution Over Pipe Connected EndPoint

8.2 Advantages of Embedded EndPoint Solution Over Pipe Connected


EndPoint
The Embedded Endpoint solution has a much lesser footprint as compared to a pipe connected EndPoint.
The transmit and receive latencies of the Embedded Enpoints are quite less in comparison to the pipe
connected EndPoint. Table 8-70 shows an example comparison of the area and latency numbers of both the
solutions; the actual numbers are configuration specific.

Table 8-70 Embedded EndPoint Area and Latency Comparison

Product 32-bit 64-bit 128-bit 256-bit 512-bit

Area (Kgates)

Pipe Connected EndPoint 245.38 291.17 439.67 894.05 1555.19

Embedded EndPoint 106.00 109.95 114.26 232.94 209.26

Latency (TX/RX Cycles)

Pipe Connected EndPoint 32/32 33/33 36/36 36/36 44/44

Embedded EndPoint 12/12 11/11 10/10 18/11 10/13

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8.3 Embedded EndPoint Delivery Flow


To obtain Embedded EndPoint solution contact Synopsys support through Solvnet providing the Switch
DSP and EndPoint configuration requirements. Synopsys uses the specified configuration to generate and
verify the embedded EndPoint solution using Core Assembler automated solution flow.
The Embedded EndPoint deliverable includes:
■ Fully configured Embedded EndPoint RTL code
■ Complete list file for exporting the design to external flows
■ Complete set of constraints for reuse/integration in external flows
■ Dummy .lib placeholder models for each RAM; you must generate technology specific memory
models for these RAMs

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PCI Express SW Controller Databook Advanced Information: Gen3/4/5 Equalization Details and Example

A
Advanced Information: Gen3/4/5 Equalization

Details and Example

This appendix discusses advanced aspects of Gen3 or above equalization operation, and also provides a
usage example. The terms MAC and PCIe controller are used interchangeably in this section. The following
topics are discussed:
■ “Equalization Overview and Synopsys-Specific Features” on page 898
■ “Detailed Equalization Procedure” on page 907
■ “Usage Example” on page 915

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A.1 Equalization Overview and Synopsys-Specific Features


The controller performs link equalization during link training to improve signal quality by adjusting the
transmitter and receiver equalization parameters for each lane on each side of the link. The receiver
equalizer is a self-contained adaptive equalizer within the PHY. After it receives its preset hints from the
downstream port (DSP) Lane Equalization Control (LEC) registers for Gen3 and the DSP Lane Equalization
Control 2 (LEC2) registers for Gen4, it does not require any more interaction with the MAC or with the
remote PHY. The transmitter equalizer is a three tap equalizer whose coefficients are adapted by a
coefficient adaptation engine in the remote MAC. This engine uses a quality metric or an error metric from
the local PHY to drive its adaptation and convergence algorithms. The controller supports figure of merit
(FOM) and direction (DIR) feedback modes. There are four phases in the equalization of the link as
indicated in Figure A-1 on page 899. They are briefly described here and are discussed in greater detail later.
■ Phase 0: When negotiating to Gen3 speed, before the link moves to Gen3 speed, the DSP applies the
DSP presets in its LEC to its local transmitter and receiver equalizers, and sends the USP presets to the
upstream port (USP) over the link using TS2 OS’s.
When negotiating to Gen4 speed, before the link moves to Gen4 speed, the DSP applies the DSP trans-
mitter presets in received TS2 OS's or its LEC2 to its local transmitter and DSP receiver presets in its
LEC2 to its local receiver equalizers, and sends the USP presets to the USP over the link using 8GT EQ
TS2 OS's. Optionally, the USP can request DSP's transmitter presets in sending TS2 OS's.
■ Phase 1: The USP and DSP apply the presets and work to operate and maintain a stable link operating
at the current Gen3 or above speed. No adaptation of presets/coefficients takes place.
■ Phase 2: The USP is the equalization master and tunes the DSP transmitter equalizer. Its adaptation
engine sends equalization requests to the DSP using TS1 OS’s. By using the Use Preset bit in the TS1,
it directs the DSP to map and use a preset or to directly use the coefficient supplied in the TS1 as shown
in Figure A-1 on page 899.
■ Phase 3: The DSP is the equalization master and tunes the USP transmitter equalizer.
■ Recovery.RcvrLock: After Phase 3, both the sides of the link move to Recovery.RcvrLock. The DSP
hardware does not initiate equalization redo if any side of the link detects equalization problems (for
example, EQ settings mismatch) in the Recovery.RcvrLock state. The DSP generates an interrupt to
notify the software of equalization problems, the software must decide whether to redo equalization
or not.
An equalization master is a port that is currently adjusting the remote transmitters settings. This can be an
USP in phase 2 or a DSP in phase 3. An equalization slave is a port that is currently receiving and applying
coefficients (requested by the remote equalization master) to its local transmitter. This can be a USP in phase
3 or a DSP in phase 2.
Gen 5 and above
For Gen5 and above data rates the controller supports “Equalization Bypass to Highest Data Rate” and “No
Equalization Needed” features.
■ Equalization Bypass to Highest Data Rate: To enable this feature, set the EQ_BYPASS_HIGH-
EST_RATE_SUPPORT field of the PL32G_CAPABILITY_REG register to ‘1’. When this feature is enabled,
and supported by the other side of the link as well, the link skips Gen3 and Gen4 equalizations and
directly performs Gen5 equalization. The link can run at Gen1, Gen2, and Gen5 rates.
■ No Equalization needed: To enable this feature, set the NO_EQ_NEEDED_SUPPORT field of the
PL32G_CAPABILITY_REG register to ‘1’. When this feature is enabled, and supported by the other side
of the link as well, the link does not need to perform equalizations for any data rate. The link can reli-
ably run at any data rate from Gen1 to Gen5, if the link is reliable at these data rates.

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Figure A-1 Gen3 Equalization Phases: Simplified Overview


PHASE 0 2.5.0 GT/s DSP Transfers Presets to USP PHASE 1 8.0 GT/s Link Is Using Default Presets
DOWNSTREAM PORT DOWNSTREAM PORT

LEC Register
M M M M
A A A A
C TS2 OS C C C

P RX P P RX P
TX TX
H Equalizer H H Equalizer H
Equalizer Equalizer
Y Y Y Y
TS2 OS

P P P P
RX TX RX TX
H H H H
Equalizer Equalizer Equalizer Equalizer
Y Y Y Y

TS2 OS
M M M M
A A A A
C C C C

UPSTREAM PORT UPSTREAM PORT

PHASE 2 8.0 GT/s USP Adapting DSP TX Coefficients PHASE 3 8.0 GT/s DSP Adapting USP TX Coefficients
DOWNSTREAM PORT : EQ SLAVE DOWNSTREAM PORT : EQ MASTER

M M M M
Coefficient
A Apply A A A
Adaptation
C Coefficients C C TS OS C
Engine

P P P FOM/DIR P
TX C-1 , C0, C+1
H H H H
Equalizer
Y Y Y Y

P P P P
TX
H H H H
FOM/DIR C-1, C0, C+1 Equalizer
Y Y Y Y

Coefficient TS OS
M M M Apply M
Adaptation A A
A A Coefficients
Engine
C C C C

UPSTREAM PORT : EQ MASTER UPSTREAM PORT : EQ SLAVE

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Preset Mapping Modes PCI Express SW Controller Databook

A.1.1 Preset Mapping Modes


The controller provides a configurable preset-to-coefficient mapping implementation to interoperate with
different PHYs. Mapping consists of converting the requested preset to generating a set of three 6-bit
coefficients using the PHYs actual LF and FS values, and by referring to the preset encoding table in Section
4.2.3.2. “Encoding of Presets” of the PCI Express Base Specification, Revision 4.0, Version 1.0. A preset index
identifies a set of typical settings for the transmitter filter coefficients. However, these floating point
coefficients are normalized values and must be scaled by the actual voltage swings (known as the LF and FS
values) used by the PHY to derive the actual coefficients used in the transmitter filter. The controller
provides three mapping modes selectable at configuration time using
CX_GEN3_EQ_PSET_COEF_MAP_MODE:

■ (0) Dynamic PHY


The coefficients are dynamically mapped in the PHY. This is the default mode.

■ When a downstream port is redoing equalization from the Gen3 or above speed L0
Note state and its PHY mapping time from presets to coefficients is greater than the dura-
tion of two TS ordered sets (OS); the controller does not strictly follow the specification
requirement: “The Port must ensure that no more than 2 TS1 OS with EC=00b are
transmitted due to being in Recovery.RcvrLock before starting to transmit the TS1 OS
required by Recovery.Equalization.” However, this does not impact any functionalities
in the controller if the mapping time is less than the duration of 8 TS OS.
■ If the PHY's mapping time is greater than the duration of 8 TS OS, the controller
cannot prevent transmitting 8 or more TS1 OS with EC=00b, which is interpreted by
the remote partner side as a condition to go to Recovery.RcvrCfg instead of
Recovery.Equalization. This defeats the intent of redoing equalization. This should
never happen because the PHY typically takes less than the duration of two TS OS to
complete the mapping.

■ (1) Dynamic MAC


The coefficients are dynamically mapped in the MAC. The MAC maps a preset to actual coefficients
using the normalized coefficients and the FS and LF values provided by the PHY.
■ (2) Programmable Table
Your application software programs a preset-to-coefficient mapping LUT called “Gen3 EQ Presets to
Coefficients Mapping Register” (GEN3_EQ_PSET_COEF_MAP__i) in the port logic register space.
The adaptation engine in the equalization master sends preset/coefficient requests to the equalization slave
using TS1 ordered sets. The Use Preset bit in the TS1 ordered set directs the equalization slave to map and
use a preset, or to directly use the coefficients supplied in the TS1.

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PCI Express SW Controller Databook Coefficient Tuning Feedback Modes

Figure A-2 Preset Mapping Modes (Symbolic Representation; not Actual Implementation)
DOWNSTREAM PORT
LEC[3:0]

1 0

Phase 1

PHY MAC TABLE 4


M M
A A
C C

PSET_COEF_MAP_MODE
“Use Preset” bit
0 1 2
1 TS1

Phase 1 ||
0 1
Phase 2/3 && ! “Use Preset”

3x6

P P
TX C-1, C0 , C+1
H H
Equalizer
Y Y

P P
H H
FOM/DIR
Y Y

M Coefficient TS1 M
A Adaptation A
C Engine C

UPSTREAM PORT

A.1.2 Coefficient Tuning Feedback Modes


The receiver PHY generates feedback to the transmitter coefficient adaptation engine for determining the
optimal coefficients in phases 2 and 3 as shown in Figure A-3 on page 903. This feedback can be in one of
two types: figure of merit (FOM) or direction control (DIR). FOM is an absolute number from 0 to 255
indicating the quality of the received signal. DIR is a 2-bit control indicating to the coefficient adaptation
engine to increment by 1, decrement by 1, or leave the current coefficient unchanged. Both DIR and FOM
could possibly (for example) be derived by the receiver PHY from the eye opening measurement or a value
that is inversely proportional to the amount of ISI at the edge of the eye. The FOM procedure in the
controller always precedes DIR.

Figure of Merit (FOM)


The coefficient adaptation engine uses the 8-bit feedback from the local PHY on phy_mac_fomfeedback. It
evaluates the FOM for each of the presets (that you specify to check) and then selects that preset which has

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Coefficient Tuning Feedback Modes PCI Express SW Controller Databook

the highest FOM. This can be considered coarse or rough tuning as the only possible coefficient sets are
those specified in the preset table in the PCIe specification. If your PHY does not support FOM, then it is
expected that your PHY returns a constant value on phy_mac_fomfeedback for each preset request (if
any), and the final preset is used as the starting point for the DIR process.

Direction Change (DIR)


The coefficient adaptation engine in the master uses the 2-bit feedback from the local PHY on
phy_mac_dirfeedback to fine tune the coefficients. There are two bits in phy_mac_dirfeedback for each of
the three coefficients in the transmit filter, indicating whether to increment-by-1, decrement-by-1, or leave
unchanged the current coefficient value. This can be considered as fine tuning. If your PHY does not
support DIR then you can skip this process by setting the Feedback Mode field in the Gen3 EQ Control
Register GEN3_EQ_CONTROL_OFF to 1 as indicated in Figure A-3 on page 903.

DIR Convergence Criteria


When you are only using FOM feedback, then the equalization process is finished after you have
determined which preset produces the highest figure of merit. When you are using DIR feedback, then the
controller normally considers coefficient optimization to be complete when the DIR feedback on all lanes is
0. You can optionally apply settling or windowed filtering to the DIR result. This is an optional mode that
allows the controller to use a different decision process to decide when coefficient optimization is complete.
It may be useful if you observe oscillations on the DIR feedback as you are waiting for a 0 value on all lanes
at the same time. The controller stores metrics corresponding to each coefficient for analysis in a window
defined by you. You program the windowing or settling criteria using the port logic Gen3 EQ Direction
Change Feedback Mode Control Register (GEN3_EQ_FB_MODE_DIR_CHANGE_OFF). You can define the
analysis window (number of evaluations) and the delta between the maximum and minimum coefficient
values. You must select the DIR convergence mode at controller RTL configuration time using the
CX_GEN3_EQ_COEF_CONV_SUPPORTED parameter. You cannot change the mode using software that is, it is
not programmable. This mode is described in more detail later in this section.

It is not advisable to choose convergence support


Note (CX_GEN3_EQ_COEF_CONV_SUPPORTED) if your application cannot program the
convergence mode registers through the DBI.

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PCI Express SW Controller Databook Coefficient Tuning Feedback Modes

Figure A-3 Representational (Not Actual) Flowchart Showing the Sequence of Major Operations for EQ Master

Start Start DIR


Phase 2/3

Calculate next
Preset
coefficient and
Request Vector
request remote
In Gen 3 EQ
TX to use it
Control register
= 0x0

No
Store DIR
feedback from
Start FOM local PHY

Request
remote TX to Use
advanced
use next No convergence
preset
support

Yes
Store FOM
value from local
PHY DIR Store coefficient
feedback is 0
and delta
for all
lanes

More
Yes Presets To
Try

Settling criteria
No
No matched

Select preset
with highest Yes
FOM and
request remote
TX to use it .

Gen3 EQ
Control register ->
Feedback Mode =
0x0

End

No

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Master Operation in FOM Mode


The controller fine tunes the link partner using only preset requests. Upon entry into phase 2 (USP) or phase
3 (DSP) in Figure A-4 on page 907, the EQ master proceeds in consecutive steps as follows:
1. The unmodified settings of the remote transmitter are evaluated.
2. The presets in the Preset Request Vector field are requested and evaluated. Preset requests are made
(one for each bit set in the Preset Request Vector in the Gen3 EQ Control Register GEN3_EQ_CON-
TROL_OFF) to the link partner. If accepted, an evaluation is made to the local PHY which returns a FOM
on the relevant lane of phy_mac_fomfeedback[NL*8-1:0].
3. The final request to the remote partner is the preset with the highest FOM from all the previous evalu-
ations. The preset that returned (through phy_mac_fomfeedback) the highest FOM in step 2 is
requested again. When the final preset request is accepted by the remote partner on all lanes, then
optimal settings are achieved.
Notes:
■ For step 3, it is also possible to choose (using the Include Initial FOM field in the Gen3 EQ Control
Register GEN3_EQ_CONTROL_OFF), whether to include or not the FOM feedback from the evaluation
performed in step 1, when finding the highest FOM among all preset evaluations.
■ Typically this mode is used in conjunction when you select multiple presets in the Preset Request
Vector field, such that multiple evaluations are performed in step 2, and a final choice is made in step 3.

Master Operation in DIR Mode


The controller initially tunes the link partner using preset requests. Upon entry into phase 2 (USP) or phase
3 (DSP) in Figure A-4 on page 907, the EQ master proceeds in consecutive steps as follows:
1. The unmodified settings of the remote transmitter are evaluated.
2. The presets in the Preset Request Vector field are requested and evaluated. Preset requests are made
(one for each bit set in the Preset Request Vector in the Gen3 EQ Control Register GEN3_EQ_CON-
TROL_OFF) to the link partner. If accepted, an evaluation is made to the local PHY which returns a FOM
on the relevant lane of phy_mac_fomfeedback[NL*8-1:0]. This step is optional, and can be skipped
by programming the Preset Request Vector field to all zeros. If your PHY does not support FOM, then
it is expected that your PHY returns a constant value on phy_mac_fomfeedback for each preset
request (if any), and the final preset is used as the starting point for the DIR process.
3. The final preset request to the remote partner is the preset with the highest FOM from all the previous
evaluations. The preset that returned (through phy_mac_fomfeedback) the highest FOM in step 2 is
requested again. This step is optional, and can be skipped by programming the Preset Request Vector
field to all zeros.
4. Incremental changes to the remote transmitter coefficients are requested and evaluated, until optimal
settings are found, or the 24 ms timeout expires.
The CX_GEN3_EQ_COEF_CONV_SUPPORTED parameter determines if the controller implements additional
logic for checking that step 4 is converging toward a stable point.
When you set it to 0, the controller uses a simple procedure to find optimal coefficient settings using the DIR
value fed back from the PHY on the relevant lane of phy_mac_dirfeedback[NL*6-1:0].When bits [5:4]
and bits [1:0] (pre and post-cursor) on the relevant lane of phy_mac_dirfeedback[NL*6-1:0] are 0x0 for
all lanes, then optimal settings are achieved.
When you set it to 1, the controller implements more sophisticated criteria to determine when the current
remote transmitter coefficients are optimal. The criteria require that the coefficients of the remote

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PCI Express SW Controller Databook Other Features and Limitations

transmitter, requested and evaluated in the last N attempts have a maximum delta that does not exceed a
value D. The convergence parameters N and D are programmable and correspond respectively to the
Convergence Windows Depth and Convergence Window Aperture fields in the Gen3 EQ Direction Change
Feedback Mode Control Register (GEN3_EQ_FB_MODE_DIR_CHANGE_OFF). To prevent premature
convergence, the criteria also require that a minimum time T has elapsed from when the EQ Master phase
has started. The value of this timer T is programmable in the Gen3 EQ Direction Change Feedback Mode
Control Register (GEN3_EQ_FB_MODE_DIR_CHANGE_OFF).
Notes:
■ When step 2 and 3 are skipped, the incremental adjustments of the coefficients in step 4 starts from the
settings that the remote transmitter has used to enter phase 2 or phase 3. When step 2 and 3 are
executed, the incremental adjustments of the coefficients start from the final preset requested in step 3.
■ For step 3, it is also possible to choose (using the Include Initial FOM field in the Gen3 EQ Control
Register GEN3_EQ_CONTROL_OFF), whether to include or not the FOM feedback from the evaluation
performed in Step 1, when finding the highest FOM among all Preset evaluations.
■ Typically this mode is used in conjunction with zero, or at most one preset selected in the Preset
Request Vector field, such that no more than one evaluation is performed in step 2.

A.1.3 Other Features and Limitations


Master 24ms Timeout
You can program the controller to the behavior of the EQ master LTSSM state machines, when the
coefficient calculation has not converged after the 24ms timeout. Instead of moving back to Recovery.Speed
(which is the PCI Express Base Specification, Revision 4.0, Version 1.0 behavior), the EQ master LTSSM
continues as normal (phase 3 if USP, Recovery.RcvrLock if DSP). For more information, see Gen3 EQ
Control Register GEN3_EQ_CONTROL_OFF.
Limitations
In Recovery.RcvrLock, there is no support for directing the controller to an arbitrary equalization phase.

A.1.4 Programming Registers


The following registers are used for programming the Gen3 or above EQ logic.

Table A-1 Port Logic Registers Used

Bits Default

+0x190 Gen3 Control Register

+0x194 Gen3 EQ FS and LF Register

+0x198 Gen3 EQ Presets To Coefficients Mapping Register

+0x19C Gen3 EQ Preset Index Register

+0x1A4 Gen3 EQ Status Register

+0x1A8 Gen3 EQ Control Register

+0x1AC Gen3 EQ Direction Change Feedback Mode Control Register

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The Gen3 EQ Presets to Coefficients Mapping registers are programmed through a register indirect
addressing scheme (using an index register) to reduce the address footprint in the PCI Express extended
configuration space. This register is only used when you set the Gen3 Equalization Presets to Coefficients
Mapping Mode to Programmable Table, by setting the CX_GEN3_EQ_PSET_COEF_MAP_MODE configuration
parameter to 2. The default value for each register is given in Table A-2.

Table A-2 Default Coefficient Values for Each Preset Index

Preset Index DEFAULT_GEN3_EQ_POSTCURSOR_PSE DEFAULT_GEN3_EQ_PRECURSOR_PSET


(i) Ti i

0 round(DEFAULT_GEN3_EQ_LOCAL_FS/4) 0

1 round(DEFAULT_GEN3_EQ_LOCAL_FS/6) 0

2 round(DEFAULT_GEN3_EQ_LOCAL_FS/5) 0

3 round(DEFAULT_GEN3_EQ_LOCAL_FS/8) 0

4 0 0

5 0 round(DEFAULT_GEN3_EQ_LOCAL_FS/10)

6 0 round(DEFAULT_GEN3_EQ_LOCAL_FS/8)

7 round(DEFAULT_GEN3_EQ_LOCAL_FS/5) round(DEFAULT_GEN3_EQ_LOCAL_FS/10)

8 round (DEFAULT_GEN3_EQ_LOCAL_FS/8) round(DEFAULT_GEN3_EQ_LOCAL_FS/8)

9 0 round(DEFAULT_GEN3_EQ_LOCAL_FS/6)

round((DEFAULT_GEN3_EQ_LOCAL_FS -
10 0
DEFAULT_GEN3_EQ_LOCAL_LF)/2)

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PCI Express SW Controller Databook Detailed Equalization Procedure

A.2 Detailed Equalization Procedure


In Section 4.2.3., Link Equalization Procedure for 8.0 GT/s Data Rate (and 4.3.3.5.1., 8.0 GT/s Transmitter
Equalization) of the PCI Express Base Specification, Revision 4.0, Version 1.0, there is provision for two
mechanisms to initiate the equalization procedure: hardware autonomous (strongly recommended) and by
software. The following acronyms are used in the following description of the equalization procedure.
■ LF: Low Frequency.
■ FS: Full Swing.
■ ecnTS1: Gen3 or above data rate formatted TS1 with EC[1:0] (Equalization Control field in symbol 6)
set to n.
■ eqTS2: Gen1/2 data rate TS2 with Gen3 equalization presets in symbol 6.
■ 8geqTS2: Gen3 data rate TS2 with Gen4 equalization presets in symbol 7.

A.2.1 Equalization Operations at the PHY Interface


During the equalization procedure the LTSSM moves through a number of different states, as indicated in
Figure A-4 on page 907. The following sections outline the behavior of the interface between the PCIe
controller and the PHY in the various equalization states of the LTSSM

Figure A-4 Equalization States in the LTSSM


!p23_ (2 4ms &
32 exit _m
!p2 ms / o de)
/ 3 2m
3_e (24 s
24ms / xit ms
_m
12ms od &
12ms e)

Eq Eq Eq Eq
RcvrCfg Speed RcvrLock Phase 0 Phase 1 Phase 2 Phase 3
done | (24ms &
e3

p23_exit_mode
as
ph

& USP)
Legend: = USP only DS P)
2_

ode &
se

xi t_m
ha

= DSP & USP 23_e


!p

s&p
|| (2 4m
DSP / USP do ne

Programming of Presets
When negotiating to Gen3 speed, before the first speed change to Gen3, the DSP must be programmed with
the preset values for its own transmitter and receiver (local presets) and the preset values for the USP
(remote presets). The values are independent for each lane and are programmed in the corresponding LEC
of the Secondary PCIe Extended capability.
When negotiating to Gen4 speed, before the first speed change to Gen4, the DSP must be programmed with
the preset values for its own transmitter and receiver (local presets) and the preset values for the USP
(remote presets). The USP can be programmed with the preset values for the transmitter preset values for
the DSP (remote presets). The values are independent for each lane and are programmed in the
corresponding LEC2 of the Secondary PCIe Extended capability.

A.2.2 Recovery.RcvrCfg
When negotiating to Gen3 speed, before the speed change to Gen3 data rate, each component is required to
enter Recovery from L0. In Recovery.RcvrCfg the DSP sends eqTS2s to the USP with the preset fields
reflecting the values programmed in the LEC registers. The USP is required to latch the preset fields in
received eqTS2s and report the latched values as RO fields in the LEC registers.
When negotiating to Gen4 speed, before the speed change to Gen4 data rate, each component is required to
enter Recovery from L0. In Recovery.RcvrCfg the DSP sends 8geqTS2s to the USP with the preset fields
reflecting the values programmed in the LEC2 registers. The USP is required to latch the preset fields in

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received 8geqTS2s and report the latched values as RO fields in the LEC2 registers. If “Upstream Port Send
8GT/s EQ TS2 Disable” (in GEN3_RELATED_OFF) for Gen4 is set to 0b, the USP controller sends 8geqTS2s to
the DSP with transmitter preset fields reflecting the values programmed in the LEC2 registers. The DSP is
required to latch the preset fields in received 8geqTS2s.

A.2.3 Recovery.Speed
In preparation for the speed change to Gen3 or above the PCIe controller asserts mac_phy_txelecidle to
the PHY and updates mac_phy_rate[1:0] to 2’b10(Gen3) or 2'b11(Gen4) to request a data rate change.
The request returning phy_mac_phystatus. Following phy_mac_phystatus the PCIe controller updates
the internal data rate variable (used in LTSSM) to match the requested data rate on mac_phy_rate.
At this point the PHY asserts valid values on phy_mac_localfs[5:0] and phy_mac_locallf[5:0].
These values correspond to FS and LF in use by the PHY transmitter. The PCIe controller uses these values
to check that the coefficients—corresponding to the preset that must be initially used at Gen3 data rate
(obtained from the eqTS2s for USP or from the LEC for DSP) or Gen4 data rate (obtained from the 8geqTS2s
for USP/DSP or from the LEC2 for DSP) —are legal according to the rules in chapter 4.2.3.1 of the PCI
Express Base Specification, Revision 4.0, Version 1.0. The same LF and FS values are also advertised through
ec1TS1s to the remote link partner during phase 1 of the equalization procedure.
To obtain the coefficients corresponding to the initial preset, the PCIe controller requests the PHY to
perform the conversion, by configuring CX_GEN3_EQ_PSET_COEF_MAP_MODE to Dynamic PHY. This is
done by asserting mac_phy_getlocal_pset_coef with mac_phy_local_pset_index[3:0] set to the
encoding of the preset. When the PHY responds with phy_mac_local_tx_coef_valid, the PCIe
controller checks that the values on phy_mac_local_tx_pset_coef[17:0]are legal, and if legal, it
reflects the same values into mac_phy_txdeemph[17:0].
When the values on phy_mac_local_tx_pset_coef[17:0]are not legal, the PCIe controller drives
mac_phy_txdeemph[17:0] with the coefficients that correspond to P4, that is, {6'b0,
phy_mac_localfs[5:0], 6'b0}. The controller also drives mac_phy_rxpresethint[2:0] with the
receiver preset Hints obtained from the eqTS2s(for Gen3)/ 8geqTS2s (for Gen4) for USP, or from the LEC
(for Gen3) / LEC2(for Gen4) for DSP. The controller uses the same mechanism for “Dynamic MAC” and
“Programmable Table”, but the mac_phy_getlocal_pset_coef / mac_phy_local_pset_index[3:0],
and phy_mac_local_tx_coef_valid / phy_mac_local_tx_pset_coef[17:0] signals are not used. In
these modes, the PCIe controller uses internal signals to do the preset-to-coefficients mapping and legality
check. The coefficients are encoded as coefficient[17:0] ={[5:0], [5:0], [5:0]} ={C+1, C0,
C-1} ={post-cursor, cursor, pre-cursor}.

A.2.4 Recovery.RcvrLock
This LTSSM state is entered after Recovery.Speed. Both sides of the link transmit ec0TS1s. When the LTSSM
determines that the equalization procedure must be performed, the next state is Recovery.Equalization.

A.2.5 Recovery.Equalization Phase 0


Upstream Port (USP)
The USP transmits ec0TS1s, advertising the coefficients in use by the transmitter, and the preset that are
requested through eqTS2s (for Gen3)/ 8gteqTS2s (for Gen4) received from the DSP in Recovery.RcvrCfg at
Gen1 or Gen2(for Gen3)/ Gen3(for Gen4) data rate. The remote link partner is in phase 1, and transmits
ec1TS1s advertising its own LF and FS. The USP latches LF and FS, and reflects the values into
mac_phy_fs[5:0]and mac_phy_lf[5:0].

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Note: phy_mac_localfs and phy_mac_locallf represent the LF and FS values of the local transmitter in
the USP, but mac_phy_fs and mac_phy_lf represent the LF and FS values of the remote transmitter.
The PHY can use the remote LF and FS to determine how to adjust the coefficients of the remote transmitter
during phase 2. The procedure moves to phase 1 after receiving two ec1TS1s. The PCIe controller asserts the
smlh_ltssm_state_rcvry_eq signal for the complete equalization state, including EQ phases 0, 1, 2, and
3.

A.2.6 Recovery.Equalization Phase 1


Downstream Port (DSP)
Phase 1 is entered by DSP after Recovery.RcvrLock, when the LTSSM determines that the equalization
procedure must be performed. The DSP advertises FS and LF in transmitted ec1TS1s, and (similar to phase 0
for USP) latches LF and FS values from received ec1TS1, and reflects the values into mac_phy_fs[5:0] and
mac_phy_lf[5:0]. The PHY can use these values to determine how to adjust the coefficients of the remote
transmitter during phase 3. The procedure moves to phase 2 after receiving two ec1TS1s.
Upstream Port (USP)
Equalization phase 1 is entered by USP after phase 0. During phase 1 the USP advertises FS and LF in
transmitted ec1TS1s. The procedure moves to phase 2 when the LTSSM determines that equalization phase
2 and phase 3 must be performed.

A.2.7 Recovery.Equalization Phase 2


Upstream Port (USP)
During phase 2, the USP can request and evaluate a number of different settings in the remote transmitter of
the DSP. Phase 2 ends successfully when all lanes reach optimal settings in the remote transmitter within
24ms, otherwise phase 2 ends unsuccessfully. After phase 2 is completed successfully, the next state is:
■ Recovery.Speed: if there is a 24ms timeout and the Behavior After 24 ms Timeout field of the Gen3 EQ
Control Register GEN3_EQ_CONTROL_OFF is 0, else
■ Equalization phase 3: Before exiting to Equalization phase 3, the port waits 24ms timeout if current
data rate is Gen4 and a Retimer has been detected in Configuration.Complete.
The sequence of operations performed by the PCIe controller as a USP in phase 2 is shown in Figure A-5 on
page 911. The following is a description of the operations in each state of the flowchart performed by the
PCIe controller (as USP) in phase 2. The same operations are performed in phase 3 when the PCIe controller
is the DSP.

Selectable FOM Gen3 EQ Master Mode


Note
You can select how the controller asserts mac_phy_rxeqeval (to instruct the PHY to do Rx
adaptation) using the RXEQ_RGRDLESS_RXTS field in the GEN3_RELATED_OFF register:
■ 0 (Legacy Mode): mac_phy_rxeqeval asserted after 1us and 2 TS1 received from remote
partner.
■ 1 (Rgardless_RxTS Mode): mac_phy_rxeqeval asserts after 500ns regardless of TS's
received or not.

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■ RST: this is the default state. Entered when the LTSSM is not in phase 2. The PCIe controller resets to
the inactive state (zero) all these phase 2 specific inputs to the PHY: mac_phy_rxeqeval, mac_phy_-
invalid_req, mac_phy_rxeqinprogress.
■ INIT: the controller asserts mac_phy_rxeqinprogress, latches the preset and coefficients in use on the
remote side from the received ec2TS1s, and initializes the internal registers containing the preset and
coefficients to be evaluated by the local receiver.If EQ_EIEOS_CNT field of GEN3_RELATED_OFF
Register is set to '1', the next state is EVAL, else the next state is WAIT_REI.
■ Wait_REI:
Rgardless_RxTS Mode: The next state is EVAL, as the controller asserts mac_phy_rxeqeval regardless
of the fact that RX TS1s are detected or not. The REI bit is set to '1' only when any lane asserts mac_-
phy_rxeqeval.
Legacy Mode: If all active lanes are sending TS1s with REI bit set to '1' or there is a 2ms timeout, the next
state is EVAL. The condition that all active lanes are sending TS1s with REI bit set to '1' is dependent
on whether all the active lanes achieve Block Alignment after the remote partner applies the new EQ
settings to its transmitter or not. This is done to filter out scenarios which fail EQ evaluation.
For example, if the controller detects TS1s on any lane and sends TS1s with REI bit set to the remote
partner, the remote partner immediately sends an EIEOS after 65536 TS1s across all lanes; as a result
of this, lanes without Block Alignment may not obtain Block Alignment for the new EQ settings.
If EQ_EIEOS_CNT field of GEN3_RELATED_OFF Register is set to '0' during PHY's evaluation of active
lanes losing Block Alignment (phy_mac_rxvalid =0), the controller transmits TS1s with REI bit reset
to '0' on all active lanes so that the PHY can obtain Block Alignment again.
■ EVAL:
Rgardless_RxTS Mode: After 500ns timeout since new request the controller asserts mac_phy_rx-
eqeval to instruct the PHY to evaluate the current remote transmitter settings. After all lanes involved
have indicated completion of the evaluation cycle with phy_mac_phystatus, the controller
de-asserts mac_phy_rxeqeval immediately. If all lanes involved detected TS1s after 1us timeout
since new request or 2ms timeout the next state is FEEDBACK.
Legacy Mode: the controller immediately asserts mac_phy_rxeqeval. After all involved lanes have
received phy_mac_phystatus the next state is FEEDBACK.
All modes: during the evaluation cycle if any lane involved does not received phy_mac_phystatus
after 2ms timeout and GEN3_EQ_EVAL_2MS_DISABLE field of GEN3_EQ_CONTROL_OFF Register is set
to ‘0’, or 24ms timeout, the next state is ABORT.
Depending upon the cause of transition to EVAL state, the following action should be taken with
respect to coefficients:
❑ If the EVAL state is entered because of a valid request (accepted by remote partner), then latch the
coefficients in use by remote transmitter.
❑ If the EVAL state is entered because of an invalid request (rejected by remote partner) or 2ms
timeout (no reject or accept is received), then do not latch the coefficients. Latching the coefficients
causes phy_mac_dirfeedback[5:0] to generate new coefficients based on valid coefficients
during transition from the final preset request to the first coefficients request.

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PCI Express SW Controller Databook Recovery.Equalization Phase 2

Figure A-5 EQ Master Flowchart Showing the Sequence of Operations in Phase 2 when PCIe Controller is USP
RST

Phase 2 No

Yes

S EXIT INIT

U EXIT
REI disable ?
Yes
No

WAIT_REI

EVAL

timeout
500ns No
Yes

rxeqeval <= 1

Yes
accept Yes

No pset_accept
<= 1

reject Yes
No pset_reject
<= 1
SKIP_EVAL

phystatus
Yes asserted all &&
timeout_1us
rxeqeval <= 0

Yes pset_accept ||
No phystatus||
pset_reject
timeout 2ms No

No

timeout 2ms
ti meout 2ms &&
!t im eout _2ms _dis Yes ABORT
Yes
No
No
pset_reject
<= 1 timeout 24ms Yes

No

state==EVAL Yes
?

No

FEEDBACK

Yes optimal

No

NEWCOEF

legal No INV REQ

Yes

REQ

WAITRESP

Yes
RXEQ_RLESS_RXTS
&& FOM ?

No pset_accept <= 1
TIMEOUT_REQ

accept Yes
No
No

reject Yes FOM?

No
No

timeout 2ms Yes FOM?

No
Yes

No timeout 24ms Yes

pset_reject <= 1

■ FEEDBACK: the controller de-asserts mac_phy_rxeqeval. When the Preset Request Vector field of
the Gen3 EQ Control Register GEN3_EQ_CONTROL_OFF has any bits set, the LTSSM moves to
NEWCOEFF and executes loops so that each preset in the Preset Request Vector field is requested and
evaluated. When all presets are requested and evaluated, then a final preset with the highest FOM
from phy_mac_fomfeedback[7:0] is requested.
❑ If the final preset request is rejected by the remote partner, and if the feedback mode is FOM, then
the next state is EXIT (with unsuccessful status), else if the final preset request is accepted by the
remote partner, next state is EXIT (with successful status).
❑ When the Preset Request Vector field is 0 (no preset request) or the feedback mode is Direction
Change after all preset requests, then the controller evaluates the feedback provided by the PHY

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on phy_mac_dirfeedback. It then determines from that feedback, if the current settings of the
remote transmitter are optimal. When they are optimal, the next state is EXIT (with successful
status), otherwise the next state is NEWCOEF.
■ NEWCOEF:
❑ For preset requests, the requested preset value is determined by right-shifting the 16-bit Preset
Request Vector field of the Gen3 EQ Control Register (GEN3_EQ_CONTROL_OFF) until bit[0] is 1.
This right-shifted number becomes the requested preset value. If the preset is found, the next state
is REQ.
❑ For coefficients requests, new coefficients for evaluation are calculated by applying the direction
change feedback to the current coefficients under evaluation. If the results satisfies the rules from
4.2.3.1 in the PCI Express Base Specification, Revision 4.0, Version 1.0, the next state is REQ, else it is
INV REQ.
■ REQ: the PCIe controller transmits ec2TS1s (preset/coefficients request by setting Use Preset bit to
1/0) to request the remote link partner to change the transmitter settings to the new preset or coeffi-
cients calculated in the previous state. Next state is WAITRESP.
■ WAITRESP:
Rgardless_RxTS: The next state is EVAL where the controller asserts mac_phy_rxeqeval after 500ns
timeout and start detecting TS1s after 1us timeout since new preset request.
Legacy Mode: The controller monitors the received ec2TS1s (after 1us timeout since new request), to
determine if the remote link partner has accepted the request to change its transmitter settings.
❑ If the request is accepted and EQ_EIEOS_CNT field of GEN3_RELATED_OFF Register is set to '1', the
next state is EVAL.
❑ If the request is accepted and EQ_EIEOS_CNT field of GEN3_RELATED_OFF Register is set to '0', the
next state is WAIT_REI.
❑ If the request is rejected and it is a FOM request, the next state is SKIP_EVAL.
❑ If the request is rejected and it is a DIR request, the next state is INV REQ.
❑ If request is FOM after a 2ms timeout the next state is SKIP_EVAL.
❑ If request is DIR after 2ms timeout the next state is TIMEOUT_REQ.
❑ Otherwise after 24ms timeout the next state is EXIT with unsuccessful status.
■ SKIP_EVAL: this state does not assert mac_phy_rxeqeval for the PHY to perform evaluation, as the
requested preset is rejected or does not work on the lane. The next state is FEEDBACK to seek the next
new preset after all active lanes (excluding the SKIP_EVAL lanes) complete evaluation. Otherwise,
after 24ms timeout the next state is EXIT with unsuccessful status.
■ TIMEOUT_REQ: this state is used to prepare the request needed to restore the last successful coeffi-
cients into the remote transmitter. The next state is REQ.
■ INV REQ: this state is used to assert mac_phy_invalid_req to indicate to the PHY, that the feedback
on the latest evaluation generated an invalid set of coefficients for the remote link partner.
The next state is EVAL if EQ_EIEOS_CNT field of GEN3_RELATED_OFF Register is set to '1'; Else, the
next state is WAIT_REI. The evaluation on the current set of coefficients is repeated (the PCIe
controller does not request through ec2TS1s any change to the remote transmitter settings in this case)
to give the PHY an opportunity to provide a different feedback on the same set of coefficients.
■ ABORT: this state is entered when the controller needs to abort an evaluation cycle (because of 2ms1
or 24ms timeout while mac_phy_rxeqeval is asserted, and the PHY has not yet terminated the eval-
1. GEN3_EQ_EVAL_2MS_DISABLE field of the GEN3_EQ_CONTROL_OFF register is set to ‘0’; its default value is ‘1’.

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uation with phy_mac_phystatus).The controller asserts the mac_phy_rxeqeval signal and then
waits for the PHY to acknowledge with phy_mac_phystatus. The next state is EXIT with unsuc-
cessful status, after the PHY responds on phy_mac_phystatus or a timeout.

Downstream port (DSP)


During phase 2, the DSP receives requests from the USP to change the settings in its local transmitter.
Requests are encoded within the received ec2TS1s in the form of presets or coefficients. To obtain the
coefficients corresponding to the requested preset, the controller requests the PHY, MAC, or Programmable
Table to perform the conversion, in a way similar to the protocol already described for the conversion of the
initial preset in Recovery.Speed. When the coefficients for the request are available, the controller uses the
local FS and LF (from phy_mac_localfs[5:0] and phy_mac_locallf[5:0]) to check that the coefficients
are legal according to the rules in “4.2.3.1 Rules for Transmitter Coefficients” section of the PCI Express Base
Specification, Revision 4.0, Version 1.0. If the coefficients are legal the controller drives
mac_phy_txdeemph[17:0]accordingly, else mac_phy_txdeemph is left unchanged. The process is
repeated at every new request. The sequence of operations performed by the controller as a DSP in phase 2
is shown in Figure A-6 on page 914. The following is a description of the operations in each state of the
flowchart performed by the controller. The same operations are performed in phase 3 when the controller is
the USP.
■ RST: This is the default state, entered when the LTSSM is not in phase 2.
■ WAIT REQ: the PCIe controller monitors received ec2TS1s for a request to change the transmitter
settings.
■ PSET2COEF: For Dynamic PHY mapping mode, the controller asserts mac_phy_getlo-
cal_pset_coef with mac_phy_local_pset_index[3:0]set to the encoding of the preset, and
waits until the PHY responds with phy_mac_local_tx_coef_valid. For Dynamic MAC mapping
mode, the controller calculates the coefficients from received preset internally. For Programmable
Table mapping mode, the controller picks the programmed coefficients mapped to the corresponding
preset.
■ CHANGE TXDEEMPH: controller changes mac_phy_txdeemph[17:0] to apply the new settings to
PHY

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Recovery.Equalization Phase 3 (DSP/USP) PCI Express SW Controller Databook

Figure A-6 EQ Slave Flowchart Showing Sequence of Operations in Phase 2 when PCIe Controller is DSP

RST

Phase 2 No

Yes

WAIT REQ

Yes Preset

PSET2 No
COEF

legal No

Yes
CHANGE
TXDEEMPH

A.2.8 Recovery.Equalization Phase 3 (DSP/USP)


Phase 3 is similar to phase 2, with the DSP taking the role of the USP, and the USP taking the role of the DSP.

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PCI Express SW Controller Databook Usage Example

A.3 Usage Example


The section provides an example for setting up Gen3 or above EQ. It also describes the sequence of events
that the controller progresses through.
EQ Master
■ Hardware Configuration
❑ CX_GEN3_EQ_COEF_CONV_SUPPORTED =1
■ Gen3 EQ Register Programming
❑ Gen3 Control Register bit [13] = 1'b0 (Legacy Mode, not Rgardless_RxTS Mode)
❑ Gen3 EQ Control Register bit [3:0] =4b0000 (Direction Change Feedback Mode)
❑ Gen3 EQ Control Register bit [23:8] =16b000000000100100 (Preset Request Vector). Presets 2 and 5
is requested and evaluated in terms of the preset vector.
❑ Gen3 EQ Control Register bit [24] =1'b1 (the initial preset evaluation FOM feedback to be included
for finding the highest FOM).
❑ Gen3 EQ Direction Change Feedback Mode Control Register bit [4:0] =5b01010 (minimum time to
check convergence is 10ms)
❑ Gen3 EQ Direction Change Feedback Mode Control Register bit [9:5] =5b00011 (number of consec-
utive coefficients evaluations is 3)
❑ Gen3 EQ Direction Change Feedback Mode Control Register bit [13:10] =4b0001 (pre-cursor
maximum depth (delta) is 1 within the convergence window)
❑ Gen3 EQ Direction Change Feedback Mode Control Register bit [17:14] =4b0001 (post-cursor
maximum depth (delta) is 1 within the convergence window)
■ Requests and Evaluations for one Lane
a. Assuming the latched mac_phy_fs and mac_phy_lf values transmitted by the remote partner in
EQ phase1 are 6h2b and 6h12.
b. When the controller enters EQ master, the state machine shown in Figure A-5 on page 911 moves
to INIT. mac_phy_rxeqinprogress =1, assuming the latched preset =4b0001 and coefficients
=18h0b800 transmitted initially by the remote partner. Next state is EVAL.
c. In EVAL, mac_phy_rxeqeval =1 for PHY to do evaluation for the initial preset 4b0001, 2ms timer
kicks off, waiting for phy_mac_phystatus asserted back. Assuming phy_mac_phystatus is
asserted back with phy_mac_fomfeedback[7:0] =8d12 within 2ms, the controller moves to
FEEDBACK.
d. In FEEDBACK, mac_phy_rxeqeval =0 to terminate the PHYs evaluation. Next state is
NEWCOEFF.
e. In NEWCOEFF, latch FOM =8d12 and its preset =4b0001. Right-shifting the preset vector until its
bit [0] =1 to find out the first requested preset value 2, and then move to REQ.
f. In REQ, set Use Preset bit to 1 and preset to 2 into the proper fields of the transmitting TS1s. Send
TS1s to the remote partner, reset and start the 2ms timer. Next state is WAITRESP.
g. In WAITRESP, assuming accept is received in the response TS1s from the remote partner within
2ms. Next state is EVAL.
h. In EVAL, mac_phy_rxeqeval =1for PHY to do evaluation for the requested preset value 2,
waiting for phy_mac_phystatus asserted back. Assuming phy_mac_phystatus is asserted back

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Usage Example PCI Express SW Controller Databook

with phy_mac_fomfeedback[7:0] =8d188 within 2ms, the controller moves to FEEDBACK and
then to NEWCOEFF.
i. In NEWCOEFF, latch FOM =8d188 and its corresponding preset 2, as 188 is larger than 12 (you
must find the preset with highest FOM). Then find out the second requested preset 5 and repeat
steps f, g, and h. Assuming phy_mac_fomfeedback[7:0] =8d66 for the last request preset 5. As
phy_mac_fomfeedback =66 is not the highest FOM, you must to do one more preset request, that
is, final preset request for the preset 2 again as the preset 2 has highest FOM =8d188. After WAIT-
RESP, next state is EVAL.
j. In EVAL, mac_phy_rxeqeval =1, latch coefficients received in TS1s from the remote partner that
are the coefficients in use by the remote partner. Assuming the latched coefficients= 18h00f80. After
receiving phy_mac_phystatus from PHY with phy_mac_dirfeedback =6b010101, move to
FEEDBACK to do coefficients requests. All the preset requests are completed.
k. In FEEDBACK, mac_phy_rxeqeval =0. Cannot get optimal settings as the programmed number
of consecutive coefficients evaluations is 3. So far in the coefficients evaluation process, it is 0. Next
state is NEWCOEFF.
l. In NEWCOEFF, need to calculate new coefficients. The current coefficients are =18h00f80, then C-1
=6b000000, C0 =6b111110, C+1 =6b000000. Because phy_mac_dirfeedback =6b010101, so the
new coefficients are C-1 =6b000001, C+1 =6b000001, C0 =(mac_phy_fs C-1 C+1) =(6h2b 1 1) =6h29.
The new coefficients =18h01a41. Now check the new coefficients legality (“4.2.3.1 Rules for Trans-
mitter Coefficients” section of the PCI Express Base Specification, Revision 4.0, Version 1.0).
Note: C0 is calculated, so ignore phy_mac_dirfeedback[3:2].
■ |C-1| =1 <= Floor (FS/4) =Floor (43/4) =10. So it is legal.
■ |C-1| + C0 + |C+1| =43 =FS =43. So it is legal.
■ C0 - |C-1| - |C+1| =41 >= LF =6h12 =18. So it is legal
Next state is REQ.
m. In REQ, reset and start 2ms timer. Set Use Preset bit to 0 and place the new coefficients C-1, C0 and
C+1 into the correct TS1 fields, and send TS1s to the remote partner. Next state is WAITRESP.
n. In WAITRESP, assuming accept is received in the response TS1s from the remote partner within
2ms. Next state is EVAL.
o. In EVAL, mac_phy_rxeqeval =1, the number of evaluation increments by 1 and push C-1 =1
and C+1 =1 into coefficient queues. Waiting for phy_mac_phystatus back from PHY. Assuming
phy_mac_phystatus is asserted back with phy_mac_dirfeedback =6b010001within 2ms, then
move to FEEDBACK and repeat steps k, l, m, and n.
p. After re-enter EVAL, mac_phy_rxeqeval =1. The number of consecutive evaluations is 2 and
C-1 =2 and C+1 =2 are pushed into the queues. Waiting for phy_mac_phystatus back from PHY.
Assuming phy_mac_phystatus is asserted back with phy_mac_dirfeedback
=6b011110within 2ms, then move to FEEDBACK and repeat steps k, l, m, and n.
q. After re-entering EVAL, mac_phy_rxeqeval =1, and the number of consecutive evaluations is
3, and C-1 =1 and C+1 =3 are pushed into queues. Waiting for phy_mac_phystatus back from
PHY. Assuming phy_mac_phystatus is asserted back with phy_mac_dirfeedback =6b101000
within 2ms, then move to FEEDBACK.

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PCI Express SW Controller Databook Usage Example

r. In FEEDBACK, mac_phy_rxeqeval =0, assuming the time spent on the phase in the EQ master
so far is 9ms, you must find out if the optimal settings are reached as the number of consecutive
evaluations reaches 3 (the programmed number of consecutive coefficients evaluations).
i. For C-1, three coefficients (1, 2, 1) are pushed into its queue. So the delta for C-1 is (2-1) =1.
ii. For C+1, three coefficients (1, 2, 3) are pushed into its queue. So the delta for C+1 is (3-1) =2.
Because the programmed maximum delta for C-1 and C+1 is 1, the delta 2 in the queue for C+1
window does not satisfy the programmed maximum delta. In addition, the time for the conver-
gence check does not satisfy the programmed minimum time 10ms because it is 9ms by now. So
the controller can proceed with the next request. Repeat l, m, and n.
s. After re-entering EVAL, mac_phy_rxeqeval =1, the number of consecutive evaluations is 3 and C-1
=1 and C+1 =2 are pushed into queues. Waiting for phy_mac_phystatus back from PHY.
Assuming phy_mac_phystatus is asserted back with phy_mac_dirfeedback
=6b010110within 2ms, then move to FEEDBACK.
t. In FEEDBACK, mac_phy_rxeqeval =0, assuming the time spent on the phase in the EQ master
so far is 10.5ms. You must find out if the optimal settings are reached as the number of consecutive
evaluations reaches 3.
i. For C-1, three latest coefficients (2, 1, 1) are pushed into its queue. So the delta for C-1 is (2-1) =1.
ii. For C+1, three latest coefficients (2, 3, 2) are pushed into its queue. So the delta for C+1 is (3-2)
=1.
Because the programmed maximum delta for C-1 and C+1 is 1, the delta in the both queues for C-1
and C+1 window does satisfy the programmed maximum delta. The time for the convergence
check also satisfies the programmed minimum time of 10ms because it is 10.5ms by now. Next
state is EXIT.
u. In EXIT, mac_phy_rxeqinprogress =0, the successful status bit for the phase is set to 1. The
PCIe controller moves to the phase3 for USP or Recovery.RcvrLock for DSP.
EQ Slave
■ Hardware Configuration
❑ CX_GEN3_EQ_PSET_COEF_MAP_MODE =0 (Dynamic PHY)
■ Mapping and Applying
a. Assuming phy_mac_localfs =6’h3e and phy_mac_locallf =6’h11 are already set before the
port changes to Gen3 or above rate.
b. When the controller enters EQ slave, the state machine shown in Figure A-6 on page 914 moves to
WAITREQ state, transmitter sends TS1s with the preset and coefficients in use. If two consecutive
TS1s with EC[1:0] =2b11 for USP or EC[1:0] =2b10 for DSP have been received in the beginning of
the phase, or two consecutive TS1s (with EC[1:0] =2b11 for USP or EC[1:0] =2b10 for DSP) with a
preset (Use Preset bit =1) different from the last two TS1s with the same EC[1:0] have been received,
next state is PSET2COEF.
c. In PSET2COEF, assuming the received request preset =4b0011, the PCIe controller asserts mac_-
phy_getlocal_pset_coef for one cycle with mac_phy_local_pset_index[3:0] =4b0011 to
PHY. Waiting for coefficients mapped back from PHY. A few cycles later, PHY completes mapping
and asserts phy_mac_local_tx_coef_valid back with phy_mac_local_tx_pset_coef
=18h0a885(C-1 =6b000101, C0 =6b100010, C+1 =6b001010) for one cycle. Next state is CHAN-
GETXDEEMPH.

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Usage Example PCI Express SW Controller Databook

d. In CHANGETXDEEMPH, the controller needs to check the coefficients legality (“4.2.3.1 Rules for
Transmitter Coefficients” section of the PCI Express Base Specification, Revision 4.0, Version 1.0).
■ |C-1| =5 <= Floor (FS/4) =Floor (62/4) =15. It is legal.
■ |C-1| + C0 + |C+1| =(5 + 34 + 10) =49 !=FS =62. It is illegal.
So phy_mac_local_tx_pset_coef =18h0a885 is not supplied to mac_phy_txde-
emph[17:0]because the coefficients are illegal (invalid). mac_phy_txdeemph[17:0] is left
unchanged. The EQ slave sends EC TS1s with reject and preset =4b0011 in the TS1 fields back to
the remote partner. The remote partner receives the reject and can do the next preset request with
preset =4b1001. The EQ slave receives two EC TS1s with preset =4b1001 different from the last
preset =4b0011, moves to PSET2COEFF.
e. In PSET2COEF, the PCIe controller asserts mac_phy_getlocal_pset_coef for one cycle with
mac_phy_local_pset_index[3:0] =4b1001to PHY. Waiting for coefficients mapped back
from PHY. A few cycles later, PHY completes mapping and asserts phy_mac_local_tx_co-
ef_valid for one cycle with phy_mac_local_tx_pset_coef =18h06c08 (C-1 =6b001000, C0
=6b110000, C+1 =6b000110) back. Next state is CHANGETXDEEMPH.
f. In CHANGETXDEEMPH, the controller checks the coefficients legality first.
■ |C-1| =8 < =Floor (FS/4) =Floor (62/4) =15. It is legal.
■ |C-1| + C0 + |C+1| =(8 + 48 + 6) =62 =FS =62. It is legal.
■ C0 - |C-1| - |C+1| =(48 - 8 - 6) =34 >=LF =17. It is legal.
So phy_mac_local_tx_pset_coef =18h06c08 is supplied to mac_phy_txde-
emph[17:0]because it satisfies the three rules. PHY detects the change on mac_phy_txde-
emph[17:0]and applies it to its transmitter. The EQ slave sends EC TS1s with accept and preset
=4b1001 in the TS1 fields back to the remote partner. The remote partner receives the accept and
starts to do evaluation. After evaluation, the remote partner might not reach optimal settings and
can continue the next preset request or coefficient request until reaching optimal settings. If it is
preset request, repeat steps b-to-f. If the remote partner reaches optimal settings, it moves to the
next EQ phase and send TS1s with EC[1:0] =2b11 for USP or EC[1:0] =2b00 for DSP. The EQ
slave receives TS1s with EC[1:0] =2b11 for DSP or EC[1:0] =2b00 for USP and moves to
Recovery state for USP or EQ phase 3 for DSP. The successful status is set to 1 for this phase.

You can also inspect the VTB test cases at


Hint <workspace>/doc/html/vtb/testenv/index.htmlfor more programming examples. For
more information on VTB, see the Integrating the Controller and VIP using VTB section in the
“Integration” chapter of the User Guide.

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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes

B
Advanced Information: Lane Reversal and

Broken Lanes

This appendix illustrates how the controller uses the lane reversal and lane flip functions to form links and
gives several example using an x8 PCIe controller with an x8 or x4 link partner.

Figure B-1 Reversing and Flipping Architecture

CX_LANE_FLIP_CTRL_EN = 1
CX_AUTO_LANE_FLIP_CTRL_EN =1
CX_AUTO_LANE_FLIP_MUX_ARCH = 2

Auto Reverse Auto Flip Manual Flip


LTSSM LTSSM rx_lane_flip_en /
(Config) (Detect) tx_lane_flip_en

Reversal Flip Mux


7 7
Mux 3

6 6
2

5 5
1

4 4 Logical Lane0
0

Remote Link
Partner
3 3

2 2

1 1

0 0 Physical Lane 0
Logical Lane0

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Advanced Information: Lane Reversal and Broken Lanes PCI Express SW Controller Databook

Table B-1 Lane Reversal and Lane Flipping Configuration Options (All Enabled by Default)

Parameter Muxes Instantiated Notes

CX_AUTO_LANE_FLIP_CTRL_EN=1 ■ Can support a full reversal or a full flip; but not


1 both simultaneously.
CX_AUTO_LANE_FLIP_MUX_ARCH =0

CX_AUTO_LANE_FLIP_CTRL_EN=1 ■ Can support a full or partial reversal, or a full


1 or partial flip; but not both simultaneously.
CX_AUTO_LANE_FLIP_MUX_ARCH =1

CX_AUTO_LANE_FLIP_CTRL_EN=1 ■ Can support a full or partial reversal, and a full


2 or partial flip; but not both simultaneously.
CX_AUTO_LANE_FLIP_MUX_ARCH =2
■ This is the default for new configurations.

Note:
■ Lane0 always refers to physical lane0, as determined by its location in the PIPE interface which is [7:0] or [15:0].
■ Full flip is when Logical Lane0 is connected to Lane NL-1.
■ Partial flip is when Logical Lane0 is connected to either Lane NL/2-1, or Lane NL/4-1, or Lane NL/8-1, and so on.

Note: To use any of these features you must set the configuration parameter CX_LANE_FLIP_CTRL_EN=1 and the
AUTO_LANE_FLIP_CTRL_EN field in GEN2_CTRL_OFF =1.

Note: Flip: When the LTSSM transitions to DETECT_WAIT, meaning that some lanes are detected in DETECT_ACT,
but not all; and lane0 is not detected, the LTSSM autonomously activates a lane flip operation.

Note: Reversal: When the LTSSM transitions to Configuration state and Logical Lane0 receives TS Ordered Sets
with lane number different from '0', the LTSSM automatically performs a lane reversal.

Note: To use this feature you must set the PRE_DET_LANE field in GEN2_CTRL_OFF to 0.
When its value is '0, auto-flip is based on detected lanes and auto-reversal is based on Lane0's lane number in the
received TS Ordered Sets. When its value is not '0', auto-lane multiplexer is based on the programmed value (only
one instantiated multiplexer).

Connection to x2 and x1 link partners work similarly. For more information, see “Link Establishment” on
page 83. It is assumed that you have set the following configuration parameters and register field:
■ CX_LANE_FLIP_CTRL_EN =1
■ CX_AUTO_LANE_FLIP_CTRL_EN =1
■ CX_AUTO_LANE_FLIP_MUX_ARCH =2
■ AUTO_LANE_FLIP_CTRL_EN =1 in GEN2_CTRL_OFF register
■ PRE_DET_LANE =0 in GEN2_CTRL_OFF register
Some of the case examples in this appendix require the programming of the Predetermined Lane for Auto
Flip field (PRE_DET_LANE) in the GEN2_CTRL_OFF port logic register. This field defines which physical lane
is connected to logical Lane0 by the flip operation performed in Detect.
When its value is '0, auto-flip is based on detected lanes and auto-reversal is based on lane0's lane number in
the received TS Ordered Sets. When its value is not '0', auto-lane multiplexer is based on the programmed
value (only one instantiated multiplexer).
Allowed values are:
■ 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1,
depending on which lane is detected

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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes

■ 3'b001: Connect logical Lane0 to physical lane 1


■ 3'b010: Connect logical Lane0 to physical lane 3
■ 3'b011: Connect logical Lane0 to physical lane 7
■ 3'b100: Connect logical Lane0 to physical lane 15
This field is used to restrict the receiver detect procedure to a particular lane when the default detect and
polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to
program this field to a value different from the default is when a lane is asymmetrically broken, that is, it is
detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state. In this case only x1
link can be formed.

If CX_AUTO_LANE_FLIP_CTRL_EN =0 or CX_AUTO_LANE_FLIP_MUX_ARCH =0, the


Note
cases in this appendix illustrating partial flipping cannot be supported.

Normal Link Establishment with Non-reversed/Reversed Lanes; and Wide/Narrow Ports


■ “x8 to x8 (Non-reversed Lanes)” on page 922
■ “x8 to x8 (Reversed Lanes)” on page 922
■ “x8 to x4-Bottom (Non-reversed Lanes)” on page 923
■ “x8 to x4-Bottom (Reversed Lanes)” on page 923
■ “x8 to x4-Top (Non-reversed Lanes)” on page 924
■ “x8 to x4-Top (Reversed Lanes)” on page 924
Link Down-sizing with Non-reversed/Reversed Lanes; and Wide/Narrow Ports
■ “x8 to x8 (Non-reversed Lanes) with Downsize to x4” on page 925
■ “x8 to x8 (Reversed Lanes) with Downsize to x4” on page 925
■ “x8 to x4-Bottom (Non-reversed Lanes) with Downsize to x2” on page 926
■ “x8 to x4-Bottom (Reversed Lanes) with Downsize to x2” on page 927
■ “x8 to x4-Top (Non-reversed Lanes) with Downsize to x2” on page 927
■ “x8 to x4-Top (Reversed Lanes) with Downsize to x2” on page 928
Broken Lane Operation
■ “x8 to x4-Bottom (Lane0 Broken in Detect)” on page 928
■ “x8 to x8 (Lane0 Asymmetrically Broken: OK in Detect; Broken in Polling)” on page 929
■ “x8 to x4-Bottom (Lane0 Asymmetrically Broken: OK in Detect; Broken in Polling)” on page 929
■ “x8 to x2-Bottom (Lane0 Asymmetrically Broken: OK in Detect; Broken in Polling)” on page 930

You can also inspect the VTB test cases at


Hint
<workspace>/doc/html/vtb/testenv/index.html. For more information on VTB, see
“Integrating the Controller and VIP using VTB” section in the “Integration” chapter of the User
Guide.

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Advanced Information: Lane Reversal and Broken Lanes PCI Express SW Controller Databook

Figure B-2 x8 to x8 (Non-reversed Lanes)

LTSSM LTSSM rx_lane_flip_en =0 /


(Config) (Detect) tx_lane_flip_en =0

7 7
7

6 6
6

5 5
5

4 4
4

3 3
3

2 2
2

1 1
1

0 0 Physical Lane 0
0
Logical Lane0 Logical Lane0
Remote Link
Reversal Mux Flip Mux Partner

Figure B-3 x8 to x8 (Reversed Lanes)

LTSSM LTSSM rx_lane_flip_en =0 /


(Config) (Detect) tx_lane_flip_en =0

7 7 Logical Lane0
0

6 6
1

5 5
2

4 4
3

3 3
4

2 2
5

1 1
6

0 0 Physical Lane 0
7
Logical Lane0
Remote Link
Reversal Mux Flip Mux Partner

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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes

Figure B-4 x8 to x4-Bottom (Non-reversed Lanes)

LTSSM LTSSM rx_lane_flip_en =0 /


(Config) (Detect) tx_lane_flip_en =0

7 7

6 6

5 5

4 4

3 3
3

2 2
2

1 1
1

0 0 Physical Lane 0
0
Logical Lane0 Logical Lane0
Remote Link
Reversal Mux Flip Mux Partner

Figure B-5 x8 to x4-Bottom (Reversed Lanes)

LTSSM LTSSM rx_lane_flip_en =0 /


(Config) (Detect) tx_lane_flip_en =0

7 7

6 6

5 5

4 4

3 3 Logical Lane0
0

2 2
1

1 1
2

0 0 Physical Lane 0
3
Logical Lane0
Remote Link
Reversal Mux Flip Mux Partner

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Figure B-6 x8 to x4-Top (Non-reversed Lanes)


GEN2_CTRL_OFF Register fieldPRE_DET_LANE[15:13] =0

LTSSM LTSSM rx_lane_flip_en /


(Config) (Detect) tx_lane_flip_en

7 7 Logical Lane0
0

6 6
1

5 5
2

4 4
3

Remote Link
Partner
3 3

2 2

Manual flip is only needed when


auto flip is not available : your
1 1 application is required to control
the input pins to manually flip
(full) to Lane NL-1.

If auto-flip is enabled , the core


0 0 Physical Lane0 attempts to detect all lanes.
When it sees Lane0 Is not
Logical Lane0 detected, it autonomously auto-
flips (full) to Lane NL-1.
Reversal Mux Flip Mux

Figure B-7 x8 to x4-Top (Reversed Lanes)


GEN2_CTRL_OFF Register field PRE_DET_LANE[15:13] =0

LTSSM LTSSM rx_lane_flip_en /


(Config) (Detect) tx_lane_flip_en

7 7
3

6 6
2

5 5
1

4 4 Logical Lane0
0

Remote Link
Partner

3 3

2 2

Manual flip is only needed when


auto flip is not available : your
1 1 application is required to control
the input pins to manually flip
(full) to Lane NL-1.

If auto-flip is enabled, the core


0 0 Physical Lane0 attempts to detect all lanes.
When it sees Lane0 Is not
Logical Lane0
detected, it autonomously auto-
Reversal Mux Flip Mux flips (full) to Lane NL-1.

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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes

Figure B-8 x8 to x8 (Non-reversed Lanes) with Downsize to x4

LTSSM LTSSM rx_lane_flip_en /


(Config) (Detect) tx_lane_flip_en

7 7 PAD PAD
7

6 6 PAD PAD
6

5 5 PAD PAD
5

4 4 PAD PAD
4

3 3
3

2 2
2

1 1
1

0 0
0

Remote Link
Reversal Mux Flip Mux Partner

Figure B-9 x8 to x8 (Reversed Lanes) with Downsize to x4


Undetected Lane0 to "force" a full x8 flip to allow correct handling of link downsize to x 4

LTSSM LTSSM rx_lane_flip_en /


(Config) (Detect) tx_lane_flip_en

7 7
0

6 6
1

5 5
2

4 4
3

3 3 PAD PAD
4

2 2 PAD PAD
5

1 1 PAD PAD
6

0 0 PAD PAD
7

Remote Link
Reversal Mux Flip Mux Partner

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Figure B-10 x8 to x4-Bottom (Non-reversed Lanes) with Downsize to x2


GEN2_CTRL_OFF Register fieldNUM_OF_LANES = 0x04

LTSSM LTSSM rx_lane_flip_en /


(Config) (Detect) tx_lane_flip_en

7 7

6 6

5 5

4 4

3 3 PAD PAD
3

2 2 PAD PAD
2

1 1
1

0 0
0
Remote Link
Reversal Mux Flip Mux Partner

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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes

Figure B-11 x8 to x4-Bottom (Reversed Lanes) with Downsize to x2


GEN2_CTRL_OFF Register fieldNUM_OF_LANES =0x04
Undetected Lane0 to "force" a partial x4 flip to allow correct handling of link downsize to x 2

LTSSM LTSSM
(Config) (Detect)

7 7

6 6

5 5

4 4

3 3
0

2 2
1

1 1 PAD PAD
2

0 0 PAD PAD
3

Remote Link
Reversal Mux Flip Mux Partner

Figure B-12 x8 to x4-Top (Non-reversed Lanes) with Downsize to x2

LTSSM LTSSM rx_lane_flip_en/


(Config) (Detect) tx_lane_flip_en

7 7 PAD PAD
3

6 6 PAD PAD
2

5 5
1

4 4
0

Remote Link
Partner

3 3

2 2

Not supported.

1 There is no way to connect


1
lane0 from remote partner to
logical lane 0 in the core.

The auto-flip feature currently


only operates in the Detect
0 0 LTSSM state, whereas the
remote link partner requests to
downsize in the Configuration
Reversal Mux Flip Mux LTSSM state.

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Advanced Information: Lane Reversal and Broken Lanes PCI Express SW Controller Databook

Figure B-13 x8 to x4-Top (Reversed Lanes) with Downsize to x2


GEN2_CTRL_OFF Register NUM_OF_LANES =0x04
Lane0 is not detected

LTSSM LTSSM rx_lane_flip_en /


(Config) (Detect) tx_lane_flip_en

7 7
0

6 6
1

PAD PAD
5 5
2

PAD PAD
4 4
3

Remote Link
Partner
3 3

2 2

1 1

0 0

Reversal Mux Flip Mux

Figure B-14 x8 to x4-Bottom (Lane0 Broken in Detect)


GEN2_CTRL_OFF Register field PRE_DET_LANE[15:13] =0

LTSSM LTSSM
(Config) (Detect)

7 7
If auto-flip is enabled, the core
attempts to detect all lanes. When it
sees Lane0 and Lane NL-1 are not
detected, it autonomously auto-flips
(partial) to Lane NL/2 -1.
6 6
PRE_DET_LANE =0 and therefore all
lanes are used for detection.

5 5

4 4

3 3
3

2 2
2

1 1
x2 link also possible 1
depending upon
features of the
remote link partner.
0 0 Physical Lane 0
Logical Lane0
X 0
Remote Link
Reversal Mux Flip Mux Partner

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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes

Figure B-15 x8 to x8 (Lane0 Asymmetrically Broken: OK in Detect; Broken in Polling)


GEN2_CTRL_OFF Register fields
NUM_OF_LANES = 0x04

If auto-flip is enabled
PRE_DET_LANE[15:13] = 3 to “force” a full flip.

Without this register setting, the core will not perform


a full flip, because Lane0 is Correctly detected.

LTSSM LTSSM rx_lane_flip_en/


(Config) (Detect) tx_lane_flip_en

Lane for receiver


7 7 detection in Detect 7

6 6
6

5 5
5

4 4
4

3 3
3

2 2
x2, x4 link also possible if : 2
• The remote link partner supports
it, and
• The controller uses manual lane
flip (GEN2_CTRL_OFF. 1 1
1
AUTO_LANE_FLIP_CTRL_EN
= 0), and manual Tx and Rx
lane reversal (tx_lane_flip_en
=1, rx_lane_flip_en = 1)
0 0 Physical Lane0
0
Logical Lane0 X
Remote Link
Reversal Mux Flip Mux Partner

Figure B-16 x8 to x4-Bottom (Lane0 Asymmetrically Broken: OK in Detect; Broken in Polling)


GEN2_CTRL_OFF Register fields
NUM_OF_LANES = 0x02

If auto-flip is enabled
PRE_DET_LANE[15:13] = 2 to “force” a partial flip to NL/2-1 .

Without this register setting, the core will not perform this flip,
because Lane 0 is correctly detected.

LTSSM LTSSM
(Config) (Detect)

7 7

6 6

5 5

4 4

Lane for receiver


3 3 detection in Detect
3

x2, x4 link also possible if : 2 2


2
• The remote link partner supports
it, and
• The controller uses manual lane
flip (GEN2_CTRL_OFF. 1 1
AUTO_LANE_FLIP_CTRL_EN 1
= 0), and manual Tx and Rx
lane reversal (tx_lane_flip_en
=1, rx_lane_flip_en = 1)
0 0 Physical Lane0
0
Logical Lane0 X
Remote Link
Reversal Mux Flip Mux Partner

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Figure B-17 x8 to x2-Bottom (Lane0 Asymmetrically Broken: OK in Detect; Broken in Polling)


GEN2_CTRL_OFF Register fields
NUM_OF_LANES = 0x01

If auto-flip is enabled
PRE_DET_LANE[15:13] =1 to “force” the core a
partial flip to NL/4-1.

Without this register setting, the core will not perform


this flip , because Lane0 is correctly detected.

LTSSM LTSSM
(Config) (Detect)

7 7

6 6

5 5

4 4

3 3

2 2

Lane for receiver


1 1 detection in Detect
1

Physical Lane0
0 0
0
Logical Lane0 X
Remote Link
Reversal Mux Flip Mux Partner

Figure B-18 x8 to x2 Partial Lane Flip and Partial Lane Reversal


Parameters:
CX_LANE_FLIP_CTRL_EN = 1
CX_AUTO_LANE_FLIP_CTRL_EN = 1
CX_AUTO_LANE_FLIP_MUX_ARCH = 2

Register GEN2_CTRL_OFF fields:


AUTO_LANE_FLIP_CTRL_EN = 1
PRE_DET_LANE[15:13] = 0

LTSSM LTSSM
(Config) (Detect)

7 7

6 6

5 5

4 4

3 3 1

2 2 0

Remote Link
Partner

1 1

0 0
Logical Lane0

Reversal Mux Flip Mux

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PCI Express SW Controller Databook Advanced Information: Loopback

C
Advanced Information: Loopback

The controller supports local and remote digital loopback. The following topics are discussed:
■ “Overview”
■ “Local Digital Loopback (PIPE/RMMI)” on page 933
■ “Local Analog Loopback” on page 935
■ “Remote Digital Loopback” on page 936

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C.1 Overview
The controller supports local digital and analog loopback modes without the need for a remote link partner,
as shown in Figure C-1 and Figure C-2. You can use this mode for chip production test, or in any other
scenario where you do not have a remote link partner. It also supports remote digital loopback with a
remote link partner acting as the loopback slave, as shown in Figure C-3. You can use this mode for board
debug, BER testing, system debug, or in any other scenario where you have a remote link partner.
Loopback in the controller operates on a per link basis only. You cannot operate it on a per lane basis. The
loopback implementation overrides LinkUp to one (it should be zero according to the specification), and
allows the link to initialize as if it is in L0.
For Gen5 with CCIX ESM configurations and the LTSSM transition is from L0 -> Recovery ->
Configuration.Linkwidth.Start -> Loopback.Entry. If ESM enabled on both sides of the link and the test
scenario tries to achieve ESM Data Rate1 in loopback on the link, then before loopback master initiates
loopback entry, it must set Max Link Speed and Target Link Speed to Gen4 rate (Loopback Slave Max and
Target Link Speed can be Gen5 or Gen4 rate).

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PCI Express SW Controller Databook Local Digital Loopback (PIPE/RMMI)

C.2 Local Digital Loopback (PIPE/RMMI)


This section discusses the operation of the controller when entering, and exiting digital local loopback. It
also discusses the behavior of the controller when in local loopback.

Figure C-1 Components Involved in Digital Local Loopback Without a Link Partner
Controller Core
TLP
your generated traffic

TS1
LOOP B A CK_E NA B LE=1
PIPE/
P IP E_LOOP B A CK =1 LTSSM RMMI

P IP E_LOOP B A CK_CONTROL_OFF
register

P ORT_LINK _CTRL_OFF regis ter

1
TLP

your looped -back traffic 0

C.2.1 Entering Local Loopback


The local loopback1 connects the PIPE/RMMI RX signals to the PIPE/RMMI TX signals, and only operates
in the loopback LTSSM state, as the link is not able to train against itself and enter L0. The procedure for
entry into local loopback is:
■ Set the Gen3 Equalization Disable bit in the Gen3 Control Register GEN3_RELATED_OFF. You must do
this, as the PHY has no role in PIPE loopback.
■ Set the PIPE_LOOPBACK bit in the PIPE_LOOPBACK_CONTROL_OFF register.
■ Set the LOOPBACK_ENABLE bit in the PORT_LINK_CTRL_OFF register.

ASPM must be disabled prior to enabling LOOPBACK mode.


Note
ASPM is disabled by programming the PCIE_CAP_ACTIVE_LINK_PM_SUPPORT field of the
LINK_CAPABILITIES_REG register to 2'b00.

C.2.2 In PIPE Loopback


The loopback mode allows the link to initialize, as if it is in L0. After entering loopback mode, the controller
initializes flow control for VC0. When this completes, you can then send traffic (TLPs) on the cores
XALI0/1/2 client interfaces. As the traffic is looped back, the port must complete its own requests. When in
loopback mode, the port initializes flow control against itself as every TLP and DLLP sent is also received.
TLPs which are not received correctly as a result of link errors are subject to replay as if the link is in L0

1. This feature is automatically enabled. The CX_PIPE_LOOPBACK_EN hidden configuration parameter is set by default to 1.

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Exiting Local Loopback PCI Express SW Controller Databook

state. Transmitted TLPs are subject to credit checks as if the link is fully operational. Received TLPs are
subject to error checking and filter checks as it the link is operating in L0 state.

Message Considerations
When the port is an upstream port (USP), you must not enable error message generation. When an error
occurs on the PCIe link, and you have enabled error message generation, the USP generates an Error
message. Traffic generated by the port is looped back to itself, and as an USP does not expect to receive
messages, it generates an additional message, and so on.
A DSP must automatically send a Set_Slot_Power_Limit message when it enters L0, so the message is sent
and is received by the port itself. A DSP does not expect to receive a Set_Slot_Power_Limit message.
Therefore, it is detected as an invalid message, and the unsupported request detected bit in Device Status
register is be set.
When the port is a downstream port (DSP), then internally generated messages are mixed together with
traffic generation by your application on the XALI0/1/2 interfaces .

Enumeration and BAR Setup


You must configure the BARs (USP), memory/IO ranges (DSP), set the memory space enable and bus
master enable, so that the receive filter accepts TLPs. Alternatively, you can turn off the filter rules to allow
TLPs that would normally be dropped to be accepted (see “Advanced Information: Advanced Error
Handling for Received TLPs” on page 981 and “Advanced Information: Advanced Filtering and Routing of
TLPs” on page 954).
In loopback mode, you can initialize the BARs by writing from the local CPU through the DBI.
Gen3 Operation
You must set the Gen3 Equalization Disable bit in the Gen3 Control Register GEN3_RELATED_OFF, as the
PHY has no role in local loopback.

C.2.3 Exiting Local Loopback


To exit loopback mode:
■ Clear the PIPE_LOOPBACK bit in the PIPE_LOOPBACK_CONTROL_OFF register.
■ Clear the LOOPBACK_ENABLE bit in the PORT_LINK_CTRL_OFF register.

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PCI Express SW Controller Databook Local Analog Loopback

C.3 Local Analog Loopback


This section discusses the operation of the controller when entering, and exiting analog local loopback. It
also discusses the behavior of the controller when in local loopback. Entering loopback mode, exiting
loopback mode, and looping the TX data back to its RX are the same as “Remote Digital Loopback” on page
936 but without the remote loopback slave (no link partner).

Figure C-2 Components Involved in Analog Local Loopback Without a Link Partner
Loopback Master
Controller Core
TLP

your generated traffic


PCS 0
PHY
1
TS1

PIPE

LOOP B A CK_E NA B LE= 1 mac_phy_txdetectrx_loopback=0


LTSSM

PORT _LINK_CTRL_OFF
register

TLP
PCS PHY
your looped -back traffic

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Remote Digital Loopback PCI Express SW Controller Databook

C.4 Remote Digital Loopback


This section discusses the operation of the controller when entering, and exiting remote digital loopback. It
also discusses the behavior of the controller when in remote digital loopback.

Figure C-3 Components Involved in Remote Digital Loopback with a Link Partner
Loopback MASTER
Controller Core
Loopback SLAVE
TLP
Controller Core
your generated traffic
PCS 0
PHY PHY PCS
1
TS1

PIPE

PIPE

TS1
TLP
LOOP B A CK_E NA B LE= 1 mac_phy_txdetectrx_loopback=0
LTSSM

mac_phy_txdetectrx_loopback=1
LTSSM
PORT _LINK_CTRL_OFF
register Loopback Enable=0

TLP 1

PCS PHY PHY


your looped -back traffic
0 PCS

C.4.1 Entering Remote Digital Loopback


A loopback master is the component requesting loopback and transmitting the data, for looping back by the
slave, as in Figure C-3. A loopback slave is the component looping back the data. The behavior of a
[loopback] master is not defined by the PCI Express Base Specification, Revision 4.0, Version 1.0. Only the
protocol for negotiating loopback in a slave device is defined.
To direct the master to enter loopback mode, you must set the LOOPBACK_ENABLE bit in the
PORT_LINK_CTRL_OFF register. You do not have to do anything to enable loopback mode in a slave. It
enters loopback mode in response to the master initiating loopback mode.
Loopback uses bit 2 (loopback) in the Training Control field which is sent within the TS1 and TS2 Ordered
Sets (OS). The slave device enters loopback whenever two consecutive TS1 OS are received with the
loopback bit set. The master device enters loopback when it receives back from the slave, the TS1 OS that it
sent. For more information, see 4.2.5.10. “Loopback” and 4.2.6.10. “Loopback” sections of the PCI Express
Base Specification, Revision 4.0, Version 1.0. When the slave LTSSM enters loopback, it asserts the
mac_phy_txdetectrx_loopback PIPE input of the slave PHY. This activates the slave loopback multiplexer
in Figure C-3.

C.4.2 In Remote Loopback


The loopback master mode allows the link to initialize, as if it is in L0. After entering loopback mode, the
controller initializes flow control for VC0. When this completes, you can then send traffic (TLPs) on the
cores XALI0/1/2 client interfaces. As the traffic is looped back by the link partner, the master must
complete its own requests. When in loopback mode, the master initializes flow control against itself as every
TLP and DLLP sent is also received. TLPs which are not received correctly as a result of link errors are
subject to replay as if the link is in L0 state. Transmitted TLPs are subject to credit checks as if the link is fully
operational. Received TLPs are subject to error checking and filter checks as it the link is operating in L0
state.

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PCI Express SW Controller Databook Exiting Remote Loopback

Message Considerations
When the loopback master is an upstream port (USP), you must not enable error message generation. When
an error occurs on the PCIe link, and you have enabled Error message generation, the USP generates an
Error message. Traffic generated by the master is looped back to itself by the slave, and as an USP does not
expect to receive messages, it generates an additional message, and so on.
A DSP must automatically send a Set_Slot_Power_Limit message when it enters L0, so the message is sent
and is received by the master itself. A DSP does not expect to receive a Set_Slot_Power_Limit message.
Therefore, it is detected as an invalid message, and the unsupported request detected bit in Device Status
register is be set.
When the loopback master is a downstream port (DSP), then internally generated messages are mixed
together with traffic generation by your application on the XALI0/1/2 interfaces .

Enumeration and BAR Setup


You must configure the BARs (USP), memory/IO ranges (DSP), set the memory space enable and bus
master enable, so that the receive filter accepts TLPs. Alternatively, you can turn off the filter rules to allow
TLPs that would normally be dropped to be accepted (see “Advanced Information: Advanced Error
Handling for Received TLPs” on page 981 and “Advanced Information: Advanced Filtering and Routing of
TLPs” on page 954).
Your RC link partner can perform enumeration and BAR setup in L0, before you enable loopback mode.
Alternatively, in loopback mode, you can initialize the BARs by writing from the local CPU through the
DBI. Any traffic generated by a slave never reaches the PCIe link. Therefore, if the RC is a slave, it cannot do
enumeration or BAR setup in loopback mode.

Gen3 Consideration
According to section 4.2.3. Link Equalization Procedure for 8.0 GT/s Data Rate of the PCI Express Base
Specification, Revision 4.0, Version 1.0, the loopback master is responsible for communicating the Transmitter
and receiver settings it wants the slave to use. It does this through the:
■ EQ TS1 Ordered Sets it transmits in the 2.5 GT/s or 5.0 GT/s data rate
■ Preset or Coefficient TS1 Ordered Sets it transmits in the 8.0 GT/s data rate
The Synopsys implementation of loopback does not support the changing of Preset and Coefficient values
in the Loopback.entry LTSSM state.

C.4.3 Exiting Remote Loopback


To cause the [loopback] master to exit loopback mode, you must clear the LOOPBACK_ENABLE bit in the
PORT_LINK_CTRL_OFF register. You do not have to explicitly direct the slave to exit loopback mode. It exits
loopback when it detects four consecutive EIOSs, which the master transmits after exiting loopback mode. If
the current link speed is 2.5 GT/s, and an EIOS is received, or Electrical Idle is detected or inferred on any
Lane, then the slave also exits loopback mode.

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Advanced Information: Lane Deskew PCI Express SW Controller Databook

D
Advanced Information: Lane Deskew

This appendix discusses lane-lane deskew by the RX path of the controller. It is a reference for calculating
the maximum theoretical deskew buffer depth; which you can set to a different value based on your PHY
and system requirements. You can disable the deskewing mechanism by setting the CX_DESKEW_DISABLE
configuration parameter. This could be used, for example, when connecting to a multi-lane PHY that
implements lane-lane deskewing.

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PCI Express SW Controller Databook Conventional PCIe Deskew Requirements

D.1 Conventional PCIe Deskew Requirements

■ In releases prior to 4.50a, the deskew buffer depth is calculated from CX_MAX-
Note _SKEW_NUM which has two options only (“Shallow” and “Deep”). Therefore, it is not
possible to select a deeper depth if required.
■ In 4.50a, the CX_MAX_SKEW_NUM parameter is not visible in the coreConsultant GUI.
For existing configurations, you can continue to set it in your configuration batch file. For
new configurations, you can configure lane deskew capabilities using the new
CX_DESKEW_DEPTH_CPCIE parameter.
■ From 4.60a onwards:
❑ The default of the CX_DESKEW_DEPTH_CPCIE parameter is calculated based on
the E12/C8/C10 Synopsys PHY.
❑ The coreConsultant GUI displays (as a read-only parameter) the maximum allowable
PHY skew based on the value of CX_DESKEW_DEPTH_CPCIE.
❑ It is expected that you confirm this PHY skew value with your PHY vendor and
adjust CX_DESKEW_DEPTH_CPCIE accordingly.
❑ The coreConsultant GUI also displays (as read-only parameters) the individual system
skew components used in the total skew calculation.

A multi-lane controller configuration removes lane-lane skew using a deskew buffer. The maximum
possible amount of PIPE lane-lane skew (as measured at the RX deskew buffer in the controller) is
comprised of the following four components:
■ Wire Skew: This is the maximum skew (LRX-SKEW) allowed by PCIe specification at the PHY RX I/O
pads. Added by the channel (physical link) or repeater delay differences.
■ PCS Skew: Assumes that the PHY skew (measured at PHY RX I/O and PIPE Rx interfaces) is
comprised of at least the following components:
❑ SKP symbol insertion/deletion
❑ Gen3/4 sync header removal skew
The sync header removal skew for Gen3/4 configuration accounts for the difference in symbol lock
timing between the lanes. phy_mac_rxdatavalid de-assertion timing can vary between the
lanes.
❑ PHY implementation-specific CDC skew
❑ PHY implementation-specific de-serializer skew
❑ PHY implementation-specific symbol aligner skew
■ MAC Component: 2*core_clk cycles for data processing. For some configurations, an additional
core_clk period is added.
■ Safety Margin: One core_clk period.

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Conventional PCIe Deskew Requirements PCI Express SW Controller Databook

Table D-1 Reference Value of Skew Components

Skew Components

Wire Skew MAC Component Safety Margin


Speed (ns) PHY Skew (core_clk cycles) (core_clk cycles)

Gen1 20 2 or 3a

Gen2 8 2 or 3
Consult your PHY vendor
Gen3 6 2 1

Gen4 5 2

Gen5 5 2

a. For on Gen1/2 2s/4s configuration an additional core_clk cycle is added because the COM symbol is not always on byte0.

Figure D-1 CX_DESKEW_DEPTH_CPCIE Parameter Setting in coreConsultant

CX_DESKEW_DEPTH_CPCIE
1

2 Wire Skew

3 PHY Skew

4 Safety Margin

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PCI Express SW Controller Databook Advanced Information: Clock and Data Crossing (CDC)

E
Advanced Information: Clock and Data

Crossing (CDC)

This appendix discusses aspects of clock and data crossing. The following topics are discussed:
■ “CDC Overview”
■ “Port Clocking and Input Synchonizers” on page 943
■ “CDC Reports” on page 944

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CDC Overview PCI Express SW Controller Databook

E.1 CDC Overview


The PCIe controller (in C-PCIe mode ) has three clock domains:
■ core_clk / radm_clk_g
■ aux_clk
■ pipe_clk
For more information on clock generation, see “Clock Requirements” on page 53
During normal operation, core_clk/radm_clk_g and aux_clk must be completely synchronous. During
low-power operation, when the controller is operating on aux_clk only, the frequency of aux_clk can be
lowered to achieve additional power reduction. Therefore, there is no CDC synchronization logic
implemented between the aux_clk and core_clk/radm_clk_g domains.
The core_clk/radm_clk_g and pipe_clk clocks must be quasi-synchronous, that is, having the same
phase, but not necessarily having the same frequency. Therefore, there is no CDC synchronization logic
implemented between the pipe_clk and core_clk/radm_clk_g domains.

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PCI Express SW Controller Databook Port Clocking and Input Synchonizers

E.2 Port Clocking and Input Synchonizers


The inputs in Table E-1 have metastability synchronizers.

Table E-1 Inputs With Synchronizers.

Synchronizing
Input Name Clocka Note

phy_clk_req_n aux_clk

phy_mac_pclkack_n aux_clk

clkreq_in_n aux_clk

perst_n aux_clk

ack_en_vmain aux_clk

phy_mac_rxelecidle aux_clk

phy_mac_phystatus aux_clk Also clocked normally on core_clk_ug,core_clk, pipe_clk

a. These signals are syncronized using aux_clk and can be driven/supplied asynchronously to the controller in certain
low-power modes. The presence of aux_clk in the SynchronousTo attribute for these signals identify the syncronizing
clock.

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CDC Reports PCI Express SW Controller Databook

E.3 CDC Reports


Detailed CDC reports and Spyglass waiver information are available at
http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/5.40a/doc/PCIe_CDC.pdf
You can inspect the Spyglass control and waiver files at the location specified in the User Guide.
The Spyglass CDC report confirms that all CDC paths in the design are synchronized between clock
domains using standard CDC library parts, with the exception of the paths that are waived. These paths do
not need synchronization for the reasons outlined in the CDC reports. The reports refer to the Common
multiplexer scheme which is explained in Figure E-1. To create a CDC path report, see the “Running STA
using PrimeTime” section in the “Configuring the Controller” chapter of the User Guide.

Figure E-1 Common Multiplexer (Recirculation) Synchronization Scheme


clock boundary

0
data[1] 1

Logic
0
data[0] 1

data_enable
src_clk
dest_clk

The controller uses a library of design-specific CDC parts that are mapped to the standard DesignWare
library parts in http://www.synopsys.com/dw/buildingblock.php as follows:

Table E-2 PCIe to DesignWare Mapping

PCIe Part Name DesignWare Library Part Name

DWC_pcie_bcm01.v DW_minmax

DWC_pcie_bcm05.v DW_fifoctl_if

DWC_pcie_bcm06.v DW_fifoctl_s1_df

DWC_pcie_bcm07.v DW_fifoctl_s2_sf

DWC_pcie_bcm21.va DW_sync

DWC_pcie_bcm22.v DW_pulse_sync

DWC_pcie_bcm23.v DW_pulseack_sync

DWC_pcie_bcm25.v DW_data_sync (x2 DW_sync plus flipflop)

DWC_pcie_bcm41.v DW_sync

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PCI Express SW Controller Databook CDC Reports

PCIe Part Name DesignWare Library Part Name

DWC_pcie_bcm43.v DW_8b10b_dec

DWC_pcie_bcm44.v DW_8b10b_enc

DWC_pcie_bcm46_a.v DW_ecc

DWC_pcie_bcm46_b.v DW_ecc

DWC_pcie_bcm46_c.v DW_ecc

DWC_pcie_bcm46_d.v DW_ecc

DWC_pcie_bcm46_e.v DW_ecc

DWC_pcie_bcm48.v DW_crc_p

DWC_pcie_bcm53.v DW_arb_2t

DWC_pcie_bcm55.v DW_arb_rr

DWC_pcie_bcm57.v DW_ram_r_w_s_dff

DWC_pcie_bcm60.v DW_ram_rw_a_ff

DWC_pcie_bcm62.v DW_ram__2r_w_a_ff

DWC_pcie_bcm64.v DW_fifo_s1_df

DWC_pcie_bcm65.v DW_fifo_s1_sf

DWC_pcie_bcmmod48.v DW_crc_p (modified)

DWC_pcie_bcmmod57.v DW_ram_r_w_s_dff

DWC_pcie_bcmmod65.v DW_fifo_s1_sf

a. It is recommend to replace BCM21 with your custom synchronizer.

Metastability Simulation
The CDC synchronizer parts have a behavioral metastability model to simulate metastability mis-sampling
across the clock domain. By passing in the DW_MODEL_MISSAMPLES parameter, the part randomly
mis-samples data transitions across the clock domain, thereby stressing the CDC design. This stressing
highlights areas of the design prone to error caused by divergence and re-convergence as the CDC signals is
skewed by the mis-sampling algorithm.

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Advanced Information: Reset Domain Crossing (RDC) PCI Express SW Controller Databook

F
Advanced Information: Reset Domain

Crossing (RDC)

The PCIe controller has a number of primary inputs which are asynchronous resets. Some of these resets are
asserted independent of each other, that is, a particular flip-flop can be reset while a flip-flop in its fan-out
cone is not being reset. This scenario can lead to metastability in the destination flip-flop due to the fact that
the start point is reset asynchronously. This issue can be identified by performing reset domain crossing
analysis on the design.
Table F-1 describes the conditions under which the PCIe controller asynchronous resets are asserted.

Table F-1 PCIe Controller Reset Conditions

Fundamental L1.2 Power Hot Reset


Reset Name Cold Reset Reset Gating (Link-down)

pwr_rst_n Asserted

sticky_rst_n Asserted Asserted Asserted

non_sticky_rst_n Asserted Asserted Asserted Asserted

core_rst_n Asserted Asserted Asserted Asserted

pipe_rst_n Asserted Asserted Asserted Asserted

phy_rst_n Asserted Asserted Asserted

phy_reg_rst_n Asserted Asserted Asserted

ret_sticky_rst_n Asserted Asserted

ret_non_sticky_rst_n Asserted Asserted Asserted

ret_core_rst_n Asserted Asserted Asserted

The PCIe controller has the following reset conditions:

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PCI Express SW Controller Databook Advanced Information: Reset Domain Crossing (RDC)

■ Cold Reset: It is a full power on reset cycle during which all resets are asserted. Hence there are no
reset domain crossing issues.
■ Fundamental Reset: It is similar to a Cold Reset except that the pwr_rst_n is not asserted. Reset
domain crossing issues are avoided in fundamental reset, by asserting the controller’s resets synchro-
nous to aux_clk, since all registers reset by pwr_rst_n are clocking by aux_clk.
■ Hot Reset: It may give reset domain crossing issues. The pwr_rst_n, sticky_rst_n,
phy_reg_rst_n, and ret_sticky_rst_n inputs are not asserted, since there are potential reset
domain crossing issues due to the active resets (For example, core_rst_n to pwr_rst_n) during hot
reset.
In the PCIe controller clock-gating during reset assertion is used to ensure that there are no clocks running
during the link down reset event.
■ All controller clocks are gated off in the clock and reset block, when the controller indicates a pending
hot reset, by asserting link_req_rst_not.
■ The resets are only asserted after the clocks have been gated off.
■ The resets are de-asserted after the clocks have been enabled.

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Advanced Information: VC-Based Arbitration PCI Express SW Controller Databook

G
Advanced Information: VC-Based Arbitration

This appendix discusses VC-Based Arbitration. For an overview of TLP transmit arbitration mechanisms see
“Transmit TLP Arbitration” on page 87. The following topics are discussed:

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PCI Express SW Controller Databook VC-Based Arbitration Overview

G.1 VC-Based Arbitration Overview


All transmit client interfaces XALI0/1/2 are served using one of the three arbitration schemes when credit
is available, regardless of the type of transaction. You can change the arbitration scheme using the
CX_XADM_ARB_MODE configuration parameter when CX_NVC >1.

■ 0: VC Based. Provides VC based programmable weighted round robin arbitration (WRR) using two
different arbitration methods for the two groups of VCs:
❑ Strict Priority for the High-Priority VC (HPVC) group
❑ RR or WRR for the Low-Priority VC (LPVC) group
Between the two groups of VCs, arbitration is as follows:
■ The HPVC group is always the highest priority. Within the HPVC group, priority order is by
VC id. The highest VC id has the highest priority. Ties within the HPVC are resolved by
client-based Strict Priority arbitration; XALI0 has lowest, XALI1 higher, and XALI2 (if imple-
mented) highest priority.
■ The LPVC group is of lower priority than the HPVC group. Within the LPVC group, priority is
determined by RR or WRR arbitration as described later. Ties within the LPVC group are
resolved by client-based RR arbitration.
Note: This scheme operates in a manner similar to that described in Section 7.11 of the PCI
Express Base Specification, Revision 4.0, Version 1.0, but provides a different software interface.
This scheme does not have a VC arbitration table, the weights are programmed through port
logic registers.
■ 1: Round Robin (RR). Provides round robin arbitration between the three transmit clients. This is the
default method.
■ 2: Strict Priority. Provides strict priority between the three transmit clients. XALI0 is lowest, XALI1 is
higher, XALI2 (if implemented) is highest.
The value of the Low Priority Extended VC Count field of “Port VC Capability Register 1” determines the
number of VCs (in addition to VC0) that are in the LPVC group. All other VCs are in the HPVC group.
Between the two groups of VCs, arbitration is as follows:
1. The HPVC group is always the highest priority. Within the HPVC group, priority order is by VC id.
The highest VC id has the highest priority.
2. The LPVC group is of lower priority than the HPVC group. Within the LPVC group, priority is deter-
mined by round robin or WRR arbitration as described in the following sections. Ties within the LPVC
group are resolved by client-based round robin arbitration.

Setting Up VC-Based WRR


The WRR arbitration scheme uses the programmed values for each LPVCs weight (programmed by VC id)
to determine the percentage of the time that each VC has the highest priority within the LPVC group. The
factors that influence WRR arbitration are:
■ Number of VCs in the LPVC group, as programmed in the Low Priority Extended VC Count field of
port VC Capability Register 1.
■ The number of phases in the selected WRR arbitration scheme, as determined by:
❑ The VC Arbitration Capability field in port VC Capability Register 2 (indicates the schemes) that
the controller is configured to support: 16, 32, 64, or 128-phase).

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VC-Based Arbitration Overview PCI Express SW Controller Databook

❑ The VC Arbitration Select field in port VC Control Register (selects the arbitration scheme).
■ The weight assigned to each VC in the LPVC group, as programmed in VC Transmit Arbitration
Register 1 and VC Transmit Arbitration Register 2. The sum of all the programmed weight values must
equal the number of phases in the selected WRR arbitration scheme. For example, for 64-phase arbi-
tration, the total of the weights assigned to all the VCs in the LPVC group must be 64.
VC-based round robin arbitration is a special case of VC-based WRR in which the weights are equal for all
VCs in the LPVC group.

VC Transmit Arbitration Registers 1 and 2


VC Transmit Arbitration Registers 1 and 2 (VC_TX_ARBI_OFF_1 and VC_TX_ARBI_OFF_2) specify the
weights assigned to VC0VC7 to be used for WRR transmit arbitration for VCs in the LPVC group. The
following rules and restrictions apply regarding the values programmed in VC Transmit Arbitration
Registers 1 and 2:
■ There are eight bits allocated for each weight value.
■ No weight value for a VC in the LPVC group can be less than 1.
■ No weight value can be greater than the number of phases in the selected arbitration scheme.
■ The sum of the weights assigned to all VCs in the LPVC group must equal the number of phases in the
selected arbitration scheme. For example, if 64-phase WRR arbitration is selected, the total of all WRR
Weight values for all VCs in the LPVC group must equal 64.
Each of the VC numbers listed in the register description is a VC id, not the VC structure number.
Read/write access to VC Transmit Arbitration Registers 1 and 2 depends on the value of
CX_LPVC_WRR_WEIGHT_WRITABLE:

■ 1: these registers are RWS.


■ 0: these registers are hardwired to a default set by configuration parameters.

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PCI Express SW Controller Databook VC-Based WRR Arbitration Programming Examples

G.2 VC-Based WRR Arbitration Programming Examples


The section provides examples for Setting up VC-Based Weighted Round-Robin (WRR) Arbitration.

G.2.1 Setting Up All VCs in the LPVC Group


The following example shows how to set up the controller to meet the following requirements:
■ Support four VCs
■ All four VCs are in the LPVC group
■ VC3 has highest priority ~50%of the time
■ VC2 has highest priority ~30%of the time
■ VC1 has highest priority ~10-15%of the time
■ VC0 has highest priority at least 5%of the time
This can be achieved with 32-phase WRR arbitration with the following weights assigned to VC03:
■ VC3 weight =16; priority allocation is 16/32 =50%
■ VC2 weight =10; priority allocation is 10/32 =31.3%
■ VC1 weight =4; priority allocation is 4/32 =12.5%
■ VC0 weight =32-(16+10+4) =2; priority allocation is 2/32 =6.25%
To implement this scheme, set up the controller as follows:
1. Select four VCs during hardware configuration.
2. Choose VC-based arbitration during hardware configuration.
3. Set the Low Priority Extended VC Count field of port VC Capability Register 1 to 3 (3 LPVCs in addition
to VC0).
4. Set the VC Arbitration Capability field in port VC Capability Register 2 to 0x02 (32-phase arbitration
supported).
5. Set the following weight values in VC Transmit Arbitration Register 1:
■ WRR Weight for VC3 =16
■ WRR Weight for VC2 =10
■ WRR Weight for VC1 =4
■ WRR Weight for VC0 =2
6. Set the VC Arbitration Select field in the port VC Control Register to 010b (32-phase arbitration
selected).

The register programming in steps 3-5 is a combination of default register value selection
Note
during hardware configuration and (optionally) update of the register values at runtime through
the DBI. Setting the VC Arbitration Select field (RW) in step 6 is a function of configuration
software.

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Setting Up 4 VCs in the LPVC Group, 2 VCs in HPVC Group PCI Express SW Controller Databook

G.2.2 Setting Up 4 VCs in the LPVC Group, 2 VCs in HPVC Group


The following example shows how to set up the controller to meet the following requirements:
■ Support 6 VCs
■ 4 VCs are in the LPVC group
■ 2 VCs are in the HPVC group
■ Round robin arbitration is to be used for the 4 VCs in the LPVC group
You can achieve round robin arbitration for the 4 VCs in the LPVC group by assigning them equal weights.
As there are 4 VCs, equal weights can be achieved with any of the following setups:
■ 16-phase arbitration; the weight of each VC is 4
■ 32-phase arbitration; the weight of each VC is 8
■ 64-phase arbitration; the weight of each VC is 16
■ 128-phase arbitration; the weight of each VC is 32
To implement this scheme, using 32-phase arbitration as an example, set up the controller as follows:
1. Select 6 VCs during hardware configuration.
2. Choose VC-based arbitration during hardware configuration.
3. Set the Low Priority Extended VC Count field of port VC Capability Register 1 to 3 (3 LPVCs in addition
to VC0).
4. Set the VC Arbitration Capability field in port VC Capability Register 2 to 0x02 (32-phase arbitration
supported).
5. Set the following weight values in VC Transmit Arbitration Register 1:
■ WRR Weight for VC3 =8
■ WRR Weight for VC2 =8
■ WRR Weight for VC1 =8
■ WRR Weight for VC0 =8
6. Set the VC Arbitration Select field in the port VC Control Register to 010b (32-phase arbitration
selected).

G.2.3 Setting Up 5 VCs in the LPVC Group, 2 VCs in HPVC Group


The following example shows how to set up the controller to meet the following requirements:
■ Support 7 VCs
■ 5 VCs are in the LPVC group
■ 2 VCs are in the HPVC group
■ Round robin arbitration is to be used for the 5 VCs in the LPVC group
You can achieve round robin arbitration for the 5 VCs in the LPVC group by assigning them equal weights.
However, because there are 5 VCs, greater granularity and closer to equal weights can be achieved with
more arbitration phases. For example, with 32-phase arbitration, equal weights would be 6.4, which could
be approximated with the following integer weight values for the 5 VCs:
■ 6, 6, 6, 6, 8 (18.75% for 4 VCs; 25% for the remaining VC)

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PCI Express SW Controller Databook Setting Up 5 VCs in the LPVC Group, 2 VCs in HPVC Group

■ 7, 7, 7, 7, 4 (21.88% for 4 VCs; 12.5% for the remaining VC)


■ 7, 7, 6, 6, 6 (21.88% for 2 VCs; 18.75% for 3 VCs)
64-phase arbitration provides increased granularity. The required equal weights of 12.8 can be more closely
achieved with weight assignments of 13, 13, 13, 13, and 12:
■ VC4 weight =13; priority allocation is 13/64 =20.3%
■ VC3 weight =13; priority allocation is 13/64 =20.3%
■ VC2 weight =13; priority allocation is 13/64 =20.3%
■ VC1 weight =13; priority allocation is 13/64 =20.3%
■ VC0 weight =64 (13 + 13 + 13 + 13) =12; priority allocation is 12/64 =18.75%
To implement the this scheme, set up the controller as follows:
1. Select 7 VCs during hardware configuration.
2. Choose VC-based arbitration during hardware configuration.
3. Set the Low Priority Extended VC Count field of port VC Capability Register 1 to 4 (4 LPVCs in addition
to VC0).
4. Set the VC Arbitration Capability field in port VC Capability Register 2 to 0x04 (64-phase arbitration
supported).
5. Set the following weight values in VC Transmit Arbitration Register 1 and VC Transmit Arbitration
Register 2:
■ WRR Weight for VC4 =13
■ WRR Weight for VC3 =13
■ WRR Weight for VC2 =13
■ WRR Weight for VC1 =13
■ WRR Weight for VC0 =12
6. Set the VC Arbitration Select field in the port VC Control Register to 100b (64-phase arbitration
selected).

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Advanced Information: Advanced Filtering and Routing of TLPs PCI Express SW Controller Databook

H
Advanced Information: Advanced Filtering

and Routing of TLPs

This appendix discusses advanced features and operation associated with “Receive Filtering” on page 94.
You should first read to familiarize yourself with basic information on the filtering and routing of received
TLPs. The following topics are discussed:
■ “Filtering Rules” on page 955
■ “Filtering Algorithm” on page 958
■ “Upstream Port Routing Overview” on page 960
■ “Request TLP Routing Rules” on page 963
■ “Processing Illegal CFG TLPs and CFG1-CFG0 Conversion in Each PCI Express Port Type” on page
966

■ For more information on advanced routing of TLPs with errors, see “Advanced Information:
Note Advanced Error Handling for Received TLPs” on page 981.

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PCI Express SW Controller Databook Filtering Rules

H.1 Filtering Rules


These tables describe the filtering rules (based on the PCIe Specification), and the results of the controller’s
filter. When a received TLP passes all of the filter rules, then it is considered to have no errors, and is routed
to the destination that is configured. For more information on routing, see “Receive Routing” on page 95.
For more information on what happens to malformed TLPs, see “Error Detection for Received TLPs” on
page 97.

Notation of filter results:


■ UR: Unsupported Request “CPL Status”1
■ CA: Completer Abort “CPL Status”1
■ CRS: Configuration Request Retry Status “CPL Status1”
■ SU: Successful Completion “CPL Status”1
■ UC: Unexpected CPL
■ MLF: Malformed
■ MA: (Received) Master Abort set in “PCI-compatible Status Register”
■ TA: (Received) Target Abort set in “PCI-compatible Status Register”
■ <blank>: Filtering rule does not apply to TLP type

Table H-1 Result of Filtering Rules Applied to Request TLPs

TLP Type

Filtering Rule MEM & I/O CFG0 CFG1 MSG

PowerState is not in D0. UR SU UR SU

Downstream Port:
Address does not meet any of the following conditions:
1. MEM: Outside of the memory range AND prefetchable
memory range as determined by the corresponding Base and
Limit fields in the Type-1 header.
UR
2. I/O: Outside of the I/O range as determined by the I/O Base
and Limit fields in the Type-1 header.
3. The filter mask CX_FLT_MASK_UR_OUTSIDE_BAR bit is set,
which treats out-of-bar TLPs as supported requests and
indicates a special application requirement

1. For non-posted TLPs, this filter result also determines the status of the completion that the controller sends back to the
requester.

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Filtering Rules PCI Express SW Controller Databook

TLP Type

Filtering Rule MEM & I/O CFG0 CFG1 MSG

Upstream Port:
Address does not meet any of the following conditions:
1. Within any configured memory BAR.
2. MEM: Inside of the memory range OR prefetchable memory
range as determined by the corresponding Base and Limit fields
in the Type-1 header. UR
3. I/O: Inside of the I/O range as determined by the I/O Base and
Limit fields in the Type-1 header.
4. The filter mask CX_FLT_MASK_UR_OUTSIDE_BAR bit is set,
which treats out-of-bar TLPs as supported requests and
indicates a special application requirement

TLP header poison bit is set and the filter mask


CX_FLT_MASK_UR_POIS bit is not set for the TLPs that are UR UR SU UR
targeted for local resources, and not for forwarding.

TLPs that is targeted locally for TRGT0 and TLP DW length is


CAa CA SU
greater than one (message is never be directed to TRGT0).

The function number of a completer ID within a CFG type0


request of upstream port does not match the function number of
UR SU
the receiver device and the filter mask
CX_FLT_MASK_UR_FUNC_MISMATCH bit is not set.

Application requests the controller filter to return CRS to CFG


type0 request by asserting signal app_req_retry_en at upstream CRS SU
port.

Not a valid message on the upstream port or downstream port. UR/MLF

Vendor MSG Type0 with filter mask


UR
CX_FLT_MASK_VENMSG0_DROP bit not set.

TLP is targeted for local resources, and not for forwarding, and
CA CA CA CA
ECRC error is detected.

a. SU for MEM if CX_LBC_NW >1 and TRGT0 is routing to ELBI.

A complete list of the filtering checks can be referenced in the descriptions of Symbol Timer Register and
Filter Mask 1 register (SYMBOL_TIMER_FILTER_1_OFF) and Filter Mask 2 register (FILTER_MASK_2_OFF).
Completions are not filtered inside the SW RADM filter. It is assumed that the SW does not generate a
request locally.

Filtering Rules Not Defined in PCIe Specification


When a zero-byte request TLP is received, also called “flush” command, the controller can drop1 the
zero-byte request. This is designed to support some applications that can not process a zero-byte request.

1. Service internally but not passing to your application

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PCI Express SW Controller Databook Filtering Rules

Applications can dynamically program a bit in the filter mask CX_FLT_MASK_HANDLE_FLUSH bit to turn
on/off this rule. If the controller is programmed to handle the flush, it is the completer’s task to return CPL
status.

When the controller receives a four DWORD TLP with the LSB of the format field set to 1 and
Note the upper 32 bits set to 0x0, then it processes the TLP as a three DWORD TLP.

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Filtering Algorithm PCI Express SW Controller Databook

H.2 Filtering Algorithm


The following algorithm is followed for RX completion filtering.
1. Relevant fields (BCM, Requester ID, Length, Tag, Byte Count, Low Address, TC, Attr) are extracted
from the incoming completion.
2. Completion Length field in DW units is converted to byte units considering the low address offset.
byte_offset = 4 - Lower Address[1:0]
CPL Length(bytes) = (Length(DW) - |byte_offset), byte_offset
Where, Lower Address and Length are fields of the incoming Completion TLP
3. Bytes pending to be received for that request are stored.
Bytes pending = Byte Count – CPL Length
Where, Byte Count is a field of the incoming Completion TLP
4. A check for the last completion is performed. A completion is the last completion,
■ If the status of the received completion is different than successful, or
■ If the number of bytes received in the completion are equal or greater than the Byte Count field
received in that completion
5. Completion filter checks performed (C1 – C9 in Figure H-1).
■ C1: Is there a current outstanding request for that Tag?
■ C2: Does the completion have ecrc error?
■ C3: Does the completion Requester ID match the current outstanding requester ID for that TAG?
■ C4: Does bus and device number of the completion requester ID match the current outstanding
requester ID for that TAG?
■ C5: Does the current outstanding attr for that TAG match the completion attr field?
■ C6: Does the current outstanding tc for that TAG match the completion tc field?
■ C7: Is the completion tag inside the pool of possible tags?
■ C8: Does the current outstanding byte_cnt pending for that TAG match the completion byte_cnt
field?
■ C9: Does the current outstanding next low_addr for that TAG match the completion low_addr
field?
6. Output based on the checks is provided (O1 – O6 in Figure H-1)
■ O1: unexpected_cpl_err
■ O2: cpl_mlf_err
■ O3: cpl_abort
■ O4: cpl_ca_err
■ O5: cpl_ur_err
■ O6: update_lut_content
Figure H-1 describes the RX completion filtering algorithm used by the controller.

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PCI Express SW Controller Databook Filtering Algorithm

Figure H-1 RX Completion Filtering Algorithm

Completion Filter Outputs

!valid_at_lut_addr ||
!func_match ||
!reqid_match ||
tag_err ||
!byte_cnt_match || FALSE
!low_addr_match

TRUE

Completion Filter Checks LUT[TAG].memrd_req &&


- !cpl_ecrc_err

C1 C2 C3
TRUE
Does
the completion
Is there a current outstanding
NO
Does the completion have
NO Requester ID match the YES O1 unexpected_cpl_err = 1 unexpected_cpl_err = 0
current outstanding
request for that TAG? ecrc error?
Requester ID for
that TAG?

YES NO (!byte_cnt_match ||
YES
!low_addr_match) &&
!LUT[TAG].memrd_req
||!attr_match || !tc_match
||!LUT[TAG].cfg_req && FALSE
valid_at_lut_addr = 1 valid_at_lut_addr = 0
status_crs

CX_FLT_MASK_CPL_ECRC NO CX_FLT_MASK_CPL_FUNC YES


_DISCARD=0 _MATCH=1

YES NO TRUE

cpl_ecrc_err = 1 cpl_ecrc_err = 0 func_match = 0 func_match = 1


!cpl_ecrc_err &&
!unexpected_cpl_err

C4 C5 C6
Does
bus and device
number of the completion Does the TRUE
YES YES Does the current YES
Requester ID match the current outstanding attr for
outstanding tc for that TAG
current outstanding that TAG match the
Requester ID completion attr field?
match the completion tc
field?
O2 cpl_mlf_err = 0 cpl_mlf_err = 0
for that TAG?

NO NO NO

unexpected_cpl_err ||
cpl_ecrc_err ||
cpl_mlf_err FALSE

CX_FLT_MASK_CPL_REQI YES YES YES


CX_FLT_MASK_CPL_ATTR CX_FLT_MASK_CPL_TC_M
D_MATCH=1 _MATCH=1 ATCH=1
TRUE

NO NO NO O3 cpl_abort = 1 cpl_abort = 0

reqid_match = 0 reqid_match = 1 attr_match = 0 attr_match = 1 tc_match = 0 tc_match = 1

C7 C8 C9 Cpl_abort==1
FALSE

Does Does the


the current outstanding current outstanding next YES
Is the completion tag inside YES YES
byte_cnt pending for that low_addr for that TAG TRUE
the pool of possible tags? match the completion
TAG match the completion
byte_cnt field? low_addr field?
O4
cpl_ca_err = 0 cpl_ca_err = cpl_status_ca
cpl_ur_err = 0 cpl_ur_err = (cpl_status_ur ||
NO NO NO
O5 cpl_reserved_status)

YES YES CX_FLT_MASK_CPL_LEN_ YES


CX_FLT_MASK_CPL_TAGE CX_FLT_MASK_CPL_LEN_
MATCH=1 Not(mlf_TLP || DLLP_err)
RR_MATCH=0 MATCH=1
&& !cpl_abort
FALSE

NO NO NO
TRUE

tag_err = 1 tag_err = 0 byte_cnt_match = 0 byte_cnt_match = 1 low_addr_match = 0 low_addr_match = 1


O6 update_lut_content = 1 update_lut_content = 0

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Upstream Port Routing Overview PCI Express SW Controller Databook

H.3 Upstream Port Routing Overview


TLPs that the controller receives over the link in a switch application fall into the following general classes:
■ TLPs that are to be routed through the switch to another port of the switch. The controller transfers
this class of TLP to your application through the TRGT1 interface. This category includes type 1 config-
uration requests that are received by an upstream switch port and must be sent downstream.
■ Configuration requests that target the controller. The controller processes this class of TLP internally
and automatically generates the required completion.
■ Memory or I/O requests that target the switch application logic. The controller transfers this class of
request to your application through the ELBI and automatically generates the required completion.
memory and I/O requests targeted to the switch application logic are limited to single-dword
accesses.
The possible destinations of a posted or non-posted request TLP are TRGT1, TRGT0, and Discard (dropped1
or terminated). By default:
■ CFG0 requests are routed to TRGT0 and then to CDM through the LBC.
■ CFG1 requests are routed to TRGT1.
■ All of the following are routed to TRGT1:
❑ MEM requests inside of the memory range or prefetchable memory range as determined by the
corresponding Base and Limit fields in the Type-1 header.
❑ I/O requests inside of the I/O range as determined by the I/O Base and Limit fields in the Type-1
header.
❑ BAR-matched MEM (not I/O) requests.
■ MSG requests are decoded internally, signalled on the SII interface and then terminated.

BAR memory region must always be outside the memory range as determined by the
Note corresponding Base and Limit fields in the Type-1 header.

1. Service internally but not passing to your application

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Figure H-2 Default Request TLP Routing (assuming no TLPs with CA/CRS/UR error status)

controller
config CDM TRGT0 CFG0
data
LBC

TRGT1 CFG1

TRGT1 MEM/IO
C
X
Type-1 Mem
P
& IO Base L
& Limit
Checks

TRGT1 MEM

BAR Address
Check

BAR

TRGT1

SII MSG

The possible destinations of a completion TLP are TRGT1 and Discard. Completions are not filtered inside
the switch filter. This is under an assumption that the switch does not generate a request locally. If an
embedded EP is involved in a switch application, there should be some modifications based on the
requirements of your application.
For more information on switches, see “Introduction to PCIe Switches” on page 894.

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Figure H-3 Configurable Request TLP Routing (assuming SU status)

TRGT1 CFG1

controller
config CDM TRGT0 0
data D
LBC M
0 U CFG0
ELBI TRGT0 D X
(external M 1
application U
registers) X register address >
TRGT1 1
CONFIG_LIMIT_REG

TARGET_ABOVE_CONFIG_LIMIT_REG

TRGT0 0
D
M
U MEM
X
TRGT1 1
C
BAR Address X
Check P
BAR L
BAR# of matched BAR

MEM_FUNC0_BAR1_TARGET_MAP
MEM_FUNC0_BAR0_TARGET_MAP

TRGT1 MEM/IO

Type-1 Mem
& IO Base
& Limit
Checks
TRGT1

SII MSG

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PCI Express SW Controller Databook Request TLP Routing Rules

H.4 Request TLP Routing Rules


The next table shows the applicability of routing rules for request TLPs, and indicates whether the
destination is as stated by the rule when the conditions of the rule are met. For a full analysis of what error
conditions contribute toward an UR or CA status, see “Receive Filtering” on page 94 and “Routing of
Request TLPs with Errors” on page 982.

■ In many cases, the standard routing rules can be masked or ignored by setting the corre-
Hint sponding bit in the Symbol Timer and Filter Mask 1 register (SYMBOL_TIMER_FIL-
TER_1_OFF) and Filter Mask 2 register (FILTER_MASK_2_OFF).
■ For message routing see, “Routing of Received Messages” on page 999.

By default, when the controller detects an error1 in a received TLP, it normally performs the following:
■ Discards the TLP
■ Generates a completion (for non-posted requests) with the completion status set to CA or UR
■ Sets the status in the PCI-compatible Status register
■ Sets the status in the AER registers (when you enable AER)
■ Generates an error message (upstream port only)

Notation of routing results:


■ UR: Unsupported Request
■ CA: Completer Abort
■ CRS: Configuration Request Retry Status
■ SU: Successful
■ No: destination is not as specified in rule, even when conditions of rule are met
■ Yes: destination is as specified in rule, when conditions of rule are met
■ <blank>: Routing rule does not apply to TLP type

Table H-2 Routing Rules for Request TLPs (Upstream Port)

Vendor Vendor
MSG MSG Other
Routing Rule MEM CFG0 CFG1 aI/O Type0 Type1 MSG

When a request is filtered with SU status, the


no no Yes Yes no no no
destination is always the TRGT1 interface.

When a request is filtered with SU status, and is


in BAR range,
Yes no
MEM_FUNC0_BAR#_TARGET_MAP parameter
determines the destination.

1. Excluding TLPs targeted for forwarding (and not for local resources) that have ECRC errors.

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Vendor Vendor
MSG MSG Other
Routing Rule MEM CFG0 CFG1 aI/O Type0 Type1 MSG

When a request is filtered with SU status, and is


NOT in BAR range, the destination is the TRGT1 Yes
interface.

When a request is filtered with UR/CA/CRS


status, and the DEFAULT_TARGET field is 0, the
TLP is dropped. Yes Yes Yes Yes Yes Yes Yes
For NP requests, a CPL is also generated.

When a request is filtered with UR/CA/CRS


status, and the DEFAULT_TARGET field is 1, the no no Yes no Yes Yes Yes
TLP is dropped.

When a request is filtered with UR/CA/CRS


status, and the DEFAULT_TARGET field is 1, the Yes Yes no Yes no no no
destination is TRGT1 interface.

When a CFG request is filtered with SU status


and the CFG register address is >
MISC_CONTRO_1_OFF.CONFIG_LIMIT_REG, Yes no
MISC_CONTRO_1_OFF.TARGET_ABOVE_CON
FIG_LIMIT_REG determines the destination.

When a CFG request is filtered with SU status


and the CFG register address is <
Yes no
MISC_CONTRO_1_OFF.CONFIG_LIMIT_REG,
TRGT0 interface is the destination.

The TLP is dropped, when the filter mask


CX_FLT_MASK_MSG_DROP bit is not set and Yes
the non-Vendor MSG is filtered with SU status.

The TLP is dropped, when the filter mask


CX_FLT_MASK_VENMSG0_DROP bit is 0 and Yes
the VEN0 MSG is filtered with SU status.

The TLP is dropped, when the filter mask


CX_FLT_MASK_VENMSG1_DROP bit is 0 and Yes
the VEN1 MSG is filtered with SU status.

a. There is no I/O BAR matching supported.

Table H-3 Routing Rules for Request TLPs (Downstream Port)

Vendor Vendor
MSG MSG Other
a
Routing Rule MRd MWr CFG I/O Type0 Type1 MSG

When a request is filtered with SU status, TRGT1


Yes Yes no Yes
is always the destination.

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PCI Express SW Controller Databook Request TLP Routing Rules

Vendor Vendor
MSG MSG Other
a
Routing Rule MRd MWr CFG I/O Type0 Type1 MSG

When a request is filtered with UR/CA status, the


TLP is dropped. Yes Yes Yes Yes Yes Yes Yes
For NP requests, a CPL is also generated.

The TLP is dropped, when the filter mask


CX_FLT_MASK_MSG_DROP bit is 0 and the Yes
non-Vendor MSG is filtered with SU status.

The TLP is dropped, when the filter mask


CX_FLT_MASK_VENMSG0_DROP bit is 0 and Yes
the VEN0 MSG is filtered with SU status.

The TLP is dropped, when the filter mask


CX_FLT_MASK_VENMSG1_DROP bit is 0 and Yes
the VEN1 MSG is filtered with SU status.

a. SW downstream port should not expect to receive a CFG request.

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Processing Illegal CFG TLPs and CFG1-CFG0 Conversion in Each PCI Express Port Type PCI Express SW Controller Databook

H.5 Processing Illegal CFG TLPs and CFG1-CFG0 Conversion in Each PCI
Express Port Type
Routing IDs, requester IDs, and completer IDs are 16-bit identifiers traditionally composed of three fields:
an 8-bit bus number, a 5-bit device number, and a 3-bit function number. Configuration requests always
move downstream, and never travel across a peer-to-peer connection. An RC or SW downstream port (DSP)
never receives configuration requests.

H.5.1 SW Upstream Port (USP)


Receive Routing
The controller routes all CFG0 requests to TRGT0 (CDM or ELBI, through the LBC). The controller routes all
CFG1 requests to your application through the receive interface. CFG1 requests targeted to the
configuration space of the SW (DSP) must be converted (to CFG0) by your application logic, and driven
onto the DBI of the DSP. Your application logic must also generate completions, for these requests, at your
application transmit interface of the USP. The USP never forwards CFG0 requests to your application
(switch controller) logic.

Receive Checking
The controller responds with UR, to CfgRd0 requests with incorrect function number, it never checks the
Bus.Device numbers.
Conversion
The controller never does conversion of CFG1 to CFG0. Your application must do the conversion where
necessary.

Bus.Device Number Assignment


The controller snoops every [completed] CfgWr0 request and updates the Bus.Device numbers in its
completer ID.

H.5.2 SW Downstream Port (DSP)


Checking
The USP never forwards CFG0 requests to your application (switch controller) logic. Consequently, the DSP
does not expect to receive CFG0 requests. The controller does not check configuration requests (at your
application transmit interface) for valid target Bus.Device.Function numbers before it transmits them. It
does not check that the target bus number > secondary bus number and that target bus number <=
subordinate bus number. Your application must not provide illegal configuration requests to the controller.
It can determine the correct range of Bus.Device numbers by looking at the contents of the secondary bus
and subordinate bus registers, which are reflected on the cfg_pbus_num[7:0], cfg_2ndbus_num[7:0],
and cfg_subbus_num[7:0] outputs. Typically, your application logic can route configuration requests as
follows:
■ CFG requests in the range secondary bus number (inclusive) to subordinate bus number (inclusive)
are forwarded.
■ CFG1 requests addressing the secondary bus number are converted and forwarded as CFG0 requests.

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■ CFG1 requests addressing bus numbers between secondary bus number (exclusive) and Subordinate
Bus Number (inclusive) are forwarded as CFG1 requests.

Conversion
The controller never does conversion of CFG1 to CFG0. Your application must do the conversion where
necessary.

Bus.Device Number Assignment


The assignment of a Device number to the DSP, can be done in an implementation specific way.

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Advanced Information: Advanced Ordering Information PCI Express SW Controller Databook

I
Advanced Information: Advanced Ordering

Information

This appendix discusses advanced features and operation of ordering. The following topics are discussed.
■ “PCIe Ordering Rules”
■ “Inbound (Receive) Order Enforcement” on page 971
■ “Outbound (Transmit) Order Enforcement” on page 973

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PCI Express SW Controller Databook PCIe Ordering Rules

I.1 PCIe Ordering Rules


The PCI Express ordering rules are designed to satisfy the following three requirements:
1. Requirement: Producer-Consumer Model
In this model, (see Figure I-1), the consumer must not start reading a data buffer before a producer is
finished writing it. To prevent violation of the model, it is necessary to ensure that no transaction passes
a previously issued posted transaction. This is covered by rules 2, 5, and 9 in Table I-1 on page 970. The
following performance optimizations are added:
■ Producer-Consumer Relaxed Ordering (RO) Optimization
Completions and writes that are not involved in producer-consumer sequences, are permitted to
pass a previously issued posted transaction. This is achieved by setting their RO bit to ‘1’.
■ Producer-Consumer ID-Based Ordering (IDO) Optimization
A completion or request that originates from a different completer or requester, and that has its
IDO bit set to 1, is permitted to pass a blocked posted request. The controller does not implement
IDO but provides the information to your application.
Strong ordering (routing all TLPs in-order without reordering) satisfies the producer-consumer model.
The next two requirements seek to modify strong ordering.
2. Requirement: Deadlock Avoidance
Avoid blocking of completion and posted TLPs, by non-posted requests that are stalled. This is covered
by rules 1 and 4 in Table I-1 on page 970.
3. Requirement: Performance Optimizations
TLPs that are not bound by any of the previous requirements can pass or be blocked by each other. This
is covered by rules 3, 6, 7, and 8 in Table I-1 on page 970.

Figure I-1 Producer-Consumer Example


time=0
NPS NPS
Status
NPS1 NPS2 Register
CPU

CPLS CPLS
EP
RC PS

RAM PD PD
RAM
(dest) Master
PD1 PD2 CPLS1 PD3 PDn CPLS2 (source)

time=0
Producer: The master in the EP is taking data from the local source RAM and writing it into the destination RAM in the RC. This posted data is indicated as P D. The
master writes to the ‘finished’ flag in the status register after it has written the last PD.

Consumer: The CPU in the RC is polling the status register in the EP, checking if the master is finished producing the data. These polling/read requests are indicated
as NP S. The corresponding completion is indicated as CPL S.

Producer-Consumer Model: The CPLS must not pass any P D, or else the CPU starts to consume the data before it is fully produced. Therefore the EP, any
intermediate SW, and RC queues must obey this rule.
The rule does not need to be applied to P TLPs and CPLs that are not part of this Producer-Consumer sequence, for example, RC CPU CFG reads to unrelated
functions in the EP. You should set the relaxed ordering (RO) bit for these requests to ‘1'.

If there is an element in your system that is not enforcing the “CPL must not pass P” rule (for example, if the CPL receive queue in the RC is in bypass mode), you must
use an alternative method for communicating status between a producer and a consumer; use interrupts or place the data being read-from/written-to in a different
location in your PCIe system .

PCIe Ordering Rules (Summarized)


Ordering rules only apply for traffic within a single Traffic Class (TC). For a proper understanding of
ordering you should be familiar with Table 2-34 in section 2.4.1, “Transaction Ordering Rules” of the PCI
Express Base Specification, Revision 4.0, Version 1.0. Table I-1 summarizes the PCI Express ordering rules.

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Table I-1 Summarized PCIe Ordering Rules

No. Description Underlying System Requirement

1 P must be allowed to pass a previously-issued NP. Deadlock Avoidance

P must not pass a previously-issued P, unless:


■ the later P’s RO bit is 1
2 Producer-Consumer Model
or
■ the later P’s IDO bit is 1, and the requester IDs are different.

3 P can optionally passa a previously-issued CPL. Performance Optimization

4 CPL must be allowed to pass a previously-issued NP. Deadlock Avoidance

CPL must not pass a previously-issued P, unless:


■ CPL’s RO bit is 1
5 Producer-Consumer Model
or
■ CPL’s IDO bit is 1, and the completer/requester IDs are different.

CPL can optionally passa a previously-issued CPL, when the


6 Performance Optimization
transactionb IDs are different.

7 NP can optionally passa a previously-issued NP. Performance Optimization

8 NP can optionally passa a previously-issued CPL. Performance Optimization

NP must not pass a previously-issued P, unless:


■ NP’s IDO bit is 1, and the requester IDs are different,
9 Producer-Consumer Model
or (in the case of NP writes only)
■ NP’s RO bit is 1.

a. Or be blocked by
b. Combination of requester ID and tag

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PCI Express SW Controller Databook Inbound (Receive) Order Enforcement

I.2 Inbound (Receive) Order Enforcement


This section discusses reordering and order enforcement in the native controller’s receive queues . The
controller only enforces ordering of TLPs that are delivered to the primary receive application interfaces1
(TRGT1/RBYP ). It does not enforce ordering between these TLPs and the TLPs that are delivered to the
TRGT0, ELBI, or SII.
The SII is connected to the output of the receive filter and is not subject to receive queuing. Therefore, TLPs
that are routed to the SII may overtake the TLPs (not in bypass) that are destined for a primary receive
application interface. Typically2, the controller sends all message TLPs including
Assert_INTx/Deassert_INTx messages to the SII.

I.2.1 Receive Ordering Schemes


The following ordering schemes are used for ordering TLPs within a single VC. For this discussion, it is
assumed that all TLP queues are configured in store-and-forward or cut-through mode. Any TLP type
that is configured in bypass mode is not subject to ordering by the controller and can pass any other TLP
type. As all TLPs of the same type are queued in a FIFO, no passing within a single queue ever occurs. For
example, posted never passes posted.

Strict ordering, or round robin ordering, between TLPs of different VCs is used. In strict
Note
ordering, the higher numbered VCs are given a higher priority. You can set the VC arbitration
scheme during configuration using the CX_RADM_STRICT_VC_PRIORITY parameter or by
software by writing to the VC_ORDERING_RX_Q field in the VC0_P_RX_Q_CTRL_OFF
register.

PCIe Ordering (CX_RADM_ORDERING_RULES =1):


Summary: This scheme fully obeys the producer-consumer model and deadlock is avoided. All of the PCI
Express ordering rules in Table 2-34 (“2.4.1 Transaction Ordering Rules” section of the PCI Express Base
Specification, Revision 4.0, Version 1.0) are obeyed.
Method: TLPs are filtered into three separate FIFO queues: posted, non-posted, and completion. The
ordering controller determines which of the three queues have a TLP that is allowed to proceed, by looking
at:
■ Packet halt inputs (trgt1_radm_pkt_halt[], “TRGT1 Packet Grant and Halt” on page 291)
■ The PCIe ordering rules
When more than one queue has a TLP that is allowed to proceed, it uses a priority arbitration algorithm to
select a transaction. This prevents starvation, which occurs when delivery rate for a particular TLP type to
your application is unfairly reduced.
Rules: This scheme implements all of the PCI Express ordering rules.
Relaxed Ordering (RELAXED_ORDER_SUPPORT =1): A completion or a posted transaction with its RO header
bit set to 1, can pass a previously issued posted transaction that is blocked. RO is not implemented for
non-posted writes.

1. And that are not in bypass queue mode.


2. You can configure the controller to send messages to the application receive interface instead of the SII.

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Strict Priority Delivery (CX_RADM_ORDERING_RULES =0):


Summary: This scheme fully obeys the producer-consumer model and deadlock is avoided. All PCI Express
ordering rules in Table 2-34 (section 2.4.1, Transaction Ordering Rules of the PCI Express Base Specification,
Revision 4.0, Version 1.0) are obeyed.
Method: TLPs are filtered into three separate FIFO queues: posted, non-posted, and completion. They are
delivered according to the priority P-CPL-NP regardless of the order in which they are received. Posted has
the highest priority. No concept of received-order is used in this scheme. TLPs are delivered according to
the following steps:
1. The posted queue is delivered until it is empty, or halted by your application.
2. The completion queue is delivered until it is empty, or halted by your application.
■ When the posted queue is halted, the completion queue becomes blocked unless RO of the comple-
tion is 1.
3. The non-posted queue is delivered until it is empty, halted by your application, or blocked as follows:
■ When the posted queue is halted, the non-posted queue becomes blocked.
■ When the completion queue is halted, the non-posted queue becomes blocked.
■ When the completion queue is blocked (by a halted posted queue), the non-posted queue becomes
blocked.
Rules: This scheme implements all of the PCI Express ordering rules.
Relaxed Ordering (RELAXED_ORDER_SUPPORT =1): A completion or a posted transaction with its RO header
bit set to 1, can pass a previously issued posted transaction that is blocked. RO is not implemented for
non-posted writes.
Starvation (Fairness Not Comprehended): No concept of received-order is used in this scheme. Therefore, a
posted TLP that is received after a non-posted is delivered first, even when the non-posted queue is not
halted or blocked. This can lead to possible starvation of the non-posted queue (and completion to a lesser
extent) if the influx stream of posted writes from the wire continues indefinitely. When a certain TLP type
(completion or non-posted) is being passed too much, then the delivery rate for that TLP type to your
application is unfairly starved/reduced, leading to possible permanent blocking of that TLP type. For
example when the posted queue is never empty (because of application stalling and the receive posted TLP
delivery rate), then the non-posted queue is permanently blocked.

Synopsys recommends that you select the PCIe Ordering scheme and not this legacy
Note
ordering scheme.

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PCI Express SW Controller Databook Outbound (Transmit) Order Enforcement

I.3 Outbound (Transmit) Order Enforcement


This section discusses reordering in the outbound direction. The following topics are discussed.
■ “Ordering Across Outbound Interfaces”
■ “Outbound Order Enforcement On XALI0/1/2 Interfaces” on page 973

I.3.1 Ordering Across Outbound Interfaces


The controller does not enforce ordering between the MSI, MSI-X, DBI, VMI, SII, XALI0 , XALI1 , and XALI2
interfaces. Furthermore, it does not enforce ordering between transactions on any of these interfaces, and
internally generated messages or completions (for example, for a CFG access to internal registers). The
request arbitration priority (highest first) for transmission of TLPs at the internal transmit interface is:
1. Messages (both internally-generated and messages requested through the VMI)
2. Internally-generated completions for received CFG requests
3. Transmit TLPs from XALI0/1/2 according to the arbitration scheme in “Transmit TLP Arbitration” on
page 87.

I.3.2 Outbound Order Enforcement On XALI0/1/2 Interfaces


There are three application outbound transmit interfaces (XALI0, XALI1, and XALI2). All interfaces are
served using a round robin arbitration scheme when credit is available, regardless of the type of transaction.
For example, when a posted transaction is presented onto XALI1 followed by a completion transaction on
XALI0, and when credits permit, then the posted transaction is transmitted onto the wire before the
completion. When the credit is not available, then the completion on XALI0 can pass the posted on XALI1
and be sent onto the wire. However, any non-posted or completion TLPs on XALI1 (behind the blocked
posted) are blocked by the halted posted queue.
It is the responsibility of your application to make appropriate use of the three interfaces. There is no
guarantee that order is preserved among client interfaces. In some cases, you might consider implementing
some ordering rules in your application logic, for example, holding off a MRd transaction until the MWr
transaction is completed. For example, when your application has one source of outbound read transactions
and one source of outbound write transactions, and they are independent sources, then the XALI0 and
XALI1 interfaces of the controller should be used to perform the outbound transmission of the transactions.
When the read and write are related, then one single interface XALI0 should be used and it is the
responsibility of your application to maintain the desired order.

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Advanced Information: Advanced LBC and DBI Usage PCI Express SW Controller Databook

J
Advanced Information: Advanced LBC and

DBI Usage

This appendix discusses advanced features and operation of the “Local Bus Controller (LBC)” on page 104.
This following topics are covered in this section:
■ “Configuration Intercept Controller (CIC) for USP” on page 976

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PCI Express SW Controller Databook Programming Examples: CDM / ELBI Register Space Access Through DBI

J.1 Programming Examples: CDM / ELBI Register Space Access Through DBI
This section discusses advanced features and operation of “Data Bus Interface (DBI) Access” on page 111.
The following topics are discussed:
■ “Access From DBI (Native) (USP)” on page 975
■ “Access From Native DBI (DSP)” on page 975

J.1.1 Access From DBI (Native) (USP)


Selecting between ELBI and CDM is explicitly done using the LSB of the DBI address bus and dbi_cs2. You
can access:
■ ELBI (function independent) by setting:
❑ dbi_addr[0] =1 and dbi_cs2 =0 to indicate ELBI access. Note, that the lbc_ex-
t_bar_num[2:0]output is set to 3b111, and the lbc_ext_io_access/lbc_ext_rom_access
outputs are set to 0.
■ Port logic (PL) registers in the CDM (excluding iATU and DMA) by setting:
❑ dbi_addr[0] =0 and dbi_cs2 =0 to indicate CDM access
❑ dbi_addr[18:16] =function number (there is one common set of PL registers)
■ PCI configuration registers of any function, by setting:
❑ dbi_addr[0] =0 to indicate CDM access
❑ dbi_addr[18:16] =function number
■ iATU and DMA port logic registers, by setting:
❑ dbi_addr[0] =1 and dbi_cs2 =1 to indicate iATU and DMA register access
❑ dbi_addr[19:0] =Register Address

J.1.2 Access From Native DBI (DSP)


You can access the following spaces without any restrictions:
■ Port logic registers in the CDM by setting:
❑ dbi_addr[0] =0 and dbi_cs2=0
■ PCI configuration registers by setting:
❑ dbi_addr[0] =0 and dbi_cs2=0

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Configuration Intercept Controller (CIC) for USP PCI Express SW Controller Databook

J.2 Configuration Intercept Controller (CIC) for USP


All CFG requests from the remote link partner are routed to the internal CDM or external ELBI registers
without notifying your application. The CIC allows your application logic to detect the occurrence of; and to
modify the behavior of CFG requests. Using the Configuration Intercept Interface (CII):
■ The controller provides a notification when a valid CFG request is received. It also provides the TLP
header information and data (for CfgWr).
■ Your application logic can delay the processing of the CFG request by the controller. This allows your
application to perform any housekeeping tasks first. For example, send any pending completions
before the Bus Master Enable is disabled.
■ Your application logic can overwrite the data payload of a CfgWr request.
■ Your application logic can overwrite the data payload of the CfgRd completion TLP.

Figure J-1 CIC Operation (CX_CONFIG_INTERCEPT_ENABLE =1)

RX PIPE
Application RBYP
2 1
Logic: RADM
Receive TRGT1

CII.monitor 3
CII.halt 4 CIC
CII.override 5

Application ELBI LBC


6
Registers
CXPL Core

CPU DBI 7
CXPL PHY

CDM Core
Registers

Request flow
Completion flow
XADM 8
TX PIPE

Intercept of CFG Access to CDM or ELBI Registers


1 Incoming request from PCIe remote link partner

2 Request is filtered and routed by RADM through TRGT0 to LBC

3 CIC indicates receipt of CFG request and presents TLP header and data (CfgWr) on CII
CIC: Your application can optionally halt/stall the progress of the CFG request (example: allow time for
4
housekeeping)
5 CIC: Your application can optionally modify CfgWr payload (or the CfgRd CPL data, step 7).

6 LBC forwards the request to internal registers in CDM

7 LBC forms completion TLPs with response received from internal registers in CDM (optionally modified by CIC)

8 PCIe core transmits response completion to remote link partner

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PCI Express SW Controller Databook Configuration Intercept Controller (CIC) for USP

Figure J-2 CIC Timing


Config Write Request Config Read Request

lbc_cii_hv

lbc_cii_hdr_poisoned
lbc_cii_hdr_type[4:0]
lbc_cii_hdr_fbe[3:0]
lbc_cii_hdr_tag[7:0]
lbc_cii_hdr_req_id[15:0]
lbc_cii_hdr_addr[11:0] VLD VLD
lbc_cii_hdr_bus_num[7:0]
lbc_cii_hdr_dev_num[4:0]
lbc_cii_hdr_func_num[(PF_WD-1):0]
SRIOV: lbc_cii_hdr_vfunc_num[(VF_WD-2):0]
SRIOV: lbc_cii_hdr_vfunc_active

lbc_cii_dv
lbc_cii_data[31:0] VLD

cii_lbc_halt

cii_lbc_override_en VLD VLD

cii_lbc_override_data[31:0] VLD VLD

When you want to halt configuration request and do house keeping tasks first:
■ Keep cii_lbc_halt =1
■ The controller provides notification on lbc_cii_* and waits for cii_lbc_halt =0
■ Perform DBI accesses to CDM while (lbc_cii_hv =1 & cii_lbc_halt =1)
■ Set cii_lbc_halt =0
When you want to override CfgWr request or CfgWr/CfgRd completion payload data:
■ Keep cii_lbc_halt =1
■ The controller provides notification on lbc_cii_* and waits for cii_lbc_halt =0
■ Set cic_lbc_override_en =1
■ Provide override data on cic_lbc_override_data
■ Set cii_lbc_halt =0

The controller only provides a notification on the CII for error-free packets that pass all Rx
Note
filtering rules successfully.

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Advanced Information: How to Tie Off Unused Lanes PCI Express SW Controller Databook

K
Advanced Information: How to Tie Off Unused

Lanes

When the link width of the PHY is smaller than the link width of the controller, you must tie off the unused
lanes of the controller’s PIPE (or RMMI) interface. This appendix describes the procedure to tie-off the
unused lanes of the controller’s PIPE (or RMMI) interface. In this appendix, connection between a four-lane
controller and one-lane PHY is used as an example to explain the procedure to tie off unused lanes.

■ This appendix only gives general guidelines, and pointers to aspects of unused lanes that
Caution you must be aware of.
■ Synopsys accepts no responsibility for any PCIe IP controller and PHY integration deci-
sions made by you as a consequence of accessing this appendix.
■ The example in this appendix is not simulated or verified by Synopsys.

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PCI Express SW Controller Databook Conventional PCIe

K.1 Conventional PCIe


Lane0 signals must always be active. For the other lanes (1,2,3) to be made inactive, you must make the
connections in Table K-1.

Table K-1 PIPE Interface Ports Affected by Unused Lanes

PIPE Port Name Direction Connection for Unused Lane signals

phy_mac_rxelecidle Input 1b1

phy_mac_phystatus Input connect to phy_mac_phystatus[0]

phy_mac_rxdata Input 0x0

phy_mac_rxdatak Input 0x0

phy_mac_rxvalid Input 0x0

phy_mac_rxstatus Input 0x0

phy_mac_rxdatavalid Input 0x0

phy_mac_rxstartblock Input 0x0

phy_mac_rxsyncheader Input 0x0

phy_mac_localfs Input 0x0

phy_mac_locallf Input 0x0

mac_phy_txdata Output Unconnected

mac_phy_txdatak Output Unconnected

mac_phy_txdetectrx_loopback Output Unconnected

mac_phy_txelecidle Output Unconnected

mac_phy_txcompliance Output Unconnected

mac_phy_rxpolarity Output Unconnected

mac_phy_txdatavalid Output Unconnected

mac_phy_txstartblock Output Unconnected

mac_phy_txsyncheader Output Unconnected

mac_phy_txdeemph Output Unconnected

mac_phy_rxpresethint Output Unconnected

mac_phy_rxeqeval Output Unconnected

mac_phy_blockaligncontrol Output Unconnected

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Conventional PCIe PCI Express SW Controller Databook

Software Configuration
When there are unused lanes in a system, you must reprogram the following registers through the DBI. For
this example, where a 4-lane controller is connected to a 1-lane PHY:
■ Reprogram LINK_CAPABLE field of the PORT_LINK_CTRL_OFF register to 6h1 from 6h7.
This is used by the LTSSM in Detect.
■ Reprogram NUM_OF_LANES[8:0] field of the GEN2_CTRL_OFF register to 9h1 from 9h4.
This indicates to the LTSSM, the number of lanes to check for exiting from L2.Idle or Polling.Active.
■ Reprogram PCIE_CAP_MAX_LINK_WIDTH field of the LINK_CAPABILITIES_REG register to 6h1 from
6h4.
This enables the RC to determine the Maximum Link Width for this port.

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PCI Express SW Controller Databook Advanced Information: Advanced Error Handling for Received TLPs

L
Advanced Information: Advanced Error

Handling for Received TLPs

This appendix discusses advanced features and operation associated with “Error Handling” on page 97.
You should first read to familiarize yourself with basic information on the filtering and routing of received
errored-TLPs. The following advanced topics are discussed in this appendix:
■ “Routing of Request TLPs with Errors” on page 982
■ “Routing of Completions with Errors” on page 986
■ “Application Error Reporting Interface” on page 990

For more information on advanced routing and filtering, see “Advanced Information: Advanced
Note Filtering and Routing of TLPs” on page 954.

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Routing of Request TLPs with Errors PCI Express SW Controller Databook

L.1 Routing of Request TLPs with Errors


The following discussion refers to requests and messages that are targeted at local resources and not for port
forwarding1.
TLPs appear on the RBYP interface in bypass mode, and on the TRGT1 interface otherwise.

Store-and-Forward Queue Mode


In general when the controller detects an error in a received TLP, it discards the TLP and does not forward it
to your application. Exceptions to this are detailed in Figure L-1.

Figure L-1 Overview of Routing For TLPs with Errors in Store-and- Forward Mode
Layer 3 Checks

ECRC Check

Other TLP
Checks

Malformed
Header
Checks

Malformed
Data Checks

Unsupported
Request
Check

Layer 1 and 2 Checks

DLLP
Checks

1
Internally Discarded
Store-Fwd
RX TLP Buffer 0 Application I/F

Table L-1 Processing of Received TLPs with Errors in Store-and-Forward Mode

Error Type TLP Destination Abort Error Outputs Asserted

Unsupported Request / Request with Malformed Header


Discardeda None
or Data / Completer Abort / CRS / Data Link Layer Error

1. A switch forwards all TLPs that are destined for other PCIe components except when a layer 1 or 2 DLLP check fails or the
TLP is malformed.

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PCI Express SW Controller Databook Routing of Request TLPs with Errors

Error Type TLP Destination Abort Error Outputs Asserted

ECRCb Error Discarded None

a. Can be redirected to your application logic when the DEFAULT_TARGET (USP only) field in the MISC_CONTROL_1_OFF
register is ‘1’.
b. If CX_FLT_MASK_ECRC_DISCARD =1, the TLP is forwarded to your application logic. In additionradm_trgt1_ecrc_err is
asserted if ECRC_ERR_PASS_THROUGH =1. The radm_trgt1_tlp_abort signal is never asserted.

Bypass Queue Mode


In general when the controller detects an error in a received TLP, it continues to forward the TLP to your
application, and asserts the *tlp_abort or *dllp_abort signals to indicate that your application should
drop the TLP and rollback its buffer pointers. Exceptions to this are detailed in Table L-2.

Figure L-2 Overview of Routing For TLPs with Errors in Bypass Mode
Layer 3 Checks

ECRC Check radm_<*_ecrc_err


@ dadm_*_eot

Other TLP
Checks

Malformed
Header radm_*_tlp_abort
Checks @ radm_*_eot or
radm_*_hv

Malformed
Data Checks

Unsupported
Request
Check

Layer 1 and 2 Checks

DLLP radm_*_dllp_abort
Checks @ radm_*_eot

See Table O-2

RX TLP
1
Internally Discarded
Bypass
0 Application I/F

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Routing of Request TLPs with Errors PCI Express SW Controller Databook

Table L-2 Processing of Received TLPs with Errors in Bypass/Cut-Though Mode

Error Type TLP Destination Abort Error Outputs Asserted

Unsupported Request / Completer Abort / CRS /


Application Logic radm_bypass_tlp_abort
Malformed Data

Data Link Layer Errora Application Logic radm_bypass_dllp_abort

ECRCb Error Discarded None

Request with Malformed Header Application Logic radm_bypass_tlp_abort

a. If Layer 3 checks fail, then controller discards the request and does not assert radm_bypass_dllp_abort.
b. If CX_FLT_MASK_ECRC_DISCARD =1, then TLP is forwarded to your application logic and radm_bypass_ecrc_err is asserted
(if ECRC_ERR_PASS_THROUGH =1). TLPs with errors are generally dropped unless the CX_FLT_MASK_ECRC_DISCARD
filter rule is set, but because an ECRC error occurs at the end of the TLP, a TLP in cut-through mode with an ECRC error must
be passed through. Note that cut-through mode decays into store-and-forward mode when the queues become full; if there is
more than one TLP in the buffer when the queue is in cut-through mode, the TLPs being received are treated the same as
store-and-forward mode. Only the first TLP in the queue behaves in cut-through mode.

Table L-3 Description of *_abort and *ecrc_err Outputs

Signal Validated By Notes

radm_*_tlp_abort radm_*_eota The error is non-correctable. You should not expect the TLP to be replayed.

The error is correctable. You can normallyb expect the DLLP to be replayed.
Some DLL error conditions such as a missing end delimiter (EOT) can
radm_*_dllp_abort radm_*_eot
cause your applications receive buffer to overflow. Your application must
implement some EOT timeout detect logic.

radm_*_ecrc_err radm_*_eot The error is non-correctable. You should not expect the TLP to be replayed.

a. Sometimes validated by radm_bypass_hv.


b. Except when the TLP fails a credit check (receiver overflow checking). In this case the controller ACKs the TLP. The assertion
of radm_*_dllp_abort indicates that no credits are returned.

Disabling of Error Filtering


In many cases, the standard routing rules can be masked or ignored by setting the corresponding bit in the
Symbol Timer and Filter Mask 1 register (SYMBOL_TIMER_FILTER_1_OFF) and Filter Mask Register 2
(FILTER_MASK_2_OFF). You can prevent all associated downstream effects such as error logging, error
MSG generation, and completion generation (for non-posted requests).
You can also turn off most of the filter rules, and perform your own error checking for all TLPs, regardless
of the receive queue mode. Your application must then report errors. This is not a recommended mode of
operation. When you mask detection of completion timeout errors, through setting the
CPL_TIMEOUT_ERR_MASK configuration parameter, then the controller does not automatically report
completion timeout errors. Your application must check for completion timeouts, and report completion
timeout errors using the “Application Error Reporting Interface” on page 990. Messages with UR status are
always dropped, regardless of any changes that you make to the filter masks. For message routing see,
“Advanced Information: Advanced Filtering and Routing of TLPs” on page 954.
When you set the DEFAULT_TARGET (USP only) field in the MISC_CONTROL_1_OFF register to ‘1’, then all
incoming I/O or memory requests with UR/CA/CRS status are not dropped, but are forwarded to your
application.

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PCI Express SW Controller Databook Routing of Request TLPs with Errors

When an LCRC error occurs on an inbound request which contains an ECRC, and the
Attention controller forwards the TLP to your application (queue is in bypass or cut-through), the
radm_trgt1_dwen outputs are not accurate on the last beat (eot) of the TLP when the TLP
payload (excluding ECRC) is not a multiple of the controller datapath width.
You must discard all data from this TLP including the additional data because
radm_*_dllp_abort is active on radm_*_eot.

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Routing of Completions with Errors PCI Express SW Controller Databook

L.2 Routing of Completions with Errors


The following discussion refers to completions that are targeted at local resources and not for port
forwarding1.
Completion TLPs appear on the RBYP interface in bypass mode, and on the TRGT1 interface otherwise.

Store-and-Forward Queue Mode


In general when the controller detects an error in a received completion, it discards the completion and does
not forward it to your application. Exceptions to this are detailed in Table L-4.

Figure L-3 Overview of Routing For Completion TLPs with Errors in Store-and- Forward Mode
Layer 3 Checks

ECRC Check

Other TLP
Checks

Malformed
Header
Checks

Malformed
Data Checks

Layer 1 and 2 Checks

DLLP
Checks

1
Internally Discarded
Store-Fwd
RX TLP Buffer 0 Application I/F

1. A switch forwards all TLPs that are destined for other PCIe components except when a layer-1 or layer-2 DLLP check fails
or the TLP is malformed.

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PCI Express SW Controller Databook Routing of Completions with Errors

Table L-4 Processing of Received Completions with Errors in Store-and-Forward Mode

Error Type CPL Destination Abort Error Outputs Asserted

Replayed Completion / Completion with Malformed


Header or Data / Completion Statusa / Data Link Layer Discarded None
Error

ECRCb Error Discarded None

Unsuccessful Completion Status / Poisoned /


Application Logic Nonec,d
Completion Timeout

a. Endpoint only.
b. If CX_FLT_MASK_CPL_ECRC_DISCARD =1, then the TLP is forwarded to your application logic. In additionrad-
m_trgt1_ecrc_err is asserted if ECRC_ERR_PASS_THROUGH =1. radm_trgt1_tlp_abort is never asserted.
c. Completion timeout: Requester information is returned on CPL Timeout interface.
d. Poisoned: radm_trgt1_ep is asserted.

In general when the controller detects an error in a received completion, it continues to forward the
completion to your application, and asserts the *tlp_abort or *dllp_abortsignals to indicate that your
application should drop the TLP and rollback its buffer pointers. Exceptions to this are detailed in Table L-5.

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Routing of Completions with Errors PCI Express SW Controller Databook

Figure L-4 Overview of Routing For Completion TLPs with Errors in Bypass/Cut-Through Mode
Layer 3 Checks

ECRC Check radm_<*_ecrc_err


@ dadm_*_eot

Other TLP
Checks

Malformed
Header radm_*_tlp_abort
Checks @ radm_*_eot or
radm_*_hv

Malformed
Data Checks

Layer 1 and 2 Checks

DLLP radm_*_dllp_abort
Checks @ radm_*_eot

See Table O-5

RX TLP
1
Internally Discarded
Bypass
0 Application I/F

Table L-5 Processing of Received Completions with Errors in Bypass/Cut-Through Mode

Error Type CPL Destination Abort Error Outputs Asserted

Unsuccessful Completion Status / Poisoned /


Application Logic Nonea,b
Completion Timeout

Malformed Data / CRS Completion Status Application Logic radm_bypass_tlp_abort

Data Link Layer Errorc Application Logic radm_bypass_dllp_abort

ECRC Error Application Logic radm_bypass_tlp_abort

Replayed Completion with Malformed Header Application Logic radm_bypass_tlp_abort

a. Completion timeout: Requester information is returned on CPL Timeout interface.


b. Poisoned: radm_bypass_ep is asserted.
c. If Layer 3 header checks fail, then controller discards the completion and does not assert radm_bypass_dllp_abort.

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PCI Express SW Controller Databook Routing of Completions with Errors

Table L-6 Description of *_abort and *ecrc_err Outputs

Signal Validated By Notes

radm_*_tlp_abort radm_*_eota The error is non-correctable. You should not expect the TLP to be replayed.

The error is correctable. You can normallyb expect the DLLP to be replayed.
Some DLL error conditions such as a missing end delimiter (EOT) can
radm_*_dllp_abort radm_*_eot
cause your applications receive buffer to overflow. Your application must
implement some EOT timeout detect logic.

radm_*_ecrc_err radm_*_eot The error is non-correctable. You should not expect the TLP to be replayed.

a. Sometimes (for malformed TLP, UC or replayed CPL) validated by radm_bypass_hv.


b. Except when the TLP fails a credit check (receiver overflow checking). In this case the controller ACKs the TLP. The assertion
of radm_*_dllp_abort indicates that no credits are returned.

When an LCRC error occurs on an inbound request which contains an ECRC, and the
Attention controller forwards the TLP to your application (queue is in bypass or cut-through), the
radm_trgt1_dwen outputs are not accurate on the last beat (eot) of the TLP when the TLP
payload (excluding ECRC) is not a multiple of the controller datapath width.
You must discard all data from this TLP including the additional data because
radm_*_dllp_abort is active on radm_*_eot.

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Application Error Reporting Interface PCI Express SW Controller Databook

L.3 Application Error Reporting Interface


You can use this optional interface when you are implementing additional error checking on received TLPs
in your application logic. For example, when you are implementing the “Reliability, Availability, and
Serviceability (RAS)” on page 124. In this case, it is expected that your application implements an
appropriate error handling scheme by monitoring the parity or ECC output signals. One way to use these
signals is to "OR" them, and drive the Uncorrectable Error bit of the app_err_bus input.

Figure L-5 Error Logging (Upstream Port)


PIPE (RX)

Core
Receive
Optional DLL Layer
Error Reporting detected
Interface errors Core
(app _err_* / app_hdr_* inputs ) Receive
TL Layer

To
Receive
Buffers

PCIe
Status
and AER
Registers

Error
Message
Generation

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PCI Express SW Controller Databook Application Error Reporting Interface

Figure L-6 Error Logging (Downstream Port)


PIPE (RX)

Core
Receive
Optional DLL Layer
Error Reporting detected
Interface errors Core
(app _err_* / app_hdr_* inputs ) Receive
TL Layer

To
Receive
Buffers

PCIe
Status
and AER
Registers

You must set the APP_RETURN_ERR_EN configuration parameter to enable the Application Error Reporting
Interface.

Table L-7 Mapping of app_err_bus Bits to AER Status Registers

app_err_bus[11:0] Target Register Bit

0: Malformed TLP AER Uncorrectable [18]

1: Receiver Overflow AER Uncorrectable [17]

2: Unexpected CPL AER Uncorrectable [16]

3: Completer Abort AER Uncorrectable [15]

4: CPL Timeout AER Uncorrectable [14]

5: Unsupported Request AER Uncorrectable [20]

6: ECRC Check Failed AER Uncorrectable [19]

7: Poisoned TLP Received AER Uncorrectable [12]

8: AtomicOp Egress Blocked: only valid when CX_ATOMIC_ROUTING_EN =1. AER Uncorrectable [24]

9: Uncorrectable Internal Error


The controller sets the INTERNAL_ERR_STATUS bit in UNCORR_ERR_STATUS_OFF AER Uncorrectable [22]
when your application asserts this input.

10: Corrected Internal Error AER Correctable [14]

11: TLP Prefix Blocked Error Status: only valid for RC and when CX_NPRFX > 0. AER Correctable [25]

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Application Error Reporting Interface PCI Express SW Controller Databook

app_err_bus[11:0] Target Register Bit

12: ACS Violation: only valid when CX_ACS_ENABLE =1. AER Uncorrectable[21]

When you report an error on this interface at the same time (exact same clock cycle) as when
Attention the controller is reporting an error internally, then there is a potential for Header Log Overflow
to occur, as described in 6.2.4.2. “Multiple Error Handling” in the PCI Express Base
Specification, Revision 4.0, Version 1.0. The controller can only log one TLP header per
function, and in this scenario it discards the header from the controller. However, both error
bits are set in the Uncorrectable Error Status register, assuming that they are of different
types.

You can also turn off the filter rules and perform your own error checking for all TLPs. For more
information, see “Routing of Request TLPs with Errors” on page 982. This is not a recommended mode of
operation.

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PCI Express SW Controller Databook Advanced Information: Calculating Gen1 PCI Express Throughput

M
Advanced Information: Calculating Gen1 PCI

Express Throughput

This appendix defines the throughput calculation (primarily) with respect to the PCI Express controller in
Gen1 2.5 GT/s mode, and provides guidelines to enable you to meet your desired throughput by selecting
the appropriate configuration parameters from those supplied with the controller.
This appendix describes the throughput calculation, parameters that impact the calculation (such as the
maximum payload size selection), and matching-up the appropriate application interface to obtain the best
system performance from the controller. The following topics are discussed.
■ “PCI Express Bandwidth and Throughput”
■ “Effective Throughput” on page 996

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PCI Express Bandwidth and Throughput PCI Express SW Controller Databook

M.1 PCI Express Bandwidth and Throughput


PCI Express bandwidth is 2.5 Gb/s (gigabits per second), per lane, when operating at the Gen 1 data rate.
The data is encoded using 8b10b encoding, so the effective maximum throughput is 250 MB/s (megabytes
per second), per lane, calculated as follows:
2.5 Gb * 8b/10b =2 Gb * 1B/8b =250 MB/sec per lane
Throughput for other lane widths are shown in Table M-1.

Table M-1 Theoretical Throughput vs. Lane Width

Lane Width Throughput after 8b/10b (MB/s)

x1 250

x2 500

x4 1000

x8 2000

x16 4000

M.1.1 Configuring the PCI Express Controller with Respect to Throughput


The PCI Express controller is available in 32, 64, and 128-bit data path widths (32 optimized for a one lane
application). The PCI Express controller supports two clock frequencies. For the FPGA environment, the
clock from the PHY and the controller clock can be configured to 125 MHz. For the ASIC, the controller can
also support the 250 MHz clock.
■ 125 MHz => 16 bit PHY (one clock per two symbols)
■ 250 MHz => 8 bit PHY (one clock per symbol)
Whether the clock is 125 MHz or 250 MHz, the throughput from the PIPE is the same, 250 MB/s per lane.
The throughput to the application interface is different, based on the clock frequency selected in the
controller.
Table M-2 shows the throughput for 32, 64, and 128-bit data path widths configured with a 125 MHz clock.
Table M-3 shows the throughput for 32, 64, and 128-bit data path widths configured with a 250 MHz clock.

Table M-2 Throughput for Data Widths with a 125 MHz Clock

Data Path Width (Bits) Max Throughput @ 125 MHz (MB/s) Lane Width

32 250 x1

32 500 x2

64 1000 x4

128 2000 x8

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PCI Express SW Controller Databook Configuring the PCI Express Controller with Respect to Throughput

Table M-3 Throughput for Data Widths with a 250 MHz Clock

Data Path Width (Bits) Max Throughput @ 250 MHz (MB/s) Lane Width

32 1000 x4

64 2000 x8

128 4000 x16

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Effective Throughput PCI Express SW Controller Databook

M.2 Effective Throughput


The effective throughput on the link is the payload throughput after all the PCIe protocol's overheads have
been factored out. The key protocol features are:
■ 8b10b encoding at the physical layer. This takes away 20% of the raw bandwidth.
■ Acknowledge and flow control update packets at the Data Link Layer (DLLPs). This takes away 1% to
5% of the remaining bandwidth.
■ Packet overhead (Figure M-1) at the transaction layer. Your design choices have a great effect here:
❑ Small packets can take away 75% of the bandwidth.
❑ Large packets can take away as little as 1%.

Figure M-1 TLP Packet (with associated Data Link Layer overhead bytes)

Table M-4 summarizes throughput calculations based on a payload size from 16 to 4K bytes.

Table M-4 Effect of Packet Overhead on Link Throughput

Data TLP Throughput Throughput


Packet Payload Header ECRC DLLP and PHY before 8b10b after 8b10b
Type Bytes Bytes Bytes Bytes Calculation encoding encoding

Worst 16 16 4 8 16/44 36% 29%

Typical 128 16 0 8 128/152 84% 67%

256 16 0 8 256/280 91% 73%

512 16 0 8 512/536 96% 76%

Best 4096 12 0 8 4096/4116 99% 79%

■ A 128-byte payload size yields about 67% of the net throughput. Increasing the payload
Note size to 512 bytes increases the net throughput to 76%.
■ Increasing the payload size from 512 bytes to 4096 bytes, and using the smaller three
DWORD header, only contributes an increase of 3% in the net throughput, and the storage
requirements are more than doubled.
■ In addition, a large payload size might have an impact on performance due to re-transmis-
sion of TLPs.
■ Therefore, 256-byte and 512-byte payload sizes are the most popular choices. Most chip
sets support 128 -byte or 256-byte payload sizes, with 512 bytes gaining in popularity.

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PCI Express SW Controller Databook Effect of Link Layer Flow Control and ACK/NAK DLLPs

A breakdown of the theoretical throughput for your specific configuration is available in the coreConsultant
GUI “Report” tab.

M.2.1 Effect of Link Layer Flow Control and ACK/NAK DLLPs


DLLPs should be sent as often as required to avoid a negative impact on the TLP throughput. The controller
sends a pending DLLP if there is no competing TLP traffic. Sending ACK/NAK and Update FC is
controlled by timers. The controller provides flexibility to fine-tune these as required. The default setup is
minimal flow control (one per time-out) and minimal ACK/NAK device latencies. The link partner’s retry
buffer (payload) size might require a change in the ACK/NAK/Update FC time-out to obtain optimal
system latency. The controller provides a feature to accumulate up to 255 ACKs before issuing an ACK. This
feature offers-fine tuning of ACK frequency impact. The controller transmits ACKs at fixed intervals, by
default. For more information, see “Ack Frequency and L0-L1 ASPM Control Register”
ACK_F_ASPM_CTRL_OFF. Figure M-2 identifies the DLLP package. Table M-5 summarizes the throughput
calculations.

Figure M-2 DLLP Package

Table M-5 Effective Throughput

Percent
Bytes Result Throughput

Worst One ACK plus one FC per 128 (8 packets of 16)


(8*44) / (8*44 + 2*8) 95%
Packet bytes of data => 2 DLLPs per 8 data packets

Typical One ACK plus one FC per 1.4 (256 byte payload)
1.4*280 / (1.4*280 + 2*8) 96%
Packet bytes of data => 2 DLLPs per 1.4 packets

Best One ACK plus one FC per 4096 bytes of data => 2
4116 / (4116 + 2*8) 99%
Packet DLLP per data packet

M.2.2 Other Factors Impacting Throughput


Replay Buffer and Receiver Queue Sizing
Replay buffer and receiver queue sizing should be optimal to avoid a harmful impact of larger ACK/NAK
or Update FC latencies by the link partner. The controller performs an effective auto-sizing of the buffers
taking into consideration the impact of these parameters.

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Advanced Information: Advanced Routing of Received Messages PCI Express SW Controller Databook

N
Advanced Information: Advanced Routing of

Received Messages

This appendix discusses advanced features and operation associated with “Message Reception” on page
164. You should first read to familiarize yourself with basic information on the filtering and routing of
received message TLPs.

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N.1 Routing of Received Messages


All error-free MSG requests are decoded internally, signaled on the SII interface and then dropped (not
forwarded to your application1 on TRGT1 or RBYP ). To configure the controller to send messages to your
application, then either (a) set the FLT_DROP_MSG configuration parameter to 0 or (b) set the register fields
outlined in Table N-1 to 1. These registers allow you to override any decisions (regarding MSG routing)
made at configuration time by the FLT_DROP_MSG, DEFAULT_FILTER_MASK_1, and
DEFAULT_FILTER_MASK_2 configuration parameters. When a MSG request is filtered with UR/CA/CRS
status, the TLP is always dropped. Only MSG requests filtered with SC status, can potentially be forwarded
to your application on TRGT1 .

Table N-1 Controlling the Routing of Received Messages

Register Bit Function Default Value

Mask the dropping of Non-Vendor Messages DEFAULT_FILTER_MASK_1[13]


Filter Mask Register 1 29
0: Drop; 1: Do not drop = ! FLT_DROP_MSG =0

Mask the dropping of Vendora Type0 Messages


Filter Mask Register 2 0 DEFAULT_FILTER_MASK_2[0] =0
0: Dropb; 1: Do not drop

Mask the dropping of Vendor1 Type1 Messages


Filter Mask Register 2 1 DEFAULT_FILTER_MASK_2[1] =0
0: Drop; 1: Do not drop

a. For the masking (of the dropping) of Vendor messages, it is not possible to differentiate between Vendor Message without
Payload (Msg) and Vendor Message with Payload (MsgD).
b. Vendor Type0 Messages are dropped with UR error reporting.

Full information of the Filter Mask Registers are in Symbol Timer and Filter Mask 1 register
(SYMBOL_TIMER_FILTER_1_OFF) and Filter Mask 2 register (FILTER_MASK_2_OFF).

Figure N-1 Received 3rd and 4th Message Header Byte Mapping at Interfaces
Byte 15 is in position [7:0]
4-DW Header ? for 4-DWORD headers

TRGT1
0 0x0
8-11
63
FLT_Q_ADDR_WIDTH

1
32 bytes 8-11
31

0
P
0 I
bytes 12-15 P
1 Core
Logic E
For 256-bit c onfigurations , this interfac e is 128-bits
wide. S ee I/O des c ription for more details .

63 bytes 8-11

32
SII.MESSAGE
(radm_msg_payload ) 31 bytes 12-15
0

1. Vendor TYPE0 messages causes an UR error.

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For more information, see the I/O descriptions of:


■ radm_cpl_data
■ radm_bypass_data/radm_bypass_addr
■ radm_trgt1_addr
■ radm_msg_payload

N.1.1 Message Reception on TRGT1


As previously mentioned in “Routing of Received Messages” on page 999, the controller does not route
messages to your application on TRGT1 . To configure the controller to send messages to your application,
you must set the register fields outlined in Table N-1 to 1. To access the third and fourth TLP header
DWORDs, you must support 64-bit addressing in your application.

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PCI Express SW Controller Databook Advanced Information: Replay Buffer Sizing

O
Advanced Information: Replay Buffer Sizing

This appendix explains how coreConsultant automatically calculates the size of the “Transmit Replay” on
page 91. The retry buffer should be large enough so that, under normal operating conditions, back-to-back
transmission of maximum sized packets (of size CX_MAX_MTU) is never throttled by a full retry buffer.
Normal operating conditions mean ACK DLLPs are received as opposed to NAK DLLPs. In determining
the optimal buffer size, one must consider the following components which are additive:
1. The remote ACK_NAK latency timer starts when the last symbol of a TLP is received. Therefore one
maximum sized packet from the local device must be stored in the replay buffer to accumulate transmit
TLP data.
2. An Ack DLLP is not scheduled by the remote device until its ACK_NAK latency timer has expired.
During the time interval between start and expiry of the ACK_NAK latency, the replay buffer must
have additional space to accumulate transmit TLP data.
3. When the ACK_NAK latency timer expires in the remote device, there is a delay to the transmission of
the Ack DLLP if the remote device has just started transmitting a TLP packet. Therefore additional
space to store a remote maximum sized packet needs to be added to the local replay buffer size to accu-
mulate transmit TLP data.
4. The L0s exit latency required by the device's receiver.
5. The delays caused by the:
a. Transmission of a TLP by the local device.
b. Processing of TLP by the remote device.
c. Transmission of a Ack DLLP by the remote device.
d. Processing of a Ack DLLP by the local device.
e. Round trip latency of Re-timer device (if present). This latency is calculated from CX_MAX_RE-
TIMER value.
The equation to derive this depth is as follows. The label in each {} represents the contribution by each factor
detailed in the previous numbered list:
depth =data_size{1} + data_size{3} + (larger of(l0s_adj{4} or
retimer_latency{5.e})+ ack_lat_limit{2} + remote_dly_factor{5.b and 5.c})/cx_nb +
cx_internal_delay{5.a and 5.d}
where:

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■ data_size{1} and data_size{3} are both the CX_MAX_MTU size expressed in units of controller
data width. For example, a 1024 byte CX_MAX_MTUfor a 128-bit controller is 1024*8/128 =64 entries.
■ l0s_adj{4}is (CX_NFTS+1)*4because there are four symbols in a fast training sequence (FTS).
■ ack_lat_limit{2} comes directly from Tables 3-7,3-8, and 3-9 of the PCI Express Base Specification,
Revision 4.0, Version 1.0.
■ cx_nb is the number of symbols processed at the PIPE interface per lane For example, the value is two
symbols (16-bit PIPE) for a Gen2 controller running at 250 MHz.
■ remote_dly_factor{5.b and 5.c} are the MAC and PHY delays (Tx and Rx) in the remote device.
To model this, Synopsys uses the PCI Express Base Specification, Revision 4.0, Version 1.0 recommenda-
tion of a constant value of 19 Symbol Times for 2.5 GT/s mode operation, 70 Symbol Times for 5.0
GT/s mode operation, and 115 Symbol Times for 8.0 GT/s and 16 GT/s mode operation.
■ cx_internal_delay{5.a and 5.d}are the MAC and PHY delays (Tx and Rx) of the local device.
It is possible that this equation gives a retry buffer depth which is too large for your requirements. For
example, referring to item {3}, this can happen if the maximum packet size that is transmitted by the
remote device is smaller than CX_MAX_MTU of the local device (the equation assumes these are the same)
OR
you choose to trade off some temporal drop in performance versus back pressure on the local transmit client
interface for the retry buffer depth.
For more information on the actual parameters used, see “Parameter Descriptions”.

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PCI Express SW Controller Databook Advanced Information: Endianness

P
Advanced Information: Endianness

PCIe transfers information as a serialized stream of bytes. At the byte level, information is transmitted and
received over the wire with the leftmost byte (byte 0 in Figure P-1) being transmitted first. However,
endianness is only relevant when considering the arrangement of bytes within (for example) a DWORD.
Reading the PCI Express Base Specification, Revision 4.0, Version 1.0, it is possible to interpret parts of the TLP
header byte ordering as big endian. For example, the most significant byte of the address field is transferred
first so that it may be used for early address decode. However, the arrangement of the payload (data) is little
endian.

Figure P-1 PCIe Express Specification Byte Ordering (Four DWORD Header)

In a similar way, the controller implements the headers1 as big endian and the datapath2 as little endian.
Figure P-2 shows the example of a 32-bit controller, where:
■ First payload byte (byte 16 in Figure P-1 or Figure P-2, and byte 12 in Figure P-3) is at location (7:0)
■ First address byte (byte 15 in Figure P-1 or Figure P-2, and byte 11 in Figure P-3) is at location (31:24)

Figure P-2 Synopsys Controller Internal Byte Ordering (Four DWORD Header)

1. Including header address and message data bytes on the following interfaces: radm_bypass_addr, radm_trgt1_addr,
client0_tlp_addr, radm_msg_payload, and ven_msg_data.
2. Including payload bytes on the following interfaces: radm_cpl_data, radm_bypass_data, radm_trgt1_data, and
client0_tlp_data.

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Figure P-3 Synopsys Controller Internal Byte Ordering (Three DWORD Header)

Therefore, you do not have to do byte reordering in your application. The controller exactly maps the
address bus to the address header field, and the data to the payload. Taking the example of
client0_tlp_addr, the bits in this address bus map directly to the address bits in the TLP header. The
third and fourth DWORDs of the header are mapped as follows:
■ 3-DWORD header
❑ Third DWORD (bytes 8-11) =client0_tlp_addr[31:0]
❑ Therefore, bits [7:0] are mapped to byte 11 which is the lowest eight bits of the TLP header address.
■ 4-DWORD header
❑ Third DWORD (bytes 8-11) =client0_tlp_addr[63:32]
❑ Fourth DWORD (bytes 12-15) =client0_tlp_addr[31:0]
❑ Therefore, bits [7:0] are mapped to byte 15 which is the lowest eight bits of the TLP header address.
This simple I/O bus bit mapping to TLP header byte mapping also applies to radm_bypass_addr,
radm_trgt1_addr, radm_msg_payload, and ven_msg_data.

Figure P-4 Transmitted 3rd and 4th Message Header Byte Mapping at Interfaces
SII.MESSAGE 31 bytes 12-15
(app _msg_*) 0
0

63 bytes 8-11
VMI
(ven_msg_data) 32
31 bytes 12-15

0
P
XALI0/1/2 Core I
Logic P
63 E
1
32 bytes 8-11

31
0
0

0x0 0
bytes 12-15

Byte 15 is in position [7:0]


4-DW Header ? for 4-DWORD headers

For more information on the format of message headers, see:


■ “Routing of Received Messages” on page 999.
■ “Byte Mapping of Third and Fourth Message Header Dwords At I/O Interfaces” on page 162

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The optional TLP prefixes are implemented as little endian. Using the example of a controller
Note
with just one prefix, this means that client0_tlp_prfx[31:0] has byte 0 (the byte with the
FMT and Type fields) of the prefix in the lower byte position of the DWORD
client0_tlp_prfx[31:0]. That is, FMT =bits 7:5, and Type =bits 4:0

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Introduction to PCIe Switches PCI Express SW Controller Databook

Q
Introduction to PCIe Switches

PCI Express provides a high speed, low-pin count, serial, chip-to-chip interface. PCI Express is a
point-to-point interface, so switches are used for fan-out. Figures Q-1 shows a switch connecting four
endpoints to a processor and chip-set.

Figure Q-1 A PCIe Switch Chip Provides Fan-Out to Multiple Endpoints

You can build a PCI Express switch by adding your switch core logic to the pre-verified, configurable
DesignWare digital and mixed-signal IP.
The following topics are discussed:
■ “Switch Architecture” on page 1008
■ “Digital IP” on page 1010
■ “Mixed Signal IP” on page 1011
■ “Switch Application Logic Summary” on page 1012

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■ “Advanced Switch Feature Summary” on page 1023


■ “Non-Standard Switch Feature Summary” on page 1025

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Q.1 Switch Architecture


A switch typically includes your switch application logic, and configurable PCI Express digital and mixed
signal IP, as shown in Figure Q-2.

Figure Q-2 A PCIe Switch Chip Includes User logic and IP Blocks

The digital IP (closest to the processor) in the Figure Q-2 is the “upstream,” or “upstream facing” switch
port. The other instances (1 to 32) of digital IPs are “downstream” or “downstream facing” ports.
Each of the PCIe links shown can be of different widths. For example, the upper link can be x4 (4 lanes
wide), while the other links are x1. Each unit of width provides 2.5 Gb/second of raw throughput at Gen1
speed, 5.0 Gb/second of raw throughput at Gen2 speed, and 8.0 Bits/second of raw throughput at Gen3
speed.
The switch application logic includes:

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■ Routing, arbitration, and response logic for PCI Express packets


■ Packet buffering
■ Power management
■ Legacy interrupt logic
■ Reset logic

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Q.2 Digital IP
The switch port digital IP as shown in Figure Q-3 implements most of the PCI Express protocol. The IP
includes the physical, link, and transaction protocol layers. The IP performs all the required character and
packet-level encoding, decoding, error checking, automatic retransmission, credit and remote buffer space
checking, packet building and power management.
When you instantiate the IP in your design, an input pin is available to configure the controller as either an
upstream or a downstream port.

Figure Q-3 PCI Express Digital (Switch controller) and Mixed Signal IP (PHY)

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Q.3 Mixed Signal IP


The mixed signal IP in the switch (see Figure Q-3) is a standard PCI Express PHY. These circuits are
designed for a particular manufacturing process and perform PCIe differential line reception/transmission,
serialization/de-serialization, idle detection, receiver detection, clock generation, and power controls.
The DesignWare PHYs also include on-board diagnostics.

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Q.4 Switch Application Logic Summary


This section describes the tasks to be performed by your switch application logic, and the support for those
tasks built into the Synopsys IP.

Q.4.1 Routing, Arbitration, and Response Logic


■ Routing is the steering of packets from one switch port to another. Routing depends on the type and
address fields in received packets. The Synopsys IP disassembles valid packets and presents these
fields to your switch application logic.
■ Arbitration is the selection of packets to be routed.
■ Response logic generates replies (completions) when a received packet targets a register inside the
switch. The register might be located in your switch application logic, or inside one of the downstream
digital IP controllers.
Configuration Packet Routing and Response
Configuration packets are sourced by the system processor and therefore are only received on the upstream
switch port. These packets are used to read or write configuration registers in the digital IP blocks. The
registers can be located in:
■ The upstream switch port
■ Any of the downstream switch ports
■ In digital IP in an endpoint beyond the switch
Configuration packets (“configuration requests”) are routed by bus, device, and function number fields in
the request packet address fields.
■ Bus numbers are assigned by host software (see Figure Q-4). Note that there is a “virtual bus” inside
the switch controller logic.
■ Device numbers are assigned by you when you instantiate your downstream switch ports. This
number is used by your switch core logic when it responds to configuration transactions directed at
the downstream switch ports.
■ The function number is always zero for switch ports. Configuration transactions which pass through
the switch can have non-zero function numbers

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Figure Q-4 An Example of Bus Numbers Assigned by Host Software

What are the most important fields in a configuration request packet?


The configuration transaction is directed to the correct register through fields in the received packet. These
fields are presented to your application logic by the upstream switch port. The important fields of the TLP
are:
■ Type: It specifies whether the request is read or write, and whether the request is directed at the
upstream port registers (Type 0) or at other PCIe ports (Type 1)
■ Address: It gives the bus, device, and register numbers for the request
■ First BE: Byte enables for configuration write requests

How do I handle Type 0 configuration packets in the switch controller logic?


You never receive Type 0 configuration requests in the switch controller logic. These requests are handled
by the upstream port IP controller.

How do I decide if a Type 1 configuration packet is directed at one of the downstream switch ports?
You can examine the bus number in the packet address field. To the host software, the downstream switch
ports appear as devices on a numbered bus. This bus number is assigned by the host software, and is
displayed on the secondary bus number signals of the upstream switch port; you can compare it to the bus
number in the configuration packet.
Note: You must use the upstream port’s secondary bus signals, and not the downstream port’s primary bus
signals, which might be temporarily “out of sync” during bus number configuration.

How do I know to which downstream facing port a configuration packet is directed?

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You can examine the device number in the packet address field. When you build your switch design, you
assign each downstream switch port a unique device number.

How do I direct a configuration request if the bus number does not match the switch’s internal bus number?
Each of the downstream switch ports displays the range of bus numbers to be found “below” that port on
the Secondary and Subordinate Bus Number signals (see Figure Q-5). You can use this range to transmit the
configuration request through the correct downstream port.
Note: If the bus number in the configuration request matches the Secondary Bus Number, then you must
change the configuration request type from 1 to 0 before you transmit the request through the downstream
port.

Figure Q-5 Each Switch Port Displays the Downstream Bus Numbers

How do I respond to a configuration request directed at a downstream port?


For configuration requests targeted to downstream switch ports, the upstream switch port passes the
configuration request to your application on TRGT1. Your application logic must respond to the
configuration request by executing that transaction on the DBI of the downstream port. You then send the
response through the upstream switch port (by generating the completion and presenting it on one of the
upstream port's XALI interfaces), which builds the response (completion) packet from the packet fields you
supply. The fields include:
■ Traffic Class, Attributes, BCM, Lower Address are all 0
■ Requester ID and TAG are copied from the original configuration request
■ Length is one DWORD (4 bytes)
■ Completer ID is copied from the configuration request’s address field (Bus, Device, and Function
number)

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■ Byte count is four


■ Completion Status is zero for a successful completion, and one for unsuccessful (see later for defini-
tion)
■ Data is 32 bits (only for a configuration read request)

What happens if the bus and device numbers of the configuration request do not match any of the internal ports and do
not match the range of any of the downstream ports beyond the switch?
This is a system software error. You should respond with an unsupported request status using the upstream
switch port’s Application Error Reporting signals.
Note: This “error” occurs during system initialization, when the host software checks to see how many
downstream ports are present on the switch.

Do I have to check the function number in the configuration request address?


You should check the function number for configuration requests targeted at one of the downstream switch
ports. The function number in this case should be zero; if not, you should respond as described above with
an unsupported request status.

How does my switch core logic “capture” bus numbers for downstream switch ports?
Whenever your switch core logic executes a configuration register write, you must also write the bus
number from the configuration request into the downstream switch port’s primary bus number register.
This is a simple transaction on the port’s DBI interface.

Memory and I/O Request Packet Routing


Memory and I/O packets are usually routed from one switch port to another. In some cases you have
memory mapped registers in your switch core.
Memory and I/O requests are routed in a manner similar to configuration requests, with the exception of
addresses being used instead of bus and device numbers. Each downstream switch port presents the range
of addresses “below” it on the corresponding signals.
In contrast to configuration packets, memory and I/O packets can be received from any port and sent to any
other port. If the target address does not match the range of addresses later any downstream port, then you
must send the packet to the upstream port.
The upstream switch port rejects any memory or I/O mapped packet which is not in the range of addresses
programmed into its registers.
Note: There might be “holes” in this memory space that can only be detected when your switch core logic
checks the downstream port’s address ranges.
It is possible to have memory or I/O mapped registers in your switch core. When a switch port (usually
upstream) receives such a request, it can handle this for you through the port’s local bus interface (ELBI).
The switch port IP accesses the register, performs the required read or write, and forms and transmits any
required completion packet. This access is restricted to a single DWORD. The memory range for these
registers is specified by a Base Address Register in the switch port.

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Completion Packet Routing


Completion (response) packets are routed by the packet’s Requester ID field, which specifies the bus and
device number of the original Requester. For completions received from a downstream port, the bus and
device numbers might not be in the range of any of the downstream ports. If so, you must send the
completion packet to the upstream port.
On the other hand, you might receive a completion packet from the upstream port whose bus number does
not map into any of the downstream port bus ranges. In that case, you should discard the completion
packet, and report an “unexpected completion” error using the upstream ports application error reporting
signals.
Message Routing
The switch core response to messages depends on the type. This is explained in “Error Messages and Error
Detection” on page 1018 and “Power Management” on page 1019.
Cross Bar /Bus Routing
You also have to choose how to physically transfer packets between switch ports. Two obvious choices are a
common bus or a crossbar. A common bus might be appropriate if all or most traffic is downstream to
upstream, or vice versa.
Preservation of Reserved Packet Bits
Certain packet header bits are marked as "reserved," and therefore are always zero in the current version of
the PCI Express specification. However, a switch is required to transfer these bits without modification. This
is to ensure that your switch design is compatible with future versions of PCIe.

Q.4.2 Packet Buffering


A switch port’s transmit interface might be busy, or unable to transmit a packet immediately, so there is a
requirement to buffer received packet data. Buffering is an advanced topic requiring considerable analysis
and modeling. Three approaches are presented here as examples:
Receive Side Buffering
This is the simplest approach (see Figure Q-6). You use the available built-in receive buffers in each switch
port to store packets when the destination port is busy. You can reduce latency by using cut-through
buffering, which allows the controller to drive a received packet to your application logic before the packet
is fully verified. This allows you to examine the packet’s type and destination address, and immediately
begin sending it to its destination. You can also stop the packet if the destination is busy, or cannot accept
the packet.

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Figure Q-6 Packet Buffering with Digital IP Receive Buffers

■ Advantages: Receive buffering uses the controller’s receive buffers and logic, which includes circuitry
for PCI Express ordering rules. The receive buffers also handle all PCI Express credit (buffer space)
reporting requirements, and arbitrate between packet types and virtual channels. No additional
transmit buffers are required.
The controller transmit clients arbitrate between packet sources for you.
■ Disadvantages: If you halt a packet from an input port, all other packets from that port might be
blocked. If the blocking lasts for a longer time, you might violate PCI Express protocol rules, which
require certain packets to pass others (to avoid deadlock).
Transmit Side Buffering
If you choose transmit buffering, you use packet buffers at each switch port’s transmit client. There is
generally one transmit buffer per packet source at each switch port. Each of these buffers in turn includes a
memory area for each packet type (posted, non-posted, completion).
■ Advantages: If you provide one transmit buffer per packet type per switch port, you can allow smaller
packets to pass blocked larger packets.
In the scheme shown in Figure Q-7, the digital IP performs arbitration between receive packet ports.

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Figure Q-7 Transmit Buffering Prevents Head of Line Blocking

■ Disadvantages: You must add buffering and buffering logic, including logic for PCI Express ordering
rules, and deletion of partially received bad packets.
Switch Core Buffering
Switch core buffering is the most complex, but most powerful packet storage scheme.
You can provide very large amounts of storage, combine on-chip and off-chip memory, and reallocate
memory freely at system startup time to handle different applications.
You can also reallocate storage during packet transfer if you are careful with PCI Express credit
management.

Q.4.3 Error Messages and Error Detection


The following Error Message and Error Detection scenarios can occur:
1. Packet errors detected in your switch logic can be reported through your application error reporting
signals on the upstream facing switch port. Errors detected by the upstream facing port are handled
internally by the port.
2. You might receive error message packets from one of the downstream switch ports. These are easily
recognized because the port disassembles the packet header for you. A bit in the upstream port’s Bridge
Control Register determines whether your switch core logic should drop these error message packets,
or send them to the upstream port.

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3. A downstream port can detect an error condition, and determine (based on internal register settings)
that an error message should be transmitted upstream. A pin for each type of message (correctable,
uncorrectable, fatal) is available.
If one of the error signals is asserted to active state, the switch application logic should construct the
corresponding message TLP, and send it to the upstream port.

Q.4.4 Power Management


For more information, see “Message Generation” on page 153.
PME Turn Off Protocol
When a PME Turn off message is received from the upstream switch port, the core logic should transmit
this message to each downstream port (following posted write ordering rules). At this point, the core logic
must wait for a PME Turn OFF Ack message from the downstream ports. These message are discarded, but
when every downstream port has responded, the upstream port should be signalled to send a PME Turn
Off Ack. These operations are facilitated by switch port signals.
PME Event Messages
These messages are simply passed from downstream ports to the upstream port. It is also possible for your
switch core logic to send a PME message upstream toward the host.
Set Slot Power Limit
The switch core detects configuration writes to the Slot Capabilities register of the downstream ports, and
generate a Set Slot Power Limit message on the corresponding link. This message must also be generated if
a link attached to a downstream port transitions to the link up (DL_Up) state.
Link Power Down States (L2/L3, L1, L0s)
The DesignWare cores automatically execute the PCI Express link power down protocol for you. However,
the switch core logic is required to consolidate and transfer some power state information between
upstream and downstream switch ports:
■ Indicate to the upstream port that all downstream switch ports are in the L1 power down link state
■ Indicate to the upstream port that all downstream switch ports are in the L0s power down link state
■ Indicate to the downstream switch ports that the upstream switch port is in the L0s power down link
state
■ Indicate to the upstream port that a downstream port has started an exit from the L1 power down link
state
D-state Packet Filtering
The host software can program each of the switch ports (actually, the associated link) into one of four
PCI-compatible power states. The programmed power state is indicated on switch port output signals.
In states D1, D2, and D3, only configuration requests can be transmitted downstream; only messages and
completions can be transmitted upstream. Any packets that violate these rules should be discarded, and an
unsupported request is signalled, as previously explained.
Clock Gating
You can use the coreConsultant configuration tool to specify fine grain synthesis clock gating for the digital
IP core. You can also shut off the clock to most of the IP core, when indicated by the clk_req_n output signal.
For more information, see the Databook.

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Legacy Interrupt Messages PCI Express SW Controller Databook

Forward beacon/WAKE# upstream


PCI Express allows downstream devices to request power-up a Beacon signal transmitted on the PCIe
wires, or through the legacy PCI WAKE# wire. The DesignWare PCI Express core supports beacon
detection and transmission in the mixed signal IP, and wake up signals in the digital IP.

Q.4.5 Legacy Interrupt Messages


Legacy interrupt messages are transmitted from PCIe endpoints toward the host. These messages are used
by the switch core to build virtual wires to emulate the INTA through INTD wires used in PCI. Your switch
core logic must keep track of these virtual wires for each downstream port. These downstream virtual wires
are combined into upstream virtual wires in the switch core logic (see Figure Q-8); any change in the state of
the upstream virtual wires is sent to the root complex, through the upstream switch port.
Wires from the downstream ports are “swizzled” before being combined. This is a simple rotation (For
example, INTA => INTB, INTB => INTC) based on the downstream port’s device number. For more
information, see “INTx Interrupt Signaling” section in the PCI Express Base Specification, Revision 4.0, Version
1.0.
You also have to monitor the state of the downstream ports’ links. If any of them go to the DL_Down status,
you have to de-assert the virtual interrupt wires associated with that port.

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PCI Express SW Controller Databook Reset and Link Down

Figure Q-8 Legacy Interrupts are Combined in Your Switch core Logic

Q.4.6 Reset and Link Down


For a switch, the following must cause a hot reset to be sent on all downstream ports:
■ Setting the Secondary Bus Reset field in the Bridge Control register of the upstream port
■ The Data Link Layer of the upstream port reporting DL_Down
■ Receiving a hot reset on the upstream port
The switch controller provide input and output signals to help your switch core perform these operations.

Q.4.7 Packet Arbitration


At each switch port’s transmit interface, you must select from available packets.
■ Selecting from packets in different virtual channels is known as VC arbitration.
■ Selecting from packets in the same virtual channel but from different receive ports is known as port
arbitration.

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Packet Arbitration PCI Express SW Controller Databook

Both of these types of arbitration are described in the PCI Express Base Specification, Revision 4.0, Version 1.0
along with optional and required features.
You might be able to use the built in VC and port arbitration in the switch port.

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PCI Express SW Controller Databook Advanced Switch Feature Summary

Q.5 Advanced Switch Feature Summary


Q.5.1 Digital IP Initialization
Each of the digital IP controller contains configuration register bits that are read-only to host software. You
can configure the reset values of these bits using the coreConsultant GUI.
For greater application flexibility, you might want to load these read-only bits after reset, but before link
communication begins. In this case, you can set the app_ltssm_enable input pin to logic zero at reset time.
When you have written all of the configuration bits from your switch core logic into the digital IP, you
should set the input pin to logic one; at this point link initialization begins.
You should release the upstream port’s app_ltssm_enable pin last, so that your switch is ready to
respond to received configuration requests.

Q.5.2 Poisoned TLPs


Generally, your switch core logic should ignore the poisoned bit in packets, unless the packet is directed at a
switch port, or at the switch core logic. For more information, see the PCI Express Base Specification, Revision
4.0, Version 1.0.

Q.5.3 Virtual Channels and Traffic Classes


Each of your switch port can be configured in the coreConsultant GUI with one to eight virtual channels
(VCs).
A port has a set of receive buffers for each virtual channel. You can choose to implement these in a single
physical memory, if you use the buffer logic in the digital IP. Alternatively, you can implement these in your
switch core logic or in transmit buffers as discussed above. Multiple virtual channels allow higher priority
traffic to pass lower priority traffic.
The digital IP transmit clients presents you with information on the available buffer space at the other end
of the link for each virtual channel. You can use this information plus traffic class and the PCI Express
ordering rules to select packets for transmission.
Each packet has a traffic class field with a value between 0 and 7. System software programs each port with
information to
■ map physical virtual channels to logical virtual channels (VCID)
■ map traffic classes to logical virtual channels
Note: Each link (port) in your system can use a different number of VCs, a different set of VC IDs, and a
different mapping of traffic classes to VC IDs.
When packets from multiple VCs are available for transmission on the same port, the switch must arbitrate
between them. For more information of VC arbitration, see the PCI Express Base Specification, Revision 4.0,
Version 1.0.

Q.5.4 Hot Plug


Downstream switch ports might be associated with a “slot” into which users can plug or unplug cards with
system power on. The PCI Express protocol includes support for this “hot-plug” activity through indicators,
retention latches, interlocks, and attention buttons that are transformed by the switch port into status
register bits and message requests.

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Locked Transactions PCI Express SW Controller Databook

The Synopsys digital IP includes the signals and registers required for hot plug support. The IP also signals
your switch core when a message is required due to a change in hot plug state.

Q.5.5 Locked Transactions


PCI Express switches must support locked transactions (from the upstream port) for compatibility with
legacy software.
To support locked transactions, your switch logic must watch for Successful Completion Lock completion
packets routed from one of the downstream ports to the upstream port. When this occurs, you must block
all packets on virtual channel zero from any of the other downstream ports to the locked downstream port.
The lock is terminated when your core logic receives an Unlock message from the upstream port. This
message should be sent to the locked port (or to all downstream ports). Pins are available for this function.

Q.5.6 Ordering Rules


When you select packets for transmission, you must follow PCI Express ordering rules to preserve Producer
Consumer Ordering as well as to prevent deadlock.
Note: The switch cores indicate the reception of certain messages with dedicated signals. You also have the
configuration option of receiving and decoding these messages yourself on the normal packet interface
(TRGT1). Irrespective of the message reception option chosen, you must take ordering into account. For
example, an interrupt message should always be forwarded upstream after any posted write packets
received before the interrupt.

Q.5.7 Deadlock Prevention


Some additions to the PCI Express specification are under consideration to prevent deadlock. For example,
“Upstream ports (Switches) acceptance of a posted or completion packet must not depend upon the
transmission (on a downstream port) of a non-posted packet within the same virtual channel” (PCI Express
1.1 C13 Errata).

Q.5.8 Bifurcation
You might have downstream signals on your switch chip that you would like to use in a flexible manner, for
example, a set of signals that can be either a single x8 PCIe link, or two independent x4 links. This is known
as bifurcation.

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PCI Express SW Controller Databook Non-Standard Switch Feature Summary

Q.6 Non-Standard Switch Feature Summary


Q.6.1 Non-transparent Switches
In a normal PCI Express system, the host software discovers and configures the entire system by traversing
switches to find all endpoints in the system. Switches that support this are known as “transparent”
switches.
Software knows that a switch port is not the end of the PCI Express hierarchy when it reads the
configuration type (a switch port always shows a Type 1 space).
If you replace one of the downstream switch ports with an endpoint, address translation logic, and another
endpoint, you could connect two different PCI Express hierarchies together.
Note: This is not allowed by the PCI Express specification, but can be made to work when you have some
control of system software.

Q.6.2 Reconfigurable Upstream / Downstream Ports


The DesignWare PCI Express ports can be configured through an input pin as upstream or downstream.
You could take advantage of this to change a downstream port to an upstream port in a fail-safe multi-host
system.
Note: This would require some endpoints in your system to operate as an endpoint or a root port; this is
possible with the DesignWare PCI Express dual mode (DM) core.

Q.6.3 Application in Switches


You can replace one switch port with your own logic to allow inclusion of applications in the switch chip.
To do that, you must have some control of the system software, as this is not legal as per the PCI Express Base
Specification, Revision 4.0, Version 1.0.

For more information on PCIe systems, see “Processing Illegal CFG TLPs and CFG1-CFG0
Hint Conversion in Each PCI Express Port Type” on page 966 in the “Advanced Information:
Advanced Filtering and Routing of TLPs” on page 954.

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Advanced Information: Area, Power Estimates, and RAM Sizes PCI Express SW Controller Databook

R
Advanced Information: Area, Power Esti-

mates, and RAM Sizes

Synopsys provides area and power consumption figures for several example configurations1 of the
controller at the following location:
http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/5.40a/doc/PCIe_Gate_Count_ASIC.pdf
The information provided here is intended to be used only as a guideline. For more information, contact
your Synopsys representative.

Synopsys provides RAM size figures for over 500 configurations of the controller at
https://www.synopsys.com/dw/doc.php/iip/DWC_pcie/5.40a/doc/PCIe_RAM_Size_ASIC.pdf.
Synopsys recommends that you use coreConsultant to generate the RAM size report for your configuration.

1. The configurations used are the default configurations, except for the parameters that are listed in the tables.

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PCI Express SW Controller Databook Area Estimation

R.1 Area Estimation


The area numbers are in kilo-gates. The total cell area is divided by the area of the x1 drive strength NAND
cell in the library to get the gate count numbers. Synthesis results are generated using Design Compiler in
topographical mode. The results do not include RAMs, scan chains, and scan logic.

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Power Estimation PCI Express SW Controller Databook

R.2 Power Estimation


Power values are generated using PrimeTime PX which uses the I/O and flip-flop switching activity file
from an RTL simulation. The analysis complies with standard power analysis practices:
■ Synopsys uses PrimeTime's time-based power analysis on the synthesized netlist.
■ Parasitics are generated by topographical synthesis.
■ Clock gating inserted.
■ Power is measured only during an active traffic window; link training, reset states, registers, and
configuration are included in the power estimation.
■ Typically, the link is busy (not in idle) for more than 90% of time. The test sends 50 128-byte memory
reads and 50 128-bytes memory writes in both directions (200 transactions in total).
Total Power = Switch Power + Leakage Power + Internal Power

Table R-1 Components of Total Power Consumption

Component Description

The switching power of a driving cell is the power dissipated by the charging and discharging of the
Switch Power load capacitance at the output of the cell. The total load capacitance at the output of a driving cell
is the sum of the net and gate capacitances on the driving output.

Leakage power is the power dissipated by a cell when it is not switching, that is, when it is inactive
Leakage Power
or static.

Internal power is the dynamic power dissipated within the boundary of a cell. It includes the power
dissipation due to charging or discharging of capacitances internal to the cell during switching; and
Internal Power
the power dissipation due to the momentary short circuit between the P and N transistors of a gate
while both are turned on.

Table R-2 estimates L0S power as a percentage of L0 power which is Total Power in the reports. The power
consumption in L1.1, L1.2, and L2 is approximately equal to Leakage Power; and L1 power is approximately
equal to L0s power.

Table R-2 L0S Power Estimation as % of L0 Power

Gen Mode

Lanes Gen1 Gen2 Gen3

x1 0-4% 0-4% 1-6%

x2 5-8% 5-8% 7-11%

x4 10-14% 10-14% 15-18%

x8 15-22% 18-27% 20-26%

x16 20-25% 20-30% 25-30%

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PCI Express SW Controller Databook RAM Sizing

R.3 RAM Sizing


The size of the RAMs required is highly dependent on many configuration parameters, the main ones being:
■ Link width (CX_NL)
■ Flow control credits
■ Number of virtual channels (CX_NVC)
■ Maximum payload size (CX_MAX_MTU)

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Advanced Information: Flow Control Credit Calculation PCI Express SW Controller Databook

S
Advanced Information: Flow Control Credit

Calculation

This appendix explains how coreConsultant automatically calculates the default buffer sizes and credits for
each TLP type from the number of lanes, the controller datapath width, the maximum PCIe payload
(CX_MAX_MTU), flow control (FC) update latencies, internal delays, and the PHY latency. For more
information on flow control, see “Flow Control” on page 176.

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PCI Express SW Controller Databook Calculation of Flow Control Latency

S.1 Calculation of Flow Control Latency


The Flow Control update latency is determined by a table lookup based upon values in “UpdateFC
Transmission Latency Guidelines” table of the PCI Express Base Specification, Revision 4.0, Version 1.0. The
specification adds 19, 51, and 115 symbol times (at Gen1, Gen2, and Gen3 speeds respectively) to the flow
control latency value.

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Calculation of Initial Flow Control Credits and Receive Buffer Sizes PCI Express SW Controller Databook

S.2 Calculation of Initial Flow Control Credits and Receive Buffer Sizes
The number of credits advertised should be large enough so that under normal operating conditions,
back-to-back transmission of maximum sized packets (MTUs) is never throttled by a lack of credits. In
determining the optimal credit advertisement, one must consider the following components which are
additive:
1. The fact that the flow control latency timer starts when the last symbol of a TLP is received. Therefore
one maximum sized packet from the local device must be stored in the receive buffer to accumulate
received TLP data.
2. The fact that a flow control update DLLP is not scheduled by the local device until its flow control
latency timer has expired. During the time interval between start and expiry of the flow control latency
timer, the receive buffer must have additional space to accumulate received TLP data.
3. The delays caused by the:
a. Transmission of a TLP by remote device.
b. Processing of TLP by local device.
c. Transmission of FC update by local device.
d. Receiving FC update by remote device.
e. Round trip latency of Re-timer device (if present). This latency is calculated from CX_MAX_RE-
TIMER value.
As an example, the equations to derive posted data credits are as follows where the label in each {}
represents the contribution to each factor detailed in the above list:
depth =(calc_bytes)/(4*CX_NW)/4

calc_bytes =roundUptoNextMTU(data_size{1} + fc_lat_limit{2} + fc_delay_bytes)

fc_lat_limit =data_size *fc_upd_fac

fc_delay_bytes =CX_INTERNAL_DELAY{3.b and 3.c}*CX_NB*CX_NL+


base_internal_delay{3.a and 3.d}*CX_NL + retimer_latency{3.e}*CX_NL
where
■ data_size is the CX_MAX_MTU + 28 that is specified in the PCI Express Base Specification, Revision 4.0,
Version 1.0 as TLP Overhead.
■ fc_upd_fac comes directly from Tables 2-39, 2-40, and 2-41 of the PCI Express Base Specification, Revi-
sion 4.0, Version 1.0.
■ CX_NB is the number of symbols processed at the PIPE interface per lane. For example, the value is two
symbols (16-bit PIPE) for a Gen2 controller running at 250 MHz. For more information, see
“Frequency, Speed, and Width Support” on page 29.
■ CX_NL is the number of lanes of the device.
■ CX_NW is the internal datapath width in DWORDs.
■ base_internal_delay is the sum of the MAC (controller) and PHY delays (Tx and Rx) in the remote
device. To model this, Synopsys uses the PCI Express Base Specification, Revision 4.0, Version 1.0 recom-
mendation of a constant value of 19 symbol times for 2.5 GT/s mode operation, 70 symbol times for
5.0 GT/s mode operation, and 115 symbol times for 8.0 GT/s and 16 GT/s mode operation.
■ CX_INTERNAL_DELAY is the sum of the controller and PHY delays (Tx and Rx) of the local device. This
also includes:

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PCI Express SW Controller Databook Calculation of Initial Flow Control Credits and Receive Buffer Sizes

❑ delays in the local device between receiving the EOT and starting the flow control latency timer.
❑ delays associated from the time the flow control latency timer expires until the controller receives
the flow control packet.
■ The number of bytes calculated is rounded up to next MTU so that the device advertises at least
another full MTU worth of bytes/credits. This helps to reduce credit starvation.
4. Default Non-Posted data credits (RADM_NPQ_DCRD_VC0) should be a fraction of the Non-Posted header
credits because Non-Posted TLPs with data, that is, I/O and Configuration Write Transactions, occur
infrequently (and Atomic Ops occur slightly more frequently).
■ RADM_NPQ_DCRD_VC0 is set to be ½ RADM_NPQ_HCRD_VC0 if Atomic Ops are enabled, or ¼ RADM_N-
PQ_HCRD_VC0 otherwise.
■ Additionally enabled VCs in configurations where AtomicOps are not enabled, do not have I/O or
Configuration Write Transactions, and thus require no data credits (RADM_NPQ_DCRD_VC(1-7)).
It is possible that these equations result in a number of credits (and a resulting receive queue depth) which
is too large for your requirements, or you choose to trade off some temporal drop in performance versus
back pressure on the remote transmitter for receive buffer depth. You can always advertise more than the
default number of credits if you want to continue to offload the wire in the presence of application halting.
Taking the case of Non-Posted header credits (RADM_NPQ_HCRD_VC(0-7)), a conservative approach is used
for the default calculation, and the total amount that can be transmitted during a Flow Control update
window is selected to ensure saturation of the datapath. This however does not take into consideration the
number of Non-Posted requests the application can handle; which is dependent on impacting factors such
as the application response time, the link latency, the credit return latency, and the number of available
Tags.
A more efficient approach can be taken by connecting the amount of Non-Posted header credits to the
number of outstanding requests supported, along with an additional margin to account for packets
currently in flight.
A general rule of thumb is:
■ If the Target Completion Lookup Table (TRGT_CPL_LUT_EN) is full, the controller must have returned
the Non-Posted credits associated with the transactions in the LUT already.
❑ Therefore, in a full LUT situation there are already CX_REMOTE_MAX_TAG Non-Posted requests in
the queues waiting to be offloaded.
■ If the LUT is not full it implies that Non-Posted requests are being completed at a rate sufficient to
prevent LUT full.
❑ In this case it is only necessary to ensure that there are sufficient credits in flight to prevent starva-
tion.
■ Ideally the LUT should run close to full.
❑ Advertising approximately the same number of credits as concurrent requests that can be handled
is a good balance, allowing a few extra credits to account for delays across the link.
■ Applications which do not use the Target Completion Lookup Table are likely to have a similar
concept to CX_REMOTE_MAX_TAG.
For example, it can be shown that for the case of 256-byte requests with a 1us round trip time, 32 tags are
sufficient to keep an X4 link saturated. Adding additional tags or credits only increases RAM sizes and area
without providing any further performance boost.

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Advanced Information: Serialization Queue Almost Full Threshold PCI Express SW Controller Databook

T
Advanced Information: Serialization Queue

Almost Full Threshold

The TLP Serialization Queue resides between Layer3 and the Virtual Channel TLP Receive Queues as
shown in Figure 1. Figure T-1.

Figure T-1 TLP Serialization Queue


Rx Queue
Gen4 4sx16
CPL
NP VC7 RTRGT1
P

Rx PHY Layer 1 Layer 2 Layer 3 Serialization


(Physical) (Link) (Transaction) Queue
CPL RBYP
NP VC0
P

The TLP Serialization Queue is used to consume one or more TLPs from the Transaction Layer (Layer3) in a
single cycle and to send TLPs in series to the application (RTRGT1, RBYP), through the VC TLP Receive
Queues. The number of TLPs to process in a single cycle depends on the TLP length. For example, for a
stream of TLPs with 3 DWORDs of header the maximum number of TLPs to process in a single cycle is 4.
Depending on the mix of TLP length's the amount of data stored in the Serialization Queue can increase or
decrease over time. For more information on how the data stored in the queue increases and decrease
depending on the TLP length, see “Data Rates” on page 1036.
Over time TLPs can accumulate and cause the Serialization Queue to overflow, unless its size is set to the
VC TLP Receive Queue size. However, allowing the Serialization Queue to buffer up this amount of data
has no benefit in terms of TLP throughput at the application interfaces (RTRGT1/RBYP). The application
can offload only one TLP at a time and therefore in the presence of short TLPs cannot keep pace with the
maximum throughput on the wire.
To minimize the RAM footprint, without any performance penalty, you can significantly reduce the
Serialization Queue size and maintain throughput at the application interface.

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PCI Express SW Controller Databook Advanced Information: Serialization Queue Almost Full Threshold

To prevent the reduced Serialization Queue from overflowing the controller takes advantage of the Data
Link layers ACK/NACK protocol. At a certain threshold or water mark, named ALMOST_FULL, the
Serialization Queue masks incoming TLPs and schedules the transmission of a NACK. The NACK sequence
number indicates the last good TLP received. The remote link partner purges all acknowledged TLPs from
its replay buffer and replays all other TLPs stored in the buffer in order. While the incoming TLPs are being
masked the Serialization Queue continues to send TLPs to the VC TLP Receive Queues. Note: halting the
RTRGT1 interface has no impact on the transfer of these TLPs. When the amount of data stored in the queue
drops below ALMOST_FULL the Serialization Queue unmasks incoming TLPs enabling the replayed TLPs to
be stored in the queue.
The following topics are discussed:
■ “Serialization Queue Almost Full Threshold”
■ “Serialization Queue Input and Output Data Rates” on page 1043

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Serialization Queue Almost Full Threshold PCI Express SW Controller Databook

T.1 Serialization Queue Almost Full Threshold


The almost full threshold (ALMOST_FULL) is determined by:
■ The maximum output rate possible at the output of the serialization queue, and
■ The round trip delay starting from the request to generate the NACK to the reception of the first
replayed TLP.
ALMOST_FULL equates to the number of QDWORDs required to sustain the maximum TLP output rate for a
given NACK request to first replayed TLP round trip latency. During this period TLPs are not written to the
queue. The accumulated TLPs present in the queue are assumed to be read at the maximum output rate. To
avoid a loss in performance the queue must not underflow.

T.1.1 Data Rates


The Transaction Layer (Layer3) receives TLPs at a rate of 16 DWORDs per cycle. These DWORDs are
extracted, packed into QDWORDs and sent to the Serialization Queue. The maximum number of
QDWORDs that can be sent in a single cycle is 7. The Serialization Queue sends TLPs to the application at a
rate of one TLP per cycle.
Figure T-2 and Figure T-3 describe how streams of TLPs, with and without prefixes, accumulate in the
Serialization Queue. The fastest accumulation rate without TLP Prefixes occurs for a TLP stream of 3 Header
DWORDs and 1 Data DWORD. The input data rate is 5.33 QDWORDs/cycle; the output data rate is 2
QDWORDs/cycle. The fastest accumulation rate with TLP Prefixes occurs for a TLP stream of 1 Prefix
DWORD, 3 Header DWORDs and 1 Data DWORD. The input data rate is 6.86 QDWORDs/cycle; the output
data rate is 3 QDWORDs/cycle.

Figure T-2 Serialization Queue Accumulation Rate = 3.33 QDWORDs/cycle (No Prefix)
DW15 d i h
h i h
h d i
h h i
i h d QDW7H/D D
i h h QDW6H/D H H D QDW3D

d i h QDW5H/D D QDW2D

h i h QDW4H/D H D H Serialization QDW1D


/CX_NW Layer 3
h d i QDW3H/D D Queue QDW0D D D D D D
h h i QDW2H/D D H H QDWH H H H H H
i h d QDW1H/D D time

i h h QDW0H/D H H
d i h time
Notes:
h i h (a) Lower Case lettering implies DWORDs (DW)
h d i (b) Upper case lettering implies QDWORDs (QDW)
DW0 h h i (c) p/P = Prefix, h/H = Header, d/D=Data, i=Idle
(d) CX_NW expresses the width of the data path in DWORDs
time

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PCI Express SW Controller Databook Data Rates

Figure T-3 Serialization Queue Accumulation Rate = ~3.86 QDWORDs/cycle (1 Prefix)


DW15 d h
h h
h
h
p QDW7P/H/D H
i QDW6P/H/D P QDW3D

i QDW5P/H/D D QDW2D

d QDW4P/H/D H Serialization QDW1D


/CX_NW Layer 3
i h QDW3P/H/D Queue QDW0D D D D
i h QDW2P/H/D H P QDWH H H H H
h h QDW1P/H/D P D N*PRFXP P P P
h p QDW0P/H/D D H time

h i time

p i Notes:
i d (a) Lower Case lettering implies DWORDs (DW)
(b) Upper case lettering implies QDWORDs (QDW)
DW0 i h (c) p/P = Prefix, h/H = Header, d/D=Data, i=Idle
(d) CX_NW expresses the width of the data path in DWORDs
time

Figure T-4 and Figure T-5 describe how streams of TLPs, with and without prefixes, dissipate in the
Serialization Queue. The fastest TLP dissipation rate without prefixes occurs for a stream TLPs consisting of
3 Header DWORDs and 16 Data DWORDs. The input data rate is 3.81 QDWORDs/cycle; the output data
rate is 5 QDWORDs/cycle. The fastest TLP dissipation rate with TLP Prefixes occurs for a TLP stream of 7
Prefix DWORDs, 3 Header DWORDs and 16 Data DWORDs. The input data rate is 4 QDWORDs/cycle; the
output data rate is 7 QDWORDs/cycle.

Figure T-4 Serialization Queue Dissipation Rate = 1.19 QDWORDs/cycle (No Prefix)
DW15 d d
d d
d d
d d
d d QDW7H/D

d d QDW6H/D D D QDW3D D D
i d d QDW5H/D D QDW2D D D
i d d QDW4H/D H D Serialization QDW1D D D
/CX_NW Layer 3
d h d QDW3H/D Queue QDW0D D D
d h d QDW2H/D D D QDWH H H
d h d QDW1H/D time

d i d QDW0H/D D D H
d i d time
Notes:
d d h
(a) Lower Case lettering implies DWORDs (DW)
d d h (b) Upper case lettering implies QDWORDs (QDW)
DW0 d d h (c) p/P = Prefix, h/H = Header, d/D=Data, i=Idle
time (d) CX_NW expresses the width of the data path in DWORDs

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Figure T-5 Serialization Queue Dissipation Rate = 3 QDWORDs/cycle (7 Prefixes)


DW15 d p d
d p d
d p d
d p d
d i d QDW7P/H/D P
d i d QDW6P/H/D D D QDW3D D D
d d h QDW5P/H/D QDW2D D D
d d h QDW4P/H/D D D H Serialization QDW1D D D
/CX_NW Layer 3
d d h QDW3P/H/D H Queue QDW0D D D
d d p QDW2P/H/D D P QDWH H H
h d p QDW1P/H/D P P
N*PRFXP
h d p QDW0P/H/D P D P P P
h d p time time

p d p Notes:
p d p (a) Lower Case lettering implies DWORDs (DW)
(b) Upper case lettering implies QDWORDs (QDW)
DW0 p d p (c) p/P = Prefix, h/H = Header, d/D=Data, i=Idle
(d) CX_NW expresses the width of the data path in DWORDs
time

The QDWORD input and output rate is determined by the following equations:
Input Rate (QDWORDs per cycle)
= (Number of TLP per cycle)*(Number of QDWORDs per TLP)
= NW/(PDW + HDW + DDW + TLP Overhead)*(PQDW + HQDW + DQDW)
Output Rate (QDWORDs per cycle)
= (Tota Number of TLP QWORDs)/(Number of cycles to offload the TLP data QDWORDs)
= (PQDW + HQDW + DQDW)/ ROUNDUP(DQDW/(NW/4))
Where:
■ NW is the width of the data path in DWORDs
■ PDW is the TLP prefix length in DWORDs
■ HDW is the TLP header length in DWORDs
■ DDW is the TLP data length in DWORDs
■ PQDW is the TLP prefix length in QDWORDs
■ HQDW is the TLP header length in QDWORDs
■ DQDW is the TLP data length in QDWORDs, and
■ TLP Overhead is the TLP overhead stripped by the lower layers (Layer1 tokens and Layer2 LCRC).
For example, a TLP stream of 1 prefix DWORD, 3 header DWORDs, and 1 data DWORD results in the
following input and output QDWORD rates:
Input Rate
= 16/(1+3+1+2)*(1+1+1)
= 6.86 QDWORDs/cycle
Output Rate
= (1+1+1)/1
= 3 QDWORDs/cycle

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PCI Express SW Controller Databook NACK Request to Replayed TLP Latency

A TLP stream consisting of 3 header DWORDs and 16 data DWORDs results in the following input and
output QDWORD rates:
Input Rate
= 16/(3+16+2)*(1+4)
= 3.81 QDWORDs/cycle
Output Rate
= (1+4)/1
= 5 QDWORDs/cycle
The increase or decrease in the number of QDWORDs stored in the queue can be expressed by the following
equations:
Constant = (PDW + HDW + DDW + 2)% CX_NW =0
Increase = (PDW + HDW + DDW + 2)% CX_NW >0 and <=(PDW + HDW + 2)
Decrease = (PDW + HDW + DDW + 2)% CX_NW >(PDW + HDW + 2) or (DDW =0)
For a table of input and output data rates for various TLP lengths see “Serialization Queue Input and
Output Data Rates” on page 1043.
The ALMOST_FULL threshold is reached for any given stream of TLPs such that over time the input rate is
greater than the output rate.
Note: These formulae are based on a stream of fixed length TLPs.

T.1.2 NACK Request to Replayed TLP Latency


The Serialization Queue output data rate must be sustained from the time the NACK (high priority DLLP) is
requested to the first replayed TLP at the input the Serialization Queue. The NACK is requested when
ALMOST_FULL is reached.
The round trip time from the NACK request to the first replayed TLP at the input to the Serialization Queue
depends on the following latencies:
A. The Local Layer2 NACK request to PIPE latency
B. The Local PHY TX latency
C. The Link Retimer latency, Local to Remote
D. The Remote PHY Rx latency
E. The Remote NACK DLLP to replay request latency
F. The Remote replay request to PIPE latency
G. The Remote PHY TX latency
H. The Link Retimer latency, Remote to Local
I. The Local PHY Rx latency
J. The Local PIPE to Serialization Queue latency

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Figure T-6 NACK Request to First Replayed TLP at Input to Serialization Queue

CX_PHY_TX_DELAY_PHY CX_RETIMER_LATENCY / 2 CX_PHY_RX_DELAY_PHY

F G H I J

TLP’s

Layer 2

Replay Serialization TLP’s


Layer 1 PHY Retimer Retimer PHY Layer 1 Layer 2 Layer 3
Buffer Queue

DLLP’s

E D C B A
Remote Device
Local Device
CX_PHY_RX_DELAY_PHY CX_RETIMER_LATENCY / 2 CX_PHY_TX_DELAY_PHY

The round trip time from transmission of the Nack to the first replayed TLP at the input to the serialization queue depends on the
following latencies:
A Local Layer2 NACK request to PIPE latency: This is known by design and is set to 9 core clock cycles.

B
The Local PHY TX latency (CX_PHY_TX_DELAY_PHY): This is the worst case delay from the PIPE interface to the TX PHY serial
pins, expressed in PIPE clock cycles. It is specified by your PHY provider and passed at build time through coreConsultant.

C
Local to Remote Link Retimer latency (CX_RETIMER_LATENCY/2): This is the worst case delay through the Retimers, expressed
in symbols times. Its value defaults to the maximum delay specified in the PCIe Base Specification.

D
Remote PHY Rx latency: This is the worst case delay from the Rx PHY serial pins to the PIPE interface, expressed in PIPE clock
cycles. It is matched to the Local PHY Rx latency, CX_PHY_RX_DELAY_PHY.

E
Remote NACK DLLP to replay request latency: This is extrapolated from the Local NACK DLLP to replay request latency. It is known
by design and has a value of 10 core clock cycles.

F
Remote replay request to PIPE latency: This is extrapolated from the Local Remote replay request to PIPE latency. It is known by
design and has a maximum value of 28 core clock cycles.

G
Remote PHY TX latency: This is the worst case delay from the PIPE interface to the TX PHY serial pins, expressed in PIPE clock cycles.
It is matched to the Local PHY TX latency, CX_PHY_TX_DELAY_PHY.

H
Remote to Local Link Retimer latency (CX_RETIMER_LATENCY/2): This is the worst case delay through the Retimers, expressed
in symbols times. Its value defaults to the maximum delay specified in the PCIe Base Specification.

I
Local PHY Rx latency (CX_PHY_RX_DELAY_PHY): This is the worst case delay from the Rx PHY serial pins to the PIPE interface,
expressed in PIPE clock cycles. It is specified by your PHY provider and passed at build time through coreConsultant.
J Local PIPE to Serialization Queue latency: This is known by design and has maximum value of 16 core clock cycles.

In summary, the latency from the transmission of the NACK, to the first replayed TLP at the input, to the
serialization queue in controller clock cycles is:
NACK_TO_RPLYD_TLP =
(2 *(Core Clock to PIPE Clock Frequency Ratio
*(CX_PHY_TX_DELAY_PHY + CX_PHY_RX_DELAY_PHY)))
+(Symbol Time * CX_RETIMER_LATENCY/Core Clock Period) + 68
Note: 2s (16-bit) and 4s (32-bit) Controller-PHY Dynamic Frequency combinations are supported. For 2s the
Controller Clock to PIPE Clock frequency ratio is 1:2, for 4s it is 1:1.

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PCI Express SW Controller Databook Almost Full Threshold Calculation

T.1.3 Almost Full Threshold Calculation


ALMOST_FULL is calculated for the worst case scenario where the threshold is reached and the TLPs stored
in queue are read at the maximum QDWORD output rate.
The queue size, expressed in QDWORDs, is equal to the latency from the NACK request to the first
replayed TLP at the input the Serialization Queue times the maximum QDWORD output rate.
ALMOST_FULL(QWORDS) = NACK_TO_RPLYD_TLP * Maximum QDWORD Output Rate
You can configure the PHY transmit latency, CX_PHY_TX_DELAY_PHY, the PHY receive latency,
CX_PHY_RX_DELAY_PHY, and the round trip Retimer latency, CX_RETIMER_LATENCY through
coreConsultant. For example, if the Controller-PHY PIPE IO width is 4 Bytes, that is, Controller clock =PIPE
Clock, then setting CX_PHY_TX_DELAY_PHY to 12, CX_PHY_RX_DELAY_PHY to 28, and
CX_RETIMER_LATENCY to 528 Symbol Times (Gen4 speed, SRIS enabled, MaxPayloadSize =256Bytes, 2
retimers) gives:
ALMOST_FULL(QWORDS) = 280 * Maximum QDWORD Output Rate
The maximum output rate depends on the number of TLP prefixes supported. Without TLP prefixes the
maximum output rate is 5 QDWORDs/cycle. If TLP prefixes are supported, and the number of prefixes
range from 1 to 4, then the maximum output rate is 6 QDWORDs/cycle; if the number of prefixes range
from 5 to 7, then the maximum output rate is 7 QDWORDs/cycle. Table T-1 summarizes the auto calculated
almost full threshold depending on the number of supported TLP prefixes.

Table T-1 Auto-calculated Almost Full Threshold

Number of Prefixes Maximum Output Rate ALMOST_FULL ALMOST_FULL


NPRFX (QDWORDs/cycle) (QDWORDs) (Bytes)

0 5 1400 22400

1 to 4 6 1680 26880

4 to 7 7 1960 31360

You can adjust the auto-calculated almost full threshold through the coreConsultant "Receive Serialization
Queue" configuration page as shown in Figure T-7.

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Figure T-7 Receive Serialization Queue Configuration Page in coreConsultant

ALMOST_FULL or Serialization Queue size is presented as a percentage of the available TLP buffer space,
that is, as a percentage of the configured TLP Receive Queue size. The auto-calculated value is the optimal
threshold to ensure TLPs are sent to the application without impacting performance, and is the default
value. To increase ALMOST_FULL, you must tick the "Enable Receive Serialization Size Configuration" tick
box prior to modifying its value.
Note: If the wire data rate is greater than the Serialization Queue output data rate then increasing the almost
full threshold only serves to extend the time before the NACK is sent. If the wire data rate is not sustained
over time, then increasing the almost full threshold can reduce the transmission frequency of the NACKs.
Refer to “Serialization Queue Input and Output Data Rates” on page 1043 for the number of fixed length
TLPs required to reach ALMOST_FULL, for a given NACK request to replayed TLP latency.
Note: To prevent the controller from sending overflow prevention related NACKs you must set
ALMOST_FULL to 100% of the configured TLP Receive Queue size.

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PCI Express SW Controller Databook Serialization Queue Input and Output Data Rates

T.2 Serialization Queue Input and Output Data Rates


Figure T-8 shows the input and output QDWORD data rates for streams of TLPs of various DWORD
lengths (no TLP prefix). For simplicity DLLPs are not considered in the data stream. DLLPs reduce the TLP
input rate, resulting in a small increase in the number of back-to-back TLPs required to reach ALMOST_FULL.
■ PDW is the TLP prefix length expressed in DWORDs
■ HDW is the TLP header length expressed in DWORDs
■ DDWis the TLP data length expressed in DWORDs
■ PQDW is the TLP prefix length expressed in QDWORDs
■ HQDW is the TLP header length expressed in QDWORDs
■ DQDW is the TLP data length expressed in QDWORDs
■ li is the TLP input data rate expressed in QDWORDs/cycle
■ lo is the TLP output data rate expressed in QDWORDs/cycle
■ li - lo tracks the TLP accumulation/dissipation rate in QDWORDs/cycle
Note: In Figure T-8, Figure T-9, and Figure T-10, Num of TLPs to reach ALMOST_FULL column is
calculated based on the PHY transmit and receive latencies specified in “Almost Full Threshold
Calculation” on page 1041, that is, CX_PHY_TX_DELAY_PHY =12 PIPE clock cycles, CX_PHY_RX_DELAY_PHY
=28 PIPE clock cycles. In addition, the PCIe link includes 2 retimers.The data is shown is for information
purposes only.

Figure T-8 Serialization Queue Input and Output Data Rates (No Prefixes)

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Figure T-9 shows the input and output QDWORD data rates for streams of TLPs of various DWORD
lengths, with 1 prefix supported.

Figure T-9 Serialization Queue Input and Output Data Rates (1 Prefix)

Figure T-10 shows the input and output QDWORD data rates for streams of TLPs of various DWORD
lengths, with 7 prefixes supported.

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Figure T-10 Serialization Queue Input and Output Data Rates (7 Prefixes)

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Internal Parameter Descriptions PCI Express SW Controller Databook

U
Internal Parameter Descriptions

Provides a description of the internal parameters that might be indirectly referenced in expressions in the
Signals, Parameters, or Registers chapters. These parameters are not visible in the coreConsultant GUI and
most of them are derived automatically from visible parameters.You must not set any of these parameters
directly.
Some expressions might refer to TCL functions or procedures (sometimes identified as function_of) that
coreConsultant uses to make calculations. The exact formula used by these TCL functions is not provided in
this chapter. However, when you configure the core in coreConsultant, all TCL functions and parameters
are evaluated completely; and the resulting values are displayed where appropriate in the coreConsultant
GUI reports.
Table U-1 Internal Parameters

Parameter Name Equals To

ACS_CTRL_VEC_WD {[function_of: ACS_CTRL_VEC_WD]}

ACS_CTRL_VEC_WD_0 ((CX_ACS_P2P_EGRESS_CTRL_0) *
((CX_ACS_EGRESS_CTRL_SIZE_0 == 0) ? 256 :
CX_ACS_EGRESS_CTRL_SIZE_0))

ADDR_TRANSLATION_SUPPORT_EN (CX_INTERNAL_ATU_ENABLE)

AHB_ENABLED AHB_POPULATED

AHB_POPULATED AMBA_INTERFACE ==1

AMBA_DECOMPOSER_DEF_DEPTH_FACTOR 2

AMBA_POPULATED AMBA_INTERFACE ! =0

APP_CRD_WD CX_NW_GTR_4_VALUE ? CX_LOGBASE2(NW/4 +


1)*CX_NVC : CX_NVC

APP_PAR_ERR_OUT_EN (CX_RAS_EN)

ARC_WIDTH {[function_of: CX_DL_NB CX_NL]}

ATOMIC_ROUTING_SUP CX_ATOMIC_ROUTING_EN

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Parameter Name Equals To

ATS_RX_ENABLE CX_ATS_ENABLE && (CC_DEVICE_TYPE ==CC_RC ||


CC_DEVICE_TYPE ==CC_DM || AMBA_POPULATED)

ATS_RX_ENABLE_VALUE ATS_RX_ENABLE

ATS_TX_ENABLE CX_ATS_ENABLE && (CC_DEVICE_TYPE ==CC_EP ||


CC_DEVICE_TYPE ==CC_DM || AMBA_POPULATED)

ATTR_WD FLT_Q_ATTR_WIDTH

ATU_IN_MIN1 ATU_IN_REGIONS > 0 ? ATU_IN_REGIONS : 1

ATU_IN_REGIONS CX_ATU_NUM_INBOUND_REGIONS

ATU_IN_SINGLE_TRGT_ADDR_ENABLE CX_INTERNAL_ATU_ENABLE

AXI_POPULATED ((AMBA_INTERFACE ==2) || (AMBA_INTERFACE ==3))

AXI_RADM_SEG_BUF_ENABLE AXI_POPULATED && RADM_SEG_BUF

BUSNUM_WD CX_BUSNUM_WD

CC_AHB_SNUM_MASTERS (AHB_POPULATED && SLAVE_POPULATED &&


SPLIT_SUPPORT ? CC_SLV_NUM_MASTERS : 1)

CC_CORE_DATA_BUS_WD (CX_RAS_EN ==1) ?


((PCIE_CORE_DATA_BUS_WD/CX_RAS_PROT_RANGE)
+ PCIE_CORE_DATA_BUS_WD) :
PCIE_CORE_DATA_BUS_WD

CC_DM 2

CC_DMA_ENABLE_VALUE CC_DMA_ENABLE

CC_DTIM_DATA_WD 160

CC_DTIM_INTF_PROT_WD CX_RAS_EN ==1 ? CC_DTIM_INTF_WD -


CC_DTIM_RAW_INTF_WD : 0

CC_DTIM_INTF_WD CX_RASDP_EN ==1 ? [function_of:


CC_DTIM_RAW_INTF_WD CX_RAS_PROT_RANGE] +
CC_DTIM_RAW_INTF_WD : CC_DTIM_RAW_INTF_WD

CC_DTIM_NUM_BYTES_PER_BEAT (CC_DTIM_DATA_WD/8)

CC_DTIM_RAW_INTF_WD CC_DTIM_DATA_WD +
CC_DTIM_NUM_BYTES_PER_BEAT + 1

CC_EP 0

CC_GENERIC_PHY 8

CC_HP_MASTER 0

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Parameter Name Equals To

CC_IN64 {(AMBA_INTERFACE ! = 0) ?
(MASTER_BUS_ADDR_WIDTH > 32) :
(FLT_Q_ADDR_WIDTH > 32)}

CCIX_ESM_SUPPORT_VALUE CX_CCIX_ESM_SUPPORT

CCIX_HDR_PROT_WD CX_RASDP_CCIX_HDR_PROT_WD

CCIX_HDR_WD CX_RASDP_CCIX_HDR_WD

CCIX_INTERFACE_ENABLE_VALUE CX_CCIX_INTERFACE_ENABLE

CCIX_VC_RESOURCE (CX_NVC-1)

CC_LEGACY_DMA_MAP 1

CC_LINK_TIMEOUT_ENABLE_DEFAULT (CC_DEVICE_TYPE ==CC_EP) ? 1 : 0

CC_LINK_TIMEOUT_PERIOD_DEFAULT 50

CC_MAX_MSTR_TAGS (AXI_POPULATED ? CC_MAX_MSTR_TAGS_AXI :


CC_MAX_MSTR_TAGS_AHB)

CC_MAX_MSTR_TAGS_AHB 1

CC_MSTR_BUS_DATA_WIDTH (CX_RAS_EN ==1) ?


((MASTER_BUS_DATA_WIDTH/CX_RAS_PROT_RANGE)
+ MASTER_BUS_DATA_WIDTH) :
MASTER_BUS_DATA_WIDTH

CC_MSTR_NW (MASTER_BUS_DATA_WIDTH/32)

CC_MSTR_RD_REQ_SIZE (CC_MSTR_BURST_LEN*MASTER_BUS_DATA_WIDTH/8
)

CC_RC 1

CC_SLV_BUS_DATA_WIDTH (CX_RAS_EN ==1) ?


((SLAVE_BUS_DATA_WIDTH/CX_RAS_PROT_RANGE) +
SLAVE_BUS_DATA_WIDTH):SLAVE_BUS_DATA_WIDTH

CC_SW 3

CC_UNROLL_EN (CC_DMA_ENABLE || CX_INTERNAL_ATU_ENABLE) && !


AHB_POPULATED

CC_UNROLL_ENABLE ((CC_UNROLL_EN ==0) ? 0: 1)

C_G1_SYNC_SI ( ! CM_HSGEAR1_SPEED) ? 0 :
(MPHY_C_HSG1_SYNC_LENGTH > 31) ?
2^(MPHY_C_HSG1_SYNC_LENGTH-32) :
MPHY_C_HSG1_SYNC_LENGTH

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Parameter Name Equals To

C_G2_SYNC_SI ( ! CM_HSGEAR2_SPEED) ? 0 :
(MPHY_C_HSG2_SYNC_LENGTH > 31) ?
2^(MPHY_C_HSG2_SYNC_LENGTH-32) :
MPHY_C_HSG2_SYNC_LENGTH

C_G3_SYNC_SI ( ! CM_HSGEAR3_SPEED) ? 0 :
(MPHY_C_HSG3_SYNC_LENGTH > 31) ?
2^(MPHY_C_HSG3_SYNC_LENGTH-32) :
MPHY_C_HSG3_SYNC_LENGTH

CLIENT1_POPULATED 1

CLIENT_HDR_PROT_WD {(CX_RASDP_EN ==1) ? [function_of: CLIENT_HDR_WD


CX_RAS_PROT_RANGE RAS_BASE_PROT_WD ]:0 }

CLIENT_HDR_WD 132 + CX_TAG_SIZE + CX_IDO_ENABLE_VALUE +


CX_NFUNC_WD + CX_LN_VALUE +
((CX_NVFUNC_EWD + 1)*CX_SRIOV_ENABLE_VALUE)
+ (CX_TPH_ENABLE_VALUE*11)

CM_GEAR1_NB ((CM_FREQ == 1) ? 1 : (CM_FREQ == 2) ? 2 : 4 )

CM_HSGEAR1_SPEED 1

CM_HSGEAR2_SPEED CM_GEAR2_MODE ! = SPEED_DISABLED

CM_HSGEAR3_SPEED CM_GEAR3_MODE ! = SPEED_DISABLED

CM_MAX_SYNC_TIME (CM_MAX_SYNC_TIME_CMN >


CM_MAX_SYNC_TIME_NONCMN) ?
CM_MAX_SYNC_TIME_CMN :
CM_MAX_SYNC_TIME_NONCMN

CM_MAX_SYNC_TIME_CMN (C_G3_SYNC_SI + G3_PREPARE_SI >


LONGER_LENGTH_C_G1_G2) ? C_G3_SYNC_SI +
G3_PREPARE_SI : LONGER_LENGTH_C_G1_G2

CM_MAX_SYNC_TIME_D4 CM_MAX_SYNC_TIME/4

CM_MAX_SYNC_TIME_NONCMN (NC_G3_SYNC_SI + G3_PREPARE_SI >


LONGER_LENGTH_NC_G1_G2) ? NC_G3_SYNC_SI +
G3_PREPARE_SI : LONGER_LENGTH_NC_G1_G2

CM_MPCIE_INTERNAL_DELAY CM_PHY_TX_DELAY_MAC + CM_PHY_TX_DELAY_PHY


+ CM_PHY_RX_DELAY_MAC +
CM_PHY_RX_DELAY_PHY +
CM_RMMI_RETIMING_MAC_PHY +
CM_RMMI_RETIMING_PHY_MAC

CM_NB ((CM_GEAR3_MODE == SPEED_DW) ? (CM_GEAR1_NB


* 4) : (CM_GEAR2_MODE == SPEED_DW) ?
(CM_GEAR1_NB * 2) : CM_GEAR1_NB)

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Parameter Name Equals To

CM_PHY_RX_DELAY_MAC ((CX_MPCIE_ENABLE && (CM_NB == 1)) ? 34


:(CX_MPCIE_ENABLE && (CM_NB == 2)) ? 16 : 9 )

CM_PHY_TX_DELAY_MAC 5

CM_RXNL (CX_S_CPCIE_MODE) ? CX_NL : CM_RXNL_GUI

CM_TXNL (CX_S_CPCIE_MODE) ? CX_NL : CM_TXNL_GUI

CUT_THROUGH_INVOLVED (RADM_P_QMODE_VC0 ==2 || RADM_NP_QMODE_VC0


==2 || RADM_CPL_QMODE_VC0 ==2 ||
RADM_P_QMODE_VC1 ==2 || RADM_NP_QMODE_VC1
==2 || RADM_CPL_QMODE_VC1 ==2 ||
RADM_P_QMODE_VC2 ==2 || RADM_NP_QMODE_VC2
==2 || RADM_CPL_QMODE_VC2 ==2 ||
RADM_P_QMODE_VC3 ==2 || RADM_NP_QMODE_VC3
==2 || RADM_CPL_QMODE_VC3 ==2 ||
RADM_P_QMODE_VC4 ==2 || RADM_NP_QMODE_VC4
==2 || RADM_CPL_QMODE_VC4 ==2 ||
RADM_P_QMODE_VC5 ==2 || RADM_NP_QMODE_VC5
==2 || RADM_CPL_QMODE_VC5 ==2 ||
RADM_P_QMODE_VC6 ==2 || RADM_NP_QMODE_VC6
==2 || RADM_CPL_QMODE_VC6 ==2 ||
RADM_P_QMODE_VC7 ==2 || RADM_NP_QMODE_VC7
==2 || RADM_CPL_QMODE_VC7 ==2)

CX_10BITS_TAG_REQ (CX_10BITS_TAG == 1 && CX_MAX_TAG > 255) ? 1: 0

CX_10BITS_TAG_REQ_VALUE (CX_10BITS_TAG_REQ == 1) ? 1: 0

CX_10BITS_TAG_VALUE (CX_10BITS_TAG == 1) ? 1: 0

CX_2ND_SPEED (CX_GEN2_SPEED || CM_HSGEAR2_SPEED)

CX_5GTS_SPEED ((CX_CPCIE_ENABLE && CX_GEN2_SPEED) ||


(CX_MPCIE_ENABLE && CM_HSGEAR3_SPEED))

CX_ADM_ADAPTOR_ENABLE (CX_PL_MODE == 1)

CX_ADM_ADAPTOR_RADM_PIPE_STAGES 16

CX_ADM_RFC_WD CX_RX_NDLLP + (32*CX_RX_NDLLP) + CX_NVC

CX_ADM_TLH_WD 10 + CX_TX_HW_W_PAR + CX_DW_W_PAR + CX_NW +


((CX_TLP_PREFIX_ENABLE ==1) ? (32*CX_NPRFX + 15)
: 0) + ((CX_P2P_ENABLE_VALUE == 1) ? 1 : 0)

CX_AMBA_ARI_OR_IOV (AMBA_INTERFACE ! = 0 && (CX_SRIOV_ENABLE ||


CX_ARI_ENABLE))

CX_APP_L1SUB_CONTROL (CX_L1_SUBSTATES_ENABLE ==1) ? 1 : 0

CX_ARI_FWD_ENABLE CX_ARI_FWD_CAP

CX_ATU_CTRL_EN CX_INTERNAL_ATU_ENABLE

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Parameter Name Equals To

CX_ATU_INCR_RGN_SIZE ((AMBA_INTERFACE ! = 0) ?
((CX_ATU_MAX_REGION_SIZE>0) &&
AMBA_INTERFACE ! = 1 &&
SLAVE_BUS_ADDR_WIDTH>32):CX_ATU_MAX_REGION
_SIZE>0)

CX_ATU_SLOC_CBUF ATU_IN_SINGLE_TRGT_ADDR_ENABLE

CX_BAR1_RESIZABLE_0 (BAR1_SIZING_SCHEME_0 ==2) ? 1 : 0

CX_BAR2_RESIZABLE_0 (BAR2_SIZING_SCHEME_0 ==2) ? 1 : 0

CX_BAR3_RESIZABLE_0 (BAR3_SIZING_SCHEME_0 ==2) ? 1 : 0

CX_BAR4_RESIZABLE_0 (BAR4_SIZING_SCHEME_0 ==2) ? 1 : 0

CX_BAR5_RESIZABLE_0 (BAR5_SIZING_SCHEME_0 ==2) ? 1 : 0

CX_BUSNUM_WD (MULTI_DEVICE_AND_BUS_PER_FUNC_EN == 0) ? 8 :
(CX_NFUNC*8)

CX_CALC_DDEPTH {(CX_ADM_ADAPTOR_ENABLE ==1) ? [function_of:


CX_NW CX_MAX_MTU
CX_ADM_ADAPTOR_RADM_PIPE_STAGES] :
[pcie_cc_gen_calc_ddepth CX_DL_NB CX_NL
CX_MAX_MTU ! CX_ECRC_STRIP_ENABLE
CX_INTERNAL_DELAY CX_GEN5_SPEED
CX_GEN4_SPEED CX_GEN3_SPEED CX_2ND_SPEED
FC_SCALE_EN CX_RETIMER_LATENCY]}

CX_CALC_HDEPTH {(CX_ADM_ADAPTOR_ENABLE ==1) ? [function_of:


CX_NW CX_ADM_ADAPTOR_RADM_PIPE_STAGES] :
[pcie_cc_gen_calc_hdepth CX_DL_NB CX_NL
CX_MAX_MTU ! CX_ECRC_STRIP_ENABLE
CX_INTERNAL_DELAY CX_RADM_MAXPKT
CX_GEN5_SPEED CX_GEN4_SPEED CX_GEN3_SPEED
CX_2ND_SPEED FC_SCALE_EN
CX_RETIMER_LATENCY]}

CX_CCIX_RX_WD (CX_CCIX_INTERFACE_ENABLE) ? 1 : 0

CX_CDM_DIAG_STATUS_BUS_WD (3 + 32 + 32 + CX_NFUNC + 4 + CX_NFUNC +


(9*CX_NFUNC) + CX_NVC + 9 + CX_DEVNUM_WD +
CX_BUSNUM_WD)

CX_CLIENT_PAR_MODE (CX_RAS_EN ==1) ? 8 : 0

CX_COMM_CLK_EN (CX_MPCIE_ENABLE) ? 1 : ((CX_NFTS


==CX_COMM_NFTS) &&
(DEFAULT_L0S_EXIT_LATENCY
==DEFAULT_COMM_L0S_EXIT_LATENCY) &&
(DEFAULT_L1_EXIT_LATENCY
==DEFAULT_COMM_L1_EXIT_LATENCY)) ? 0 : 1

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Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_CPCIE_ENABLE (CX_S_CPCIE_MODE || CX_SEL_PHY_MODE )

CX_CPCIE_INTERNAL_DELAY CX_PHY_TX_DELAY_MAC + CX_PHY_TX_DELAY_PHY


+ CX_PHY_RX_DELAY_MAC +
CX_PHY_RX_DELAY_PHY

CX_CXPL_DIAG_STATUS_BUS_WD 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 2 + 1 + CX_NL + CX_NW +


CX_NW + CX_NW + CX_NW + CX_NW + 1 + CX_NW +
(32*CX_NW) + CX_NW + CX_NW + 1 + 1 + 1 + 1 + 1 + 1 +
12 + 1 + 1 + 1 + 12 + CX_NW + CX_NW + CX_NW +
TRGT_DATA_PROT_WD + (32*CX_NW) + 1 + 1 + 1 + (
(CX_NW > 2) ? CX_NW : 1) + ( (CX_NW > 2) ? CX_NW : 1)
+ ( (CX_NW > 2) ? CX_NW : 1) + (32*CX_NW) + 1 +
CX_RTLH_DIAG_STATUS_BUS_WD

CX_CXPL_EN (CX_PL_MODE == 0)

CX_CXS_CCIXDATAWIDTH ((CX_NW == 16) ? 512 : (CX_NW == 8) ? 256 : 128)

CX_CXS_CNTLCHKWIDTH ((CX_CXS_RX_DATACHECK == 2) ? 8 :
((CX_CXS_RX_DATACHECK == 1) ? 1 :
((CX_CXS_TX_DATACHECK == 2) ? 8 : 1)))

CX_CXS_CNTLWIDTH (CX_CXS_MAXPKTPERFLIT*(3 + ([function_of:


CX_CXS_DATAFLITWIDTH]-5) + ([pcie_cc_logbase2
CX_CXS_DATAFLITWIDTH]-7)))

CX_CXS_DATACHKWIDTH (CX_CXS_DATAFLITWIDTH/8)

CX_CXS_RX_BUFF_ADDRW ([function_of: CX_CXS_RX_BUFF_DEPTH])

CX_CXS_RX_BUFF_DATAW (CXS_FLIT_LOWER_DATA_WIDTH ?
(CX_CXS_CCIXDATAWIDTH +
CX_CXS_RX_CCIXCNTLWIDTH + (CX_RAS_EN ?
(CX_CXS_CCIXDATAWIDTH/8 + 8) : 0)) :
(CX_CXS_DATAFLITWIDTH + CX_CXS_CNTLWIDTH +
(CX_RAS_EN ? (CX_CXS_DATACHKWIDTH + 8) : 0)) )

CX_CXS_RX_BUFF_DEPTH (CX_CXS_RX_BUFF_FIFO_DEPTH +
CX_CXS_RX_MEM_DEPTH_ADJ)

CX_CXS_RX_BUFF_FIFO_DEPTH (CX_CXS_RX_CREDITS + 1 +
((CX_CXS_RX_CONTINUOUSDATA &&
(CXS_FLIT_EQUALS_DATA_WIDTH ==1)) ? 0 :
(4096/(CXS_FLIT_LOWER_DATA_WIDTH ?
CX_CXS_CCIXDATAWIDTH :
CX_CXS_DATAFLITWIDTH))))

CX_CXS_RX_CCIXCNTLWIDTH ((CX_CXS_CCIXDATAWIDTH/128)*(3 + ([function_of:


CX_CXS_CCIXDATAWIDTH]-5) + ([pcie_cc_logbase2
CX_CXS_CCIXDATAWIDTH]-7)))

CX_CXS_RX_MEM_DEPTH_ADJ ([function_of: CX_CXS_RX_BUFF_FIFO_DEPTH]) ? 0 :


(CX_CXS_RX_BUFF_FIFO_DEPTH % 2) ? 1 : 2

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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CX_CXS_TX_BUFF_ADDRW ([function_of: CX_CXS_TX_BUFF_DEPTH])

CX_CXS_TX_BUFF_DATAW (CXS_FLIT_LOWER_DATA_WIDTH ?
(CX_CXS_CCIXDATAWIDTH +
CX_CXS_TX_CCIXCNTLWIDTH + (CX_RAS_EN ?
(CX_CXS_CCIXDATAWIDTH/8 + 8) : 0)) :
(CX_CXS_DATAFLITWIDTH + CX_CXS_CNTLWIDTH +
(CX_RAS_EN ? (CX_CXS_DATACHKWIDTH + 8) : 0)) )

CX_CXS_TX_BUFF_DEPTH (4*(4096/(CXS_FLIT_LOWER_DATA_WIDTH ?
CX_CXS_CCIXDATAWIDTH :
CX_CXS_DATAFLITWIDTH)))

CX_CXS_TX_CCIXCNTLWIDTH ((CXS_FLIT_EQUALS_DATA_WIDTH ?
CX_CXS_MAXPKTPERFLIT : 1)*(3 + ([function_of:
CX_CXS_CCIXDATAWIDTH]-5) + ([pcie_cc_logbase2
CX_CXS_CCIXDATAWIDTH]-7)))

CX_DBI_ISO_EN (DBISLV_CLK_DIFF_ENABLE ==1 &&


CX_ENHANCED_PM_EN ==1)

CX_DEFAULT_EQ_BYPASS_HIGHEST_RATE_SUPPORT CX_SKIP_LOWER_RATE_EQ

CX_DEFAULT_GEN5_TX_MOD_CMPL_PATTERN_FOR_L CX_DEFAULT_GEN5_EQ_FOR_LOOPBACK
OOPBACK

CX_DEFAULT_LANE_UNDER_TEST 0

CX_DEFAULT_MOD_TS_PCIE_SUPPORT 0

CX_DEFAULT_NO_EQ_NEEDED_SUPPORT CX_NO_EQ_NEEDED

CX_DEVNUM_WD (MULTI_DEVICE_AND_BUS_PER_FUNC_EN == 0) ? 5 :
(CX_NFUNC*5)

CX_DIAG_STATUS_BUS_WD (CX_RADM_DIAG_STATUS_BUS_WD +
CX_XADM_DIAG_STATUS_BUS_WD +
CX_CDM_DIAG_STATUS_BUS_WD +
CX_PM_DIAG_STATUS_BUS_WD +
CX_CXPL_DIAG_STATUS_BUS_WD)

CX_DL_NB (CX_FREQ_STEP_DL_EN ==1 &&


CX_FREQ_STEP_DL_RATIO ==2) ? (CX_NB * 2) :
(CX_FREQ_STEP_DL_EN ==1 &&
CX_FREQ_STEP_DL_RATIO ==4) ? (CX_NB * 4) : CX_NB

CX_DMA_CHANNEL_GROUP_ENABLE 0

CX_DMA_PF_ENABLE 0

CX_DMA_RD_LLQ 1

CX_DMA_WR_LLQ 1

CX_DPC_ENABLE 0

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Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_DPC_ENABLE_VALUE CX_DPC_ENABLE

CX_DPC_RP_PIO_EXTNS 0

CX_DPC_RP_PIO_EXTNS_VALUE CX_DPC_RP_PIO_EXTNS

CX_DSCALE {CX_CALC_DDEPTH <= 2047 ? 1 : CX_CALC_DDEPTH


<= 8188 ? 4 : 16}

CX_DW {[function_of: CX_DL_NB CX_NL]}

CX_DW_W_PAR 32*CX_NW + TRGT_DATA_PROT_WD

CX_ECC_PIPE_EN 0

CX_EXTDPC_ENABLE 0

CX_FLR_ENABLE_VALUE CX_FLR_ENABLE

CX_FLT_Q_ADDR_GT_32 (FLT_Q_ADDR_WIDTH > 32) ? 1 : 0

CX_FREQ (CX_MAC_SMODE_GEN1 ==1) ? 1 :


(CX_MAC_SMODE_GEN1 ==2) ? 2 :
(CX_MAC_SMODE_GEN1 ==4) ? 3 : 3

CX_FREQ_MULTIPLIER (CX_FREQ_VALUE == 0) ? 1 : (CX_FREQ_VALUE == 1) ?


2 : (CX_FREQ_VALUE == 2) ? 4 : (CX_FREQ_VALUE ==
3) ? 8 : 16

CX_FREQ_STEP_DL_EN (CX_FREQ_STEP_DL > 0 )

CX_FREQ_STEP_DL_RATIO ((CX_FREQ_STEP_DL > 0) ? CX_FREQ_STEP_DL : 1)

CX_FREQ_VALUE ((CX_FREQ_STEP_DL_EN == 1) &&


(CX_FREQ_STEP_DL_RATIO == 2)) ? (CX_FREQ - 1 + 1):
((CX_FREQ_STEP_DL_EN == 1) &&
(CX_FREQ_STEP_DL_RATIO == 4)) ? ((CX_FREQ == 3) ?
3 : (CX_FREQ - 1 + 2)): (CX_FREQ - 1)

CX_GEN2_DYNAMIC_FREQ (CX_GEN2_MODE == GEN2_DF)

CX_GEN2_DYNAMIC_WIDTH (CX_GEN2_MODE == GEN2_DW)

CX_GEN2_MODE (CX_MAX_PCIE_SPEED<2) ? 2 :
(CX_MAC_SMODE_GEN1 ==1) &&
(CX_MAC_SMODE_GEN2 ==2) ? 1 :
(CX_MAC_SMODE_GEN1 ==2) &&
(CX_MAC_SMODE_GEN2 ==4) ? 1 :
(CX_MAC_SMODE_GEN1 ==1) &&
(CX_MAC_SMODE_GEN2 ==1) ? 0 :
(CX_MAC_SMODE_GEN1 ==2) &&
(CX_MAC_SMODE_GEN2 ==2) ? 0 :
(CX_MAC_SMODE_GEN1 ==4) &&
(CX_MAC_SMODE_GEN2 ==4) ? 0 : 2

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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CX_GEN2_SPEED (CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 2)


: CX_S_CPCIE_MODE ? (CX_GEN2_MODE ! =
GEN2_DISABLED) : 0)

CX_GEN3_DYNAMIC_FREQ (CX_GEN3_MODE == GEN3_DF)

CX_GEN3_DYNAMIC_WIDTH (CX_GEN3_MODE == GEN3_DW)

CX_GEN3_EQ_PSET_COEF_MAP_MODE_PROG (CX_GEN3_EQ_PSET_COEF_MAP_MODE ==2)

CX_GEN3_MODE (CX_MAX_PCIE_SPEED<3) ? 2 :
(CX_MAC_SMODE_GEN2 ==2) &&
(CX_MAC_SMODE_GEN3 ==4) ? 1 :
(CX_MAC_SMODE_GEN2 ==4) &&
(CX_MAC_SMODE_GEN3 ==8) ? 1 :
(CX_MAC_SMODE_GEN2 ==4) &&
(CX_MAC_SMODE_GEN3 ==16) ? 4 :
(CX_MAC_SMODE_GEN2 ==1) &&
(CX_MAC_SMODE_GEN3 ==1) ? 0 :
(CX_MAC_SMODE_GEN2 ==1) &&
(CX_MAC_SMODE_GEN3 ==4) ? 4 :
(CX_MAC_SMODE_GEN2 ==2) &&
(CX_MAC_SMODE_GEN3 ==2) ? 0 :
(CX_MAC_SMODE_GEN2 ==4) &&
(CX_MAC_SMODE_GEN3 ==4) ? 0 : 2

CX_GEN3_SPEED (CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3)


: CX_S_CPCIE_MODE ? (CX_GEN3_MODE ! =
GEN3_DISABLED) : 0)

CX_GEN3_SPEED_VALUE CX_GEN3_SPEED

CX_GEN4_DYNAMIC_FREQ CX_GEN4_SPEED ? (CX_GEN4_MODE == GEN4_DF) : 0

CX_GEN4_DYNAMIC_WIDTH CX_GEN4_SPEED ? (CX_GEN4_MODE == GEN4_DW) :


0

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Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_GEN4_MODE (CX_MAX_PCIE_SPEED<4) ? 2 :
(CX_MAC_SMODE_GEN3 ==2) &&
(CX_MAC_SMODE_GEN4 ==4) ? 1 :
(CX_MAC_SMODE_GEN3 ==4) &&
(CX_MAC_SMODE_GEN4 ==8) ? 1 :
(CX_MAC_SMODE_GEN3 ==8) &&
(CX_MAC_SMODE_GEN4 ==16) ? 1 :
(CX_MAC_SMODE_GEN3 ==1) &&
(CX_MAC_SMODE_GEN4 ==1) ? 0 :
(CX_MAC_SMODE_GEN3 ==2) &&
(CX_MAC_SMODE_GEN4 ==2) ? 0 :
(CX_MAC_SMODE_GEN3 ==4) &&
(CX_MAC_SMODE_GEN4 ==4) ? 0 :
(CX_MAC_SMODE_GEN3 ==8) &&
(CX_MAC_SMODE_GEN4 ==8) ? 0 :
(CX_MAC_SMODE_GEN3 ==16) &&
(CX_MAC_SMODE_GEN4 ==16) ? 0 : 2

CX_GEN4_SPEC07_PLCAP (CX_GEN4_SPEC07)

CX_GEN4_SPEED CX_GEN4_MODE ! = GEN4_DISABLED

CX_GEN4_SPEED_VALUE CX_GEN4_SPEED

CX_GEN5_SPEED CX_MAX_PCIE_SPEED >= 5

CX_HEADER_RSVD_ENABLE CX_P2P_ENABLE ==1 || CC_DEVICE_TYPE ==CC_SW

CX_HSCALE {CX_CALC_HDEPTH <= 127 ? 1 : CX_CALC_HDEPTH <=


508 ? 4 : 16}

CX_IDO_ENABLE_VALUE CX_IDO_ENABLE

CX_INTERFACE_TIMER_EN (CX_AUTOMOTIVE_ENABLE ==1) ? 1 : 0

CX_INTERNAL_ERR_REPORTING CX_INTERNAL_ERR_REPORTING_EN

CX_INTERNAL_ERR_REPORTING_EN 1

CX_IS_EP (CC_DEVICE_TYPE ==CC_EP) ? 1 : 0

CX_IS_RC (CC_DEVICE_TYPE ==CC_RC) ? 1 : 0

CX_IS_SW (CC_DEVICE_TYPE ==CC_SW) ? 1 : 0

CX_L1_PG_ENABLE CX_L12_PG_EN

CX_LANE_REVERSE (CX_S_MPCIE_MODE) ? 0 : 1

CX_LANE_UNDER_TEST_EN (CX_GEN5_SPEED || CX_FORCE_LANE_FLIP_EN) &&


(CX_NL > 1)

CX_LN_RC_ENABLE (CX_LN_ENABLE ==1 && (CC_DEVICE_TYPE ==CC_RC


|| CC_DEVICE_TYPE ==CC_DM))

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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CX_LN_VALUE CX_LN_ENABLE

CX_LTR_M_ENABLE_VALUE CX_LTR_M_ENABLE

CX_LTSSM_EMU_WD 6+5

CX_MAX_APP_RD_REQ_SIZE_AMBA_DMA ((CC_SLV_MTU < CX_MAX_MTU) ? CX_MAX_MTU :


CC_SLV_MTU)

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Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_MAX_CORECLK_FREQ ((CX_MAX_PCIE_SPEED ==1) &&


(CX_MAC_SMODE_GEN1 == 1) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 250 :
((CX_MAX_PCIE_SPEED ==1) &&
(CX_MAC_SMODE_GEN1 == 2) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 125 :
((CX_MAX_PCIE_SPEED ==1) &&
(CX_MAC_SMODE_GEN1 == 4) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 63 :
((CX_MAX_PCIE_SPEED ==2) &&
(CX_MAC_SMODE_GEN2 == 1) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 500 :
((CX_MAX_PCIE_SPEED ==2) &&
(CX_MAC_SMODE_GEN2 == 2) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 250 :
((CX_MAX_PCIE_SPEED ==2) &&
(CX_MAC_SMODE_GEN2 == 4) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 125 :
((CX_MAX_PCIE_SPEED ==3) &&
(CX_MAC_SMODE_GEN3 == 1) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 1000 :
((CX_MAX_PCIE_SPEED ==3) &&
(CX_MAC_SMODE_GEN3 == 2) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 500 :
((CX_MAX_PCIE_SPEED ==3) &&
(CX_MAC_SMODE_GEN3 == 4) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 250 :
((CX_MAX_PCIE_SPEED ==3) &&
(CX_MAC_SMODE_GEN3 == 8) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 125 :
((CX_MAX_PCIE_SPEED ==3) &&
(CX_MAC_SMODE_GEN3 == 16) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 63 :
((CX_MAX_PCIE_SPEED ==4) &&
(CX_MAC_SMODE_GEN4 == 1) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 2000 :
((CX_MAX_PCIE_SPEED ==4) &&
(CX_MAC_SMODE_GEN4 == 2) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 1000 :
((CX_MAX_PCIE_SPEED ==4) &&
(CX_MAC_SMODE_GEN4 == 4) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 500 :
((CX_MAX_PCIE_SPEED ==4) &&
(CX_MAC_SMODE_GEN4 == 8) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 250 :
((CX_MAX_PCIE_SPEED ==4) &&
(CX_MAC_SMODE_GEN4 == 16) &&
(CX_CCIX_ESM_SUPPORT == 0)) ? 125 :
((CX_MAX_PCIE_SPEED ==4) &&
(CX_MAC_SMODE_GEN4 == 2) &&
(CX_CCIX_ESM_SUPPORT == 1)) ? 1562 :
((CX_MAX_PCIE_SPEED ==4) &&
(CX_MAC_SMODE_GEN4 == 4) &&
Synopsys, Inc.
(CX_CCIX_ESM_SUPPORT == 1)) ? 781 :
1058 SolvNet ((CX_MAX_PCIE_SPEED ==4) &&
Synopsys, Inc. 5.40a
DesignWare.com (CX_MAC_SMODE_GEN4 == 8) && March 2019
(CX_CCIX_ESM_SUPPORT == 1)) ? 390 :
((CX_MAX_PCIE_SPEED ==4) &&
PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CX_MAX_DELAY_LAYER2_LAYER3 16

CX_MAX_END2END_TLP_PRFXS (CX_NPRFX < 4) ? CX_NPRFX : 0

CX_MAX_END2END_TLP_PRFXS_VALUE (CX_NPRFX < 4) ? CX_NPRFX : 4

CX_MAX_L0S_LTIME (CX_S_CPCIE_MODE) ? CX_MAX_NFTS :


(CX_S_MPCIE_MODE) ? CM_MAX_SYNC_TIME_D4 :
(CX_MAX_NFTS > CM_MAX_SYNC_TIME_D4) ?
CX_MAX_NFTS : CM_MAX_SYNC_TIME_D4

CX_MAX_NFTS ((CX_GEN2_SPEED ==1) ? ((DEFAULT_GEN2_N_FTS >


CX_MAX_NFTS_TMP) ? DEFAULT_GEN2_N_FTS :
CX_MAX_NFTS_TMP) : CX_MAX_NFTS_TMP)

CX_MAX_NFTS_TMP ((CX_NFTS > CX_COMM_NFTS) ? CX_NFTS :


CX_COMM_NFTS)

CX_MEMORY_MAP_PCIE_TYPE (CX_PCIE_MODE ==1) ? 1 : 0

CX_MPCIE_ENABLE (CX_S_MPCIE_MODE || CX_SEL_PHY_MODE )

CX_MSI_CTRL_EN CX_MSI_CTRL_ENABLE

CX_MSTR_ISO_EN (MSTR_CLK_DIFF_ENABLE ==1 &&


CX_ENHANCED_PM_EN ==1)

CX_NB (CX_NB_GEN5)

CX_NB_GEN1 (CX_MAC_SMODE_GEN1)

CX_NB_GEN2 (CX_GEN2_SPEED ? CX_MAC_SMODE_GEN2 :


CX_NB_GEN1 )

CX_NB_GEN3 (CX_GEN3_SPEED ? CX_MAC_SMODE_GEN3 :


CX_NB_GEN2 )

CX_NB_GEN4 (CX_GEN4_SPEED ? CX_MAC_SMODE_GEN4 :


CX_NB_GEN3 )

CX_NB_GEN5 (CX_GEN5_SPEED ? CX_MAC_SMODE_GEN5 :


CX_NB_GEN4 )

CX_NCLIENTS ((CLIENT2_POPULATED ==1) ? 3: 2)

CX_NDQ (CX_NW ==16) ? 4 : (CX_NW ==8) ? 2 : 1

CX_NFUNC_WD (CX_ARI_ENABLE) ? [function_of: CX_NFUNC] : 3

CX_NHQ (CX_NW ==8) ? 2 : 1

CX_NL_M_1 CX_NL-1

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Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_NP_CALC_DDEPTH {(CX_ADM_ADAPTOR_ENABLE ==1) ? [function_of:


CX_NW CX_ADM_ADAPTOR_RADM_PIPE_STAGES] :
(CX_ATOMIC_ENABLE ?
(RADM_NPQ_HCRD_VC0*CX_HSCALE)/2 :
(RADM_NPQ_HCRD_VC0*CX_HSCALE)/4)}

CX_NP_DSCALE {CX_NP_CALC_DDEPTH <= 2047 ? 1 :


CX_NP_CALC_DDEPTH <= 8188 ? 4 : 16}

CX_NUM_DMA_RD_CHAN CC_NUM_DMA_RD_CHAN

CX_NUM_DMA_WR_CHAN CC_NUM_DMA_WR_CHAN

CX_NVFUNC_EWD {[function_of: CX_NVFUNC]}

CX_NVFUNC_NUM_WD {CX_NVFUNC_WD}

CX_NVFUNC_WD {[function_of: CX_NVFUNC] + 1}

CX_NW_GTR_4 (CX_NW > 4) ? 1 : 0

CX_NW_GTR_4_VALUE CX_NW_GTR_4

CX_OBFF_ENABLE (CX_OBFF_SUPPORT > 0) ? 1 : 0

CX_P2P_ENABLE_VALUE CX_P2P_ENABLE

CX_PCIE_BRIDGE CX_PCIE_BRIDGE_ENABLE

CX_PCIE_BRIDGE_ENABLE 0

CX_PHY_2S_DYN_PACE ((CX_PHY_FREQ == 1 && CX_PHY_NB_GEN1 == 2 &&


CX_PHY_GEN2_MODE == GEN2_DF &&
CX_PHY_GEN3_MODE == GEN3_DP &&
CX_PHY_GEN4_MODE == GEN4_DISABLED) ? 1 :
(CX_PHY_FREQ == 1 && CX_PHY_NB_GEN1 == 2 &&
CX_PHY_GEN2_MODE == GEN2_DF &&
CX_PHY_GEN3_MODE == GEN3_DP &&
CX_PHY_GEN4_MODE == GEN4_DF) ? 1 : 0)

CX_PHY_FREQ (CX_PHY_SMODE_GEN1 ==1) ? 1 :


(CX_PHY_SMODE_GEN1 ==2) ? 2 :
(CX_PHY_SMODE_GEN1 ==4) ? 3 :
(CX_PHY_SMODE_GEN1 ==102) ? 0 :
(CX_PHY_SMODE_GEN1 ==202) ? 1 : 3

CX_PHY_GEN1_DP (CX_PHY_FREQ == FREQ_500 ||


CX_PHY_2S_DYN_PACE == 1)

CX_PHY_GEN2_DP (CX_PHY_2S_DYN_PACE == 1)

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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CX_PHY_GEN2_MODE (CX_MAX_PCIE_SPEED<2) ? 2 :
(CX_PHY_SMODE_GEN1 ==1) &&
(CX_PHY_SMODE_GEN2 ==2) ? 1 :
(CX_PHY_SMODE_GEN1 ==2) &&
(CX_PHY_SMODE_GEN2 ==4) ? 1 :
(CX_PHY_SMODE_GEN1 ==1) &&
(CX_PHY_SMODE_GEN2 ==1) ? 0 :
(CX_PHY_SMODE_GEN1 ==2) &&
(CX_PHY_SMODE_GEN2 ==2) ? 0 :
(CX_PHY_SMODE_GEN1 ==4) &&
(CX_PHY_SMODE_GEN2 ==4) ? 0 :
(CX_PHY_SMODE_GEN1 ==202) &&
(CX_PHY_SMODE_GEN2 ==202) ? 0 :
(CX_PHY_SMODE_GEN1 ==102) &&
(CX_PHY_SMODE_GEN2 ==1) ? 1 : 2

CX_PHY_GEN3_MODE (CX_MAX_PCIE_SPEED<3) ? 2 :
(CX_PHY_SMODE_GEN2 ==1) &&
(CX_PHY_SMODE_GEN3 ==2) ? 1 :
(CX_PHY_SMODE_GEN2 ==2) &&
(CX_PHY_SMODE_GEN3 ==4) ? 1 :
(CX_PHY_SMODE_GEN2 ==4) &&
(CX_PHY_SMODE_GEN3 ==8) ? 1 :
(CX_PHY_SMODE_GEN2 ==1) &&
(CX_PHY_SMODE_GEN3 ==4) ? 4 :
(CX_PHY_SMODE_GEN2 ==4) &&
(CX_PHY_SMODE_GEN3 ==16) ? 4 :
(CX_PHY_SMODE_GEN2 ==1) &&
(CX_PHY_SMODE_GEN3 ==1) ? 0 :
(CX_PHY_SMODE_GEN2 ==2) &&
(CX_PHY_SMODE_GEN3 ==2) ? 0 :
(CX_PHY_SMODE_GEN2 ==4) &&
(CX_PHY_SMODE_GEN3 ==4) ? 0 :
(CX_PHY_SMODE_GEN2 ==202) &&
(CX_PHY_SMODE_GEN3 ==2) ? 3 : 2

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Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_PHY_GEN4_MODE (CX_MAX_PCIE_SPEED<4) ? 2 :
(CX_PHY_SMODE_GEN3 < CX_PHY_SMODE_GEN4) ? 1
: (CX_PHY_SMODE_GEN3 ==1) &&
(CX_PHY_SMODE_GEN4 ==2) ? 1 :
(CX_PHY_SMODE_GEN3 ==2) &&
(CX_PHY_SMODE_GEN4 ==4) ? 1 :
(CX_PHY_SMODE_GEN3 ==4) &&
(CX_PHY_SMODE_GEN4 ==8) ? 1 :
(CX_PHY_SMODE_GEN3 ==1) &&
(CX_PHY_SMODE_GEN4 ==1) ? 0 :
(CX_PHY_SMODE_GEN3 ==2) &&
(CX_PHY_SMODE_GEN4 ==2) ? 0 :
(CX_PHY_SMODE_GEN3 ==4) &&
(CX_PHY_SMODE_GEN4 ==4) ? 0 :
(CX_PHY_SMODE_GEN3 ==8) &&
(CX_PHY_SMODE_GEN4 ==8) ? 0 :
(CX_PHY_SMODE_GEN3 ==16) &&
(CX_PHY_SMODE_GEN4 ==16) ? 0 : 2

CX_PHY_INTERFACE (CX_GEN3_SPEED_VALUE == 1)

CX_PHY_NB (CX_MAX_PCIE_SPEED ==1) ? CX_PHY_NB_GEN1 :


(CX_MAX_PCIE_SPEED ==2) ? CX_PHY_NB_GEN2 :
(CX_MAX_PCIE_SPEED ==3) ? CX_PHY_NB_GEN3 :
(CX_MAX_PCIE_SPEED ==4) ? CX_PHY_NB_GEN4 :
(CX_MAX_PCIE_SPEED ==5) ? CX_PHY_NB_GEN5 :
CX_PHY_NB_GEN5

CX_PHY_NB_GEN1 (CX_PHY_SMODE_GEN1 ==1) ? 1 :


(CX_PHY_SMODE_GEN1 ==2) ? 2 :
(CX_PHY_SMODE_GEN1 ==4) ? 4 :
(CX_PHY_SMODE_GEN1 ==102) ? 1 :
(CX_PHY_SMODE_GEN1 ==202) ? 2 : 2

CX_PHY_NB_GEN2 (CX_PHY_SMODE_GEN2 ==1) ? 1 :


(CX_PHY_SMODE_GEN2 ==2) ? 2 :
(CX_PHY_SMODE_GEN2 ==4) ? 4 :
(CX_PHY_SMODE_GEN2 ==102) ? 1 :
(CX_PHY_SMODE_GEN2 ==202) ? 2 : 2

CX_PHY_NB_GEN3 (CX_PHY_SMODE_GEN3 ==1) ? 1 :


(CX_PHY_SMODE_GEN3 ==2) ? 2 :
(CX_PHY_SMODE_GEN3 ==4) ? 4 :
(CX_PHY_SMODE_GEN3 ==8) ? 8 :
(CX_PHY_SMODE_GEN3 ==16) ? 16 : 2

CX_PHY_NB_GEN4 (CX_PHY_SMODE_GEN4 ==1) ? 1 :


(CX_PHY_SMODE_GEN4 ==2) ? 2 :
(CX_PHY_SMODE_GEN4 ==4) ? 4 :
(CX_PHY_SMODE_GEN4 ==8) ? 8 :
(CX_PHY_SMODE_GEN4 ==16) ? 16 : 2

Synopsys, Inc.
1062 SolvNet Synopsys, Inc. 5.40a
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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CX_PHY_NB_GEN5 (CX_PHY_SMODE_GEN5 ==1) ? 1 :


(CX_PHY_SMODE_GEN5 ==2) ? 2 :
(CX_PHY_SMODE_GEN5 ==4) ? 4 :
(CX_PHY_SMODE_GEN5 ==8) ? 8 :
(CX_PHY_SMODE_GEN5 ==16) ? 16 : 2

CX_PHY_NUM_MACROS [function]

CX_PHY_PDOWN_WD 4

CX_PHY_RATE_WD (CX_GEN5_SPEED) ? 3 : (CX_GEN3_SPEED ==1) ? 2 : 1

CX_PHY_RX_DELAY_MAC 4

CX_PHY_RXSB_WD (CX_PIPERX_MULTI_BLOCK ==1) ? (CX_PHY_NB / 4) :


(SNPS_RSVDPARAM_42) ? 2 : 1

CX_PHY_RXSH_WD (CX_PIPERX_MULTI_BLOCK ==1) ? (CX_PHY_NB / 4) * 2


:2

CX_PHY_TXDEEMPH_WD (PHY_IS_PIPE ==1 && CX_GEN3_SPEED ==1) ?


(CX_NL*18) : 2

CX_PHY_TX_DELAY_MAC 4

CX_PHY_TXEI_WD (CX_PIPE51_SUPPORT) ? 4 : 1

CX_PHY_VIEWPORT_DATA 16

CX_PHY_WIDTH_WD ((CX_GEN3_SPEED ==1) && (CX_PHY_NB ==16)) ? 3 : 2

CX_PIPE44_SUPPORT (CX_PIPE_VER>=2)

CX_PIPE51_LOW_PIN_COUNT (CX_PIPE51_SUPPORT)

CX_PIPE51_SUPPORT (CX_PIPE_VER>=3)

CX_PIPE_LEGACY_MSGBUS_SUPPORT CX_GEN4_SPEED && ( ! CX_PIPE44_SUPPORT && !


CX_PIPE51_SUPPORT)

CX_PIPE_LOOPBACK_EN (CX_S_MPCIE_MODE ? 0 : 1)

CX_PIPE_MSGBUS_SUPPORT (CX_GEN4_SPEED && CX_PIPE44_SUPPORT) ||


CX_PIPE51_SUPPORT

CX_PIPE_REGIF_L1_PG_ALWAYS_ON (CX_L12_PG_EN && SNPS_RSVDPARAM_28) &&


(CX_PIPE51_LOW_PIN_COUNT ||
CX_CCIX_ESM_SUPPORT)

CX_PIPE_WIDTH_ {(8 * (CX_NB))}

CX_PL16G_ENABLE (CX_GEN4_SPEC07_PLCAP)

CX_PL32G_ENABLE (CX_GEN5_SPEED)

CX_PL_MODE 0

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Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_PL_REG_DISABLE 0

CX_PM_DIAG_STATUS_BUS_WD (CX_NVC + CX_NVC + 4 + 3)

CX_PRFX_PAR_WD (CX_RASDP_EN) ? [function_of: CX_NW CX_NPRFX


CX_RAS_PROT_RANGE CX_RAS_PROT_TYPE] : 0

CX_PTM_REQUESTER_CAPABLE (CX_PTM_ENABLE ==1 && CC_DEVICE_TYPE !


=CC_RC)

CX_PTM_REQUESTER_VALUE CX_PTM_REQUESTER_CAPABLE

CX_PTM_RESPONDER_CAPABLE (CX_PTM_ROOT_CAPABLE || (CX_PTM_ENABLE &&


CC_DEVICE_TYPE ! =CC_EP))

CX_PTM_RESPONDER_VALUE CX_PTM_RESPONDER_CAPABLE

CX_PTM_ROOT_CAPABLE (CX_PTM_ENABLE && CC_DEVICE_TYPE ! =CC_EP)

CX_RADM_DATAQ_DEPTH CX_RADM_DDP_VC0 + CX_RADM_DDP_VC1 +


CX_RADM_DDP_VC2 + CX_RADM_DDP_VC3 +
CX_RADM_DDP_VC4 + CX_RADM_DDP_VC5 +
CX_RADM_DDP_VC6 + CX_RADM_DDP_VC7 +
(CX_NVC*3)

CX_RADM_DATASIZE (CX_NW ==16) ? CX_MAX_MTU/(4*CX_NW) +


(CX_ECRC_STRIP_ENABLE ==0) :
CX_NHQ*CX_RADM_MAXPKT/(4*CX_NW)

CX_RADM_DDP_VC0 RADM_PQ_DDP_VC0 + RADM_NPQ_DDP_VC0 +


RADM_CPLQ_DDP_VC0

CX_RADM_DDP_VC1 CX_NVC<=1 ? 0 : RADM_PQ_DDP_VC1 +


RADM_NPQ_DDP_VC1 + RADM_CPLQ_DDP_VC1

CX_RADM_DDP_VC2 CX_NVC<=2 ? 0 : RADM_PQ_DDP_VC2 +


RADM_NPQ_DDP_VC2 + RADM_CPLQ_DDP_VC2

CX_RADM_DDP_VC3 CX_NVC<=3 ? 0 : RADM_PQ_DDP_VC3 +


RADM_NPQ_DDP_VC3 + RADM_CPLQ_DDP_VC3

CX_RADM_DDP_VC4 CX_NVC<=4 ? 0 : RADM_PQ_DDP_VC4 +


RADM_NPQ_DDP_VC4 + RADM_CPLQ_DDP_VC4

CX_RADM_DDP_VC5 CX_NVC<=5 ? 0 : RADM_PQ_DDP_VC5 +


RADM_NPQ_DDP_VC5 + RADM_CPLQ_DDP_VC5

CX_RADM_DDP_VC6 CX_NVC<=6 ? 0 : RADM_PQ_DDP_VC6 +


RADM_NPQ_DDP_VC6 + RADM_CPLQ_DDP_VC6

CX_RADM_DDP_VC7 CX_NVC<=7 ? 0 : RADM_PQ_DDP_VC7 +


RADM_NPQ_DDP_VC7 + RADM_CPLQ_DDP_VC7

CX_RADM_DIAG_STATUS_BUS_WD ((CX_NHQ*(17 + (CX_NW *32) + CX_NW + 128)) +


((CX_NHQ == 2) ? 1 : 0))

Synopsys, Inc.
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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CX_RADM_FORMQ_NQW CX_RADM_SERQ_NUM_RAMS

CX_RADM_FORMQ_QDW_RAM_PW CX_RADM_SERQ_QDW_RAM_PW

CX_RADM_HDP_VC0 RADM_PQ_HDP_VC0 + RADM_NPQ_HDP_VC0 +


RADM_CPLQ_HDP_VC0

CX_RADM_HDP_VC1 CX_NVC<=1 ? 0 : RADM_PQ_HDP_VC1 +


RADM_NPQ_HDP_VC1 + RADM_CPLQ_HDP_VC1

CX_RADM_HDP_VC2 CX_NVC<=2 ? 0 : RADM_PQ_HDP_VC2 +


RADM_NPQ_HDP_VC2 + RADM_CPLQ_HDP_VC2

CX_RADM_HDP_VC3 CX_NVC<=3 ? 0 : RADM_PQ_HDP_VC3 +


RADM_NPQ_HDP_VC3 + RADM_CPLQ_HDP_VC3

CX_RADM_HDP_VC4 CX_NVC<=4 ? 0 : RADM_PQ_HDP_VC4 +


RADM_NPQ_HDP_VC4 + RADM_CPLQ_HDP_VC4

CX_RADM_HDP_VC5 CX_NVC<=5 ? 0 : RADM_PQ_HDP_VC5 +


RADM_NPQ_HDP_VC5 + RADM_CPLQ_HDP_VC5

CX_RADM_HDP_VC6 CX_NVC<=6 ? 0 : RADM_PQ_HDP_VC6 +


RADM_NPQ_HDP_VC6 + RADM_CPLQ_HDP_VC6

CX_RADM_HDP_VC7 CX_NVC<=7 ? 0 : RADM_PQ_HDP_VC7 +


RADM_NPQ_HDP_VC7 + RADM_CPLQ_HDP_VC7

CX_RADM_HDRQ_DEPTH CX_RADM_HDP_VC0 + CX_RADM_HDP_VC1 +


CX_RADM_HDP_VC2 + CX_RADM_HDP_VC3 +
CX_RADM_HDP_VC4 + CX_RADM_HDP_VC5 +
CX_RADM_HDP_VC6 + CX_RADM_HDP_VC7 +
(CX_NVC*3)

CX_RADM_MAXPKT (CX_MAX_MTU + 28)

CX_RADM_ORDERING_RULES_VC0 CX_RADM_ORDERING_RULES

CX_RADM_ORDERING_RULES_VC1 CX_RADM_ORDERING_RULES

CX_RADM_PQ_D_ADDRBITS CX_NDQ * (CX_RADMQ_MODE ==2 ?


CX_RADM_SBUF_DATAQ_PW : (RADM_PQ_DPW *
CX_NVC))

CX_RADM_PQ_H_ADDRBITS CX_NHQ * (CX_RADMQ_MODE ==2 ?


CX_RADM_SBUF_HDRQ_PW : (RADM_PQ_HPW *
CX_NVC))

CX_RADM_PQ_H_DATABITS CX_NHQ * (CX_RADMQ_MODE ==2 ?


CX_RADM_SBUF_HDRQ_WD : (CX_RADM_PQ_HWD *
CX_NVC))

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March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_RADM_PQ_H_DATABITS_OUT ( ! CX_ECC_PIPE_EN) ? CX_RADM_PQ_H_DATABITS :


(CX_RADMQ_MODE ==2) ?
(CX_RADM_SBUF_HDRQ_WD +
2*(RADM_ECRC_ERR_WD + RADM_DLLP_ABORT_WD
+ RADM_TLP_ABORT_WD) + P_HDRQ_NECC_BITS) *
CX_NHQ : (CX_RADM_PQ_HWD + 16 +
P_HDRQ_NECC_BITS) * CX_NVC * CX_NHQ

CX_RADM_PQ_HWD {[function_of: RADM_P_HWD 6 ]}

CX_RADM_Q_DATABITS (CX_RADMQ_MODE ==2) ?


CX_RADM_SBUF_DATAQ_RAM_WD*CX_NDQ :
(CX_NVC * ((32*CX_NW) + CX_NW + 5*CX_NDQ))

CX_RADM_Q_DATABITS_OUT ( ! CX_ECC_PIPE_EN) ? CX_RADM_Q_DATABITS :


(CX_RADMQ_MODE ==2) ?
CX_NDQ*(CX_RADM_SBUF_DATAQ_RAM_WD +
2*(CX_RADM_SBUF_DATAQ_CTRL_WD-CX_RADM_SBU
F_DATAQ_CTRLQ_WD) + P_DATAQ_NECC_BITS) :
(CX_NW*32 + 3*(CX_NW + 5) + P_DATAQ_NECC_BITS) *
CX_NVC

CX_RADM_Q_D_CTRLBITS CX_NDQ * (CX_RADMQ_MODE ==2 ? 1 : CX_NVC)

CX_RADM_Q_H_CTRLBITS CX_NHQ * (CX_RADMQ_MODE ==2 ? 1 : CX_NVC)

CX_RADMQ_MODE (CC_DEVICE_TYPE ==CC_SW || CX_P2P_ENABLE ==1 ||


CX_NW ==16) ? 2 : 0 ==1 ? 0 : 2

CX_RADM_RXQ_NUM_QDWS CX_RADM_HDRQ_DEPTH +
CX_RADM_DATAQ_DEPTH*(CX_NW/4)

CX_RADM_RXQ_NUM_QDWS_PER_SERQ_RAM {CX_RADM_HDRQ_DEPTH <


CX_RADM_SERQ_NUM_RAMS ? 1 : [function_of:
CX_RADM_RXQ_NUM_QDWS
CX_RADM_SERQ_NUM_RAMS]}

CX_RADM_SBUF_DATAQ_CTRLQ_WD RADM_EOT_WD

CX_RADM_SBUF_DATAQ_CTRL_WD RADM_DLLP_ABORT_WD + RADM_ECRC_ERR_WD +


RADM_TLP_ABORT_WD + RADM_EOT_WD

CX_RADM_SBUF_DATAQ_DATA_WD (32*CX_NW)/CX_NDQ

CX_RADM_SBUF_DATAQ_PROT_WD {(CX_RAS_EN ==1) ? [function_of:


CX_RADM_SBUF_DATAQ_DATA_WD
CX_RADM_SBUF_DATAQ_CTRL_WD CX_RASDP_EN
CX_RAS_PROT_TYPE CX_RAS_PROT_RANGE
CX_RAS_RAM_PROT_RANGE RAS_BASE_PROT_WD
RAS_RAM_BASE_PROT_WD ]: 0}

CX_RADM_SBUF_DATAQ_PW {[function_of: CX_RADM_DATAQ_DEPTH]}

CX_RADM_SBUF_DATAQ_RAM_WD

Synopsys, Inc.
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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CX_RADM_SBUF_HDRQ_CTRL_WD RADM_DLLP_ABORT_WD + RADM_ECRC_ERR_WD +


RADM_TLP_ABORT_WD

CX_RADM_SBUF_HDRQ_PROT_WD {(CX_RAS_EN ==1) ? [function_of:


CX_RAS_RADM_P_HWD_TOPROT
CX_RADM_SBUF_HDRQ_CTRL_WD CX_RASDP_EN
CX_RAS_PROT_TYPE CX_RAS_PROT_RANGE
CX_RAS_RAM_PROT_RANGE RAS_BASE_PROT_WD
RAS_RAM_BASE_PROT_WD ]:0}

CX_RADM_SBUF_HDRQ_PW {[function_of: CX_RADM_HDRQ_DEPTH]}

CX_RADM_SBUF_HDRQ_WD CX_RAS_RADM_P_HWD + RADM_DLLP_ABORT_WD +


RADM_ECRC_ERR_WD + RADM_TLP_ABORT_WD +
CX_RADM_SBUF_HDRQ_PROT_WD

CX_RADM_SERQ_AF_NUM_QDWS CX_RADM_SERQ_AF_NUM_QDWS_PER_RAM*CX_RAD
M_SERQ_NUM_RAMS

CX_RADM_SERQ_AF_NUM_QDWS_PER_RAM {[function_of: [
CX_RADM_RXQ_NUM_QDWS_PER_SERQ_RAM *
CX_RADM_SERQ_TO_RXQ_SIZE_RATIO] 100]}

CX_RADM_SERQ_MARGIN_NUM_QDWS {[function_of: CX_MAX_MTU


CX_MAX_DELAY_LAYER2_LAYER3 CX_NPRFX]}

CX_RADM_SERQ_MARGIN_NUM_QDWS_PER_RAM {[function_of: CX_RADM_SERQ_MARGIN_NUM_QDWS


CX_RADM_SERQ_NUM_RAMS]}

CX_RADM_SERQ_NUM_RAMS (CX_NW == 16) ? ((CX_TLP_PREFIX_ENABLE) ? 7 : 6) :


(CX_NW == 8) ? 3 : 2

CX_RADM_SERQ_OPT_AF_NUM_QDWS {[function_of: CX_PHY_TX_DELAY_PHY


CX_PHY_RX_DELAY_PHY CX_NB CX_PHY_NB
CX_RETIMER_LATENCY CX_NPRFX]}

CX_RADM_SERQ_OPT_AF_NUM_QDWS_PER_RAM {[function_of: CX_RADM_SERQ_OPT_AF_NUM_QDWS


CX_RADM_SERQ_NUM_RAMS]}

CX_RADM_SERQ_QDW_RAM_DP {CX_RADM_SERQ_AF_NUM_QDWS_PER_RAM +
CX_RADM_SERQ_MARGIN_NUM_QDWS_PER_RAM}

CX_RADM_SERQ_QDW_RAM_PW {[function_of: CX_RADM_SERQ_QDW_RAM_DP]}

CX_RAM_PROTECTION_MODE 0

CX_RAS_DES_EC_G0_BW 4

CX_RAS_DES_EC_G1_BW 8

CX_RAS_DES_EC_G2_BW 8

CX_RAS_DES_EC_G3_BW 8

CX_RAS_DES_EC_G4_BW 4

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Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_RAS_DES_EC_G5_BW 32

CX_RAS_DES_EC_G6_BW 32

CX_RAS_DES_EC_G7_BW 32

CX_RAS_DES_EC_INFO_CMN_BW 171

CX_RAS_DES_EC_INFO_PLN_BW 13

CX_RAS_DES_EC_RAM_ADDR_WIDTH {[function_of: CX_RAS_DES_EC_RAM_DEPTH]}

CX_RAS_DES_EC_RAM_DATA_WIDTH 64

CX_RAS_DES_EC_RAM_DEPTH {[function_of: CX_RAS_DES_EC_G0_BW


CX_RAS_DES_EC_G1_BW CX_RAS_DES_EC_G2_BW
CX_RAS_DES_EC_G3_BW CX_RAS_DES_EC_G4_BW
CX_RAS_DES_EC_G5_BW CX_RAS_DES_EC_G6_BW
CX_RAS_DES_EC_G7_BW CX_RAS_DES_EC_ENABLE
CX_NL CX_GEN2_SPEED CX_GEN3_SPEED
CX_GEN4_SPEED CX_L1_SUBSTATES_ENABLE
SNPS_RSVDPARAM_29 CX_MPCIE_ENABLE
CX_CCIX_INTERFACE_ENABLE]}

CX_RAS_DES_SD_INFO_CMN_BW 79

CX_RAS_DES_SD_INFO_PLN_BW 205

CX_RAS_DES_SD_INFO_PVC_BW 240

CX_RAS_DES_TBA_DATA_WIDTH {[function_of: CX_MAX_CORECLK_FREQ]}

CX_RAS_DES_TBA_INFO_CMN_BW 7

CX_RAS_DES_TBA_RAM_ADDR_WIDTH {[function_of: CX_RAS_DES_TBA_RAM_DEPTH]}

CX_RAS_DES_TBA_RAM_DATA_WIDTH {[function_of: CX_RAS_DES_TBA_DATA_WIDTH]}

CX_RAS_DES_TBA_RAM_DEPTH {[function_of: CX_RAS_DES_TBA_ENABLE


CX_L1_SUBSTATES_ENABLE
CX_CCIX_ESM_SUPPORT]}

CX_RASDP_BYPASS_HDR_PROT_WD {(CX_RASDP_EN ==1) ? [function_of:


CX_RASDP_BYPASS_HDR_WD CX_RAS_PROT_RANGE
RAS_BASE_PROT_WD ]: 0}

CX_RASDP_BYPASS_HDR_WD (CX_RASDP_EN) ? ((CX_IS_SW) ? 50: 55) +


CX_TAG_SIZE + (ATS_RX_ENABLE_VALUE*2) +
FLT_Q_ADDR_WIDTH + (CX_TPH_ENABLE_VALUE*11)
+ ((CX_NVFUNC_EWD +
1)*CX_SRIOV_ENABLE_VALUE) + CX_NFUNC_WD +
FLT_Q_ATTR_WIDTH + CX_LN_VALUE: 0

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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CX_RASDP_CCIX_HDR_PROT_WD {(CX_RASDP_EN ==1) ? [function_of:


CX_RASDP_CCIX_HDR_WD CX_RAS_PROT_RANGE
RAS_BASE_PROT_WD ]: 0}

CX_RASDP_CCIX_HDR_WD 128

CX_RASDP_EN ((CX_RASDP ==0) ? 0: 1)

CX_RASDP_FORMQ_ERR_SYND_WD ((CX_RAS_EN && CX_NW ==16) ? ((CX_RASDP>2) ?


CX_RASDP_FORMQRAM_ECC_WD +
TRGT_DATA_PROT_WD/(CX_NW/4):
CX_RASDP_FORMQRAM_ECC_WD) : 0)

CX_RASDP_FORMQRAM_ECC_WD (CX_RAS_EN ? ((CX_RASDP >2 && CX_RASDP_EN ==1)


? 6 : 22) : 0)

CX_RASDP_HDRQ_ERR_SYND_WD (CX_RASDP_EN && CX_TLP_PREFIX_ENABLE &&


CX_RAS_PROT_TYPE ==0) ?
CX_RADM_SBUF_HDRQ_PROT_WD +
CX_RX_PRFX_PAR_WD :
CX_RADM_SBUF_HDRQ_PROT_WD

CX_RASDP_TRGT1_HDR_PROT_WD {(CX_RASDP_EN ==1) ? [function_of:


CX_RASDP_TRGT1_HDR_WD CX_RAS_PROT_RANGE
RAS_BASE_PROT_WD ]: 0}

CX_RASDP_TRGT1_HDR_WD CX_RASDP_EN ? (CX_IS_SW ? CX_ATU_CTRL_EN &&


(CX_RADMQ_MODE ==2) ? 51 + FLT_Q_ADDR_WIDTH :
50 + FLT_Q_ADDR_WIDTH : CX_IS_RC ?
CX_ATU_CTRL_EN && (CX_RADMQ_MODE ==2) ? 52 +
FLT_Q_ADDR_WIDTH : 51 + FLT_Q_ADDR_WIDTH :
CX_ATU_CTRL_EN && (CX_RADMQ_MODE ==2) ? 56 +
FLT_Q_ADDR_WIDTH : 55 + FLT_Q_ADDR_WIDTH) +
CX_TAG_SIZE + (ATS_RX_ENABLE_VALUE*2) +
FLT_Q_ADDR_WIDTH + (CX_TPH_ENABLE_VALUE*11)
+ ((CX_NVFUNC_EWD +
1)*CX_SRIOV_ENABLE_VALUE) + CX_NFUNC_WD +
FLT_Q_ATTR_WIDTH + CX_LN_VALUE: 0

CX_RAS_EN ((CX_RASDP ==0) && (CX_RASDP_RAM_PROT ==0)) ?


0: 1

CX_RAS_EXT_IF 0

CX_RAS_PCIE_HDR_PROT_WD ((CX_RASDP_EN ==1) ? [function_of:


CX_RAS_PROT_RANGE RAS_BASE_PROT_WD ]: 0)

CX_RAS_PROT_RANGE (CX_RAS_PROT_TYPE ==0) ? ((CX_NW>1) ? 64: 32): 8

CX_RAS_PROT_TYPE ((CX_RASDP ==1) || (CX_RASDP ==2))

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March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_RAS_RADM_P_HWD (CX_RASDP_EN && CX_TLP_PREFIX_ENABLE) ?


((CX_RAS_PROT_TYPE ==0) ? RADM_P_HWD :
RADM_P_HWD-CX_RX_PRFX_PAR_WD) :
RADM_P_HWD

CX_RAS_RADM_P_HWD_TOPROT (CX_RASDP_EN && CX_TLP_PREFIX_ENABLE) ?


((CX_RAS_PROT_TYPE ==0) ?
RADM_P_HWD-FLT_Q_PRFX_WIDTH :
RADM_P_HWD-CX_RX_PRFX_PAR_WD) :
RADM_P_HWD

CX_RAS_RAM_PROT_RANGE ((CX_NW>1) ? 64: 32)

CX_RAS_SOTBUF_PROT_WD {(CX_RAS_EN ==1) ? (([function_of: CX_RBUF_DEPTH] >


26) ? 7: 6): 0}

CX_RBARS_INCLUDED {[ PortCfg::is_rbar_enabled ]}

CX_RBUF_CTRL_WD ( CX_TLP_PREFIX_ENABLE && CX_GEN3_SPEED ==1)


? (11 + CX_NW + CX_RBUF_SOT_WD): (CX_NW +
CX_RBUF_SOT_WD)

CX_RBUF_SOT_WD (CX_NW>2) ? ( (CX_NW ==16) ? 5 : (CX_NW ==8) ?


CX_NW/2: CX_NW-1): CX_NW

CX_RCB (CC_DEVICE_TYPE == CC_RC) ? 128 : 64

CX_RET_CORE_CLK_UG_EN (CX_PIPE_REGIF_L1_PG_ALWAYS_ON && ( !


CX_FREQ_STEP_EN && ! CX_FREQ_STEP_DL_EN))

CX_RET_CORE_PL_CLK_UG_EN (CX_PIPE_REGIF_L1_PG_ALWAYS_ON && ( !


CX_FREQ_STEP_EN && CX_FREQ_STEP_DL_EN))

CX_RET_PIPE_CLK_EN (CX_PIPE_REGIF_L1_PG_ALWAYS_ON &&


CX_FREQ_STEP_EN)

CX_RP_PIO_IMPSPEC 0

CX_RTLH_DIAG_STATUS_BUS_WD 15 * ( (CX_NW == 16) ? 4 : (CX_NW == 8) ? 2 : 1 )

CX_RTLH_SIMPLE_EXTRACT CX_RTLH_SIMPLE_EXTRACT_ENABLE

CX_RTLH_SIMPLE_EXTRACT_ENABLE CX_NW ==16

CX_RX_HEADER_RSVD_ENABLE CX_HEADER_RSVD_ENABLE ==1 ||


CX_CCIX_INTERFACE_ENABLE ==1

CX_RXMARGIN_RATE_MODE_ENABLE 0

CX_RX_NDLLP (CX_NW >> 1 == 0) ? 1 : (CX_NW >> 1)

CX_RX_PRFX_PAR_WD (CX_RASDP_EN) ? [function_of: CX_NW CX_NPRFX


CX_RAS_PROT_RANGE CX_RAS_PROT_TYPE] : 0

CXSCNTLCHKWIDTH CX_CXS_CNTLCHKWIDTH

Synopsys, Inc.
1070 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CXSCNTLWIDTH CX_CXS_CNTLWIDTH

CX_S_CPCIE_MODE CX_PCIE_MODE == SINGLE_CPCIE

CXSDATACHKWIDTH CX_CXS_DATACHKWIDTH

CXSDATAFLITWIDTH CX_CXS_DATAFLITWIDTH

CX_SEL_PHY_MODE CX_PCIE_MODE == DUAL_CMPCIE

CXS_FLIT_EQUALS_DATA_WIDTH (CX_CXS_DATAFLITWIDTH
==CX_CXS_CCIXDATAWIDTH)

CXS_FLIT_LOWER_DATA_WIDTH (CX_CXS_DATAFLITWIDTH<CX_CXS_CCIXDATAWIDTH)

CX_SKEW_MAC_IMPLE_CCIX20G_CORECLK 2

CX_SKEW_MAC_IMPLE_CCIX25G_CORECLK 2

CX_SKEW_MAC_IMPLE_GEN1_CORECLK (CX_NB_GEN1 == 4 || CX_NB_GEN1 == 2 ) ? 3 : 2

CX_SKEW_MAC_IMPLE_GEN2_CORECLK (CX_NB_GEN2 == 4 || CX_NB_GEN2 == 2 ) ? 3 : 2

CX_SKEW_MAC_IMPLE_GEN3_CORECLK 2

CX_SKEW_MAC_IMPLE_GEN4_CORECLK 2

CX_SKEW_MAC_IMPLE_GEN5_CORECLK 2

CX_SKEW_PIPEIF_CCIX20G_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_CCIX20G_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)

CX_SKEW_PIPEIF_CCIX20G_PCLK {[function_of: CX_SKEW_PIPEIF_CCIX20G_CORECLK


CX_PHY_NB_GEN4 CX_NB_GEN4 0]}

CX_SKEW_PIPEIF_CCIX25G_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_CCIX25G_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)

CX_SKEW_PIPEIF_CCIX25G_PCLK {[function_of: CX_SKEW_PIPEIF_CCIX25G_CORECLK


CX_PHY_NB_GEN4 CX_NB_GEN4 0]}

CX_SKEW_PIPEIF_GEN1_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_GEN1_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)

CX_SKEW_PIPEIF_GEN1_PCLK {[function_of: CX_SKEW_PIPEIF_GEN1_CORECLK


CX_PHY_NB_GEN1 CX_NB_GEN1 CX_PHY_GEN1_DP]}

CX_SKEW_PIPEIF_GEN2_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_GEN2_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)

CX_SKEW_PIPEIF_GEN2_PCLK {[function_of: CX_SKEW_PIPEIF_GEN2_CORECLK


CX_PHY_NB_GEN2 CX_NB_GEN2 CX_PHY_GEN2_DP]}

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1071


March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

CX_SKEW_PIPEIF_GEN3_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_GEN3_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)

CX_SKEW_PIPEIF_GEN3_PCLK {[function_of: CX_SKEW_PIPEIF_GEN3_CORECLK


CX_PHY_NB_GEN3 CX_NB_GEN3 0]}

CX_SKEW_PIPEIF_GEN4_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_GEN4_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)

CX_SKEW_PIPEIF_GEN4_PCLK {[function_of: CX_SKEW_PIPEIF_GEN4_CORECLK


CX_PHY_NB_GEN4 CX_NB_GEN4 0]}

CX_SKEW_PIPEIF_GEN5_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_GEN5_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)

CX_SKEW_PIPEIF_GEN5_PCLK {[function_of: CX_SKEW_PIPEIF_GEN5_CORECLK


CX_PHY_NB_GEN5 CX_NB_GEN5 0]}

CX_SLV_ISO_EN (SLV_CLK_DIFF_ENABLE ==1 &&


CX_ENHANCED_PM_EN ==1)

CX_S_MPCIE_MODE CX_PCIE_MODE == SINGLE_MPCIE

CX_SRIOV_ENABLE_VALUE CX_SRIOV_ENABLE

CXS_RX_BUFF_ADDRW CX_CXS_RX_BUFF_ADDRW

CXS_RX_BUFF_DATAW CX_CXS_RX_BUFF_DATAW

CXSRXREPWIDTH CX_CXS_RX_REPLICATION

CXS_TX_BUFF_ADDRW CX_CXS_TX_BUFF_ADDRW

CXS_TX_BUFF_DATAW CX_CXS_TX_BUFF_DATAW

CXSTXREPWIDTH CX_CXS_TX_REPLICATION

CX_SYS_INT_GRANT_EN (CX_IS_RC ! =1)

CX_TAG_SIZE (CX_10BITS_TAG == 1) ? 10: 8

CX_TLP_PREFIX_ENABLE (CX_NPRFX == 0) ? 0 : 1

CX_TLP_PREFIX_ENABLE_VALUE CX_TLP_PREFIX_ENABLE

CX_TPH_ENABLE_VALUE CX_TPH_ENABLE

CX_TX_HW_W_PAR 128 + CX_RAS_PCIE_HDR_PROT_WD

CX_VF_RBARS_INCLUDED {[ PortCfg::is_vfrbar_enabled ]}

CX_WIRE_SKEW_CCIX20G_PCLK {[function_of: CX_WIRE_SKEW_CCIX20G_NS


CX_PHY_NB_GEN4 0 50000 8]}

Synopsys, Inc.
1072 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

CX_WIRE_SKEW_CCIX25G_PCLK {[function_of: CX_WIRE_SKEW_CCIX25G_NS


CX_PHY_NB_GEN4 0 40000 8]}

CX_WIRE_SKEW_GEN1_PCLK {[function_of: CX_WIRE_SKEW_GEN1_NS


CX_PHY_NB_GEN1 CX_PHY_GEN1_DP 400000 10]}

CX_WIRE_SKEW_GEN2_PCLK {[function_of: CX_WIRE_SKEW_GEN2_NS


CX_PHY_NB_GEN2 CX_PHY_GEN2_DP 200000 10]}

CX_WIRE_SKEW_GEN3_PCLK {[function_of: CX_WIRE_SKEW_GEN3_NS


CX_PHY_NB_GEN3 0 125000 8]}

CX_WIRE_SKEW_GEN4_PCLK {[function_of: CX_WIRE_SKEW_GEN4_NS


CX_PHY_NB_GEN4 0 62500 8]}

CX_WIRE_SKEW_GEN5_PCLK {[function_of: CX_WIRE_SKEW_GEN5_NS


CX_PHY_NB_GEN5 0 31250 8]}

CX_XADM_DIAG_STATUS_BUS_WD (((CX_NCLIENTS + 2) * 3) + ((CX_NCLIENTS + 2) *


CX_NVC))

DATA_PAR_WD TRGT_DATA_PROT_WD

DBISLV_CLK_DIFF_ENABLE ((AXI_POPULATED || AHB_CLK_DIFF_ENABLE) &&


DBI_4SLAVE_POPULATED)

DCRD_WD SCALED_FC_SUPPORTED ? 16 : 12

DEFAULT_ACK_FREQUENCY 8'h0

DEFAULT_CURSOR_P0 (DEFAULT_GEN3_EQ_LOCAL_FS - FS_DIV_4)

DEFAULT_DO_DESKEW_FOR_SRIS CX_SRIS_SUPPORT

DEFAULT_DSP_16G_RX_PRESET_HINT1 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT10 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT11 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT12 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT13 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT14 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT15 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT2 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT3 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT4 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT5 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1073


March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

DEFAULT_DSP_16G_RX_PRESET_HINT6 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT7 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT8 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_RX_PRESET_HINT9 (DEFAULT_DSP_16G_RX_PRESET_HINT0)

DEFAULT_DSP_16G_TX_PRESET1 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET10 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET11 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET12 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET13 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET14 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET15 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET2 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET3 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET4 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET5 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET6 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET7 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET8 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_16G_TX_PRESET9 (DEFAULT_DSP_16G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET1 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET10 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET11 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET12 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET13 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET14 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET15 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET2 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET3 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET4 (DEFAULT_DSP_32G_TX_PRESET0)

Synopsys, Inc.
1074 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

DEFAULT_DSP_32G_TX_PRESET5 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET6 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET7 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET8 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_32G_TX_PRESET9 (DEFAULT_DSP_32G_TX_PRESET0)

DEFAULT_DSP_RX_PRESET_HINT1 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT10 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT11 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT12 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT13 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT14 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT15 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT2 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT3 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT4 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT5 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT6 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT7 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT8 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_RX_PRESET_HINT9 (DEFAULT_DSP_RX_PRESET_HINT0)

DEFAULT_DSP_TX_PRESET1 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET10 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET11 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET12 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET13 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET14 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET15 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET2 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET3 (DEFAULT_DSP_TX_PRESET0)

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1075


March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

DEFAULT_DSP_TX_PRESET4 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET5 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET6 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET7 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET8 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_DSP_TX_PRESET9 (DEFAULT_DSP_TX_PRESET0)

DEFAULT_ESM_DSP_TX_PRESET_20G1 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G10 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G11 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G12 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G13 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G14 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G15 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G2 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G3 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G4 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G5 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G6 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G7 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G8 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_20G9 (DEFAULT_ESM_DSP_TX_PRESET_20G0)

DEFAULT_ESM_DSP_TX_PRESET_25G1 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G10 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G11 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G12 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G13 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G14 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G15 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G2 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

Synopsys, Inc.
1076 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

DEFAULT_ESM_DSP_TX_PRESET_25G3 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G4 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G5 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G6 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G7 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G8 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_DSP_TX_PRESET_25G9 (DEFAULT_ESM_DSP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_20G1 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G10 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G11 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G12 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G13 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G14 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G15 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G2 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G3 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G4 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G5 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G6 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G7 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G8 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_20G9 (DEFAULT_ESM_USP_TX_PRESET_20G0)

DEFAULT_ESM_USP_TX_PRESET_25G1 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G10 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G11 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G12 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G13 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G14 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G15 (DEFAULT_ESM_USP_TX_PRESET_25G0)

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1077


March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

DEFAULT_ESM_USP_TX_PRESET_25G2 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G3 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G4 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G5 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G6 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G7 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G8 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_ESM_USP_TX_PRESET_25G9 (DEFAULT_ESM_USP_TX_PRESET_25G0)

DEFAULT_EXT_TAG_FIELD_SUPPORTED_0 (CX_MAX_TAG>31) ? 1 : 0

DEFAULT_FAST_LINK_SCALING_FACTOR 0

DEFAULT_GEN2_TXSWING 0

DEFAULT_GEN3_AUTONOMOUS_EQ_REQ_DISABLE 0

DEFAULT_GEN3_EQ_EVAL_2MS_DISABLE 1

DEFAULT_GEN3_LOWER_RATE_EQ_REDO_ENABLE CX_GEN3_SPEED

DEFAULT_GEN3_REQ_SEND_CONSECUTIVE_EIEOS_F 1
OR_PSET_MAP

DEFAULT_GEN3_RXEQ_PH01_EN 0

DEFAULT_GEN3_ZRXDC_NONCOMPL 1

DEFAULT_GEN4_USP_SEND_8GT_EQ_TS2_DISABLE 1

DEFAULT_LANE_SKEW_OFF_26 CX_PIPE_HYBRID_MODE

DEFAULT_PHANTOM_FUNC_SUPPORTED_0 2'h0

DEFAULT_PIPE_GARBAGE_DATA_MODE (RIO_POPULATED ==1) ? 1 : 0

DEFAULT_RXMARGIN_RATE_MODE CX_RXMARGIN_RATE_MODE_ENABLE

DEFAULT_RX_SERIALIZATION_Q_ALMOST_FULL_THR CX_RADM_SERQ_AF_NUM_QDWS
ESHOLD

DEFAULT_SURPRISE_DOWN_RPT_CAP SURPRISE_LINK_DOWN_SUPPORTED

DEFAULT_USP_16G_RX_PRESET_HINT1 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT10 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT11 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT12 (DEFAULT_USP_16G_RX_PRESET_HINT0)

Synopsys, Inc.
1078 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

DEFAULT_USP_16G_RX_PRESET_HINT13 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT14 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT15 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT2 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT3 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT4 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT5 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT6 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT7 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT8 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_RX_PRESET_HINT9 (DEFAULT_USP_16G_RX_PRESET_HINT0)

DEFAULT_USP_16G_TX_PRESET1 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET10 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET11 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET12 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET13 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET14 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET15 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET2 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET3 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET4 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET5 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET6 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET7 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET8 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_16G_TX_PRESET9 (DEFAULT_USP_16G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET1 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET10 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET11 (DEFAULT_USP_32G_TX_PRESET0)

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1079


March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

DEFAULT_USP_32G_TX_PRESET12 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET13 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET14 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET15 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET2 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET3 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET4 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET5 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET6 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET7 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET8 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_32G_TX_PRESET9 (DEFAULT_USP_32G_TX_PRESET0)

DEFAULT_USP_RX_PRESET_HINT1 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT10 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT11 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT12 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT13 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT14 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT15 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT2 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT3 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT4 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT5 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT6 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT7 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT8 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_RX_PRESET_HINT9 (DEFAULT_USP_RX_PRESET_HINT0)

DEFAULT_USP_TX_PRESET1 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET10 (DEFAULT_USP_TX_PRESET0)

Synopsys, Inc.
1080 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

DEFAULT_USP_TX_PRESET11 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET12 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET13 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET14 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET15 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET2 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET3 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET4 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET5 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET6 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET7 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET8 (DEFAULT_USP_TX_PRESET0)

DEFAULT_USP_TX_PRESET9 (DEFAULT_USP_TX_PRESET0)

DEMUX_EXCLUSIVE_WIDTH {[function_of: FLT_Q_DW_LENGTH_WIDTH


FLT_Q_IN_MEMBAR_RANGE_WIDTH
FLT_Q_ROM_IN_RANGE_WIDTH
FLT_Q_IO_REQ_IN_RANGE_WIDTH
FLT_Q_BYTE_CNT_WIDTH FLT_Q_CMPLTR_ID_WIDTH
FLT_Q_BCM_WIDTH
FLT_Q_CPL_LOWER_ADDR_WIDTH FLT_Q_TD_WIDTH
FLT_Q_EP_WIDTH FLT_Q_CPL_LAST_WIDTH ]}

DEVNUM_WD CX_DEVNUM_WD

DIRFEEDBACK_WD 6

DL_FEATURE_SUPPORTED DL_FEATURE_EN

DPC_CAP_INT_MSG_NUM 5'h0

DTIM_ATS_SID_LWR_WD DC_DTIM_ATS_SID_LWR_WD

DTIM_DATA_WD CC_DTIM_DATA_WD

DTIM_INTF_PROT_WD CC_DTIM_INTF_PROT_WD

DTIM_NUM_BYTES_PER_BEAT CC_DTIM_NUM_BYTES_PER_BEAT

DUAL_CMPCIE 2

DW (CC_DEVICE_TYPE ==CC_EP) ?
(RADM_PARBITS_OUT_VALUE ? (32*NW) +
DATA_PAR_WD : (32*NW) ) : (32*NW)

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1081


March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

DW_W_PAR (32*NW) + DATA_PAR_WD

ECC_PROTECTION_EN ((CX_RASDP_EN ==1) && (CX_RAS_PROT_TYPE ==0))

EP_INTERFACE_ACTIVATED ( (CC_DEVICE_TYPE ==CC_DM) || (CC_DEVICE_TYPE


==CC_EP) )

ERR_BUS_WD 13 + CX_DPC_ENABLE_VALUE

EXT_VF_TPH_ENABLE EXT_VF_TPH_ENABLE_VALUE

FLT_Q_ATTR_WIDTH CX_IDO_ENABLE ? 3 : 2

FLT_Q_AT_WIDTH ATS_RX_ENABLE ? 2 : 0

FLT_Q_BCM_WIDTH 1

FLT_Q_BYTE_CNT_WIDTH 12

FLT_Q_CCIX_WIDTH CX_CCIX_INTERFACE_ENABLE ? CX_CCIX_RX_WD : 0

FLT_Q_CMPLTR_ID_WIDTH 16

FLT_Q_COMMON_WIDTH {[function_of: FLT_Q_DESTINATION_WIDTH


FLT_Q_FMT_WIDTH FLT_Q_TYPE_WIDTH
FLT_Q_TC_WIDTH FLT_Q_ATTR_WIDTH
FLT_Q_LN_WIDTH FLT_Q_REQID_WIDTH
FLT_Q_TAG_WIDTH FLT_Q_FUNC_NMBR_WIDTH
FLT_Q_CPL_STATUS_WIDTH FLT_Q_VF_WIDTH
FLT_Q_PRFX_WIDTH]}

FLT_Q_CPL_LAST_WIDTH 1

FLT_Q_CPL_LOWER_ADDR_WIDTH 7

FLT_Q_CPL_STATUS_WIDTH 3

FLT_Q_DESTINATION_WIDTH 2

FLT_Q_DWADDR_WIDTH {[function_of: FLT_Q_ADDR_WIDTH ]}

FLT_Q_DW_LENGTH_WIDTH 10

FLT_Q_EP_WIDTH 1

FLT_Q_FMT_WIDTH 2

FLT_Q_FRSTDW_BE_WIDTH 4

FLT_Q_FUNC_NMBR_WIDTH CX_ARI_ENABLE ? CX_NFUNC_WD : 3

FLT_Q_HDR_RSVD_DW0_WIDTH CX_RX_HEADER_RSVD_ENABLE*8

FLT_Q_HDR_RSVD_DW2_WIDTH CX_RX_HEADER_RSVD_ENABLE

Synopsys, Inc.
1082 SolvNet Synopsys, Inc. 5.40a
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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

FLT_Q_IN_MEMBAR_RANGE_WIDTH {(CC_DEVICE_TYPE ==CC_RC || CC_DEVICE_TYPE


==CC_SW) ? 0 : [function_of: CC_DEVICE_TYPE CC_DM
CC_EP]}

FLT_Q_IO_REQ_IN_RANGE_WIDTH 1

FLT_Q_LN_WIDTH CX_LN_ENABLE ? 1 : 0

FLT_Q_LSTDW_BE_WIDTH 4

FLT_Q_PRFX_WIDTH CX_TLP_PREFIX_ENABLE ? CX_NPRFX*32 +


CX_RX_PRFX_PAR_WD : 0

FLT_Q_REQID_WIDTH 16

FLT_Q_ROM_IN_RANGE_WIDTH {EP_INTERFACE_ACTIVATED ==1}

FLT_Q_SATA_WIDTH SATA_CAP_ENABLE ? 1 : 0

FLT_Q_TAG_WIDTH CX_TAG_SIZE

FLT_Q_TC_WIDTH 3

FLT_Q_TD_WIDTH 1

FLT_Q_TH_WIDTH CX_TPH_ENABLE ? 1 : 0

FLT_Q_TYPE_WIDTH 5

FLT_Q_VF_WIDTH CX_SRIOV_ENABLE ? CX_NVFUNC_NUM_WD : 0

FLUSH_CNTRL_ENABLE (AXI_RADM_SEG_BUF_ENABLE || CX_DPC_ENABLE)

FOMFEEDBACK_WD 8

FREQ_125 2

FREQ_250 1

FREQ_500 0

FREQ_62_5 3

FS_DIV_4 {[function_of: DEFAULT_GEN3_EQ_LOCAL_FS]}

FULL_SWING 0

G1_PREPARE_SI ( ! CM_HSGEAR1_SPEED) ? 0 :
MPHY_HSG1_PREPARE_LENGTH

G2_PREPARE_SI ( ! CM_HSGEAR2_SPEED) ? 0 :
MPHY_HSG2_PREPARE_LENGTH*2

G3_PREPARE_SI ( ! CM_HSGEAR3_SPEED) ? 0 :
MPHY_HSG3_PREPARE_LENGTH*4

GEN2_DF 0

Synopsys, Inc.

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March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

GEN2_DISABLED 2

GEN2_DW 1

GEN3_DF 0

GEN3_DISABLED 2

GEN3_DP 3

GEN3_DW 1

GEN4_DF 0

GEN4_DISABLED 2

GEN4_DW 1

HCRD_WD SCALED_FC_SUPPORTED ? 12 : 8

INTERNAL_VF_ENABLE CX_SRIOV_ENABLE && (CX_INTERNAL_NVFUNC ! = 0)

INT_NVF CX_INTERNAL_NVFUNC

LBC_EXT_AW CX_LBC_EXT_AW

LONGER_LENGTH_C_G1_G2 (C_G1_SYNC_SI + G1_PREPARE_SI > C_G2_SYNC_SI +


G2_PREPARE_SI) ? C_G1_SYNC_SI + G1_PREPARE_SI
: C_G2_SYNC_SI + G2_PREPARE_SI

LONGER_LENGTH_NC_G1_G2 (NC_G1_SYNC_SI + G1_PREPARE_SI >


NC_G2_SYNC_SI + G2_PREPARE_SI) ?
NC_G1_SYNC_SI + G1_PREPARE_SI : NC_G2_SYNC_SI
+ G2_PREPARE_SI

LTSSM_EMU_IN_WD CX_LTSSM_EMU_WD

LTSSM_EMU_OUT_WD CX_LTSSM_EMU_WD

MASTER_POPULATED (AMBA_POPULATED)

MAX_LINK_SP (CX_SEL_PHY_MODE && (CX_MAX_CPCIE_SPEED


==5) ? 5 : CX_SEL_PHY_MODE &&
(CX_MAX_CPCIE_SPEED ==4) ? 4 :
CX_SEL_PHY_MODE && (CX_MAX_CPCIE_SPEED ==3)
? 3 : CX_SEL_PHY_MODE && (CX_MAX_CPCIE_SPEED
==2) ? 2 : CX_SEL_PHY_MODE &&
(CX_MAX_CPCIE_SPEED ==1) ? 1 : CX_GEN5_SPEED ?
5 : CX_GEN4_SPEED ? 4 : CX_GEN3_SPEED ? 3 :
CX_GEN2_SPEED ? 2 : 1)

MSI_PVM_EN_VALUE MSI_PVM_EN

Synopsys, Inc.
1084 SolvNet Synopsys, Inc. 5.40a
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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

NC_G1_SYNC_SI ( ! CM_HSGEAR1_SPEED) ? 0 :
(MPHY_NC_HSG1_SYNC_LENGTH > 31) ?
2^(MPHY_NC_HSG1_SYNC_LENGTH-32) :
MPHY_NC_HSG1_SYNC_LENGTH

NC_G2_SYNC_SI ( ! CM_HSGEAR2_SPEED) ? 0 :
(MPHY_NC_HSG2_SYNC_LENGTH > 31) ?
2^(MPHY_NC_HSG2_SYNC_LENGTH-32) :
MPHY_NC_HSG2_SYNC_LENGTH

NC_G3_SYNC_SI ( ! CM_HSGEAR3_SPEED) ? 0 :
(MPHY_NC_HSG3_SYNC_LENGTH > 31) ?
2^(MPHY_NC_HSG3_SYNC_LENGTH-32) :
MPHY_NC_HSG3_SYNC_LENGTH

NDQ CX_NDQ

NF CX_NFUNC

NHQ CX_NHQ

NL CX_NL

NQW CX_RADM_FORMQ_NQW

NVC CX_NVC

NVF CX_NVFUNC

NW CX_NW

NW_PRFX CX_NPRFX

ORIG_DATA_WD PHY_NB * 8

PCIE_ATS_INV_REQ_ITAG_WD DC_PCIE_ATS_INV_REQ_ITAG_WD

PCIE_CORE_DATA_BUS_WD (CX_NW * 32)

PCLK_RATE_WD (CX_CCIX_ESM_SUPPORT) ? 4 : 3

P_DATAQ_NECC_BITS (CX_RADMQ_MODE == 2) ? [function_of:


CX_RADM_SBUF_DATAQ_RAM_WD ] :
[pcie_cc_gen_necc_bits RADM_PQ_DWD]

PDWN_WIDTH CX_PHY_PDOWN_WD

PF_WD CX_NFUNC_WD

P_HDRQ_NECC_BITS (CX_RADM_SBUF_HDRQ_WD > 247) ? 10 : 9

PHY_IS_PIPE (CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==


PIPE_INTERFACE))

PHY_IS_V7 (CX_PHY_INTERFACE == V7_INTERFACE)

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1085


March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

PHY_NB CX_PHY_NB

PHY_RXSB_WD CX_PHY_RXSB_WD

PHY_RXSH_WD CX_PHY_RXSH_WD

PHY_TXEI_WD CX_PHY_TXEI_WD

PHY_VPT_DATA CX_PHY_VIEWPORT_DATA

PHY_VPT_NUM CX_PHY_NUM_MACROS

PIPE_DATA_WD (SNPS_RSVDPARAM_26_VALUE) ? (NL *


SERDES_DATA_WD) : (NL * ORIG_DATA_WD)

PIPE_INTERFACE 1

PM_MST_WD 5

PM_SLV_WD 5

PRFX_DW (CC_DEVICE_TYPE ==CC_SW) ? ((32*NW_PRFX) +


PRFX_PAR_WD) : (CX_TLP_PREFIX_ENABLE_VALUE ?
(32*NW_PRFX) + PRFX_PAR_WD : 32)

PRFX_PAR_WD CX_PRFX_PAR_WD

PRFX_W_PAR CX_TLP_PREFIX_ENABLE_VALUE ?
FLT_Q_PRFX_WIDTH : 32

P_R_WD PCLK_RATE_WD

PSET_ID_WD (CX_PIPE51_SUPPORT ==1) ? 6 :


(CX_PIPE44_SUPPORT ==1) ? 5 : 4

RADM_DATAQ_WD CX_NW + 5*CX_NDQ + CX_DW

RADM_DEPTH_DECOUPLE_VC0 0

RADM_DEPTH_DECOUPLE_VC1 CX_NVC<=1 && RADM_DEPTH_DECOUPLE_VC0

RADM_DLLP_ABORT_WD CUT_THROUGH_INVOLVED

RADM_ECRC_ERR_WD ECRC_ERR_PASS_THROUGH

RADM_EOT_WD 1

RADM_PARBITS_OUT 0

RADM_PARBITS_OUT_VALUE RADM_PARBITS_OUT

Synopsys, Inc.
1086 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

RADM_P_HWD {[function_of: CX_RADMQ_MODE


RADM_CPL_QMODE_VC0 TRGT1_POPULATE
FLT_Q_COMMON_WIDTH
TRGT1_TRGT0_INCLUSIVE_WIDTH
TRGT0_EXCLUSIVE_WIDTH
DEMUX_EXCLUSIVE_WIDTH]}

RADM_PQ_D_ADDRBITS CX_RADM_PQ_D_ADDRBITS

RADM_PQ_DPW {[function_of: RADM_PQ_DDP_VC0 ]}

RADM_PQ_DWD RADM_DATAQ_WD/CX_NDQ

RADM_PQ_H_ADDRBITS CX_RADM_PQ_H_ADDRBITS

RADM_PQ_H_DATABITS CX_RADM_PQ_H_DATABITS

RADM_PQ_H_DATABITS_O CX_RADM_PQ_H_DATABITS_OUT

RADM_PQ_HPW {[function_of: RADM_PQ_HDP_VC0 ]}

RADM_Q_DATABITS CX_RADM_Q_DATABITS

RADM_Q_DATABITS_O CX_RADM_Q_DATABITS_OUT

RADM_Q_D_CTRLBITS CX_RADM_Q_D_CTRLBITS

RADM_Q_H_CTRLBITS CX_RADM_Q_H_CTRLBITS

RADM_RFC_OUT_WD CX_ADM_RFC_WD

RADM_SBUF_HDRQ_ERR_ADDR_WD CX_RADM_SBUF_HDRQ_PW + CX_LOGBASE2(NHQ)

RADM_SEG_BUF (CX_RADMQ_MODE ==2)

RADM_SEG_BUF_CT_DPT_ADJ (CX_RADMQ_MODE ==2 &&


CUT_THROUGH_INVOLVED) ?
CX_RADM_DATASIZE*2/CX_NHQ + 4: 0

RADM_SEG_BUF_MIN_DPT 3

RADM_TLP_ABORT_WD 1

RADM_VFINDEX_REGOUT (VFINDEX_CALC_REGOUT)

RAM_PW CX_RADM_FORMQ_QDW_RAM_PW

RAM_WD CX_RADM_FORMQ_QDW_RAM_WD

RAS_BASE_PROT_WD (CX_RAS_PROT_TYPE ==1) ? 1:


(CX_RAS_PROT_RANGE<=16) ? 6:
(CX_RAS_PROT_RANGE ==32) ? 7:
(CX_RAS_PROT_RANGE ==64) ? 8: 9

RAS_DEFAULT_NULLIFY_EN 1

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1087


March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

RASDES_EC_INFO_CM CX_RAS_DES_EC_INFO_CMN_BW

RASDES_EC_INFO_PL CX_RAS_DES_EC_INFO_PLN_BW

RASDES_EC_RAM_ADDR_WIDTH CX_RAS_DES_EC_RAM_ADDR_WIDTH

RASDES_EC_RAM_DATA_WIDTH CX_RAS_DES_EC_RAM_DATA_WIDTH

RASDES_SD_INFO_CM CX_RAS_DES_SD_INFO_CMN_BW

RASDES_SD_INFO_PL CX_RAS_DES_SD_INFO_PLN_BW

RASDES_SD_INFO_PV CX_RAS_DES_SD_INFO_PVC_BW

RASDES_TBA_INFO_CM CX_RAS_DES_TBA_INFO_CMN_BW

RASDES_TBA_RAM_ADDR_WIDTH CX_RAS_DES_TBA_RAM_ADDR_WIDTH

RASDES_TBA_RAM_DATA_WIDTH CX_RAS_DES_TBA_RAM_DATA_WIDTH

RASDP_BYPASS_HDR_PROT_WD CX_RASDP_BYPASS_HDR_PROT_WD

RASDP_DATAQ_ERR_SYND_WD CX_RADM_SBUF_DATAQ_PROT_WD

RASDP_FORMQ_ERR_SYND_WD CX_RASDP_FORMQ_ERR_SYND_WD

RASDP_HDRQ_ERR_SYND_WD CX_RASDP_HDRQ_ERR_SYND_WD

RASDP_RBUF_ERR_SYND_WD RBUF_PROT_WD

RASDP_SOTBUF_ERR_SYND_WD CX_RAS_SOTBUF_PROT_WD

RASDP_TRGT1_HDR_PROT_WD CX_RASDP_TRGT1_HDR_PROT_WD

RAS_PCIE_HDR_PROT_WD CX_RAS_PCIE_HDR_PROT_WD

RAS_RAM_BASE_PROT_WD (CX_RAS_RAM_PROT_RANGE ==32) ? 7: 8

RATE_WIDTH CX_PHY_RATE_WD

RBUF_PROT_WD {(CX_RAS_EN ==1) ? [function_of: (32*CX_NW)


CX_RBUF_CTRL_WD CX_RASDP_EN
CX_RAS_PROT_TYPE CX_RAS_PROT_RANGE
CX_RAS_RAM_PROT_RANGE RAS_BASE_PROT_WD
RAS_RAM_BASE_PROT_WD ]: 0}

RBUF_PW {[function_of: CX_RBUF_DEPTH]}

RIO_POPULATED 0

RTLH_RAMD_IN_WD CX_ADM_TLH_WD

RX_NDLLP (NW>>1 == 0) ? 1 : NW>>1

RX_PSET_WD 3

RX_SERIALIZATION_OVFLW_PRVNTN CX_NW ==16

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1088 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

RX_TLP (NW ==16) ? 4 : (NW ==8) ? 2 : 1

SATA_CAP_ENABLE 1'b0

SCALED_FC_SUPPORTED FC_SCALE_EN

S_CFG_COMPLETE 6'h0B

S_CFG_IDLE 6'h0C

S_CFG_LANENUM_ACEPT 6'h0A

S_CFG_LINKWD_ACEPT 6'h08

S_CFG_LINKWD_START 6'h07

S_DETECT_ACT 6'h01

S_DETECT_QUIET 6'h00

S_DETECT_WAIT 6'h06

S_DISABLED 6'h19

S_DISABLED_ENTRY 6'h17

S_DISABLED_IDLE 6'h18

SERDES_DATA_WD PHY_NB * 10

S_HOT_RESET 6'h1F

S_HOT_RESET_ENTRY 6'h1E

SINGLE_CPCIE 0

SINGLE_MPCIE 1

S_L0 6'h11

S_L0S 6'h12

S_L123_SEND_EIDLE 6'h13

S_L1_EXIT 6'h2C

S_L1_IDLE 6'h14

S_L2_IDLE 6'h15

S_L2_WAKE 6'h16

SLAVE_BUS_ADDR_WIDTH_IS_64 (SLAVE_BUS_ADDR_WIDTH ==64)

SLAVE_POPULATED (AMBA_POPULATED)

S_LPBK_ACTIVE 6'h1B

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1089


March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

S_LPBK_ENTRY 6'h1A

S_LPBK_EXIT 6'h1C

S_LPBK_EXIT_TIMEOUT 6'h1D

SNPS_RSVDPARAM_1 (CX_NW == 16) ? 1 : 0

SNPS_RSVDPARAM_15 0

SNPS_RSVDPARAM_17 0

SNPS_RSVDPARAM_21 0

SNPS_RSVDPARAM_22 (CX_GEN4_SPEC07_RM)

SNPS_RSVDPARAM_23 SNPS_RSVDPARAM_35 ? 4096 : 256

SNPS_RSVDPARAM_24 CX_EXTENSIBLE_VFUNC ? 0xFFFF :


SNPS_RSVDPARAM_35 ? 4096 : 256

SNPS_RSVDPARAM_25 0

SNPS_RSVDPARAM_26 0

SNPS_RSVDPARAM_26_VALUE SNPS_RSVDPARAM_26

SNPS_RSVDPARAM_28 CX_PIPE_MSGBUS_SUPPORT ||
CX_PIPE_LEGACY_MSGBUS_SUPPORT

SNPS_RSVDPARAM_29 0

SNPS_RSVDPARAM_30 (SNPS_RSVDPARAM_31) ? 8 : (( CX_MAX_MTU / (4 *


CX_NW) ) + 8)

SNPS_RSVDPARAM_31 0

SNPS_RSVDPARAM_32 0

SNPS_RSVDPARAM_33 0

SNPS_RSVDPARAM_35 0

SNPS_RSVDPARAM_4 CX_DMA_PF_ENABLE

SNPS_RSVDPARAM_42 ((CX_PHY_FREQ == FREQ_125) &&


(CX_PHY_GEN2_MODE == GEN2_DF) &&
(CX_PHY_GEN3_MODE == GEN3_DW) &&
(CX_PHY_GEN4_MODE == GEN4_DW) &&
(CX_PHY_INTERFACE == V7_INTERFACE)) ? 1 : 0

SNPS_RSVDPARAM_9 0

Synopsys, Inc.
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PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

SOTBUF_L2DEPTH {[function_of: CX_DL_NB CX_NL CX_MAX_MTU


CX_ECRC_ENABLE CX_TLP_PREFIX_ENABLE_VALUE
CX_NPRFX CX_INTERNAL_DELAY CX_MAX_L0S_LTIME
CX_RBUF_AUTOSIZE CX_SOTBUF_DEPTH
CX_GEN5_SPEED CX_GEN4_SPEED CX_GEN3_SPEED
CX_5GTS_SPEED CX_RETIMER_LATENCY]}

SOTBUF_PW SOTBUF_L2DEPTH

SOTBUF_WD SOTBUF_WIDTH

SPEED_DISABLED 2

SPEED_DW 1

SPLIT_SUPPORT (CC_RESPONSE_MODE ==1)

S_POLL_ACTIVE 6'h02

S_POLL_COMPLIANCE 6'h03

S_POLL_CONFIG 6'h04

S_PRE_DETECT_QUIET 6'h05

S_RCVRY_EQ0 6'h20

S_RCVRY_EQ1 6'h21

S_RCVRY_EQ2 6'h22

S_RCVRY_EQ3 6'h23

S_RCVRY_IDLE 6'h10

S_RCVRY_LOCK 6'h0D

S_RCVRY_RCVRCFG 6'h0F

S_RCVRY_SPEED 6'h0E

TRGT0_EXCLUSIVE_WIDTH {[function_of: FLT_Q_IN_MEMBAR_RANGE_WIDTH


FLT_Q_ROM_IN_RANGE_WIDTH
FLT_Q_IO_REQ_IN_RANGE_WIDTH
FLT_Q_FRSTDW_BE_WIDTH FLT_Q_DWADDR_WIDTH
FLT_Q_LSTDW_BE_WIDTH
FLT_Q_DW_LENGTH_WIDTH]}

TRGT1_POPULATE 1

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1091


March 2019 DesignWare.com
Internal Parameter Descriptions PCI Express SW Controller Databook

Parameter Name Equals To

TRGT1_TRGT0_INCLUSIVE_WIDTH {[function_of: FLT_Q_DW_LENGTH_WIDTH


FLT_Q_IN_MEMBAR_RANGE_WIDTH
FLT_Q_ROM_IN_RANGE_WIDTH
FLT_Q_IO_REQ_IN_RANGE_WIDTH
FLT_Q_FRSTDW_BE_WIDTH FLT_Q_ADDR_WIDTH
FLT_Q_TD_WIDTH FLT_Q_EP_WIDTH
FLT_Q_CPL_LAST_WIDTH FLT_Q_LSTDW_BE_WIDTH
FLT_Q_SATA_WIDTH FLT_Q_AT_WIDTH
FLT_Q_TH_WIDTH FLT_Q_HDR_RSVD_DW0_WIDTH
FLT_Q_HDR_RSVD_DW2_WIDTH FLT_Q_CCIX_WIDTH]}

TRGT_DATA_PROT_WD {(CX_RASDP_EN ==1) ? [function_of: (32*CX_NW)


CX_RAS_PROT_RANGE RAS_BASE_PROT_WD]:0}

TRGT_DATA_WD (CX_RASDP_EN) ? (32*CX_NW) +


TRGT_DATA_PROT_WD : (32*CX_NW)

TX_COEF_WD 18

TX_CRSR_WD 6

TX_DEEMPH_WD CX_PHY_TXDEEMPH_WD

TX_FS_WD 6

TX_HW_W_PAR 128 + RAS_PCIE_HDR_PROT_WD

TX_PSET_WD 4

UNROLL_ATU_SIZE {CC_UNROLL_EN ==1 ? ([function_of:


CX_ATU_NUM_INBOUND_REGIONS
CX_ATU_NUM_OUTBOUND_REGIONS]):0}

UNROLL_DMA_SIZE {CC_UNROLL_EN ==1 ? ([function_of:


CC_NUM_DMA_RD_CHAN CC_NUM_DMA_WR_CHAN]
+ 512):0}

V7_INTERFACE 2

VF_AER_EN VF_AER_ENABLE

VF_BAR0_RESIZABLE_0 (VF_BAR0_SIZING_SCHEME_0 ==2) ? 1 : 0

VF_BAR1_RESIZABLE_0 (VF_BAR1_SIZING_SCHEME_0 ==2) ? 1 : 0

VF_BAR3_RESIZABLE_0 (VF_BAR3_SIZING_SCHEME_0 ==2) ? 1 : 0

VF_BAR4_RESIZABLE_0 (VF_BAR4_SIZING_SCHEME_0 ==2) ? 1 : 0

VF_BAR5_RESIZABLE_0 (VF_BAR5_SIZING_SCHEME_0 ==2) ? 1 : 0

VF_PASID_ENABLE 0

VF_TPH_ENABLE VF_TPH_ENABLE_VALUE

Synopsys, Inc.
1092 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions

Parameter Name Equals To

VGA_SUPPORT (CC_DEVICE_TYPE ==CC_SW)

WIDTH_WIDTH CX_PHY_WIDTH_WD

XADM_RFC_IN_WD CX_ADM_RFC_WD

XADM_XTLH_OUT_WD CX_ADM_TLH_WD

Synopsys, Inc.

5.40a Synopsys, Inc. SolvNet 1093


March 2019 DesignWare.com

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