DWC Pcie CTL SW Databook
DWC Pcie CTL SW Databook
Version 5.40a
March 2019
PCI Express SW Controller Databook
Synopsys, Inc.
www.synopsys.com
Synopsys, Inc.
2 SolvNet Version 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Contents
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1 General Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.3 Features and Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4 Frequency, Speed, and Width Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.6 Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 2
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.2 RAM Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.3 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.4 Reset Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.5 Receive Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Chapter 3
Controller Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.2 Link Establishment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.3 Transmit TLP Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.4 Receive TLP Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.5 Register Module, LBC, and DBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.6 Reliability, Availability, and Serviceability (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.7 Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
3.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
3.9 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
3.10 Internal Address Translation Unit (iATU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
3.11 Gen2/3/4/5 Speed Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
3.12 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
3.13 Completion Timeout Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
3.14 Crosslink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
3.15 TLP Processing Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
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Chapter 4
Signal Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
4.1 Transmit Interfaces (XALI0/1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
4.2 CCIX Transmit Interface (XALI_CCIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
4.3 Receive Bypass Interface (RBYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
4.4 Receive Request Interface (TRGT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
4.5 CCIX Receive Request Interface (TRGT1_CCIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
4.6 Data Bus Interface (DBI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
4.7 External Local Bus Interface (ELBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
4.8 Message Signaled Interrupt (MSI) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
4.9 MSI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
4.10 Vendor Message Interface (VMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
4.11 System Information Interface (SII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
4.12 PIPE Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
4.13 PHY Register Bus Interface (PRBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Chapter 5
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
5.1 Distributed Translation Interface AXI4-Stream Master Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
5.2 Distributed Translation Interface AXI4-Stream Slave Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
5.3 Distributed Translation Interface Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
5.4 Distributed Translation Interface Invalidate Request Timeout Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
5.5 CXS Rx Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
5.6 CXS Tx Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
5.7 XALI0 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
5.8 XALI1 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
5.9 XALI2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
5.10 XALI_CCIX Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
5.11 ADM adaptor Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
5.12 Bypass Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
5.13 RTRGT1 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5.14 TRGT1_CCIX Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
5.15 Clock and Reset (APM) Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
5.16 Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
5.17 DBI Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
5.18 ELBI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
5.19 CXS Rx FIFO RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
5.20 CXS Tx FIFO RAM Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
5.21 Receive Data Queue RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
5.22 Receive Formation Queue RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
5.23 Receive Header Queue RAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
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Contents PCI Express SW Controller Databook
Chapter 6
Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
6.1 Main Features Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
6.2 Basic Features Config / PCIe Basic Features Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
6.3 Basic Features Config / Common Basic Features Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
6.4 DMA Configuration Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
6.5 Basic AXI Config Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
6.6 Basic AXI Config / PCIe TAGs and AXI IDs Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
6.7 Basic AXI Config / PCIe and AHB TAGs Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
6.8 Device-Wide Optional Non-PCIe Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
6.9 Advanced AXI Config / Advanced AHB Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
6.10 Advanced AXI Config / Advanced AXI Config Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
6.11 Device-Wide PCIe Features and Capabilities Config / MSI/MSI-X Capability Parameters. . . . . . . . . 703
6.12 Device-Wide PCIe Features and Capabilities Config / PCIe Capability Parameters . . . . . . . . . . . . . . . 705
6.13 Device-Wide PCIe Features and Capabilities Config / PF Extended Capabilities Parameters. . . . . . . 714
6.14 Device-Wide PCIe Features and Capabilities Config / VC Capability Parameters . . . . . . . . . . . . . . . . 718
6.15 Device-Wide PCIe Features and Capabilities Config / Slot ID Capability Parameters . . . . . . . . . . . . . 719
6.16 Device-Wide PCIe Features and Capabilities Config / AtomicOp Support Options Parameters . . . . 720
6.17 Device-Wide PCIe Features and Capabilities Config / Readiness Support Options Parameters. . . . . 722
6.18 Device-Wide PCIe Features and Capabilities Config / Lightweight Notification Support Options Pa-
rameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
6.19 Device-Wide PCIe Features and Capabilities Config / Other Optional PCIe Features Parameters. . . 726
6.20 Device-Wide PCIe Features and Capabilities Config / SR-IOV Related Features Parameters . . . . . . . 728
6.21 Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities Parameters . . . . . . 730
6.22 Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability Parameters. . .
738
6.23 Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability / L1 Substates
Capability Register Defaults Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
6.24 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support Parameters . . . . . . . . . . . . 741
6.25 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support / PASID Capability Register
Defaults Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
6.26 Device-Wide PCIe Features and Capabilities Config / Precision Time Management Support Options Pa-
rameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
6.27 Device-Wide PCIe Features and Capabilities Config / Secondary PCIe Extended Capability Parameters
744
6.28 Device-Wide PCIe Features and Capabilities Config / CCIX Transport DVSEC Parameters . . . . . . . 746
6.29 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Express Capability
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
6.30 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / MSI-X Register Configu-
ration (PF0) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
6.31 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Advanced Error Register
Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
6.32 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / TLP Processing Hints
Register Configuration (PF0) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
6.33 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ATS Register Configura-
tion (PF0) Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
6.34 Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ACS Register Configura-
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Chapter 7
Cache Coherent Interconnect for Accelerators (CCIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
7.1 CCIX PCIe Controller Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
7.2 CCIX PCIe Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
Chapter 8
Embedded EndPoint (Switch DSP Integrated EndPoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
8.2 Advantages of Embedded EndPoint Solution Over Pipe Connected EndPoint . . . . . . . . . . . . . . . . . . . . 895
8.3 Embedded EndPoint Delivery Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
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Contents PCI Express SW Controller Databook
Appendix A
Advanced Information: Gen3/4/5 Equalization Details and Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
A.1 Equalization Overview and Synopsys-Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
A.2 Detailed Equalization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
A.3 Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Appendix B
Advanced Information: Lane Reversal and Broken Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Appendix C
Advanced Information: Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
C.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
C.2 Local Digital Loopback (PIPE/RMMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
C.3 Local Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
C.4 Remote Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Appendix D
Advanced Information: Lane Deskew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
D.1 Conventional PCIe Deskew Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Appendix E
Advanced Information: Clock and Data Crossing (CDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
E.1 CDC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
E.2 Port Clocking and Input Synchonizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
E.3 CDC Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Appendix F
Advanced Information: Reset Domain Crossing (RDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Appendix G
Advanced Information: VC-Based Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
G.1 VC-Based Arbitration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
G.2 VC-Based WRR Arbitration Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Appendix H
Advanced Information: Advanced Filtering and Routing of TLPs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
H.1 Filtering Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
H.2 Filtering Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
H.3 Upstream Port Routing Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
H.4 Request TLP Routing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
H.5 Processing Illegal CFG TLPs and CFG1-CFG0 Conversion in Each PCI Express Port Type . . . . . . . . . 966
Appendix I
Advanced Information: Advanced Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
I.1 PCIe Ordering Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
I.2 Inbound (Receive) Order Enforcement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
I.3 Outbound (Transmit) Order Enforcement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Appendix J
Advanced Information: Advanced LBC and DBI Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
J.1 Programming Examples: CDM / ELBI Register Space Access Through DBI. . . . . . . . . . . . . . . . . . . . . . . 975
J.2 Configuration Intercept Controller (CIC) for USP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
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Appendix K
Advanced Information: How to Tie Off Unused Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
K.1 Conventional PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
Appendix L
Advanced Information: Advanced Error Handling for Received TLPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
L.1 Routing of Request TLPs with Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
L.2 Routing of Completions with Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
L.3 Application Error Reporting Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
Appendix M
Advanced Information: Calculating Gen1 PCI Express Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
M.1 PCI Express Bandwidth and Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
M.2 Effective Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
Appendix N
Advanced Information: Advanced Routing of Received Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
N.1 Routing of Received Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
Appendix O
Advanced Information: Replay Buffer Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
Appendix P
Advanced Information: Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
Appendix Q
Introduction to PCIe Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
Q.1 Switch Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
Q.2 Digital IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
Q.3 Mixed Signal IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
Q.4 Switch Application Logic Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
Q.5 Advanced Switch Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Q.6 Non-Standard Switch Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
Appendix R
Advanced Information: Area, Power Estimates, and RAM Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
R.1 Area Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
R.2 Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
R.3 RAM Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Appendix S
Advanced Information: Flow Control Credit Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
S.1 Calculation of Flow Control Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
S.2 Calculation of Initial Flow Control Credits and Receive Buffer Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
Appendix T
Advanced Information: Serialization Queue Almost Full Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
T.1 Serialization Queue Almost Full Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
T.2 Serialization Queue Input and Output Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Appendix U
Internal Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
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Revision History PCI Express SW Controller Databook
Revision History
■ A full list of functional (RTL) changes is in the “Release Notes: PCI Express Cores” document.
■ A change-tracked version of this databook is available at
https://www.synopsys.com/dw/doc.php/iip/DWC_pcie/5.40a/doc/DWC_pcie_ctl_sw_databook_change.pdf
■ The change-tracked version does not indicate minor changes that has been made for readability, formatting, and
so on. It only indicates changes to functionality, new features, and major rewrites.
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PCI Express SW Controller Databook Preface
Preface
A single coreKit is provided for DesignWare PCI Express DM, EP, RC, and SW controller ports. Using the
Device Type parameter (CC_DEVICE_TYPE) in coreConsultant GUI (as shown in Figure 1) you can configure
the controller as a:
■ 0 (EP): Endpoint port
■ 1 (RC): Root complex port
■ 2 (DM): Dual Mode port (pin-selectable EP/RC)
■ 3 (SW): Switch port (pin-selectable upstream/downstream)
After the PCIe controller is configured as DM, EP, RC, or SW port, depending upon the features licensed,
the PCIe controller can be identified as:
■ Native PCIe controller (without AMBA bridge): Basic PCIe controller which has its own non-stan-
dard, proprietary dedicated bus interface to your application.
■ CCIX PCIe controller (without/with AMBA bridge): PCIe controller which has its own non-standard,
proprietary dedicated CCIX interface to your application (when not using the AMBA bridge) or CCIX
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compliant AMBA bridge interface to your application (when using the AMBA bridge). To enable CCIX
features, set the parameter CX_CCIX_ENABLE to 1.
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PCI Express SW Controller Databook Preface
Product Codes
Table 1 lists the product codes and product names for DesignWare PCI Express controller ports.
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CCIX
Automotive
CCIX Automotive
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PCI Express SW Controller Databook Preface
Reference Documentation
After installing the controller, the DWC PCI Express documents can be found under:
$DESIGNWARE_HOME/iip/DWC_pcie_ctl/latest/doc.
When you create a workspace in coreConsultant,
■ Pre-configuration, the DWC PCI Express documents for all four ports are available in <work-
space>/doc.
■ Post-configuration, only the documents corresponding to your configured controller port are avail-
able in <workspace>/doc.
When viewing documents from coreConsultant GUI (as shown in Figure 2),
■ Pre-configuration, the coreConsultant GUI points to the DM port documents.
■ Post-configuration, the coreConsultant GUI points to your configured controller port documents.
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Web Resources
■ DesignWare IP product information: https://www.synopsys.com/designware-ip.html
■ Your custom DesignWare IP page: https://www.synopsys.com/dw/mydesignware.php
■ Documentation through SolvNet: https://solvnet.synopsys.com (Synopsys password required)
■ Synopsys Common Licensing (SCL):https://www.synopsys.com/support/licensing-installa-
tion-computeplatforms/licensing.html
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PCI Express SW Controller Databook Preface
Term Description
CPL Completion
Downstream port
DSP
Refers to root complex (RC) port and/or switch downstream port.
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Term Description
PCIe transactions that enter the controller from the wire side of the controller (PCIe wire).
Inbound traffic
These transactions are delivered to your application side.
Identifies the basic PCIe controller (without AXI Bridge) which has its own non-standard,
Native PCIe controller
proprietary dedicated bus interface to your application.
Number of Functions
NF
The value “1” represents one function.
NP Non-posted
Transactions that enter the controller from your application side of the controller. These
Outbound traffic
transactions are passed to the native controller, where they are sent out onto the PCIe wire.
P Posted
Standard PIPE interface between the PCI Express PHY and the controller. If you set
PIPE
PHY_TYPE to be the Synopsys PHY, then the PHY is included inside the controller.
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PCI Express SW Controller Databook Preface
Term Description
RAM Interface
RAMI Optional top-level interface to connect external RAMs for the retry buffer and receive
queues. If you do not select the optional top-level RAMI, the RAMs reside inside the
top-level hierarchy of the controller.
Software Software is often divided into application software and system software.
System software includes System Firmware (BIOS, UEFI), Operating System, VMM, power
management services, device drivers, user-mode services, kernel mode services, platform
vendor's add-on to the Operating System. It is also responsible for managing hardware
System Software
components and providing basic non-task-specific functions.
Configuration Software is an example of system software responsible for accessing
Configuration Space and configuring the PCI/PCIe bus.
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Term Description
Generic term for customer specific software (system as well as application, depending on
User Application
the context).
Upstream port
USP
Refers to endpoint port and/or switch upstream port.
VC Virtual Channel
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PCI Express SW Controller Databook Preface
Customer Support
To obtain support for your product:
■ First, prepare the following debug information, if applicable:
❑ For environment setup problems or failures with configuration, simulation, or synthesis that occur
within coreConsultant or coreAssembler, use the following menu entry:
File > Build Debug Tar-file
Check all the boxes in the dialog box that apply to your issue. This menu entry gathers all the
Synopsys product data needed to begin debugging an issue and writes it to the file <controller tool
startup directory>/debug.tar.gz.
❑ For simulation issues outside of coreConsultant or coreAssembler:
■ Create a waveforms file (such as VPD or VCD)
■ Identify the hierarchy path to the DesignWare instance
■ Identify the timestamp of any signals or locations in the waveforms that are not understood Then,
contact Support Center, with a description of your question and supplying the previous information,
using one of the following methods:
❑ For fastest response, use the SolvNet website. When you fill in your information as explained later,
your issue is automatically routed to a support engineer who is experienced with your product.
The Sub Product 1 entry is critical for correct routing.
Go to http://solvnet.synopsys.com/EnterACall and click on the link to enter a call. Provide the
requested information, including:
■ Customer Tracking Number: Enter your project name. Use the same name for cases related to
the same project.
■ Product: DesignWare Cores
■ Sub Product 1: PCI Express
■ Product Version: 5.10a (for example)
■ Problem Type:
■ Issue Severity:
■ Problem Title: Provide a brief summary of the issue or list the error message you have encoun-
tered
■ Problem Description: For simulation issues, include the timestamp of any signals or locations in
waveforms that are not understood
After creating the case, attach any debug files you created in the previous step.
❑ Or, send an e-mail message to [email protected] (your e-mail is queued and then, on
a first-come, first-served basis, is manually routed to the correct support engineer):
■ Include the Product name, Sub Product name
■ For simulation issues, include the timestamp of any signals or locations in waveforms that are
not understood
■ Attach any debug files you created in the previous step.
❑ Or, telephone your local support center:
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■ North America: Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific time, Monday through
Friday.
■ All other countries: https://www.synopsys.com/support/global-support-centers.html
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PCI Express SW Controller Databook Product Overview
1
Product Overview
This section gives an overview of the PCI Express controller. The topics in this section are:
■ “General Product Description” on page 24
■ “Applications” on page 26
■ “Features and Limitations” on page 27
■ “Frequency, Speed, and Width Support” on page 29
■ “Deliverables” on page 40
■ “Standards” on page 41
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Attention The Synopsys PCI Express IP does not implement a full switch.
To implement a full switch, you must add your application routing logic (connected to the application client
interface ) and other support logic (including clock and reset generation). For more information, see
“Integrating with your Application RTL” section in the “Integrating the controller with the PHY, or
Application RTL, or Verification IP” chapter of the User Guide.
The PCIe controller implements the three PCI Express protocol layers (Transaction layer, Data Link layer,
and the MAC portion of the physical layer) in synthesizable RTL. It also implements the
application-dependent functionality of the PCI Express Transaction Layer for packet transmission, which is
located between your application logic and the PCI Express protocol layers.
A complete PCI Express port solution includes the controller, an analog PHY macro, and application logic to
source and sink data. The physical layer is split across the PIPE and controller such that the MAC
functionality (LTSSM, lane-to-lane deskew) is in the controller and the PHY functionality is implemented in
the PIPE-compliant PHY. The PHY is outside of the controller, interfacing through the standard PIPE
interface. For more information, see “Integrating the Controller with the PHY” section in the “Integrating
the Controller with the PHY, or Application RTL, or Verification IP” chapter of the User Guide.
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PCI Express SW Controller Databook General Product Description
Figure 1-1 Three Instances of Switch Port Controller in a Three-Port PCI Express Switch
PCI Express Link to Upstream Device
PIPE-Compliant PHY
Transaction Layer
Data Link Layer
Physical Layer(MAC)
Application Dependent
part of the
Transaction Layer
Switch Port 0
Application
Interfaces
Switch Application Logic
Application Application
Interfaces Interfaces
PCI Express Link to Downstream Device PCI Express Link to Downstream Device
Customer Logic
PCIe Protocol
Synopsys Implementation
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1.2 Applications
Typical applications for a PCI Express component built with the controller include:
■ Hyper-transport to PCI Express bridge
■ SATA to PCI Express bridge
■ Transparent PCI Express switch (For more information, see “Non-transparent Switches” on page 1025)
■ Non-Transparent PCI Express switch
The switch port controller is configurable as Upstream Switch or Downstream Switch port/device type but
is not configurable as a PCI Express to PCI/PCI-X bridge or PCI/PCI-X to Express bridge port/device type.
For more information on switches see “Introduction to PCIe Switches” on page 1006.
Note The switch port controller is not intended for use in a PCI Express endpoint or root complex.
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PCI Express SW Controller Databook Features and Limitations
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■ Configuration Intercept Controller to allow your application modify CFG access from wire
■ Multiple Virtual Channels (VCs), Traffic Classes (TCs), and Quality of Service (QOS)
■ Bypass, Cut-through, and Store-and-forward Queue Modes for Rx TLPs
■ Configurable Receive and Retry Buffer sizes
■ Configurable Max_Payload_Size size (128 bytes to 4 KB)
■ Configurable Filtering Rules for Posted, Non-posted, and Completion Traffic
■ Configurable BAR Filtering, I/O Filtering, Configuration Filtering and Completion Lookup/Timeout
■ Three Application Transmit Clients
■ Type 1 Configuration space
■ Application-initiated Manual Lane Reversal/flip for situations where controller does not detect Lane
0
■ MSI and MSI-X with Per-Vector Masking (PVM)
■ Configuration as Upstream Switch or Downstream Switch port/device type. It is NOT Configurable
as a PCI Express to PCI/PCI-X bridge or PCI/PCI-X to Express bridge port/device type
■ Prefetchable Memory Space
■ Transaction Filtering and Routing Look up
■ Configurable VC/TC Mapping
■ PHY Register access (Only for PHYs supporting Control Register Parallel Interface)
■ Automotive support
■ Transmit Interface Progression Detection
■ CDM Register Check
■ CCIX Support
Some features require an additional license. Licensing requirements are given in the
Attention
Installation Guide
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PCI Express SW Controller Databook Frequency, Speed, and Width Support
Figure 1-2 Conventional PCIe Frequency, Speed, and Width Configuration Parameters in coreConsultant GUI
After you have set these parameters, the coreConsultant tool cross-references your available licenses and
automatically calculates the following values:
■ Controller PIPE Lane Width (CX_PIPE_WIDTH_ bits or CX_NB bytes)
■ PHY PIPE Lane Width: (CX_PHY_PIPE_WIDTH_ bits or CX_PHY_NB bytes)
■ Datapath Width: (CX_NW/32 bits rounded up to multiple of 32 or CX_NL*CX_NB bytes)
■ CX_FREQ_STEP_DOWN_EN. This is the enable for the “Frequency Step Module (CX_FREQ_STEP_EN
=1)” on page 38
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■ Dynamic Pacing (DP): DP is a rate reduction mode for the PIPE interface that allows for a higher clock
rate to be used at a slower data rate. It uses the mac_phy_txdatavalid and phy_mac_rxdatavalid
Gen3 signals to obtain the slower effective rate by toggling them every other clock (2:1 DP) or every
fourth clock (4:1 DP). This controls the number of valid symbols per one, two, or four clock cycles.
When DP is not used in a lower speed mode, these signals must be held high. At Gen3 rate these
signals are also used for regular de-assertion for 128b/130b encoding and decoding. The mac_-
phy_txdatavalid and phy_mac_rxdatavalid signals are present on all Gen3 and Gen4 configura-
tions. However, DP is only enabled for some controller/PHY combinations as indicated in Table 1-5.
For more information on the usage of the mac_phy_txdatavalid and phy_mac_rxdatavalid
signals, see “Signal Interfaces” on page 278.
■ The controller and PHY can have different Gen2 modes. For example, you can configure
Note the controller for Dynamic Frequency and the PHY for Dynamic Width. This is also true for
Gen3, Gen4, and Gen5.
■ For more information, see “Gen2/3/4/5 Speed Modes” on page 206, “Gen3 8.0 GT/s Oper-
ation” on page 206, and “Gen4 16.0 GT/s Operation” on page 207.
Table 1-1 Timing Critical Parameter Setting for 1Ghz Clock Frequency
3 or 4
RASDP
Data path Use Parity for Data path protection
Datapath CX_RASDP High
protection (CX_RASDP = 1 or 2)
Protection
with ECC
CX_INTERNAL_ATU_ENABLE
Address
CX_ATU_NUM_OUTBOUND_REGION >= 64
Translation High Reduce the number of regions
S Regions
Unit (ATU)
CX_ATU_NUM_INBOUND_REGIONS
Multiple
Virtual CX_NVC >= 3 High Reduce the number of VCs
Channels
Multiple
CX_NFUNC >= 16 High Reduce the number of functions
Functions
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PCI Express SW Controller Databook Synthesis for 1GHz Clock Frequency
Two or more medium severity configuration parameter settings High Follow the suggestions given
Simultaneous
Inbound Non
CX_REMOTE_MAX_TAG >= 127 Medium Reduce number of tags
Posted
Requests
Address
Translation CX_INTERNAL_ATU_ENABLE 1 Medium Reduce number of regions
Unit (ATU)
Multiple
CX_NFUNC >= 8 Medium Reduce number of functions
Functions
Outbound
AXI CC_MAX_SLV_TAG (AXI) >= 64 Medium Reduce number of tags
Transactions
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Inbound AXI
CC_MAX_MSTR_TAGS_AXI (AXI) >= 64 Medium Reduce number of tags
Transactions
a. This is a hidden parameter and is not visible in coreConsultant GUI. The default value of CC_DMA_BA_ENABLE is ‘1’. You can
change the value of this parameter through coreConsultant command line (using set_configuration_parameter command).
b. This is a hidden parameter and is not visible in coreConsultant GUI. The default value of CC_MSTR_AXI_GM_EDMA_HT is ‘0’.
You can change the value of this parameter through coreConsultant command line (using set_configuration_parameter
command).
To discuss trade-offs, or optimizations to your configuration, contact Synopsys support through Solvnet.
Floorplan Considerations for 1GHz Clock Frequency (Controller standalone)
The module and pin placement floorplan considerations for 1GHz clock frequency are as follows:
Module Placement
■ Place application interface modules close to your application logic
❑ Native Configuration
■ u_DWC_pcie_core/u_xadm
■ u_DWC_pcie_core/u_radm
■ Place physical layer modules close to PHY
❑ u_DWC_pcie_core/u_cx_pl/u_xmlh
❑ u_DWC_pcie_core/u_cx_pl/u_rmlh
❑ u_DWC_pcie_core/u_cx_pl/u_smlh
❑ u_DWC_pcie_core/gen_pipe_regif *
❑ u_DWC_pcie_core/gen_freq_step *
❑ u_DWC_pcie_core/u_lane_flip
❑ u_DWC_pcie_core/u_pipe *
PIN Placement
■ Place PIPE interface pins close to PHY
❑ PIPE Interface
❑ PHY Register Bus Interface
■ Place application interface pins close to your application logic
❑ Native Configuration
■ Receive Bypass / Request Interface (RBYP/TRGT1)
■ Transmit Interfaces (XALI0/1/2)
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PCI Express SW Controller Databook Supported Controller Configurations
250, 250,
g1_1s g2_2s_dw g3_4s_dw NA NA x1 x2 x4 x8 x16
250
125, 125,
g1_2s g2_4s_dw g3_8s_dw NA NA NA x1 x2 x4 x8
125
Gen3
250, 500,
Configu g1_1s g2_1s_df g3_1s_df NA NA x4 x8 x16 NA NA
1000d
rations
125, 250,
g1_2s g2_2s_df g3_2s_df NA NA x2 x4 x8 x16 NA
500
62.5, 125,
g1_4s g2_4s_df g3_4s_df NA NA x1 x2 x4 x8 x16
250
250, 250,
g1_1s g2_2s_dw g3_4s_dw g4_8s_dw NA NA x1 x2 x4 x8
250, 250
125, 250,
g1_2s g2_2s_df g3_2s_df g4_2s_df NA x2 x4 x8 x16 NA
Gen4 500, 1000d
Configu
rations 62.5, 125, g1_4s g2_4s g3_8s g4_8s NA NA x1 x2 x4 x8
125, 250
62.5, 125,
g1_4s g2_4s_df g3_4s_df g4_4s_df NA x1 x2 x4 x8 x16
250, 500
Synopsys, Inc.
62.5, 125,
250, 500, g1_4s g2_4s_df g3_4s_df g4_4s_df g5_4s_df x1 x2 x4 x8 x16
1000d
125, 250,
250, 500, g1_2s g2_2s g3_4s g4_4s g5_4s x1 x2 x4 x8 x16
1000d
a. The value in each cell indicates the maximum link width supported. You can configure the controller with a link width up to this value,
and coreConsultant automatically calculates the datapath width.
b. For license scheme , see the “Checking License Requirements” section in the DWC PCI Express Controller Installation Guide.
c. The g value indicates the speed mode. The s value indicates the number of 8-bit symbols processed per clock cycle per lane by the
controller PIPE interface, in the indicated speed mode. The dw/df value indicates how the speed change to that mode is achieved.
d. For more information, see “Synthesis for 1GHz Clock Frequency” on page 30.
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PCI Express SW Controller Databook Controller-PHY Compatibility
PHY
g1_2s
g2_2s_df
g3_4s_dw
g4_4s_df
C
g5_4s_df
O
N g1_4s
T g2_4s_df
R
g3_4s_df
O
L g4_4s_df
L g5_4s_df
E
g1_4s
R
g2_4s_df a
g3_8s_dw
g4_8s_df
g5_8s_df
a. Support for 64-bit (8s) PIPE is specific to Synopsys; the PIPE specification specifies a maximum of the
maximum data width of 32 bits. When CX_PIPERX_MULTI_BLOCK =0, the controller only accepts
64-bit-aligned SKP OS. If you use this configuration, your PHY PCS must follow this requirement. When
CX_PIPERX_MULTI_BLOCK =1, blocks can start any 32-bit boundary by extending bit-width of rxstart-
block and rxsyncheader (phy_mac_rxstartblock: 2-bit per-lane and phy_mac_rxsyncheader 4-bit per-lane).
For more information, see “64-Bit PIPE Receive Operation (CX_PIPERX_MULTI_BLOCK =1)” on page
308.
Synopsys, Inc.
PHY
g1_1s
g2_2s_dw a
g3_4s_dw
g4_8s_dw
C g1_2s
O g2_2s_df b c
N
g3_2s_df
T
R g4_2s_df
O g1_4s
L d
g2_4s_df
L
E g3_4s_df
R g4_4s_df
g1_4s
g2_4s_df
g3_8s_dw
g4_8s_dw
a. Support for 64-bit (8s) PIPE is specific to Synopsys; the PIPE specification specifies a maximum of the maximum data width of 32
bits. When CX_PIPERX_MULTI_BLOCK =0, the controller only accepts 64-bit-aligned SKP OS. If you use this configuration, your
PHY PCS must follow this requirement. When CX_PIPERX_MULTI_BLOCK =1, blocks can start any 32-bit boundary by extending
bit-width of rxstartblock and rxsyncheader (phy_mac_rxstartblock: 2-bit per-lane and phy_mac_rxsyncheader 4-bit per-lane). For
more information, see “64-Bit PIPE Receive Operation (CX_PIPERX_MULTI_BLOCK =1)” on page 308.
b. DP PHY: doing Gen1 with 2:1 DP, Gen2 with no DP, Gen3 using DW, and obtaining Gen4 using DF.
c. DP PHY: doing Gen1 with 2:1 DP, Gen2 with 2:1 DP, Gen3 with no DP, and obtaining Gen4 using DF.
d. DP PHY: doing Gen1 with 2:1 DP, Gen2 with no DP, Gen3 using DW, and obtaining Gen4 using DW.
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PCI Express SW Controller Databook Controller-PHY Compatibility
PHY
g1_1s
g2_1s_df
g3_1s_df
g1_1s
C
g2_2s_dw
O
N g3_4s_dw
T g1_2s
R a
g2_4s_dw
O
L g3_8s_dw
L
g1_2s b c
E
g2_2s_df
R
g3_2s_df
g1_4s
g2_4s_df
g3_4s_df
a. Support of a 64-bit (8s) PIPE is specific to Synopsys; the PIPE specification specifies a maximum of the maximum data width
of 32 bits. The controller only accepts 64-bit-aligned SKP OS. If you use this configuration, your PHY PCS must follow this
requirement
b. DP PHY: doing Gen1 with 2:1 DP, Gen2 with no DP, and obtaining Gen3 using DW.
c. DP PHY: doing Gen1 and Gen2 with 2:1 DP, Gen3 with no DP.
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PHY
g1_1s
g2_2s_dw
C
O g1_2s
N g2_4s_dw
T
R g1_1s
O g2_1s_df
L
L g1_2s
E g2_2s_df
R
g1_4s
g2_4s_df
PHY
C
g1_1s
O
N
T g1_2s
R
O
L
L g1_4s
E
R
1. Located in workspace/src/common/freq_step.v
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PCI Express SW Controller Databook Controller-PHY Compatibility
Controller P pclk
freq_step
Sub- (pclkx2)
PIPE (core) PIPE (PHY) H
blocks Y
pipe_clk
CLK
core_clk Gen
This module steps up/down the signals at the PIPE interface and adjusts the controller PIPE width
according to the PHY PIPE width if the core_clk frequency is slower or faster than the pipe_clk frequency.
Controller-PHY Integration
The PHY module resides outside of the controller, interfacing through the standard PIPE interface. For more
information, see “Integrating the Controller with the PHY” in the User Guide.
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1.5 Deliverables
The deliverables for the PCIe controllers include:
■ Synthesizable RTL source code
■ Synopsys coreConsultant tool for automated configuration, synthesis, and simulation
■ Synopsys PHY simulation model
■ A Verilog Testbench (VTB):
❑ Allows you to re-execute the regression tests on your configuration of the controller for the
purpose of verifying your configuration.
❑ Demonstrates connectivity and many types of transfers. Can be used for system-level testbench
integration.
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PCI Express SW Controller Databook Standards
1.6 Standards
The PCIe controller implements the following standards:
■ PCI Express Base Specification, Revision 4.0, Version 1.0
Access to this specification requires membership in PCI-SIG.
Download site:
http://pcisig.com/specifications
■ PIPE Specification for PCI Express, Version 4.4.1
Download site:
http://www.intel.com/technology/pciexpress/devnet/resources.htm
■ PCI Local Bus Specification, Revision 3.0
Access to this specification requires membership in PCI-SIG.
Download site:
http://www.pcisig.com/specifications/conventional/pci_30
■ PCI Bus Power Management Specification, Revision 1.2
Access to this specification requires membership in PCI-SIG.
Download site:
http://www.pcisig.com/specifications/conventional/pci_bus_power_management_interface
■ PCI Express Card Electromechanical Specification, Revision 3.0
Access to this specification requires membership in PCI-SIG.
Download site:
https://members.pcisig.com/wg/PCI-SIG/document/download/8250
Synopsys, Inc.
2
Architecture
This section describes the architecture of the PCI Express controller. The topics in this section are:
■ “Overview” on page 43
■ “RAM Requirements” on page 48
■ “Clock Requirements” on page 53
■ “Reset Requirements” on page 64
■ “Receive Queues” on page 74
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PCI Express SW Controller Databook Overview
2.1 Overview
The implementation of the PCIe protocol and mode-specific features is split across several modules.
Application Interfaces
(RADM/XADM/CDM)
CXPL
Transaction Layer
Physical Layer(MAC)
■ Common Express Port Logic (CXPL) Module implements the basic functionality for the PCI Express
physical, link, and transaction layers. This module implements a large part of the transaction layer
logic, all of the data link layer logic, and the MAC portion of the physical layer, including the link
training and status state machine (LTSSM). The CXPL connects to the external PHY through the PIPE.
For more information, see “Integrating with the PHY in the PCI Express controller” in the User Guide.
■ Transmit Application-Dependent Module (XADM) implements the application-specific function-
ality of the PCI Express transaction layer for packet transmission. Its functions include:
❑ TLP Arbitration
❑ TLP Formation
❑ Flow Control (FC) Credit checking
The transmit path uses a cut-through architecture. It does not implement transmit buffering/queues
(other than the retry buffer).
■ Receive Application-Dependent Module (RADM) implements application-specific functionality of
the PCI Express transaction layer for packet reception. Its functions include:
❑ Sorting/filtering of received TLPs. The filtering rules and routing are configurable.
❑ Buffering and queuing of the received TLPs. For more information, see “Receive Queues” on page
74.
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INTx hp_int
PMEa hp_pme
a. The controller does not check if the PM state is D1, D2, or D3hot. It is up to your application to check the value on pm_dstate
to make sure the device is in D1, D2, or D3hot.
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PCI Express SW Controller Databook Overview
RBYP
RAM
Application
Logic: TRGT1 RADM RX PIPE
Receive
TRGT1_CCIX
TRGT0
CPU DBI
CIC
Application ELBI LBC
Registers
iATU
1 PRBI PRC
CXPL Core PHY
Application CDM
Logic: Controller
PRC
MSI(-X) Registers
RAS
RAM
Application
Logic:
SII
Rx Vendor
Messages
XALI0
Application XALI1
Logic: XADM RAM TX PIPE
Transmit XALI2
XALI_CCIX CRPI
PMBC
1
Application
Logic:
Tx Vendor VMI MSG_GEN
Messages
Application CLK/RST
Logic: HOT PLUG
Optional
SII
System Status/
Control
Registers PMC
Application Optional
Logic: Note: In DSP there is no wire
Customer Logic
Coherent CXS access to CDM or ELBI.
CXS PCIe Protocol
Multichip Link Controller However, there is DBI access.
Synopsys
(CML) Specific
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Interface Function
Receive Target 1 (TRGT1)/ Receive TRGT1 and RBYP are receive interfaces used to connect the native controller
Bypass Interface (RBYP) and your application . RBYP is used by queues that are in bypass mode.
TRGT1_CCIX receive interface is used to connect the controller and the CCIX
Receive Target 1 CCIX Interface logic of your application.
(TRGT1_CCIX)
Message Signaled Interrupt (MSI) MSI Interface can be used by your application to send MSI requests to the
Interface controller, independent of XALI client interfaces.
SII is used for exchanging system information between the controller and your
System Information Interface (SII)
application.
Standard PIPE interface (PIPE Specification for PCI Express, Version 4.4.1)
PIPE
between the PCI Express PHY and the controller.
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PCI Express SW Controller Databook Overview
Interface Function
Allows your application logic to detect the occurrence of; and to modify the
behavior of Rx CFG requests (from the remote link partner) that are
Configuration Intercept Interface (CII)
accessing the controller's internal registers. See also CIC in “Configuration
Intercept Controller (CIC) for USP” on page 976.
CXS in the PCIe controller enables the use of PCIe IP in the implementation
CCIX Stream Interface (CXS)
of Coherent Multi-chip Links.
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2.2.1 Overview
The controller supports external and internal RAMs.
■ The value of configuration parameter CX_RAM_AT_TOP_IF indicates if the RAMs are external or
internal.
❑ CX_RAM_AT_TOP_IF =1; RAMs are external.
❑ CX_RAM_AT_TOP_IF =0; RAMs are internal.
■ RAMs are either dual-port (write port A and read port B) or one-port (one shared read/write port).
Note: All RAMs are dual-port, except the retry buffer and iMSI-RX RAMs, which are one port.
■ RAMs must have single-cycle access latency, that is, read data is expected on the next cycle after the
address is supplied. The controller supports the RAM types in Figure 2-3 and Figure 2-4.
■ RAMs do not have to be initialized.
■ When using the UPF flow (CX_ENHANCED_PM_EN =1), all RAMs are in the PD_VAUX power domain
and may be powered-down in L2 and L1.
UPF model for RAMs or isolation rules to cover the outputs of the RAMs are not provided
Note when RAMs are powered down. You should ensure that RAM power gating or isolation is
handled correctly in your application.
Cells Cells
tim
-
Re
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PCI Express SW Controller Databook Overview
g
adr adr
in
m
-t i
Re
wen re wen ren
RAM RAM
din dout din dout
g
in
Cells Cells
tim
-
Re
RAM Implementation
Each module that uses RAM instantiates one of the following synthesizable RAM models with the required
width and depth parameters:
■ workspace/src/vendor/generic/ram1p.v (for one-port RAM)
■ workspace/src/vendor/generic/ram2p.v (for dual-port RAM)
You must instantiate your technology-specific RAM models from your RAM vendor inside ram1p.v and
ram2p.v.
The CX_RAM_TYPE configuration parameter determines the type of RAMs used in the controller when you
are using internal RAM (CX_RAM_AT_TOP_IF =0).
To implement or synthesize a small RAM as a register file, either replace the ram1p.v/ram2p.v
Hint files with your own register-file implementation or choose CX_RAM_TYPE =1.
■ 0: Simple
This is synchronous RAM supplied by your vendor. For simulation, you do not need to do anything
because a Verilog register-based RTL code exists in the ram1p.v/ram2p.v files. For implementation,
ou need to instantiate your technology-specific compiled RAM inside ram1p.v and ram2p.v.
Note: External RAMs are always simple RAMs.
■ 1: DesignWare
This is Synopsys DesignWare Library (register-based) SRAM memory generator for sizes up to 256 X
256. For more information, see http://www.synopsys.com/dw/ipdir.php?c=DW_ram_2r_w_s_dff
or http://www.synopsys.com/dw/ipdir.php?c=DW_ram_rw_s_dff.
■ 2: FPGA RAM
This is FPGA memory. For simulation, you do not need to do anything because Verilog register-based
RTL code exists in the ram1p.v/ram2p.v files. For implementation, the FPGA synthesis tool should
infer the appropriate block RAMs.
Synopsys, Inc.
RAM Timing
The RAM read cycle latency is the delay between the time at which the read address is presented by the
controller to the RAM, and the time at which the read data is presented by the RAM to the controller. The
default read access time of the RAM is one clock cycle.
To ease timing closure at high clock frequencies, external pipelines on the read address path or the read data
path can be added to the RAM read path. You can configure the appropriate RAM read latency parameter
(described in the Table 2-3 ) so that the controller can sample the read data correctly. These parameters
specify the number of cycles after which the controller expects RAM read data to appear. For example, if the
AXI Master Completion Buffer RAM read data is externally re-timed, then you can set
CC_MSTR_CPL_SEG_BUF_RAM_RD_LATENCY =2.
clk
read_enable/
address
read_data
Table 2-3 RAM Read Latency Parameters for Native Controller RAMs
RAM Parameter
By default, the AXI bridge registers RAM interfaces to facilitate timing closure. To reduce RAM
Note write/read latencies, pipeline stages on the write/read control interface signals can be removed,
subject to closing timing on these interfaces. Contact Synopsys support through SolvNet, if the
default RAM write/read latencies are of concern.
You can also set the following parameters to place a re-timing register at the output of the RAMs.
■ CX_RETRYSOTRAM_REGOUT
■ CX_RETRYRAM_REGOUT
The read data output of the Rx Queue RAMs is always re-timed/registered by the controller.
You can set the following parameter to place a register at the boundary between the Rx queue manager
outputs and the Rx queue RAM inputs.
■ CX_RADM_INQ_MGR_REGOUT
After you configure the RAM1P_RD_ACCESS, RAM1P_ADDR_SU, RAM2P_RD_ACCESS, and RAM2P_ADDR_SU
parameters, the coreConsultant tool generates the timing requirements. For more information on accessing
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PCI Express SW Controller Databook Internal and External RAM Verilog Instances
synthesis scripts and SDC, see “Synthesizing to a Device Outside of coreConsultant” in the “Exporting a
Controller From coreConsultant to Your Chip Design Database” section of the User Guide.
a. The retry buffer which stores transmitted TLPs for potential replaying has an associated Start-of-TLP (SOT) buffer. This
is required for identifying the start of TLPs in the retry buffer.
b. When you select 32-bit, 64-bit and 128-bit datapath configurations the controller instantiates one header RAM and one
data RAM, that is, H=D=1. When you select a 256-bit datapath configuration an additional header and data RAM are
required to process 2 TLPs in one cycle, that is, H=D=2. When you select a 512-bit datapath configuration one header
RAM and 4 data RAMs are instantiated, that is, H=1, D=4. Only one header RAM is required as the 512-bit Rx Queue
processes only 1 TLP per cycle. For 512-bit datapath configurations a serialization queue is used to send TLPs to the
Rx Queue, one TLP at a time. The data RAMs store 128 bits of data per cycle and scale with the data width, that is,
for datapath configurations up to 128-bit one data RAM is required, for 256-bit two data RAMs are required, for 512-bit
4 data RAMs are required. Note: the number of RAMs is not influenced by the number of VCs. As the number of VC's
increase the depth of the RAMs increase.
c. When you select a 512-bit datapath configuration a TLP serialization queue is instantiated before the Receive queues.
The Receive Serialization Queue is comprised of 6 RAMs when TLP prefixing is disabled (S=6), increasing to 7 RAMs
when TLP prefixing is enabled (S=7).
Synopsys, Inc.
Figure 2-6 Snippet of Log File Showing the Reporting of RAM Sizes
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PCI Express SW Controller Databook Clock Requirements
2.3.1 Overview
The PCIe controller requires the clocks outlined in Table 2-6.
Table 2-6 Generation of Individual Clock Signals by Your Clock Generation Logic
Clock Notes
■ The gated version of the core_clk for modules retained during L1 power gating.
ret_core_clk ■ The ret_core_clk frequency is the same as core_clk.
■ You can gate this clock during the L1 and L2 low power states under the same condi-
tions as core_clk.
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Clock Notes
aux_clk_g ■ This is a gated version of aux_clk that is used to clock the CDM registers and the
LBC/DBI.
■ This is a gated version of core_clk that is used to clock the RADM (Rx filter and
queues).
radm_clk_g
■ The DWC_pcie_clkrst.v module uses the en_radm_clk_g controller outputa to
enable radm_clk_g.
■ In typical configurations (CX_FREQ_STEP_EN =0), this clock pin does not exist.
■ The pipe_clk input is used by the controller to clock the PIPE.
■ It can have a frequency of 62.5, 125, 250, 500, or 1000 MHz.
pipe_clk ■ The PHY TX PLL generates pipe_clk from the platform reference clock. The PHY
adapts and re-times RX data to pipe_clk.
■ The core_clk and pipe_clk clocks must have the same phase and have frequencies
that are integer multiples of each other.
■ In normal operation (L0/D0), core_clk and core_clk_ug are derived from pipe_clk.
a. The controller de-asserts this signal when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty,
RADM completion LUT is empty, and there are no FLR actions pending. You must set the RADM_CLK_GATING_EN
field in the CLOCK_GATING_CTRL_OFF register to enable this functionality; otherwise the en_radm_clk_g output is
always be set to ‘1’.
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PCI Express SW Controller Databook General Clock Relationships
simulate the controller to obtain precise timings. For the purposes of simplicity, the diagram shows
core_clk being derived from pipe_clk without division. For the meaning of signal labels, refer to the
“Clock Generation Module” on page 60.
Figure 2-7 Clock Waveforms with External PHY (Not Cycle Accurate)
REF_CLK
#
pipe_clk
Normally all clocks are derived
from pipe _clk
core_clk
core_clk_ug
core_clk_ug is never gated
or shut off. It runs until
pipe_clk ceases.
aux_clk
(platform AUX
clock)
In the “Signal Descriptions” chapter, the “Synchronous To:” attribute indicates which controller clocks
sample an input (or drive an output) when considering all possible configurations.
■ In many cases an output has components driven (or an input sampled) by multiple clocks.
■ The attribute lists all clocks which drive or sample for all possible configurations. It is an automatically
generated list accumulated over all configurations.
■ Your particular configuration might not have all of the clocks listed. If you have access to the Spyglass
tool, then you can generate a configuration-specific report using the process outlined in the “Running
Spyglass” section of the User Guide.
■ When there is only one clock in the list, this clock is normally but not always the same as the clock that
your application logic should use to clock (sample/drive) this pin.
■ When there is more than one clock in the list:
■ A {} is placed around the clock which is used in generating the synthesis in/out timing delay
constraints and which is also used in Spyglass boundary CDC checking.
■ In most cases, this is also the clock that you should use to drive/sample the pin in normal operational
(non low-power) mode.
■ If more1 than one clock has a {}, that clock is configuration-dependent, and you should look in your
SDC file (as explained in the “Synthesizing to a Device Outside of coreConsultant” section of the User
Guide) to see which one is relevant.
1. Normally only applies to the PIPE outputs which are clocked on pipe_clk or core_clk depending on CX_FREQ_STEP_EN.
Synopsys, Inc.
■ When you see “perbitclk” in the clock list, it indicates that there is a different clock for some of the bits
in the multi-bit port, and/or that some of the bits in a multi-bit port falls into the various categories as
defined next by “None”.
■ When you see “None_as” in the clock list, it indicates the following and is equivalent/mapped to
core_clk for CDC synthesis.
❑ Asynchronous reset with synchronous de-assertion.
■ When you see “None” in the clock list, it indicates any of the following1 and is equivalent/mapped to
core_clk for CDC and synthesis.
❑ Direct or combinatorial feed-through.
❑ Gated-off (that is, unclocked) inputs.
❑ Unused inputs.
❑ Hard-coded outputs.
❑ Asynchronous outputs.
❑ Asynchronous resets.
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❑ All are clocked out by aux_clk_g which runs slow in low-power mode.
❑ You might want to sample some of these outputs during L1 and take action.
❑ However, it is not expected that you have your complete application running in low-power mode
(on aux_clk_g) because this might result in higher and unnecessary power consumption.
■ Client Interfaces (client0/1/2_*)
❑ When driven from the aux_clk domain the client0_tlp_hv pin triggers exit from low power
as per “L1 Operation (Non-substates)” on page 230.
❑ The whole interface (all client0_tlp_* inputs) must be driven from the same clock because
header info and so on, needs to be provided at the same time as client0_tlp_hv.
❑ An alternative method to trigger L1 low-power exit is to use and clock xfer_pending on aux_clk
and to drive the client0_tlp_* interface on core_clk.
■ TRGT1 Interface (trgt1_*)
❑ The controller clocks this interface on radm_clk. However, there are some status paths going back
to the CDM (aux_clk_g and core_clk).
❑ If your application interface is receiving requests and generating responses (on client0_tlp_*), it
recommended to use core_clk to sample this interface and drive the response interface.
❑ If your application interface is only receiving requests, it recommended to use radm_clk to
sample this interface.
■ PIPE Interface (mac_phy_*/mac_phy_*)
❑ pipe_clk indicates a frequency step1.
❑ The PIPE interface also drives/samples logic on aux_clk for low-power entry and exit.
2.3.3 Gen2, Gen3, Gen4, or Gen5 Speed Changing Considerations (CX_FREQ_STEP_EN =1)
When the PHY is dynamic frequency and the controller is dynamic width, pipe_clk changes frequency
when moving between modes. However, core_clk should not change frequency. Your synthesized
controller logic operates at a fixed frequency, so it is imperative that your external clock generation and
switching logic (see DWC_pcie_clkrst.v) never generates core_clk with a higher frequency during
mode switching. The controller uses the mac_phy_rate output to negotiate the link data rate and waits for
a pulse on the phy_mac_phystatus input to confirm that the PHY has accepted the requested rate.
However, you must carefully consider the following facts when designing the logic that controls the
core_clk switch selection between pipe_clk and the divided pipe_clk:
■ The PHY can start generating pipe_clk at the newer frequency several clock cycles before it asserts
phy_mac_phystatus.
■ A typical anti-glitch clock switch does not switch the clock source until several clock cycles after it has
been instructed to do so.
Therefore, your external clock generation and switching logic should:
■ Start switching as soon as mac_phy_rate changes if moving to a faster speed mode. That is, do not
switch too late.
Synopsys, Inc.
Figure 2-9 Recommended Clock Divider Switching Points During Speed Changes (Not Cycle Accurate)
#
pipe_clk
core_clk
phy_mac_phystatus
pipe_clk divider /1 /2 /1
The controller uses core_clk to sample the phy_mac_phystatus input which the PHY generates at
pipe_clk. Therefore when the PHY is dynamic frequency and the controller is dynamic width (that is,
when core_clk is not equivalent to pipe_clk), you must ensure that:
■ core_clk is toggling when the PHY updates phy_mac_phystatus for a speed change
OR
■ your external logic holds phy_mac_phystatus (for the speed change) until core_clk toggles again.
L1 CLK PM
clk_req_n
(CX_L1_SUBSTATES_EN =0) “L1 Clock PM (L1 with REFCLK removal/PLL Off)
L1 CLK PM Overview” on page 233
mac_phy_pclkreq_n[0]a
(CX_L1_SUBSTATES_EN =1)
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PCI Express SW Controller Databook Removing the Reference Clock
REFCLK
pclk PLL
CX_L1_SUBSTATES_ENABLE =0 &
CX_PIPE_VER =0 (PIPE 4.2)
mac_phy_powerdown[1:0] mac_phy_powerdown[1:0]
mac_phy_powerdown[3:2] NC
phy_mac_phystatus[NL-1:0] phy_mac_phystatus[NL-1:0]
mac_phy_pclkreq_n mac_phy_pclkreq_n
phy_clk_req_n
CX_L1_SUBSTATES_ENABLE =0 &
CX_PIPE_VER >=1 (PIPE 4.3 or Later)
mac_phy_powerdown[3:0] mac_phy_powerdown[3:0]
phy_mac_phystatus[NL-1:0] phy_mac_phystatus[NL-1:0]
phy_clk_req_n
CX_L1_SUBSTATES_ENABLE =1 &
CX_PIPE_VER =0 (PIPE 4.2)
mac_phy_rxelecidle_disable mac_phy_rxelecidle_disable
mac_phy_txcommonmode_disable mac_phy_txcommonmode_disable
mac_phy_powerdown[1:0] mac_phy_powerdown[1:0]
mac_phy_powerdown[3:2] NC
mac_phy_pclkreq_n[0] mac_phy_pclkreq_n[0]
mac_phy_pclkreq_n[1] mac_phy_pclkreq_n[1]
phy_clk_req_n L1 substate
L1.CPM PLL on/off
phy_mac_pclkack_n phy_mac_pclkack_n
L1 substate Logic
Logic phy_mac_phystatus[NL-1:0] phy_mac_phystatus[NL-1:0]
CX_L1_SUBSTATES_ENABLE =1 &
CX_PIPE_VER >=1 (PIPE 4.3 or Later)
optional
mac_phy_rxelecidle_disable mac_phy_rxelecidle_disable
optional
mac_phy_txcommonmode_disable mac_phy_txcommonmode_disable
mac_phy_powerdown[3:0] mac_phy_powerdown[3:0]
optional
mac_phy_asyncpowerchangeack mac_phy_asyncpowerchangeack
phy_mac_phystatus[NL-1:0] phy_mac_phystatus[NL-1:0]
phy_clk_req_n
local_ref_clk_req_n
Platform Reference
cfg_l1_sub_en
Clock Generation
phy_ref_clk_req_n
clkreq_in_n
pm_sel_aux_clk
aux_clk_active
local_ref_clk_req_n
aux_clk
Pullup
muxd_aux_clk
aux_clk_active
Tristate Buffer
‘0’
aux_clk CLKREQ#
switching logic USP
clk divider/ 1
test mux DSP
DWC_pcie_clkrst_cpcie ‘1’ 0
device_type
aux_clk pipe_clk
* The aux_clk_active signals indicates that your external Example application specific logic to enable DSP drive hi-Z on CLKREQ#
clock logic has switched the aux_clk input from pipe_clk when L1 substates are disabled, such that the USP can assert/de-assert
to the platform auxiliary clock. The core does not request CLKREQ# freely as required in pre-L1 substates functionality.
the PHY to remove pipe_clk until you have switched Note: When L1 substates are enabled, the specification requires that the
aux_clk. This is used to give time to your application to DSP asserts CLKREQ# in the Recovery state when exiting L1. The example
switch aux_clk. When this signal is '0' in L1, the core stalls logic shown satisfies this requirement by ensuring that when the L1
the entry into the L1 substates and the de-assertion of substates are enabled, CLKREQ# is always asserted outside of the L1 link
mac_phy_pclkreq_n (clkreq_n). state (because mac_phy_pclkreq_n[1] will always be ‘0').
Synopsys, Inc.
MAIN POWER
Power On Reset
AUX_CLK
WAKE# (from EP )
WakeUp
EP Power Low Power Mode
Link Training Configuration Operation Link Training Config
PROCESS OFF Low Power Standby Low Power Sleep
sys_aux_pwr_det
When the controller transitions the PHY Powerdown state to P2 or P1.CPM, it simultaneously
Note requests the source of aux_clk to be switched to the slow clock. The clock switch design used
in the clock and reset generation module of the controller requires 2 cycles of the PHY clock to
perform the clock switch. It is assumed that the PHY clock runs for a minimum of 2 cycles after
the controller has transitioned PHY Powerdown to P2 or P1.CPM.
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CORE?CLK?UG
PHY CLK_RST.v
mac_phy_rate CORE?CLK
2%&?#,+
PIPE?CLK
#LOCK $IVIDE
0 MUXD?AUX?CLK
&OR 'EN -UX
'EN 3PEED !58?#,+
1
AUX?CLK?G
En
0,, D
en_aux_clk_g
APP?LTSSM?ENABLE
PM?EN?CORE?CLK
PM?SEL?AUX?CLK
LINK?REQ?RST?NOT
MAC?PHY?RATE
AUX?CLK?ACTIVE
EN?AUX?CLK?G
CONTROLLER
SYS?AUX?PWR?DET
Core Logic LBC/DBI/ELBI
;CORE?CLK= ;AUX?CLK?G=
;CORE?RST?N= ;CORE?RST?N= AUX?CLK?G
AUX?CLK
PERSTN CDM (sticky)
PMBC CORE?CLK
APP?REQ?ENTR?L ;AUX?CLK?G=
;PIPE?CLK=
;STICKY?RST?N= CORE?CLK?UG
APP?REQ?EXIT?L ;CORE?CLK?UG=
APP?READY?ENTR?L ;PIPE?MSGBUS?RST?N= PIPE?CLK
CDM (non-sticky)
PWR?RST?N ;PIPE?RST?N=
;AUX?CLK?G=
;CORE?RST?N=
APPS?PM?XMT?PME ;NON?STICKY?RST?N=
outband_pwrup_cmd
PMC RxEI Squelch SLV?ACLK
;AUX?CLK= ;AUX?CLK= MSTR?ACLK
;PWR?RST?N= ;SQUELCH?RST?N=
DBI?ACLK
FREQ_STEP
PHY?MAC?PHYSTATUS ;PIPE?CLK=
;PIPE?RST?N=
CORE?CLK?UG
4HESE SIGNALS DO NOT EXIST FOR 2# PORTS
$30 CORE IGNORES THESE INPUTS
Synopsys, Inc.
AUX?CLK MUXD?AUX?CLK
CORE?CLK
#LOCK 'ATER
PM?SEL?AUX?CLK 'LITCH &REE #LOCK 3WITCH
%. '#,+ MUXD?AUX?CLK?G
#,+
EN?MUXD?AUX?CLK
CORE?CLK?UG
#LOCK 'ATER
#,+
#LOCK 'ATER
#,+
Figure 2-13 describes the clock switch and gating logic which functions as follows:
■ The clock reset module implements a glitch free clock switch to permit the generation of the aux_clk
input to the controller. The switch is controlled by the output pm_sel_aux_clk, which selects the
aux_clk in certain low power states, and power on reset or fundamental reset.
■ The clock reset module implements architectural clock gating on core_clk, which permits the
disabling of core_clk in certain low power states as determined by the de-assertion of
pm_en_core_clk.
■ The clock for the RADM may be gated off when the signal en_radm_clk_g is de-asserted to allow
architectural clock gating in the receive path.
■ The clock muxd_aux_clk_g is a clock gated version of the muxd_aux_clk, which may be disabled
when power gating is supported in L1.2.
For more information on the clock switch logic and implemented architectural clock gating, see the RTL of
the clock and reset module.
#LOCK 'ATER
MAC?PHY?RATE
PHY?MAC?PHYSTATUS 0IPE #LOCK
#8?0(9?." $IVIDE &ACTOR %. '#,+ CORE?CLK
#8?." ,OGIC
#,+
PCLK
Figure 2-14 describes the frequency step down clock divider logic which functions as follows:
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PCI Express SW Controller Databook Clock Generation Module
If the derived parameter CX_FREQ_STEP_DOWN_EN is defined, the core_clk frequency is slower than the
pipe_clk frequency, in this scenario it is necessary to generate the core_clk as a divided down version of
the pipe_clk.
■ The following factors contribute to the selection of the pipe_clk division factor used to generate the
core_clk:
❑ Number of symbols per cycle for the controller and the PHY
❑ The required link signaling rate as requested by the mac_phy_rate output of the controller
For example, if the PHY supports two symbols per pipe_clk cycle at GEN1 speed while the controller
supports four symbols per core_clk cycle at GEN1 speed, the divide by two is enabled.
■ A counter running on pclk is used to count the required number of pclk cycles, the output of this
counter in combination with the required division factor is used to enable the clock gating.
■ The clock divider uses a pulse suppression technique to generate the divided version of the pipe_clk.
This means that the generated core_clk do not have a 50% duty cycle.
For the detailed implementation of the divider circuit, see the RTL of the clock and reset generation module.
You could use a PLL/DPLL instead of the clock divider. This eases balancing of the core_clk ,
radm_clk_g, and pipe_clk clock trees as the PLL/DPLL can eliminate the divider insertion delay.
Synopsys, Inc.
2.4.1 Overview
The DWC_pcie_clkrst.v module generates the resets as per Table 2-8.
Note: Sticky is a PCIe term and means that the register retains its value during some reset sequences. There
are many reset inputs for the controller as describes in Table 2-8. All of these reset inputs are asserted on a
cold/fundamental/power-on reset. Not all these reset inputs are asserted during a hot reset (when link is
reset and most of controller logic is not reset but some small parts of the controller and some registers ARE
reset). Any registers that you want to remain un-reset during a hot reset must be wired to the
sticky_rst_n pin.
Table 2-8 Generation of Individual Reset Signals for each Reset Event
core_clk /
core_rst_n Controller Yes Yes Yes Yes
radm_clk_g
phy_reg_clk_u
phy_reg_rst_nl Controller Yes Yes Yes
g
ret_non_sticky_rst_n
d aux_clk_g Controller Yes Yes Yes
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a. When CX_ENHANCED_PM_EN =1, the DWC_pcie_clkrst.v asserts all resets upon PERST# (perst_n) except
pwr_rst_n. PERST# is the trigger for L2 power removal.
b. On PERST# assertion, all of the controllers resets apart from pwr_rst_n are asserted synchronous to aux_clk. If a
register reset by core_rst_n, for example, fans in to a register reset by pwr_rst_n there is a reset domain crossing path.
The path through the preset or clear pin of the register being reset to the data pin of register which is not being reset
should be timed to ensure that there is no metastability on the register reset by pwr_rst_n.
c. CX_ENHANCED_PM_EN =1
d. TS protocol-based hot reset or link-down reset.
e. On link down reset the clock and reset module gates off the controller’s clocks when the resets are being asserted.
This is to ensure that the registers in the design are not being clocked when the resets are asynchronously asserted,
thereby avoiding any Reset Domain Crossing (RDC) issues.
f. This signal exists only when MSTR_CLK_DIFF_ENABLE ==1 && CX_ENHANCED_PM_EN ==1
g. This signal exists only when SLV_CLK_DIFF_ENABLE ==1 && CX_ENHANCED_PM_EN ==1
h. This signal exists only when DBISLV_CLK_DIFF_ENABLE ==1 && CX_ENHANCED_PM_EN ==1
i. See ret_sticky_rst_n.
j. pipe_rst_n and pipe_clk are not used when CX_FREQ_STEP_EN =0.
k. pipe_msgbus_rst_n is not used when CX_PIPE_VER <3.
l. Exists when CX_PHY_VIEWPORT_ENABLE =1.
m.Exists when CX_ENHANCED_PM_EN =1. ret_<resetname> is the reset signal for the logic that is retained in L1.2. In
L2, it is asserted identically to <resetname>. In L1.2, it is not asserted.
Synopsys, Inc.
- PHY in Reset
- DWC_pcie_clkrst.v asserts all PHY / Controller resets - Controller PMC in Reset
- Set app_ltssm_enable =0 for reprogramming before linkup. - Controller (other logic) in Reset
- Application keeps app_ltssm_enable =0 to disable link training - Reprogram Controller’s Registers [optional]
- Local application updates registers through DBI - Link Training Disabled
If you want to delay link re-establishment (after reset) so that you can reprogram some registers through
DBI, you must set app_ltssm_enable =0 as shown in Figure 2-16.
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Figure 2-16 Delaying the Link Training After Cold Reset (Run a Simulation to Obtain Accurate Timing)
#
pipe_clk
core_clk
aux_clk
power_up_rst_n
pwr_rst_n
phy _rst_n
core_rst_n
non_sticky_rst_n
sticky_rst_n
To postpone Link Training;
set app_ltssm_enable =0
when core_rst_n -> 0;
app_ltssm_enable and release when finished programming
Synopsys, Inc.
Figure 2-17 PCIe Cold Reset Sequence with PHY Initialization (CX_PHY_VIEWPORT_ENABLE =1)
- VMAIN Power Good (perst_n =1)
- Application asserts Power-On Reset (power_up_rst_n)
For PHY Initialization information when CX_PHY_VIEWPORT_ENABLE =1, see Figure 3-2 on page 81.
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phy_reset (!power_up_rst_n)
aux_clk/phy_reg_clk Active
power_up_rst_n
Application
app_hold_phy_rst
Logic
app_ltssm_enable
Active
muxd_aux_clk/aux_clk_g Active (aux_clk)
(pclk)
core_rst_n
non_sticky_rst_n
sticky_rst_n
clk/rst -
phy_reg_rst_n
Controller
Interface
pm_req_phy_rst
pm_req_core_rst
(sticky/non_sticky)
pm_sel_aux_clk
■ To obtain accurate timing of PHY initialization after cold reset you must run a simu-
Attention lation.
■ The controller's PHY Viewport (PRBI) to PHY registers can have high access
latency. If your application needs low latency to initialize Synopsys PHY registers or
SRAM, then PRBI should not be used. Instead, you should design a direct interface
to the PHY's SRAM or CR Bus. PRBI is recommended only for PHY debug.
Synopsys, Inc.
DWC_pcie_clkrst.v
link_req_rst_not
app_ltssm_enable
pm_req_phy_rst
pm_req_iso_vmain_to_vaux
pm_req_retention_rst
pm_req_core_rst
pm_req_non_sticky_rst
pm_req_sticky_rst
(Hot Reset)
From link_down event or
remote partner’s TS hot-
reset
Button
Reset
CONTROLLER
CORE
Core Logic LBC/DBI/ELBI
Vaux [aux_clk_g]
[core_clk]/
[radm_clk_g] [core_rst_n]
Power-On [core_rst_n]
Reset CDM (non-sticky)
(Cold Reset) PMBC [aux_clk_g]
[pipe_clk]/ [non_sticky_rst_n]
[core_clk_ug]
[pipe_msgbus_rst_n]/ CDM (sticky)
[pipe_rst_n]/ [aux_clk_g]
[core_rst_n] [sticky_rst_n]
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PCI Express SW Controller Databook Implementing the PCIe Resets
Figure 2-20 Reset Generation Module (Refer to RTL for Complete Design)
sync_reset
`1' pclk_link_down_rst_n test_rst_en
D Q D Q 0 sync_power_up_rst_n
muxd_aux_clk int_ret_core_rst_n
1 0 ret_core_rst_n
power_up_rst_n r r
0
dft_power_up_rst_n test_rst_n
1
test_rst_n
1
pm_req_retention_rst
test_rst_en sync_reset test_rst_en
`1'
D Q D Q 0 sync_button_rst_n int_non_sticky_rst_n ret_non_sticky_rst_n
muxd_aux_clk 0
1
button_rst_n r r test_rst_n
0 dft_button_rst_n 1
test_rst_n
1
pm_req_retention_rst
sync_reset test_rst_en
test_rst_en
`1'
D Q D Q 0 sync_perst_n int_sticky_rst_n
0 ret_sticky_rst_n
muxd_aux_clk
perst_n 1 test_rst_n
0 r r pm_req_retention_rst 1
dft_perst_n
test_rst_n
1
test_rst_en sync_reset test_rst_en
`1'
D Q D Q 0
int_mstr_axi_rstn
0 mstr_axi_resetn
mstr_axi_clk 1
r r test_rst_n
1
test_rst_en
sync_reset test_rst_en
`1'
D Q D Q 0
int_slv_axi_rstn
slv_axi_clk 0 slv_axi_resetn
1
r r test_rst_n
1
test_rst_en
sync_reset test_rst_en
`1'
D Q D Q 0
int_dbi_slv_rstn
dbi_axi_clk 0 dbi_axi_resetn
1
r r test_rst_n
1
test_rst_en
sync_reset test_rst_en
`1'
D Q D Q 0
int_pipe_rst_n
pipe_clk 0 pipe_rst_n
1
r r test_rst_n
1
test_rst_en
sync_reset test_rst_en
`1' pclk_link_down_rst_n
D Q D Q 0 sync_power_up_rst_n
muxd_aux_clk int_core_rst_n
1 0 core_rst_n
power_up_rst_n r r
0
dft_power_up_rst_n test_rst_n
1
test_rst_n
1
pm_req_core_rst
test_rst_en
test_rst_en sync_reset
`1'
D Q D Q 0 sync_button_rst_n
int_non_sticky_rst_n non_sticky_rst_n
muxd_aux_clk 0
1
button_rst_n r r test_rst_n
0 1
dft_button_rst_n
test_rst_n
1 test_rst_en
pm_req_non_sticky_rst
test_rst_en
int_sticky_rst_n
0 sticky_rst_n
test_rst_n
1
pm_req_sticky_rst
test_rst_en
int_pwr_rst_n
0 pwr_rst_n
test_rst_n
1'b1 0 1
link_down_rst_n
D Q
link_req_rst_not
1
app_ltssm_enable core_clk s
core_rst_n sync_generic
D Q D Q
pclk_link_down_rst_n
muxd_aux_clk r r
sync_generic
D Q D Q D Q D Q D Q 0
test_rst_n
auxclk s auxclk s s auxclk s auxclk s 1
Synopsys, Inc.
Figure 2-21 Delaying the Controller Hot Reset (Run a Simulation to Obtain Accurate Timing)
pipe _clk
core_clk
aux _clk Software asserts the Secondary Software de-asserts the
Bus Reset (SBR) Secondary Bus Reset
BRIDGE_CTRL_PIN_LINE_REG.SBR
(Secondary Bus Reset)
link_req_rst_not
non _sticky_rst_n
core_rst_n
slv_aresetn
mstr_aresetn
sticky_rst_n
pwr_rst_n To postpone ‘Reset Mode’; set app_ltssm_enable=0 immediately (combinatorially) when smlh_req_rst_not ->0.
The bridge enters ‘Reset Mode’ when it has finished ‘Flushing Mode’ and app _ltssm_enable=1.
app_ltssm_enable
slv_*ready
MODE Normal Mode Flushing Mode (variable duration depending on number of outstanding transactions ) Reset Mode Normal mode
If you want to delay link re-establishment (after reset) so that you can reprogram some registers through
DBI, you must set app_ltssm_enable =0 immediately after core_rst_n as shown in Figure 2-22. Also
applies to non-AXI configurations.
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Figure 2-22 Delaying the Link Training After Hot Reset (Run a Simulation to Obtain Accurate Timing)
pipe_clk
core_clk
aux_clk
link_req _rst_not
non_sticky_rst_n
core_rst_n
slv_aresetn
mstr_aresetn
phy _rst_n
sticky_rst_n
pwr_rst_n To postpone ‘Link Training;
set app_ltssm_enable =0 immediately
(combinatorially)
app_ltssm _enable after core_rst_n ->0.
Unless app_ltssm_enable is de-asserted immediately in Detect state, the controller continues to link up. If
app_ltssm_enable is de-asserted or the controller is reset when the controller is out of the Detect state, the
LTSSM moves immediately back to the Detect state. This transition is not defined in the PCIe Specification
and might cause a PIPE protocol violation.
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Figure 2-23 Queue Architecture (512-bit Controller has Formation/Serialization Queue Before Receive Queue)
BYP‡
Receive Queues
CPL F I F O Output Pipe
(3-4 cycles )
TRGT1‡
P F I F O /CDM
/ELBI
NP F I F O trgt1_radm_halt
‡
CDM and ELBI are also possible destinations in an upstream port .
Queue Modes
The three possible queue modes for posted, non-posted and completion TLPs are described in Figure 2-9.
Table 2-9 shows the division of functionality for these actions between the controller and your application
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PCI Express SW Controller Databook Receive Queue Architecture
RADM_<P|NP|CPL>_QMODE_VCn
Your application.
Credit Manager Controller Controller Not necessary if infinite
credits advertised.
a. Cut-through mode decays into store-and-forward mode when the queues become full; if there is more than one TLP in
the buffer when the queue is in cut-through mode, the TLPs being received are treated the same as store-and-forward
mode. Only the first TLP in the queue behaves in cut-through mode.
b. For more information, see “TRGT1 Packet Grant and Halt” on page 291.
c. “CPL must not pass a previously-issued P” rule is violated, which is only a problem when you have a real “Producer-
Consumer” scenario. For more information, see “PCIe Ordering Rules” on page 969.
d. This is the default operation. You can optionally configure the controller to forward the corrupt TLP (not recommended).
For more information, see “Advanced Information: Advanced Error Handling for Received TLPs” on page 981.
e. When the controller signals an error or abort indication to your application at the end of the TLP, you must discard that
TLP. For more information, see “Advanced Information: Advanced Error Handling for Received TLPs” on page 981.
The following tables show which queue modes can be used in which controller configurations. You can set
the queue mode independently for each VC.
Table 2-10 Supported Queue Modes for 32-bit, 64-bit, and 128-bit Datapath (Default is Marked D)
Posted D Y Ya
Non-Postedb D Y Y
Completion D Y Y
a. In this configuration you cannot send posted requests to the ELBI interface; that is, you cannot memory map the
port logic registers.
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b. You cannot put the non-posted receive queue in bypass mode because the controller needs to manage credits for
both internally consumed non-posted TLPs (for example CFG requests to internal registers in the CDM), as well
as credit returns that are stalled while the controller is waiting to return completions to the remote link partner.
Table 2-11 Supported Queue Modes for 256-bit Datapath (Default is Marked D)
Posted D Y -
Non-Posted D Y -
Completion D Y -
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PCI Express SW Controller Databook Configuring Your Queues
S/F S/F
No buffering.
Yes Assumption is that your
Infinite
application logic can always
Credits
accept all of the the read data
that it requested.
Yes WARNING!
Internal and external backpressure
might cause overflow. See Note (c)
Core Auto-Calculates
For configurations with a 256-bit core
Credits and Buffer datapath, there is an additional
Sizes (from Credits) possibility of queue overflow even when
your application does not halt the queue.
This is caused by the fact that the
internal pop rate of very small
Set CX_APP_RD_REQ_SIZE completions from the receive queue is
= your application’s max less than the push (arrival) rate from the
individual read request size PCIe wire.
WARNING!
When a CPL is blocked by a P, then
Core Auto-Calculates there is a risk that the queue will
Buffer Sizes – see overflow.
Note (b)
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■ (a) For more information, see “PCIe Ordering Rules” on page 969.
Note
■ (b) Size = (CX_MAX_TAG + 1) * (CX_APP_RD_REQ_SIZE + 1)
■ (c) A CPL buffer that advertises infinite credits and that is configured in
store-and-forward or cut-through modes, is not protected from overflow by the
"flow-control: credit-return" protocol. If you do not size the buffer to accept all of the
data that you have requested, the queue might overflow when the P queue is blocked
and the controller halts delivery of CPLs to your application when it is enforcing the
CPL must not pass P ordering rule. If you do not have a local Producer-Consumer
scenario, you can set the RO bit of the outbound NP requests to 1 so that CPL can
overtake P requests in the queue. For more information, see “PCIe Ordering Rules”
on page 969.
■ In the unlikely event that the buffer RAMs overflow, the controller asserts the
radm_qoverflow output. If overflow is caused by a lack of credits for incoming TLPs
(causing a TLP to be discarded), the controller sets the Receiver Overflow bit in the
AER Status Register.
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PCI Express SW Controller Databook Controller Operations
3
Controller Operations
This section describes the operations of the PCI Express controller. The topics in this section are:
■ “Initialization” on page 80
■ “Link Establishment” on page 83
■ “Transmit TLP Processing” on page 87
■ “Receive TLP Processing” on page 94
■ “Register Module, LBC, and DBI” on page 99
■ “Reliability, Availability, and Serviceability (RAS)” on page 124
■ “Messages” on page 152
■ “Interrupts” on page 170
■ “Flow Control” on page 176
■ “Internal Address Translation Unit (iATU)” on page 178
■ “Gen2/3/4/5 Speed Modes” on page 206
■ “Power Management” on page 213
■ “Completion Timeout Ranges” on page 254
■ “Crosslink” on page 255
■ “TLP Processing Hints” on page 256
■ “Atomic Operations (AtomicOps)” on page 257
■ “TLP Prefix” on page 259
■ “Separate Refclk Independent SSC (SRIS)” on page 260
■ “Readiness Notifications (RN)” on page 261
■ “Precision Time Measurement (PTM)” on page 263
■ “Access Control Services (ACS)” on page 271
■ “Completion Queue Management” on page 273
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3.1 Initialization
Immediately upon powerup the SW controller goes into either upstream or downstream port mode,
depending on the state of the device_type input. If you have enabled crosslink (CX_CROSSLINK_ENABLE
=1), then the determination of the device type is different.
LTSSM
Detect
DBI Programming
Your local application can reprogram the controller’s sticky registers before link
training
LTSSM
L0
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PCI Express SW Controller Databook Initialization
phy_reg_clk
CLK phy_reg_clk_g
Gating
core_clk
auxclk
aux_clk/
Mux
pclk aux_clk_g
pm_sel_aux_clk
pm_req_phy_rst
!power_up_rst_n
pm_req_core_rst/pm_req_sticky_rst/pm_req_non_sticky_rst
phy_reset phy_rst_n
pipe_laneX_reset_n Reset Logic
phy_reg_rst_n
Reset core_rst_n
Logic sticky_rst_n
non_sticky_rst_n
cr_para_clk Configuration
Register
Control Register Bus Interface PHY View Port
Register
Control/Status signals for
app_ltssm_enable
app_hold_phy_rst
PHY Initialization
DBI
power_up_rst_n
phy_reg_clk
auxclk
Application Logic
The controller's PHY Viewport (PRBI) to PHY registers can have high access latency. If your
Attention application needs low latency to initialize Synopsys PHY registers or SRAM, then PRBI should
not be used. Instead, you should design a direct interface to the PHY's SRAM or CR Bus.
PRBI is recommended only for PHY debug.
For more information on cold reset sequence with PHY initialization see Figure 2-17 on page 68. For more
information on PHY initialization after cold reset, see Figure 2-18 on page 69.
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PCI Express SW Controller Databook Link Establishment
a. Previous versions of the Databook described a method of link resizing by taking the link down, and transitioning the LTSMM
from L0 -> Recovery -> Loopback -> Detect. The controller still supports that method for legacy designs (see previous version
of databook for more information), but new designs should use the method described here.
b. Called UpConfigure in the PCI Express Specification.
c. If the lanes are reversed, your application must manually flip the lanes to achieve downsizing for some configurations. For more
information, see “Link Down-sizing with Non-reversed/Reversed Lanes; and Wide/Narrow Ports” on page 921.
The following steps show how you can initiate link resizing:
1. Ensure the link is in the L0 LTSSM state.
2. Program the TARGET_LINK_WIDTH[5:0] field of the MULTI_LANE_CONTROL_OFF register.
3. Program the DIRECT_LINK_WIDTH_CHANGE2 field of the MULTI_LANE_CONTROL_OFF register.
It is assumed that the PCIE_CAP_HW_AUTO_WIDTH_DISABLE field in the
LINK_CONTROL_LINK_STATUS_REG register is 0.
1. Resizing (up or down) only occurs if both link partners advertised the Upconfigure Capability bit. In cases of link reliability,
the PCIe specification permits the remote partner to initiate downsizing regardless of the value of this bit. You must set the
UPCONFIGURE_SUPPORT field in MULTI_LANE_CONTROL_OFF so that the controller advertises 1 in the Upconfigure
Capability bit of the TS2 OS. Default for this field comes from DEFAULT_UPCONFIGURE_SUPPORT parameter.
2. The controller clears the contents of this register after it has accepted the request.
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If your system has reversed lanes in Gen3, Gen4, or Gen5 mode, then you should perform
Note
upsizing at Gen1 or Gen2 speed only. Otherwise, there is a risk of link-down caused by LFSR
mismatching.
For Gen3 and above, the controller does not send the first EIEOS before the first TS1 OS in
Configuration.Linkwidth.Start state for the upconfiguring lanes because of the requirement
that TxDataValid and TxElecidle signals must be aligned with other active lanes. After the first
EIEOS, the upconfiguring lanes send all Ordered Sets including EIEOS, in the same manner
as the other active lanes.
Figure 3-3 to 3-5 show the muxing logic implemented in the controller as a function of parameters
CX_LANE_FLIP_CTRL_EN and CX_AUTO_LANE_FLIP_CTRL_EN.
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PCI Express SW Controller Databook Lane Reversal and Flipping
6 6
2
5 5
1
4 4 Logical Lane0
0
Remote Link
Partner
3 3
2 2
1 1
0 0 Physical Lane0
Logical Lane 0
CX_LANE_FLIP_CTRL_EN = 1
CX_AUTO_LANE_FLIP_CTRL_EN = 0
Manual Flip
rx_lane_flip _en =1 /
tx_lane_flip _en =1
Flip Mux
7
0
4 Logical Lane 0
Remote Link
Partner
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CX_LANE_FLIP_CTRL_EN = 0
Logical Lane0
0
Physical Lane0
Remote Link
Partner
For more information, see “Advanced Information: Lane Reversal and Broken Lanes” on page 919.
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PCI Express SW Controller Databook Transmit TLP Processing
TLP
Round Robin
Arbiter
No DLLP pending
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TLPs from the transaction layer (in the following order of priority):
■ Messages generated by the controller (including by your application through the MSI interface)
■ Upstream ports: Completions generated by the controller (including memory or I/O mapped appli-
3 cation register space) for Type 0 configuration read and write requests, or responses to error condi-
tions (unsupported requests)
■ Downstream ports: Completions generated by the controller for unsupported requests or completer
aborts
2 NAK DLLP
All transmit client interfaces XALI0/1/2 are served using one of the three arbitration schemes when credit
is available, regardless of the type of transaction. You can change the arbitration scheme using the
CX_XADM_ARB_MODE configuration parameter when CX_NVC >1.
■ 0: VC Based. Provides a VC-based programmable weighted round robin arbitration (WRR) using two
different arbitration methods for the two groups of VCs:
❑ Strict Priority for the High-Priority VC (HPVC) group
❑ RR or WRR for the Low-Priority VC (LPVC) group
Between the two groups of VCs, arbitration is as follows:
❑ The HPVC group is always the highest priority. Within the HPVC group, priority order is by VC
ID. The highest VC ID has the highest priority. Ties within the HPVC are resolved by client-based
Strict Priority arbitration; XALI0 has lowest, XALI1 higher, and XALI2 (if implemented) highest
priority.
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PCI Express SW Controller Databook Transmit TLP Arbitration
❑ The LPVC group is of lower priority than the HPVC group. Within the LPVC group, priority is
determined by RR or WRR arbitration as described later. Ties within the LPVC group are resolved
by client-based RR arbitration.
For more information, see “Advanced Information: VC-Based Arbitration” on page 948.
■ 1: Round Robin (RR). Provides round robin arbitration between the three transmit clients. This is the
default method.
■ 2: Strict Priority. Provides strict priority between the three transmit clients. XALI0 is lowest, XALI1 is
higher, XALI2 (if implemented) is highest.
The controller checks that enough flow control (FC) credits are available in the remote device for the specific
type of transaction (posted, non-posted, completion) before allowing a transmission of a TLP. TLPs that
passed the credit check are arbitrated according to the supported arbitration method. Internally generated
completions and messages are also gated by the arbitration logic, though at highest priority, and must also
pass the FC credit test before they are accepted for transmission.
For example when using the RR scheme, when a posted (P) transaction is presented onto XALI1 followed by
a completion (CPL) on XALI0, and when credits permit, then the P transaction is transmitted onto the wire
before the CPL. When the credit is not available then the CPL on XALI0 can pass the P transaction on XALI1
and be sent onto the wire. However, any non-posted (NP) or CPL TLPs on XALI1 (behind the blocked P) are
blocked by the halted P. It is the responsibility of your application to make appropriate use of the three
interfaces. There is no guarantee that order is preserved among client interfaces.
When your application is using a single transmit client interface for more than one TLP type (for example,
posted and non-posted), and the current request (for example, a posted request) is being blocked due to lack
of available FC credits, then that client interface is effectively blocked from sending other requests (for
example, non-posted) even though credits might be available for that type. To avoid this situation, your
application can use different transmit client interfaces for different request types (for example, XALI0 for
posted requests, XALI1 for non-posted requests, and XALI2 for completions). Another way your application
can avoid this situation is to monitor the current FC credit availability on the xadm_*_cdts outputs from
the controller and only generate requests for which FC credits are available.
When using xadm_*_cdts to monitor credit availability, your application must consider that it is possible
that the controller might generate a message or completion TLP (which would change the number of credits
available), between the time your application samples xadm_*_cdts and when your application generates
the request. To avoid this scenario, your application can use the Application Credit Control feature, for
more information, see “Application Credit Control” on page 89.
For more information on flow control, see “Flow Control” on page 176. For more information on TLP
ordering, see “Advanced Information: Advanced Ordering Information” on page 968. For more information
on how to select the client interfaces, see the “Configuration Guide” appendix in the User Guide.
The optional application credit control feature (APP_CREDIT_CTRL =1) allows your application to monitor
and control the credit expenditure. In addition to a reporting interface for all credit consumption, an
interface is provided to grant your application control over transmission and credit consumption of internal
controller generated messages and completions. Only when your application grants the credits for
internally generated messages and completions, these TLPs enter arbitration. Using this feature your
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application can maintain an accurate credit count and define packet ordering to achieve the best
performance when using a single transmit client interface for more than one TLP type (for example, posted
and non-posted).
The credit control handshake between the controller and your application, as depicted in Figure 3-7, is as
follows:
■ Credit Request (controller => application)
The controller requests your application to grant credits for internally generated messages/comple-
tions by asserting the output signals xadm_crd_*_h_req/xadm_crd_*_d_req/xadm_crd_*_vc1.
■ Credit Grant (controller <= application)
Only when your application grants the credits by asserting app_crd_ms-
g_grant/app_crd_cpl_grant signals the internally generated messages/completions TLPs enter
arbitration, and are immediately transmitted by the controller.
■ Credit Consumption (controller => application)
The output signal xadm_*_consumed indicates that the granted credit has been consumed by the
controller.
Figure 3-7 Credit Control Handshake Between the Controller and Your Application
CLK
XADM?CRD? ?H?REQ
XADM?CRD? ?D?REQ
XADM?CRD? ?VC;=
XADM?CRD? ?CONSUMED
APP?CRD? ?GRANT
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PCI Express SW Controller Databook Transmit Replay
SET
D Q
LANE_SKEW_OFF register Enable ACK/NAK
ACK_NAK_DISABLE field request
CLR Q ACK Latency Timer
SET
reset
D Q
timer
TIMER_CTRL_MAX_FUNC_NUM_OFF register x64 + limit
TIMER_MOD_ACK_NAK field limit
CLR Q
increment reached
SET
D Q
ACK_LATENCY_TIMER_OFF register
ROUND_TRIP_LATENCY_TIME_LIMIT field
(automatically set; see register description) CLR Q
ACK Fr equency Counter
High Priority
SET ACK_FREQ counter ACK Request
D Q
limit
limit ACK_FREQ
ACK_F_ASPM_CTRL_OFF register reached
ACK_FREQ field TLPs received
CLR Q != 0 enable
increment
Low Priority NAK
ACK Request Request
When a low priority ACK request is scheduled for transmission to the remote link partner, the
Note
controller waits until either the ACK Latency Timer or the ACK Frequency Counter expires, then
converts the low priority ACK request to a high priority ACK request, and schedules it for
transmission to the remote link partner.
TX Processing Path
TX
Replay
Buffer
RAM
SET
Replay Timer
D Q
TIMER_CTRL_MAX_FUNC_NUM_OFF register x64 timer
TIMER_MOD_REPLAY_TIMER field
+ limit
CLR Q
SET
D Q
ACK_LATENCY_TIMER_OFF register reset limit
REPLAY_TIME_LIMIT field reached
(automatically set; see register description) CLR Q
Expired
Begin Replay
ACK NAK
Received Received
RX Processing
RX Processing
Path Path
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The interface progression timer module instantiates a watchdog timer and timeout detection units in the
interfaces to be monitored. The application sets a window for monitoring transfer progression by
programming the watchdog timer period through INTERFACE_TIMER_TARGET_OFF register. The watchdog
timer signal is connected to the timeout detection units. When a change occurs in the watchdog timer signal,
the timeout detection unit checks the interface signals to determine if the interface is halted, and sets a flag.
For example, on XALI0/1/2, if client*_tlp_hv =1 and xadm_client*_halt =1 the timeout detection
unit sets the flag. This flag is reset if the interface is progressing. If the flag is found to be set on the next
change to the watchdog timer signal, interface timeout status signal (if_timeout_status ) is asserted.
This indicates to the application that a progression timeout has occurred on one of the interfaces. The
application can then read the INTERFACE_TIMER_STATUS_OFF register to determine which interface is
causing the timeout.
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PCI Express SW Controller Databook Tx Interface Progression Detection (CX_INTERFACE_TIMER_EN =1)
XALI1
For each of the above inter faces a timeout
detection unit is implemented.
When CX_INTERFACE_TIMER_EN =1,
2-5 timeout detection units are instantiated by
XALI2 the Progression Detection module, depending
upon your configuration.
INTERFACE_TIMER_STATUS_OFF register
SET
DS Q @ posedge
if_timeout_status 1. Read INTERFACE_TIMER_STATUS_OFF to locate halted transmit
interface
Register Write ‘1’ RCLR Q 2. Write ‘1’ to INTERFACE_TIMER_STATUS_OFF to clear status bit
INTERFACE_TIMER_CONTROL_OFF register D
SET
Q
AER Msg Generation
INTERFACE_T IMER_AER_EN field (MSG_GEN)
CLR Q
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P
TLP Filtering
CXPL
TRGT1
Routing NP
RBYP
Message
Processing
CPL
RTRGT0
MSG
ERR
MSG
DBI
LBC CFG Data CDM
ELBI
The following general rules apply to all incoming TLPs that are not malformed. For more information on
what happens to malformed TLPs, see “Error Detection for Received TLPs” on page 97. By default:
■ For a function in device power states D1, D2, and D3hot, the controller only accepts CFG and MSG
requests TLPs for that function. All other incoming request types for that function are treated as
unsupported requests (UR).
■ When the controller detects an error1 in a received TLP, it normally performs the following:
❑ Discards the TLP
❑ Generates a completion (for non-posted requests) with the completion status set to CA or UR
1. Excluding TLPs targeted for forwarding (and not for local resources) that have ECRC errors.
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For more information on advanced filtering, see “Advanced Information: Advanced Filtering and
Note Routing of TLPs” on page 954
TLPs that the controller receives over the link in a switch application fall into the following general classes:
■ TLPs that are to be routed through the switch to another port of the switch. The controller transfers
this class of TLP to your application through the TRGT1 interface. This category includes type 1 config-
uration requests that are received by an upstream switch port and must be sent downstream.
■ Configuration requests that target the controller. The controller processes this class of TLP internally
and automatically generates the required completion.
■ Memory or I/O requests that target the switch application logic. The controller transfers this class of
request to your application through the ELBI and automatically generates the required completion.
Memory and I/O requests targeted to the switch application logic are limited to single-dword
accesses.
The possible destinations of a posted or non-posted request TLP are TRGT1, TRGT0, and Discard1. By
default:
■ CFG0 requests are routed to TRGT0 and then to CDM through the LBC.
■ CFG1 requests are routed to TRGT1.
■ All of the following are routed to TRGT1:
❑ MEM requests inside of the memory range or prefetchable memory range as determined by the
corresponding Base and Limit fields in the Type-1 header.
❑ I/O requests inside of the I/O range as determined by the I/O Base and Limit fields in the Type-1
header.
❑ BAR-matched MEM (not I/O) requests.
■ MSG requests are decoded internally, signaled on the SII interface, and then terminated.
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BAR memory region must always be outside the memory range as determined by the
Attention corresponding Base and Limit fields in the Type-1 header.
Figure 3-12 Default Request TLP Routing (Assuming no TLPs with CA/CRS/UR Error Status)
core
CDM
config CDM LBC TRGT0 CFG0
data LBC
TRGT1 CFG1
TRGT1 MEM/IO
C
X
P
TYPE 1 L
MEM & IO
Base & Limit
Checks
TRGT1 MEM
BAR Address
Check
BAR
TRGT1
SII MSG
The possible destinations of a completion TLP are TRGT1 and Discard1. Completions are not filtered inside
the SW filter. This is under an assumption that the SW does not generate a request locally. If an embedded
EP is involved in a switch application, there should be some modifications based on the requirements of
your application.
The possible destinations of a posted or non-posted request are TRGT1 and Discard2. By default:
■ MEM requests outside of the memory range and prefetchable memory range as determined by the
corresponding Base and Limit fields in the Type-1 header, are routed to TRGT1.
■ I/O requests outside of the I/O range as determined by the corresponding Base and Limit fields in the
Type-1 header are routed to TRGT1.
■ MSG requests are decoded internally, signaled on the SII interface, and then terminated.
■ A downstream port does not expect to receive CFG requests.
■ BARs should be disabled and not used.
The possible destinations of a completion TLP are TRGT1 and Discard. Completions are not filtered inside
the SW filter. This is under an assumption that the SW does not generate a request locally. When an
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PCI Express SW Controller Databook Error Handling
embedded EP is involved in a switch application, there should be some modifications based on the
requirements of your application.
For configuration requests targeted to downstream switch ports, the upstream switch
Attention port passes the configuration request to your application on TRGT1. Your application
logic must respond to the configuration request by executing a transaction on the DBI of
the downstream port, then generating the completion and presenting it on one of the
upstream port's XALI interfaces.
For more information on switches, see “Introduction to PCIe Switches” on page 1006. Completions are not
filtered inside the SW filter. It is assumed that the SW does not generate a request locally. If an embedded
endpoint is involved in a switch application, there should be some modifications based on the requirements
of your application.
The controller performs all mandatory error detections, the error reporting mechanism based on the PCI
Express Base Specification, Revision 4.0, Version 1.0, and some optional error detections (using the
ENABLE_OPTIONAL_CHECKS parameter). For more information of what error conditions contribute toward
a UR or CA status, see “Advanced Information: Advanced Filtering and Routing of TLPs” on page 954.
When the controller detects an error1 in a received TLP, it normally performs the following:
■ Discards the TLP
■ Generates a completion (for non-posted requests) with the completion status set to CA or UR
■ Sets the status in the PCI-compatible status register
■ Sets the status in the AER registers (when you enable AER)
■ Generates an error MSG (upstream port only)
■ For malformed TLPs credit is returned based on the buffer space which has been consumed by the TLP
For more information see “Advanced Information: Advanced Error Handling for Received TLPs” on page
981
1. Excluding TLPs targeted for forwarding (and not for local resources) that have ECRC errors.
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The controller supports the AER multiple header logging as specified in Section 6.2.4.2, “Multiple Error
Handling (Advanced Error Reporting Capability)” of the PCI Express Base Specification, Revision 4.0, Version
1.0.
A valid queue entry is never overwritten. If your software does not read the header log registers fast
enough, you can miss the new header log information when the queue is full.
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Approx. (CDM)
0xD00 0x0000
(CDM)
0x700
Per Function Space
CS2 =1
CDM/ELBI Select Bit
=0
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PCI Express SW Controller Databook Register Configuration Space Overview
Approx. (CDM)
0xD00 0x0000
(CDM)
0x700
Per Function Space
CS2 =1
CDM/ELBI Select Bit
=0
Capability configuration registers are in structures (groups) identified by a capability ID. The groups are
linked together as in PCI. Register locations within a group are specified, but the starting location of each
group must be found by traversing the linked list.
There are two linked lists of register groups:
■ PCI compatible capability registers
PCI compatible capability register groups begin at the configuration address stored in the capability
pointer register at 0x34.
■ PCI Express extended capability registers
PCI Express extended capability register groups begin at address 0x100.
The capability pointer register in the PCI-compatible header register points to the next item in the linked list
of capabilities, which by default is the PCI Power Management capability.
For releases previous to 4.80a, the iATU registers have been programmed through an indirect
Attention addressing scheme using an index register (iATU_VIEWPORT_OFF), to reduce the address
footprint in the PCI Express extended configuration space. To use the legacy method of
accessing iATU and DMA registers, contact Synopsys support through Solvnet.
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There are three types of registers in the controller as shown in Table 3-4 on page 102
Register
Type Description Access/Addressing Method
Another register exists at the same address Normally can only be accessed through the DBI where
as a Simple register. For example the BAR you select between the two registers using the dbi_cs2
Shadow
Mask registers have the same address as the input . This is called DBI2, CS2, dbi_cs2, DBI_CS2, or
BAR registers. Dbi2 access; all of these terms mean the same thing.
There are three views for most registers in the controller (see Table 3-5 on page 102), depending on how you
access a register.
Table 3-6 describes the possible ways to access the controller registers in USP mode.
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Synopsys-Specific (Port
Register Type PCI-SIG Logic) User
DBI Y Y Y Y Y
CFG Request Y - Y - Y
Wire
BAR Matched MEM Request - - Yb Y Yc
In DSP mode, the controller register space is fully accessible from the DBI without any restrictions. There is
no wire access in RC Mode.
Your application can write to some read-only (RO) and HwInit registers over the DBI when you set the
“Write to RO Registers Using DBI” (DBI_RO_WR_EN) field of the MISC_CONTROL_1_OFF register to 1. The
app_dbi_ro_wr_disable input pin must be driven to 0 to allow writes to DBI_RO_WR_EN field. Setting the
app_dbi_ro_wr_disable input pin to 1 forces DBI_RO_WR_EN to 0, and disables writing to the
DBI_RO_WR_EN field.
Your application can write to some shadow registers using DBI CS2 accesses. For more information on DBI
CS2, see “Types of Register Views in PCIe Controller” on page 102.
For upstream ports (USP), you should set this to 1. For downstream ports, you can only program the PCIe
configuration space registers (in the CDM) using the DBI. There is no wire access for DSP. In this case, when
programming the Type-1 headers and capabilities, your host software can use the standard model of the
configuration space as in the PCI-SIG specification. Therefore register fields marked RO do not become
writable from the DBI. The exception to this is the SPCIE capability in a Gen3 configured device. RO
registers never become writable over the wire, regardless of the setting of this register bit. The same applies
for HwInit.
For configuration requests targeted to downstream switch ports, the upstream switch port
Note passes the configuration request to your application on TRGT1. Your application logic must
respond to the configuration request by executing a transaction on the DBI of the downstream
port, then generating the completion and presenting it on one of the upstream port's XALI
interfaces.
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DBI
CPU
4
CXPL PHY
Note: For DSP there is no
wire access to CDM or ELBI
CDM Core
Registers
Request flow
Response flow
XADM 5
TX PIPE
3 LBC forwards the request to external registers (through ELBI) or internal registers in CDM
4 LBC forms completion TLPs with response received from ELBI or internal registers in CDM
RX PIPE
Application RBYP
Logic: RADM
Receive TRGT1
CPU 1
DBI
CDM Core
Registers
Request flow
Response flow
XADM
TX PIPE
2 LBC forwards the request to external registers (through ELBI) or internal registers in CDM
3 LBC forms completion TLPs with response received from ELBI or internal registers in CDM
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PCI Express SW Controller Databook Local Bus Controller (LBC)
CPU 1
DBI
LBC CIC
2
CXPL Core
3
CXPL PHY
CDM Core
Registers
Request flow
Response flow
XADM
TX PIPE
3 LBC forms completion TLPs with response received from registers in CDM
The LBC is single-threaded. Therefore the DBI and PCIe wire cannot use the LBC at the same time. A
non-posted PCIe wire transaction is not considered to be complete until the XADM has accepted the
completion for transmission. If there are not sufficient TX completion credits, then the LBC remains locked
and unavailable for the next request (from the DBI or PCIe wire). A request on the DBI is not accepted when
a PCIe wire transaction is already in progress, therefore, you must not use the ELBI to drive the DBI. This
would result in a deadlock of the LBC. When the DBI and the PCIe wire start a request at the same time
(regardless of the target/destination of each request), then the LBC grants access to the PCIe wire (TRGT0).
3
ELBI (external local
DBI bus interface )
4
1 Inbound PCIe request to read /write the PCIe core’s internal configuration space registers .
2 Inbound PCIe request to read /write external application specific registers .
3 Local CPU request at DBI to read/write PCIe core’s internal configuration space registers .
4 Local CPU request at DBI to read/write external application specific registers .
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3.5.3.1 Overview
The controller address space can be accessed from the wire using CFG request, BAR matched MEM request,
or BAR matched IO request in USP mode. Table 3-7 gives information of which address space can be
accessed through which type of request from the wire.
In DSP mode the controller address space cannot be accessed from the wire.
CFG Request Y - Y - - Y
TLP Routing
Wire Access Type Allowed Path Normal Shadow Misc Rsvd IATU DMA Misc
(Figure 3-18)
CFG Request
Address >= 0x0 1 Ya - - - - - -
Address < 0x700
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CFG Request
Address >= 0x700 1 - - Y - - - -
Address <= 0xD00
CFG Request
Address > 0xD00 1 - - - Y - - -
b
Address <= 4*CONFIG_LIMIT_REG
CFG Request
(Address > 4*CONFIG_LIMIT_REG; 2 - - - - - - Yc
TARGET_ABOVE_CONFIG_LIMIT_REG
=ELBI)
CFG Request
(Address > 4*CONFIG_LIMIT_REG; 3 - - - - - - -
TARGET_ABOVE_CONFIG_LIMIT_REG
=TRGT1)
a. To access the Standard Capabilities and the PCIe Extended Capabilities, you should not use an absolute address but should
traverse the linked link using the “next” pointer of each capability.
b. MISC_CONTROL_1_OFF.CONFIG_LIMIT_REG (default =0x3FF DWORDs, which is 0xFFF bytes) specifies a DWORD
address limit, above which incoming CFG requests are routed to the destination defined by MISC_CON-
TROL_1_OFF.TARGET_ABOVE_CONFIG_LIMIT_REG, which can be ELBI or TRGT1 (default). CONFIG_LIMIT_REG is
normally set to a limit that divides the controller's configuration space registers in CDM from your application's external config-
uration space registers on ELBI. The default corresponds to the 0xFFF (4K bytes) upper limit of configuration space, and so
the controller consumes all CFG transactions by default. CONFIG_LIMIT_REG must be set to a value lower than this to have
an effect. Normally, you would never set it to less than 0x340 DWORDs (equivalent to 0xD00 bytes) which is the top of the
Synopsys Port Logic register space.
c. The function number (PF) that is being accessed is identified by a 1 on the corresponding lbc_ext_cs[NF-1:0] output bit loca-
tion. When the function is a VF, then it is identified on the lbc_ext_vfunc_active and lbc_ext_vfunc_num[NVF_WD-2:0]
outputs. The controller sets lbc_ext_bar_num[2:0] =3’b111 for all ELBI CFG accesses.
TRGT1
For configuration requests targeted to downstream switch ports, the upstream switch port
Attention passes the configuration request to your application on TRGT1. Your application logic must
respond to the configuration request by executing a transaction on the DBI of the downstream
port, then generating the completion and presenting it on one of the upstream port's XALI
interfaces.
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A MEM/IO access with a TLP address within the range of any enabled memory BAR of any function (PF or
VF), is routed to the destination indicated by the BAR target parameter MEM_FUNC#_BAR#_TARGET_MAP of
the matched BAR. Table 3-9 shows the possible TLP routing paths for MEM/IO requests.
TLP
Routing
Wire Access Type Alloweda Path Normal Shadow Misc Rsvd IATU DMA Misc
(Figure 3-1
9)
a. You cannot memory map Posted requests when the Posted queue is in bypass mode.
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PCI Express SW Controller Databook PCIe Wire Access
b. Or VF_MEM_FUNC#_BAR#_TARGET_MAP for VFs. For other functions and BARs, change to FUNC# and BAR# respec-
tively.
c. The accessed function number (PF) s identified by a 1 on the corresponding lbc_ext_cs[NF-1:0] output bit location. When
the function is a VF, then it is identified on the lbc_ext_vfunc_active and lbc_ext_vfunc_num[NVF_WD-2:0] outputs. The
matched BAR number is identified by lbc_ext_bar_num[2:0]. For an I/O access, the controller also asserts the lbc_ext_io_-
access output.
d. Byte address.
BAR
* CX_NFUNC
MEM_FUNC#_BAR#_TARGET_MAP
MEM_FUNC0_BAR1_TARGET_MAP
MEM_FUNC0_BAR0_TARGET_MAP
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❑ ENABLE_MEM_MAP_UNROLL_DMA_REG =1
❑ UNROLL_DMA_OFFSET_BAR =dma_offset_bar
ATU:
❑ ENABLE_MEM_MAP_UNROLL_ATU_REG =1
❑ UNROLL_ATU_OFFSET_BAR =atu_offset_bar
Then a MEM access with a TLP address within the range of memory BARn of physical function N, and
whose address offset is in the range (UNROLL_ATU_OFFSET_BAR to UNROLL_ATU_OFFSET_BAR+
UNROLL_ATU_SIZE1/UNROLL_DMA_OFFSET_BAR to UNROLL_DMA_OFFSET_BAR+UNROLL_DMA_-
SIZE1), is routed to the iATU/DMA registers. Parameters UNROLL_DMA_OFFSET_BAR and
UNROLL_ATU_OFFSET_BAR default to 02.
This is called “Memory Mapping” the iATU and DMA configuration registers. When you configure
the posted queue mode as bypass (in the segmented-buffer queue architecture), you cannot memory
map the iATU and DMA configuration registers.
ELBI Access
When MEM_FUNC#_BAR#_TARGET_MAP =TRGT0, then by default the BAR-matched MEM TLP is routed to
the ELBI. The accessed function number (PF) is identified by a 1 on the corresponding
lbc_ext_cs[NF-1:0] output bit location. When the function is a VF, then it is identified on the
lbc_ext_vfunc_active and lbc_ext_vfunc_num[NVF_WD-2:0] outputs. The matched BAR number is
identified by the lbc_ext_bar_num[2:0].When you configure the posted queue mode as bypass (in the
segmented-buffer queue architecture), you cannot send posted requests to the ELBI interface.
1. coreConsultant automatically calculates the size of the iATU and DMA address spaces (UNROLL_ATU_SIZE/
UNROLL_DMA_SIZE parameters) which are configuration-dependent.
2. If enabled the OFFSET is different. For example, UNROLL_ATU_OFFSET_BAR =h1000.
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PCI Express SW Controller Databook Data Bus Interface (DBI) Access
3.5.4.1 Overview
The DBI can access all 4096 bytes (1024 DWORDs) of the PCI Express configuration space per function. DBI
can also access iATU, DMA, MSI-X Table, and MSI-X PBA configuration space. This address space is fully
accessible from the DBI without any restrictions.
Table 3-10 Native Controller DBI Address Bus Layout for Accessing CDM
iATU
DMA 11
Address/Type Check
Shadow 10 D BAR5
Registers M BAR4
BAR3
U BAR2
Application BAR1
ELBI 01 X BAR0
Registers
* CX_NFUNC
RTRGT0
* CX_NFUNC CDM 00
Receive Filter
dbi_addr[0]
dbi_cs2
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Table 3-11 Native Controller DBI Address Bus Layout for Accessing CDM (dbi_cs2 =0)
The lower 12 bits are used to access the 4KB (1K DWORDs) of the PCI Express configuration space .
Table 3-12 Native Controller DBI Address Bus Layout for Accessing ELBI (dbi_cs2 =0; CX_LBC_EXT_AW
=5'd16)
Only 12-bits are needed to access the 4 KB (1K DWORDs) of the PCI Express configuration
Note
space per function. However, to access more than 4 KB of ELBI register space, you can
increase the value of CX_LBC_EXT_AW up to a maximum of 32-bits. The addressing scheme
described in Table 3-13 is used to access the extended ELBI address space.
Table 3-13 Native Controller DBI Address Bus Layout for Accessing ELBI (dbi_cs2 =0; CX_LBC_EXT_AW
=6'd32)
Table 3-14 Native Controller DBI Address Bus Layout for Accessing iATU and DMA Configuration
Registers(dbi_cs2 =1)
Access
Type 31-20 19 18-17 16-9 8 7-2 1 0
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PCI Express SW Controller Databook Access Limitations
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PHY#
PHY0 PHY1 PHY2 PHY3
x2 x2 x2 x2
PRBI
Controller
PHY Register
Controller
(PRC)
RADM
CDM
LBC
Port Logic Registers
CFG TRGT0 PHY Viewport Registers
PHY_VIEWPORT_CTLSTS_OFF
PHY_VIEWPORT _DATA_OFF
Control registers of all the PHY sub-blocks map to a single PHY_VIEWPORT_CTLSTS_OFF register. To
perform a read/write operation on the PHY, an indirect addressing mechanism is used, where first the
PHY_VIEWPORT_CTLSTS_OFF register is programmed through DBI (dbi_addr[0] =0 and dbi_cs =1) or
CFG to select the PHY block/lane to read from/write to, and then actual read/write on the PHY sub-block
happens.
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PCI Express SW Controller Databook PHY Port Logic Registers
PHY_VIEWPORT_ADDR
PHY0.lane0
PHY1.lane0
1 NAb 0 Address 0 Address
PHY2.lane0
PHY3.lane0
PHY0.lane1
PHY1.lane1
1 NAb 0 Address 1 Address
PHY2.lane1
PHY3.lane1
a. if PHY_VIEWPORT_ADDR[15] =1, all lanes inside sub-block selected by PHY_VIEWPORT_NUM are written.
b. if PHY_VIWEPORT_BWCR =1, PHY_VIWEPORT_NUM is not considered.
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PHY_VIEWPORT_ADDR
PHY0.lane0/PHY0.lane1
PHY1.lane0/PHY1.lane1
1 NAa 1 Address NA Address
PHY2.lane0/PHY2.lane1
PHY3.lane0/PHY3.lane1
PHY0.lane0
PHY1.lane0
1 NAa 0 Address 0 Address
PHY2.lane0
PHY3.lane0
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PCI Express SW Controller Databook BAR Details
3.5.7.1 RC Mode
3.5.7.1.1 Overview
Base Address Registers (Offset: 0x100x14)
Downstream Port: Two BARs are present but are not expected to be used. You should disable them (see
“Disabling a BAR” on page 119) to avoid unnecessary memory assignment during device enumeration. If
you do use a BAR, then you should program it to capture TLPs that are targeted to your local
non-application memory space residing on TRGT1, and not for the application on TRGT11. The BAR range
must be outside of the three Base/Limit regions. The controller provides one pair of 32-bit BARs (BAR0 and
BAR1). The BARs can be configured as follows:
■ One 64-bit BAR: BAR0 and BAR1 are combined to form a single 64-bit BAR.
■ Two 32-bit BARs: BAR0 and BAR1 are two independent 32-bit BARs.
■ One 32-bit BAR: BAR0 is a 32-bit BAR and BAR1 is either disabled or removed from controller alto-
gether to reduce gate count.
Upstream Port: Using MEM_FUNCN_BARn_TARGET_MAP you can configure each of the six BARs to capture
and route incoming MEM and I/O requests routed to:
■ 1: TRGT1
■ 0: TRGT0 (ELBI or Port Logic Registers)
1. Because in a DSP, there is no wire access to TRGT0 (ELBI or CDM) using CFG requests or BAR-matched MEM requests.
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■ For more information about routing requests to either TRGT1 or TRGT0 on a BAR-by-BAR
Note basis, see “Advanced Information: Advanced Filtering and Routing of TLPs” on page 954.
For more information on BAR operation, see “Receive Routing” on page 95.
■ If you have configured (MEM_FUNCN_BARn_TARGET_MAP =0) any BAR to have its
incoming requests routed to TRGT0 in upstream port, then you must disable1 that BAR
(through a DBI write) when operating the controller in downstream port. See “Disabling a
BAR” on page 119.
The following sections describe how to set up the BAR types and sizes by programming values into the base
address registers.
Figure 3-22 Fixed and Programmable Mask Example for 32-bit Memory BAR0 (CX_BAR0_SIZING_SCHEME_0 !=2)
DBI write
0
0 3:0
0 write 1
bar0_enabled data RO(cs)
0 0 1
write data 1
1 WO(cs2)
DBI write to 0x10 reset
DBI write BAR dbi_cs *
dbi_cs2 reset Enable
{ PREFETCHABLE_0_0,BAR0_TYPE_0,MEM0_SPACE_DECODER_0 }
Note: Register address decoding and register BAR0_ENABLED _0 * This is gated with theDBI _RO_WR_EN register field .
write enable generation not shown for clarity.
# The lower 8-bits of write data are overwritten with0xFF
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PCI Express SW Controller Databook BAR Details
Figure 3-23 Resizable BAR Example for 32-bit Memory BAR0 (CX_BAR0_SIZING_SCHEME_0 =2)
ResizableBAR Clear all bits that are changing from R/W to RO
0 Control Register
x28 BAR0 Register
0 encode Change read-write 0
1 RWS
data access of individual
1 0 31:4
BAR 0 register bits to 1
reflect the chosen BAR data
Wire write BAR Size RW
reset size 0x0 1
To
dbi_cs 2 x28 BAR
DBI write 0x0 RE S B A R_CTRL_RE G_0_RE G Address
Wire write
Matching
Logic in
reset Receive
dbi_cs Filter
0 DBI write
0
0
1 ROS(cs)
data 0 3:0
write 1
1 Resizable data
BAR RO(cs)
1
Capability
reset Register
DBI write to 0x10 reset
RE S B A R_CA P_RE G_0_RE G
dbi_cs
1
CX_BAR0_RESOURCE_AVAIL_N
{ PREFETCHABLE_0_0,BAR0_TYPE _0,MEM0_SPACE_DECODER_0 }
0
0 0
write data 1
WO(cs2)
1
DBI write BAR
Notes:
reset Enable
dbi_cs2 1 This is gated with theDBI_RO_WR_EN field.
2 The RESBAR _CTRL_REG_BAR _SIZE field is automatically updated when you write to RESBAR_CAP_REG_0_REG
through the DBI.
BAR0_ENABLED _0
After it selects a BAR size, it writes this value to the BAR Size field of Resizable BAR Control register. From
this field, the controller automatically derives the R/W mask for the BAR register. The host software can
now start the normal BAR query process. You can change the BAR size at runtime, because the “Supported
Resource Sizes” register field is writable through the local DBI (only).
3.5.7.1.4 General Rules for BAR Setup (Fixed Mask or Programmable Mask Schemes Only)
At runtime, application software can overwrite the BAR contents to reconfigure the BARs (unless the
affected BAR is removed during hardware configuration). Application software must observe the following
rules when writing to the BARs:
■ BAR0 and BAR1 can be configured as one 64-bit BAR, two 32-bit BARs, or one 32-bit BAR.
■ Any 32-bit BAR that is not needed can be removed during controller hardware configuration to reduce
gate count.
■ An I/O BAR must be a 32-bit BAR and cannot be prefetchable.
■ When BAR0 is configured as a 64-bit BAR:
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❑ BAR1 is the upper 32 bits of the combined 64-bit BAR formed by BAR0 and BAR1. Therefore, BAR1
must be disabled and cannot be configured independently.
❑ BAR0 must be a memory BAR and can be either prefetchable or non-prefetchable.
❑ The contents of the BAR0 mask register determine the number of writable bits in the 64-bit BAR,
subject to the restrictions described in “BAR Mask Registers” on page 120. The BAR1 mask register
contains the upper 32 bits of the BAR0 mask value.
❑ BAR0 can be disabled by writing 0 to bit [0] of the BAR0 mask register.
■ When BAR0 is configured as a 32-bit BAR:
❑ You can configure BAR1 as an independent 32-bit BAR or remove BAR1 from the controller hard-
ware configuration.
❑ BAR0 can be configured as a memory BAR or an I/O BAR.
❑ The contents of the BAR0 mask register determine the number of writable bits in the 32-bit BAR0,
subject to the restrictions described in “BAR Mask Registers” on page 120.
❑ BAR0 can be disabled by writing 0 to bit [0] of the BAR0 mask register.
■ When BAR0 is configured as a 32-bit BAR, BAR1 is available as an independent 32-bit BAR according
to the following rules:
❑ BAR1 can be configured as a memory BAR or an I/O BAR.
❑ The contents of the BAR1 mask register determine the number of writable bits in the 32-bit BAR1,
subject to the restrictions described in “BAR Mask Registers” on page 120.
❑ BAR1 can be disabled by writing 0 to bit [0] of the BAR1 mask register.
❑ When BAR1 is not required in your design, you can remove BAR1 from the hardware configura-
tion by setting both BAR1_ENABLED_0 and BAR1_MASK_TYPE_0 to 0.
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PCI Express SW Controller Databook BAR Details
3.5.7.1.9 Expansion ROM BAR Mask Register (Offset: 0x38; same as the Expansion ROM BAR, but
requires dbi_cs2/CS2 for write access)
Your local CPU can change the mask at runtime using the DBI. The mask register is at the same address as
the BAR register. The mask is a shadow register that is invisible to the PCIe wire but visible to the local
processor over the DBI. Furthermore, it is only visible for a write not for a read. So you cannot read the mask
register but you can write to it. The shadow register is accessed by asserting CS2 and CS. If you assert CS
(only) then you access the BAR which is the primary register at that location.
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Table 3-16 describes the parameters to consider for generating DocBook XML and HTML Register Reports.
Table 3-16 Parameters to Consider for Generating DocBook XML and HTML Register Reports
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PCI Express SW Controller Databook Generating Register Map
■ Even though there is a unique standard capabilities linked lists provided per function,
Note specific capabilities cannot be included/excluded on a per-function basis. For example,
MSI-X capability is included/excluded for all functions (PF) at the same time through the
coreConsultant GUI.
■ Even though there is a unique extended capabilities linked list provided per function,
specific capabilities cannot be included/excluded on a per function basis (in particular for
LTR and VC, this is a non-fatal violation of a strict reading of the PCIe specification).
■ Each function can have a different setup of a capability structure after it is included,
although some features/settings are common across all functions.
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3.6.1 Overview
PCIe system Reliability, Availability, and Serviceability (RAS) ensures that failures in the underlying
processes and hardware components do not cause any interruptions in the overall system operation.
Synopsys PCIe RAS consists of four fundamental components:
■ Reliable protocol architecture involving LCRC, ECRC, ACK/NAK handshake, and Replay mecha-
nisms.
■ Internal device-level Datapath and RAM protection (RAS DP) of data, header, and RAM control
signals from application I/F to LCRC extraction/generation points.
■ Debug, Error Injection, and Statistic gathering (RAS DES).
■ Hot-plug usage to swap out components with uncorrectable errors.
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PCI Express SW Controller Databook RAS Wire Protection (ECRC)
3.6.2.1 Generation
It is expected that the ECRC is already present in traffic that your application is presenting on the transmit
interfaces of the controller. The controller forwards it unchanged. You should set client0_tlp_td =0.
3.6.2.2 Checking
When the ECRC is present, the controller checks it and forwards it unchanged. To enable ECRC checking:
■ Set CX_ECRC_ENABLE =AER_ENABLE =CX_ECRC_STRIP_ENABLE =1
■ Set the ECRC_CHECK_EN field of the ADV_ERR_CAP_CTRL_OFF AER register.
By default, when the controller detects a TLP, targeted for local resources and not for forwarding, with an
ECRC error, it performs the following:
■ Discards1 the TLP
■ Generates a completion (for non-posted requests) with the completion status set to CA or UR
■ Sets the status in the PCI-compatible status register
■ Sets the status in the AER registers (when you enable AER)
❑ When an ECRC error is detected by a PF, with ECRC checking enabled for any PF, ECRC error
status is set for all PFs
❑ ECRC error status is not set for VFs and reads zero
■ Generates an error message (upstream port only)
A TLP, targeted for local resources and not for forwarding, with an ECRC error is never discarded.
1. You can program the controller to forward the TLP. For more information, see “Advanced Information: Advanced Error
Handling for Received TLPs” on page 981.
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3.6.3.1 Overview
For the parts of the controller outside of ECRC/LCRC protection, you can use the RAS DP feature
consisting of:
■ RAM Protection (ECC on data and Parity on address)
An ECC checksum is calculated and added to data that is written to the RAM. When the data is read
from the RAM, then the controller recalculates the ECC and compares it against the value read from
RAM. RAM ECC protection is provided for all of the RAMs in the controller, except for the RAS-DES
RAM. ECC corrects single-bit errors and reports (without correction) multi-bit errors.
■ Datapath Protection (ECC or Parity)
For Tx traffic, your local application logic must add ECC or parity protection codes1 to traffic using:
❑ client0_tlp_hdr_prot and client1_tlp_hdr_prot for the TLP header.
❑ Additional MSBs on client0_tlp_data and client1_tlp_data for the TLP data.
❑ Additional MSBs on client0_tlp_prfx and client1_tlp_prfx for the TLP prefixes.
For Rx traffic, your local application must check the protection codes on:
❑ radm_trgt1_hdr_prot and radm_bypass_hdr_prot for the TLP header.
❑ The MSBs on radm_trgt1_tlp_data and radm_bypass_tlp_data for the TLP data.
❑ The MSBs on radm_trgt1_tlp_prfx and radm_bypass_tlp_prfx for the TLP prefixes.
You can find a reference RASDP wiring template that has an example implementation of the
Attention application logic required to drive the controller's RASDP inputs and the expected outputs in:
workspace/examples/pcie_rasdp_glue.v. This file is for reference purpose only, it must
not be used as is.
1. For more information on how to calculate the protection codes, see the description of these signals in the Signal Descriptions
chapter.
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PCI Express SW Controller Databook RAS Data Protection (DP)
RAM
RBYP
RX PIPE
TRGT1 RADM
TRGT0
CIC
Application ELBI LBC
Registers
iATU
CXPL Core
PHY
Application MSI CDM Core
Logic :
MSI(-X) MSI-X
Registers
RAS
Application
Logic : RAM
SII
Rx Vendor
Messages
CPU DBI
XALI0
XADM
XALI2
Application
Logic:
VMI MSG_GEN
Tx Vendor
Messages
Protected by RAS
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# Errors Detectable 1, 2
# Errors Correctable 1
Controller Regenerates ECC Code at Output of RAM When Uncorrectable (2-bit) Error
Detected
a. See Limitations.
b. Using the RASDP_ERROR_PROT_CTRL_OFF register.
c. The controller does not check the address parity. RAM address parity checking and error handling is application specific.
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Controller Checks and Recalculates Protection Codes at all Internal Processing (Data
Manipulation) Stepsb
# Errors Detectable
ECC 1,2
Parity 1
# Errors Correctable
ECC 1
Parity 0c
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8-bit
32-bit
64-bit
a. See Limitations.
b. Detailed report of all check points is available at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/5.40a/doc/RASDP_-
CheckPoints.pdf.
c. The controller pulses app_parity_err[2:0]output bus. Your application can OR the bus bits and drive the Uncorrectable
Error bit of the app_err_bus input. This is not required when RASDP error mode is enabled because the controller handles the
parity error as an uncorrectable error in this mode.
d. Using the RASDP_ERROR_PROT_CTRL_OFF register.
e. Except for 32-bit datapath.
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Error Statisticsb
Limitations
The controller has a set of RAS DP registers as defined in Table 3-18. For detailed descriptions of how you
use them, see the “Registers” chapter (DWC_pcie_ctl_sw_registers.pdf).
Register Description
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Register Description
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Figure 3-27 RAS DP Register Access to Error Counters (Same Method Applies to Uncorrectable Errors)
CORR_CLEAR _COUNTERS
CORR_EN_COUNTERS
CORR_COUNTER_SELECTION [7:0]
Counter j
Software Write
Counter0
RST
EN
Region i
Counter j
error
RASDP_CORR_COUNTER_CONTROL_OFF
CORR_COUNTER_SELECTED [7:0]
Region 0
Counters CORR_COUNTER_SELECTION _REGION [3:0]
Software
. CORR_COUNTER[7:0]
Read
.
. Counter j
RASDP_CORR_COUNT_REPORT_OFF
Counter0
RST
EN
error
Region i
Counters
Upon detection of first Uncorrectable error (RAM and Datapath/Interface Protection), depending on value
of AUTO_LINK_DOWN_EN field of the RASDP_ERROR_MODE_EN_OFF register, the controller takes one of the
two actions:
■ Forces the PCIe link to go down (AUTO_LINK_DOWN_EN =1), or
■ Enters RASDP Error Mode (AUTO_LINK_DOWN_EN =0)
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1. In RASDP error mode, TLPs are not guaranteed to be correct. You must discard all TLPs when this signal is high.
2. The controller might nullify TLPs that are received prior to the bad TLP.
3. The controller might drop TLPs that are received prior to the bad TLP.
4. 2-bit ECC and all parity errors.
5. The controller only reports uncorrectable errors when it exits RASDP error mode.
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The controller takes the following action to handle correctable (RAM and Datapath/Interface Protection)
errors:
■ Correctable1 Error is Logged
■ Correctable Internal Error Reported (AER)
■ TLP is Modified/Corrected
■ Errors Reported When Detected (Immediately)
■ Error Correction Enable/Disable Control (Per TX/RX Direction and Per-Layer)2
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3.6.4.1 Debug
To facilitate system level debugging the controller provides the following features:
■ General Diagnostic Support (Legacy Internal Probe Points).
■ Silicon Debug Support (Control and Status of PIPE, Deskew, Ack/Nak, Reversal, FC, EQ, LTSSM,
Replay)
Output Description
Register Description
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Register Description
In addition, you can also use the non-optional silicon debug outputs in Table 3-22 and registers in Table 3-23
that always exist regardless of parameter settings.
Output
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Output
Register Fields
TX_P_HEADER_FC_CREDIT
TX_P_FC_CREDIT_STATUS_OFF
TX_P_DATA_FC_CREDIT
TX_NP_HEADER_FC_CREDIT
TX_NP_FC_CREDIT_STATUS_OFF
TX_NP_DATA_FC_CREDIT
TX_CPL_HEADER_FC_CREDIT
TX_CPL_FC_CREDIT_STATUS_OFF
TX_CPL_DATA_FC_CREDIT
RX_QUEUE_NON_EMPTY
QUEUE_STATUS_OFF TX_RETRY_BUFFER_NE
RX_TLP_FC_CREDIT_NON_RETURN
PL_DEBUG0_OFF DEB_REG_0
PL_DEBUG1_OFF DEB_REG_1
GEN3_EQ_COEFF_LEGALITY_STATUS_OFF GEN3_EQ_VIOLATE_COEF_RULES
VC0_P_TLP_Q_MODE
VC0_P_RX_Q_CTRL_OFF VC0_P_HEADER_CREDIT
VC0_P_DATA_CREDIT
VC0_NP_TLP_Q_MODE
VC0_NP_RX_Q_CTRL_OFF VC0_NP_HEADER_CREDIT
VC0_NP_DATA_CREDIT
VC0_CPL_TLP_Q_MODE
VC0_CPL_RX_Q_CTRL_OFF VC0_CPL_HEADER_CREDIT
VC0_CPL_DATA_CREDIT
GEN1_EI_INFERENCE
PRE_DET_LANE
GEN2_CTRL_OFF
NUM_OF_LANES
FAST_TRAINING_SEQ
PIPE_LOOPBACK_CONTROL_OFF PIPE_LOOPBACK
REPLAY_TIME_LIMIT
ACK_LATENCY_TIMER_OFF
ROUND_TRIP_LATENCY_TIME_LIMIT
VENDOR_SPEC_DLLP_OFF VENDOR_SPEC_DLLP
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Register Fields
CPL_SENT_COUNT
LINK_STATE
PORT_FORCE_OFF FORCE_EN
FORCED_LTSSM
LINK_NUM
ENTER_ASPM
L1_ENTRANCE_LATENCY
ACK_F_ASPM_CTRL_OFF
L0S_ENTRANCE_LATENCY
ACK_FREQ
TRANSMIT_LANE_REVERSALE_ENABLE
EXTENDED_SYNCH
BEACON_ENABLE
LINK_CAPABLE
LINK_RATE
PORT_LINK_CTRL_OFF FAST_LINK_MODE
LINK_DISABLE
DLL_LINK_EN
RESET_ASSERT
SCRAMBLE_DISABLE
VENDOR_SPECIFIC_DLLP_REQ
LANE_SKEW_OFF DISABLE_LANE_TO_LANE_DESKEW
UPDATE_FREQ_TIMER
TIMER_MOD_ACK_NAK
IMER_CTRL_MAX_FUNC_NUM_OFF
TIMER_MOD_REPLAY_TIMER
MAX_FUNC_NUM
MASK_RADM_1
SYMBOL_TIMER_FILTER_1_OFF DISABLE_FC_WD_TIMER
EIDLE_TIMER
FILTER_MASK_2_OFF MASK_RADM_2
AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_O
OB_RD_SPLIT_BURST_EN
FF
TIMER_MOD_FLOW_CONTROL_EN
QUEUE_STATUS_OFF
TIMER_MOD_FLOW_CONTROL
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Register Fields
USP_SEND_8GT_EQ_TS2_DISABLE
AUTO_EQ_DISABLE
GEN3_DC_BALANCE_DISABLE
GEN3_DLLP_XMT_DELAY_DISABLE
GEN3_EQUALIZATION_DISABLE
GEN3_RELATED_OFF RXEQ_PH01_EN
EQ_REDO
EQ_EIEOS_CNT
EQ_PHASE_2_3
DISABLE_SCRAMBLER_GEN_3
GEN3_ZRXDC_NONCOMPL
GEN3_EQ_LOCAL_FS
GEN3_EQ_LOCAL_FS_LF_OFF
GEN3_EQ_LOCAL_LF
GEN3_EQ_POST_CURSOR_PSET
GEN3_EQ_PSET_COEF_MAP__i
GEN3_EQ_CURSOR_PSET
(for i = 0; i <= 10)
GEN3_EQ_PRE_CURSOR_PSET
GEN3_EQ_PSET_INDEX_OFF GEN3_EQ_PSET_INDEX
GEN3_EQ_PSET_REQ_AS_COEF
GEN3_EQ_FOM_INC_INITIAL_EVAL
GEN3_EQ_PSET_REQ_VEC
GEN3_EQ_CONTROL_OFF
GEN3_EQ_EVAL_2MS_DISABLE
GEN3_EQ_PHASE23_EXIT_MODE
GEN3_EQ_FB_MODE
GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA
GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF
GEN3_EQ_FMDC_N_EVALS
GEN3_EQ_FMDC_T_MIN_PHASE23
You enable this feature with the CX_RAS_DES_EINJ_ENABLE parameter. The controller provides support for
your application to inject the following types of errors:
■ CRC Error
■ Sequence Number Error
■ DLLP Error
■ Symbol DataK Mask Error or Sync Header Error
■ FC Credit Update Error
■ TLP Duplicate/Nullify Error
■ Specific TLP Error
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Your application can use the registers in Table 3-24 to set up error injection. For register descriptions, see
DWC_pcie_ctl_sw_registers.pdf.
Table 3-24 Error Injection Vendor Specific Extended Capability (VSEC) Registers
Register Description
.........other registers (for example, Event Counter, Time-based Analysis, Error Injection) .........
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Register Description
Limitations
You can use the Error Injection6 only when both the conditions are satisfied.
■ The RAS datapath protection (DP) has been disabled (CX_RASDP =0, CX_RASDP_RAM_PROT =0), and
■ The address translation has been disabled (ADDR_TRANSLATION_SUPPORT_EN =0)
3.6.4.3 Statistics
Signal Name
Signal Name
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Table 3-27 Time-based Analysis Vendor Specific Extended Capability (VSEC) Registers
Register Description
aux _clk
app _ras_des _tba_ctrl[1:0] =01 (start)
TIMER_START =1 (start ) app _ras_des _tba_ctrl[1:0] =10 (stop)
0 0
TIMER_START =0 (stop)
Counter
.
.
.
32 Software
Read
Counter
The counters measure, for example, what percentage of time does the controller stay in L0 in a one second
window (configurable through TIME_BASED_DURATION_SELECT field). The measurement range of each
Event in Group#0 is shown in Figure 3-29.
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Measurement
duration
L0 Event
Tx L0s Event
Rx L0s Event
L1 aux Event
L1.1 Event
Config/Recovery
Event
This event counts when both This event counts when current state is L1 and This event counts when current state is L1 and the controller(PMC) is running on aux_clk.
Tx L0s and Rx L0s are active. the controller(PMC) is running on core_clk. It also counts even if the current state is L1.1 or L1.2.
Table 3-28 Time-based Analysis Counter Group #0 (32-bit Low-Power Cycle Counter (RAM)
0x01 Tx L0s -
0x02 Rx L0s -
0x03 L0 -
0x05 L1.1 -
0x06 L1.2 -
0x07 Configuration/Recovery -
Table 3-29 Time-based Analysis Counter Group #1 (32-bit Throughput 4-DWORD Counter)
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Event Counters
You enable this feature with the CX_RAS_DES_EC_ENABLE parameter. Your application can use the outputs
in Table 3-30 and registers in Table 3-32. For register descriptions, see
DWC_pcie_ctl_sw_registers.pdf.
Output Description
This is a common signal bus that provides RAS D.E.S. event counter
cdm_ras_des_ec_info_common
information.
cdm_ras_des_ec_info_i This is Lanei event signal bus that provides RAS D.E.S. event counter
(for i = 0; i <CX_NL)) information.
This signal bus provides RAS D.E.S. Event Counter information for the
cdm_ras_des_ec_ram_*
RAMs.
Register Description
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Group i
Event j
event
Lane k
Event Counter
* Group 0
* Event 0 Software Write
* Lane 0
.
.
EVENT_COUNTER_CONTROL_REG
.
RST
EN
Software
Read
event
Event Counter
* Group i EVENT_COUNTER_DATA_REG
* Event j
* Lane k
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Table 3-33 Event Counter Group #0 (4-bit Layer1 Error Counter Per-Lane)
Table 3-34 Event Counter Group #1 (8-bit Layer1 Error Counter Common-Lane)
0x00 Reserved -
0x01 Reserved -
0x02 Reserved -
0x03 Reserved -
0x04 Reserved -
0x07 Rx Recovery Request When the controller receives TS1 OS in L0s state.
Table 3-35 Event Counter Group #2 (8-bit Layer2 Error Counter Common-Lane)
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Table 3-36 Event Counter Group #3 (8-bit Layer3 Error Counter Common-Lane)
0x00 FC Timeout -
a. Malformed TLP, FC & DL Protocol errors are excluded because of low frequency.
Table 3-37 Event Counter Group #4 (4-bit Layer1 Non-Error Counter Per-Lane)
Table 3-38 Event Counter Group #5 (32-bit Layer1 Non-Error Counter [RAM] Common Lane)
0x05 L1 Entry -
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(CX_L1_SUBSTATES_ENABLE)
0x09 L1 short duration No. of times link entered L1.0 state but exited to L0
without entering L1.1 or L1.2 states
(CX_L1_SUBSTATES_ENABLE)
No. of times link entered L1.2_Entry state but is forced
0x0A L1.2 abort to exit to L1.0 then L0 because it saw clkreq# asserted
while in this state
0x0B L2 Entry -
0x0E Reserved -
Table 3-39 Event Counter Group #6 (32-bit Layer2 Non-Error Counter [RAM])
Table 3-40 Event Counter Group #7 (32-bit Layer3 Non-Error Counter [RAM])
0x04 Tx IO Write -
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0x05 Tx IO Read -
0x09 Tx Atomic -
0x0F Rx IO Write -
0x10 Rx IO Read -
0x14 Rx Atomic -
Limitations
If the controller (PMC) is running on aux_clk during the measurement:
■ The measurement timers (TIME_BASED_DURATION_SELECT: 1 ms, 10 ms, …, 2 s, 4 s) have measure-
ment error less than 4 us.
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■ The measurement timers and event timers of all the events are stopped temporarily when aux_-
clk_active/pm_sel_aux_clk are controlled. Figure 3-31 describes the timing details when aux_-
clk_active/pm_sel_aux_clk are controlled.
No Measurement No Measurement
clk
pm_sel_aux_clk
䞉䞉䞉
aux_clk_active
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3.7 Messages
This section describes the processing of messages through the controller. The following topics are discussed:
■ “Message Generation” on page 153
■ “Message Reception” on page 164
For a proper understanding of messages you should be familiar with Section 2.2.8, “Message Request
Rules” of the PCI Express Base Specification, Revision 4.0, Version 1.0.
■ Messages (Msg/MsgD1) are posted transactions.
■ Vendor Defined and PTM messages are Msg / MsgD.
■ Set Slot Power Limit, Invalidate Request, and LN messages are MsgD.
■ All other messages are Msg.
For more information, see “Interrupts” on page 170.
1. With payload.
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3.7.1.1 Overview
Messages that are transmitted by the controller are derived from the following sources:
■ the controller (automatically)
■ the controller (under the control of your application)
■ your application
■ the host/client software
For internally generated messages, or for messages generated at any of the SII
Note interfaces:
■ ID Based Ordering (IDO) is not supported.
■ The controller does not check the messages for TLP errors; instead it sends the TLP
as presented on the message interfaces.
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iATU
Application Logic :
Transmit XADM
Direct supply of any
4
class of Msg/MsgD
XALI1 TX PIPE
RAM
Application Logic :
Tx Vendor Messages
2 Error Signalling
5 Vendor Defined VMI
Application Logic :
Optional System Status/
Control Registers
Legacy PCI CLK/RST
7 SII: Interrupt Signals MSG_GEN
Interrupt
13 PTM Request
App Error
8
Signalling
SII: Transmit Control Signals
3 LTR Clear
12 DRS/FRS
PMC
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Synopsys Specific
RADM RX PIPE
LBC
CDM Core
Registers
Slot
Capabilities
CXPL Core
PHY
iATU
11 Set_Slot_Power_Limit
Application Logic :
Tx Vendor Messages
5 Vendor Defined VMI
Application Logic :
Optional System Status/
MSG_GEN 13 PTM Response
Control Registers
Locked CLK/RST
6 SII: PM, Unlock, and Error Messages
Transaction
PTM
Power
1
Management
SII: Power Management Signals
For definitions of acronyms used for block and interface names, see “Terms and Descriptions” on page 17.
Message Source
Index (Type) SW (Upstream Port) SW (Downstream Port)
Power Management For more information, see “Power For more information, see “Power
1
interface (Msg) Management” on page 213. Management” on page 213.
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Message Source
Index (Type) SW (Upstream Port) SW (Downstream Port)
COR_ERR / ERR_NONFATAL /
ERR_FATAL.
Error Signaling inside
2 For more information, see NA
the controller (Msg)
“Reliability, Availability, and
Serviceability (RAS)” on page 124.
XALI0/1/2
Direct Supply of any
4 class of message For more information on how to generate a message at the XALI0/1/2
(Msg/MsgD) interface, see “Transmit Client Interface Protocol Rules” on page 279 and
“Application Msg/MsgD Programming Examples” on page 162.
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Message Source
Index (Type) SW (Upstream Port) SW (Downstream Port)
Set_Slot_Power_Limit message,
Set_Slot_Power_Limit triggered by writing to the Slot
11 NA
(MsgD) Capabilities register through the DBI, or
when LTSSM enters L0.
a. MsgD transmission not possible on Vendor Message Interface (VMI). For more information, see “Vendor Defined
Message (VDM) Generation” on page 157. However, it is possible through (4).
VDMs can be generated by your application using any of the following methods:
■ The controller generates VDMs in response to requests on the VMI.
■ The VMI can be used to send Msg only. It does not support message with payload (MsgD).
■ The inputs ven_msg_fmt[1:0]and ven_msg_len[9:0] should be set to 0x1 and 0x0 respectively to
indicate 4-DWORD header and no payload.
■ VDMs created by you at the VMI are always subject to translation by the “Internal Address Transla-
tion Unit (iATU)” on page 178.
You must use 64-bit addressing when you are using the Direct supply method of VDM
Caution generation. For more information, see Figure 3-37 .
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You can enable LTR message generation by setting CX_LTR_M_ENABLE =1. You can generate LTR messages
using any of the following methods:
■ The controller generates LTR messages in response to requests made by your application logic on the
SII input see app_ltr_msg_req.
■ Direct supply of Msg TLPs at XALI0/1/2 .
■ Direct supply of I/O and MEM TLPs at XALI0/1/2 to be converted to LTR messages. The iATU can
convert I/O and MEM TLPs to Msg TLPs. For more information, see “IO/MEM to Msg/MsgD Type
Translation” on page 185.
When the LTR is changing fast and dynamically with the data stream, the LTR message should be
synchronized with the data stream and transmitted over the cores XALI0/1/2 interfaces . For applications
where the LTR is changing slowly or is static, then you can transmit the LTR message over the SII message
interface. In that case, it is assumed that the LTR message is guided by software and the SII message
interface is externally stimulated by software (by writing to a memory mapped application register whose
outputs are driving the SII inputs). When you are using the SII interface you should drive the contents of the
LTR message header on the app_ltr_msg_latency[31:0] input. It has the same format as LTR messages
described in the PCIe specification.
The actual values in the LTR message transmitted by this upstream port are captured in the port logic LTR
Latency Register (PL_LTR_LATENCY_OFF). They are also reflected on the app_ltr_latency[31:0]output.
The values in the LTR Max Snoop and No-Snoop Latency register (LTR_LATENCY_REG) are reflected on the
cfg_ltr_max_latency output.
LTR Msg
transmitted
SII or XALI0/1/2 to
XADM
TX wire
Device
cfg_ltr_m_en
Control 2
Registers
cfg_ltr_max_latency[31:0] LTR
Capability
(platform configured
max latency)
Registers
app_ltr_latency[31:0]
( reported latency)
The controller automatically generates a new LTR message with the Requirement bits set to 0 for both
Snoop and No-Snoop latencies when:
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■ A function is directed to a non-D0 state through a write to the Power State field of the Power Manage-
ment Control and Status register, and the LTR mechanism is active since the last DL_Down to DL_Up
transition.
or
■ The LTR mechanism is disabled by clearing the LTR Mechanism Enable field of the Device Control 2
register. This field is cleared through a CFG write or a function level reset (FLR).
■ By setting DISABLE_AUTO_LTR_CLR_MSG field of the MISC_CONTROL_1_OFF register to 1, the auto-
matic generation of the LTR clear message in the above situations can be disabled.
You must not send an LTR message when the LTR Mechanism Enable bit of the Device Control 2 Register is
0. When this bit is 0, the controller does not block transmission of LTR messages that you generate. The
value of the LTR Mechanism Enable bit is reflected on the cfg_ltr_m_en output.
You can enable OBFF message generation by setting CX_OBFF_SUPPORT. You can generate OBFF messages
using any of the following methods:
■ The controller generates OBFF messages in response to requests made by your application logic on the
SII app_obff_*_msg_req inputs.
■ Direct supply of Msg TLPs at XALI0/1/2 .
■ Direct supply of I/O and MEM TLPs at XALI0/1/2 to be converted to OBFF messages. The optional
iATU) can convert I/O and MEM TLPs to Msg TLPs. For more information, see “MEM or I/O Match
Modes” on page 224.
You must not send an OBFF message when the OBFF Enable field of the Device Control 2 Register
(DEVICE_CONTROL2_DEVICE_STATUS2_REG) is 00. When this field is 00, the controller does not block
transmission of OBFF messages that you generate. The value of the OBFF Enable field is reflected on the
cfg_obff_en[1:0] output.
When you configure the controller to support either variation (A or B) of OBFF messages (through the OBFF
Enable field of the Device Control 2 Register (DEVICE_CONTROL2_DEVICE_STATUS2_REG), and your
application sends an OBFF message when the controller is in the L0s or L1 TX states, then the controller
transitions to the L0 state and transmits the message. According to the PCI Express Base Specification, Revision
4.0, Version 1.0, the controller should drop a Variation A message in this scenario. Therefore, your
application must not send Variation A OBFF messages when the controller is in the L0s or L1 TX states.
Your application must monitor the pm_linkst_in_l0s, pm_linkst_in_l1sub, and pm_linkst_in_l1
outputs. For the purpose of controller optimization the controller does not do this check; your application
must do the check.
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An optional example WAKE Signal Encoder design, that you can integrate into your application logic, is
provided at <workspace>/src/customer/generic/obff_wake_ref*. It translates OBFF requests (from
the same source that is driving the controller inputs app_obff_obff_msg_req,
app_obff_cpu_active_req, and app_obff_idle_msg_req) to WAKE# patterns
Note You must verify the integration of the example encoder/decoder in your design.
PCIe Core
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WAKE# from downstream function to wake up main power and PCIe reference clock
owrd_wake_idle
owrd_wake_obff '1'
`RC
owrd_wake_cpu_act Decoder wake_rx
owrd_wake_err (obff_wake_ref_dec) IN
IN pullup
`EP
owrd_cur_state
device_type
(tristate_buffer)
app_owre_idle
'0' OUT
app_owre_obff Encoder owre_wake
oe
Application `RC IO
app_owre_cpu_act Encoder
(obff_wake_ref_enc) wake_tx
owre_grant OUT_EN
`EP
owre_cur_state
PCIe DM Core
(RC Mode) wake#
PMC I/O PAD for WAKE#
(u_pm_ctrl )
device_type
DM in RC Mode
DM in EP Mode
WAKE# from downstream function to wake up main power and PCIe reference clock
owrd_wake_idle
owrd_wake_obff '1'
`RC
owrd_wake_cpu_act wake_rx
Decoder
owrd_wake_err (obff_wake_ref_dec)
`EP IN
IN
owrd_cur_state
device_type
(tristate_buffer)
app_owre_idle
'0' OUT
app_owre_obff oe
Application `RC
`RC IO
app_owre_cpu_act Encoder wake_tx
owre_grant (obff_wake_ref_enc) OUT_EN
`EP
`EP
owre_cur_state
PCIe DM Core
(EP Mode) wake#
PMC I/O PAD for WAKE#
(u_pm_ctrl )
device_type
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The following tables enumerate the different ways that your application can generate Msg and MsgD TLPs.
Applicatio
n Interface Description Application I/O Signals
client1_tlp_type =MSG
client1_tlp_fmt[1:0] =01
client1_tlp_byte_len =0
Direct Supply using a Msg transaction.
client1_tlp_byte_en =message Code
client1_tlp_addr[31:0] =header bytes 12-15
client1_tlp_addr[63:32] =header bytes 8-11
XALI0/1/2
Indirect Supply (iATU) using an MWra transaction.
The iATU needs to be configured to translate MWr client1_tlp_type =MSG
to Msg TLPs.
client1_tlp_byte_len =0
A MWr with an “effective length of 0” is converted
client1_tlp_byte_en =00000000
to Msg and all other MWr TLPs are converted to
MsgD.
The controller generates Vendor Defined messages in response to requests on the VMI. For
VMI
more information, see “Vendor Message Interface (VMI)” on page 305.
Application
Interface Description Application I/O Signals
client1_tlp_type =MSG
client1_tlp_fmt[1:0] =11
client1_tlp_byte_len !=0
Direct Supply using a Msg transaction.
client1_tlp_byte_en =message Code
client1_tlp_addr[31:0] =header bytes 12-15
XALI0/1/2
client1_tlp_addr[63:32] =header bytes 8-11
3.7.1.7 Byte Mapping of Third and Fourth Message Header Dwords At I/O Interfaces
Figure 3-37 indicates the byte mapping between the message generation interfaces and the third and fourth
DWORDs of the message TLP header. For more information, see:
■ Descriptions of client0_tlp_addr and client0_tlp_data at “Transmit Interfaces (XALI0/1/2)” on
page 279.
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Figure 3-37 Transmitted 3rd and 4th DWORD Message Header Byte Mapping at Interfaces
SII.MESSAGE 31 bytes 12-15
(app _msg_*) 0
0
63 bytes 8-11
VMI
(ven_msg_data) 32
31 bytes 12-15
0
P
XALI0/1/2 Core I
Logic P
63 E
1
32 bytes 8-11
31
0
0
0x0 0
bytes 12-15
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3.7.2.1 Overview
The PCI Express controller can receive the following types of messages. The index in the first column refers
to the circled numbers in the following diagrams.
Message Source
Index (Type) SW (Upstream Port) SW (Downstream Port)
Power Management For more information, see “Power For more information, see “Power
1
(Msg). Management” on page 213. Management” on page 213.
Vendor Defined
3 For more information, see “Routing of Received Messages” on page 166.
(Msg/MsgD).
Locked Transaction
4 Unlock message NA
(Msg).
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Message Source
Index (Type) SW (Upstream Port) SW (Downstream Port)
Synopsys Specific
TRGT1 RADM RX PIPE
4
Locked PTM
Transaction
Slot Power
1a
Limit
Power
1
Management CLK/RST
Synopsys Specific
TRGT1 RADM RX PIPE
Legacy PCI
5
Interrupt
Power
1
Management CLK/RST
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For definitions of acronyms used for block and interface names, see “Terms and Abbreviations” on page 17.
The RADM filter provides a message interface that is grouped as part of the System Information Interface
(SII)to handle the message TLPs received from the upstream component. The RADM filter processes the
message and decodes the header before sending it to your application logic on the SII. Some of the message
reception signals are also used in “Interrupts” on page 170 and “Reliability, Availability, and Serviceability
(RAS)” on page 124.
All1 error-free MSG requests are decoded internally, signaled on the SII interface, and then dropped (not
forwarded to your application2 on TRGT1. When a MSG request is filtered with UR/CA/CRS status, the
TLP is always dropped.
a. Except PTM
b. The exception to this is an ATS Invalidation Request which is too big and is delivered on the TRGT1 interface regard-
less of filter mask settings
You can enable LTR message reception by setting CX_LTR_M_ENABLE. When the controller receives an LTR
message, it pulses the radm_msg_ltr output. You can access the LTR message information on the
radm_msg_payload output, which is part of the SII message interface. The actual values in the LTR message
received by this downstream port are captured in the port logic LTR Latency Register
(PL_LTR_LATENCY_OFF). They are also reflected on the app_ltr_latency[31:0]output.
1. Except PTM .
2. Vendor TYPE0 messages generate an UR error.
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LTR Port
Logic
Registers
LTR Msg
received
from RX
RADM
wire
app_ltr_latency[31:0]
(reported latency)
When you configure the controller with a 256-bit datapath, and when two LTR messages are received in the
same clock cycle (back-to-back), the earlier message is discarded.
■ It is preferable to use the SII interface to receive LTR messages. The bridge master
Note cannot support reception of LTR messages.
You can enable OBFF message reception by setting CX_OBFF_SUPPORT. When you configure the controller
with a 256-bit datapath, and when two OBFF messages are received in the same clock cycle (back-to-back),
the earlier message is discarded. When you have not enabled OBFF in the Device Control 2 register, or when
the Traffic Class is non-zero; then the controller generates an UR completion when it receives an OBFF
message. When the upstream port receives an OBFF message, it pulses one of the radm_msg_obff,
radm_msg_cpu_active, or radm_msg_idle outputs. Your application logic must use these outputs to
control the traffic it generates. For more information, see PCI Express Base Specification, Revision 4.0, Version
1.0.
■ It is preferable to use the SII interface to receive OBFF messages. The bridge master
Note cannot support reception of OBFF messages.
An optional WAKE Signal Decoder example design, that you can integrate into your application logic, is
provided at workspace/src/customer/generic/obff_wake_ref*. It translates WAKE# patterns to the
corresponding OBFF codes. When it receives a reserved OBFF code, it decodes it as a CPU_ACTIVE event.
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app_init Error reset: one cycle pulse to reset the decoder into the state specified
by app _idle, app _obff, or app_cpu_act.
app_idle
Used when your application detects (one cycle pulse on
app_obff owrd_wake_err) that the decoder has received an invalid WAKE #
pattern (for example, a valid inactive pulse after a valid active pulse
app_cpu_act drives the OBFF code from IDLE to CPU _ACT, but the falling -to-falling
width is smaller than the minimum falling edge -to-falling edge width ).
owrd_wake_idle Waveform
1-cycle pulse
owrd_wake_obff Decoder
indicating type
of WAKE #
pattern received owrd_wake_cpu_act wake IN
pullup
owrd_wake_err
Current FSM
(tristate buffer)
state for debug .
owrd_cur_state
'0' OUT
Not equal to
oe WAKE#
OBFF code .
cfg_wk_max_pls_wdt IO
cfg_wk_min_pls_wdt OUT_EN
Determine pulse
cfg_wk_max_f2f_wdt width and edge -to-
edge timing .
cfg_wk_min_f2f_wdt I/O PAD
PCIe Core
wake
(active high )
Note You must fully verify the integration of the example encoder/decoder in your testbench.
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■ For specific information on how the handling of a message is affected by its error status, see
“Advanced Information: Advanced Error Handling for Received TLPs” on page 981 and“Advanced
Information: Advanced Filtering and Routing of TLPs” on page 954.
■ For more information on optional address translation of VDMs, see “MSG/MSGD Match Mode” on
page 195.
■ For more information on ordering considerations, see “Advanced Information: Advanced Ordering
Information” on page 968.
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3.8 Interrupts
The following section describes the processing of interrupts in the controller. You should be familiar with
the different types of interrupts as specified in Sections 6.1.1, “Rationale for PCI Express Interrupt Model”,
6.1.4, “Message Signaled Interrupt (MSI/MSI-X) Support”, 6.1.2, “PCI Compatible INTx Emulation”, and
6.1.3, “INTx Emulation Software Model” of the PCI Express Base Specification, Revision 4.0, Version 1.0.
■ “Interrupt Generation (USP)” on page 171
■ “Interrupt Reception (DSP)” on page 175
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3.8.1.1 Overview
An USP creates MSI’s using MWr requests. Your application logic issues MSI requests through the MSI
interface; the controller then generates the corresponding memory write. Alternatively, your application
logic can create the MSI MWr and supply it on a XALI0/1/2 Tx interface .
cfg_msi_pending[31:0]
cfg_msi_addr[63:0]
cfg_msi_data[15:0]
cfg_msi_mask[31:0]
cfg_msi_mask[31:0]
ven_msi_vector[4:0]
ven_msi_grant
ven_msi_req
cfg_msi_en
cfg_msi_en
Your
Your
Application
Application
Logic
Logic
3 3
MSI FSM MSI FSM
5 5
4 4
Clear Clear
Pending Pending
Bit Bit
An MSI-X interrupt is identical to an MSI, except that it: supports more than 32 vectors (2048) through the
use of multiple address and data pairs that are written by software to an MSI-X Table. Your application
logic issues MSI requests through the MSI interface; the controller then generates the corresponding
memory write. Alternatively, your application logic can create the MSI MWr and supply it on a XALI0/1/2
Tx interface .
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Figure 3-43 Example MSI-X Application Logic Using SII MSI Interface (MSIX_CAP_ENABLE =1)
Traffic Arbiter
Normal Traffic PCIe
Lo core
A
MWr D
Tx
Message Generator Hi
cfg_msix_table_of fset[28:0]
cfg_msix_table_bir[2:0]
cfg_bar5_start/limit[31:0]
cfg_bar4_start/limit[63:0]
cfg_bar3_start/limit[31:0]
cfg_bar2_start/limit[63:0]
cfg_bar1_start/limit[31:0]
cfg_bar0_start/limit[63:0]
cfg_bar0_start/limit[63:0]
cfg_bar1_start/limit[31:0]
cfg_bar2_start/limit[63:0]
cfg_bar3_start/limit[31:0]
cfg_bar4_start/limit[63:0]
cfg_bar5_start/limit[31:0]
cf g_msix_en =1
cfg_msix_func_mask =0
msix_addr[ 63:0]
msix_data[31:0]
cfg_msix_pba_bir[2:0]
cfg_msix_pba_offset[28:0]
N = cfg_msix_table_size[]
ven_msi_req
3
MSI-X FSM
+ +
5
Address Address
Priority Encoder 3 Decoder Decoder
D,A
rdata raddr r/ waddr
MSI-X Table Host Read
PBA Access
(N)
r/ wdata
Clear
Pending mask
Bit 1 Host Write
Set/ clear pending Access
bit control
2
N
Example for single -function non -VF.
Local Interrupt Lines Your Application Logic
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Traffic Ar bi ter
Normal Traffic
PCIe
Lo core
A Tx
MWr D
Hi
XALI0/1/ 2 or
AXI
Slave Interface
PCI Header BARS
MSI-X Capability 1 BAR5
Capability/Control BAR4
Table Of fset BI R BAR3
PBA Of fset BI R BAR2
BAR1
BAR0
cfg_msix_table_bir[2:0]
cfg_msix_table_off set[ 28: 0]
cfg_bar5_start/limit [31:0]
cfg_bar4_start/limit [63:0]
cfg_bar3_start/limit [31:0]
cfg_bar2_start/limit [63:0]
cfg_bar1_start/limit [31:0]
cfg_bar0_start/limit [63:0]
cfg_msix_func_mask =0
cfg_bar0_start/limit [63:0]
cfg_bar1_start/limit [31:0]
cfg_bar2_start/limit [63:0]
cfg_bar3_start/limit [31:0]
cfg_bar4_start/limit [63:0]
cfg_bar5_start/limit [31:0]
cfg_msix_en =1
cfg_msix_pba_bir[2:0]
3
MSI-X FSM
+ +
5
2
N
Example for single-function non-VF.
Local Interrupt Lines Your Application Logic
MSI/MSI-X requests created at the MSI interface are given higher Tx priority than traffic at the
Note
XALI0/1/2 transmit interfaces . To preserve ordering, you should supply MSI/MSI-X MWr
requests at the XALI0/1/2 transmit interfaces .
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S W DS P S W US P
Msg
A ss ert_ INTx /
Deass ert_ INTx
s ys_int *
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3.8.2.1 Overview
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radm_bypass_tlp_abort
Asserted Credit needs to be returned
radm_trgt1_tlp_abort
radm_bypass_dllp_abort
Asserted Credit need not be returned
radm_trgt1_dllp_abort
For more information, see “System Information Interface (SII)” on page 306 and “Advanced Information:
Advanced Error Handling for Received TLPs” on page 981. The controller does not return flow control
credits for packets that have data link layer errors.
You can override the default flow control update latency timer value using the FC Latency
Note
Timer Override Value field (TIMER_MOD_FLOW_CONTROL) in the Queue Status register
(Q_STATUS).
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The default behavior of the ATU when there is no address match in the outbound direction or
Note
no TLP attribute match in the inbound direction, is to pass the transaction through.
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Figure 3-46 64-bit Region Mapping: Outbound and Inbound (Address Match Mode); INCREASE_REGION_SIZE=0
Region Size =
Untranslated Translated
End Address – Start Address
Upper Base Address Limit Address Address Map Address Map
31 0 31
* 0
0xFFFF
63 0 Region #n
End Address
Region #n
63 0
0x0000
Start Address 31 0 31
* 0
0x0000
31 0 31
* 0
Note: * is log2(CX_ATU_MIN_REGION_SIZE)
1. When the Region Enable bit of the Region Control 2 register is ‘0’, then that region is not used for address matching.
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PCI Express SW Controller Databook Outbound Basic Operation (Address Match Mode)
Figure 3-47 64-bit Region Mapping: Outbound and Inbound (Address Match Mode); INCREASE_REGION_SIZE=1
Upper Upper Region Size =
Base Limit Untranslated Translated
End Address – Start Address
Address Address Limit Address Address Map Address Map
#
31 0 31
* 0
0xFFFF
63 0 Region #n
End Address
Region #n
63 0
0x0000
Start Address 31 0 31
* 0
0x0000
31
Upper Base Address
0 31
*
Lower Base Address
0
Note: * is log2(CX_ATU_MIN_REGION_SIZE)
The combination of region size and number of regions must not consume the maximum space
Caution
that is addressable with your 32-bit or 64-bit system address.
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Figure 3-48 32-bit Region Mapping: Outbound and Inbound (Address Match Mode)
Region Size =
Untranslated Translated
End Address – Start Address
Limit Address Address Map Address Map
31
* 0
0xFFFF
31 0 Region #n
End Address The resulting translated address space can
be 64-bits or 32-bits.
Region #n
63 0
0x0000
Start Address 31 0 31
* 0
0x0000
31
* 0
Note: * is log2(CX_ATU_MIN_REGION_SIZE)
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Overview: When there is a successful address match on an outbound TLP, then the function number used
in generating the function part of the requester ID1 field of the TLP is taken from the 3-bit Function Number
field of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i register. To override this behavior, use the “Function
Number Translation Bypass” on page 186.
Overview: The iATU supports TYPE translation/conversion of MEM and I/O TLPs to Msg/MsgD TLPs.
When there is a successful address match on an outbound MEM TLP, and the translated TLP type field is
MSG (that is, the type field of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i register is 10xxx), then the
message code field of the TLP is set to the value in the Message Code field of the
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register. A MWr with an effective length of ‘0’ is converted to
Msg and all other MWr TLPs are converted to MsgD. For more information on generating messages, see
“Message Generation” on page 153
Usage Scenario: This is useful for applications that are unable to generate Msg/MsgD TLPs.
Overview: The iATU automatically sets the TLP format field for three DWORDs when it detects all zeros in
the upper 32 bits of the translated address. Otherwise, it sets it to four DWORDs when it detects a 64-bit
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address (that is, when there is a ‘1’ in the upper 32 bits of the translated address). When the original address
and the translated address are of different format, the iATU ensures that the TLP header size matches the
translated address format.
Overview: When there is a successful address match for an outbound write and the type header field in the
IATU_REGION_CTRL_1_OFF_OUTBOUND_i register is “00001” indicating a locked MEM transfer, then the
controller sets the type field to “0000” (MEM).
Overview: When there is no address match then the address is untranslated but the TLP header information
(for fields that are programmable) comes from the relevant fields on the application transmit interface
XALI* or .
Overview: In normal operation an address match on an outbound TLP occurs when the untranslated
address is in the region bounded by the base address and limit address. When the invert feature is enabled,
an address match occurs when the untranslated address is not in the region bounded by the base address
and limit address.
Feature Configuration: To enable Invert feature, set the INVERT_MODE field of the
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to ‘1’.
Overview: When you set client0_tlp_iatu_bypass, the iATU does not process that transaction.
Overview: When function number translation bypass is enabled and region address is matched, the
function number of the translated TLP is taken from your application transmit interface and not from the
Function Number field of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i register .
Usage Scenario: This is useful for AXI-based SR-IOV applications where the upper bits of the AXI ID are
used to identify the source (PF or VF) of a request. These upper bits of the ID can be mapped to the function
number of the slave request PF/VF misc_info buses of the controller. There is then no need for the iATU to
translate the PF and VF information.
Feature Configuration: To enable function number translation bypass, set the FUNC_BYPASS field of the
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to ‘1’.
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Overview: When TLP header field bypass is enabled and region address is matched, header fields of the
translated TLP are taken from your application transmit interface or, if AMBA is configured, from the
AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the
IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The
header fields are TC, AT, PH, TH, ST and Attr (IDO, RO and NS) fields.
Feature Configuration: To enable TLP header field bypass, set the TLP_HEADER_FIELDS_BYPASS field of
the IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to '1'.
Overview: When payload inhibit is enabled and region address is matched, the iATU converts transactions
with data payload to TLPs without payload data by forcing the TLP header Fmt[1] bit =0, regardless of the
application inputs .
Note: This feature is not supported for MemWr/IOWr with data payload greater than 1DW.
This feature must not be used for outbound transactions with data poisoning, because the EP
Caution bit is set for TLPs without data payload, this is a violation of data poisoning rules defined in
section “2.7.2.2. Rules For Use of Data Poisoning” of the PCI Express Base Specification,
Revision 4.0, Version 1.0.
Usage Scenario: This is useful for Vendor Defined Msg (without data); your application sends a MWr but
does not set the byte write enables to 0.
Feature Configuration: To enable payload inhibit, set the INHIBIT_PAYLOAD field of
IATU_REGION_CTRL_2_OFF_OUTBOUND_i to ‘1’.
Overview: When header substitution is enabled and region address is matched, the iATU fully substitutes
bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with
the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i.
Note: For a Vendor Defined Msg/MsgD having 4 DWORD header, when HEADER_SUBSTITUTE_EN =1, the
4th DWORD (bytes 12-15) is replaced with the contents of LWR_TARGET_RW field in the
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register. But regardless of the value of
HEADER_SUBSTITUTE_EN, the 3rd DWORD is replaced with the contents of UPPER_TARGET_RW field in the
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_i register. So for a Vendor Defined Msg, BDF (or reserved)
and Vendor ID must be programmed in UPPER_TARGET_RW.
Usage Scenario: This is useful for Vendor Defined Msg/MsgD and ATS transactions which is normally
inefficient requiring a very large iATU region.
Feature Configuration: To enable header substitution, set the HEADER_SUBSTITUTE_EN field in
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to ‘1’.
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Overview: When tag substitution is enabled and region address is matched, the iATU substitutes the TAG
field of the outbound TLP header with the contents of the TAG field in
IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_TPH_ENABLE =1): TAG substitution for MWr does not occur because this field (byte 6) in the TLP
header is the ST field. ST substitution can still take place using the MSG_CODE field in
IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Your application must not attempt to perform TAG substitution for outgoing non-posted TLPs.
Usage Scenario:
Feature Configuration: To enable tag substitution, set the TAG_SUBSTITUTE_EN field of the
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to ‘1’.
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You can access the iATU registers through the DBI interface or through BAR Matched Mem/IO requests.
The following registers are used for programming the iATU.
Table 3-51 Example: Address Table for Accessing iATU Outbound Region 1 Configuration Registers
Register Bit Value
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For releases previous to 4.80a, the iATU registers have been programmed through an indirect
Attention addressing scheme using an index register (iATU_VIEWPORT_OFF), to reduce the address
footprint in the PCI Express extended configuration space. To use the legacy method of
accessing iATU registers, contact Synopsys support through SolvNet.
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PCI Express SW Controller Databook Inbound Features
The default behavior of the ATU when there is no address match in the outbound direction or
Note
no TLP attribute match in the inbound direction, is to pass the transaction through.
1. If DEFAULT_TARGET =1, UR/CA TLPs which are BAR matched for an ATU region are forwarded to the TRGT1 interface
and translated.
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3.10.9.1 Overview
The main difference between inbound and outbound iATU operation is that the TLP type is
Note
never changed in the inbound direction. Instead, the type field is used for more precise
matching. Other fields can also be optionally used to further refine the matching process.
Another difference is that for MEM and I/O TLPs, you can select between address matching
(as used in outbound operation) or BAR matching. Normally, an endpoint uses BAR match
mode, and a root complex uses address mode as an root complex normally does not
implement BARs.
Address Match Mode: The operation is similar to “Outbound Basic Operation (Address Match Mode)” on
page 182. The address field of each request TLP is checked to see if it falls into any of the enabled1 address
regions as shown in Figure 3-50. When an address match is found then the TLP address field is modified as
follows:
Address = Address - Base Address + Target Address
1. When the Region Enable bit of the Region Control 2 register is 0, then that region is not used for address matching.
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When the TLP address field matches more than one of the CX_ATU_NUM_INBOUND_REGIONS address
regions, then the first (lowest of the numbers from 0 to CX_ATU_NUM_INBOUND_REGIONS - 1)enabled region
to be matched is used.
BAR Match Mode
Looking for an address match is a two-step process.
1. The standard internal PCI Express BAR Matching mechanism checks if the address field of any MEM
and I/O request TLP falls into any address region defined by the enabled BAR addresses and masks.
2. When a matched BAR is found, then the iATU compares the BAR ID to the BAR Number (BAR_NUM)
field in the IATU_REGION_CTRL_2_OFF_INBOUND_i register for all enabled regions. Figure 3-49 and
Figure 3-50 on page 195 provide more information on inbound translation in BAR Match Mode.
When the PCIe controller is operating with 64-bit BARs, the operation is defined as in Figure 3-49 where * is
log2(BAR_MASK+1).
Figure 3-49 iATU Address Region Mapping: Inbound (BAR Match Mode), 64-bit BAR
Region Size = set by the BAR Mask
of the matched-BAR.
Untranslated Translated
Address Map Address Map
x = Matched-BAR number
Region #x
The resulting translated address space can
be 64-bits or 32-bits.
Region #x
63 0
0x0000
Start Address 31
63 0
eATU Region#x Register eATU Region#x Register
63 0
BAR#x
In address match mode, when the address range does not match one of its BAR ranges in an upstream port,
then the device rejects the request with unsupported request (UR) completion status and no translation
occurs. When the PCIe controller is operating with 32-bit BARs, the operation is defined as in Figure 3-50.
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Figure 3-50 iATU Address Region Mapping: Inbound (BAR Match Mode), 32-bit BAR
Region Size = set by the BAR Mask
of the matched-BAR.
Untranslated Translated
Address Map Address Map
x = Matched-BAR number
Region #x
The resulting translated address space can
be 64-bits or 32-bits.
Region #x
63 0
0x0000
Start Address 31
Upper Target Address
0 31
*
Lower Target Address
0
31 0
eATU Region#x Register eATU Region#x Register
31
* 0
The controller normally routes CFG TLPs (to the internal CDM or ELBI) without translation. The iATU only
translates CFG0 TLPs that the controller has routed to the TRGT1.
Accept Mode
In Accept Mode, the controller always accepts CFG0 TLPs even when the CFG bus number does not match
the current bus number of the device. The routing ID of received CFG0 TLPs are ignored when determining
a match.
Routing ID Match Mode
The operation is similar to “Outbound Basic Operation (Address Match Mode)” on page 182. The routing ID
of the inbound CFG0 TLP must fall within the Base and Limit of the defined iATU region for matching to
proceed. The iATU interprets the routing ID (Bytes1 8-11 of TLP header) as an address. This corresponds to
the upper 16 bits of the address in MEM and I/O transactions.
1. For more information, see Figure 2-18 Request Header Format for Configuration Transactions in Section 2.2.7 Memory, I/O,
and Configuration Request Rules of the PCI Express Base Specification, Revision 4.0, Version 1.0.
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For more information on generating messages, see “Message Generation” on page 153.
Hint
For a proper understanding of messages, you should be familiar with Section 2.2.8, Message
Request Rules of the PCI Express Base Specification, Revision 4.0, Version 1.0.
1. In Figure 2-25 Header for Vendor_Defined Messages in Section 2.2.8.6, Vendor_Defined Message of the PCI Express Base
Specification, Revision 4.0, Version 1.0.
2. In Figure 2-25 Header for Vendor_Defined Messages in Section 2.2.8.6, Vendor_Defined Message of the PCI Express Base
Specification, Revision 4.0, Version 1.0.
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The iATU automatically sets the TLP format field for three DWORDs when it detects all zeroed in the upper
32 bits of the translated address. Otherwise it sets it to four DWORDs when it detects a 64-bit address (when
there is a 1 in the upper 32 bits of the translated address). When the original address and the translated
address are of a different format then the iATU ensures that the TLP header size matches the translated
address format.
Overview: In address and BAR match modes, a successful address/BAR match can be optionally gated by
successful matching of the programmable TLP header fields (per region) mentioned in Table 3-53. When the
associated Match Enable bit is set, the TLP header field of an inbound TLP is matched to the programmed
TLP header field value.
Feature Configuration: Table 3-53 provides information on the registers to consider for TLP header field
matching.
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TLP
Header
Field Field Register Field Register
TC TC_MATCH_EN TC
TD TD_MATCH_EN TD
AT AT_MATCH_EN IATU_REGION_CTRL_ AT
2_OFF_INBOUND_i
PH PH_MATCH_EN PH
MSG_CODE_MATC
ST MSG_CODE
H_EN IATU_REGION_CTRL_
Message MSG_CODE_MATC 2_OFF_INBOUND_i
MSG_CODE
Code H_EN
Note Address translation only proceeds when compares on all enabled field are successful.
Overview: Single address location feature has two modes of operation, fixed and circular buffer.
Fixed: When enabled and region address matches, the TLPs translates to a single address location as
determined by the target address register of the iATU region.
Received Message TLP Header Bytes 8 - 15 at TRGT1 Interface
Bytes 8 to 15 of the received TLPs header destined for TRGT1 are made available on radm_trgt1_
hdr_uppr_bytes irrespective of TLP translation. When radm_trgt1_hdr_uppr_bytes_valid is asserted
your application should use radm_trgt1_hdr_uppr_bytes along with radm_trgt1_data.The
radm_trgt1_hdr_uppr_bytes_valid is set only when an ATU match occurs for Single Address Location
enabled region.
For example, if a received MsgD matches a Single Address Location enabled ATU region, bytes 8 to 15 of the
MsgD header are available on radm_trgt1_hdr_uppr_bytes when
radm_trgt1_hdr_uppr_bytes_valid is asserted, and radm_trgt1_hv is true. The available
radm_trgt1_hdr_uppr_bytes can be concatenated with radm_trgt1_data and used by your
application.
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Circular Buffer: In this mode, the first TLP translates to a single address location as determined by the
target address register of the iATU region. But, for subsequent TLPs, the target address increments by a
programmable increment size (CBUF_INCR), each time a region address matches. You can program the
increment size using CBUF_INCR field of the IATU_LIMIT_ADDR_OFF_INBOUND_i register (the maximum
increment size is 8192; this incorporates the maximum VDM data payload of 4096 and 2 DWs of header
radm_trgt1_hdr_uppr_bytes). On reaching the circular buffer window size, the target address wraps
around, and resets to single location base address. The controller uses the output signal
radm_trgt1_atu_cbuf_err to notify your application if the region matched received VDM size is greater
than the programmed circular buffer increment size (CBUF_INCR).
0xFFFF
When target address =
Translated
63 0 Single Location Base Address +
Address Map 4 Circular Buffer Window Size,
End Address
target address is wrapped around to Single Location
Circular Buffer Base Address
Window
Third translation to Single Location Base Address +
3
2 * CBUF_INCR (and so on ...)
Circular Buffer Window Size =
End Address – Single Location Base Address 2 Second translation to Single Location Base Address
+ CBUF_INCR
63 0
0x0000
31 0 31
* 0
* = log2(CX_ATU_MIN_REGION_SIZE)
The controller output port radm_trgt1_atu_sloc_match can be used as IRQs for any
Note VDM received which is processed in the iATU using the circular buffer feature.
Usage Scenario: The main usage scenario is translation of Messages (such as Vendor Defined or ATS
Messages) to MWr TLPs when the AXI bridge is enabled.
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Feature Configuration: To enable single address location feature, set the SINGLE_ADDR_LOC_TRANS_EN
field of the IATU_REGION_CTRL_2_OFF_INBOUND_i register to ‘1’. Table 3-54 describes additional
configuration settings for choosing the single address location operation mode.
Steps to Program ATU Circular Buffer Registers
1. Write to Upper Target Address, Lower Target Address, and Limit Address (all inbound) registers for
start and end address values of Circular Buffer window for the ATU region.
2. Set SINGLE_ADDR_LOC_TRANS_EN =1 to enable single location address.
3. Write the desired increment value to the CBUF_INCR field of the IATU_LIMIT_ADDR_OFF_INBOUND_i
register. This enables the circular buffer feature.
IATU_LIMIT_ADDR_OFF_INBOUND_i.
CBUF_INCR >0
IATU_LIMIT_ADDR_OFF_INBOUND_i. IATU_REGION_CTRL_2_OFF_INBOUND_i.
CBUF_INCR =0 SINGLE_ADDR_LOC_TRANS_EN =1
CX_ATU_SLOC_CBUF =1(default)
CX_ATU_MAX_REGION_SIZE =0
Overview: Inbound CFG transactions routed to the Rx application interface can exist anywhere in address
space, because the PCIe controller filter processes the routing ID (BDF) as bits [31:16] of an address. This
BDF changes according on the PCIe bus topology. Bits [15:12] of the third DWORD1 of CFG TLPs are
reserved. The CFG shift feature uses this fact to reduce the memory requirement. The CFG shift feature
shifts/maps the BDF (bits [31:16] of the third header DWORD, which would be matched against the Base
and Limit addresses) of the incoming CfgRd0/CfgWr0 down to bits[27:12] of the translated address.
CFG1 Transactions
For CfgRd1/CfgWr1 transactions, the base and limit addresses could enclose the entire 32-bit 4 GB memory
space with the routing ID forming the upper 16 bits. The target address maps these CFG transactions to
anywhere in application address space.
Usage Scenario: This is useful for CFG transactions where the PCIe configuration mechanism maps bits
[27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be
located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits
[31:16] of the untranslated address to form bits [27:12] of the translated address.
Feature Configuration: To enable CFG shift (compressor) feature, set the CFG_SHIFT_MODE field of the
IATU_REGION_CTRL_2_OFF_INBOUND_i register to ‘1’.
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Overview: Based on the setting of the response code field of the IATU_REGION_CTRL_REG_2_INBOUND_i
register (2b00: Normal RADM filter response, 2b01: UR, or 2b10: CA), the controller sets the completion
status field of completion TLPs, sent in response to successfully matched non-posted TLPs. When the
response code field is set to 2b00, then the normal receive filter response for this TLP is used.
Response Code feature is not available in regions where Single Address Location
Note Enable is set.
Feature Configuration: To enable response code feature, set the RESPONSE_CODE field of the
IATU_REGION_CTRL_2_OFF_INBOUND_i register!=‘00’.
Overview: When this feature and “Single Address Location” on page 198 is enabled, the iATU matches
Msg/MsgD TLP Type field with TYPE field of IATU_REGION_CTRL_1_OFF_INBOUND_i register.
If “Fuzzy Type Match” on page 201 is also enabled, then any Msg received is matched (that is, Msg Type's
sub-field r[2:0], which specifies the Message routing mechanism, is ignored).
The Message should be consumed by your application before the next message arrives
Caution as all messages go to the same address.
Usage Scenario: This feature can be used for translation of VDM or ATS messages when AXI bridge is
configured on client interface.
Feature Configuration: To enable message type match feature, set the MSG_TYPE_MATCH_MODE field of the
IATU_REGION_CTRL_2_OFF_INBOUND_i register to =‘1’.
Overview: When this feature is enabled, the iATU relaxes the matching of the TLP type field against the
expected type field so that:
■ CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1.
■ MWr, MRd, and MRdLk TLPs are seen as identical.
■ The routing field of MsgD TLPs is ignored.
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■ Atomic Ops TLPs - FetchAdd, Swap, and CAS are seen as identical.
For example, CFG0 in the type field in the IATU_REGION_CTRL_1_OFF_INBOUND_i register matches
against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP. To enable this feature, set the Fuzzy Type
Match Mode bit of the IATU_REGION_CTRL_OFF_2_INBOUND_i register.
Feature Configuration: To enable fuzzy type match feature, set the FUZZY_TYPE_MATCH_CODE field of the
IATU_REGION_CTRL_2_OFF_INBOUND_i register to =‘1’.
3.10.10.8 Invert
Overview: Normally an address match on an inbound TLP occurs when the untranslated address is in the
region bounded by the Base address and Limit address. When the invert feature is enabled, an address
match occurs when the untranslated address is not in the region bounded by the Base address and Limit
address.
Usage Scenario: This feature is supported only when all regions of that type are set to address match mode.
Feature Configuration: To enable invert feature, set the INVERT_MODE field of the
IATU_REGION_CTRL_2_OFF_INBOUND_i register to =‘1’.
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You can access the iATU registers through the DBI interface or through BAR Matched Mem/IO requests.
The following registers are used for programming the iATU.
Table 3-57 Example: Address Table for Accessing iATU Inbound Region 1 Configuration Registers
Register Bit Value
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For releases previous to 4.80a, the iATU registers have been programmed through an indirect
Attention addressing scheme using an index register (iATU_VIEWPORT_OFF), to reduce the address
footprint in the PCI Express extended configuration space. To use the legacy method of
accessing iATU registers, contact Synopsys support through Solvnet.
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Define Inbound Region 2 as MEM region matching BAR4 (BAR match mode) mapping to
0x8000_0000_2000_0000 in your application memory space.
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For more information on supported clock frequencies and datapath widths, see “Frequency,
Note Speed, and Width Support” on page 29.
When you set the default of the Directed Speed Change field of the Link Width and Speed Change Control
register (GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE) using the DEFAULT_GEN2_SPEED_CHANGE
configuration parameter to 1, then the speed change is initiated automatically after link up, and the
controller clears the contents of GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE. If you want to prevent this
automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2
register (LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before
link up.
To manually initiate the speed change then:
■ Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device
■ De-assert GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE in the local device
■ Assert GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE in the local device
The controller uses the mac_phy_rate output to negotiate the link data rate. It changes the rate signal and
waits for a pulse on the phy_mac_phystatus signal to confirm that the PHY has accepted the requested
rate. For core_clk considerations when changing speed, see “Gen2, Gen3, Gen4, or Gen5 Speed Changing
Considerations (CX_FREQ_STEP_EN =1)” on page 57.
As per the PCI Express Base Specification, Revision 4.0, Version 1.0, the controller
Note does not implement the optional Compliance Receive bit for Gen1 configurations.
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PCI Express SW Controller Databook Gen4 16.0 GT/s Operation
PIPE Specification for PCI Express, Version 4.4.1. The controller supports two different mechanisms of
achieving the Gen3 rate: dynamic frequency and dynamic width.
■ For dynamic frequency configurations, the number of active symbols on the PIPE is constant and the
frequency of the controller doubles each time as the controller transitions from Gen1 => Gen2 => Gen3
rates.
■ When supporting dynamic width, the clock frequency of the controller remains constant and the
number of active symbols on the PIPE doubles each time as the controller transitions from Gen1 =>
Gen2 => Gen3 rates.
For more information on supported clock frequencies and datapath widths, see “Frequency,
Note Speed, and Width Support” on page 29.
The controller performs link equalization during link training to improve signal quality by adjusting the
transmitter and receiver equalization parameters for each lane on each side of the link. There are three
modes for the mapping of presets to coefficients, selectable at configuration time using the
CX_GEN3_EQ_PSET_COEF_MAP_MODE parameter:
■ Dynamic PHY: The coefficients are dynamically mapped in the PHY. This is the default mode.
■ Dynamic MAC: The coefficients are dynamically mapped in the MAC.
■ Programmable Table: The coefficients are programmed in a table by your application.
There are two feedback modes for determining the optimal equalization settings, programmable using the
Gen3 EQ Control Register (GEN3_EQ_CONTROL_OFF).
■ Figure of merit (FOM)
■ Direction change with optional convergence support
For more information on the EQ procedure and a usage guide, see “Advanced
Hint Information: Gen3/4/5 Equalization Details and Example” on page 897.
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■ When supporting dynamic width, the clock frequency of the controller remains constant and the
number of active symbols on the PIPE doubles each time as the controller transitions from Gen1 =>
Gen2 => Gen3 rates => Gen4.
For more information on supported clock frequencies and datapath widths, see “Frequency,
Note Speed, and Width Support” on page 29.
The controller performs link equalization during link training to improve signal quality by adjusting the
transmitter and receiver equalization parameters for each lane on each side of the link. There are three
modes for the mapping of presets to coefficients, selectable at configuration time using the
CX_GEN3_EQ_PSET_COEF_MAP_MODE parameter:
■ Dynamic PHY: The coefficients are dynamically mapped in the PHY. This is the default mode.
■ Dynamic MAC: The coefficients are dynamically mapped in the MAC.
■ Programmable Table: The coefficients are programmed in a table by your application.
There are two feedback modes for determining the optimal equalization settings, programmable using the
Gen3 EQ Control Register (GEN3_EQ_CONTROL_OFF).
■ Figure of merit (FOM)
■ Direction change with optional convergence support
For more information on the EQ procedure and a usage guide, see “Advanced
Hint Information: Gen3/4/5 Equalization Details and Example” on page 897.
The controller supports all mandatory PIPE message bus interface features specified in PIPE Specification for
PCI Express, Version 4.4.1, except for elastic buffer depth control and generation of read command from the
controller to PHY. Figure 3-52 to Figure 3-58 describe the lane margining operation.
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PCI Express SW Controller Databook Gen4 16.0 GT/s Operation
MAC LTSSM L0
Error Count[5:0] 0 1
PHY
Used only when IndErrorSampler=1
Sample Count[6:0] 0 3 5 6 7
Note:
If the DEFAULT_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH is less than 2 for PIPE 5.1.1 or 1 for PIPE 4.4.1, the Controller sends only write_committed command instead of
using write_uncommitted command.
Margin Margin co mmand =
left/offset=0x1 Tim + StartMagin
cmd addr data cmd addr data
M2P_MessageBus[7:0] 0x0 WC 0x1 0x1 0x0 WC 0x0 0x3 0x0
IF
No Clear
Step Margin: Tim/Left Go To No No
Margin Control Offset: 0x5
Comm
Normal Command
Error
Command
and Log
MAC LTSSM
Error Count[5:0] 1 Don’t care
Stop Margin
cmd addr data
M2P_MessageBus[7:0] 0x0 WA 0x0 WC 0x0 0x0 0x0 WA 0x0
PIPE Sample
Margin status
Cnt=0x9
P2M_MessageBus[7:0] 0x0 WC 0x1 0x9 0x0 WA 0x0 WU 0x2 0x2 WC 0x0 0x1 0x0
Error Count[5:0] 1 2 0
PHY
Used only when IndErrorSampler=1
Sample Count[6:0] 8 9 0
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MAC LTSSM L0
Error Count[5:0] 1 0
PHY
Used only when IndErrorSampler=1
Sample Count[6:0] 5 6 7 0 3 5
IF
No Clear
No Step Margin: Voltage/Up Go To No No
Margin Control Command Offset: 0x5
Comm
Normal Command
Error
Command
and Log
MAC
LTSSM L0
P2M_MessageBus[7:0] 0x0 WA 0x0 WC 0x0 0x2 0x0 WA 0x0 WC 0x0 0x1 0x0
Margining
PHY DISABLE
function
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Error Count[5:0] 3 4
Margin Margin
offset=0x0 offset=0x1
cmd addr data cmd addr data
M2P_MessageBus[7:0] 0x0 WC 0x1 0x0 0x0 WA 0x0 WC 0x1 0x1 0x0 WA 0x0
P2M_MessageBus[7:0] 0x0 WA 0x0 WC 0x0 0x1 0x0 WA 0x0 WC 0x0 0x1 0x0
IF
Clear
Step Margin: Tim/Left No No Step Margin: Tim/Left
Margin Control Offset: 0x1 Command
Error
Command Offset: 0x1
Log
MAC LTSSM L0
Error Count[5:0] 0 1 0
Sample Count[6:0] 5 6
Error Count[5:0] 0 1 0
PHY
Used only when IndErrorSampler=1
Sample Count[6:0] 5 6 7
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IF
No Clear
Step Margin: Tim/Left Go To No No
Margin Control Offset: 0x1
Comm
Normal Command
Error
Command
and Log
MAC LTSSM L0
Error Count > Error Count Limit
Error Count[5:0] 3 4 Don’t care
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PCI Express SW Controller Databook Power Management
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3.12.1 Overview
The controller supports two categories of PM operations to control the device state (D-state) and link state.
■ Software PCI Compatible PM (PCI-PM)
❑ D-state PM of Function
The host software can direct the function to enter any of the D1, D2, or D3 low-power states. It does
this by writing to the Power Management Control and Status Register (PMCSR) in the PCI-PM
capability structure.
❑ D-state PM of Link
Link states are not visible to PCI-PM legacy compatible software, and are derived from the power
management D-states of the components connected to that link. The action of changing the D-state
in the PMCSR indirectly causes a change in the link power state. The L1 state is entered whenever
all functions of a USP on a link are programmed to a non-D0 state. The entry into L2 and L3 states
is initiated by the DSP.
❑ Clock PM (L1 with REFCLK removal/PLL Off)
This is an optional feature that enables components on a link to further reduce idle power
consumption while the link is in L1, by turning off the PLL.
■ Native PCIe PM Mechanisms
❑ Active State PM (ASPM)
When the USP is in L0 and detects idleness on the link for a specific amount of time, it automati-
cally transitions the link to the L0s or L1 (optional) power state.
❑ L1 Substates
This is an optional PCIe feature that enables components on a link to further reduce idle power
consumption while the link is in L1, including almost complete removal of power for the high
speed PHY circuits.
The link state and D-state determine what power and clock supplies are on or off. For implementation
information of low-power clocking logic, see “Clock Requirements” on page 53.
D0unitialized L0 NA
L0 ON P0, P0S
Vmainb REFCLK
D0active L0S ASPM
Vaux AUXCLK
L1
ONc P1
D1, D2, D3hot L1 PCI-PM
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L2 Vaux AUXCLK
D3coldd PCI-PM OFF P2/OFFe
L3f None None
a. REFCLK is the platform reference clock for the PHY TX PLL. AUXCLK is the platform low-power clock. For more information,
see “Clock Requirements” on page 53
b. Optionally removable in L2 and L1.2 using “Advanced Power Management and Power Domain Gating” on page 238.
c. You can remove REFCLK (and pipe_clk/core_clk). For more information, see “Removing the Reference Clock” on page 58
d. Transitioned from D3hot to D3cold by removal of Vmain. D3cold is entered by the controller in response to PME_Turn_Off
MSG
e. When CX_P2NOBEACON_ENABLE =1 and PHY_INTEROP_CTRL_OFF.P2NOBEACON_ENABLE =1, mac_phy_power-
down drives P2.NoBeacon encoding, instead of P2 encoding, when the link goes to L2.
f. A function can be transitioned from L2 to L3 by the removal of Vaux.
a. You can prevent/delay the controller from entering L1-ASPM (not L1-PCI-PM) by asserting app_xfer_pending.
b. USP application asserts the app_req_entr_l1 input. A DSP controller ignores this input.
c. DSP can indirectly initiate L1 by writing non-D0 value to PMCSR of the USP link partner. A non-D0 write to the USP PMCSR
always triggers a transition to L1.
d. L2/L3 entry is initiated after the RC PM software transitions a device into a D3 state and subsequently instructs the DSP to
transmit PME_Turn_Off message TLP to initiate the removal of power and clocks.
Table 3-60 indicates the different levels of power savings (obtained by switching off circuits outside the
controller) that can be expected from executing L1 in different ways. Higher exit latencies are associated
with higher power savings. Power saving and latency are PHY implementation specific, and may be
determined by consulting your PHY documentation.
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Table 3-60 L1 Execution Modes and Permissible Power States of PHY Circuits
RX Electrical Idle
L1 Execution Mode PLL/REFCLK Detector TX Common Mode
L1 without Clock PM ON ON ON
For more information on power consumption figures, see “Advanced Information: Area, Power
Note
Estimates, and RAM Sizes” on page 1026.
For more information on optimizing system resumption time after exiting low-power states, see
“Readiness Notifications (RN)” on page 261.
The host software can direct the downstream device function to enter any of the low-power states:
■ D1 (light sleep)
■ D2 (deep sleep)
■ D3hot (full of; reference clock optionally removed; Vmain normally available)
■ D3cold (full of; reference clock removed; Vmain removed; Vaux optionally available)
It does this by writing to the PMCSR in the PCI-PM capability structure. This action also indirectly causes
the downstream component (USP) to change the link power state. The controller negotiates with the link
partner using PM TLPs and DLLPs before entering the corresponding low-power link state. The controller
exits the device low-power state (and returns to D0) when it detects a CFG access to a device function, or
when it detects a PME such as an event on the outband_pwrup_cmd1 input signal. For a function in device
power states D1, D2, and D3hot, the controller only accepts CFG and MSG requests TLPs for that function.
All other incoming request types for that function are treated as unsupported requests (UR). For more
information see Section 5.3.3, “Power Management Event Mechanisms” of the PCI Express Base Specification,
Revision 4.0, Version 1.0.
You must enable ASPM through the ASPM Control field in the Link Control register. When the USP is in L0
and detects idleness on the link for a specific amount of time (determined by the L0s Entrance Latency field2
in the “Ack Frequency and L0-L1 ASPM Control Register” ACK_F_ASPM_CTRL_OFF), it automatically
transitions the link to the L0s power state. Each link direction (TX and RX) is processed separately. The
controller exits L0s when there is traffic waiting to be sent.
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PCI Express SW Controller Databook Overview
When the USP is in L0 or L0s and it detects idleness on the link (both directions) for a specific amount of
time (determined by the L1 Entrance Latency field in ACK_F_ASPM_CTRL_OFF), it automatically transitions
the link to the L1 power state. The link partners must negotiate entry into the L1 link power state using PM
TLPs and DLLPs. The L1 state achieves greater power savings but the exit latency from this state is higher
than from L0s. You can also instruct an USP controller (only) to enter L1 by asserting the app_req_entr_l1
input. The USP exits L1 when there is traffic waiting to be sent or when a PME (such as an event on the
app_req_exit_l1 input) is received.
If the ASPM exit latencies from L0s or L1 are too high for the overall PCIe system data latency requirements,
then the host software can disable ASPM using the ASPM Control Field of the Link Control register. The
controller reports the exit latencies using the Link Capability registers. You set these by writing to these
registers or by setting the DEFAULT_L0S_EXIT_LATENCY and DEFAULT_L1_EXIT_LATENCY parameters.
Table 3-61 lists the registers shadowed in the power management controller (PMC) and the reason for
shadowing them.
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PCI Express SW Controller Databook L1 Substates
3.12.2 L1 Substates
This section discusses the L1 link substates. The following topics are discussed:
■ “L1.1 and L1.2 Entry and Exit Conditions” on page 221
■ “L1 Exit Latency (PIPE 4.2)” on page 225
■ “L1 Exit Latency (PIPE 4.3 or Later)” on page 227
The L1 substates are applicable in both the ASPM and PCI-PM L1 link states. L1 substates management
utilizes a per-link sideband signal called CLKREQ#. The controller supports this feature (with the additional
I/O as shown in “Removing the Reference Clock” on page 58) when you set CX_L1_SUBSTATES_ENABLE
=1.
To prevent L1 substates entry you can either perform a configuration write to change the
Note settings of the L1 Substates Control 1 register or set app_l1sub_disable =1.
PIPE Operation
The controller supports three interface options for L1 substates.
■ PIPE 4.2 + Sideband signals (CX_PIPE_VER =0)
❑ The controller uses the sideband signals mac_phy_rxelecidle_disable, mac_phy_txcommon-
mode_disable, and phy_mac_pclkack_n.
■ PIPE 4.3 or later (CX_PIPE_VER >1)
❑ The controller and PHY use the mac_phy_powerdown[3:0] output to indicate the PHY power
state.
❑ You can specify the power-down encodings using the CX_PIPE43_P1CPM_ENCODING,
CX_PIPE43_P1_1_ENCODING, and CX_PIPE43_P1_2_ENCODING parameters.
❑ You can specify P1.CPM entry sequence using the CX_PIPE43_P0_P1CPM parameter.
❑ You can specify P1.1 (P1.2) exit sequence using the CX_PIPE43_P1CPM_P1 parameter.
❑ The sideband signals mac_phy_rxelecidle_disable and mac_phy_txcommonmode_disable
exist on top of the controller. PHY can optionally use these signals.
❑ The sideband signal phy_mac_pclkack_n does not exist on the top of the controller.
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Contact your PHY vendor regarding L1 substates operation because the PIPE specification
Note does not clarify all details.
MAC(in) clkreq_in_n
MAC(in) clkreq_in_n
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PCI Express SW Controller Databook L1 Substates
MAC(in) clkreq_in_n
This section discusses the L1 link state. The following topics are discussed
■ “Overview”
■ “PIPE 4.2 L1 Substates Entry” on page 221
■ “PIPE 4.2 L1 Substates Exit (Locally Initiated)” on page 222
■ “PIPE 4.2 L1 Substates Exit (Remotely Initiated)” on page 222
■ “PIPE 4.3 or Later L1 Substates Entry” on page 222
■ “PIPE 4.3 or Later Substates Exit (Locally Initiated)” on page 223
■ “PIPE 4.3 or Later Substates Exit (Remotely Initiated)” on page 225
■ “L1 Substates Software Control” on page 223
3.12.2.1.1 Overview
After the link has entered L1 through the normal L1 negotiation, the USP can initiate the sequence for
entering the target L1 substate (L1.1 or L1.2) by tri-stating its CLKREQ# output buffer. The entry sequence
can only proceed if the DSP is also tri-stating its CLKREQ# output buffer, resulting in the bidirectional
CLKREQ# signal being pulled up to 1. Otherwise CLKREQ# remains asserted at 0 and the link state stays in
L1. The exit sequence can be initiated by either ports by asserting CLKREQ# to 0. For each port there are two
cases to consider, the first where the exit is initiated locally, the second where the exit is initiated remotely.
The following sections provide details on the signaling that occurs between the PCIe controller as the MAC,
the PHY, and the CLKREQ# output buffer, for entering and exiting L1 substates. L1 substates management
utilizes a per-link sideband signal called CLKREQ#. After all of the entry conditions for a L1 substate are met,
the controller asserts the mac_phy_rxelecidle_disable output. When the target L1 substate is L1.2, it
also asserts the mac_phy_txcommonmode_disable output.
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PCI Express SW Controller Databook L1 Substates
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After the USP controller enters L1, it uses the D-state of the device to determine if L1 is entered in ASPM
mode or PCI-PM mode. Table 3-62 shows the target L1 substate as a function of the relevant programmable
register fields.
After the DSP controller enters L1, it uses the USPs DLLP L1 request type to determine if L1 is entered in
ASPM mode or PCI-PM mode. Table 3-63 shows the target L1 substate as a function of the relevant
programmable register fields.
PCI PM
ASPM PM L1.1 ASPM PM L1.2 Reported LTR >= L1.1 PCI PM L1.2 Target L1
D-Statea Enabled Enabled L1.2 Threshold Enabled Enabled Substate
!D0 - - - 0 0 L1
!D0 - - - 1 0 L1.1
!D0 - - - - 1 L1.2
D0 0 0 - - - L1
D0 1 0 - - - L1.1
D0 0 1 0 - - L1
D0 1 1 0 - - L1.1
D0 - 1 1 - - L1.2
DLLP ASPM PM ASPM PM L1.2 Reported LTR >= PCI PM L1.1 PCI PM L1.2 Target L1
Received L1.1 Enabled Enabled L1.2 Threshold Enabled Enabled Substate
- - - 0 0 L1
PM_Enter_L
- - - 1 0 L1.1
1
- - - - 1 L1.2
0 0 - - - L1
1 0 - - - L1.1
PM_Active_
State_Reque 0 1 0 - - L1
st_L1
1 1 0 - - L1.1
- 1 1 - - L1.2
The Reported LTR is the maximum of the snoop/nosnoop latency values embedded in LTR messages
transmitted by the upstream ports or received by the downstream port. The controller stores these values in
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PCI Express SW Controller Databook L1 Substates
the port logic LTR Latency Register (PL_LTR_LATENCY_OFF). When the requirement bit in the message is 0,
the latency value is considered infinite (that is, the check with the threshold always pass).
For more information on LTR, see “Latency Tolerance Reporting (LTR) Message Reception” on page 166
and “Latency Tolerance Reporting (LTR) Message Generation” on page 158.
L1Substates
Capability Registers
LTR Msg
received DP LTR Port > target L1 L1Substates
Logic < substate FSM
UP Registers
L1.2 Threshold
LTR Msg device_type
transmitted
to
XADM
TX wire
Device
cfg_ltr_m_en Colour Code:
Control 2
Register only required for UP (Upstream Port)
app_ltr_latency[31:0]
(reported latency)
This section provides a breakdown of the L1 exit latency when CX_L1_SUBSTATES is enabled for L1
substates or L1 Clock PM in a PIPE 4.2 system.
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Table 3-64 L1 (PIPE 4.2) Substates and L1 Clock PM Exit Latency Component Values
A B C D E
mac_phy_powerdo
pipe_clk stable
CLKREQ# mac_phy_pclkreq_n wn Recovery
Event in Figure ->
-> -> -> ->
3-63
mac_phy_pclkreq_n phy_mac_pclkack_n mac_phy_powerdow phy_mac_phystatu L0
n
s & LTSSM change
Includes time to
Time required after
Time required to switch aux_clk back
pipe_clk is stable
Description 0 produce a stable to pipe_clk and -
to power up circuits
pipe_clk. ungating of
for P0
core_clk.
Time to
Values when 400ns to reactivate
0 execute
exiting L1.1 REFCLK + 15 us
Recovery
Estimate: 3 aux_clk T_common
cycles (slow freq) + Time to P0, ~ 2 us modea (~
T_power_on to 3 core_clk cycles.
Values when 255 us) +
0 reactivate REFCLK
exiting L1.2 time to
+ 15 us
execute
Recovery
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PCI Express SW Controller Databook L1 Substates
This section provides a breakdown of the L1 exit latency when CX_L1_SUBSTATES is enabled for L1
substates or L1 Clock PM in a PIPE 4.3 or later system.
Table 3-65 L1 (PIPE 4.3 or Later) Substates and L1 Clock PM Exit Latency Component Values
A B C D E
mac_phy_powerd
mac_phy_powerdo
CLKREQ# own pipe_clk stable
wn Recovery
Event in -> -> ->
-> ->
Figure 3-64 mac_phy_power phy_mac_phystat mac_phy_powerdo
down us phy_mac_phystatu L0
wn
s & LTSSM change
(pipe_clk stable)
Includes time to
Time required after
Time required to switch aux_clk back
pipe_clk is stable to
Description 0 produce a stable to pipe_clk and -
power up circuits
pipe_clk. ungating of
for P0
core_clk.
Synopsys, Inc.
A B C D E
400ns to
Values when Time to execute
0 reactivate
exiting L1.1 Estimate: 3 aux_clk Recovery
REFCLK + 15 us
cycles (slow freq) + Time to P0, ~ 2 us
T_power_on to 3 core_clk cycles. T_common mode
Values when
0 reactivate (~ 55 us) + time to
exiting L1.2
REFCLK + 15a us execute Recovery
a. The 15us time includes the P1.1 to P1.CPM transition time for PIPE 4.4.
CLKREQ#
REFCLK
PCLK
mac_phy_powerdown P1.1 P1 P0
phy_mac_phystatus
LTSSM L1 Recovery L0
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PCI Express SW Controller Databook L0s Entry and Exit Conditions
3.12.3.1 Overview
L0s is a low-power state enabled by ASPM. ASPM controls entry into L0s for the transmitter. The remote
device controls entry into L0s for the receiver.
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This section discusses the L1 link state. L1 is a low-power state enabled either by ASPM (L1-ASPM) or by
the software changing the D-state (L1-PM). The L1 state is a bi-directional link low-power state and both
link partners must negotiate to go to this state.
■ “L1-ASPM Overview”
■ “L1-ASPM Entry (Scenario 1): L1 Idle Timeout in L0s” on page 230
■ “L1-ASPM Entry (Scenario 2): L1 Idle Timeout in L0” on page 231
■ “L1-ASPM Entry (Scenario 3): Application Controlled (USP only)” on page 231
■ “L1-PM Entry” on page 231
■ “L1-PM/L1-ASPM Exit” on page 232
1. Created by your application, or remote link partner. DBI requests do not prevent L1 entry because the CDM registers are
clocked off aux_clk_g.
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1. Created by your application or remote link partner. DBI requests do not prevent L1 entry because the CDM registers are
clocked off aux_clk_g.
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1. PME_ENABLE bit is set in CON_STATUS_REG, and the PME_SUPPORT bit is set in CAP_ID_NXT_PTR_REG for the
corresponding D-state for which the function is currently in.
2. This exit mechanism does not apply to legacy interrupts. Before requesting the transmission of a legacy interrupt the
application should use an existing L1 exit mechanism.
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PCI Express SW Controller Databook L1 Operation (Non-substates)
L1 Exit
Note
■ The CDM space is accessible in L1, but some CDM register bits do not produce the
desired results.
■ Writing to CDM register bits which trigger LTSSM state transitions in L1 does not
have the desired effect because the LTSSM clock is not running in L1.
■ radm_idle is set to 1'b0 if ADV_ERR_CAP_CTRL_OFF[ECRC_CHK_EN] is set to 1'b1
during L1.
This feature allows you to shut down the PLL and the reference clock during standard (non-substates) L1.
Table 3-66 lists the inputs and outputs that are considered for L1 Clock PM.
clk_req_n
0
phy_clk_req_n
0 clk_req_n
1 mac_phy_powerdown[3:0] =CX_PIPE43_P1CPM_ENCODING
phy_mac_phystatus
mac_phy_pclkreq_n[0]
0
phy_mac_pclkack_n
1
mac_phy_powerdown[3:0] =CX_PIPE43_P1CPM_ENCODING
1
phy_mac_phystatus
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local_ref_clk_req_n[0] (L1SS=1)
MAC -> clk_rst
clk_req_n (L1SS=0)
MAC(in) clkreq_in_n
wake up event
local_ref_clk_req_n[0](L1SS=1)
MAC -> clk_rst
clk_req_n (L1SS=0)
MAC(in) clkreq_in_n
wake up event
3.12.4.3 L1 Clock PM (L1 with REFCLK removal/PLL Off); Entry and Exit Conditions
To enable the controller (upstream port only) to execute L1 with Clock PM:
■ The Support Clock Power Management bit in the Link Capabilities register must be set. The default
value of this register is controlled by the DEFAULT_CLK_PM_CAP parameter. For downstream ports it
is hardcoded to 0, for upstream ports it can be accessed through the DBI.
■ The Enable Clock Power Management bit in the Link Control register must be set.
■ You must set the app_clk_pm_en input to 1. The controller only samples app_clk_pm_en when L1
is entered.
L1 with Clock PM and L1 substates work orthogonal to each other. L1 with Clock PM uses the
mac_phy_pclkreq_n[0] signaling, and L1 substates uses the mac_phy_pclkreq_n[1]signaling. However,
L1 substates takes precedence over Clock PM within the cores PM state machine. This means that when the
entry conditions for any L1 substate are satisfied (as per “L1 Substates Software Control” on page 223), then
the controller's LTSSM executes the corresponding L1 substate protocol.
For more information on L1 exit latency, see “L1-PM/L1-ASPM Exit” on page 232.
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PCI Express SW Controller Databook L2 and L3 Power Down Entry and Exit Conditions (USP)
3.12.5.1 Overview
L2/L3 entry is initiated1 after the RC calls power management software to initiate the removal of power and
clocks. USPs of devices in D0, D1, D2, and D3hot must respond to the receipt of a PME_Turn_Off MSG TLP
by transmitting a PME_TO_Ack MSG TLP. The device must then request a link transition to L2/L3_Ready.
L2/L3_Ready is a bi-directional link power down state. If your application is not ready to be shut-down, it
must keep the app_ready_entr_l23 input de-asserted. This causes the controller to delay sending the
PM_Enter_L23 DLLP and thereby stalling the negotiation handshake that uses the following DLLPs:
■ PM_Enter_L23
■ PM_Request_Ack
When your application is eventually ready for transitioning to D3cold, that is, loss of main power and
reference clock, L2/L3_Ready is entered and the downstream device begins preparation for the power and
clock removal. After main power has been removed, the link transitions to L2 if Vaux is provided, or it
transitions to L3 if no Vaux is provided.
1. In preparation for removing the main power source, your RC application asserts the apps_pm_xmt_turnoff input which
causes the RC to broadcast the PME_Turn_Off MSG TLP to all USPs.
2. PME_ENABLE bit is set in CON_STATUS_REG, and the PME_SUPPORT bit is set in CAP_ID_NXT_PTR_REG for the
corresponding D-state for which the function is currently in.
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The controller directs the PHY to generate beacon signaling when a PCIe device initiates a wake-up event.
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PCI Express SW Controller Databook Outbound TLP Blocking in USP
Table 3-67 Configuration Settings for Blocking all Outbound TLPs on Transmit Interfaces in Non-D0 State
PCIPM_NEW_TLP_CLIENT0/1/2_BLO
Only Request TLPs CX_CLIENT0/1/2_BLOCK_NEW_TLP =1
XALI0, CKED =1
XALI1, Both Request and
or Completion TLPs
XALI2a CX_CLIENT0/1/2_BLOCK_NEW_TLP =0b NA
(not Message
TLPs)
a. Depending on the interface being used, the corresponding parameter or PCIPM_TRAFFIC_CTRL register field must be set.
b. That is, the default value of parameter CX_CLIENT0/1/2_BLOCK_NEW_TLP, so that the controller allows all outbound comple-
tion TLPs on that transmit interface in non-D0 state. Your application must prevent new request TLPs from appearing on the
corresponding transmit interface when pm_xtlh_block_tlp =1.
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This feature allows you to implement power domain gating in your SoC design. It provides all the necessary
clock, reset, and power gating controls.
Description Supported
C-PCIe Features
Optional Wait for External Application/PHY to Save Any State Before Power Removal in L1.2
■ The PHY or your application can use the pm_save_state_req and pm_restore_state_req outputs to
retain any useful information in the always-on memory. For example, the PHY configuration regis-
ters.
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Description Supported
PIPE Status Frozen Using Controller Logic (no Change in Value) in L1.2
■ The controller freezes all PIPE outputs at the values prior to power removal using shadow registers
in the RTL. This includes Gen3 equalization data. The controller does not redo Gen3 equalization
after restoration of power.
Note: DBI requests do not prevent L1 entry because the CDM registers ) are clocked off aux_clk_g.
However, outstanding DBI transactions forces the controller to keep the link in L1 (with core_clk gated
off) and power gating deactivated.
Power Restoration in L1.2 Indirectly Triggered by Application Activity Causing L1.2 Exit
■ The controller does not restore power until it is required to exit L1.2. The controller exits L1.2 (and
L1) when your application is requesting to send traffic by asserting client0_tlp_hv. This consequently
triggers restoration of power. For more information, see “L1-PM/L1-ASPM Exit” on page 232.
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Description Supported
Power Restoration in L1.2 Indirectly Triggered by SII Activity Causing L1.2 Exit
■ The controller does not restore power until it is required to exit L1.2. Activity on any of the SII or ancil-
lary interfaces does not trigger L1.2 exit. Therefore activity on any of the SII or ancillary interfaces
do not trigger restoration of power.
Assumptions/Limitations
PHY Autonomously Generates its Own Reset When Exiting L1.2 Power Gating
■ The controller does not reset the PHY when exiting L1.2 power gating.
Power-gating Interoperability with Synopsys PHYs Using L1 Clock Power Management (CPM)
■ PHY controller interoperability with some Synopsys PHY's is ongoing.
L1.CPM with power-gating is not supported when some Synopsys PHYs are power-gating their
receiver electrical idle detection circuitry in that state; because this causes violations of the specifi-
cation.
UPF Features
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Description Supported
CX_ENHANCED_PM_EN
CX_L2_PG_EN
CX_L12_PG_EN
CX_L1_RETENTION
CX_RETENTION_TYPE
CX_LEVEL_SHIFT_EN
CM_STORE_MPHY_ATTR_ENABLE
When the controller MAC is in L2 (after being programmed to D3), the system might decide to power-down
the primary supply of VMAIN by asserting perst_n. Therefore, the assertion of perst_n is an indication
that the system power controller is going to switch off VMAIN.
■ CX_L2_PG_EN =1
■ CX_L12_PG_EN =0
■ CX_L1_SUBSTATES_ENABLE =0 || (CX_L1_SUBSTATES_ENABLE =1 && app_l1_pwr_off_en
=0)
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■ CX_L1_RETENTION =0
Power Supply
L0/L1 ON ON
L2 ON OFF
L3 OFF OFF
PCIe Controller
All Controller Logic
(DWC_pcie_ctl)
(DWC_pcie_core)
iso_vmain_to_
vaux
iso User
PMC Application
Isolation Logic
Cell
PHY
Isolation
Cell
iso
DWC_pcie
_clkrst.v iso_vmain_to_vaux
VAUX Board
perst_n L2
Power Domains
Power
Switch PD_VAUX
PD_VMAIN_SW
(pcie_iip_device.upf) VMAIN
PD_VMAIN_SW
pm_linkst_in_l2
perst_n
iso_vmain_to_vaux
core_rst_n
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PCI Express SW Controller Databook Advanced Power Management and Power Domain Gating
0RE REQUISITE
v .EGOTIATION FOR , ENTRY HAS BEEN SUCCESSFULLY COMPLETED
0
4HE CONTROLLER WILL ASSERT THE OUTPUT pm_linkst_in_l2
WHEN THIS IS THE CASE
0%234 ,
4HE CONTROLLER WAITS FOR THE INPUT perst_n TO BE SET TO B
1
BEFORE IT BEGINS THE PROCESS OF ISOLATING THE ALWAYS ON DOMAIN
)3/,!4)/.
$/.%
2%,%!3%
2%3%4
6 4HE RESET REQUESTS ARE DE ASSERTED
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3.12.7.3 C-PCIe L2 Power Gating + Autonomous L1.2 Power Gating (No Retention Registers)
There is a power switch in the UPF to allow the power management circuitry of the controller to
automatically switch off the primary power supply to the selected parts of the design. Certain parts1 of the
design may still need to retain the state when power is removed. The state retention task is achieved by
creating always on supply islands for modules requiring power in L1 sub-states. There are seven L1ON
power islands (representing different parts of the RTL hierarchy) defined in the UPF. You can merge these
into one power domain (PD_L1ON).
■ CX_L2_PG_EN =1
■ CX_L12_PG_EN =1
■ CX_L1_SUBSTATES_ENABLE =1 && app_l1_pwr_off_en =1
■ CX_L1_RETENTION =0
Power Supply
L0/L1/L1.1 ON ON
L1.2 ON ONa
L2 ON OFF
L3 OFF OFF
a. In L1.2 mode the MAIN power domain inside the controller is completely switched off. It might be ON at the SoC level, but in
PCIe controller context it is switched off.
1. Such as CDM register block, Gen3 EQ settings, credits, lane reversal information and so on.
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PCI Express SW Controller Databook Advanced Power Management and Power Domain Gating
iso_vmain_to_von
PCIe Controller User
All Controller Logic
(DWC_pcie_ctl) iso Application
(DWC_pcie_core)
Logic
iso_vmain_to_vl1on
pm_en_vmain_n
Isolation
L1.2 Always On
Cells
Logic
PMC
iso
Tx iso_vmain_to_vaux
PHY
pm_en_vmain_n
Autonomous
DWC_pcie L1.2 SoC
_clkrst.v Power Switch
Note: This switch
representation will
reflect in the UPF
deliverables of the
controller.
VAUX
perst_n
Power Domains
Board L2
Power Switch PD_VAUX
Note: This switch PD_VMAIN_SW
VMAIN
representation will NOT
PD_L1ON
reflect in the UPF
(pcie_iip_device_upf) deliverables of the controller. PD_PHY
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VAUX
PD_PLL
PD_L1ON
PD_VMAIN_SW
pm_linkst_in_l2
perst_n
iso_vmain_to_vaux
iso_vl1on_to_vaux
iso_vmain_to_vl1on
core_rst_n
VAUX
PD_L1ON
PD_PLL
PD_VMAIN_SW assume ack_en_vmain =1
pm_link_st_in_l1sub
iso_vmain_to_vaux
iso _vl1on_to_vaux
iso_vmain_to_vl1on
core_rst_n
en_vmain_n
app_req_exit_l1
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PCI Express SW Controller Databook Advanced Power Management and Power Domain Gating
0RE REQUISITE
, 0/7%2$/7.
0 ! PRE REQUISITE FOR THE POWER GATING PROCESS IS THAT THE LINK HAS
ENTERED THE , 0- 3UB STATE
4HE CONTROLLER PERFORMS A HANDSHAKE WITH THE !-"! BRIDGE IF
v !-"! BRIDGE 1
HANDSHAKE
PRESENT TO ENSURE THAT THERE ARE NO TRANSFERS PENDING 4HE
v #HECK $") 6 CONTROLLER CHECKS FOR PENDING !8) TRANSFERS AND $") TRANSFERS
!#4)6%
PENDING 1 AND ONLY PROCEEDS WITH THE POWER GATING PROCESS IF THERE ARE
v #HECK , SUB 0OWER 3WITCH NO PENDING TRANSFERS AND THE BRIDGE HAS ACKNOWLEDGED
STATES EXIT REQUEST !CKNOWLEDGE READINESS FOR POWER GATING )F THE LINK EXITS , DURING THIS
PROCESS THE POWER GATING PROCESS WILL NOT BE INITIATED
2 4HE CONTROLLER ASSERTS AN OUTPUT CALLED pm_save_state_req
2EADY AND WAITS FOR THE APPLICATION TO ASSERT THE INPUT
FOR 0OWER 7 2
2EMOVAL
save_state_ack THIS IS INTENDED TO ALLOW ANY APPLICATION
SPECIFIC STATE TO BE SAVED
0/7%2 50
4HE CONTROLLER ISOLATES THE OUTPUTS FROM ITS SWITCHABLE POWER
DOMAINS
v )F !-"! BRIDGE IS PRESENT AND ASYNCHRONOUS TO THE
!PPLICATION 8 3 core_clk THE ISOLATION ENABLE IS SYNCHRONIZED TO THE
3!6%?34!4%
3AVES 3TATE !-"! CLOCK DOMAINS
0OWER 3WITCH v 4HE CONTROLLER WAITS FOR ALL ISOLATION ENABLES TO BE ASSERTED
!CKNOWLEDGE BEFORE PROCEEDING WITH POWER REMOVAL
2%,%!3%?2%3%4
4HE CONTROLLER SETS THE OUTPUT pm_en_vmain TO 1’b0 TO
5
INDICATE THAT IT IS READY FOR POWER REMOVAL
3
4HE CONTROLLER EXPECTS AN ACKNOWLEDGEMENT FROM THE EXTERNAL
10 6
)3/,!4%
POWER SWITCH TO INDICATE POWER HAS BEEN REMOVED
2%3%4 7HEN A POWER UP REQUEST IS DETECTED THE CONTROLLER SETS THE
$/.%
7 OUTPUT pm_en_vmain TO 1’b1 TO REQUEST THE RESTORATION OF
POWER
3.12.7.4 C-PCIe L2 Power Gating + Autonomous L1.2 Power Gating (Using Retention Registers)
There is a power switch in the UPF to allow the power management circuitry of the controller to
automatically switch off the primary power supply to selected parts of the design. Certain parts1 of the
design may still need to retain the state when power is removed. The state retention task is achieved by
implementing (using your technology vendors library) retention registers in selected modules.
1. Such as CDM register block, Gen3 EQ settings, credits, lane reversal information and so on.
Synopsys, Inc.
■ CX_L2_PG_EN =1
■ CX_L12_PG_EN =1
■ CX_L1_SUBSTATES_ENABLE =1 && app_l1_pwr_off_en =1
■ CX_L1_RETENTION =1
Power Supply
L0/L1/L1.1 ON ON
L1.2 ON ONa
L2 ON OFF
L3 OFF OFF
a. In L1.2 mode the MAIN power domain inside the controller is completely switched off. It might be ON at the SoC level, but in
PCIe controller context it is switched off.
PMC
iso
iso_vmain_to_vaux
pm_ en_vmain_n
Autonomous
DWC_pcie L1.2 SoC
_clkrst.v Power
Switch
VAUX Board
perst_n L2
Power Domains
Power
Switch PD_VAUX
PD_VMAIN_SW
(pcie_iip_device_upf) VMAIN
VMAIN
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PCI Express SW Controller Databook Advanced Power Management and Power Domain Gating
pm_linkst_in_l2
perst_n
iso_vmain_to_vaux
iso_vl1on_to_vaux
core_rst_n
L1.2 Timing
VAUX
PD_PLL
pm_link_st_in_l1sub
save_state
iso_vmain_to_vaux
iso_vl1on_to_vaux
core_rst_n
en_vmain_n
app_req_exit_l1
restore_state
Synopsys, Inc.
This scheme is similar to “C-PCIe L2 Power Gating + Autonomous L1.2 Power Gating (No Retention
Registers)” on page 244 except that there is no always-on power supply available in L2.
■ CX_L2_PG_EN =0
■ CX_L12_PG_EN =1
■ CX_L1_SUBSTATES_ENABLE =1 && app_l1_pwr_off_en =1
■ CX_L1_RETENTION =0
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PCI Express SW Controller Databook Advanced Power Management and Power Domain Gating
Power Supply
Isolation
pm_en_vmain_n L1.2 Always
Cells
iso_vmain_to_vl1on On Logic
PMC
iso
iso_vmain_to_vaux
Tx
PHY
pm_en_vmain_n
DWC_pcie Autonomous
_clkrst.v L1.2 SoC
Power
Switch
Power Domains
VMAIN
PD_VAUX
PD_VMAIN_SW
PD_L1ON
(pcie_iip_device_upf) PD_PHY
pm_link_st_in_l1sub
iso _vmain_to_vaux
iso _vl1on_to_vaux
iso_vmain_to_vl1on
core_rst_n
en_vmain_n
app_req_exit_l1
Synopsys, Inc.
This scheme is similar to “C-PCIe L2 Power Gating + Autonomous L1.2 Power Gating (Using Retention
Registers)” on page 247 except that there is no always-on power supply available in L2.
■ CX_L2_PG_EN =0
■ CX_L12_PG_EN =1
■ CX_L1_SUBSTATES_ENABLE =1 && app_l1_pwr_off_en =1
■ CX_L1_RETENTION =1
Power Supply
PCIe Controller
iso_vmain_to_vaux User
(DWC_pcie_ctl)
Application
All Controller Logic iso Logic
pm_en_vmain_n (DWC_pcie_core)
pm_save_state_req
Retention
Registers
pm_restore_state_req
PMC
iso
iso_vmain_to_vaux
pm_en_vmain_n
DWC_pcie Autonomous
_clkrst.v L1.2 SoC
Power
Switch
Power Domains
VMAIN
PD_VAUX
PD_VMAIN_SW
VMAIN
(pcie_iip_device_upf)
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PCI Express SW Controller Databook Advanced Power Management and Power Domain Gating
pm_link_st_in_l1sub
save_state
iso_vmain_to_vaux
iso _vl1on_to_vaux
core_rst_n
en_vmain_n
app_req_exit_l1
restore_state
A set of configuration-specific UPF files which are supported by VTB simulations and synthesis are created
by the coreConsultant tool in workspace/upf. The main UPF file defines:
■ Power domains
■ Isolation rules
■ Level shifter rules
■ Retention cell technology cell name. You must edit the UPF and replace this with the actual name of
the retention registers in your technology vendor s library.
■ Power supplies
■ Power states
■ Power state table
Note For more information, see the “UPF Flow and Methodology” section in the User Guide
P2.NoBeacon is a custom powerdown encoding supported by Synopsys PHYs that enables deeper power
saving as compared to the P2 state. To enable the controller to drive the PHY’s P2.NoBeacon state you must
set the parameter CX_P2NOBEACON_ENABLE to ‘1’.
When this feature is enabled,
■ The controller/PHY exits from L2/P2 only when PERST# is de-asserted. Beacon is not supported as
an exit condition by the PHY, and is ignored
■ mac_phy_powerdown drives P2.NoBeacon encoding, instead of P2 encoding, when the link goes to L2
To configure P2.NoBeacon encoding use CX_PIPE43_P2NOBEACON_ENCODING parameter. The default
value of this parameter is 4'b1111. To disable this feature, set P2NOBEACON_ENABLE field of the
PHY_INTEROP_CTRL_OFF register to ‘0’.
Synopsys, Inc.
As the PCIe specification states, This mechanism is intended to be activated only when there
Attention is no reasonable expectation that the completion is returned, and should never occur under
normal operating conditions.
Table 3-74 Comparison of PCIe Specification and Synopsys PCIe Controller Completion Timeout Ranges
(CX_CPL_TO_RANGES_ENABLE =1)
PCIe controller PCIe controller
Range Encoding Spec Minimum Spec Maximum Minimum Maximum
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PCI Express SW Controller Databook Crosslink
3.14 Crosslink
Crosslink allows a downstream port to be connected to another downstream port or an upstream port to be
connected to another upstream port. When a crosslink capable port negotiates a crosslink connection, the
port changes its behavior accordingly (see description of device_type input in “SII: Global Controller
Control” on page 306. For this reason crosslink is supported in the SW controller because this product
already contains the functionality for both upstream and downstream support.
Crosslink provides more than simply the ability to connect two like ports together. For instance, a DM
operating in EP mode that negotiates a crosslink connection switches to RC mode and follows all of the PCI
Express Base Specification, Revision 4.0, Version 1.0 rules for an RC.
Part of the crosslink functionality requires a random timeout to be used. Your application is required to
provide this non-zero value on the app_crosslink_time[7:0] input. Your application must update this
value randomly every time the controller pulses the smlh_crosslink_time_request signal. The
controller samples the app_crosslink_time[7:0] inputs 4 us later for a CX_FREQ =1 configuration, 8 us
later for a CX_FREQ =2 configuration, and 16 us later for a CX_FREQ =3 configuration, after it pulses the
smlh_crosslink_time_request signal.
The crosslink feature is enabled by the CX_CROSSLINK_ENABLE configuration parameter.
To be compliant with the PCI Express Specification and to make sure crosslink functions
Note properly when two instances of the same device are connected together, the random timeout
must be unique to each device.
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PCI Express SW Controller Databook Atomic Operations (AtomicOps)
Limitations
■ When you enable 128-bit Atomic CAS instructions (through the CX_ATOMIC_128_CAS_EN configura-
tion parameter), you must configure the controller (through the RADM_NP_DCRD_VCn configuration
parameter) to advertise more than one non-posted data credit on at least one VC.
■ The controller rejects AtomicOps that target the ELBI, and returns a completion with CA status.
■ AtomicOp TLP type cannot be nullified on TX.
Synopsys, Inc.
DWC_pcie_sw A
(Egress Port/USP)
cfg_atomic_egress_block
app_err_bus[8]
Upstream
Traffic
Downstream
Traffic
UR Cpl
Discard
AtomicOp enable
Detector
1 0
detected demux
0 1
mux
C
Switch Application
1
Logic
Upstream Atomic
2 Request
Downstream
UR Cpl
DWC_pcie_sw B
(Ingress Port/DSP)
1. The unsupported request detected bit in the Device Status register is not set.
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PCI Express SW Controller Databook TLP Prefix
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Table 3-75 SKP Ordered Set Intervals in SRIS and non-SRIS Modes
SKP Ordered Set Intervals SKP Ordered Set Intervals
CX_SRIS_SUPPORT app_sris_mode (8b/10b Encoding) (128b/130b Encoding)
1 0 Normal Normal
1 1 Short (less than 154 Symbol times) short (less than 38 Blocks)
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PCI Express SW Controller Databook Readiness Notifications (RN)
■ The reason field in the transmitted message may contain a code from any of
the events.
3. Software is permitted to issue requests to the function (following any of these
events) after receiving an FRS message from this function and need not wait for
the (longer) times required elsewhere in the specification for these events.
4. The DSP controller asserts the cfg_up_drs_to_frs output and sends an FRS
message with the reason code set to “DRS Message Received” when:
■ It receives a DRS message, and
■ PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STA-
TUS_REG is 2b10
Synopsys, Inc.
CX_RN_DRS_SUPPORTED
1. Your application can delay/prevent DRS message generation by setting
app_req_retry_en/app_pf_req_retry_en =1 or app_drs_ready =0.
2. Software is permitted to issue requests to the function (following any of these
events) after receiving an DRS message from this function and need not wait for
the (longer) times required elsewhere in the specification for these events.
3. The DSP controller asserts the cfg_drs_msi output when all of the following are
true:
■ It receives a DRS message
■ PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STA-
TUS_REG is 2b01
■ MSI or MSI-X is enabled
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PCI Express SW Controller Databook Precision Time Measurement (PTM)
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Controller Logic
Physical Boundary
PTM Response
Increasing Time PTM Request Message or ResponseD Increasing Time
Message
Physical Boundary
Controller Logic
The Tx and Rx Latency registers are programmed through an indirect addressing scheme using an index
register (PTM_[RES|REQ]_LATENCY_REG_SEL_OFF), to reduce the address footprint in the PCI Express
extended configuration space. The index register has Responder/Requester Latency Register Write Select
field (PTM_[RES|REQ]_LATENCY_REG_SEL), referred to as index, to determine which Tx or Rx Latency
viewport register (PTM_RES_[TX|RX]_LATENCY_OFF) to program/read for each link speed. Table 3-77
provides the index to link speed mapping.
0 0 2.5
0 1 5
0 2 8
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PCI Express SW Controller Databook Transmit and Receive Latencies
0 3 16
0 4 32
1 0 20
1 1 25
If the Tx and Rx latency registers are not programmed, the default latency values are the same for all speeds,
and are set by configuration parameters, as follows:
■ Tx Latency =CX_PHY_TX_DELAY_PHY + CX_PHY_TX_DELAY_MAC
■ Rx Latency =CX_PHY_RX_DELAY_PHY + CX_PHY_RX_DELAY_MAC
Programming Examples
Example 1: To setup PTM Requester Tx Latency to 56ns and Rx Latency to 334ns for 2.5 GT/s
1. Setup speed mode (PCI Express or CCIX ESM)
Write 1'b0 to PTM_REQ_ESM_SEL, to set PCI Express speed mode
2. Setup the index
Write 32'h0000_0000 to PTM_REQ_LATENCY_REG_SEL, to select 2.5 GT/s Latency viewport Tx and Rx
registers
3. Write the Tx/Rx Latency values
Write 32'h0000_0038 to PTM_REQ_TX_LATENCY, to set 2.5 GT/s Tx latency to 56 ns
Write 32'h0000_014E to PTM_REQ_RX_LATENCY, to set 2.5 GT/s Rx latency to 334 ns
Example 2: To setup PTM Responder Tx Latency to 24ns and Rx Latency to 115ns for 8 GT/s
1. Setup speed mode (PCI Express or CCIX ESM)
Write 1'b0 to PTM_RES_ESM_SEL, to set PCI Express speed mode
2. Setup the index
Write 32'h0000_0002 to PTM_RES_LATENCY_REG_SEL, to select 8 GT/s Latency viewport Tx and Rx
registers
3. Write the Tx/Rx Latency value
Write 32'h0000_0018 to PTM_RES_TX_LATENCY, to set 8 GT/s Tx latency to 24ns
Write 32'h0000_0073 to PTM_RES_RX_LATENCY_OFF register, to set 8 GT/s Rx latency to 115ns
Example 3: To setup PTM Requester Tx Latency to 7ns and Rx Latency to 18ns for 20 GT/s
(CX_CCIX_ESM_SUPPORT =1)
1. Setup speed mode (PCI Express or CCIX ESM)
Write 1'b1 to PTM_REQ_ESM_SEL, to set CCIX ESM speed mode
Synopsys, Inc.
TX Processing Path
ptm_auto_update _signal
SET OR EN
PTM_REQ_CONTROL_OFF D Q 10 mS
register PTM Timer
PTM_REQ _AUTO_UPDATE_ENABLED
field CLR Q
VSEC Registers
(PTM_REQ_*)
PTM Response or
Timestamps ResponseD Message
Received
t4 updated
1uS / t4' updated
100 uS name
PTM
Update PTM PTM Master Time at t 1' is
3 Timers
Context Clock Software calculated when
access
ResponseD message is
received, and Local Clock Tx Latency
is also updated Rx Latency
PTM Request
Message Receiver
PTM Response or ResponseD
PTM Response Message Sent
RX or ResponseD TX
t3 updated
Message t3' updated
RX Processing Path
Receive
2
Response
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PCI Express SW Controller Databook Requester (USP) Features
When PTM context is invalidated due to duplicates or replays, speed change, or L0 exit,
the Requester waits for a PTM response or for 100µs timeout since the previous request
was sent before allowing a new update cycle to start. If a timeout occurs while waiting,
Note ptm_req_response_timeout is asserted. To check for unexpected
ptm_req_response_timeout assertions, externally AND the timeout indication with the
ptm_updating output.
■ Requester automatically updates PTM context (starting dialogs) when enabled using any or all of:
❑ Automatic trigger every 10ms (can be enabled through top-level pin or through a register)
❑ Manual trigger through top-level pin, if ptm_trigger_allowed is asserted
❑ Manual trigger through a register write, if ptm_trigger_allowed is asserted or PTM_REQ_MAN-
UAL_UPDATE_ALLOWED field in the PTM_REQ_STATUS_OFF register is set
■ Requester indicates that a PTM update is in progress (through ptm_updating)
■ Requester indicates reception of duplicate PTM TLP (through ptm_req_dup_rx) while PTM updates
are in progress, or between updates when PTM context is valid
If a new update is started immediately after context was invalidated due to duplicate
TLP it results in a double assertion of the ptm_req_dup_rx output and the update is
Note delayed by a cycle. This can happen when auto-update is used.
■ Requester indicates that a PTM request is replayed (through ptm_req_replay_tx) while PTM
updates are in progress, or between updates when PTM context is valid
■ Local PTM Clock
❑ Runs on core_clk, counts time in non-integer nanosecond, and its minimum granularity is
defined by the core_clk frequency
❑ Auto-updated on PTM context refresh
❑ Can also be updated by software
❑ Can be read by software
❑ Available through top-level port
■ Context automatically invalidated when:
❑ core_clk stops or runs at the wrong frequency (for example, in L1 substates or when the link
speed is changing), or
❑ PTM is disabled by clearing the PTM_ENABLE bit in the PTM_CONTROL_OFF register, or
❑ PTM response timeouts (the requester restarts the PTM dialog when the auto-update or manual
update start conditions are met), or
❑ A duplicate PTM TLP is received or a replay TLP is sent (if waiting for a response the requester
waits for 100µs since the last non-duplicate request has been sent, before allowing a new PTM
dialog to be started)
Synopsys, Inc.
If PTM is disabled by clearing the PTM_ENABLE bit, it is recommended to wait for some
time to allow the PTM Responder in the link partner to complete sending a response
Note before re-enabling PTM. The wait time will depend on the maximum response time of
the PTM Responder.
■ Context information stored in PTM Requester VSEC (PTM_REQ_*_OFF); one instance shared across all
functions):
❑ Provides access to timestamps of most recent context refresh
❑ Provides notification when context is valid
❑ Programmable Tx and Rx latency values for each link speed, automatically selected based on
current link speed
■ Requester prevents low power entry due to ASPM during PTM updates
PTM Request
Message Received
t2 updated
t2' updated
RX Processing Path
PTM Request Message Sent
t1 updated PTM Request
TX RX
t1' updated Message
PTM Request
Rx Latency Message Receiver
Tx Latency
Receive
1 Request
VSEC Registers
(PTM_RES_*)
Timestamps
1uS /
100 uS name
PTM
PTM Timers
Clock Software
access
PTM Response or
ResponseD Message
Sent
Generate
Tx Latency t3 updated 2 Response
Rx Latency t3' updated
PTM Response or ResponseD
Message Received
t4 updated PTM Response
t4' updated PTM Response Message Generator
RX or ResponseD TX
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PCI Express SW Controller Databook Local PTM Clock Scaling
❑ If CX_PTM_EXTERNAL_MASTER_TIME =1 an external master time can be used to set the clock value
Note: The external master time is latched when ptm_external_master_strobe signal is set to 1.
❑ Can also be updated by software
❑ Can be read by software
❑ Available through top-level port
■ Context automatically invalidated when core_clk stops, or runs at the wrong frequency (for
example, in L1 substates or when the link speed is changing), or when PTM is disabled by clearing the
PTM_ENABLE bit in the PTM_CONTROL_OFF register. When the controller asserts ptm_respond-
er_rdy_to_validate signal, your application can re-validate the context by either,
❑ [CX_PTM_EXTERNAL_MASTER_TIME =1]: Updating the local PTM clock using the ptm_exter-
nal_master_time and ptm_external_master_strobe signals, which automatically asserts
the ptm_context_valid signal, or
❑ [DBI Access]: Updating the local PTM clock by writing to PTM_RES_LOCAL_LSB_OFF and
PTM_RES_LOCAL_MSB_OFF registers, and then setting the PTM_RES_CCONTEXT_VALID field of
PTM_RES_CONTROL_OFF to 1, which automatically asserts ptm_context_valid signal
■ Root Support
❑ Ideally a PTM root behaves like a responder with permanently valid context. However,
- If the PTM root enters low power modes or changes link frequency, PTM context is invalidated
(indicated by ptm_context_valid =0)
- Following PTM context invalidation, the application must re-validate PTM context, by using
either the PTM master time interface signals or the PTM responder VSEC registers, as described in
the previous list item
❑ PTM messages must not contain TLP prefixes
■ Context information stored in PTM Responder VSEC (PTM_RES_*_OFF):
❑ Provides access to timestamps of most recent context refresh
❑ Provides notification when context is valid
❑ Programmable Tx and Rx latency values for each link speed, automatically selected based on
current link speed
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For the PTM Responder, your application fully controls PTM local clock updates. If the external master
clock runs from the same source clock as the PCIe controller, clock scaling is not needed. However, for
applications where the external master and PCIe controller run on unrelated clock sources, it may be
necessary to scale the local PTM clock period.
To enable this feature set the PTM_RES_SCALED_CLOCK_T_EN field of PTM_RES_SCALED_CLOCK_T_OFF
register to ‘1’ (this bit can only be set when ptm_context_valid is set). You can set a 24-bit value
consisting of an 8-bit integral part (nanoseconds) and 16-bit fractional part (1/216 nanoseconds) using
PTM_RES_SCALED_CLOCK_T_INT and PTM_RES_SCALED_CLOCK_T_FRAC fields of the
PTM_RES_SCALED_CLOCK_T_OFF register, which represents the scaled local PTM clock period.
The clock scaling procedure is as follows:
■ Your application initializes the PTM Responder with a known time from an external master
■ The PTM Responder counts local PTM time using the Nominal PTM Clock Period, which your appli-
cation can read from the PTM_RES_NOM_CLOCK_T_OFF register
■ Your application waits for a known time and reads the local PTM clock value again
■ Your application calculates the scaled PTM clock period using the deviation between the external
master clock and the local PTM clock, and writes the scaled PTM clock period to PTM Responder's
Scaled PTM Clock Period register (PTM_RES_SCALED_CLOCK_T_OFF), which represents the scaled
local PTM clock period
If the PTM context becomes invalid your application must reiterate the steps listed in this section.
The PTM Requester and PTM Responder scaled clock period enable bits are cleared when the core_clk
rate changes, and can only be set when the clock rate change is complete. The core_clk rate is controlled
by LTSSM, using the mac_phy_rate signal. When mac_phy_rate changes, the register bits are cleared.
When the current data rate has been updated to match mac_phy_rate, setting of the bits is enabled.
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PCI Express SW Controller Databook Access Control Services (ACS)
ACS Source Validation (V) CX_ACS_SRC_VALID ■ The controller returns CA status CPL for NP
requests.
■ The controller reports AER: ACS Violation Error.
Note: For NP Requests, If ACS violation is
ACS Translation Blocking non-fatal, Advisory Non-Fatal Error is reported.
CX_ACS_AT_BLOCK
(B) ■ The controller sets the Signaled Target Abort bit
in the PCI compatible Status, or Secondary
Status register.
Synopsys, Inc.
ACS P2P Request Redirect CX_ACS_P2P_REQ_REDIRECT_n ■ The controller does not take any action.
(R)b (n =0; n <=CX_NFUNC-1) ■ Your application logic should generate CPL for
NP requests.
CX_ACS_P2P_COMPL_REDIRECT ■ Your application logic can use the controller
ACS P2P Completion
_n signal app_err_bus[12] to detect ACS viola-
Redirect (C)a tion, and take action accordingly.
(n =0; n <=CX_NFUNC-1)
CX_ACS_P2P_EGRESS_CTRL_n
ACS P2P Egress Control (E)
(n =0; n <=CX_NFUNC-1)
CX_ACS_P2P_DIRECT_TRANSL_
ACS Direct Translated P2P
n
(T)
(n =0; n <=CX_NFUNC-1)
a. When CX_ACS_UP_FORWARD =1, DSP forwards TLPs within the memory/IO ranges upstream. When CX_ACS_UP_FOR-
WARD =0, these TLPs are treated as UR.
b. It is not used by the controller internally to gate peer-to-peer traffic.
CX_ACS_P2P_DIRECT_TRANSL_n
ACS Direct Translated P2P (T)
(n =0; n <=CX_NFUNC-1)
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PCI Express SW Controller Databook Completion Queue Management
XADM_MUX
Decide whether to
Scan the NP request 2 transmit or halt the
for the number of NP request Cpl_I/F
Data and Header
TLP A 1 Msg_I/F
credits required Mux_out
client0_tlp_* Client0_I/F
NO
The completion queue manager decides to transmit or halt the NP request transmission on a particular
transmit client interface (XALI 0/1/2) based on the number of split completions that can be expected in the
worst case, and free slots available in RADM header and data completion queues.
A few example scenarios that depict the completion queue operation are as follows:
Scenario 1: A 64 byte MemRd request at XALI0 complying with RCB rules can be completed two ways:
■ One Completion with 64bytes of data
■ Two Completions with Completion A data + Completion B data =64bytes (worst case scenario)
Considering the worst case, in this scenario the completion queue manager allows transmission of MemRd
request because the completion header queue has 2 free slots and the completion data queue has more than
64 bytes of space available, as described in Figure 3-87.
Synopsys, Inc.
Scenario 2: A 256 bytes MemRd request at XALI0 complying with RCB rules can be completed several
ways, the worst case would be five Completions with Completion A data + Completion B data +
Completion C data + Completion D data + Completion E data =256 bytes.
In this scenario, the completion queue manager does not allow transmission of MemRd request because
even though the completion header queue has 5 free slots, the completion data queue has space available for
248 bytes (62 DW) only, as described in Figure 3-88.
RCB = 64 bytes
RADM_CPLQ_DDP_VC0 = 256 bytes
RADM
Queues
CPLQ DATA VC0 CPLQ HDR VC0
RADM_CPLQ_DDP_VC0 RADM_CPLQ_HDP_VC0
... ...
4 4
3 3
2 2
1 1
Filled
0 0
positions
Scenario 3: In scenario 2, let us suppose that after some time the controller pops the header and data
completion queues. Now, enough space has been created in header and data completion queues to
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PCI Express SW Controller Databook Completion Queue Management
accommodate the halted MemRd completions, so the completion queue manager transmits the halted
MemRd request, as described in Figure 3-89.
Figure 3-89 Scenario 3: Transmission of Halted 256 Byte MemRd Request at XALI0
RCB = 64 bytes
MemReq = 256 bytes / 64 bytes = 4
Maximum expected CPL HDR = 256 bytes / 64 bytes + 1 (mis-alignment)
=4+1
=5
Limitations
■ This feature is supported only for PCIe devices. It is not supported for PCI-X devices.
■ This feature is supported only when ECRC stripping is enabled (CX_ECRC_STRIP_ENABLE =1).
■ For correct operation of the completion queue management feature the following filter rules must not
be changed from the default value of 0.
❑ CX_FLT_MASK_CPL_LEN_MATCH
❑ CX_FLT_MASK_CPL_TC_MATCH
❑ CX_FLT_MASK_CPL_TAGERR_MATCH
❑ CX_FLT_MASK_CPL_ECRC_DISCARD
❑ CX_FLT_MASK_DABORT_4UCPL
Completion Timeout
In the event of a Completion Timeout it is recommended that your application perform the following steps:
■ Disable completion queue management feature by setting the CPLQ_MANAGEMENT_ENABLE field of
MISC_CONTROL_1_OFF register to 0. This resets the completion queue counters to the initial value.
■ Wait until the completion queue is empty and there is no NP request pending in the LUT.
■ Enable completion queue management feature by setting the CPLQ_MANAGEMENT_ENABLE field of
MISC_CONTROL_1_OFF register to 1.
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PCI Express SW Controller Databook Header and Data Completion Queue Size Calculation
application can make. The completion header queue depth (CPLQ_HDP) and completion data queue depth
(CPLQ_DDP) are calculated as follows:
CPLQ_HDP = (CX_MAX_TAG + 1) * [CX_APP_RD_REQ_SIZE / RCB + 1]
CPLQ_DDP = [(CX_MAX_TAG + 1) * CX_APP_RD_REQ_SIZE / 4]/CX_NW
Where,
■ CX_MAX_TAG: Specifies the maximum number of simultaneous outbound PCIe non-posted requests in
total for all functions.
■ CX_APP_RD_REQ_SIZE: This parameter is used to set the depth of the receive completion data queue
(CX_CPLQ_DDP_VC*) when completions are in store-and-forward or cut-through modes, and comple-
tion credits are infinite. It is the maximum individual MRd size that your application (or AXI bridge
slave) makes.
■ RCB: Specifies the minimum Read Completion Boundary (RCB) of all CPLs with which the controller
inter-operates. For a root port this can be set to 128 bytes, all other components should assume an RCB
of 64 bytes unless they exist entirely within closed systems where the minimum RCB is known. This
parameter is used only to calculate the required size of the completion header queues when comple-
tion credits are infinite and the completion queues are not bypassed.
RCB (RC) = 128/64 bytes
RCB (no RC) = 64 bytes
■ CX_NW: Specifies the width of the datapath in dwords.
For example, for a configuration with CX_MAX_TAG = 255, CX_APP_RD_REQ_SIZE = 4096 bytes, RCB = 128
bytes, CX_NW = 256 bits, the completion queue header and completion queue data size per VC are calculated
as follows:
CPLQ_HDP = (255 + 1) * [4096 / 128 + 1] = 8448 (128 bits) = 135168 bytes
CPLQ_DDP = [(255 + 1) * 4096 / 4] / 8 = 32768 (256 bits) = 1048576 bytes
There is a relation between the number of tags and the latency of the PCIe link to optimize the design based
on the bandwidth expected. The higher the latency the higher the number of TAGs that can be used.
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4
Signal Interfaces
The descriptions for each I/O are given in the next chapter.
When you configure the controller in coreConsultant, you can access the I/O descriptions for
Attention your actual configuration at workspace/report/IO.html using the process described in the
“Creating Optional Views and Reports” section in the User Guide. This report comes from the
exact same source as the Databook but removes all the signals that are not in your actual
configuration.
RX_TLP is the number of TLPs processed per clock cycle and is also the number of receive queues per TLP
type per VC. It is 2 for 256-bit datapath configurations, and 1 for all other configurations.
This section describes any relevant timing protocols for the following signal interfaces.
■ “Transmit Interfaces (XALI0/1/2)” on page 279
■ “CCIX Transmit Interface (XALI_CCIX)” on page 286
■ “Receive Bypass Interface (RBYP)” on page 289
■ “Receive Request Interface (TRGT1)” on page 290
■ “CCIX Receive Request Interface (TRGT1_CCIX)” on page 293
■ “Data Bus Interface (DBI)” on page 296
■ “External Local Bus Interface (ELBI)” on page 298
■ “Message Signaled Interrupt (MSI) Interface” on page 300
■ “MSI-X Interface” on page 301
■ “Vendor Message Interface (VMI)” on page 305
■ “System Information Interface (SII)” on page 306
■ “PIPE Interface” on page 307
■ “PHY Register Bus Interface (PRBI)” on page 310
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PCI Express SW Controller Databook Transmit Interfaces (XALI0/1/2)
In the timing diagrams, the actual clock used to clock the interface might vary in low-power
Attention mode. In this case, you should use a different clock than the one indicated in the timing
diagram. For more information, see “Synchronous To Attribute” on page 55.
For more information on how to select these client interfaces, see the Configuration Guide
Hint
section in the Configuring the PCI Express controller chapter of the User Guide.
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■ To send a message through the transmit client interface, your application asserts the message code on
client0_tlp_byte_en, and the last two DWORDs of the header through
client0_tlp_addr[63:0], where client0_tlp_addr[63:32] is the third DWORD (bytes 8-11) of
the header. When there is data to send with the message, your application sends the data through
client0_tlp_data, as with other TLP data. For more information, see “Message Generation” on
page 153.
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PCI Express SW Controller Databook Transmit Client Transactions
core_clk
client0_tlp_hv
client_tlp_dv
xadm_client0_halt
client0_tlp_eot
client0_tlp_data[DW-1:0]
core_clk
client0_tlp_hv
client0_tlp_dv
xadm_client0_halt
client0_tlp_eot
client0_tlp_data[DW-1:0] W0 W1 W2 W3 W4
client0_tlp_*
MEM_WR
(TLP header signals)
core_clk
client0_tlp_hv
client0_tlp_dv
xadm_client0_halt
client0_tlp_eot
client0_tlp_dwen[NW-1:0] 0xF
client0_tlp_data[DW-1:0] W0
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core_clk
client0_tlp_hv
client0_tlp_dv
xadm_client0_halt
client0_tlp_eot
client0_tlp_dwen[NW-1:0] 0xF
client0_tlp_data[DW-1:0] W0 W1 W2 W3 W4
client0_tlp_* CPL
(TLP header signals )
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PCI Express SW Controller Databook Transmit Address Alignment
core_clk
client0_tlp_hv
client0_tlp_dv
xadm_client0_eot
client0_tlp_halt
client0_addr _align_en
For read requests, the client0_tlp_data bus has no requirements. Figure 4-95 shows example waveforms
for the transmission of four 3-byte memory write requests with incrementing byte addresses starting from
0x80000000 and ending at 0x80000003. Note that the first enabled byte is shifted up for each request with
increasing address. Also, when the address plus length crosses a DWORD boundary (third TLP in Figure
4-95), the byte length goes directly from four to eight.
You must not use address alignment for completions and must set clienti_addr_align_en
Note
=0. Your application must drive the correct byte address on clienti_tlp_addr so that the
completion lower address bits [6:0] are derived from the DWORD-aligned address and FBE of
the original request.
Address Alignment On
When address alignment is on for a packet, the client interface becomes more of a byte interface. The
formatting information that your application provides is as follows:
■ client0_tlp_addr: The address is the full byte address of the first enabled byte of the request. That
is, the request must be byte-aligned.
■ client0_tlp_byte_en: Should be 0x0, that is, not used for a packet with address alignment on.
■ client0_tlp_byte_len: Must be the full byte length of the request.
■ client0_tlp_data: The first enabled byte of the request must be on bits [7:0] of this data bus. The
controller up-shifts the data in the transmitted TLP based on the lower two bits of the byte address.
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core_clk
client0_tlp_hv
client0_tlp_dv
xadm_client0_eot
client0_tlp_halt
client0_addr _align_en
client0_tlp_byte_en[7:0] 0x00
Based on the address and byte length, the controller determines the FBE and LBE fields of the TLP. For read
requests, the client0_tlp_data signal has no requirements. For write requests, the controller determines
how many DWORDs of data payload is transmitted in the associated TLP. Figure 4-96 shows the same
sequence of memory write requests as Figure 4-95, except that address alignment is on. The data vector does
not change based on the byte address. The controller never generates a TLP with non-contiguous LBE/FBE.
When address alignment is enabled, application logic must make sure that the transmitted
Note
TLP sent has a length value less than the maximum payload supported. For example, when
maximum payload is set to 128 bytes (32 DWORDs) and your application sends a request of
128 bytes but with a non-DWORD-aligned address the controller sends the request with a
DWORD-aligned address and with a length of 33 DWORDs. This is detected as a malformed
TLP at the destination.
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PCI Express SW Controller Databook Transmit Address Alignment
Figure 4-97 Client0 Transaction: Address Alignment and Data Bus Cycles
TLP1 TLP2 TLP3 TLP4
core_clk
client0_tlp_hv
client0_tlp_dv
xadm_client0_eot
client0_tlp_halt
client0_addr _align_en
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CORE?CLK
CCIX?TLP?HV
CCIX?TLP?DV
CCIX?TLP?EOT
CCIX?TLP?BAD?EOT
CFG?CCIX?OPT?TLP?EN
XADM?CCIX?TLP?HALT
For PCIe compatible TLP format the complete header bus is used (ccix_tlp_hdr[127:0]) to transmit the
header information.
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PCI Express SW Controller Databook CCIX TLP Header Fields and ccix_tlp_hdr Mapping
CORE?CLK
CCIX?TLP?HV
CCIX?TLP?HDR;= 2ESERVED?NOT?USED?FOR?OPTIMIZED?4,0?FORMAT
CCIX?TLP?DV
CCIX?TLP?EOT
CCIX?TLP?BAD?EOT
CFG?CCIX?OPT?TLP?EN
XADM?CCIX?TLP?HALT
For optimized CCIX TLP format only 32 bits of the header bus are used (ccix_tlp_hdr[31:0]) to transmit
the header information. The remaining header bits are reserved.
Figure 4-100 XALI_CCIX Data Bus Usage Example for 128-bit Datapath
CORE?CLK
CCIX?TLP?DV
CCIX?TLP?EOT
XADM?CCIX?TLP?HALT
Clock cycle one and clock cycle five in Figure 4-100 illustrate how the ccix_tlp_data bus is expected to be
used when the amount of data to transmit in one clock cycle is not enough to fill the complete
ccix_tlp_data bus. For both PCIe compatible TLP format and optimized CCIX TLP format the same
behavior applies.
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Table 4-80 Mapping Between CCIX TLP Header Fields and ccix_tlp_hdr
PCIe Compatible TLP Format Optimized CCIX TLP Format ccix_tlp_hdr bits
Vendor ID 95 - 80
Device Number 79 - 75
Function Number 74 - 72
NOT USED
Bus Number 71 - 64
Message Code 63 - 56
TAG 55 - 48
Requester ID 47 - 32
TD 23
EP 22
Attr 21 -20
Length[9] 17
Length[8] 16
R 15
TC TC 14 - 12
R 11
Attr[2] 10
CCIX DW0 Content
R 9
TH 8
0 7
FMT Type 6
5
CCIX DW0 Content
Type 4-0
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PCI Express SW Controller Databook Receive Bypass Interface (RBYP)
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In the timing diagrams, the actual clock used to clock the interface might vary in low-power
Attention mode. In this case, you should use a different clock than the one indicated in the timing
diagram. For more information, see “Synchronous To Attribute” on page 55.
core_clk
radm_trgt1_hv
radm_trgt1_dv
radm_trgt1_data[ ] W0 W1 W2 W3 W4 W5
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PCI Express SW Controller Databook TRGT1 Packet Grant and Halt
radm_trgt1_hv
radm_trgt1_dv
radm_trgt1_eot
radm_trgt1_ecrc_err
radm_trgt1_tlp_abort
radm_trgt1_data[ ] W0 W1 W2 W3 W4 W5 W6
radm_trgt1_* Header
(TLP header signals) signals
radm_trgt1_dwen[3:0] 0xF
Figure 4-103 TRGT1 Transaction: MWr Request TLP with Wait States
core_clk
radm_trgt 1_hv
radm_trgt 1_dv
radm _trgt1_eot
trgt1_radm _halt
radm_trgt 1_data[ ] W0 W1 W2 W3 W4
radm_trgt 1_*
Header signals
(TLP header signals )
radm_trgt1_dwen[3:0] 0xF
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packet type in the receive queue and not unload it into the output pipe. You must implement a
counter/tracker in your application logic for each TLP type using the radm_grant_tlp_type[2:0]
outputs. For example, design a counter that increments on radm_grant_tlp_type[2:0]. When
radm_trgt1_hv of the correct type of transaction is asserted, decrement the counter. When this counter
reaches the number of free TLP locations in your applications buffer, assert trgt1_radm_pkt_halt.
Figure 4-104 Receive Queue and Output Queue Halting (Single-VC Design)
optional RBYP
Receive Queues
CPL
F I F O Output Pipe
(3-4 cycles )
P
F I F O TRGT1
NP trgt1_radm_halt
F I F O (global interface halt )
trgt1_radm_pkt_halt[2:0]
Order FIFO Order Controller Packet Halt/Unload
(controls the unloading 0: P Tracker/Counter Per-
of each receive queue 1: NP TLP-Type and Per-Vc
based on ordering 2: CPL (Implemented in your
rules) application logic)
radm_grant _tlp_type[2:0]
The radm_grant_tlp_type[2:0] signals are pulse outputs indicating that a transaction has been granted
to dequeue from the receive queue. The level input signal trgt1_radm_pkt_halt[2:0] acts like a flow
control On/Off. It alone does not control the exact number of transactions that the controller delivers,
because of the pipelines inside the output pipe. The signal radm_grant_tlp_type[2:0] is a clocked
output. Therefore you must combinatorially assert the signaltrgt1_radm_pkt_halt[2:0] to stop extra
transactions from being dequeued from the receive-queue. There is a minimum delay of one clock cycle
from the de-assertion of trgt1_radm_pkt_halt[2:0] to the assertion of radm_grant_tlp_type[2:0].
core_clk
trgt1_radm_pkt_halt[0]
radm_grant_tlp_type[0] 1 2 3 4
When you have used all the entries in the Target LUT, the RADM automatically halts the TRGT1 interface.
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PCI Express SW Controller Databook CCIX Receive Request Interface (TRGT1_CCIX)
CORE?CLK
RADM?CCIX?HV
RADM?CCIX?DV
RADM?CCIX?DATA;$7 = DATA DATA DATA DATA DATA DATA DATA DATA DATA
RADM?CCIX?DWEN;.7 = [.[gBg]] [.7[gBg]] [.[gBg]] [.[gBg]] [.7[gBg]] [.[gBg]] [.[gBg]] [.[gBg]] [.[gBg]]
RADM?CCIX?EOT
RADM?CCIX?TLP?ABORT
RADM?CCIX?DLLP?ABORT
CFG?CCIX?OPT?TLP?EN
CCIX?RADM?HALT
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CORE?CLK
RADM?CCIX?HV
RADM?CCIX?HDR;= 2ESERVED?NOT?USED?FOR?OPTIMIZED?4,0?FORMAT
RADM?CCIX?DV
RADM?CCIX?DATA;$7 = DATA DATA DATA DATA DATA DATA DATA DATA DATA
RADM?CCIX?DWEN;.7 = [.[gBg]] [.7[gBg]] [.[gBg]] [.[gBg]] [.7[gBg]] [.[gBg]] [.[gBg]] [.[gBg]] [.[gBg]]
RADM?CCIX?EOT
RADM?CCIX?TLP?ABORT
RADM?CCIX?DLLP?ABORT
CFG?CCIX?OPT?TLP?EN
CCIX?RADM?HALT
Figure 4-108 CCIX_TRGT1 Data bus Usage Example for 128-bit Datapath
CORE?CLK
RADM?CCIX?DV
RADM?CCIX?EOT
CCIX?RADM?HALT
Clock cycle one and clock cycle five in Figure 4-108 illustrate how the radm_ccix_data bus is expected to
be used when the amount of data received in one clock cycle is not enough to fill the complete
radm_ccix_data bus. For both PCIe compatible TLP format and optimized CCIX TLP format the same
behavior applies.
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PCI Express SW Controller Databook CCIX TLP Header Fields and radm_ccix_hdr Mapping
Table 4-81 Mapping Between CCIX TLP Header Fields and radm_ccix_hdr
PCIe Compatible TLP Format Optimized CCIX TLP Format radm_ccix_hdr bits
Vendor ID 95 - 80
Device Number 79 - 75
Function Number 74 - 72
NOT USED
Bus Number 71 - 64
Message Code 63 - 56
TAG 55 - 48
Requester ID 47 - 32
TD 23
EP 22
Attr 21 -20
Length[9] 17
Length[8] 16
R 15
TC TC 14 - 12
R 11
Attr[2] 10
CCIX DW0 Content
R 9
TH 8
0 7
FMT Type 6
5
CCIX DW0 Content
Type 4-0
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In the timing diagrams, the actual clock used to clock the interface might vary in low-power
Attention mode. In this case, you should use a different clock than the one indicated in the timing
diagram. For more information, see “Synchronous To Attribute” on page 55.
For more information, see “Data Bus Interface (DBI) Access” on page 111. Limitations are detailed in
“Access Limitations” on page 113.
core_clk
dbi_cs
lbc_dbi_ack
dbi_din[31:0] DW 0 DW 1
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PCI Express SW Controller Databook DBI Protocol Transactions
core_clk
dbi_cs
lbc_dbi_ack
dbi_wr[3:0] 0x0
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PCI Express SW Controller Databook ELBI Protocol Transactions
core_clk
lbc_ext_cs
ext_lbc_ack
lbc_ext_dout [31:0] DW 0 DW 1
lbc_ext_rom_access/
lbc_ext_io_access
core_clk
lbc_ext_cs
ext_lbc_ ack
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core_clk
ven_msi_req
ven_msi_grant
ven_msi_tc[2:0] 3'b000
cfg_msi_en
cfg_msix_en
The internal MSI arbiter performs arbitration for MSI requests from different functions. ven_msi_grant is
a one-cycle pulse acknowledging ven_msi_req. ven_msi_req is not required to be de-asserted before
reasserting again. When ven_msi_req remains asserted, the controller generates another MSI.
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PCI Express SW Controller Databook MSI-X Interface
core_clk
ven_msi_req
ven_msi_grant
ven_msi_tc[2:0] 3'b000
cfg_msix_en
cfg_msi_en
As with MSI, the internal arbiter performs arbitration for MSI-X requests from different functions.
ven_msi_grant is a one-cycle pulse, after which the controller does not wait for ven_msi_req to be
de-asserted. When ven_msi_req remains asserted, the controller generates another MSI-X.
4.9.3 Relationship Between Configuration Parameters, Registers, and I/O for MSI-X and MSI
Figure 4-115 and Figure 4-116 show the configuration parameters that the controller uses to set the default
values of the MSI-X and MSI Capability Registers. Figure 4-115 and Figure 4-118 show which configuration
parameters are used to set the default of the MSI-X and MSI Capability Registers. They also show how the
controller makes the contents of the Capability Registers available on I/O signals. The contents of the
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Read-Only (RO) fields of the VF MSI-X Capability registers are not available as I/O, because the values of
these registers are the same for all VFs, and these values are set using configuration parameters. There is one
exception, which is the Table Size field of the Control Register.
PF Configuration Parameters
*1
* NF
A set of values
for EACH PF.
* NF * NVF
PF Capability Register I/O MSI-X Generation I/O (PF and VF) VF Capability Register I/O
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PCI Express SW Controller Databook Relationship Between Configuration Parameters, Registers, and I/O for MSI-X and
*1
* NF * NVF
PF Capability Register /IO MSI Generation I/O (PF and VF) VF Capability Register /IO
These I/O are also used for MSI-X
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PCI Express SW Controller Databook Vendor Message Interface (VMI)
In the timing diagrams, the actual clock used to clock the interface might vary in low-power
Attention mode. In this case, you should use a different clock than the one indicated in the timing
diagram. For more information, see “Synchronous To Attribute” on page 55.
core_clk
ven_msg_req
ven_msg_grant
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0 S/R
1
SW_up <-> 1
device_type[3:0]
SW_down To Configuration
Registers and
Core Logic
smlh_crosslink _active
CX_CROSSLINK_ENABLE
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PCI Express SW Controller Databook PIPE Interface
In addition to the PIPE-compliant interface signals, the controller provides two 32-bit sideband buses
(cfg_phy_control and phy_cfg_status) that connect to controller configuration registers. You can
optionally use the sideband buses for additional PHY control and/or status monitoring.
When the automatically derived CX_FREQ_STEP_DOWN_EN parameter is ‘1’, then a module called
freq_step (workspace/src/common/freq_step.v) is placed between the PHYs PIPE and the cores
PIPE. This module steps up/down the signals to/from the PIPE interface. For more information, see
“Frequency Step Module (CX_FREQ_STEP_EN =1)” on page 38.
clk
mac_phy_txelecidle
mac_phy_txdatavalid
32 blocks
mac_phy_txstartblock
mac_phy_txsyncheader[1:0] V V V V V V
mac_phy_txdata[63:32] 1 3 1 3 1 3 1 3 1 3 1 3
mac_phy_txdata[31:0] 0 2 0 2 0 2 0 2 0 2 0 2
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Figure 4-122 describes the 64-bit PIPE transmit operation when CX_PIPERX_MULTI_BLOCK =0.
■ The controller only accepts 64-bit-aligned SKP OS
■ rxdatavalid can be de-asserted at anytime
■ Possible SKP OS length: 64/128/192 bit
phy_mac_rxvalid
phy_mac_rxdatavalid
phy_mac_rxstartblock 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0
phy_mac_rxsyncheader[1:0] V V V V V V V V V V V V
Figure 4-122 describes the 64-bit PIPE transmit operation when CX_PIPERX_MULTI_BLOCK =1.
■ Extend bit width of rxstartblock and rxsyncheader
❑ phy_mac_rxstartblock 2-bit (per-lane)
❑ phy_mac_rxsyncheader 4-bit (per-lane)
■ rxdatavalid can be de-asserted at anytime
■ Possible SKP OS length: 32/64/96/128/160/192/224 bit
phy_mac_rxvalid
phy_mac_rxdatavalid
phy_mac_rxstartblock[1] 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0
phy_mac_rxstartblock[0] 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0
phy_mac_rxsyncheader[3:2] V V V V V V
phy_mac_rxsyncheader[1:0] V V V V V V
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PCI Express SW Controller Databook PIPE 5.1.1
SerDes architecture and PCLK as PHY input features of the PIPE Specification for PCI
Note
Express, Version 5.1.1 are not supported in this release.
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■ The PHY can be controlled through PRBI only when PHY’s Control Register (CR) Parallel
Note Interface Select signal (cr_para_sel) is set to 1.
■ This feature does not work during L1.CPM and L1 substate, if CX_PHY_ENHANCED_PM_EN
=1.
■ This feature does not work during L2.
The controller's PHY Viewport (PRBI) to PHY registers can have high access latency. If your
Attention application needs low latency to initialize Synopsys PHY registers or SRAM, then PRBI should
not be used. Instead, you should design a direct interface to the PHY's SRAM or CR Bus.
PRBI is recommended only for PHY debug.
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PCI Express SW Controller Databook PRBI Protocol Transactions
phy_reg_clk_g
phy_cr_para_ack
phy_cr_para_wr_en
>= 1*Tcr
Maximum (6+2N)*Tref
phy_reg_clk_g
phy_cr_para_ack
phy_cr_para_rd_en
>= 1*Tcr
Maximum (6+2N)*Tref + 5*Tcr
phy_cr_para_rd_en is asserted for a single cycle. When asserted, the data at address
phy_cr_para_addr[15:0] is read and provided on phy_cr_para_rd_data[15:0]. Assertion of
phy_cr_para_ack indicates completion of read access.
Synopsys, Inc.
phy_reg_clk_g
phy_cr_para_addr[15:0] valid
phy_cr_para_wr_data[15:0] valid
>=1*Tcr
Maximum (6+2N)*Tref
phy_cr_para_wr_en[3:0] is asserted for a single cycle. The value 0001b indicates write access to PHY0
sub-block of the PHY. The controller waits for response from PHY0 sub-block.
phy_reg_clk_g
phy_cr_para _rd_data[16*4-1:16]
>=1*Tcr
phy_cr_para_rd_en[3:0] is asserted for a single cycle. The value 0001b indicates read access to PHY0
sub-block of the PHY. Data at address phy_cr_para_addr[15:0] is read and provided on
phy_cr_para_rd_data[15:0]. The controller waits for response from PHY0 sub-block.
Figure 4-128 Write Operation: Broadcast to all Sub-blocks of a PHY Containing 4 Sub-blocks
phy_reg_clk_g
phy_cr_para_wr_en[3:0] is asserted for a single cycle. Value 1111b indicates write access to all the four
sub-blocks of the PHY. The controller waits for response from all the four sub-blocks.
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PCI Express SW Controller Databook Signal Descriptions
5
Signal Descriptions
This chapter details all possible I/O signals in the controller. For configurable IP titles, your actual
configuration might not contain all of these signals.
Inputs are on the left of the signal diagrams; outputs are on the right.
Attention: For configurable IP titles, do not use this document to determine the exact I/O footprint of the
controller. It is for reference purposes only.
When you configure the controller in coreConsultant, you must access the I/O signals for your actual
configuration at workspace/report/IO.html or workspace/report/IO.xml after you have completed the
report creation activity. That report comes from the exact same source as this chapter but removes all the
I/O signals that are not in your actual configuration. This does not apply to non-configurable IP titles. In
addition, all parameter expressions are evaluated to actual values. Therefore, the widths might change
depending on your actual configuration.
Some expressions might refer to TCL functions or procedures (sometimes identified as <functionof>) that
coreConsultant uses to make calculations. The exact formula used by these TCL functions is not provided in
this chapter. However, when you configure the controller in coreConsultant, all TCL functions and
parameters are evaluated completely; and the resulting values are displayed where appropriate in the
coreConsultant GUI reports.
In addition to describing the function of each signal, the signal descriptions in this chapter include the
following information:
■ Active State: Indicates whether the signal is active high or active low. When a signal is not intended
to be used in a particular application, then this signal needs to be tied or driven to the inactive state
(opposite of the active state).
■ Registered: Indicates whether or not the signal is registered directly inside the IP boundary without
intervening logic (excluding simple buffers). A value of No does not imply that the signal is not
synchronous, only that there is some combinatorial logic between the signal's origin or destination
register and the boundary of the controller. A value of N/A indicates that this information is not
provided for this IP title.
■ Synchronous to: Indicates which clocks in the IP sample this input (drive for an output) when consid-
ering all possible configurations. A particular configuration might not have all of the clocks listed. This
clock might not be the same as the clock that your application logic should use to clock (sample/drive)
this pin. For more details, consult the clock section in the databook.
■ Exists: Name of configuration parameter that populates this signal in your configuration.
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■ Validated by: Assertion or de-assertion of signals that validates the signal being described.
Synchronous To
The Synchronous To: attribute indicates which controller clocks sample an input (or drive an output) when
considering all possible configurations. In many cases an output has components driven (or an input
sampled) by multiple clocks. The attribute lists all clocks which drive or sample for all possible
configurations. It is an automatically generated list accumulated over all configurations. Your particular
configuration might not have all of the clocks listed.
■ When there is only one clock in the list, this clock is normally but not always the same as the clock that
your application logic should use to clock (sample/drive) this pin.
■ When there is more than one clock in the list:
❑ A {} is placed around the clock which is used in generating the synthesis in/out timing delay
constraints and which is also used in Spyglass boundary CDC checking.
❑ In most cases, this is also the clock that you should use to drive/sample the pin in normal opera-
tional (non low-power) mode.
❑ If more than one clock has a {}, that clock is configuration-dependent and you should look in your
SDC file (as explained in the Synthesizing to a Device Outside of coreConsultantsection of the User
Guide) to see which one is relevant. Normally only applies to the PIPE outputs which are clocked
on pipe_clk or core_clk depending on CX_FREQ_STEP_EN.
■ When you see perbitclockin the clock list, it indicates that there is a different clock for some of the bits
in the multi-bit port, and/or that some of the bits in a multi-bit port falls into the various categories as
defined next by None.
■ When you see None_asin the clock list, it indicates the following and is equivalent/mapped to core_clk
for CDC synthesis.
❑ Asynchronous reset with synchronous de-assertion.
■ When you see Nonein the clock list, it indicates any of the following and is equivalent/mapped to
core_clk for CDC and synthesis.
❑ Direct or combinatorial feed-through.
❑ Gated-off (that is, unclocked) inputs.
❑ Unused inputs.
❑ Hard-coded outputs.
❑ Asynchronous outputs.
❑ Asynchronous resets.
■ For asynchronous inputs (excluding asynchronous resets), CDC synchronizers are added in the RTL,
and are detailed in Port Clocking and Input Synchonizersin the Databook. Asynchronous inputs are indi-
cated with Synchronous To: myclock, where myclock is the synchronizer clock.
■ Asynchronous outputs are indicated with Synchronous To: None.
For more information on Generalized interface clocking guidelines qualifying the synchronous to: attribute,
see 2.3.2 General Clock Relationshipsin Clock Requirementssection of the Databook.
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PCI Express SW Controller Databook Signal Descriptions
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PCI Express SW Controller Databook Distributed Translation Interface AXI4-Stream Master Signals
tready_dti_up - - tvalid_dti_dn
- tdata_dti_dn
- tkeep_dti_dn
- tlast_dti_dn
- tprot_dti_dn
tready_dti_up I tready_dti_up indicates that the slave can accept a transfer in the
current cycle.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
tdata_dti_dn[(DTIM_DATA_WD-1):0] O tdata_dti_dn is the primary payload that is used to provide the data that
is passing across the interface. The width of the data payload is an
integer number of bytes.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: tvalid_dti_dn
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tkeep_dti_dn[(DTIM_NUM_BYTES_PER_ O tkeep_dti_dn is the byte qualifier that indicates whether the content of
BEAT-1):0] the associated byte of tdata_dti_dn is processed as part of the data
stream. Associated bytes that have the tkeep_dti_dn byte qualifier
deasserted are null bytes and can be removed from the data stream.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: tvalid_dti_dn
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PCI Express SW Controller Databook Distributed Translation Interface AXI4-Stream Slave Signals
tvalid_dti_up - - tready_dti_dn
tdata_dti_up -
tkeep_dti_up -
tlast_dti_up -
tprot_dti_up -
tready_dti_dn O tready_dti_dn indicates that the slave can accept a transfer in the
current cycle.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
tdata_dti_up[(DTIM_DATA_WD-1):0] I tdata_dti_up is the primary payload that is used to provide the data that
is passing across the interface. The width of the data payload is an
integer number of bytes.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: tvalid_dti_up
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tkeep_dti_up[(DTIM_NUM_BYTES_PER_ I tkeep_dti_up is the byte qualifier that indicates whether the content of
BEAT-1):0] the associated byte of tdata_dti_up is processed as part of the data
stream. Associated bytes that have the tkeep_dti_up byte qualifier
deasserted are null bytes and can be removed from the data stream.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: tvalid_dti_up
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PCI Express SW Controller Databook Distributed Translation Interface Interrupt Signals
- dtim_int
- dtim_err_tresp_oas_int
- dtim_err_tresp_uid_int
- dtim_err_icpl_uc_int
- dtim_err_ireq_opertn_int
- dtim_err_ireq_to_int
dtim_int O Indicates that the Distributed Translation Interface Master (DTIM) has
detected one or more errors. This is a level interrupt. For more details,
refer to the DTI "Interrupts and Error Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.
dtim_err_tresp_oas_int O Indicates that the Distributed Translation Interface Master (DTIM) has
detected a DTI-ATS translation response output address size mismatch
error. This is a level interrupt. For more details, refer to the DTI
"Interrupts and Error Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.
dtim_err_tresp_uid_int O Indicates that the Distributed Translation Interface Master (DTIM) has
detected an unexpected DTI-ATS translation response. The translation
response translation ID can not be associated with an outstanding
DTI-ATS translation request. This is a level interrupt. For more details,
refer to the DTI "Interrupts and Error Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.
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dtim_err_icpl_uc_int O Indicates that the Distributed Translation Interface Master (DTIM) has
detected an unexpected PCIe invalidate completion error. The PCIe
invalidate completion tag can not be associated with an outstanding
DTI-ATS invalidate request. This is a level interrupt. For more details,
refer to the DTI "Interrupts and Error Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.
dtim_err_ireq_opertn_int O Indicates that the Distributed Translation Interface Master (DTIM) has
detected an illegal DTI-ATS invalidate request operation code. This is a
level interrupt. For more details, refer to the DTI "Interrupts and Error
Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.
dtim_err_ireq_to_int O Indicates that the Distributed Translation Interface Master (DTIM) has
timed out one or more DTI-ATS invalidate requests. The Endpoint
Translation Cache (ATC) has not returned one or more invalidate
completions within an expected timeframe. The outstanding invalidate
completion(s) are not expected to be received at this point in time. This
is a level interrupt. For more details, refer to the DTI "Interrupts and
Error Handling" section of the Databook.
Exists: CC_DTIM_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal.
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PCI Express SW Controller Databook Distributed Translation Interface Invalidate Request Timeout Signals
- dtim_ireq_timeout
- dtim_ireq_timeout_sid
- dtim_ireq_timeout_itag
dtim_ireq_timeout_sid[(DTIM_ATS_SID_L O The lower 16 bits of the DTI-ATS Stream ID of the timed out Invalidate
WR_WD-1):0] Request. These bits represent the Bus, Device and Function Numbers
(BDF) of the target device finction.
Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: dtim_ireq_timeout
dtim_ireq_timeout_itag[(PCIE_ATS_INV_ O The PCIe Invalidate Request ITAG of the timed out Invalidate Request.
REQ_ITAG_WD-1):0] Exists: CC_DTIM_ENABLE
Synchronous To: mstr_aclk_ug
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: dtim_ireq_timeout
Synopsys, Inc.
cxsrxvalid - - cxsrxcrdgnt
cxsrxdata - - cxsrxactiveack
cxsrxcntl - - cxsrxdeacthint
cxsrxcrdrtn - - cxsrxcrdgntchk
cxsrxactivereq -
cxsrxdatachk -
cxsrxcntlchk -
cxsrxvalidchk -
cxsrxcrdrtnchk -
cxsrxcntl[(CXSCNTLWIDTH-1):0] I CXS Receiver control bus; contains information on packet start, end,
and errors.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: aux_clk_g,{core_clk}
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxsrxvalid is asserted
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PCI Express SW Controller Databook CXS Rx Interface Signals
cxsrxcrdgnt O CXS Receiver credit grant; grants a single credit for the Transmitter.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: aux_clk_g,{core_clk}
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: cxsrxactiveack is asserted
cxsrxcrdrtn I CXS Receiver credit return; returns a single credit to the Receiver.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: cxsrxvalid is not asserted
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PCI Express SW Controller Databook CXS Tx Interface Signals
cxstxcrdgnt - - cxstxvalid
cxstxactiveack - - cxstxdata
cxstxdeacthint - - cxstxcntl
cxstxcrdgntchk - - cxstxcrdrtn
- cxstxactivereq
- cxstxdatachk
- cxstxcntlchk
- cxstxvalidchk
- cxstxcrdrtnchk
cxstxcntl[(CXSCNTLWIDTH-1):0] O CXS Transmitter control bus, contains information on packet start, end,
and errors.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: N/A
Validated by: cxstxvalid is asserted
Synopsys, Inc.
cxstxcrdgnt I CXS Transmitter credit grant; grants a single credit for the transmitter.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: No
Power Domain: PD_VAUX
Active State: High
Validated by: cxstxactiveack is asserted
cxstxcrdrtn O CXS Transmitter credit return; returns a single credit to the receiver.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: cxstxvalid is not asserted
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PCI Express SW Controller Databook CXS Tx Interface Signals
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client0_addr_align_en - - xadm_client0_halt
client0_tlp_byte_en -
client0_remote_req_id -
client0_cpl_byte_cnt -
client0_tlp_tc -
client0_tlp_attr -
client0_cpl_status -
client0_cpl_bcm -
client0_tlp_dv -
client0_tlp_eot -
client0_tlp_bad_eot -
client0_tlp_hv -
client0_tlp_fmt -
client0_tlp_type -
client0_tlp_td -
client0_tlp_ep -
client0_tlp_byte_len -
client0_tlp_addr -
client0_hdr_prot -
client0_tlp_tid -
client0_tlp_data -
client0_tlp_func_num -
client0_tlp_prfx -
client0_tlp_atu_bypass -
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PCI Express SW Controller Databook XALI0 Interface Signals
client0_tlp_byte_en[7:0] I Byte enables for the first and last dword of the TLP:
■ [3:0]: Byte enables for the first dword
■ [7:4]: Byte enables for the last dword
A TLP can have 'holes' between bytes when the TLP is less than eight
bytes (two dwords) long, according to the PCI Express Specification(not
all valid bytes need to be contiguous). However, a TLP is not allowed to
have holes between bytes when the TLP is more than eight bytes. Not
used (set to 0x0) when 'Transmit Address Alignment' is
(client0_addr_align_en =1 and GLOB_ADDR_ALIGN_EN =1). When
sending a message, your application asserts the message code onto
these signals.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted. Not valid when
client0_addr_align_en is asserted.
client0_cpl_byte_cnt[11:0] I The value to be used for the Byte Count field of a memory read
completion TLP. The value client0_cpl_byte_cnt indicates the number of
bytes remaining to be delivered for the request, as defined in the PCI
Express Specification.
■ 001h: 1 byte
■ FFFh: 4095 bytes
■ 000h: 4096 bytes
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted. Only used when XALI0 is
connected to a completer.
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client0_tlp_tc[2:0] I The value to be used for the Traffic Class (TC) field of the TLP header
(000b'111b) on XALI0.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
client0_cpl_status[2:0] I The value to be used in the completion Status field of a completion TLP
header on XALI0:
■ 000b: Successful completion
■ 001b: Unsupported request
■ 010b: Configuration request retry status
■ 100b: Completer abort
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted. Only used when XALI0 is
connected to a completer.
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PCI Express SW Controller Databook XALI0 Interface Signals
client0_tlp_dv I Indicates that the TLP payload data client0_tlp_data is valid. Your
application must not assert client0_tlp_dv for TLPs that do not include a
payload, such as memory read requests. Your application must present
the first payload data the same cycle with the TLP header.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
client0_tlp_eot I Indicates the end of TLP payload data for a TLP that includes a payload.
For a TLP that does not include a payload (such as a memory read
request), your application must assert and de-assert client0_tlp_eot at
the same time as client0_tlp_hv. You must not assert it at any other time.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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client0_tlp_bad_eot I Indicates that the current TLP must be nullified. To nullify a TLP, your
application must assert client0_tlp_bad_eot in the same cycle as
client_tlp_eot. When client0_tlp_bad_eot is asserted, the controller
nullifies the TLP (inverts the LCRC and inserts EDB as the final framing
symbol in the transmitted TLP). Your application can use
client0_tlp_bad_eot to nullify a TLP because of a known error condition,
or to abort the current transaction when the current transaction is being
blocked (for example, due to lack of FC credits):
■ To cancel a request that has not been granted (xadm_client0_halt
has never been de-asserted for the transfer), the CLIENT PULL-
BACK feature from coreConsultant must be selected. In addition, the
following signals must be driven as follows. Assert
client0_tlp_bad_eot and client0_tlp_eot for one clock cycle while
xadm_client0_halt is asserted (indicating that the request has not
been granted), then de-assert client0_tlp_hv, client0_tlp_dv,
client0_tlp_bad_eot, and client0_tlp_eot to terminate the request.
Without the CLIENT_PULLBACK feature, your application has to
send the full packet and mark the EOT and BAD_EOT at the end.
With the CLIENT_PULLBACK feature, your application can mark
EOT and BAD_EOT when it realizes that it needs to nullify the TLP,
without having to present the full packet.
■ To cancel a request that is in progress (xadm_client0_halt has been
asserted for the transfer), assert client0_tlp_bad_eot and
client0_tlp_eot for one clock cycle while xadm_client0_halt is
de-asserted (indicating that the request has been granted), then
de-assert client0_tlp_hv, client0_tlp_dv, client0_tlp_bad_eot, and
client0_tlp_eot to terminate the request. In this case, the controller
nullifies the TLP as described above.
■ When the TLP is a one-cycle request (client0_tlp_hv and
client0_tlp_eot asserted in the same cycle) and client0_tlp_bad_eot
is also asserted, this request is ignored. Sending a nullified TLP is
not very useful because the link partner has to ignore it anyway. Your
application should realize that this request is nullified (in this case
ignored) and de-assert client0_tlp_hv and client0_tlp_eot while
keeping client0_tlp_bad_eot asserted.
■ Nullify Atomic Ops TLP is not supported.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_eot is asserted
client0_tlp_hv I Indicates that the TLP header data the TLP header ports is valid. The
header data must remain valid until client0_tlp_hv is de-asserted.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk,aux_clk_g,radm_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook XALI0 Interface Signals
client0_tlp_fmt[1:0] I The value to be used for the Format field of the TLP header on XALI0:
■ 00b: 3 dword header, no data
■ 01b: 4 dword header, no data
■ 10b: 3 dword header, with data
■ 11b: 4 dword header, with data
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
client0_tlp_type[4:0] I The value to be used for the Type field of the client0 TLP header, as
defined in the PCI Express Specification.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
client0_tlp_td I TLP Digest bit on XALI0. It is expected that the ECRC is already
present, and the controller forwards it unchanged. You should set this
input to 1.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
client0_tlp_ep I When asserted, the controller sets the Poisoned TLP (EP) bit in the TLP
header on XALI0.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
Synopsys, Inc.
client0_tlp_byte_len[12:0] I The number of bytes in the TLP Payload (not including ECRC). The
value should be in the range 0x0000 (0) to 0x1000 (4096)
When 'Transmit Address Alignment' is (client0_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), this must be the full byte length of the
request. When transmit alignment is off (client0_addr_align_en=0), bits
[1:0] must be set to '00'. The byte length value must be rounded up to
the next dword boundary. For example, when the request is five bytes
long, the value of bits [12:0] must be eight.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
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PCI Express SW Controller Databook XALI0 Interface Signals
client0_tlp_addr[63:0] I The Address field for the TLP header. The TLP address can be 64 or 32
bits. When sending completions, the controller uses
client0_tlp_addr[6:0] for the Lower Address field of the completion TLP.
The bits in this address bus map directly to the address bits in the TLP
header. The third and fourth dwords of the header are mapped as
follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. The third dword
(bytes 8-11) =client0_tlp_addr[31:0]. Therefore, bits [7:0] are
mapped to byte 11 which is the lowest eight bits of the TLP header
address. For more details, see the 'Endianness' advanced informa-
tion chapter.
■ MEM (64-bit) / MSG have a 4-dword header. The third dword (bytes
8-11) =client0_tlp_addr[63:32]. The fourth dword (bytes 12-15)
=client0_tlp_addr[31:0]. Therefore, bits [7:0] are mapped to byte 15
which is the lowest eight bits of the TLP header address. For more
details, see the 'Endianness' advanced information chapter.
When sending a configuration request (DSP), client0_tlp_addr must
contain the following information:
■ [31:24]: Bus Number
■ [23:19]: Device Number
■ [18:16]: Function Number
■ [11:8]: Extended Register Number
■ [7:2]: Register Number
The base width of client0_tlp_addr is 64 bits. When 'Transmit Address
Alignment' is (client0_addr_align_en =1 and GLOB_ADDR_ALIGN_EN
=1), this address is the full byte address of the first enabled byte of the
request. That is, the address is byte-aligned. When transmit alignment
is off (client0_addr_align_en=0), bits [1:0] must be '00', that is, the
address must be dword-aligned.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
Synopsys, Inc.
client0_hdr_prot[(CLIENT_HDR_PROT_W I ECC or parity bits (protection code) for the XALI0 header. Your
D-1):0] application must calculate the protection code over all of the XALI0
header inputs in this order: client0_tlp_th, client0_tlp_st, client0_tlp_ph,
client0_tlp_ln, client0_tlp_func_num, client0_tlp_attr,
client0_addr_align_en, client0_tlp_byte_en, client0_remote_req_id,
client0_cpl_status, client0_cpl_bcm, client0_cpl_byte_cnt,
client0_tlp_tid, client0_tlp_byte_len, client0_tlp_ep, client0_tlp_td,
client0_tlp_tc, client0_tlp_type, client0_tlp_fmt, client0_tlp_addr[63:0].
Exists: (!(AMBA_INTERFACE!=0)) && (((CX_RASDP==0)? 0: 1))
Synchronous To: core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
client0_tlp_tid[(TAG_SIZE-1):0] I Tag field for the TLP header. Your application must provide a valid Tag
client0_tlp_tid for all posted and non-posted requests. The value of the
CX_MAX_TAG configuration option determines the maximum number of
outstanding Client requests. Your application is expected to manage the
Tag for every posted and non-posted request. For completions, the
client0_tlp_tid value must be the Tag from the corresponding request.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
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PCI Express SW Controller Databook XALI0 Interface Signals
client0_tlp_data[(DW_W_PAR-1):0] I The data payload for the TLP. The data is in little endian format. The first
transmitted payload byte is in [7:0]. The base width of client0_tlp_data is
your application datapath width, which is automatically determined
according to the selected operating frequency and number of lanes.
■ For a 32-bit controller, the base width is 32 (client0_tlp_data[31:0])
■ For a 64-bit controller, the base width is 64 (client0_tlp_data[63:0])
■ For a 128-bit controller, the base width is 128 (client0_tlp_-
data[127:0])
■ For a 256-bit controller, the base width is 256(client0_tlp_-
data[255:0])
When 'Transmit Address Alignment' is (client0_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), the first enabled byte of the request
must be bits [7:0] of this data bus. The controller up-shifts the data in the
transmitted TLP based the lower two bits of the byte address. Your
application must append protection code bits to the most significant bits
of this bus when ECC or parity datapath protection is used.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_dv is asserted
client0_tlp_func_num[(PF_WD-1):0] I Indicates from which physical function (PF) the request is coming. The
controller uses client0_tlp_func_num to form the requester ID for
requests and the completer ID for completions. Function numbering
starts at '0'. For a single-function device, set client0_tlp_func_num to
000b.
Exists: !(AMBA_INTERFACE!=0)
Synchronous To: None,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
Synopsys, Inc.
client0_tlp_prfx[(PRFX_DW-1):0] I TLP prefixes. The field [31:0] represents the first prefix to be
transmitted. The optional TLP prefixes are implemented as little endian.
Using the example of a controller with just one prefix (CX_NPRFX =1),
this means that client0_tlp_prfx[31:0] has prefix byte #0 in the lower byte
position of the dword client0_tlp_prfx[31:0]. That is, FMT =bits 7:5, and
Type =bits 4:0. Your application is responsible for passing Local and
End-End prefixes in the correct order for transmission. Local prefixes
must precede End-End prefixes. The controller passes along and
appends to the prefix, any protection codes it receives, when datapath
protection is enabled.
Exists: (!(AMBA_INTERFACE!=0)) && (CX_TLP_PREFIX_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
client0_tlp_atu_bypass I Internal ATU Bypass for XALI0. When set it indicates that this
transaction should not be processed by the internal address translation
unit
Exists: (!(AMBA_INTERFACE!=0)) &&
(CX_INTERNAL_ATU_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
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PCI Express SW Controller Databook XALI1 Interface Signals
client1_addr_align_en - - xadm_client1_halt
client1_tlp_byte_en -
client1_remote_req_id -
client1_cpl_status -
client1_cpl_bcm -
client1_cpl_byte_cnt -
client1_tlp_dv -
client1_tlp_eot -
client1_tlp_bad_eot -
client1_tlp_hv -
client1_tlp_fmt -
client1_tlp_type -
client1_tlp_tc -
client1_tlp_td -
client1_tlp_ep -
client1_tlp_attr -
client1_tlp_byte_len -
client1_tlp_tid -
client1_tlp_addr -
client1_hdr_prot -
client1_tlp_data -
client1_tlp_func_num -
client1_tlp_prfx -
client1_tlp_atu_bypass -
Synopsys, Inc.
client1_tlp_byte_en[7:0] I Byte enables for the first and last dword of the TLP:
■ [3:0]: Byte enables for the first dword
■ [7:4]: Byte enables for the last dword
A TLP can have 'holes' between bytes when the TLP is less than eight
bytes (2 dwords) long, according to the PCI Express Specification(not
all valid bytes need to be contiguous). However, a TLP is not allowed to
have holes between bytes when the TLP is more than eight bytes. Not
used (set to 0x0) when 'Transmit Address Alignment' is
(client1_addr_align_en =1 and GLOB_ADDR_ALIGN_EN =1). When
sending a message, your application asserts the message code onto
these signals.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted. Not valid when
client1_addr_align_en is asserted.
client1_cpl_status[2:0] I The value to be used in the completion Status field of a completion TLP
header on XALI1:
■ 000b: Successful completion
■ 001b: Unsupported request
■ 010b: Configuration request retry status
■ 100b: Completer abort
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted. Only used when XALI1 is
connected to a completer.
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PCI Express SW Controller Databook XALI1 Interface Signals
client1_cpl_byte_cnt[11:0] I The value to be used for the Byte Count field of a memory read
completion TLP. The value client1_cpl_byte_cnt indicates the number of
bytes remaining to be delivered for the request, as defined in the PCI
Express Specification:
■ 001h: 1 byte
■ FFFh: 4095 bytes
■ 000h: 4096 bytes
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted. Only used when XALI1 is
connected to a completer.
client1_tlp_dv I Indicates that the TLP payload data client1_tlp_data is valid. Your
application must not assert client1_tlp_dv for TLPs that do not include a
payload, such as memory read requests.
Your application must present the first payload data the same cycle with
the TLP header.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
client1_tlp_eot I Indicates the end of TLP payload data for a TLP that includes a payload.
For a TLP that does not include a payload (such as a memory read
request), your application must assert and de-assert client1_tlp_eot at
the same time as client1_tlp_hv. You must not assert it at any other time.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
client1_tlp_bad_eot I Indicates that the current TLP must be nullified. To nullify a TLP, your
application must assert client1_tlp_bad_eot in the same cycle as
client_tlp_eot. When client1_tlp_bad_eot is asserted, the controller
nullifies the TLP (inverts the LCRC and inserts EDB as the final framing
symbol in the transmitted TLP). Your application can use
client1_tlp_bad_eot to nullify a TLP because of a known error condition,
or to abort the current transaction when the current transaction is being
blocked (for example, due to lack of FC credits):
■ To cancel a request that has not been granted (xadm_client1_halt
has never been de-asserted for the transfer), the CLIENT PULL-
BACK feature from coreConsultant must be selected. In addition, the
following signals must be driven as follows. Assert
client1_tlp_bad_eot and client1_tlp_eot for one clock cycle while
xadm_client1_halt is asserted (indicating that the request has not
been granted), then de-assert client1_tlp_hv, client1_tlp_dv,
client1_tlp_bad_eot, and client1_tlp_eot to terminate the request.
Without the CLIENT_PULLBACK feature, your application has to
send the full packet and mark the EOT and BAD_EOT at the end.
With the CLIENT_PULLBACK feature, your application can mark
EOT and BAD_EOT when it realizes that it needs to nullify the TLP,
without having to present the full packet.
■ To cancel a request that is in progress (xadm_client1_halt has been
asserted for the transfer), assert client1_tlp_bad_eot and
client1_tlp_eot for one clock cycle while xadm_client1_halt is
de-asserted (indicating that the request has been granted), then
de-assert client1_tlp_hv, client1_tlp_dv, client1_tlp_bad_eot, and
client1_tlp_eot to terminate the request. In this case, the controller
nullifies the TLP as described above.
■ When the TLP is a one-cycle request (client1_tlp_hv and
client1_tlp_eot asserted in the same cycle) and client1_tlp_bad_eot
is also asserted, this request is ignored. Sending a nullified TLP is
not very useful because the link partner has to ignore it anyway. Your
application should realize that this request is nullified (in this case
ignored) and de-assert client1_tlp_hv and client1_tlp_eot while
keeping client1_tlp_bad_eot asserted.
■ Nullify Atomic Ops TLP is not supported.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_eot is asserted
client1_tlp_hv I Indicates that the TLP header data the TLP header ports is valid. The
header data must remain valid until client1_tlp_hv is de-asserted.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook XALI1 Interface Signals
client1_tlp_fmt[1:0] I The value to be used for the Format field of the TLP header on XALI1:
■ 00b: 3 dword header, no data
■ 01b: 4 dword header, no data
■ 10b: 3 dword header, with data
■ 11b: 4 dword header, with data
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
client1_tlp_type[4:0] I The value to be used for the Type field of the client1 TLP header, as
defined in the PCI Express Specification.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
client1_tlp_tc[2:0] I The value to be used for the Traffic Class (TC) field of the TLP header
(000b'111b) on XALI1.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
client1_tlp_td I TLP Digest bit on XALI1. It is expected that the ECRC is already
present, and the controller forwards it unchanged. You should set this
input to 1.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
Synopsys, Inc.
client1_tlp_ep I When asserted, the controller sets the Poisoned TLP (EP) bit in the TLP
header on XALI1.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
client1_tlp_byte_len[12:0] I The number of bytes in the TLP (not including ECRC). The value should
be in the range 0x0000 (0) to 0x1000 (4096)
When 'Transmit Address Alignment' is (client1_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), this must be the full byte length of the
request. When transmit alignment is off (client1_addr_align_en=0), bits
[1:0] must be set to '00'. The byte length value must be rounded up to
the next dword boundary. For example, when the request is five bytes
long, the value of bits [12:0] must be eight.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
client1_tlp_tid[(TAG_SIZE-1):0] I Tag field for the TLP header. Your application must provide a valid Tag
client1_tlp_tid for all posted and non-posted requests. The value of the
CX_MAX_TAG configuration option determines the maximum number of
outstanding Client requests. Your application is expected to manage the
Tag for every posted and non-posted request. For completions, the
client1_tlp_tid value must be the Tag from the corresponding request.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
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PCI Express SW Controller Databook XALI1 Interface Signals
client1_tlp_addr[63:0] I The Address field for the TLP header. The TLP address can be 64 or 32
bits. When sending completions, the controller uses
client1_tlp_addr[6:0] for the Lower Address field of the completion TLP.
The bits in this address bus map directly to the address bits in the TLP
header. The third and fourth dwords of the header are mapped as
follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. Third dword (bytes
8-11) =client1_tlp_addr[31:0]. Therefore, bits [7:0] are mapped to
byte 11 which is the lowest eight bits of the TLP header address. For
more details, see the 'Endianness' advanced information chapter.
■ MEM (64-bit) / MSG have a 4-dword header. Third dword (bytes
8-11) =client1_tlp_addr[63:32]. Fourth dword (bytes 12-15)
=client1_tlp_addr[31:0]. Therefore, bits [7:0] are mapped to byte 15
which is the lowest eight bits of the TLP header address. For more
details, see the 'Endianness' advanced information chapter.
When sending (DSP) a configuration request, client1_tlp_addr must
contain the following information:
■ [31:24]: Bus Number
■ [23:19]: Device Number
■ [18:16]: Function Number
■ [11:8]: Extended Register Number
■ [7:2]: Register Number
The base width of client1_tlp_addr is 64 bits. When 'Transmit Address
Alignment' is (client1_addr_align_en =1 and GLOB_ADDR_ALIGN_EN
=1), this address is the full byte address of the first enabled byte of the
request. That is, the address is byte-aligned. When transmit alignment
is off (client1_addr_align_en=0), bits [1:0] must be '00', that is, the
address must be dword-aligned.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
Synopsys, Inc.
client1_hdr_prot[(CLIENT_HDR_PROT_W I ECC or parity bits (protection code) for the XALI1 header. Your
D-1):0] application must calculate the protection code over all of the XALI0
header inputs in this order: client1_tlp_th, client1_tlp_st, client1_tlp_ph,
client1_tlp_ln, client1_tlp_func_num, client1_tlp_attr,
client1_addr_align_en, client1_tlp_byte_en, client1_remote_req_id,
client1_cpl_status, client1_cpl_bcm, client1_cpl_byte_cnt,
client1_tlp_tid, client1_tlp_byte_len, client1_tlp_ep, client1_tlp_td,
client1_tlp_tc, client1_tlp_type, client1_tlp_fmt, client1_tlp_addr[63:0].
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED) &&
(((CX_RASDP==0)? 0: 1))
Synchronous To: core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
client1_tlp_data[(DW_W_PAR-1):0] I The data payload for the TLP. The data is in little endian format. The first
transmitted payload byte is in [7:0]. The base width of client1_tlp_data is
your application datapath width, which is automatically determined
according to the selected operating frequency and number of lanes.
■ For a 32-bit controller, the base width is 32 (client1_tlp_data[31:0])
■ For a 64-bit controller, the base width is 64 (client1_tlp_data[63:0])
■ For a 128-bit controller, the base width is 128 (client1_tlp_-
data[127:0])
■ For a 256-bit controller, the base width is 256(client1_tlp_-
data[255:0])
When 'Transmit Address Alignment' is (client1_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), the first enabled byte of the request
must be bits [7:0] of this data bus. The controller up-shifts the data in the
transmitted TLP based the lower two bits of the byte address. Your
application must append protection code bits to the most significant bits
of this bus when ECC or parity datapath protection is used.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_dv is asserted
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PCI Express SW Controller Databook XALI1 Interface Signals
client1_tlp_func_num[(PF_WD-1):0] I Indicates from which physical function (PF) the request is coming. The
controller uses client1_tlp_func_num to form the requester ID for
requests and the completer ID for completions. Function numbering
starts at '0'. For a single-function device, set client1_tlp_func_num to
000b.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED)
Synchronous To: None,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
Synopsys, Inc.
client1_tlp_prfx[(PRFX_DW-1):0] I TLP prefixes. The field [31:0] represents the first prefix to be
transmitted. The optional TLP prefixes are implemented as little endian.
Using the example of a controller with just one prefix (CX_NPRFX =1),
this means that client1_tlp_prfx[31:0] has prefix byte #0 in the lower byte
position of the dword client1_tlp_prfx[31:0]. That is, FMT =bits 7:5, and
Type =bits 4:0. Your application is responsible for passing Local and
End-End prefixes in the correct order for transmission. Local prefixes
must precede End-End prefixes. The controller passes along and
appends to the prefix, any protection codes it receives, when datapath
protection is enabled.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED) &&
(CX_TLP_PREFIX_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client1_tlp_hv is asserted
client1_tlp_atu_bypass I Internal ATU Bypass for XALI1. When set it indicates that this
transaction should not be processed by the internal address translation
unit
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED) &&
(CX_INTERNAL_ATU_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
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PCI Express SW Controller Databook XALI2 Interface Signals
client2_addr_align_en - - xadm_client2_halt
client2_tlp_byte_en -
client2_remote_req_id -
client2_cpl_status -
client2_cpl_bcm -
client2_cpl_byte_cnt -
client2_tlp_dv -
client2_tlp_eot -
client2_tlp_bad_eot -
client2_tlp_hv -
client2_tlp_fmt -
client2_tlp_type -
client2_tlp_tc -
client2_tlp_td -
client2_tlp_ep -
client2_tlp_attr -
client2_tlp_byte_len -
client2_tlp_tid -
client2_tlp_addr -
client2_hdr_prot -
client2_tlp_data -
client2_tlp_func_num -
client2_tlp_prfx -
client2_tlp_atu_bypass -
Synopsys, Inc.
client2_tlp_byte_en[7:0] I Byte enables for the first and last dword of the TLP:
■ [3:0]: Byte enables for the first dword
■ [7:4]: Byte enables for the last dword
A TLP can have 'holes' between bytes when the TLP is less than eight
bytes (2 dwords) long, according to the PCI Express Specification(not
all valid bytes need to be contiguous). However, a TLP is not allowed to
have holes between bytes when the TLP is more than eight bytes. Not
used (set to 0x0) when 'Transmit Address Alignment' is
(client2_addr_align_en =1 and GLOB_ADDR_ALIGN_EN =1). When
sending a message, your application asserts the message code onto
these signals.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted. Not valid when
client2_addr_align_en is asserted.
client2_cpl_status[2:0] I The value to be used in the completion Status field of a completion TLP
header:
■ 000b: Successful completion
■ 001b: Unsupported request
■ 010b: Configuration request retry status
■ 100b: Completer abort
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted. Only used when XALI2 is
connected to a completer.
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PCI Express SW Controller Databook XALI2 Interface Signals
client2_cpl_byte_cnt[11:0] I The value to be used for the Byte Count field of a memory read
completion TLP. The value client2_cpl_byte_cnt indicates the number of
bytes remaining to be delivered for the request, as defined in the PCI
Express Specification:
■ 001h: 1 byte
■ FFFh: 4095 bytes
■ 000h: 4096 bytes
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted. Only used when XALI2 is
connected to a completer.
client2_tlp_dv I Indicates that the TLP payload data client2_tlp_data is valid. Your
application must not assert client2_tlp_dv for TLPs that do not include a
payload, such as memory read requests.
Your application must present the first payload data the same cycle with
the TLP header.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
client2_tlp_eot I Indicates the end of TLP payload data for a TLP that includes a payload.
For a TLP that does not include a payload (such as a memory read
request), your application must assert and de-assert client2_tlp_eot at
the same time as client2_tlp_hv. You must not assert it at any other time.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
client2_tlp_bad_eot I Indicates that the current TLP must be nullified. To nullify a TLP, your
application must assert client2_tlp_bad_eot in the same cycle as
client_tlp_eot. When client2_tlp_bad_eot is asserted, the controller
nullifies the TLP (inverts the LCRC and inserts EDB as the final framing
symbol in the transmitted TLP). Your application can use
client2_tlp_bad_eot to nullify a TLP because of a known error condition,
or to abort the current transaction when the current transaction is being
blocked (for example, due to lack of FC credits):
■ To cancel a request that has not been granted (xadm_client2_halt
has never been de-asserted for the transfer), the CLIENT PULL-
BACK feature from coreConsultant must be selected. In addition, the
following signals must be driven as follows. Assert
client2_tlp_bad_eot and client2_tlp_eot for one clock cycle while
xadm_client2_halt is asserted (indicating that the request has not
been granted), then de-assert client2_tlp_hv, client2_tlp_dv,
client2_tlp_bad_eot, and client2_tlp_eot to terminate the request.
Without the CLIENT_PULLBACK feature, your application has to
send the full packet and mark the EOT and BAD_EOT at the end.
With the CLIENT_PULLBACK feature, your application can mark
EOT and BAD_EOT when it realizes that it needs to nullify the TLP,
without having to present the full packet.
■ To cancel a request that is in progress (xadm_client2_halt has been
asserted for the transfer), assert client2_tlp_bad_eot and
client2_tlp_eot for one clock cycle while xadm_client2_halt is
de-asserted (indicating that the request has been granted), then
de-assert client2_tlp_hv, client2_tlp_dv, client2_tlp_bad_eot, and
client2_tlp_eot to terminate the request. In this case, the controller
nullifies the TLP as described above.
■ When the TLP is a one-cycle request (client2_tlp_hv and
client2_tlp_eot asserted in the same cycle) and client2_tlp_bad_eot
is also asserted, this request is ignored. Sending a nullified TLP is
not very useful because the link partner has to ignore it anyway. Your
application should realize that this request is nullified (in this case
ignored) and de-assert client2_tlp_hv and client2_tlp_eot while
keeping client2_tlp_bad_eot asserted.
■ Nullify Atomic Ops TLP is not supported.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_eot is asserted
client2_tlp_hv I Indicates that the TLP header data the TLP header ports is valid. The
header data must remain valid until client2_tlp_hv is de-asserted.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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client2_tlp_fmt[1:0] I The value to be used for the Format field of the TLP header:
■ 00b: 3 dword header, no data
■ 01b: 4 dword header, no data
■ 10b: 3 dword header, with data
■ 11b: 4 dword header, with data
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
client2_tlp_type[4:0] I The value to be used for the Type field of the client2 TLP header, as
defined in the PCI Express Specification.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
client2_tlp_tc[2:0] I The value to be used for the Traffic Class (TC) field of the TLP header
(000b'111b) on XALI2.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
client2_tlp_td I TLP Digest bit. It is expected that the ECRC is already present, and the
controller forwards it unchanged. You should set this input to 1.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
Synopsys, Inc.
client2_tlp_ep I When asserted, the controller sets the Poisoned TLP (EP) bit in the TLP
header on XALI2.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
client2_tlp_byte_len[12:0] I The number of bytes in the TLP (not including ECRC). The value should
be in the range 0x0000 (0) to 0x1000 (4096)
When 'Transmit Address Alignment' is (client2_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), this must be the full byte length of the
request. When transmit alignment is off (client2_addr_align_en=0), bits
[1:0] must be set to '00'. The byte length value must be rounded up to
the next dword boundary. For example, when the request is five bytes
long, the value of bits [12:0] must be eight.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
client2_tlp_tid[(TAG_SIZE-1):0] I Tag field for the TLP header. Your application must provide a valid Tag
client2_tlp_tid for all posted and non-posted requests. The value of the
CX_MAX_TAG configuration option determines the maximum number of
outstanding Client requests. Your application is expected to manage the
Tag for every posted and non-posted request. For completions, the
client2_tlp_tid value must be the Tag from the corresponding request.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
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PCI Express SW Controller Databook XALI2 Interface Signals
client2_tlp_addr[63:0] I The Address field for the TLP header. The TLP address can be 64 or 32
bits. When sending completions, the controller uses
client2_tlp_addr[6:0] for the Lower Address field of the completion TLP.
The bits in this address bus map directly to the address bits in the TLP
header. The third and fourth dwords of the header are mapped as
follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. Third dword (bytes
8-11) =client2_tlp_addr[31:0]. Therefore, bits [7:0] are mapped to
byte 11 which is the lowest eight bits of the TLP header address. For
more details, see the 'Endianness' advanced information chapter.
■ MEM (64-bit) / MSG have a 4-dword header. Third dword (bytes
8-11) =client2_tlp_addr[63:32]. Fourth dword (bytes 12-15)
=client2_tlp_addr[31:0]. Therefore, bits [7:0] are mapped to byte 15
which is the lowest eight bits of the TLP header address. For more
details, see the 'Endianness' advanced information chapter.
When sending (DSP) a configuration request, client2_tlp_addr must
contain the following information:
■ [31:24]: Bus Number
■ [23:19]: Device Number
■ [18:16]: Function Number
■ [11:8]: Extended Register Number
■ [7:2]: Register Number
The base width of client2_tlp_addr is 64 bits. When 'Transmit Address
Alignment' is (client2_addr_align_en =1 and GLOB_ADDR_ALIGN_EN
=1), this address is the full byte address of the first enabled byte of the
request. That is, the address is byte-aligned. When transmit alignment
is off (client2_addr_align_en=0), bits [1:0] must be '00', that is, the
address must be dword-aligned.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
Synopsys, Inc.
client2_hdr_prot[(CLIENT_HDR_PROT_W I ECC or parity bits (protection code) for the XALI2 header. Your
D-1):0] application must calculate the protection code over all of the XALI0
header inputs in this order: client2_tlp_th, client2_tlp_st, client2_tlp_ph,
client2_tlp_ln, client2_tlp_func_num, client2_tlp_attr,
client2_addr_align_en, client2_tlp_byte_en, client2_remote_req_id,
client2_cpl_status, client2_cpl_bcm, client2_cpl_byte_cnt,
client2_tlp_tid, client2_tlp_byte_len, client2_tlp_ep, client2_tlp_td,
client2_tlp_tc, client2_tlp_type, client2_tlp_fmt, client2_tlp_addr[63:0].
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED) &&
(((CX_RASDP==0)? 0: 1))
Synchronous To: core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
client2_tlp_data[(DW_W_PAR-1):0] I The data payload for the TLP. The data is in little endian format. The first
transmitted payload byte is in [7:0]. The base width of client2_tlp_data is
your application datapath width, which is automatically determined
according to the selected operating frequency and number of lanes.
■ For a 32-bit controller, the base width is 32 (client2_tlp_data[31:0])
■ For a 64-bit controller, the base width is 64 (client2_tlp_data[63:0])
■ For a 128-bit controller, the base width is 128 (client2_tlp_-
data[127:0])
■ For a 256-bit controller, the base width is 256(client2_tlp_-
data[255:0])
When 'Transmit Address Alignment' is (client2_addr_align_en =1 and
GLOB_ADDR_ALIGN_EN =1), the first enabled byte of the request
must be bits [7:0] of this data bus. The controller up-shifts the data in the
transmitted TLP based the lower two bits of the byte address. Your
application must append protection code bits to the most significant bits
of this bus when ECC or parity datapath protection is used.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_dv is asserted
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PCI Express SW Controller Databook XALI2 Interface Signals
client2_tlp_func_num[(PF_WD-1):0] I Indicates from which physical function (PF) the request is coming. The
controller uses client2_tlp_func_num to form the requester ID for
requests and the completer ID for completions. Function numbering
starts at '0'. For a single-function device, set client2_tlp_func_num to
000b.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED)
Synchronous To: None,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
Synopsys, Inc.
client2_tlp_prfx[(PRFX_DW-1):0] I TLP prefixes. The field [31:0] represents the first prefix to be
transmitted. The optional TLP prefixes are implemented as little endian.
Using the example of a controller with just one prefix (CX_NPRFX =1),
this means that client2_tlp_prfx[31:0] has prefix byte #0 in the lower byte
position of the dword client2_tlp_prfx[31:0]. That is, FMT =bits 7:5, and
Type =bits 4:0. Your application is responsible for passing Local and
End-End prefixes in the correct order for transmission. Local prefixes
must precede End-End prefixes. The controller passes along and
appends to the prefix, any protection codes it receives, when datapath
protection is enabled.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED) &&
(CX_TLP_PREFIX_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client2_tlp_hv is asserted
client2_tlp_atu_bypass I Internal ATU Bypass for XALI2. When set it indicates that this
transaction should not be processed by the internal address translation
unit
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED) &&
(CX_INTERNAL_ATU_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: client0_tlp_hv is asserted
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PCI Express SW Controller Databook XALI_CCIX Interface Signals
ccix_tlp_hv - - xadm_ccix_tlp_halt
ccix_tlp_dv -
ccix_tlp_hdr -
ccix_tlp_data -
ccix_tlp_eot -
ccix_tlp_bad_eot -
ccix_tlp_hv I Indicates that the TLP header data in the TLP header ports is valid. The
header data must remain valid until ccix_tlp_hv is de-asserted.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: aux_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
ccix_tlp_dv I Indicates that the TLP payload data ccix_tlp_data is valid. Your
application must not assert ccix_tlp_dv for TLPs that do not include a
payload.
Your application must present the first payload data the same cycle with
the TLP header.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
ccix_tlp_hdr[(TX_HW_W_PAR-1):0] I Header for the TLP being presented in the CCIX interface.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: ccix_tlp_hv is asserted
Synopsys, Inc.
ccix_tlp_data[(DW_W_PAR-1):0] I Payload data in CCIX interfaces. Your application must not assert
ccix_tlp_dv for TLPs that do not include a payload.
Your application must present the first payload data the same cycle with
the TLP header.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
ccix_tlp_eot I Indicates the last segment of the TLP in the CCIX dedicated interface.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ccix_tlp_hv or ccix_tlp_dv is asserted
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PCI Express SW Controller Databook ADM adaptor Interface Signals
xadm_rfc_in - - xadm_xtlh_out
rtlh_radm_in - - radm_rfc_out
cx_pl_ltssm_emu_in - - cx_pl_ltssm_emu_out
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PCI Express SW Controller Databook Bypass Interface Signals
- radm_bypass_data
- radm_bypass_dwen
- radm_bypass_dv
- radm_bypass_hv
- radm_bypass_eot
- radm_bypass_dllp_abort
- radm_bypass_tlp_abort
- radm_bypass_ecrc_err
- radm_bypass_hdr_prot
- radm_bypass_fmt
- radm_bypass_type
- radm_bypass_tc
- radm_bypass_attr
- radm_bypass_reqid
- radm_bypass_tag
- radm_bypass_func_num
- radm_bypass_td
- radm_bypass_poisoned
- radm_bypass_dw_len
- radm_bypass_first_be
- radm_bypass_last_be
- radm_bypass_addr
- radm_bypass_bcm
- radm_bypass_cpl_last
- radm_bypass_cmpltr_id
- radm_bypass_byte_cnt
- radm_bypass_cpl_status
- radm_bypass_tlp_prfx
radm_bypass_data[(DW_W_PAR-1):0] O The payload data from the received TLP. The data is in little endian
format. The first received payload byte is in [7:0]. The controller
appends protection code bits to the most significant bits of this bus
when ECC or parity datapath protection is used.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_dv is asserted
Synopsys, Inc.
radm_bypass_dwen[(NW-1):0] O The databus dword enables identify the location of the last dword of the
TLP the data bus (radm_bypass_data). The width and usage of
radm_bypass_dwen depend the data width of the controller. For a 32-bit
controller, radm_bypass_dwen is not used. For a 64-bit controller, NW
=2. The radm_bypass_dwen[1:0] encoding is:
■ 01: Last dword at radm_bypass_data[31:0].
■ 11: Last dword at radm_bypass_data[63:32].
For a 128-bit controller, NW =4. The radm_bypass_dwen[3:0] encoding
is:
■ 0001: Last dword at radm_bypass_data[31:0].
■ 0011: Last dword at radm_bypass_data[63:32].
■ 0111: Last dword at radm_bypass_data[95:64].
■ 1111: Last dword at radm_bypass_data[127:96].
For a 256-bit controller, NW =8. The radm_bypass_dwen[7:0] encoding
is:
■ 00000001: Last dword at radm_bypass_data[31:0].
■ 00000011: Last dword at radm_bypass_data[63:32].
■ 00000111: Last dword at radm_bypass_data[95:64].
■ 00001111: Last dword at radm_bypass_data[127:96].
■ 00011111: Last dword at radm_bypass_data[159:128].
■ 00111111: Last dword at radm_bypass_data[191:160].
■ 01111111: Last dword at radm_bypass_data[223:192].
■ 11111111: Last dword at radm_bypass_data[255:224].
All other encodings are not generated by the controller.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_eot is asserted
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PCI Express SW Controller Databook Bypass Interface Signals
radm_bypass_eot[(NHQ-1):0] O Indicates the last cycle of valid payload data radm_bypass_data for the
received TLP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv or radm_bypass_dv is asserted
radm_bypass_tlp_abort[(NHQ-1):0] O Indicates to your application to drop the TLP because of malformed TLP
on RBYP, ECRC error, or completion lookup failures (such as TAG or
requester ID (RID) mismatches). You should not expect the TLP to be
replayed. For more details, see the 'Advanced Error Handling For
Received TLPs' advanced information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_eot, radm_bypass_hv
Synopsys, Inc.
radm_bypass_ecrc_err[(NHQ-1):0] O Indicates to your application to drop the TLP because of an ECRC error
in the received TLP on RBYP. You should not expect the TLP to be
replayed. For more details, see the 'Advanced Error Handling For
Received TLPs' advanced information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_eot
radm_bypass_hdr_prot[((NHQ*RASDP_B O ECC or parity bits (protection code) generated by the controller for the
YPASS_HDR_PROT_WD)-1):0] TLP header (bypass mode). Your application must calculate the
protection code over all of the XALI0 header inputs in this order:
radm_bypass_ats, radm_bypass_th, radm_bypass_st,
radm_bypass_ph, radm_bypass_ln, radm_bypass_last_be,
radm_bypass_cpl_last, radm_bypass_poisoned, radm_bypass_td,
radm_bypass_addr, radm_bypass_first_be,
radm_bypass_io_req_in_range, radm_bypass_rom_in_range,
radm_bypass_in_membar_range, radm_bypass_dw_len,
radm_bypass_cpl_status, radm_bypass_func_num, radm_bypass_tag,
radm_bypass_reqid, radm_bypass_attr, radm_bypass_tc,
radm_bypass_type, radm_bypass_fmt.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2)) &&
(((CX_RASDP==0)? 0: 1))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_bypass_hv is asserted
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PCI Express SW Controller Databook Bypass Interface Signals
radm_bypass_tc[((NHQ*3)-1):0] O The Traffic Class (TC) field in the received TLP header on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
radm_bypass_func_num[((NHQ*PF_WD)- O The function number of the incoming TLP on RBYP. Function numbering
1):0] starts at '0'.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
Synopsys, Inc.
radm_bypass_td[(NHQ-1):0] O The TLP Digest (TD) bit in the received TLP header on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
radm_bypass_poisoned[(NHQ-1):0] O The Poisoned (EP) bit in the received TLP header on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
radm_bypass_dw_len[((NHQ*10)-1):0] O The Length field (length of TLP in dwords) in the received TLP header
on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
radm_bypass_first_be[((NHQ*4)-1):0] O The first dword byte enable field in the received TLP header on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
radm_bypass_last_be[((NHQ*4)-1):0] O The last dword byte enable field in the received TLP header on RBYP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
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PCI Express SW Controller Databook Bypass Interface Signals
radm_bypass_addr[((NHQ*FLT_Q_ADDR O The Address in the received TLP header on RBYP. The bits in this
_WIDTH)-1):0] address bus map directly to the address bits in the TLP header. The
third and fourth dwords of the header are mapped as follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. Then radm_by-
pass_addr[31:0] =Third dword (bytes 8-11). Therefore, bits [7:0] are
mapped to byte 11 which is the lowest eight bits of the TLP header
address. For more details, see the 'Endianness' advanced informa-
tion chapter.
■ MEM (64-bit) / MSG have a 4-dword header. Then radm_by-
pass_addr[63:32] =Third dword (bytes 8-11) and radm_by-
pass_addr[31:0] =Fourth dword (bytes 12-15). Therefore, bits [7:0]
are mapped to byte 15 which is the lowest eight bits of the TLP
header address. For more details, see the 'Endianness' advanced
information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
radm_bypass_bcm[(NHQ-1):0] O Byte Count Modified (BCM) bit from the received TLP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
radm_bypass_cpl_last[(NHQ-1):0] O Reserved
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
Synopsys, Inc.
radm_bypass_cpl_status[((NHQ*3)-1):0] O Completion Status field from the header of a received completion TLP.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2))
Synchronous To: None,aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
radm_bypass_tlp_prfx[((NHQ*PRFX_W_P O Receive TLP prefixes. The field [31:0] represents the first prefix to be
AR)-1):0] received. The optional TLP prefixes are implemented as little endian.
Using the example of a controller with just one prefix (CX_NPRFX =1),
this means that radm_bypass_tlp_prfx[31:0] has prefix byte #0 in the
lower byte position of the dword radm_bypass_tlp_prfx[31:0]. That is,
FMT =bits 7:5, and Type =bits 4:0. If no prefix is present for a given TLP,
then that DW, including the FMT field is all zeros. The controller passes
along and appends to the prefix, any protection codes it receives, when
datapath protection is enabled.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2)) &&
(CX_TLP_PREFIX_ENABLE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_bypass_hv is asserted
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PCI Express SW Controller Databook RTRGT1 Interface Signals
trgt1_radm_halt - - radm_trgt1_dv
trgt1_radm_pkt_halt - - radm_trgt1_hv
- radm_trgt1_eot
- radm_trgt1_tlp_abort
- radm_trgt1_dllp_abort
- radm_trgt1_ecrc_err
- radm_trgt1_data
- radm_trgt1_tlp_prfx
- radm_trgt1_dwen
- radm_trgt1_hdr_prot
- radm_trgt1_fmt
- radm_trgt1_type
- radm_trgt1_tc
- radm_trgt1_attr
- radm_trgt1_reqid
- radm_trgt1_tag
- radm_trgt1_func_num
- radm_trgt1_td
- radm_trgt1_poisoned
- radm_trgt1_dw_len
- radm_trgt1_first_be
- radm_trgt1_last_be
- radm_trgt1_addr
- radm_trgt1_hdr_uppr_bytes
- radm_trgt1_hdr_uppr_bytes_valid
- radm_trgt1_cpl_status
- radm_trgt1_bcm
- radm_trgt1_byte_cnt
- radm_trgt1_cpl_last
- radm_trgt1_cmpltr_id
- radm_trgt1_vc
- radm_grant_tlp_type
- radm_trgt1_atu_sloc_match
- radm_trgt1_atu_cbuf_err
Synopsys, Inc.
radm_trgt1_dv O Indicates that the received TLP data is valid on radm_trgt1_data. For
timing details, see the Receive Request Interface (TRGT1) section in
the Signal Interfaces chapter of the Databook.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
radm_trgt1_hv O Indicates that the received TLP header (and prefix) is valid on the
corresponding radm_trgt1_* outputs. For timing details, see the Receive
Request Interface (TRGT1) section in the Signal Interfaces chapter of
the Databook.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
radm_trgt1_eot O Indicates the last cycle of valid data for the received TLP.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv or radm_trgt1_dv is asserted
radm_trgt1_tlp_abort O Indicates to your application to drop the TLP because of malformed TLP
on TRGT1, ECRC error, or completion lookup failures (such as TAG or
requester ID (RID) mismatches). You should not expect the TLP to be
replayed. For more details, see the 'Advanced Error Handling For
Received TLPs' advanced information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_eot, radm_trgt1_hv
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PCI Express SW Controller Databook RTRGT1 Interface Signals
radm_trgt1_ecrc_err O Indicates to your application to drop the TLP because of an ECRC error
in the received TLP on TRGT1. You should not expect the TLP to be
replayed. For more details, see the 'Advanced Error Handling For
Received TLPs' advanced information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_eot
radm_trgt1_data[(TRGT_DATA_WD-1):0] O Received TLP payload data from the upstream component to your
application client. The data is in little endian format. The first received
payload byte is in [7:0]. The controller appends protection code bits to
the most significant bits of this bus when ECC or parity datapath
protection is used.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_dv is asserted
Synopsys, Inc.
radm_trgt1_tlp_prfx[(PRFX_W_PAR-1):0] O Receive TLP prefixes. The field [31:0] represents the first prefix to be
received. The optional TLP prefixes are implemented as little endian.
Using the example of a controller with just one prefix (CX_NPRFX =1),
this means that radm_trgt1_tlp_prfx[31:0] has prefix byte #0 in the lower
byte position of the dword radm_trgt1_tlp_prfx[31:0]. That is, FMT =bits
7:5, and Type =bits 4:0. If no prefix is present for a given TLP, then that
DW, including the FMT field is all zeros. The controller passes along and
appends to the prefix, any protection codes it receives, when datapath
protection is enabled.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
(CX_TLP_PREFIX_ENABLE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
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PCI Express SW Controller Databook RTRGT1 Interface Signals
radm_trgt1_dwen[(NW-1):0] O The databus dword enables identify the location of the last dword of the
TLP the data bus (radm_trgt1_data). The width and usage of
radm_trgt1_dwen depend the data width of the controller. For a 32-bit
controller, radm_trgt1_dwen is not used.
For a 64-bit controller, NW =2. The radm_trgt1_dwen[1:0] encoding is:
■ 01: Last dword at radm_trgt1_data[31:0].
■ 11: Last dword at radm_trgt1_data[63:32].
For a 128-bit controller, NW =4. The radm_trgt1_dwen[3:0] encoding is:
■ 0001: Last dword at radm_trgt1_data[31:0].
■ 0011: Last dword at radm_trgt1_data[63:32].
■ 0111: Last dword at radm_trgt1_data[95:64].
■ 1111: Last dword at radm_trgt1_data[127:96].
For a 256-bit controller, NW =8. The radm_trgt1_dwen[7:0] encoding is:
■ 00000001: Last dword at radm_trgt1_data[31:0].
■ 00000011: Last dword at radm_trgt1_data[63:32].
■ 00000111: Last dword at radm_trgt1_data[95:64].
■ 00001111: Last dword at radm_trgt1_data[127:96].
■ 00011111: Last dword at radm_trgt1_data[159:128].
■ 00111111: Last dword at radm_trgt1_data[191:160].
■ 01111111: Last dword at radm_trgt1_data[223:192].
■ 11111111: Last dword at radm_trgt1_data[255:224].
For a 512-bit controller, NW =16. The radm_trgt1_dwen[15:0] encoding
is:
■ 00000001_11111111: Last dword at radm_trgt1_data[287:256].
■ 00000011_11111111: Last dword at radm_trgt1_data[319:288].
■ 00000111_11111111: Last dword at radm_trgt1_data[351:320].
■ 00001111_11111111: Last dword at radm_trgt1_data[383:352].
■ 00011111_11111111: Last dword at radm_trgt1_data[415:384].
■ 00111111_11111111: Last dword at radm_trgt1_data[447:416].
■ 01111111_11111111: Last dword at radm_trgt1_data[479:448].
■ 11111111_11111111: Last dword at radm_trgt1_data[511:480].
All other encodings are not generated by the controller.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_eot is asserted and NW > 1
Synopsys, Inc.
radm_trgt1_hdr_prot[(RASDP_TRGT1_H O ECC or parity bits (protection code) generated by the controller for the
DR_PROT_WD-1):0] TLP header. Your application must calculate the protection code over all
of the target1 header inputs in this order: radm_trgt1_hdr_uppr_bytes,
radm_trgt1_hdr_uppr_bytes_valid, radm_trgt1_ats, radm_trgt1_th,
radm_trgt1_st, radm_trgt1_ph, radm_trgt1_ln, radm_trgt1_last_be,
radm_trgt1_cpl_last, radm_trgt1_poisoned, radm_trgt1_td,
radm_trgt1_addr, radm_trgt1_first_be, radm_trgt1_io_req_in_range,
radm_trgt1_dw_len, radm_trgt1_cpl_status, radm_trgt1_func_num,
radm_trgt1_tag, radm_trgt1_reqid, radm_trgt1_attr, radm_trgt1_tc,
radm_trgt1_type, radm_trgt1_fmt.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
(((CX_RASDP==0)? 0: 1))
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_trgt1_hv is asserted
radm_trgt1_tc[2:0] O The Traffic Class (TC) field in the received TLP header on TRGT1.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
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PCI Express SW Controller Databook RTRGT1 Interface Signals
radm_trgt1_td O The TLP Digest (TD) bit in the received TLP header on TRGT1.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
Synopsys, Inc.
radm_trgt1_poisoned O The Poisoned (EP) bit in the received TLP header on TRGT1.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
radm_trgt1_dw_len[9:0] O The Length field (length of TLP in dwords) in the received TLP header
on TRGT1.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
radm_trgt1_first_be[3:0] O The first dword byte enable field in the received TLP header on TRGT1.
When a TLP is a message, radm_trgt1_first_be is overlaid with
message_code[3:0]
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
radm_trgt1_last_be[3:0] O The last dword byte enable field in the received TLP header on TRGT1.
When a TLP is a message, radm_trgt1_last_be is overlaid with
message_code[7:4]
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
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PCI Express SW Controller Databook RTRGT1 Interface Signals
radm_trgt1_addr[(ADDR_WIDTH-1):0] O The Address in the received TLP header on TRGT1. The bits in this
address bus map directly to the address bits in the TLP header. The
third and fourth dwords of the header are mapped as follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. Then
radm_trgt1_addr[31:0] =Third dword (bytes 8-11). Therefore, bits
[7:0] are mapped to byte 11 which is the lowest eight bits of the TLP
header address. For more details, see the 'Endianness' advanced
information chapter.
■ MEM (64-bit) / MSG have a 4-dword header. Then
radm_trgt1_addr[63:32] =Third dword (bytes 8-11) and
radm_trgt1_addr[31:0] =Fourth dword (bytes 12-15). Therefore, bits
[7:0] are mapped to byte 15 which is the lowest eight bits of the TLP
header address. For more details, see the 'Endianness' advanced
information chapter.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
radm_trgt1_hdr_uppr_bytes[(ADDR_WIDT O The raw upper bytes in the received TLP header on TRGT1. The upper
H-1):0] bytes in the received TLP header on TRGT1. For a 3-dword header
these are bytes 8 to 11, for a 4-dword header they are bytes 8-15. When
radm_trgt1_hdr_uppr_bytes_valid is asserted, then
radm_trgt1_hdr_uppr_bytes has valid Msg data. These bytes of the TLP
header are mapped as follows:
■ MEM (32-bit) / IO / CFG have a 3-dword header. Then radm_trgt1_
hdr_uppr_bytes[31:0] = bytes 8-11. Therefore, bits [7:0] are mapped
to byte 8 of the TLP header.
■ MEM (64-bit) / MSG have a 4-dword header. Then radm_trgt1_
hdr_uppr_bytes[63:32] = bytes 12-15 and radm_trgt1_ hdr_uppr_-
bytes[31:0] = bytes 8-11. Therefore, bits [7:0] are mapped to byte 8
of the TLP header while bits 39-32 are mapped to byte 12, etc.
Note: For radm_trgt1_hdr_uppr_bytes[63:32] to exist,
FLT_Q_ADDR_WIDTH must have a value of 64. If 32<
FLT_Q_ADDR_WIDTH <64, then
radm_trgt1_hdr_uppr_bytes[FLT_Q_ADDR_WIDTH-1:32] =0; that is,
radm_trgt1_hdr_uppr_bytes[FLT_Q_ADDR_WIDTH-1:32] contains TLP
Header data only if FLT_Q_ADDR_WIDTH =64.
Your application can ensure FLT_Q_ADDR_WIDTH =64 by setting
VENDOR_MESSAGE_SUPPORT =1.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: None,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
Synopsys, Inc.
radm_trgt1_hdr_uppr_bytes_valid O Indicates that the transaction being presented on the TRGT1 interface
has been successfully translated in the iATU from a TLP received in the
PCIe controller. radm_trgt1_hdr_uppr_bytes has valid Msg data when
this signal is asserted.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
((CX_RADMQ_MODE==2)) && (CX_INTERNAL_ATU_ENABLE)
Synchronous To: None,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
radm_trgt1_cpl_status[2:0] O When the received TLP is a completion: completion Status field from the
header of a received completion TLP. When the received TLP is a
request: What the completion status for this request should be,
according to internal filtering rules.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted and completion is not in
bypass mode
radm_trgt1_bcm O Byte Count Modified (BCM) bit from the header of a received completion
TLP.
The BCM bit is not applicable for an endpoint device. However, the
controller does provide the value of the BCM bit radm_trgt1_bcm.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted and the completion is not in
bypass mode
radm_trgt1_byte_cnt[11:0] O Byte Count field from the header of a received completion TLP.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted and completion is not in
bypass mode
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PCI Express SW Controller Databook RTRGT1 Interface Signals
radm_trgt1_cpl_last O Reserved
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
((CX_RADMQ_MODE==2))
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted and completion is not in
bypass mode
Synopsys, Inc.
radm_grant_tlp_type[((NVC*3)-1):0] O Indicates that a particular VC and type transaction has been granted to
output from the receive queue. There is one bit for each TLP type for
each configured VC:
■ 0: Grant posted TLPs for VC0
■ 1: Grant non-posted TLPs for VC0
■ 2: Grant completion TLPs for VC0
■ 3: Grant posted TLPs for VC1
■ .......
■ up to the number of configured VCs.
This grant signal is a pulse. It is used together with trgt1_radm_pkt_halt
to control the amount of transactions that the controller's output queue
outputs.
Exists: ((AMBA_POPULATED==0 ||
CX_CCIX_INTERFACE_ENABLE==1)) && ((CX_RADMQ_MODE==2))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: The TLP type is in not in bypass mode
trgt1_radm_pkt_halt[((NVC*3)-1):0] I Halts the transfer of packets from individual queues. There is one bit of
trgt1_radm_pkt_halt for each TLP type for each configured VC:
■ 0: Halt posted TLPs for VC0
■ 1: Halt non-posted TLPs for VC0
■ 2: Halt completion TLPs for VC0
■ 3: Halt posted TLPs for VC1
■ up to the number of configured VCs.
For more details, see 'RTRGT1 Protocol Rules and Example
Transaction'.
Exists: ((AMBA_POPULATED==0 ||
CX_CCIX_INTERFACE_ENABLE==1)) && ((CX_RADMQ_MODE==2))
&& (TRGT1_POPULATE)
Synchronous To: aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: The TLP type is in not in bypass mode
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PCI Express SW Controller Databook RTRGT1 Interface Signals
radm_trgt1_atu_sloc_match[(ATU_IN_MIN O ATU Single Location match indication per ATU region. Set for 1 core_clk
1-1):0] period pulse when the ATU region matched a received VDM Single
Location Address translation.
Exists: ATU_IN_SINGLE_TRGT_ADDR_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
radm_trgt1_atu_cbuf_err[(ATU_IN_MIN1-1 O ATU Error indication per ATU region. Set for 1 core_clk period pulse
):0] when the ATU region matched received VDM size (payload + 3rd and
4th DW of Header) is greater than the programmed Circular Buffer
Increment size (CBUF_INCR) for Single Location Address translation.
Exists: ATU_IN_SINGLE_TRGT_ADDR_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_trgt1_hv is asserted
Synopsys, Inc.
ccix_radm_halt - - radm_ccix_dv
- radm_ccix_hv
- radm_ccix_data
- radm_ccix_hdr
- radm_ccix_dwen
- radm_ccix_eot
- radm_ccix_tlp_abort
- radm_ccix_dllp_abort
radm_ccix_dv O Indicates the data is valid in the CCIX receive data bus.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook TRGT1_CCIX Interface Signals
ccix_radm_halt I When asserted, this signal causes the controller to stop streaming
information in the CCIX receive interface.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: aux_clk_g,core_clk,{radm_clk_g}
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
radm_ccix_eot O Signals the end of the TLP being delivered in the CCIX receive
interface.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
radm_ccix_tlp_abort O Indication for the application to drop the TLP received in the CCIX
receive interface because of the malformed TLP or ECRC error.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: radm_ccix_hv, radm_ccix_eot
radm_ccix_dllp_abort O Indication for the application to drop the TLP received in the CCIX
receive interface because of the data link layer error such as LCRC.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE) && (!CX_CXS_ENABLE)
Synchronous To: radm_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: radm_ccix_eot
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PCI Express SW Controller Databook Clock and Reset (APM) Signals
perst_n - - pm_req_sticky_rst
app_clk_req_n - - pm_req_core_rst
phy_clk_req_n - - pm_req_non_sticky_rst
ack_sticky_rst - - pm_sel_aux_clk
ack_core_rst - - pm_en_core_clk
ack_non_sticky_rst - - pm_req_phy_rst
ret_sticky_rst_n - - pm_req_retention_rst
ret_non_sticky_rst_n -
ret_core_rst_n -
ret_core_pl_rst_n -
perst_n I Indicates when the main power supply is within its tolerated voltage
range and is stable.
This signal is syncronized using aux_clk and can be driven/supplied
asynchronously to the controller in certain low-power modes.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
app_clk_req_n I Indicates that the application logic is ready to have reference clock
removed. In designs which support reference clock removal through
either L1 PM Sub-states or L1 CPM, the application should set this
signal to 1'b when it is ready to have reference clock removed. If the
application does not want to remove reference clock it should set this
signal to 1'b0.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
Synopsys, Inc.
phy_clk_req_n I Acknowledge from the PHY that it is ready to have reference clock
removed. In designs that support L1 PM Sub-states or L1 CPM, there is
a handshake with the PHY prior to reference clock removal. This signal
should be connected to the acknoweldge signal from the PHY. If the
PHY does not want to remove the reference clock it should set this
signal to 1'b0.
This signal is syncronized using aux_clk and can be driven/supplied
asynchronously to the controller in certain low-power modes.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Clock and Reset (APM) Signals
pm_sel_aux_clk O This signal switches the source of aux_clk from core_clk to the low
speed clock.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
pm_en_core_clk O This signal is used to gate off the core_clk in low power states.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
ret_sticky_rst_n I Resets all sticky bit registers in the retention (L1 power gating) register
based modules of configuration register space. For more details, see
"Advanced Power Management and Power Domain Gating" in the
Power Management section, and the "Reset Requirements" section in
the Architecture chapter of the Databook.
Exists: CX_L1_PG_ENABLE
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
ret_non_sticky_rst_n I Resets all non-sticky bit registers in the retention (L1 power gating)
register based modules of configuration register space. For more
details, see "Advanced Power Management and Power Domain Gating"
in the Power Management section, and the "Reset Requirements"
section in the Architecture chapter of the Databook.
Exists: CX_L1_PG_ENABLE
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Clock and Reset (APM) Signals
ret_core_rst_n I Resets retention (L1 power gating) register based modules of the
controller logic. For more details, see "Advanced Power Management
and Power Domain Gating" in the Power Management section, and the
"Reset Requirements" section in the Architecture chapter of the
Databook. Asynchronous assertion with synchronous de-assertion.
Exists: CX_L1_PG_ENABLE
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
ret_core_pl_rst_n I Resets retention (L1 power gating) register based modules of the
controller logic for layer1. For more details, see "Advanced Power
Management and Power Domain Gating" in the Power Management
section, and the "Reset Requirements" section in the Architecture
chapter of the Databook. Asynchronous assertion with synchronous
de-assertion.
Exists: (CX_L1_PG_ENABLE) && (CX_FREQ_STEP_DL_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
Synopsys, Inc.
ret_pipe_clk - - en_aux_clk_g
ret_pipe_rst_n - - en_radm_clk_g
ret_core_clk_ug - - radm_idle
ret_core_pl_clk_ug - - training_rst_n
pipe_clk -
pipe_msgbus_rst_n -
cxs_clk -
cxs_rst_n -
core_clk -
ret_core_clk -
core_clk_ug -
core_pl_clk -
core_pl_clk_ug -
ret_core_pl_clk -
aux_clk -
aux_clk_g -
radm_clk_g -
pwr_rst_n -
sticky_rst_n -
non_sticky_rst_n -
core_rst_n -
pipe_rst_n -
core_pl_rst_n -
app_init_rst -
aux_clk_active -
slv_pwr_rst_n -
mstr_pwr_rst_n -
dbi_pwr_rst_n -
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PCI Express SW Controller Databook Clock and Reset Signals
ret_core_clk_ug I The ungated version of the primary clock input to the controller, for
modules retained during L1 power gating. The ret_core_clk_ug
frequency is the same as core_clk_ug.
Exists: ((CX_CPCIE_ENABLE)) && (CX_RET_CORE_CLK_UG_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
ret_core_pl_clk_ug I The ungated version of the primary clock input to the controller for
physical layer, for modules retained during L1 power gating. The
ret_core_pl_clk_ug frequency is the same as core_pl_clk_ug.
Exists: ((CX_CPCIE_ENABLE)) &&
(CX_RET_CORE_PL_CLK_UG_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
pipe_clk I PIPE clock from external PHY. Used by the controller to clock the PIPE.
The PHY TX PLL generates pipe_clk from the platform reference clock.
The PHY adapts and re-times RX data to pipe_clk. The PIPE clock rate
is 62.5 MHz, 125 MHz, 250 MHz, or 500 MHz, depending on datapath
configuration and symbol/datapath width at the PHY interface.
Exists: ((CX_CPCIE_ENABLE)) && (CX_FREQ_STEP_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
pipe_msgbus_rst_n I Resets controller logic clocked on pipe_clk. Reset logic should assert
pipe_msgbus_rst_n at same time as phy_rst_n and deassert
synchronous to pipe_clk.
Exists: ((CX_CPCIE_ENABLE)) && (CX_PIPE51_SUPPORT)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
core_clk I The gated version of the primary clock input to the controller. It is
assumed that all input signals except resets are synchronous to this
clock. Depending the controller configuration and Gen2/Gen3 mode, the
core_clk frequency is 62.5 MHz, 125 MHz, 250 MHz, or 500 MHz if
Base PCIe. You can gate this clock during the L1 and L2 low power
states.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
ret_core_clk I The gated version of the primary clock input to the controller, for
modules retained during L1 power gating. The ret_core_clk frequency is
the same as core_clk. You can gate this clock during the L1 and L2 low
power states under the same conditions as core_clk.
Exists: CX_L1_PG_ENABLE
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Clock and Reset Signals
core_clk_ug I The ungated version of the primary clock input to the controller.
Depending the controller configuration and Gen2/Gen3 mode, the
core_clk_ug frequency is 62.5 MHz, 125 MHz, 250 MHz, or 500 MHz.
■ You must not gate this during the L1 and L2 low power states.
■ It is used in the PCIe controller to sample phy_mac_phystatus.
In Selectable PHY mode (M-PCIe), you must connect this signal to
core_clk.
Exists: (CX_S_CPCIE_MODE || CX_SEL_PHY_MODE )
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
core_pl_clk I The gated version of the primary clock input to the controller for physical
layer. It is assumed that all input signals except resets are synchronous
to this clock. Depending the controller configuration and Gen2/Gen3
mode, the core_clk frequency is 62.5 MHz, 125 MHz, 250 MHz, or 500
MHz if Base PCIe. You can gate this clock during the L1 and L2 low
power states.
Exists: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE )) &&
(CX_FREQ_STEP_DL_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
core_pl_clk_ug I The ungated version of the primary clock input to the controller for
physical layer. Depending the controller configuration and Gen2/Gen3
mode, the core_pl_clk_ug frequency is 62.5 MHz, 125 MHz, 250 MHz,
or 500 MHz.
■ You must not gate this during the L1 and L2 low power states.
■ It is used in the PCIe controller to sample phy_mac_phystatus.
In Selectable PHY mode (M-PCIe), you must connect this signal to
core_clk.
Exists: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE )) &&
(CX_FREQ_STEP_DL_EN)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
ret_core_pl_clk I The gated version of the primary clock input to the controller for physical
layer, for modules retained during L1 power gating. The ret_core_pl_clk
frequency is the same as core_pl_clk. You can gate this clock during the
L1 and L2 low power states under the same conditions as core_plclk.
Exists: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE )) &&
(CX_FREQ_STEP_DL_EN) && (CX_L1_PG_ENABLE)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
aux_clk I Auxiliary clock to the PMC domain. The partitioning of the controller
enables some functions to operate aux_clk in certain power
management states. The PMC is partitioned to run aux_clk in L2 states,
if supported by your application. In normal operation, the aux_clk and
core_clk inputs are assumed to be equivalent and the physical design
implementation must assume they are the same in terms of clock tree
matching and skew. For power management enabled solutions, it is the
responsibility of your application designer to manage any clock
switching required to gate core_clk and switch aux_clk from the normal
operating frequency to the slower clock rate used in the low power
states.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Clock and Reset Signals
radm_idle O RADM activity status signal. The controller creates the en_radm_clk_g
output by gating this signal with the output of the
RADM_CLK_GATING_EN field in the CLOCK_GATING_CTRL_OFF
register. For debug purposes only.
Exists: Always
Synchronous To: aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
pwr_rst_n I Resets the PMC module. The pwr_rst_n signal is used as the 'cold
reset' applied to the controller power-up. It must be asserted
(asynchronously) following your application of auxiliary power or
following your application of main power if auxiliary power is not
available to the device. The pwr_rst_n input resets all registers in the
aux_clk domain, including sticky bits. It must be de-asserted
synchronously.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
Synopsys, Inc.
sticky_rst_n I Resets all sticky bit registers in the configuration register space.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
non_sticky_rst_n I Resets all non-sticky bit registers in the configuration register space.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
core_rst_n I Resets the controller, except for the PMC module. Upon initial power-up,
core_rst_n is asserted in order to reset the non-auxiliary power domain
logic. Reset logic should assert core_rst_n whenever link_req_rst_not is
transitioned from high to low. It is recommended that you reset your
application logic together with the controller. Asynchronous assertion
with synchronous de-assertion.
Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
pipe_rst_n I Resets controller logic clocked on pipe_clk. Reset logic should assert
pipe_rst_n at same time as core_rst_n and deassert synchronous to
pipe_clk.
Exists: CX_FREQ_STEP_EN
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Clock and Reset Signals
core_pl_rst_n I Resets the controller, except for the PMC module. Upon initial power-up,
core_rst_n is asserted in order to reset the non-auxiliary power domain
logic. Reset logic should assert core_pl_rst_n whenever
link_req_rst_not is transitioned from high to low. It is recommended that
you reset your application logic together with the controller.
Asynchronous assertion with synchronous de-assertion.
Exists: CX_FREQ_STEP_DL_EN
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
app_init_rst I Request from your application to send a hot reset to the upstream port.
The hot reset request is sent when a single cycle pulse is applied to this
pin. In an upstream port, you should set this input to '0'.
Note: This signal is not used by the controller to set the SBR field in the
BRIDGE_CTRL_INT_PIN_INT_LINE_REG register. During the
transition from DL_Active to DL_inactive, assertion of app_init_rst signal
indicates a Surprise Down Error, but setting of SBR field in the
BRIDGE_CTRL_INT_PIN_INT_LINE_REG register through DBI does
not trigger a Surprise Down Error.
Exists: Always
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
training_rst_n O Hot reset from upstream component. When the controller LTSSM
receives two consecutive TS1 ordered sets with the hot_reset bit
asserted, it asserts training_rst_n for one clock cycle. This signal is only
kept for legacy purposes. You should use the link_req_rst_not signal to
reset the controller after a 'hot reset' request. For details hot reset, see
'Generating and Processing Hot Resets (Training Resets)' in the
Databook.
Exists: Always
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
Synopsys, Inc.
aux_clk_active I Indicates that your external clock logic has switched the aux_clk input
from pipe_clk to the platform auxiliary clock.
Exists: Always
Synchronous To: aux_clk_g,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook DBI Interface Signals
dbi_addr - - lbc_dbi_ack
dbi_din - - lbc_dbi_dout
dbi_cs -
dbi_cs2 -
dbi_wr -
dbi_addr[31:0] I Address of the configuration register for the current DBI access:
■ [31:19]: Not used
■ [18:16]: Function number
■ [15:12]: Not used
■ [11:2]: Register address, must be dword-aligned.
■ [1]: Not used
■ [0]: Target of DBI access: 0 to access internal register; 1 to access
external register the ELBI
You can use an address larger than 12 bits dbi_addr when you access
the ELBI interface instead of the Configuration Registers. You can use
up to 32 bits if the controller has been configured for a 32-bit ELBI
address width with the parameter CX_LBC_EXT_AW. For more details,
see 'Local Bus Controller (LBC) and Data Bus Interface (DBI)'.
Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: dbi_cs is asserted
Synopsys, Inc.
dbi_cs2 I Additional chip select that enables writing to BAR mask registers. To
write to a BAR mask register, your application must assert dbi_cs2 in
addition to dbi_cs.
Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: dbi_cs is asserted
dbi_wr[3:0] I Indicates the configuration register access type (read or write). For
writes, dbi_wr also indicates the byte enables:
■ 0000b: Read
■ 0001b: Write byte 0
■ 0010b: Write byte 1
■ 0100b: Write byte 2
■ 1000b: Write byte 3
■ 1111b: Write all bytes
Combinations of byte enables (for example, 0101b) are also valid.
Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: dbi_cs is asserted
lbc_dbi_ack O Indicates that the requested read or write operation to the selected
configuration register is complete. When accessing a non-existent or
Read-Only register, the signal is asserted for one clock cycle, and not
two cycles.
Exists: (!DBI_4SLAVE_POPULATED) && (!SHARED_DBI_ENABLED)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook ELBI Interface Signals
ext_lbc_ack - - lbc_ext_addr
ext_lbc_din - - lbc_ext_dout
- lbc_ext_cs
- lbc_ext_wr
- lbc_ext_rom_access
- lbc_ext_io_access
- lbc_ext_bar_num
ext_lbc_din[(((CX_LBC_NW*32)*NF)-1):0] I Data bus from the external register block. Depending on value of
CX_LBC_NW, there are 32/64/128 bits of ext_lbc_din for each function
in your controller configuration.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ext_lbc_ack is asserted
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lbc_ext_addr[(LBC_EXT_AW-1):0] O Address bus to the external register block. The width of the address bus
is the value you select for the CX_LBC_EXT_AW parameter.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted
lbc_ext_dout[((CX_LBC_NW*32)-1):0] O Write data bus to the external register block, driven to all functions in a
multi-function configuration.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted
lbc_ext_cs[(NF-1):0] O The controller asserts lbc_ext_cs when a received TLP for a read or
write request has an address in the range of your application device, as
determined by the BAR configuration. The width of the lbc_ext_cs signal
is equal to the number of functions in your controller configuration
(CX_NFUNC). That is, there is one lbc_ext_cs bit for each configured
function. The controller de-asserts lbc_ext_cs only after the external
register block acknowledges completion of the access by asserting the
corresponding bit of ext_lbc_ack.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook ELBI Interface Signals
lbc_ext_wr[((4*CX_LBC_NW)-1):0] O Indicates when the external register access is a read or a write. For
writes, lbc_ext_wr also indicates the byte enables.
When CX_LBC_NW = 1:
■ 0000b: Read
■ 0001b: Write byte 0
■ 0010b: Write byte 1
■ 0100b: Write byte 2
■ 1000b: Write byte 3
■ 1111b: Write all bytes
When CX_LBC_NW = 2:
■ 00000000b: Read
■ 00000001b: Write byte 0
■ 00000010b: Write byte 1
■ 00000100b: Write byte 2
■ 00001000b: Write byte 3
■ 00010000b: Write byte 4
■ 00100000b: Write byte 5
■ 01000000b: Write byte 6
■ 10000000b: Write byte 7
■ 11111111b: Write all bytes
Combinations of byte enables (for example, 0011b) are also valid.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted
lbc_ext_rom_access O Indicates that the current ELBI access is for expansion ROM.
Exists: Always
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_ext_cs is asserted
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PCI Express SW Controller Databook CXS Rx FIFO RAM Signals
cxs_rxram_doutb - - cxs_rxram_ena
- cxs_rxram_wea
- cxs_rxram_addra
- cxs_rxram_dina
- cxs_rxram_enb
- cxs_rxram_addrb
- cxs_rxram_addra_par
- cxs_rxram_addrb_par
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PCI Express SW Controller Databook CXS Rx FIFO RAM Signals
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cxs_txram_doutb - - cxs_txram_ena
- cxs_txram_wea
- cxs_txram_addra
- cxs_txram_dina
- cxs_txram_enb
- cxs_txram_addrb
- cxs_txram_addra_par
- cxs_txram_addrb_par
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PCI Express SW Controller Databook CXS Tx FIFO RAM Signals
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PCI Express SW Controller Databook Receive Data Queue RAM Signals
p_dataq_dataout - - p_dataq_addra
- p_dataq_addrb
- p_dataq_addra_par
- p_dataq_addrb_par
- p_dataq_err_synd
- p_dataq_err_addr
- p_dataq_ce
- p_dataq_ue
- p_dataq_datain
- p_dataq_ena
- p_dataq_enb
- p_dataq_wea
p_dataq_dataout[(RADM_Q_DATABITS_O I Read data from port B of the data queue buffer. The width of the read
-1):0] data bus is automatically set according to the datapath width and
number of VCs, as follows:
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_dataq_enb is asserted
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p_dataq_addrb[(RADM_PQ_D_ADDRBIT O Address to port B of the data queue buffer. The width is the same as the
S-1):0] p_dataq_addra width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_dataq_enb is asserted
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PCI Express SW Controller Databook Receive Data Queue RAM Signals
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p_dataq_datain[(RADM_Q_DATABITS-1): O Write data to port A of the data queue buffer. The width is the same as
0] the p_dataq_dataout width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: None,aux_clk_g,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_dataq_wea is asserted
p_dataq_ena[(RADM_Q_D_CTRLBITS-1): O Port A select to the data queue buffer. The controller asserts this at the
0] same time as p_dataq_wea.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Receive Data Queue RAM Signals
p_dataq_enb[(RADM_Q_D_CTRLBITS-1): O Port B read enable to the data queue buffer. Always '1' even when the
0] read port is idle.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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formqram_radm_doutb - - radm_formqram_addra
- radm_formqram_addra_par
- radm_formqram_ena
- radm_formqram_wea
- radm_formqram_dina
- radm_formqram_addrb
- radm_formqram_addrb_par
- radm_formqram_enb
- radm_formqram_err_addr
- radm_formqram_err_synd
- radm_formqram_ce
- radm_formqram_ue
radm_formqram_addra[((NQW*RAM_PW) O Address buses to port A (write port) of the formation queue RAMs,
-1):0] concatenated from RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_ena or radm_formqram_wea is asserted
radm_formqram_addra_par[(NQW-1):0] O Parity bit for address buses to port A (write port) of the formation queue
RAMs, concatenated from RAM 0 to RAM
CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_ena or radm_formqram_wea is asserted
radm_formqram_ena[(NQW-1):0] O Port A selects to the formation queue RAMs, concatenated from RAM 0
to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Receive Formation Queue RAM Signals
radm_formqram_wea[(NQW-1):0] O Port A write enables to the formation queue RAMs, concatenated from
RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
radm_formqram_dina[((NQW*RAM_WD)- O Write data to port A of the formation queue RAMs, concatenated from
1):0] RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: None,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_wea is asserted
radm_formqram_addrb[((NQW*RAM_PW) O Address buses to port B (read port) of the formation queue RAMs,
-1):0] concatenated from RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted
radm_formqram_addrb_par[(NQW-1):0] O Parity bit for address buses to port B (read port) of the formation queue
RAMs, concatenated from RAM 0 to RAM
CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted
radm_formqram_enb[(NQW-1):0] O Port B selects to the formation queue RAMs, concatenated from RAM 0
to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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formqram_radm_doutb[((NQW*RAM_WD) I Read data from port B of the formation queue RAMs, concatenated
-1):0] from RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted
radm_formqram_err_addr[((NQW*RAM_P O Logged error address buses to port B (read port) of the formation queue
W)-1):0] RAMs, concatenated from RAM 0 to RAM
CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted
radm_formqram_err_synd[((NQW*RASDP O Error syndrome for radm formation queue RAMs, concatenated from
_FORMQ_ERR_SYND_WD)-1):0] RAM 0 to RAM CX_RADM_FORMQ_NQW-1.
Exists: (CX_RAM_AT_TOP_IF) && (SNPS_RSVDPARAM_1) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: radm_formqram_enb is asserted
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PCI Express SW Controller Databook Receive Formation Queue RAM Signals
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p_hdrq_dataout - - p_hdrq_addra
- p_hdrq_addrb
- p_hdrq_addra_par
- p_hdrq_addrb_par
- p_hdrq_err_synd
- p_hdrq_err_addr
- p_hdrq_ce
- p_hdrq_ue
- p_hdrq_datain
- p_hdrq_ena
- p_hdrq_enb
- p_hdrq_wea
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PCI Express SW Controller Databook Receive Header Queue RAM Signals
p_hdrq_addrb[(RADM_PQ_H_ADDRBITS O Address to port B of the header queue buffer. The width is the same as
-1):0] the p_hdrq_addra width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_hdrq_enb is asserted
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PCI Express SW Controller Databook Receive Header Queue RAM Signals
p_hdrq_datain[(RADM_PQ_H_DATABITS- O Write data to port A of the header queue buffer. The width is the same
1):0] as the p_hdrq_dataout width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: None,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: p_hdrq_wea is asserted
p_hdrq_ena[(RADM_Q_H_CTRLBITS-1): O Port A select to the header queue buffer. The controller asserts this at
0] the same time as p_hdrq_wea.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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p_hdrq_enb[(RADM_Q_H_CTRLBITS-1): O Port B read enable to the header queue buffer. Always '1' even when the
0] read port is idle.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RADMQ_MODE==0 ?
(RADM_P_QMODE_VC0!=4 || RADM_NP_QMODE_VC0!=4 ||
RADM_CPL_QMODE_VC0!=4) : CX_RADMQ_MODE==2 ||
(CX_RADMQ_MODE==1 && RADM_P_QMODE_VC0!=4))
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Transmit Retry Buffer RAM Signals
retryram_xdlh_data - - xdlh_retryram_addr
- xdlh_retryram_addr_par
- xdlh_retryram_err_synd
- xdlh_retryram_err_addr
- xdlh_retryram_ce
- xdlh_retryram_ue
- xdlh_retryram_data
- xdlh_retryram_we
- xdlh_retryram_en
- xdlh_retrysotram_err_synd
- xdlh_retrysotram_err_addr
- xdlh_retrysotram_ce
- xdlh_retrysotram_ue
xdlh_retryram_addr[(RBUF_PW-1):0] O Address to the retry buffer RAM. The width of the address bus
(RBUF_PW) is automatically set as a function of the retry buffer depth,
which is automatically calculated, or set explicitly by you if you disable
autosizing.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: xdlh_retryram_we or xdlh_retryram_en is asserted
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xdlh_retryram_err_addr[(RBUF_PW-1):0] O Retry RAM address where a protection error has been detected
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: xdlh_retryram_ce or xdlh_retryram_ue is asserted
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PCI Express SW Controller Databook Transmit Retry Buffer RAM Signals
retryram_xdlh_data[(RBUF_WIDTH-1):0] I Read data from the retry buffer RAM. The width is the same as the
xdlh_retryram_data width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
xdlh_retrysotram_err_addr[(SOTBUF_PW- O Retry SOT RAM address where a protection error has been detected
1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1) &&
(CX_RAS_EXT_IF)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: xdlh_retrysotram_ce or xdlh_retrysotram_ue is asserted
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PCI Express SW Controller Databook Transmit Retry SOT Buffer RAM Signals
retrysotram_xdlh_data - - xdlh_retrysotram_waddr
- xdlh_retrysotram_raddr
- xdlh_retrysotram_waddr_par
- xdlh_retrysotram_raddr_par
- xdlh_retrysotram_data
- xdlh_retrysotram_we
- xdlh_retrysotram_en
xdlh_retrysotram_waddr[(SOTBUF_PW-1) O Write address for the SOT buffer RAM. The width of the address bus
:0] (SOTBUF_PW) is automatically set as a function of the SOT buffer
depth, which is automatically calculated.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: xdlh_retrysotram_we is asserted
xdlh_retrysotram_raddr[(SOTBUF_PW-1): O Read address for the SOT buffer RAM. The width of the address bus
0] (SOTBUF_PW) is automatically set as a function of the SOT buffer
depth, which is automatically calculated.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: xdlh_retrysotram_en is asserted
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xdlh_retrysotram_data[(SOTBUF_WD-1):0 O Write data to the SOT buffer RAM. The width of the write data bus is
] automatically set to the width of the retry buffer address bus. (Each
location in the SOT buffer is used to store a retry buffer address.)
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: None,aux_clk,aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: xdlh_retrysotram_we is asserted
xdlh_retrysotram_en O Read enable to the SOT buffer RAM. The controller asserts the SOT
buffer enable when replay is in progress and SOT read data is required.
This signal is low when the SOT buffer is not accessed, thus saving
power.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
retrysotram_xdlh_data[(SOTBUF_WD-1):0 I Read data from the SOT buffer RAM. The width is the same as the
] xdlh_retrysotram_data width.
Exists: (CX_RAM_AT_TOP_IF) && (CX_CXPL_EN)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook MSI Interface Signals
ven_msi_req - - ven_msi_grant
ven_msi_func_num - - cfg_msi_en
ven_msi_tc - - cfg_msi_mask
ven_msi_vector - - cfg_msi_addr
cfg_msi_pending - - cfg_msi_data
- cfg_msi_64
- cfg_multi_msi_en
- cfg_msi_ext_data_en
ven_msi_req I Request from your application to send an MSI when MSI is enabled.
When MSI-X is enabled instead of MSI, assertion of ven_msi_req
causes the controller to generate an MSI-X message. Once asserted,
ven_msi_req must remain asserted until the controller asserts
ven_msi_grant.
Exists: Always
Synchronous To: aux_clk,aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
ven_msi_func_num[(PF_WD-1):0] I The function number of the MSI request. Function numbering starts at
'0'.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msi_req is asserted
ven_msi_tc[2:0] I Traffic Class of the MSI request, valid when ven_msi_req is asserted.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msi_req is asserted
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ven_msi_vector[4:0] I Used to modulate the lower five bits of the MSI Data register when
multiple message mode is enabled.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msi_req is asserted. Valid only when multiple
message mode is enabled for the device through the MSI Control
register.
ven_msi_grant O One-cycle pulse that indicates that the controller has accepted the
request to send an MSI. After asserting ven_msi_grant for one cycle,
the controller does not wait for ven_msi_req to be de-asserted then
reasserted to generate another MSI. When ven_msi_req remains
asserted after the controller asserts ven_msi_grant for one cycle, the
controller generates another MSI.
Exists: Always
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_msi_en[(NF-1):0] O Indicates that MSI is enabled (INTx message is not sent), one bit per
configured function.
Exists: Always
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_msi_mask[((32*NF)-1):0] O Contents of the Per Vector Mask register in the MSI Capability structure.
For each bit that is set, the function is prohibited from sending the
associated message.
Exists: MSI_PVM_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
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PCI Express SW Controller Databook MSI Interface Signals
cfg_msi_addr[((64*NF)-1):0] O Contents of the MSI Lower 32 Bits and Upper 32 Bits Address registers
in the MSI Capability structure. There are 64 bits of cfg_msi_addr for
each configured function.
Exists: MSI_IO
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_msi_data[((32*NF)-1):0] O Contents of the MSI Data register in the MSI Capability structure. There
are 32 bits of cfg_msi_data for each configured function.
Exists: MSI_IO
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_msi_64[(NF-1):0] O The 64-bit Address Capable bit of the MSI Control register in the MSI
Capability structure, one bit for each configured function.
Exists: MSI_IO
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_multi_msi_en[((3*NF)-1):0] O The Multiple Message Enabled field of the MSI Control register in the
MSI Capability structure. There are 3 bits of cfg_multi_msi_en for each
configured function.
Exists: MSI_IO
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook MSI-X Interface Signals
msix_addr - - cfg_msix_en
msix_data - - cfg_msix_func_mask
- cfg_msix_table_size
- cfg_msix_table_bir
- cfg_msix_table_offset
- cfg_msix_pba_bir
- cfg_msix_pba_offset
cfg_msix_en[(NF-1):0] O The MSI-X Enable bit of the MSI-X Control register in the MSI-X
Capability structure. There is 1 bit of cfg_msix_en for each configured
function.
Exists: (MSIX_CAP_ENABLE) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_msix_func_mask[(NF-1):0] O The function Mask bit of the MSI-X Control register in the MSI-X
Capability structure. There is 1 bit of cfg_msix_func_mask for each
configured function.
Exists: (MSIX_CAP_ENABLE) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_msix_table_size[((11*NF)-1):0] O The MSI-X Table Size field of the MSI-X Control register in the MSI-X
Capability structure. There are 11 bits of cfg_msix_table_size for each
configured function.
Exists: (MSIX_CAP_ENABLE) && (MSIX_IO) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_msix_table_bir[((3*NF)-1):0] O Table BAR Indicator Register (BIR) field of the MSI-X Table Offset and
BIR register in the MSI-X Capability structure. There are 3 bits of
cfg_msix_table_bir for each configured function.
Exists: (MSIX_CAP_ENABLE) && (MSIX_IO) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_msix_table_offset[((29*NF)-1):0] O Table Offset field of the MSI-X Table Offset and BIR register in the
MSI-X Capability structure. There are 29 bits of cfg_msix_table_offset
for each configured function.
Exists: (MSIX_CAP_ENABLE) && (MSIX_IO) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook MSI-X Interface Signals
cfg_msix_pba_bir[((3*NF)-1):0] O PBA BIR field of the MSI-X PBA Offset and BIR register in the MSI-X
Capability structure. There are 3 bits of cfg_msix_pba_bir for each
configured function.
Exists: (MSIX_CAP_ENABLE) && (MSIX_IO) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_msix_pba_offset[((29*NF)-1):0] O PBA Offset field of the MSI-X PBA Offset and BIR register in the MSI-X
Capability structure. There are 29 bits of cfg_msix_pba_offset for each
configured function.
Exists: (MSIX_CAP_ENABLE) && (MSIX_IO) && (!MSIX_TABLE_EN)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
ven_msg_fmt - - ven_msg_grant
ven_msg_type -
ven_msg_tc -
ven_msg_td -
ven_msg_ep -
ven_msg_attr -
ven_msg_len -
ven_msg_func_num -
ven_msg_tag -
ven_msg_code -
ven_msg_data -
ven_msg_req -
ven_msg_fmt[1:0] I The Format field for the vendor-defined Message TLP. Should be set to
0x1.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted
ven_msg_tc[2:0] I The Traffic Class field for the vendor-defined Message TLP.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted
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PCI Express SW Controller Databook VMI Signals
ven_msg_td I The TLP Digest (TD) bit for the vendor-defined Message TLP, valid
when ven_msg_req is asserted.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted
ven_msg_ep I The Poisoned TLP (EP) bit for the vendor-defined Message TLP.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted
ven_msg_len[9:0] I The Length field for the vendor-defined Message TLP (indicates length
of data payload in dwords).
Should be set to 0x0.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted
Synopsys, Inc.
ven_msg_data[63:0] I Third and fourth dwords of the Vendor Defined Message header where:
■ Bytes 8-11 (third header dword) =ven_msg_data[63:32]
■ Bytes 12-15 (fourth header dword) =ven_msg_data[31:0], where
ven_msg_data[7:0] =byte 15
For more details, see the 'Endianness' advanced information chapter.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: ven_msg_req is asserted
ven_msg_grant O One-cycle pulse that indicates that the controller has accepted the
request to send the vendor-defined Message.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Power Budgeting Signals
cfg_pwr_budget_data_reg - - cfg_pwr_budget_data_sel_reg
cfg_pwr_budget_func_num - - cfg_pwr_budget_sel
cfg_pwr_budget_sel[(NF-1):0] O One cycle pulse signal indicates new contents in Data Select Register.
Something changed the value of Data Select Register, so your
application should take a look at the new value and provide the updated
Data Register value corresponding to it.
Exists: PWR_BUDGET_CAP_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
app_dpc_triggered -
app_dpc_trig_en -
app_dpc_trig_status -
app_dpc_trig_en[1:0] I DPC trigger Enable from the application and should be taken from the
corresponding external DPC Control register field, DPC Trigger Enable.
Encodings are:
■ 00b: DPC is disabled.
■ 01b: DPC is enabled and is triggered when the Downstream Port
detects an unmasked uncorrectable error or when the Downstream
Port receives an ERR_FATAL Message.
■ 10b: DPC is enabled and is triggered when the Downstream Port
detects an unmasked uncorrectable error or when the Downstream
Port receives an ERR_NONFATAL or ERR_FATAL Message.
■ 11b: Reserved.
Exists: CX_EXTDPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
app_dpc_trig_status I DPC trigger status from the application and should be taken from the
corresponding external DPC Status register field, DPC Trigger Status.
Exists: CX_EXTDPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: CCIX Configuration/Control/Status Signals
ccix_tlp_disable - - pm_current_data_rate
- cfg_ccix_esm_enable
- cfg_ccix_esm_data_rate0
- cfg_ccix_esm_data_rate1
- cfg_ccix_opt_tlp_sup
- cfg_ccix_vc_resource
- cfg_ccix_opt_tlp_en
- cfg_ccix_tc_enable
cfg_ccix_esm_data_rate0[6:0] O Contents of the ESM Data Rate0 field of ESM Control Register.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_ESM_SUPPORT)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_ccix_esm_data_rate1[6:0] O Contents of the ESM Data Rate1 field of ESM Control Register.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_ESM_SUPPORT)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_ccix_opt_tlp_sup O CCIX optimized TLP format supported field of CCIX Transaction Layer
Capabilities Register.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_ccix_tc_enable[7:0] O A bus that indicates which of the TCs are mapped to CCIX VC.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE)
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: CCIX Configuration/Control/Status Signals
ccix_tlp_disable I Disable the support of CCIX TLP. This is a boot strap signal and it needs
to be valid and static during reset.
Exists: ((CX_CPCIE_ENABLE)) && (CX_CCIX_ENABLE) &&
(CX_CCIX_INTERFACE_ENABLE)
Synchronous To: core_clk,radm_clk_g,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
app_link_cap_mask - - cfg_10b_tag_req_en
cdm_reg_chk_test_en - - cfg_vf_pasid_en
- cfg_vf_pasid_execute_perm_en
- cfg_vf_pasid_priv_mode_en
- cfg_atomic_req_en
- cfg_atomic_egress_block
- cfg_obff_en
- cfg_ltr_m_en
- cfg_ltr_max_latency
- cfg_disable_ltr_clr_msg
- cfg_ari_fwd_en
- cfg_pwr_ind
- cfg_atten_ind
- cfg_pwr_ctrler_ctrl
- cfg_exp_rom_start
- cfg_exp_rom_limit
- cfg_bus_master_en
- cfg_mem_space_en
- cfg_max_rd_req_size
- cfg_ext_tag_en
- cfg_pm_no_soft_rst
- cfg_pbus_num
- cfg_pbus_dev_num
- cfg_bridge_crs_en
- cfg_vc_enable
- cfg_vc_struc_vc_id_map
- cfg_vc_id_vc_struc_map
- cfg_tc_enable
- cfg_tc_struc_vc_map
- cfg_mem_base
- cfg_mem_limit
- cfg_pref_mem_base
- cfg_pref_mem_limit
- cfg_io_limit_upper16
- cfg_io_base_upper16
- cfg_io_base
- cfg_io_limit
- cfg_io_space_en
- cfg_2ndbus_num
- cfg_subbus_num
- cfg_end2end_tlp_pfx_blck
- cfg_no_snoop_en
- cfg_relax_order_en
- cfg_ats_stu
- cfg_ats_cache_en
- cfg_acs_validation_en
- cfg_acs_at_blocking_en
- cfg_acs_p2p_req_redirect_en
- cfg_acs_p2p_compl_redirect_en
- cfg_acs_up_forward_en
- cfg_acs_p2p_egress_ctrl_en
- cfg_acs_p2p_direct_transl_en
- cfg_acs_egress_ctrl_vec
- acs_vf_p2p_req_redirect_en
- acs_vf_p2p_compl_redirect_en
- acs_vf_p2p_egress_ctrl_en
- acs_vf_p2p_direct_transl_en
- acs_vf_egress_ctrl_vec
- cfg_acs_func_grp_en
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PCI Express SW Controller Databook SII: Configuration Information Signals
- cfg_ari_func_grp
- cfg_vf_ari_func_grp
- cdm_reg_chk_logic_err
- cdm_reg_chk_cmp_err
- cdm_reg_chk_cmplt
- rbar_ctrl_update
- cfg_rbar_size
- vf_rbar_ctrl_update
- cfg_vf_rbar_size
- cfg_hp_slot_ctrl_access
- cfg_dll_state_chged_en
- cfg_cmd_cpled_int_en
- cfg_hp_int_en
- cfg_pre_det_chged_en
- cfg_mrl_sensor_chged_en
- cfg_pwr_fault_det_en
- cfg_atten_button_pressed_en
- if_timeout_status
cfg_vf_pasid_en[(INT_NVF-1):0] O The value of the PASID Enable field in each VF PASID Control Register.
Exists: (CX_SRIOV_ENABLE) && (VF_PASID_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_vf_pasid_execute_perm_en[(INT_NV O The value of the Execute Permission Enable field in each VF PASID
F-1):0] Control Register.
Exists: (CX_SRIOV_ENABLE) && (VF_PASID_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_vf_pasid_priv_mode_en[(INT_NVF-1): O The value of the Privileged Mode Enable field in each VF PASID Control
0] Register.
Exists: (CX_SRIOV_ENABLE) && (VF_PASID_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_obff_en[1:0] O The OBFF Enable field of the Device Control 2 register of function 0.
Exists: CX_OBFF_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_ltr_m_en O The LTR Mechanism Enable field of the Device Control 2 register of
function 0.
Exists: CX_LTR_M_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Configuration Information Signals
cfg_ari_fwd_en[(NF-1):0] O ARI Forwarding Enabled (DSP). Indicates that the port is ARI-aware
and that the Alternate Routing ID (ARI) Capability is enabled.
Exists: CX_ARI_FWD_CAP
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_pwr_ind[((2*NF)-1):0] O Controls the system power indicator (from bits [9:8] of the Slot Control
register), per function:
■ 00b: Reserved
■ 01b: On
■ 10b: Blink
■ 11b: Off
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_atten_ind[((2*NF)-1):0] O Controls the system attention indicator (from bits [7:6] of the Slot Control
register), per function:
■ 00b: Reserved
■ 01b: On
■ 10b: Blink
■ 11b: Off
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_pwr_ctrler_ctrl[(NF-1):0] O Controls the system power controller (from bit 10 of the Slot Control
register), per function:
■ 0: Power On
■ 1: Power Off
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Configuration Information Signals
cfg_mem_space_en[(NF-1):0] O The state of the Memory Space Enable bit in the PCI-compatible
Command register. There is 1 bit of cfg_mem_space_en assigned to
each configured function.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_pm_no_soft_rst[(NF-1):0] O This is the value of the No Soft Reset bit in the Power Management
Control and Status Register. When set, you should not reset any
controller registers when transitioning from D3hot to D0. Therefore, you
should not assert the non_sticky_rst_n and sticky_rst_n inputs.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_pbus_num[(BUSNUM_WD-1):0] O The primary bus number assigned to the function. The number of bits
depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN:
■ If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0, there are eight
bits of cfg_pbus_num ([7:0]), regardless of the number of functions.
■ If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =1, there are eight
bits of cfg_pbus_num for each configured function.
Exists: Always
Synchronous To: core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_pbus_dev_num[(DEVNUM_WD-1):0] O The device number assigned to the function. The number of bits
depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN:
■ If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0, there are five
bits of cfg_pbus_dev_num ([4:0]), regardless of the number of func-
tions.
■ If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =1, there are five
bits of cfg_pbus_dev_num for each configured function.
Exists: Always
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_bridge_crs_en[(NF-1):0] O Bridge Configuration Retry Enable. Indicates the status of the Bridge
Configuration Retry Enable bit in the Device Control register. Applicable
only for PCI Express to PCI(-X) bridge devices
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Configuration Information Signals
app_link_cap_mask[5:0] I Link Capability Mask. Masks the Link Capability that the controller has
been advertised. Allows your application to drive a bit mask for the value
in the "Link Mode Enable" field of the "Port Link Control Register" (Port
Logic register at address 0x710). The masked value is used by LTSSM
to determine which lanes to detect during the initial phase of training.
Typical value is 6'h3F.
Exists: Always
Synchronous To: None,perbitclk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Configuration Information Signals
cfg_mem_base[((16*NF)-1):0] O Configured Memory Base register. The contents of the Memory Base
register from the PCIe type 1 configuration space. Memory and I/O
ranges are programmed in each downstream switch port to route
request packets.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_mem_limit[((16*NF)-1):0] O Configured Memory Limit register. The contents of the Memory Limit
register from the PCIe type 1 configuration space. Memory and I/O
ranges are programmed in each downstream switch port to route
request packets.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_io_limit_upper16[((16*NF)-1):0] O Configured I/O Limit Upper 16 bits. The contents of the I/O Limit Upper
16 Bits register from the PCIe type 1 configuration space. Memory and
I/O ranges are programmed in each downstream switch port to route
request packets.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_io_base_upper16[((16*NF)-1):0] O Configured I/O Base Upper 16 bits. The contents of the I/O Base Upper
16 Bits register from the PCIe type 1 configuration space. Memory and
I/O ranges are programmed in each downstream switch port to route
request packets.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_io_base[((8*NF)-1):0] O Configured I/O Base register. The contents of the I/O Base register from
the PCIe type 1 configuration space. Memory and I/O ranges are
programmed in each downstream switch port to route request packets.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_io_limit[((8*NF)-1):0] O Configured I/O Base register. The contents of the I/O Limit register from
the PCIe type 1 configuration space. Memory and I/O ranges are
programmed in each downstream switch port to route request packets.
Exists: Always
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Configuration Information Signals
cfg_io_space_en[(NF-1):0] O Configured I/O Space Enable. The contents of the I/O Space Enable bit
in the PCIe Type 1 configuration space. Memory and I/O ranges are
programmed in each downstream switch port to route request packets.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_end2end_tlp_pfx_blck[(NF-1):0] O The value of the End-End TLP Prefix Blocking field in the Device Control
2 register.
Exists: CX_TLP_PREFIX_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Configuration Information Signals
cfg_acs_validation_en O Contents of the "ACS Source Validation Enable (V)" field (ACS) in the
ACS_CAPABILITIES_CTRL_REG register. When set, the component
validates the Bus Number from the requester ID of upstream requests
against the secondary/subordinate Bus Numbers.
Exists: CX_ACS_ENABLE
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_acs_at_blocking_en O Contents of the "ACS Translation Blocking Enable (B)" field (ACS) in the
ACS_CAPABILITIES_CTRL_REG register. When set, the component
blocks all upstream memory requests whose Address Translation (AT)
field is not set to the default value.
Exists: CX_ACS_ENABLE
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_acs_p2p_req_redirect_en[(NF-1):0] O Contents of the "ACS P2P Request Redirect Enable (R)" field (ACS) in
the ACS_CAPABILITIES_CTRL_REG register. It determines when the
component redirects peer-to-peer requests upstream.
Exists: CX_ACS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_acs_p2p_compl_redirect_en[(NF-1):0] O Contents of the "ACS P2P Completion Redirect Enable (C)" field (ACS)
in the ACS_CAPABILITIES_CTRL_REG register. It determines when
the component redirects peer-to-peer completions upstream.
Exists: CX_ACS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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cfg_acs_up_forward_en O Contents of the "ACS Upstream Forwarding Enable (U)" field (ACS) in
the ACS_CAPABILITIES_CTRL_REG register. When set, the
component forwards upstream any request or completion TLPs it
receives, that were redirected upstream by a component lower in the
hierarchy.
Exists: CX_ACS_ENABLE
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_acs_p2p_egress_ctrl_en[(NF-1):0] O Contents of the "ACS P2P Egress Control Enable (E)" field (ACS) in the
ACS_CAPABILITIES_CTRL_REG register. It determines when to allow,
disallow, or redirect peer-to-peer requests.
Exists: CX_ACS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_acs_p2p_direct_transl_en[(NF-1):0] O Contents of the "ACS Direct Translated P2P Enable (T)" field (ACS) in
the ACS_CAPABILITIES_CTRL_REG register. It overrides the ACS
P2P Request Redirect and ACS P2P Egress Control mechanisms with
peer-to-peer Memory Requests whose Address Translation (AT) field
indicates a translated address.
Exists: CX_ACS_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_acs_egress_ctrl_vec[((ACS_CTRL_V O Contents of the "ACS Egress Control" Register. The width is defined by
EC_WD*NF)-1):0] ACS_CTRL_VEC_WD, per-function. ACS_CTRL_VEC_WD is the
largest egress control vector size of all functions.
Exists: (CX_ACS_ENABLE) && ([<functionof>
CX_ACS_P2P_EGRESS_CTRL])
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Configuration Information Signals
acs_vf_p2p_req_redirect_en[(INT_NVF-1) O Contents of the "ACS P2P Request Redirect Enable (R)" field (ACS) in
:0] the VF_ACS_CAPABILITIES_CTRL_REG register. It determines when
the component redirects peer-to-peer requests upstream.
Exists: (CX_ACS_ENABLE) && (VF_ACS_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
acs_vf_p2p_compl_redirect_en[(INT_NVF O Contents of the "ACS P2P Completion Redirect Enable (C)" field (ACS)
-1):0] in the VF_ACS_CAPABILITIES_CTRL_REG register. It determines
when the component redirects peer-to-peer completions upstream.
Exists: (CX_ACS_ENABLE) && (VF_ACS_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
acs_vf_p2p_egress_ctrl_en[(INT_NVF-1): O Contents of the "ACS P2P Egress Control Enable (E)" field (ACS) in the
0] VF_ACS_CAPABILITIES_CTRL_REG register. It determines when to
allow, disallow, or redirect peer-to-peer Requests.
Exists: (CX_ACS_ENABLE) && (VF_ACS_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
acs_vf_p2p_direct_transl_en[(INT_NVF-1) O Contents of the "ACS Direct Translated P2P Enable (T)" field (ACS) in
:0] the VF_ACS_CAPABILITIES_CTRL_REG register. It overrides the ACS
P2P Request Redirect and ACS P2P Egress Control mechanisms with
peer-to-peer memory requests whose Address Translation (AT) field
indicates a translated address.
Exists: (CX_ACS_ENABLE) && (VF_ACS_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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acs_vf_egress_ctrl_vec[((ACS_CTRL_VE O Contents of the "VF ACS Egress Control Vector" Register. The size
C_WD*INT_NVF)-1):0] ACS_CTRL_VEC_WD is the largest egress control vector size of all
functions.
Exists: (CX_ACS_ENABLE) && (VF_ACS_ENABLE) && ([<functionof>
CX_ACS_P2P_EGRESS_CTRL])
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_vf_ari_func_grp[((3*INT_NVF)-1):0] O Contents of the "VF ARI Function Group [2:0]" settings, per VF.
Exists: VF_ACS_FUNC_GRP
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cdm_reg_chk_test_en I Signal to enter test mode in the Register Checking Logic. u_cdm_b is
not be written to when this signal is high. Allows a value to be written to
u_cdm to compare against the previous value in u_cdm_b
Exists: CX_CDM_REG_CHK_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Configuration Information Signals
cdm_reg_chk_logic_err O Signal to indicate that there is an Error in the Register Checking Logic.
Exists: CX_CDM_REG_CHK_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cdm_reg_chk_cmp_err O Signal to indicate that the register values read from both CDM's do not
match.
Exists: CX_CDM_REG_CHK_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
rbar_ctrl_update[(NF-1):0] O Indicates that a resizable BAR control register has been updated: 1 bit
per Physical function.
Exists: CX_RBARS_INCLUDED
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_rbar_size[((NF*(6*6))-1):0] O BAR size field from each of the resizable BAR control registers, per
function. For BARs that are not resizable the corresponding bits in
cfg_rbar_size are set to 0.
Exists: CX_RBARS_INCLUDED
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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vf_rbar_ctrl_update[(NF-1):0] O Indicates that a resizable VF BAR control register has been updated: 1
bit per Physical function.
Exists: (CX_RBARS_INCLUDED) && (CX_VF_RBARS_INCLUDED)
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_vf_rbar_size[((NF*(6*6))-1):0] O BAR size field from each of the resizable VF BAR control registers, per
function. For BARs that are not resizable, the corresponding bits in
cfg_vf_rbar_size are set to 0.
Exists: (CX_RBARS_INCLUDED) && (CX_VF_RBARS_INCLUDED)
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Configuration Information Signals
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PCI Express SW Controller Databook SII: Debug Signals
- rdlh_link_up
- rtlh_rfc_upd
- rtlh_rfc_data
- radm_q_not_empty
- radm_qoverflow
- cxpl_debug_info
- cxpl_debug_info_ei
rdlh_link_up O Data link layer up/down indicator: This status from the flow control
initialization state machine indicates that flow control has been initiated
and the Data link layer is ready to transmit and receive packets. For
multi-VC designs, this signal indicates status for VC0 only.
■ 1: Link is up
■ 0: Link is down
Exists: Always
Synchronous To: aux_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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rtlh_rfc_upd[(RX_NDLLP-1):0] O Indicates that the controller received a flow control update DLLP. Used
for applications that implement flow Control outside the controller.
■ For the 32 and 64-bit versions of the controller, RX_NDLLP =1 and
the data from the flow control update DLLP is available rtlh_rfc_-
data[31:0].
■ For the 128-bit versions of the controller, RX_NDLLP =2 because it
is possible to receive two flow control update DLLPs in one clock
cycle. In this case, assertion of one bit indicates one flow control
update DLLP was received and assertion of both bits indicates two
flow control update DLLPs were received. Each bit corresponds to
one dword rtlh_rfc_data: bit [0] indicates valid data flow control
update data rtlh_rfc_data[31:0] and bit [1] indicates valid data flow
control update data rtlh_rfc_data[63:32]. The controller only asserts
rtlh_rfc_upd[1] when two flow control update DLLPs are received in
the same clock cycle.
■ For the 256-bit versions of the controller, RX_NDLLP =4 because it
is possible to receive four flow control update DLLPs in one clock
cycle. In this case, assertion of one bit indicates one flow control
update DLLP was received, assertion of two bits indicates two flow
control update DLLPs were received, and so on. Each bit corre-
sponds to one dword rtlh_rfc_data: bit [0] indicates valid data flow
control update data rtlh_rfc_data[31:0] and bit [3] indicates valid data
flow control update data rtlh_rfc_data[255:224]. The controller only
asserts add four bits when four flow control update DLLPs are
received in the same clock cycle.
Exists: Always
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
rtlh_rfc_data[((32*RX_NDLLP)-1):0] O The data from a received flow control update DLLP. The width and
contents of rtlh_rfc_data depend the value of RX_NDLLP which is
defined in the description of rtlh_rfc_upd.
Exists: Always
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: rtlh_rfc_upd is asserted
radm_q_not_empty[(NVC-1):0] O Level indicating that the receive queues contain TLP header/data.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High indicates data in queues
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Debug Signals
radm_qoverflow[(NVC-1):0] O Pulse indicating that one or more of the P/NP/CPL receive queues have
overflowed. There is a 1-bit indication for each configured virtual
channel. You can connect this output to your internal error reporting
mechanism.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High pulse indicates overflow
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Debug Signals
cxpl_debug_info_ei[15:0] O State of selected internal signals in relation to electrical idle (EI) at the
receiver. The encoding of the bits is as follows:
Group 1(pulse) - information about received ordered sets:
■ [0]: EIOS detected
Group 2(level) - LTSSM is in one of the states that depend rxelecidle =0:
■ [1]: L1
■ [2]: L2
■ [3]: RxL0s
■ [4]: Disabled
■ [5]: Detect.Quiet
■ [6]: Polling.Active (Reserved for M-PCIe)
■ [7]: Polling.Compliance (Reserved for M-PCIe)
Group 3(level) - LTSSM is in one of the states that depend rxelecidle =1:
■ [8]: LTSSM is in a transitory state prior to L1 or L2
■ [9]: LTSSM is in a transitory state prior to Disabled
■ [10]: LTSSM is in Loopback.Active as a Slave at Gen1
■ [11]: LTSSM is in Polling.Active (Reserved for M-PCIe)
Group 4(pulse) - LTSSM state transitions with EI inferred:
■ [12]: LTSSM enters Recovery from L0 with EI inferred, first row in
base spec Table 4-11
■ [13]: LTSSM enters Recovery.Speed from Recovery.RcvrCfg with EI
inferred, second row in Table 4-11 of PCI Express Specifica-
tion(Reserved for M-PCIe)
■ [14]: EI inferred while LTSSM in Recovery.Speed, third/fourth rows
in base spec Table 4-11 (Reserved for M-PCIe)
■ [15]: EI inferred while LTSSM in Loopback.Active as a slave, fifth row
in base spec Table 4-11 (Reserved for M-PCIe)
Exists: Always
Synchronous To: perbitclk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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diag_ctrl_bus - - diag_status_bus
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PCI Express SW Controller Databook SII: Diagnostic Control Signals
diag_status_bus[CX_DIAG_STATUS_BUS O Diagnostic Status Bus. Contains all of the important status signals from
_WD-1:0] each controller module. The individual diagnostic sub-buses and their
corresponding signals are listed below in the order from least significant
bit to most significant bit (with respect to the entire diagnostic bus
group). Therefore, diag_status_bus[0] is rtfcgen_incr_amt[0]. The
parameter macros will be replaced by actual parameter values in the
configured IP-XACT and coreConsultant report (DocBook XML and
HTML) files.
Data Link Layer Diagnostic Signals
■ rtfcgen_incr_amt[9*NHQ-1:0] = Payload flow control credits
consumed. NOTE: hdr credits consumed is always 1
■ rtfcgen_incr_enable[NHQ-1:0] = Header flow control credit
consumed
■ rtfcgen_fctype[2*NHQ-1:0] = Flow control type consumed (P=0,
NP=1, CPL=2)
■ rtcheck_rtfcgen_vc[3*NHQ-1:0] = Virtual channel of received TLP
■ xdlh_xtlh_halt = Layer2 is not accepting data to transmit this cycle
■ xtlh_xdlh_data[TRGT_DATA_PROT_WD+(NW*32)-1:0] = Transmit
data at the interface between Layer3 and Layer2. If RASDP is
enabled, includes the ECC or parity protection code bits.
■ xtlh_xdlh_badeot[NW-1:0] = Nullify this transmit TLP (invert CRC,
append EDB)
■ xtlh_xdlh_eot[NW-1:0] = Transmit End of TLP this cycle
■ xtlh_xdlh_sot[NW-1:0] = Transmit Start of TLP this cycle
■ ecrc_err_asserted = End-to-end CRC corrupted for this packet
■ lcrc_err_asserted = Link CRC corrupted for this packet
■ xmlh_xdlh_halt = PHY Layer not accepting data this cycle
■ xdlh_xmlh_data[32*NW-1:0] = Transmit packet payload (completely
framed)
■ xdlh_xmlh_sdp[NW-1:0] = Transmit Start of DLLP (per dword)
■ xdlh_xmlh_stp[NW-1:0] = Transmit Start of TLP (per dword)
■ xdlh_xmlh_eot[NW-1:0] = Transmit end of TLP/DLLP (per dword)
■ rdlh_xdlh_req_acknack_seqnum[11:0] = Sequence Number for
ACK/NAK DLLP
■ rdlh_xdlh_req2send_nack = DataLink Layer request to send NAK
■ rdlh_xdlh_req2send_ack_due2dup = Request to send ACK due to
duplicate TLP
■ rdlh_xdlh_req2send_ack = DataLink Layer request to send ACK
■ rdlh_xdlh_rcvd_acknack_seqnum[11:0] = Sequence number corre-
sponding to NAK/ACK
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PCI Express SW Controller Databook SII: Diagnostic Control Signals
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❑ 1: TRGT0
❑ 2: TRGT1
❑ 3: Reserved
❑ 1: TRGT0
❑ 2: TRGT1
❑ 3: Reserved
diag_status_bus[CX_DIAG_STATUS_BUS O... ■ form_filt_dllp_err = This TLP has a DataLink Layer Error (for
_WD-1:0]...(cont....) . example, LCRC)
■ form_filt_eot = End of TLP received this cycle
■ form_filt_dwen[NW-1:0] = Dword enables
■ form_filt_data[32*NW-1:0] = Packet data from receive Transaction
Layer
■ form_filt_dv = Packet is in payload stage
■ form_filt_hdr[127:0] = Header data (size of stored header is configu-
rable)
■ form_filt_hv = Information to the receive packet filter block is valid
RADM Diagnostic Dual Bus Selector.
■ form_filt_formation = Indicates which TLP was received first by the
controller for 256-bit configurations.
❑ 1: TLP #0 received first, see "RADM Diagnostic Bus 1"
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PCI Express SW Controller Databook SII: Electromechanical Signals
sys_atten_button_pressed - - cfg_eml_control
sys_pre_det_state -
sys_mrl_sensor_state -
sys_pwr_fault_det -
sys_mrl_sensor_chged -
sys_pre_det_chged -
sys_cmd_cpled_int -
sys_eml_interlock_engaged -
nhp_pm_pme -
sys_atten_button_pressed[(NF-1):0] I Attention Button Pressed. Indicates that the system attention button was
pressed, sets the Attention Button Pressed bit in the Slot Status
Register. There is a separate sys_atten_button_pressed input bit for
each function in your controller configuration.
Exists: Always
Synchronous To: aux_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
sys_pre_det_state[(NF-1):0] I Presence Detect State. Indicates whether or not a card is present in the
slot:
■ 0: Slot is empty
■ 1: Card is present in the slot
There is a separate sys_pre_det_state input bit for each function in your
controller configuration.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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sys_pwr_fault_det[(NF-1):0] I Power Fault Detected. Indicates the power controller detected a power
fault at this slot. There is a separate sys_pwr_fault_det input bit for each
function in your controller configuration.
Exists: Always
Synchronous To: aux_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
sys_mrl_sensor_chged[(NF-1):0] I MRL Sensor Changed. Indicates that the state of MRL sensor has
changed. There is a separate sys_mrl_sensor_chged input bit for each
function in your controller configuration.
Exists: Always
Synchronous To: aux_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
sys_pre_det_chged[(NF-1):0] I Presence Detect Changed. Indicates that the state of card present
detector has changed. There is a separate sys_pre_det_chged input bit
for each function in your controller configuration.
Exists: Always
Synchronous To: aux_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Electromechanical Signals
nhp_pm_pme[(NF-1):0] I Native Hot-Plug Event. Enables your application to notify the controller
of a native Hot-Plug event (applicable only in D1, D2, or D3hot). The
controller wakes up the device upon detecting a rising edge
nhp_pm_pme.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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app_drs_ready - - cfg_drs_msi
app_pf_frs_ready - - cfg_up_drs_to_frs
- pf_frs_grant
cfg_drs_msi[(NF-1):0] O DRS Message Received Interrupt Pulse. The DSP controller asserts the
cfg_drs_msi output when all of the following are true:
■ It receives a DRS message
■ PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CON-
TROL_LINK_STATUS_REG is 2'b01
■ MSI or MSI-X is enabled
Exists: CX_RN_DRS_SUPPORTED
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_up_drs_to_frs[(NF-1):0] O DRS to FRS Pulse. The DSP controller asserts the cfg_up_drs_to_frs
output and sends an FRS message with the reason code set to 'DRS
Message Received' when:
■ It receives a DRS message, and
■ PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CON-
TROL_LINK_STATUS_REG is 2'b10
Exists: (CX_RN_DRS_SUPPORTED) &&
(CX_RN_FRS_SUPPORTED)
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: FRS/DRS Messaging Signals
pf_frs_grant[(NF-1):0] O Indicator of when an FRS message for this function has been scheduled
for transmission.
Exists: CX_RN_FRS_SUPPORTED
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High (One clock pulse)
Validated by: app_pf_frs_ready asserted
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rx_lane_flip_en - - cfg_vf_bme
tx_lane_flip_en - - cxs_ltssm_enable
app_sris_mode -
phy_type -
app_ltssm_enable -
device_type -
app_req_retry_en -
app_pf_req_retry_en -
app_dbi_ro_wr_disable -
rx_lane_flip_en I Performs manual lane reversal for receive lanes. For use when
automatic lane reversal does not occur because lane 0 is not detected.
In most cases, rx_lane_flip_en should be wired to a static value at the
chip level. For more details, see 'Lane Reversal and Broken Lanes'. This
signal is only used in Conventional PCIe mode. When in M-PCIe mode,
mpcie_rx_lane_flip_en is used.
Exists: CX_LANE_FLIP_CTRL_EN
Synchronous To:
aux_clk,aux_clk_g,core_clk_ug,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
tx_lane_flip_en I Performs manual lane reversal for transmit lanes. For use when
automatic lane reversal does not occur because lane 0 is not detected.
In most cases, tx_lane_flip_en should be wired to a static value at the
chip level. For more details, see 'Lane Reversal and Broken Lanes'. This
signal is only used in Conventional PCIe mode. When in M-PCIe mode,
mpcie_tx_lane_flip_en is used.
Exists: CX_LANE_FLIP_CTRL_EN
Synchronous To:
aux_clk,aux_clk_g,core_clk_ug,pipe_clk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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cfg_vf_bme[(INT_NVF-1):0] O Bus master enable bit from the Control Register in the PCI header of
each VF. Each bit field corresponds to one of the NVF virtual functions.
You can use the cfg_start_vfi output signal or the VF Index in 'Bus
Numbering Overview' index the corresponding bit field for a particular
VF.
Exists: (CX_SRIOV_ENABLE) && (INTERNAL_VF_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
phy_type I Indicates the PCIe operating mode of the controller. When you configure
the controller to support both Conventional PCIe and M-PCIe modes by
choosing the Selectable PHY setting (CX_PCIE_MODE =2), then you
must indicate to the controller which mode to operate in.
■ 1'b0: Conventional PCIe Mode.
■ 1'b1: M-PCIe mode
You have to completely reset the controller after you change this input.
The result is undefined if this signal is changed without reset.
Exists: CX_PCIE_MODE == DUAL_CMPCIE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
Synopsys, Inc.
app_ltssm_enable I Driven low by your application after cold, warm or hot reset to hold the
LTSSM in the Detect state until your application is ready for the link
training to begin. When your application has finished reprogramming the
controller configuration registers using the DBI, it asserts
app_ltssm_enable to allow the LTSSM to continue link establishment.
Can also be used to delay hot resetting of the controller until you have
read out any register status.
Cold Reset
■ Optionally hold LTSSM and delay link training, so that you can repro-
gram some registers through DBI.
❑ Set app_ltssm_enable =0 before your application de-asserts
Power-On Reset (power_up_rst_n). Best way is to set app_ltss-
m_enable =0 at power-up or at assertion of core_rst_n.
❑ Wait for de-assertion of core_rst_n, sticky_rst_n, and non_-
sticky_rst_n.
❑ Write any register through DBI.
■ Optionally hold LTSSM and delay link training, so that you can repro-
gram some registers through DBI.
❑ Set app_ltssm_enable =0 immediately (combinatorially) upon
falling edge of core_rst_n.
❑ Write any register through DBI.
■ Note:For Hot Reset, you can do both or either of the above (delay
reset and/or delay link training). If you do both, you must do in order
presented.
Note:You must only de-assert this signal using one of the recommended
timings described in the "Reset Requirements" section in the
Architecture chapter of the Databook
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PCI Express SW Controller Databook SII: General Core Control Signals
device_type[3:0] I Device/port type. Indicates the specific type of this PCI Express
function. It is also used to set the 'Device/Port Type' field of the 'PCI
Express Capabilities Register'. The controller uses this input to
determine the operating mode of the controller at run time. Defined
encodings are:
■ 4'b0101: Upstream port of switch
■ 4'b0110: downstream port of switch
All other encodings (including those for PCI/PCI-X bridges and RC
Integrated endpoint) are not supported. If CX_CROSSLINK_ENABLE is
defined and when smlh_crosslink_active is '1' then the value
device_type is modified as follows before being used internally in the
controller:
■ if device_type =4'b0101 then device_type =4'b0110
■ if device_type =4'b0110 then device_type =4'b0101
Exists: Always
Synchronous To:
aux_clk,aux_clk_g,radm_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: General Core Control Signals
Synopsys, Inc.
upstream_surprise_down - - radm_vendor_msg
- radm_msg_payload
- radm_msg_req_id
- cfg_send_cor_err
- cfg_send_nf_err
- cfg_send_f_err
- surprise_down_err
- cfg_br_ctrl_serren
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PCI Express SW Controller Databook SII: General Messaging Reception Signals
cfg_send_cor_err[(NF-1):0] O Send Correctable Error. The controller detected a correctable error at its
receive path. This error signal is designed to allow the switch to report
its detect receive error from the downstream port to the upstream port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_send_nf_err[(NF-1):0] O Send Non-Fatal Error. The controller detected a non-fatal error at its
receive path. This error signal is designed to allow the switch to report
its detect receive error from the downstream port to the upstream port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_send_f_err[(NF-1):0] O Send Fatal Error. The controller detected a fatal error at its receive path.
This error signal is designed to allow the switch to report its detect
receive error from the downstream port to the upstream port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: General Messaging Reception Signals
cfg_br_ctrl_serren[(NF-1):0] O PF's SERR# Enable registers value in Bridge Control Register of Type1
Header. You can use this value to control forwarding of ERR_COR,
ERR_NONFATAL, and ERR_FATAL from secondary to primary.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
sys_int - - cfg_vpd_int
xal_xmt_cpl_ca - - cfg_pcie_cap_int_msg_num
xal_rcvd_cpl_ca - - radm_inta_asserted
xal_rcvd_cpl_ur - - radm_intb_asserted
dp_inta - - radm_intc_asserted
dp_intb - - radm_intd_asserted
dp_intc - - radm_inta_deasserted
dp_intd - - radm_intb_deasserted
- radm_intc_deasserted
- radm_intd_deasserted
- hp_pme
- hp_int
- hp_msi
- cfg_link_auto_bw_int
- cfg_link_auto_bw_msi
- cfg_bw_mgt_int
- cfg_bw_mgt_msi
- cfg_link_eq_req_int
- assert_inta_grt
- assert_intb_grt
- assert_intc_grt
- assert_intd_grt
- deassert_inta_grt
- deassert_intb_grt
- deassert_intc_grt
- deassert_intd_grt
- cfg_int_pin
- cfg_int_disable
- cfg_safety_corr
- cfg_safety_uncorr
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PCI Express SW Controller Databook SII: Interrupt Signals
cfg_vpd_int[(NF-1):0] O This pin is set as a one cycle pulse to notify your application to read the
VPD registers. The sequence of events for a VPD read cycle is:
■ The controller sends a request (single-cycle pulse of the cfg_vpd_int
signal) to your application to read or write vital product data.
■ Your application reads the VPD Control and Capabilities register.
■ The VPD Flag (bit 31) is set to '0' indicating a read request. Your
application fetches four bytes of data from the VPD Address location
and transfers this to the VPD Data register.
■ Your application sets the VPD Flag bit to '1' indicating the request is
complete.
The sequence of events for a VPD write cycle is:
■ The controller sends a request (single-cycle pulse of the cfg_vpd_int
signal) to your application to read or write vital product data.
■ Your application reads the VPD Control and Capabilities register.
■ The VPD Flag (bit 31) is set to '1' indicating a write request. Your
application reads the VPD Data register and transfers this to the
location specified by the VPD Address register.
■ Your application sets the VPD Flag bit to '0' indicating the request is
complete.
Exists: VPD_CAP_ENABLE
Synchronous To: None,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High (pulse)
Validated by: Not validated by another signal.
sys_int[(NF-1):0] I When sys_int goes from low to high, the controller generates an
Assert_INTx Message. When sys_int goes from high to low, the
controller generates a Deassert_INTx Message.
There is a separate sys_int input bit for each function in your controller
configuration. The Interrupt Pin register for the corresponding function
determines which INTx Message the controller generates (INTA, INTB,
INTC, or INTD). Legacy and native PCIe devices capable of generating
an interrupt must support both Assert_INTx/Deassert_INTx and MSI or
MSI-X. sys_int is intended to generate a message that emulates the
legacy PCI Interrupts.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_pcie_cap_int_msg_num[((NF*5)-1):0] O From bits [13:9] of the PCI Express Capabilities register, used when MSI
or MSI-X is enabled. Assertion of hp_msi or cfg_pme_msi along with a
value cfg_pcie_cap_int_msg_num is equivalent to the controller
receiving an MSI with the cfg_pcie_cap_int_msg_num value as the MSI
vector.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Interrupt Signals
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hp_pme[(NF-1):0] O The controller asserts hp_pme when all of the following conditions are
true:
■ The PME Enable bit in the Power Management Control and Status
register is set to 1.
■ Any bit in the Slot Status register transitions from 0 to 1 and the asso-
ciated event notification is enabled in the Slot Control register.
The controller does not check if the PM state is D1, D2, or D3hot. It is up
to your application to check the value pm_dstate to make sure the
device is in D1, D2, or D3hot. There is one bit of hp_pme for each
configured function. The controller pulses the hp_pme output only when
any hot plug status bit changes from 0 to 1 (as is hp_msi). hp_int stays
asserted as long as the status bit is set. In addition, it asserts hp_pme
only if PME is enabled, but it does not matter if hot-plug interrupts are
enabled.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (pulse)
Validated by: Not validated by another signal
hp_int[(NF-1):0] O The controller asserts hp_int when all of the following conditions are
true:
■ The INTx Assertion Disable bit in the Command register is 0.
■ Hot-Plug interrupts are enabled in the Slot Control register.
■ Any bit in the Slot Status register is equal to 1, and the associated
event notification is enabled in the Slot Control register.
There is one bit of hp_int for each configured function.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Interrupt Signals
hp_msi[(NF-1):0] O The controller asserts hp_msi (as a one-cycle pulse) when the logical
AND of the following conditions transitions from false to true:
■ MSI or MSI-X is enabled.
■ Hot-Plug interrupts are enabled in the Slot Control register.
■ Any bit in the Slot Status register transitions from 0 to 1 and the asso-
ciated event notification is enabled in the Slot Control register.
There is one bit of hp_int for each configured function. The controller
pulses the hp_msi output only when any of the hot plug status bits
change from 0 to 1 (as is hp_pme).
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (pulse)
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_link_auto_bw_msi O The controller sets this pin when following conditions are true:
■ MSI or MSI-X is enabled.
■ The Link Autonomous Bandwidth Status register (Link Status
register bit 15) is updated.
■ The Link Autonomous Bandwidth Interrupt Enable (Link Control
register bit 11) is set.
The controller does not check if the associated MSI vector (asserted
cfg_pcie_cap_int_msg_num) is unmasked. It is up to the application to
check whether the vector is masked or unmasked. For upstream port:
Reserved. <ct:CX_IS_EP>Reserved.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (pulse)
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Interrupt Signals
cfg_bw_mgt_msi O The controller sets this pin when following conditions are true:
■ MSI or MSI-X is enabled.
■ The Link Bandwidth Management Status register (Link Control
Status register bit 14) is updated
■ The Link Bandwidth Management Interrupt Enable (Link Control
register bit 10) is set.
reuse-pragma beginAttr Description This pin is set as a notification
when the Link Bandwidth Management Status register (Link Status
register bit 14) is updated and the Link Bandwidth Management
Interrupt Enable (Link Control register bit 10) is set and in addition the
msi or msix aare enabled . This bit is not applicable to, and is reserved,
for endpoint devices and upstream ports of Switches.
For upstream port: Reserved. <ct:CX_IS_EP>Reserved.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (pulse)
Validated by: Not validated by another signal
Synopsys, Inc.
dp_inta I INTA From downstream port. Indicates to an upstream port the state of
your application logic's "Virtual Interrupt" wire. When legacy interrupts
are enabled, a rising edge this signal causes the upstream port to send
an Assert_INTA message; a falling edge causes the port to send a
Deassert_INTA message.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
dp_intb I INTB From downstream port. Indicates to an upstream port the state of
your application logic's "Virtual Interrupt" wire. When legacy interrupts
are enabled, a rising edge this signal causes the upstream port to send
an Assert_INTB message; a falling edge causes the port to send a
Deassert_INTB message.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Interrupt Signals
dp_intc I INTC From downstream port. Indicates to an upstream port the state of
your application logic's "Virtual Interrupt" wire. When legacy interrupts
are enabled, a rising edge this signal causes the upstream port to send
an Assert_INTC message; a falling edge causes the port to send a
Deassert_INTC message.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
dp_intd I INTD From downstream port. Indicates to an upstream port the state of
your application logic's "Virtual Interrupt" wire. When legacy interrupts
are enabled, a rising edge this signal causes the upstream port to send
an Assert_INTD message; a falling edge causes the port to send a
Deassert_INTD message.
Exists: Always
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Interrupt Signals
cfg_int_pin[((8*NF)-1):0] O The cfg_int_pin indicates the configured value for the Interrupt Pin
Register field in the BRIDGE_CTRL_INT_PIN_INT_LINE register.
Exists: CX_SYS_INT_GRANT_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: N/A
Synopsys, Inc.
cfg_safety_uncorr O The controller asserts cfg_safety_uncorr when any of the internal safety
mechanisms reports an uncorrectable error and the associated mask for
that event is not set.
Exists: CX_AUTOMOTIVE_ENABLE
Synchronous To: aux_clk_g
Registered: Yes
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Link Reset/Status Signals
- smlh_link_up
- smlh_req_rst_not
- link_req_rst_not
- cfg_link_dis
smlh_req_rst_not O Early version of the link_req_rst_not signal. For more details, see the
'Warm and Hot Resets' section in the Architecture chapter of the
Databook.
Exists: Always
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: Low (high-to-low transition )
Validated by: Not validated by another signal
link_req_rst_not O Reset request because the link has gone down or the controller
received a hot-reset request. A low level indicates that the controller is
requesting external logic to reset the controller because the PHY link is
down. For more details, see the "Hot Reset" section in the Architecture
chapter of the Databook.
Exists: Always
Synchronous To: aux_clk_g,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_link_dis O The controller asserts cfg_link_dis when Link Disable bit in the Link
Control register is set to 1. The cfg_link_dis output is a level signal.
For upstream port: Reserved.
Exists: SNPS_RSVDPARAM_33
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: LTR Message Generation Signals
app_ltr_msg_req - - app_ltr_msg_grant
app_ltr_msg_latency - - app_ltr_latency
app_ltr_msg_func_num -
app_ltr_msg_grant O Indicates that the controller has accepted your request to send an LTR
message.
Exists: CX_LTR_M_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_ltr_msg_req is asserted
app_ltr_msg_latency[31:0] I LTR message that your application is requesting to send. The message
format is defined in the PCI Express Specification.
Exists: CX_LTR_M_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_ltr_msg_req is asserted
Synopsys, Inc.
app_ltr_latency[31:0] O The current LTR values reported and in-use by the downstream device.
■ For a downstream device, when LTR is disabled, or when any func-
tion is directed to a non-D0 state, if a device had previously reported
one or both latency fields with the Requirement bit set, the applica-
tion must send a new LTR Message with both Requirement bits
clear.
■ For an upstream device, it reflects the captured LTR values from
received LTR message, one clock cycle after the controller asserts
the radm_msg_ltr output. When RX_TLP > 1 and when two
messages of the same type are received in the same clock cycle,
then this output reflects the second captured message.
For more details, see 'Port Logic Registers: Latency Tolerance
Reporting (LTR) Registers'.
Exists: CX_LTR_M_ENABLE
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: For a downstream device, not validated by another signal
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PCI Express SW Controller Databook SII: LTR Message Reception Signals
- radm_msg_ltr
radm_msg_ltr O One-clock-cycle pulse that indicates that the controller received an LTR
message. The controller makes the message header available the
radm_msg_payload output. It is also available the app_ltr_latency
output. When RX_TLP > 1 and when two messages of the same type
are received in the same clock cycle (back-to-back), then no separate
indication is given for the second message.
Exists: CX_LTR_M_ENABLE
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
- cfg_2nd_reset
cfg_2nd_reset O Secondary Bus Reset. Indicates that your application has requested this
downstream port to start Link hot reset. This signal is asserted when
your application writes to the Secondary Bus Reset field (bit 6) of the
Bridge Control Register (Offset 0x3E) in the Type 1 Configuration Space
header. Setting this bit triggers a hot reset the corresponding PCI
Express port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: OBFF Message Generation Signals
app_obff_idle_msg_req - - app_obff_msg_grant
app_obff_obff_msg_req -
app_obff_cpu_active_msg_req -
app_obff_msg_grant O Indicates that the controller has accepted your request to generate an
OBFF message. Only usable in a downstream port
Exists: CX_OBFF_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: any of app_obff_*msg_req are asserted
Synopsys, Inc.
- radm_msg_idle
- radm_msg_obff
- radm_msg_cpu_active
radm_msg_cpu_active O One-clock-cycle pulse that indicates that the controller received a 'CPU
Active' OBFF message. When RX_TLP > 1 and when two messages of
the same type are received in the same clock cycle (back-to-back), then
no separate indication is given for the second message. Only usable in
an upstream port
Exists: CX_OBFF_ENABLE
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: PM, Unlock, and Error Messages Signals
apps_pm_xmt_turnoff - - radm_msg_unlock
app_unlock_msg - - radm_correctable_err
all_dwsp_rcvd_toack_msg - - radm_nonfatal_err
- radm_fatal_err
- radm_pm_pme
- radm_pm_to_ack
- radm_pm_turnoff
- pm_req_dwsp_turnoff
radm_msg_unlock O One-cycle pulse that indicates that the controller received an Unlock
message. When RX_TLP > 1 and when two messages of the same type
are received in the same clock cycle (back-to-back), then no separate
indication is given for the second message.
Exists: Always
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
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PCI Express SW Controller Databook SII: PM, Unlock, and Error Messages Signals
radm_pm_turnoff O One-clock-cycle pulse that indicates that the controller received a PME
Turnoff message. When RX_TLP > 1 and when two messages of the
same type are received in the same clock cycle (back-to-back), then no
indication is given for the second message.
Exists: Always
Synchronous To: core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
pm_req_dwsp_turnoff O Request downstream port PME Turn Off. Asserted by upstream switch
port when it has received a PME_Turn_Off message from the upstream
device. Your application can:
■ Respond to pm_req_dwsp_turnoff assertion by generating
PME_Turn_Off messages to all downstream ports, or
■ Ignore pm_req_dwsp_turnoff and, instead of generating a
PME_Turn_Off message in response to pm_req_dwsp_turnoff, pass
the received PME_Turn_Off message through to the downstream
ports.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
outband_pwrup_cmd - - pm_curnt_state
apps_pm_xmt_pme - - smlh_ltssm_state
sys_aux_pwr_det - - wake
app_req_entr_l1 - - local_ref_clk_req_n
app_ready_entr_l23 - - pm_dstate
app_req_exit_l1 - - pm_pme_en
app_xfer_pending - - pm_linkst_in_l0s
all_dwsp_in_l1 - - pm_linkst_in_l1
all_dwsp_in_rl0s - - pm_linkst_in_l2
upsp_in_rl0s - - pm_linkst_l2_exit
one_dwsp_exit_l1 - - pm_master_state
one_dwsp_exit_l23 - - pm_slave_state
clkreq_in_n - - pm_l1sub_state
app_clk_pm_en - - pm_status
test_bypass_lp - - aux_pm_en
ack_en_vmain - - pm_linkst_in_l1sub
app_l1_pwr_off_en - - cfg_l1sub_en
save_state_ack - - pm_en_vmain_n
restore_state_ack - - pm_en_vmain
app_l1sub_disable - - pm_save_state_req
- pm_restore_state_req
- pm_req_iso_vmain_to_vaux
- pm_req_slv_iso
- pm_req_mstr_iso
- pm_req_dbi_iso
- pm_l1_entry_started
outband_pwrup_cmd[(NF-1):0] I Wake Up. If PME is enabled and PME support is configured for current
PMCSR D-state asserting this signal causes the controller to wake from
either L1 or L2 state. When the controller has transitioned back to the L0
state it transmits a PME message and set the PME_Status. There is a
separate outband_pwrup_cmd input bit for each function in your
controller configuration. This port is functionally identical to
apps_pm_xmt_pme. Upon receiving the PME message the root
complex should clear the PME_Status and change the D-state back to
D0.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Power Management Signals
apps_pm_xmt_pme[(NF-1):0] I Wake Up. If PME is enabled and PME support is configured for current
PMCSR D-state asserting this signal causes the controller to wake from
either L1 or L2 state. When the controller has transitioned back to the L0
state it transmits a PME message and set the PME_Status. Upon
receiving the PME message the root complex should clear the
PME_Status and change the D-state back to D0.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
sys_aux_pwr_det I Auxiliary Power Detected. Used to report to the host software that
auxiliary power (Vaux) is present.
Exists: Always
Synchronous To: aux_clk_g,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Power Management Signals
wake O Wake Up. Wake up from power management unit. The controller
generates wake to request the system to restore power and clock when
a wakeup event has been detected such as apps_pm_xmt_pme or
outband_pwrup_cmd. The wake signal is an active high signal and its
rising edge should be detected to drive the WAKE# the connector.
Assertion of wake could be for a single clock cycle or multiple clock
cycles.
Not used in downstream port.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
local_ref_clk_req_n O This signal may be connected to the CLKREQ# driver to negotiate entry
into L1 sub-states. When this signal is set to 1 the controller is
requesting entry into L1 sub-states and CLKREQ# may be de-asserted.
For an Upstream port this signal is also used to request reference clock
removal when Clock Power Management is enabled. This signal should
only be set to 1 if the PHY is also ready for reference clock removal, the
input phy_clk_req_n is a handshake from the PHY, which when set to 1
indicates that the PHY is ready for reference clock removal.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
Synopsys, Inc.
pm_pme_en[(NF-1):0] O PME Enable bit in the PMCSR. There is 1 bit of pm_pme_en for each
configured function.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Power Management Signals
pm_status[(NF-1):0] O PME Status bit from the PMCSR. There is 1 bit of pm_status for each
configured function.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
aux_pm_en[(NF-1):0] O Auxiliary Power Enable bit in the Device Control register. There is 1 bit
of aux_pm_en for each configured function.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
app_ready_entr_l23 I Application Ready to Enter L23. Indication from your application that it is
ready to enter the L23 state. The app_ready_entr_l23 signal is provided
for applications that must control L23 entry (in case certain tasks must
be performed before going into L23). The controller delays sending
PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes
active. When this signal has been asserted by the application, it must be
kept asserted until L2 entry has completed. Hardwire to 1 for
applications that do not require this feature.
Note:The controller ignores this input in a downstream port.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
app_req_exit_l1 I Application request to Exit L1. Request from your application to exit L1.
It is only effective when L1 is enabled.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Power Management Signals
app_xfer_pending I Indicates that your application has transfers pending and prevents the
controller from entering L1. If the entry into L1 is already in progress,
assertion of app_xfer_pending causes an exit from L1. This is a level
signal used to inform the controller about the state of external queues
and pipeline stages that contain transactions to be transmitted by the
controller. The controller uses this information to determine when to
enter/exit L1. When this signal is asserted, it indicates that there are
transactions outside the controller that the controller needs to transmit.
When de-asserted, it indicates that there are no transactions outside the
controller. The controller responds to an assertion on this signal as
follows:
■ Upstream Ports: Prevents generation of requests to enter L1. Trig-
gers exit if already in L1.
■ Downstream Ports: Triggers exit if already in L1.
You can instruct the controller to exit L1 by asserting either or both of
app_xfer_pending and app_req_exit_l1. The controller only samples
app_req_exit_l1 when the controller is already in the L1 state.
Exists: Always
Synchronous To: aux_clk_g,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
all_dwsp_in_l1 I All downstream ports in L1. Indicates to an upstream switch port that all
downstream switch ports are in the L1 state.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
one_dwsp_exit_l1 I Downstream port Exiting L1. Indicates to an upstream switch port that
one or more downstream switch ports is exiting the L1 state.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
one_dwsp_exit_l23 I Downstream port Exiting L23. Indicates to an upstream switch port that
one or more downstream switch ports is exiting the L2 or L3 state.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Power Management Signals
cfg_l1sub_en O Indicates that any of the L1 Substates are enabled in the L1 Substates
Control 1 Register. Could be used by your application in a downstream
port to determine when not to drive CLKREQ# such as when L1
Substates are not enabled.
Exists: CX_L1_SUBSTATES_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
save_state_ack I Application acknowledges that state retention (L1 power gating) task is
completed.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
restore_state_ack I Application acknowledges that saved state has been restored after
power-up.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Power Management Signals
pm_en_vmain_n O Active Low Enable for power switch supplying PD_VMAIN. This signal
will be set to 1 when the controller is requesting power to be gated in
L1.2. The application must set the acknowledge ack_en_vmain to 0
when power has been gated. The controller will set this signal to 0
when it is requesting power to be restored, the application should set
ack_en_vmain to 1 when it has restored power. For more details, see
"Advanced Power Management and Power Domain Gating" in the
Power Management section of the Databook.
Exists: (CX_ENHANCED_PM_EN) && (CX_PSW_EN_ACTIVE_LOW)
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
pm_en_vmain O Active High Enable for power switch supplying PD_VMAIN. This signal
will be set to 0 when the controller is requesting power to be gated in
L1.2. The application must set the acknowledge ack_en_vmain to 0
when power has been gated. The controller will set this signal to 1
when it is requesting power to be restored, the application should set
ack_en_vmain to 1 when it has restored power. For more details, see
"Advanced Power Management and Power Domain Gating" in the
Power Management section of the Databook.
Exists: (CX_ENHANCED_PM_EN) && (!CX_PSW_EN_ACTIVE_LOW)
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
pm_save_state_req O Request which can be used by your application to store any data which
needs to be retained during L1 power gating. For more details, see
"Advanced Power Management and Power Domain Gating" in the
Power Management section of the Databook.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
pm_restore_state_req O Request which can be used by your application to restore any data
which has been retained prior to L1 power gating. For more details, see
"Advanced Power Management and Power Domain Gating" in the
Power Management section of the Databook.
Exists: CX_ENHANCED_PM_EN
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
pm_req_slv_iso O Request from PMC to enable isolation on AXI slave output signals. For
more details, see "Advanced Power Management and Power Domain
Gating" in the Power Management section of the Databook.
Exists: CX_SLV_ISO_EN
Synchronous To: slv_aclk_ug
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
pm_req_mstr_iso O Request from PMC to enable isolation on AXI master output signals. For
more details, see "Advanced Power Management and Power Domain
Gating" in the Power Management section of the Databook.
Exists: CX_MSTR_ISO_EN
Synchronous To: mstr_aclk_ug
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Power Management Signals
pm_req_dbi_iso O Request from PMC to enable isolation on AXI DBI slave output signals.
For more details, see "Advanced Power Management and Power
Domain Gating" in the Power Management section of the Databook.
Exists: CX_DBI_ISO_EN
Synchronous To: dbi_aclk_ug
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
app_l1sub_disable I The application can set this input to 1'b1 to prevent entry to L1
Sub-states. This pin is used to gate the L1 sub-state enable bits from
the L1 PM Substates Control 1 Register.
Exists: CX_APP_L1SUB_CONTROL
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
ptm_sw_dn_context_valid - - ptm_context_valid
ptm_sw_dn_local_clock - - ptm_responder_rdy_to_validate
cfg_ptm_sw_dn_enable - - ptm_local_clock
cfg_ptm_sw_dn_responder_capable - - cfg_ptm_sw_up_enable
ptm_external_master_strobe - - cfg_ptm_sw_up_responder_capable
ptm_external_master_time - - ptm_trigger_allowed
ptm_auto_update_signal - - ptm_updating
ptm_manual_update_pulse - - ptm_clock_updated
- ptm_clock_correction
- ptm_req_response_timeout
- ptm_req_dup_rx
- ptm_req_replay_tx
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PCI Express SW Controller Databook SII: Precision Time Management Signals
Synopsys, Inc.
ptm_auto_update_signal I Indicates that the controller should update the PTM Requester Context
and Clock automatically every 10ms.
Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (Level)
Validated by: Not validated by another signal
ptm_manual_update_pulse I Indicates that the controller should update the PTM Requester Context
and Clock now.
Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (Pulse)
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Precision Time Management Signals
ptm_clock_updated O Indicates that the controller has updated the Local Clock.
Exists: CX_PTM_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (Pulse)
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: RAS Data Protection Signals
- cfg_rasdp_error_mode
cfg_rasdp_error_mode O Indication from the controller that it has entered RASDP error mode.The
controller enters RASDP error mode (if the ERROR_MODE_EN register
field =1) upon detection of the first uncorrectable error. During this
mode, Rx TLPs that are forwarded to your application are not
guaranteed to be correct; you must discard them. For more details, see
the RAS Data Protection (DP) section in the Controller Operations
chapter of the Databook.
Exists: (!(AMBA_INTERFACE!=0)) &&
(((CX_RASDP==0)&&(CX_RASDP_RAM_PROT==0))? 0: 1)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
app_ph_ca -
app_pd_ca -
app_nph_ca -
app_npd_ca -
app_cplh_ca -
app_cpld_ca -
app_ph_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that posted header credits have been
returned. In implementations where your application is responsible for
queuing the receive data (such as in bypass mode), your application
must pulse the app_ph_ca input each time your application consumes a
posted header credit so that the controller can update the number of
posted header credits available. There is 1 bit of app_ph_ca assigned to
each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
app_pd_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that posted data credits have been returned.
In implementations where your application is responsible for queuing
the receive data (such as in bypass mode), your application must pulse
the app_pd_ca input each time your application consumes a posted
data credit so that the controller can update the number of posted data
credits available. Your application must assert app_pd_ca once for each
packet, even if the packet contains less than 16 bytes (1 credit) of data.
There is 1 bit of app_pd_ca assigned to each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Receive Control/CPL Timeout Signals
app_nph_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that non-posted header credits have been
returned. In implementations where your application is responsible for
queuing the receive data (such as in bypass mode), your application
must pulse the app_nph_ca input each time your application consumes
a non-posted header credit so that the controller can update the number
of non-posted header credits available. There is 1 bit of app_nph_ca
assigned to each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
app_npd_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that non-posted data credits have been
returned. In implementations where your application is responsible for
queuing the receive data (such as in bypass mode), your application
must pulse the app_npd_ca input each time your application consumes
a non-posted data credit so that the controller can update the number of
non-posted data credits available. Your application must assert
app_npd_ca once for each packet, even if the packet contains less than
16 bytes (1 credit) of data. There is 1 bit of app_npd_ca assigned to
each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
app_cplh_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that completion header credits have been
returned. In implementations where your application is responsible for
queuing the receive data (such as in bypass mode), your application
must pulse the app_cplh_ca input each time your application consumes
a completion header credit so that the controller can update the number
of completion header credits available. There is 1 bit of app_cplh_ca
assigned to each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
app_cpld_ca[(APP_CRD_WD-1):0] I One-cycle pulse indicating that completion data credits have been
returned. In implementations where your application is responsible for
queuing the receive data (such as in bypass mode), your application
must pulse the app_cpld_ca input each time your application consumes
a completion data credit so that the controller can update the number of
completion data credits available. Your application must assert
app_cpld_ca once for each packet, even if the packet contains less than
16 bytes (1 credit) of data. There is 1 bit of app_cpld_ca assigned to
each configured virtual channel.
Exists: APP_RETURN_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Transmit Control Signals
app_hdr_valid - - pm_xtlh_block_tlp
app_hdr_log - - app_parity_errs
app_tlp_prfx_log - - xadm_ph_cdts
app_err_bus - - xadm_pd_cdts
app_err_advisory - - xadm_nph_cdts
app_err_func_num - - xadm_npd_cdts
app_crd_cpl_grant - - xadm_cplh_cdts
app_crd_msg_grant - - xadm_cpld_cdts
- xadm_crd_msg_h_req
- xadm_crd_msg_d_req
- xadm_crd_cpl_h_req
- xadm_crd_cpl_d_req
- xadm_crd_msg_vc
- xadm_crd_cpl_vc
- xadm_crd_msg_consumed
- xadm_crd_cpl_consumed
- xadm_hcdt_consumed
- xadm_dcdt_consumed
- xadm_data_credit
pm_xtlh_block_tlp O Indicates that your application must stop generating new outgoing
request TLPs due to the current power management state. Your
application can continue to generate completion TLPs. For more details,
see "Outbound TLP Blocking In USP". This output is not used in a
downstream switch port.
Exists: Always
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
app_parity_errs[2:0] O Indicates that the controller detected a datapath parity error, one bit for
each of the following parity errors:
■ app_parity_errs[0]: Parity error at front end of the transmit datapath.
■ app_parity_errs[1]: Parity error at back end of the transmit datapath.
■ app_parity_errs[2]: Parity error the receive datapath.
The app_parity_errs signals are one-cycle pulses that indicate the
associated parity error occurred; they do not indicate which packet
contained the parity error. A suggested usage of the app_parity_errs
signals is to register each bit and to provide a control to turn off system
notification of parity errors. By doing so, your application can choose to
only respond to the first detection of a parity error. The controller
performs transmit and receive datapath parity if data path protection is
selected.
Exists: APP_PAR_ERR_OUT_EN
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
xadm_ph_cdts[((NVC*HCRD_WD)-1):0] O The amount of posted header buffer space currently available at the
receiver at the other end of the link (in units of posted header credits).
The controller maintains the current number of credits xadm_ph_cdts as
the receiver continues to send UpdateFC DLLPs and your application
uses credits by sending new TLPs to be transmitted. There are eight
bits of xadm_ph_cdts assigned to each configured virtual channel. Only
needed if you want your application to check available credits before
submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Transmit Control Signals
xadm_pd_cdts[((NVC*DCRD_WD)-1):0] O The amount of posted data buffer space currently available at the
receiver at the other end of the link (in units of posted data credits). The
controller maintains the current number of credits xadm_pd_cdts as the
receiver continues to send UpdateFC DLLPs and your application uses
credits by sending new TLPs to be transmitted. There are twelve bits of
xadm_pd_cdts assigned to each configured virtual channel. Only
needed if you want your application to check available credits before
submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
xadm_nph_cdts[((NVC*HCRD_WD)-1):0] O The amount of non-posted header buffer space currently available at the
receiver at the other end of the link (in units of non-posted header
credits). The controller maintains the current number of credits
xadm_nph_cdts as the receiver continues to send UpdateFC DLLPs
and your application uses credits by sending new TLPs to be
transmitted. There are eight bits of xadm_nph_cdts assigned to each
configured virtual channel. Only needed if you want your application to
check available credits before submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
xadm_npd_cdts[((NVC*DCRD_WD)-1):0] O The amount of non-posted data buffer space currently available at the
receiver at the other end of the link (in units of non-posted data credits).
The controller maintains the current number of credits xadm_npd_cdts
as the receiver continues to send UpdateFC DLLPs and your
application uses credits by sending new TLPs to be transmitted. There
are twelve bits of xadm_npd_cdts assigned to each configured virtual
channel. Only needed if you want your application to check available
credits before submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
xadm_cplh_cdts[((NVC*HCRD_WD)-1):0] O The amount of completion header buffer space currently available at the
receiver at the other end of the link (in units of completion header
credits). The controller maintains the current number of credits
xadm_cplh_cdts as the receiver continues to send UpdateFC DLLPs
and your application uses credits by sending new TLPs to be
transmitted. There are eight bits of xadm_cplh_cdts assigned to each
configured virtual channel. Only needed if you want your application to
check available credits before submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
xadm_cpld_cdts[((NVC*DCRD_WD)-1):0] O The amount of completion data buffer space currently available at the
receiver at the other end of the link (in units of completion data credits).
The controller maintains the current number of credits xadm_cpld_cdts
as the receiver continues to send UpdateFC DLLPs and your
application uses credits by sending new TLPs to be transmitted. There
are twelve bits of xadm_cpld_cdts assigned to each configured virtual
channel. Only needed if you want your application to check available
credits before submitting TLPs for transmission.
Exists: XADM_CRD_EN
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Transmit Control Signals
app_hdr_log[127:0] I The header of the TLP that contained the error indicated app_err_bus,
valid when 1. app_hdr_valid is asserted. For Corrected Internal and
Uncorrectable Internal errors (app_err_bus[10:9]),and receiver Overflow
(app_err_bus[1]), the header information this input is not logged by the
controller. 2. app_dpc_err_valid is asserted. The header of the TLP that
contained the error indicated on app_dpc_err_bus. When DPC RP PIO
exgtensions are supported, it is used to update DPC RP PIO Header
Log Register.
Exists: APP_RETURN_ERR_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_hdr_valid or app_dpc_err_valid is asserted
app_tlp_prfx_log[127:0] I End-End TLP prefixes of the TLP that contained an error. Valid when 1.
app_hdr_valid is asserted. The header of the TLP that contained the
error indicated on app_err_bus. For Corrected Internal and
Uncorrectable Internal errors (app_err_bus[10:9]),and receiver Overflow
(app_err_bus[1]), the header information this input is not logged by the
controller. 2. app_dpc_err_valid is asserted. The header of the TLP that
contained the error indicated on app_dpc_err_bus. When DPC RP PIO
exgtensions are supported, it is used to update DPC RP PIO Header
Log Register.
Exists: (APP_RETURN_ERR_EN) && (CX_TLP_PREFIX_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_hdr_valid is asserted
Synopsys, Inc.
app_err_bus[(ERR_BUS_WD-1):0] I The type of error that your application detected. The controller combines
the values the app_err_bus bits with the internally-detected error signals
to set the corresponding bit in the Uncorrectable or Correctable Error
Status Registers:
■ app_err_bus[0]: Malformed TLP
■ app_err_bus[1]: Receiver Overflow
■ app_err_bus[2]: Unexpected completion
■ app_err_bus[3]: Completer abort
■ app_err_bus[4]: Completion Timeout
■ app_err_bus[5]: Unsupported request
■ app_err_bus[6]: ECRC Check Failed
■ app_err_bus[7]: Poisoned TLP received
■ app_err_bus[8]: AtomicOp Egress Blocked: only valid when
CX_ATOMIC_ROUTING_EN =1
■ app_err_bus[9]: Uncorrectable Internal Error
■ app_err_bus[10]: Corrected Internal Error
■ app_err_bus[11]: TLP Prefix Blocked Error Status: only valid when
CX_NPRFX >0
■ app_err_bus[12]: ACS Violation: only valid when CX_ACS_ENABLE
=1
For more details, see 'Application Error Reporting Interface'.
Exists: APP_RETURN_ERR_EN
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_hdr_valid is asserted
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PCI Express SW Controller Databook SII: Transmit Control Signals
app_err_advisory I Indicates that your application error is an advisory error. Your application
should assert app_err_advisory under either of the following conditions:
■ The controller is configured to mask completion timeout errors, your
application is reporting a completion timeout error app_err_bus, and
your application intends to resend the request. In such cases the
error is an advisory error, as described in PCI Express Specification.
When your application does not intend to resend the request, then
your application must keep app_err_advisory de-asserted when
reporting a completion timeout error.
■ The controller is configured to forward poisoned TLPs to your appli-
cation and your application is going to treat the poisoned TLP as a
normal TLP, as described in PCI Express Specification. Upon receipt
of a poisoned TLP, your application must report the error app_er-
r_bus, and either assert app_err_advisory (to indicate an advisory
error) or de-assert app_err_advisory (to indicate that your applica-
tion is dropping the TLP).
For more details, see the PCI Express Specification to determine when
an application error is an advisory error.
Exists: APP_RETURN_ERR_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_hdr_valid is asserted
app_err_func_num[(PF_WD-1):0] I The number of the function that is reporting the error indicated
app_err_bus, valid when app_hdr_valid is asserted. Correctable and
Uncorrected Internal errors (app_err_bus[10:9]) are not function
specific, and are recorded for all physical functions, regardless of the
value this bus. Function numbering starts at '0'.
Exists: APP_RETURN_ERR_EN
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: app_hdr_valid is asserted
Synopsys, Inc.
app_crd_msg_grant I Application grants the use of credits for internally generated messages.
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
xadm_crd_msg_h_req O The controller requests app for grant to send internally generated msg
(consuming header credit).
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
xadm_crd_msg_d_req O The controller requests app for grant to send internally generated msg
(consuming data credit).
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
xadm_crd_cpl_h_req O The controller requests app for grant to send internally generated cpl
(consuming header credit).
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
xadm_crd_cpl_d_req O The controller requests app for grant to send internally generated cpl
(consuming data credit).
Exists: APP_CREDIT_CTRL
Synchronous To: core_clk
Registered: Yes
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: Transmit Control Signals
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PCI Express SW Controller Databook Common PIPE Signals
phy_mac_rxelecidle - - mac_phy_powerdown
phy_mac_phystatus - - mac_phy_txdata
phy_mac_rxdata - - mac_phy_txdatak
phy_mac_rxdatak - - mac_phy_elasticbuffermode
phy_mac_rxvalid - - mac_phy_txdatavalid
phy_mac_rxstatus - - mac_phy_txdetectrx_loopback
phy_mac_rxstandbystatus - - mac_phy_txelecidle
phy_cfg_status - - mac_phy_txcompliance
phy_mac_rxdatavalid - - mac_phy_rxpolarity
phy_mac_pclkack_n - - mac_phy_width
- mac_phy_serdes_arch
- mac_phy_rxwidth
- mac_phy_pclk_rate
- mac_phy_cclk_rate
- mac_phy_plclk_rate
- mac_phy_rxstandby
- cfg_phy_control
- mac_phy_pclkreq_n
- mac_phy_rxelecidle_disable
- mac_phy_txcommonmode_disable
- mac_phy_asyncpowerchangeack
Synopsys, Inc.
mac_phy_powerdown[(PDWN_WIDTH-1): O Power control bits that drive the PHY power state. This signal is shared
0] by all the lanes of the PHY. so you must fan out this signal (through your
power-down controller block) to all the corresponding lanes of the PHY.
Power states (with the corresponding link states and L1 Substates) are
as follows:
■ 0000: P0 (L0): normal
■ 0001: P0s (L0s): low recovery time, power saving.
■ 0010: P1 (L1): longer recovery time, additional power saving.
■ 0011: P2 (L2): lowest power state.
The following encodings are used when CX_L1_SUBSTATES_ENABLE
=CX_PIPE43_SUPPORT =1. You can specify the encodings using
CX_PIPE43_P1CPM_ENCODING, CX_PIPE43_P1_1_ENCODING,
and CX_PIPE43_P1_2_ENCODING parameters.
■ CX_PIPE43_P1CPM_ENCODING: P1.CPM (L1 Substates L1.0):
PHY specific powerdown state, instructs PHY to turn off PCLK.
Controller stays in this state until PHY asserts phy_mac_phystatus
back.
■ CX_PIPE43_P1_1_ENCODING: P1.1 (L1 Substates L1.1): PHY
specific powerdown state, instructs PHY to disable Receiver Elec-
trical Idle detection logic. If CX_PIPE43_ASYNC_HS_BYPASS is
not set, controller stays in this state until the asynchronous power-
down change handshake completes.
■ CX_PIPE43_P1_2_ENCODING: P1.2 (L1 Substates L1.2): PHY
specific powerdown state, instructs PHY to disable Receiver Elec-
trical Idle detection logic and Transmitter Common Mode logic.
When CX_PIPE43_ASYNC_HS_BYPASS is not set, the controller
stays in this state until the asynchronous powerdown change hand-
shake completes.
This is a 4-bit output to support PIPE 4.3 version. When your PHY is not
PIPE 4.3 compliant, use the lower bits for connection; the controller
drives the MSB bits to '0'.
The following encoding is used when CX_P2NOBEACON_ENABLE =1
and PHY_INTEROP_CTRL_OFF.P2NOBEACON_ENABLE =1.
■ CX_PIPE43_P2NOBEACON_ENCODING: P2.NoBeacon: When
CX_P2NOBEACON_ENABLE =1, mac_phy_powerdown drives
P2.NoBeacon encoding instead of P2 encoding, when the link goes
to L2. To configure P2.NoBeacon encoding use
CX_PIPE43_P2NOBEACON_ENCODING parameter. The default
value of this parameter is 4'b1111.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: None,perbitclk,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Common PIPE Signals
phy_mac_rxelecidle[(NL-1):0] I Indicates receiver detection of an Electrical Idle for each lane. This can
be signaled asynchronously by the PHY macro.
■ Bit 0 corresponds to lane 0
■ Bit 1 corresponds to lane 1
■ and so on, up to the maximum number of lanes.
You can set a DFT control point to force this controller input to '1' during
scan mode to make the pc_rxelecidle register in the rxeidle_squelch
module scannable.
This signal is syncronized using aux_clk and can be driven/supplied
asynchronously to the controller in certain low-power modes.
Exists: ((CX_CPCIE_ENABLE)) && (!CX_ADM_ADAPTOR_ENABLE)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
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PCI Express SW Controller Databook Common PIPE Signals
phy_mac_rxvalid[(NL-1):0] I Indicates symbol lock and valid data for each lane. Bit 0 corresponds to
lane 0.
For SerDes architecture, this is used to indicate that the recovered clock
is stable.
Exists: (CX_CPCIE_ENABLE)
Synchronous To:
aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
phy_mac_rxstatus[((NL*3)-1):0] I Receive status and error codes for each lane. Bits 2:0 correspond to
lane 0; bits 5:3 correspond to lane 1, and so on, up to the maximum
number of lanes. Encoding is as follows:
■ 000: Received data OK
■ 001: A SKP set has been added. For Gen1/2, a SKP set is one byte.
For Gen3, a SKP set is four bytes.
■ 010: A SKP set has been removed. For Gen1/2: A SKP set is one
byte. For Gen3: A SKP set is four bytes
■ 011: Receiver detected
■ 100: Decode error. For Gen1/2, this indicates detection of an 8b/10b
decode error. For Gen3, this indicates detection of a 128b/130b
decode error.
■ 101: Elastic buffer overflow
■ 110: Elastic buffer underflow
■ 111: Receive disparity error. The controller does not report disparity
errors at Gen3 speed.
The controller supports Bare COM. When the PHY removes SKP
symbols it assigns phy_mac_rxstatus[2:0] = 3'b010 aligned to COM for
Gen1/2 rate or to phy_mac_rxstartblock=1 for Gen3/4 rate at the same
clock cycle.
For SerDes architecture, the only status applicable to SerDes
architecture is 'Receiver detected' (0x3).
Exists: (CX_CPCIE_ENABLE)
Synchronous To:
aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
phy_mac_rxstandbystatus[(NL-1):0] I The PHY uses this signal to indicate its RxStandby state.
■ 0: Active
■ 1: Standby
The Synopsys controller uses this signal only when
CX_RXSTANDBY_CONTROL[6] =1. Contact your PHY vendor for
guidelines on how to properly configure the RxStandby behavior. Refer
to the User Guide for guidelines on how to configure this parameter for
each supported Synopsys PHY.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: Low
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Common PIPE Signals
phy_cfg_status[31:0] I Input bus that can optionally be used to read PHY status. The
phy_cfg_status bus maps to the PHY Status register
(PHY_STATUS_REG). For specific bit usage, see 'PHY Status
Register'.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
mac_phy_elasticbuffermode O Selects Elasticity Buffer operating mode. 0: Nominal Half Full Buffer
mode 1: Nominal Empty Buffer Mode
Exists: ((CX_CPCIE_ENABLE)) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,{None},{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
mac_phy_txdatavalid[(NL-1):0] O This signal allows the PCIe controller to instruct the PHY to ignore the
data interface for one or two clock cycles. A value of one indicates that
the data is valid and should be used. The PCIe controller asserts this
output during mac_phy_txelecidle.
Note: If your PHY does not support the mac_phy_txdatavalid signal you
can leave this pin unconnected.
Exists: (CX_CPCIE_ENABLE)
Synchronous To:
None,aux_clk,aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Common PIPE Signals
mac_phy_txelecidle[((NL*PHY_TXEI_WD) O Forces transmit output to Electrical Idle for each lane which it is
-1):0] asserted.
For PIPE4.4 or below, bit 0 corresponds to lane 0. Bit 1 corresponds to
lane 1, and so on, up to the maximum number of lanes.
For PIPE5.1 Original PIPE architecture, only bit 0 is used for lane 0 and
bit 1:3 are reserved. Only bit 4 is used for lane 1 and bit 5:7 are
reserved. The remaining bits continue similarly.
For PIPE5.1 and SerDes architecture, one bit is required per two
symbols of interface data. For example, for an eight symbol wide
interface, bit 0 would apply to symbols 0 and 1, bit 1 would apply to
symbols 2 and 3, bit 2 would apply to symbols 4 and 5, bit 3 would apply
to symbol 6 and 7 of lane 0. For narrower interfaces, unused bits of this
signal are reserved.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
mac_phy_rxpolarity[(NL-1):0] O Directs the PHY to perform a polarity inversion the received data the
specified lanes. Bit 0 corresponds to lane 0; bit 1 corresponds to lane 1,
and so on, up to the maximum number of lanes.
■ 1: Polarity inversion
■ 0: No polarity inversion
Exists: ((CX_CPCIE_ENABLE)) && (!(CX_PIPE51_SUPPORT))
Synchronous To:
aux_clk,aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Common PIPE Signals
mac_phy_rxwidth[(WIDTH_WIDTH-1):0] O This signal is only used in the SerDes architecture. Controls the PIPE
receive datapath width.
■ 0: 10 bits
■ 1: 20 bits
■ 2: 40 bits
■ 3: 80 bits
■ 4: 160 bits
Exists: ((CX_CPCIE_ENABLE)) && (SNPS_RSVDPARAM_26)
Synchronous To: CX_FREQ_STEP_EN ? "pipe_clk" : "core_clk"
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
mac_phy_cclk_rate[2:0] O Controls clock frequency ratio between the core_clk and the
core_pl_clk.
■ 0: Reserved
■ 1: 1:1
■ 2: 1:2
■ 3: 1:4
■ 4: 1:8
■ 5: 1:16
■ 6: Reserved
■ 7: Reserved
Exists: ((CX_CPCIE_ENABLE)) && (CX_FREQ_STEP_DL_EN)
Synchronous To: CX_FREQ_STEP_EN ? "pipe_clk" : "core_clk"
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
mac_phy_plclk_rate[2:0] O Controls clock frequency ratio between the core_pl_clk and the
pipe_clk.
■ 0: 2:1
■ 1: 1:1
■ 2: 1:2
■ 3: 1:4
■ 4: 1:8
■ 5: 1:16
■ 6: Reserved
■ 7: Reserved
Exists: ((CX_CPCIE_ENABLE)) && (CX_FREQ_STEP_DL_EN)
Synchronous To: CX_FREQ_STEP_EN ? "pipe_clk" : "core_clk"
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Common PIPE Signals
Synopsys, Inc.
mac_phy_rxstandby[(NL-1):0]...(cont.) O.
Refer to the User Guide for guidelines on how to configure this
parameter for each supported Synopsys Phy
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
phy_mac_rxdatavalid[(NL-1):0] I This signal allows a PHY to indicate valid data on the PIPE interface. A
value of '1' indicates that the data is valid and should be used. If your
PHY does not support this signal, then set it to '1'. You should set this
signal at the different link rates as follows:
■ Gen1: If data pacing is enabled in this mode, then toggle every other
or fourth clock, else '1'
■ Gen2: If data pacing is enabled in this mode, then toggle every other
or fourth clock, else '1'
■ Gen3: '1' except for regular de-assertion for 128b/130b
encoding/decoding
For more details, see the "Data Pacing (DP) Support" section in the
Product Overview chapter of the Databook. Clock tolerance
compensation is normally done by inserting or removing SKIP symbols
from a SKIP ordered set (OS). The controller also supports a
non-standard clock tolerance compensation mode at Gen3 speed. In
this mode SKIP OS's can be left unaltered in length. Clock tolerance
compensation is then achieved by modulating the period of de-assertion
of phy_mac_rxdatavalid. Therefore this input might be de-asserted
anywhere within a block (and not only at the end of a block), and the low
pulses can be up to two cycles long.
Exists: ((CX_CPCIE_ENABLE)) && (!CX_ADM_ADAPTOR_ENABLE)
&& (!SNPS_RSVDPARAM_26)
Synchronous To:
None,aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Common PIPE Signals
cfg_phy_control[31:0] O Output bus that can optionally be used for additional PHY control
purposes. The cfg_phy_control bus maps to the PHY Control register
(PHY_CONTROL_REG). For specific bit usage, see PHY Control
Register.
Exists: (CX_CPCIE_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
mac_phy_rxelecidle_disable O Instructs the PHY to disable the receiver Electrical Idle detection logic.
For more details, see 'L1 Substates'.
Exists: CX_L1_SUBSTATES_ENABLE
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
mac_phy_txcommonmode_disable O Instructs the PHY to disable the transmitter Common Mode logic. For
more details, see 'L1 Substates'.
Exists: CX_L1_SUBSTATES_ENABLE
Synchronous To: aux_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Gen2/3-Only PIPE Signals
- mac_phy_rate
- mac_phy_txdeemph
- mac_phy_txmargin
- mac_phy_txswing
- cfg_hw_auto_sp_dis
Synopsys, Inc.
mac_phy_txdeemph[(TX_DEEMPH_WD-1 O For Gen2 configurations, this two bits wide output selects transmitter
):0] de-emphasis as follows:
■ 00: -6 dB de-emphasis at 5GT/s
■ 01: -3.5 dB de-emphasis at 5GT/s
■ 10: No de-emphasis.
Note:This is the only possible value when PIPE is configured for low
swing (mac_phy_txswing == 1) as per base specification Sect.
4.3.3.6
For Gen3 configurations at Gen3 speed, this (NL*18)-bit output conveys
the transmitter equalization coefficients where:
■ [5:0]: C-1 (Pre-cursor)
■ [11:6]: C0 (Cursor)
■ [17:12]: C+1 (Post-cursor). If your PHY has assigned mac_phy_tx-
deemph[17:0] as {C-1, C0, C+1}, then you must swap C-1 and C+1
to match the mapping of these fields in the controller.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 2) : CX_S_CPCIE_MODE ?
(CX_GEN2_MODE != GEN2_DISABLED) : 0)) &&
(!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Gen2/3-Only PIPE Signals
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PCI Express SW Controller Databook Gen3-Only Equalization PIPE Signals
phy_mac_dirfeedback - - smlh_ltssm_state_rcvry_eq
phy_mac_fomfeedback - - mac_phy_rxpresethint
phy_mac_local_tx_pset_coef - - mac_phy_fs
phy_mac_local_tx_coef_valid - - mac_phy_lf
- mac_phy_local_pset_index
- mac_phy_getlocal_pset_coef
- mac_phy_rxeqinprogress
- mac_phy_invalid_req
- mac_phy_rxeqeval
- mac_phy_dirchange
smlh_ltssm_state_rcvry_eq O This status signal is asserted during all Recovery Equalization states.
Exists: (CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0)
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Gen3-Only Equalization PIPE Signals
phy_mac_fomfeedback[((NL*FOMFEEDB I Provides the link equalization evaluation feedback in the Figure of Merit
ACK_WD)-1):0] (FOM) format. The value is encoded as an integer from 0 to 255. You
should hardwire this input to a constant value when you are not using
FOM. This signal is only used at the 8.0 GT/s signaling rate.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: phy_mac_phystatus is pulsed, per lane
phy_mac_local_tx_pset_coef[((NL*TX_CO I These are the coefficients post-mapping from the preset the
EF_WD)-1):0] mac_phy_local_pset_index after a request
mac_phy_getlocal_pset_coef.
■ [5:0]: C-1
■ [11:6]: C0
■ [17:12]: C+1
The controller reflects these values mac_phy_txdeemph when it wants
to apply this preset. You must externally tie-off this input when
CX_GEN3_EQ_PSET_COEF_MAP_MODE ='Programmable Table' ||
'Dynamic MAC'.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: phy_mac_local_tx_coef_valid
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mac_phy_local_pset_index[((NL*PSET_ID O The TX equalization preset that the MAC wants the PHY to convert into
_WD)-1):0] coefficients. For more details, see mac_phy_getlocal_pset_coef
description. You can leave this output unconnected when
CX_GEN3_EQ_PSET_COEF_MAP_MODE ='Programmable Table' ||
'Dynamic MAC'. For ESM mode the ESM data rata0 corresponds to
PCIe mode 8 GT/s and the ESM data rate1 corresponds to PCIe mode
16 GT/s.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Gen3-Only Equalization PIPE Signals
mac_phy_rxeqinprogress[(NL-1):0] O This status signal is asserted and remains asserted for the duration of
Recovery.Equalization Phase2 when the PCIe controller is the USP
(Phase3 when DSP).
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
mac_phy_invalid_req[(NL-1):0] O Indicates that the Link Evaluation feedback requested a link partner TX
EQ setting that was out of range. The controller asserts this signal when
it detects an out-of-range error. It remains asserted until the next time
mac_phy_rxeqeval asserts.
Note: If your PHY requires mac_phy_invalid_req to follow the same
timing protocol as mac_phy_rxeqeval, you must program
GEN3_RELATED_OFF[23] register field to '1'.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
mac_phy_rxeqeval[(NL-1):0] O The PHY starts evaluation of the far end transmitter TX EQ settings
while this signal is held high by the controller.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Gen3-Only Equalization V7 Signals
phy_mac_v7_txeq_fs - - mac_phy_v7_rxeq_preset
phy_mac_v7_txeq_lf - - mac_phy_v7_rxeq_lffs
phy_mac_v7_rxeq_done - - mac_phy_v7_txeq_control
phy_mac_v7_rxeq_adapt_done - - mac_phy_v7_rxeq_control
phy_mac_v7_txeq_done - - mac_phy_v7_txeq_preset
phy_mac_v7_txeq_coeff - - mac_phy_v7_txeq_deemph
phy_mac_v7_rxeq_new_txcoeff - - mac_phy_v7_rxeq_txpreset
phy_mac_v7_rxeq_lffs_sel -
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PCI Express SW Controller Databook Gen3-Only Equalization V7 Signals
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PCI Express SW Controller Databook Gen3-Only Equalization V7 Signals
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PCI Express SW Controller Databook Gen3-Only PIPE Signals
phy_mac_rxstartblock - - mac_phy_txsyncheader
phy_mac_rxsyncheader - - mac_phy_txstartblock
phy_mac_localfs - - mac_phy_encodedecodebypass
phy_mac_locallf - - mac_phy_blockaligncontrol
mac_phy_txsyncheader[((NL*2)-1):0] O At 8.0 GT/s this is used by the PCIe controller MAC to tell the PHY the
value of the Sync header in the current 130b block.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
(!SNPS_RSVDPARAM_26)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
mac_phy_txstartblock[(NL-1):0] O Only used at the 8.0 GT/s signaling rate. This signal allows the PCIe
controller MAC to indicate (to the PHY) the starting cycle
mac_phy_txdata for a 128b block.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
(!SNPS_RSVDPARAM_26)
Synchronous To: aux_clk,aux_clk_g,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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mac_phy_blockaligncontrol O Enable EIEOS detection in the PHY. EIEOS detection is one of the
mechanisms used to control the block aligner in the PHY. The PCIe
controller uses this signal at the 8.0 GT/s signaling rate to disable the
PHY from searching for a new block alignment. The PHY should ignore
this signal in Gen3 loopback slave mode. This output is a level signal
and not a pulse. It is not time-sensitive, so you can re-register it if
required.
Note:For Virtex-7 GTX PHY configurations, EIOS detection is not used
and this Block Align Control output directs the PHY to perform internal
sync header detection and re-alignment.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
(!(CX_PIPE51_SUPPORT))
Synchronous To: aux_clk,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Gen3-Only PIPE Signals
phy_mac_rxstartblock[((NL*PHY_RXSB_ I Only used at the 8.0 GT/s signaling rate. This signal allows the PHY to
WD)-1):0] indicate (to the PCIe controller MAC) the starting cycle phy_mac_rxdata
for a 128b block. The starting byte for a 128b block must always start
with Bit 0 of the data interface.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
(!SNPS_RSVDPARAM_26)
Synchronous To:
aux_clk_g,core_clk_ug,ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
phy_mac_rxsyncheader[((NL*PHY_RXSH I At 8.0 GT/s this is used by the PHY to tell the PCIe controller MAC the
_WD)-1):0] value of the Sync header in the current 130b block.
Exists: ((CX_CPCIE_ENABLE)) && ((CX_SEL_PHY_MODE ?
(CX_MAX_CPCIE_SPEED >= 3) : CX_S_CPCIE_MODE ?
(CX_GEN3_MODE != GEN3_DISABLED) : 0)) &&
(!SNPS_RSVDPARAM_26)
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
phy_mac_localfs[((NL*TX_FS_WD)-1):0] I At 8.0 GT/s rate, it is the Local FS value advertised by the local PHY.
This signal is driven to a constant value following the first speed change
to Gen3. You must externally tie-off this input when
CX_GEN3_EQ_PSET_COEF_MAP_MODE ='Programmable Table'.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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phy_mac_locallf[((NL*TX_FS_WD)-1):0] I At 8.0 GT/s rate, it is the Local LF value advertised by the local PHY.
This signal is driven to a constant value following the first speed change
to Gen3. You must externally tie-off this input when
CX_GEN3_EQ_PSET_COEF_MAP_MODE ='Programmable Table'.
Exists: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
&& ((CX_CPCIE_ENABLE && (CX_PHY_INTERFACE ==
PIPE_INTERFACE))) && (!(CX_PIPE51_SUPPORT))
Synchronous To: ret_core_clk,{core_clk},{pipe_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Gen4-Only Margining Signals
app_margining_ready -
app_margining_software_ready -
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phy_mac_messagebus - - mac_phy_messagebus
phy_mac_pbus - - mac_phy_mbus
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PCI Express SW Controller Databook SerDes PIPE Signals
pipe_rx_clk -
pipe_rx_rst_n -
pipe_rx_clk[(NL-1):0] I RxCLK from external PHY. This clock signal is recovered clock used for
RxData in the SerDes architecture.
Exists: ((CX_CPCIE_ENABLE)) && (SNPS_RSVDPARAM_26)
Synchronous To: None
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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app_crosslink_time - - smlh_crosslink_active
- smlh_crosslink_time_request
smlh_crosslink_time_request O A pulse indicating the controller needs a new random crosslink timeout
value supplied the app_crosslink_time signal.
Exists: CX_CROSSLINK_ENABLE
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook Peer-to-Peer Signals
client0_app_dev_id - - radm_bypass_rsvd
client0_hdr_rsvd - - radm_trgt1_rsvd
client1_app_dev_id -
client1_hdr_rsvd -
client2_app_dev_id -
client2_hdr_rsvd -
client0_hdr_rsvd[14:0] I Used to provide header reserved fields for the TLP being presented to
the client0 interface. The input bits are mapped to the TLP header
reserved fields as follows:
■ [14] .....................DWORD2 Byte11, bit[7]
■ [13:12] ................DWORD2 Byte11, bits[1:0] for 32-bit address TLP;
DWORD3 Byte15, bits[1:0] for 64-bit address TLP
■ [11:8] ..................DWORD2 Byte10, bits[7:4]
■ [7:6] ....................DWORD0 Byte2, bits[3:2]
■ [5] .......................DWORD0 Byte1, bit[7]
■ [4:1] ....................DWORD0 Byte1, bits[3:0]
■ [0] .......................DWORD0 Byte0, bit[7]
Exists: (!(AMBA_INTERFACE!=0)) && (CX_P2P_ENABLE==1 ||
CC_DEVICE_TYPE==CC_SW)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: client0_tlp_hv is asserted
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client1_hdr_rsvd[14:0] I Provides the same information as client0_hdr_rsvd but for the client1
interface.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT1_POPULATED) &&
(CX_P2P_ENABLE==1 || CC_DEVICE_TYPE==CC_SW)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: client1_tlp_hv is asserted
client2_hdr_rsvd[14:0] I Provides the same information as client0_hdr_rsvd but for the client2
interface.
Exists: (!(AMBA_INTERFACE!=0)) && (CLIENT2_POPULATED) &&
(CX_P2P_ENABLE==1 || CC_DEVICE_TYPE==CC_SW)
Synchronous To: core_clk
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: client2_tlp_hv is asserted
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PCI Express SW Controller Databook Peer-to-Peer Signals
radm_bypass_rsvd[((NHQ*15)-1):0] O Used to output header reserved fields of TLPs presented the bypass
interface. The bit mapping is the same as client0_hdr_rsvd.
Exists: (!(AMBA_INTERFACE!=0)) && ((CX_RADMQ_MODE==2)) &&
(CX_P2P_ENABLE==1 || CC_DEVICE_TYPE==CC_SW)
Synchronous To: aux_clk,aux_clk_g,core_clk,{radm_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_bypass_hv is asserted
radm_trgt1_rsvd[14:0] O Used to output header reserved fields of TLPs presented the target1
interface. The bit mapping is the same as client0_hdr_rsvd.
Exists: (!(AMBA_INTERFACE!=0)) && (TRGT1_POPULATE) &&
(CX_P2P_ENABLE==1 || CC_DEVICE_TYPE==CC_SW)
Synchronous To: radm_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: radm_trgt1_hv is asserted
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cdm_ras_des_ec_ram_dataout - - cdm_ras_des_ec_ram_addra
- cdm_ras_des_ec_ram_addrb
- cdm_ras_des_ec_ram_datain
- cdm_ras_des_ec_ram_wea
- cdm_ras_des_ec_ram_ena
- cdm_ras_des_ec_ram_enb
cdm_ras_des_ec_ram_addra[(RASDES_ O Port A write address for the RAM in RAS D.E.S. event counter register.
EC_RAM_ADDR_WIDTH-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_ec_ram_wea &
cdm_ras_des_ec_ram_ena are asserted
cdm_ras_des_ec_ram_addrb[(RASDES_ O Port B read address for the RAM in RAS D.E.S. event counter register.
EC_RAM_ADDR_WIDTH-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_ec_ram_enb is asserted
cdm_ras_des_ec_ram_datain[(RASDES_ O Port A write data to the RAM in RAS D.E.S. event counter register.
EC_RAM_DATA_WIDTH-1):0] Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_ec_ram_wea &
cdm_ras_des_ec_ram_ena are asserted
cdm_ras_des_ec_ram_wea O Port A write enable for the RAM in RAS D.E.S. event counter register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook RAS D.E.S. Event Counter RAM Signals
cdm_ras_des_ec_ram_ena O Port A access enable for the RAM in RAS D.E.S. event counter register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cdm_ras_des_ec_ram_enb O Port B access enable for the RAM in RAS D.E.S. event counter register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cdm_ras_des_ec_ram_dataout[(RASDES I Port B read data from the RAM that used in RAS D.E.S. event counter
_EC_RAM_DATA_WIDTH-1):0] register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_EC_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
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- cdm_ras_des_ec_info_common
- cdm_ras_des_ec_info_i (for i = 0; i <=
CX_NL)
cdm_ras_des_ec_info_common[(RASDES O Common event signal bus that is used in RAS D.E.S. event counters
_EC_INFO_CM-1):0] ■ [170:167]: rtlh_rx_ccix_tlp_evt: Pulse: Rx CCIX TLP
■ [166:165]: xtlh_tx_ccix_tlp_evt: Pulse: Tx CCIX TLP
■ [164:161]: rtlh_rx_tlpwprefix_evt: Pulse: Rx TLP with Prefix
■ [160:157]: rtlh_rx_atmcop_evt: Pulse: Rx Atomic
■ [156:153]: rtlh_rx_msg_evt: Pulse: Rx Message TLP
■ [152:149]: rtlh_rx_cplwd_evt: Pulse: Rx Completion w data
■ [148:145]: rtlh_rx_cplwod_evt: Pulse: Rx Completion wo data
■ [144:141]: rtlh_rx_iord_evt: Pulse: Rx IO Read
■ [140:137]: rtlh_rx_iowr_evt: Pulse: Rx IO Write
■ [136:133]: rtlh_rx_cfgrd_evt: Pulse: Rx Config Read
■ [132:129]: rtlh_rx_cfgwr_evt: Pulse: Rx Config Write
■ [128:125]: rtlh_rx_memrd_evt: Pulse: Rx Memory Read
■ [124:121]: rtlh_rx_memwr_evt: Pulse: Rx Memory Write
■ [120:119]: xtlh_tx_tlpwprefix_evt: Pulse: Tx TLP with Prefix
■ [118:117]: xtlh_tx_atmcop_evt: Pulse: Tx AtomicOp
■ [116:115]: xtlh_tx_msg_evt: Pulse: Tx Message
■ [114:113]: xtlh_tx_cplwd_evt: Pulse: Tx Completion w data
■ [112:111]: xtlh_tx_cplwod_evt: Pulse: Tx Completion wo data
■ [110:109]: xtlh_tx_iord_evt: Pulse: Tx IO Read
■ [108:107]: xtlh_tx_iowr_evt: Pulse: Tx IO Write
■ [106:105]: xtlh_tx_cfgrd_evt: Pulse: Tx Config Read
■ [104:103]: xtlh_tx_cfgwr_evt: Pulse: Tx Config Write
■ [102:101]: xtlh_tx_memrd_evt: Pulse: Tx Memory Read
■ [100:99]: xtlh_tx_memwr_evt: Pulse: Tx Memory Write
■ [98:95]: rdlh_duplicate_tlp_err_pertlp: Pulse: Rx Duplicate TLP
■ [94]: xtlh_xadm_restore_enable: Pulse: Tx Nullified TLP
■ [93:90]: rdlh_nulified_tlp_err_pertlp : Pulse: Rx Nullified TLP
■ [89:82]: rtlh_rcvd_ufc_perdllp: Pulse: Rx Update FC DLLP
■ [81:74]: rdlh_rcvd_ack_perdllp: Pulse: Rx Ack DLLP
■ [73]: xdlh_update_fc_sent: Pulse: Tx Update FC DLLP
■ [72]: xdlh_ack_sent: Pulse: Tx Ack DLLP
■ [71]: smlh_lwd_change: Pulse: Link width Change
■ [70]: smlh_spd_change: Pulse: Speed Change
■ [69]: smlh_in_l23: Level: L2 Entry
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PCI Express SW Controller Databook RAS D.E.S. Event Counters Debug Signals
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cdm_ras_des_ec_info_i[(RASDES_EC_IN O Laneievent signal bus that is used in RAS D.E.S. event counters.
FO_PL-1):0] ■ [12]: |rmlh_deskew_ctlskp_err[i*5+4:i*5+3]: Pulse: Margin CRC and
(for i = 0; i <= CX_NL) Parity Error
■ [11]: rmlh_deskew_ctlskp_err[i*5+2]: Pulse: 2nd Retimer Parity Error
■ [10]: rmlh_deskew_ctlskp_err[i*5+1]: Pulse: 1st Retimer Parity Error
■ [9]: rmlh_deskew_ctlskp_err[i*5]: Pulse: CTL SKP OS Data Parity
Error
■ [8]: rmlh_ebuf_rxskipremoved: Pulse: EBUF SKP Del
■ [7]: rmlh_ebuf_rxskipadded: Pulse: EBUF SKP Add
■ [6]: rmlh_rxvalid_deasserted: Pulse: Rx Valid de-assertion
■ [5]: rmlh_sync_header_err: Pulse: SYNC Header Error
■ [4]: rmlh_skp_parity_err: Pulse: SKP OS Parity Error
■ [3]: rmlh_phy_rxdisperror: Pulse: Running Disparity Error
■ [2]: rmlh_phy_rxcodeerror: Pulse: Decode Error
■ [1]: rmlh_ebuf_rxunderflow: Pulse: EBUF underrun
■ [0]: rmlh_ebuf_rxoverflow: Pulse: EBUF Overflow
Exists: (CX_RAS_DES_EC_ENABLE) &&
(CX_RAS_DES_DBGIO_ENABLE)
Synchronous To: None,perbitclk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
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PCI Express SW Controller Databook RAS D.E.S. Silicon Debug Internal Signals
app_ras_des_sd_hold_ltssm - - cdm_ras_des_sd_info_common
- cdm_ras_des_sd_info_i (for i = 0; i <=
CX_NL)
- cdm_ras_des_sd_info_vi (for i = 0; i <=
CX_NVC)
app_ras_des_sd_hold_ltssm I Hold and release LTSSM. For as long as this signal is '1', thecontroller
stays in the current LTSSM.
Exists: CX_RAS_DES_SD_ENABLE
Synchronous To: ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
Synopsys, Inc.
cdm_ras_des_sd_info_common[(RASDES O Common debug signal bus that is used in RAS D.E.S. silicon debug
_SD_INFO_CM-1):0] ■ [78]: init_eq_pending_g4: Level: Equalization sequence Gen5
■ [77:75]: l1sub_state: Level: L1 sub state
■ [74]: init_eq_pending_g4: Level: Equalization sequence Gen4
■ [73]: init_eq_pending: Level: Equalization sequence Gen3
■ [72:61]: xdlh_curnt_seqnum [11:0]: Level: Tx TLP SEQ#
■ [60:49]: rdlh_curnt_rx_ack_seqnum[11:0]: Level: Rx ACK SEQ#
■ [48]: rdlh_vc0_initfc2_status: Level: Init-FC Flag2 VC0
■ [47]: rdlh_vc0_initfc1_status: Level: Init-FC Flag1 VC0
■ [46:45]: rdlh_dlcntrl_state [1:0]: Level: DLCM
■ [44:37]: latched_ts_nfts[7:0]: Level: Latched NFTS
■ [36:34]: ltssm_powerdown[1:0]: Level: PIPE: Power Down
■ [33:18]: smlh_ltssm_variable [15:0]: Level: LTSSM Variable
■ [17]: pm_pme_resend_flag: Pulse: PME Re-Send flag
■ [16]: smlh_lane_reversed: Level: Lane Reversal Operation
■ [15:9]: rmlh_framing_err_ptr[6:0]: Pulse: 1st Framing Error Pointer
■ [8:5]: pm_slave_state[3:0]: Level: PM Internal State (Slave)
■ [4:0]: pm_master_state[4:0]: Level: PM Internal State (Master)
Exists: (CX_RAS_DES_SD_ENABLE) &&
(CX_RAS_DES_DBGIO_ENABLE)
Synchronous To:
None,aux_clk,core_clk,perbitclk,ret_core_clk,{aux_clk_g}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
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PCI Express SW Controller Databook RAS D.E.S. Silicon Debug Internal Signals
cdm_ras_des_sd_info_i[(RASDES_SD_IN O Laneidebug signal bus that is used in RAS D.E.S. silicon debug
FO_PL-1):0] ■ [204:203]: eq_convergence_sts_g5 [1:0]: Level: Equalization
(for i = 0; i <= CX_NL) convergence information Gen5
■ [202]: eqpa_violate_rule_123_g5[2]: Level: Rule C Violation Event
Status Gen5
■ [201]: eqpa_violate_rule_123_g5[1]: Level: Rule B Violation Event
Status Gen5
■ [200]: eqpa_violate_rule_123_g5[0]: Level: Rule A Violation Event
Status Gen5
■ [199]: mac_cdm_ras_des_reject_rtx_g5: Level: Receive Reject
Coefficient Event status Gen5
■ [198:191]: phy_cdm_ras_des_fomfeedback_g5: Level: Current
Figure of Merit Gen5
■ [190:185]: mac_cdm_ras_des_coef_ltx_g5[5:0]: Level: Current
Local Transmitter Pre Cursor coefficient Gen5
■ [184:179]: mac_cdm_ras_des_coef_ltx_g5[11:6]: Level: Current
Local Transmitter Cursor coefficient Gen5
■ [178:173]: mac_cdm_ras_des_coef_ltx_g5[17:12]: Level: Current
Local Transmitter Post Cursor coefficient Gen5
■ [172:167]: mac_cdm_ras_des_coef_rtx_g5[5:0]: Level: Current
Remote Transmitter Pre Cursor coefficient Gen5
■ [166::161]: mac_cdm_ras_des_coef_rtx_g5[11:6]: Level: Current
Remote Transmitter Cursor coefficient Gen5
■ [160:155]: mac_cdm_ras_des_coef_rtx_g5[17:12]: Level: Current
Remote Transmitter Post Cursor coefficient Gen5
■ [154:149]: mac_cdm_ras_des_lf_g5: Level: Remote Device LF
Gen5
■ [148:143]: mac_cdm_ras_des_fs_g5: Level: Remote Device FS
Gen5
■ [142:141]: eq_convergence_sts_g4 [1:0]: Level: Equalization
convergence information Gen4
■ [140]: eqpa_violate_rule_123_g4[2]: Level: Rule C Violation Event
Status Gen4
■ [139]: eqpa_violate_rule_123_g4[1]: Level: Rule B Violation Event
Status Gen4
■ [138]: eqpa_violate_rule_123_g4[0]: Level: Rule A Violation Event
Status Gen4
■ [137]: mac_cdm_ras_des_reject_rtx_g4: Level: Receive Reject
Coefficient Event status Gen4
■ [136:129]: phy_cdm_ras_des_fomfeedback_g4: Level: Current
Figure of Merit Gen4
■ [128:126]: 3'b000: Reserved
■ [125:120]: mac_cdm_ras_des_coef_ltx_g4[5:0]: Level: Current
Local Transmitter Pre Cursor coefficient Gen4
Synopsys, Inc.
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PCI Express SW Controller Databook RAS D.E.S. Silicon Debug Internal Signals
Synopsys, Inc.
cdm_ras_des_sd_info_vi[(RASDES_SD_I O VCidebug signal bus that is used in RAS D.E.S. silicon debug.
NFO_PV-1):0] ■ [239:228]: rtlh_fc_allctd_cpld: Level: Credit Allocated (CD) VCn
(for i = 0; i <= CX_NVC)
■ [227:220]: rtlh_fc_allctd_cplh: Level: Credit Allocated (CH) VCn
■ [219:208]: rtlh_fc_allctd_npd: Level: Credit Allocated (ND) VCn
■ [207:200]: rtlh_fc_allctd_nph: Level: Credit Allocated (NH) VCn
■ [199:188]: rtlh_fc_allctd_pd: Level: Credit Allocated (PD) VCn
■ [187:180]: rtlh_fc_allctd_ph: Level: Credit Allocated (PH) VCn
■ [179:168]: rtlh_fc_rcvd_cpld: Level: Credit Received (CD) VCn
■ [167:160]: rtlh_fc_rcvd_cplh: Level: Credit Received (CH) VCn
■ [159:148]: rtlh_fc_rcvd_npd: Level: Credit Received (ND) VCn
■ [147:140]: rtlh_fc_rcvd_nph: Level: Credit Received (NH) VCn
■ [139:128]: rtlh_fc_rcvd_pd: Level: Credit Received (PD) VCn
■ [127:120]: rtlh_fc_rcvd_ph: Level: Credit Received (PH) VCn
■ [119:108]: xadm_fc_limit_cpld: Level: Credit Limit (CD) VCn
■ [107:100]: xadm_fc_limit_cplh: Level: Credit Limit (CH) VCn
■ [99:88]: xadm_fc_limit_npd: Level: Credit Limit (ND) VCn
■ [87:80]: xadm_fc_limit_nph: Level: Credit Limit (NH) VCn
■ [79:68]: xadm_fc_limit_pd: Level: Credit Limit (PD) VCn
■ [67:60]: xadm_fc_limit_ph: Level: Credit Limit (PH) VCn
■ [59:48]: xadm_fc_cnsmd_cpld: Level: Credit Consumed (CD) VCn
■ [47:40]: xadm_fc_cnsmd_cplh: Level: Credit Consumed (CH) VCn
■ [39:28]: xadm_fc_cnsmd_npd: Level: Credit Consumed (ND) VCn
■ [27:20]: xadm_fc_cnsmd_nph: Level: Credit Consumed (NH) VCn
■ [19:8]: xadm_fc_cnsmd_pd: Level: Credit Consumed (PD) VCn
■ [7:0]: xadm_fc_cnsmd_ph: Level: Credit Consumed (PH) VCn
Exists: (CX_RAS_DES_SD_ENABLE) &&
(CX_RAS_DES_DBGIO_ENABLE) && (Always)
Synchronous To: aux_clk_g,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
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PCI Express SW Controller Databook RAS D.E.S. Time-Based Analysis Debug Signals
app_ras_des_tba_ctrl - - cdm_ras_des_tba_info_common
cdm_ras_des_tba_info_common[(RASDE O Common event signal status bus used in RAS D.E.S. time based
S_TBA_INFO_CM-1):0] analysis. Indicates the internal signals that are used in the time-based
analysis . The results are in TIME_BASED_ANALYSIS_DATA_REG.
Each bit indicates the state that the controller stays in. All signals are
level sensitive unless otherwise indicated.
■ [6]: smlh_link_in_training: Config/Recovery
■ [5]: pm_in_l12: L1.2
■ [4]: pm_in_l11: L1.1
■ [3]: smlh_in_l1: L1
■ [2]: smlh_in_l0: L0
■ [1]: smlh_in_rl0s: Rx L0s
■ [0]: smlh_in_l0s: Tx L0s
Exists: (CX_RAS_DES_TBA_ENABLE) &&
(CX_RAS_DES_DBGIO_ENABLE)
Synchronous To: None,aux_clk,perbitclk,ret_core_clk,{core_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: See description.
Validated by: Not validated by another signal
app_ras_des_tba_ctrl[1:0] I Controls the start/end of time based analysis. You must only set the pins
to the required value for the duration of one clock cycle. This signal must
be 2'b00 while the TIMER_START field in
TIME_BASED_ANALYSIS_CONTROL_REG register is controlled by
the DBI interface or the accesses from the wire side.
■ 2'b00: No action
■ 2'b01: Start
■ 2'b10: End. This setting is only used when the TIME_BASED_DU-
RATION_SELECT field of TIME_BASED_ANALYSIS_CON-
TROL_REG is set to "manual control".
■ 2'b11: Reserved
These pins also set the contents of the TIMER_START field in
TIME_BASED_ANALYSIS_CONTROL_REG register.
Exists: CX_RAS_DES_TBA_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
Synopsys, Inc.
cdm_ras_des_tba_ram_dataout - - cdm_ras_des_tba_ram_addra
- cdm_ras_des_tba_ram_addrb
- cdm_ras_des_tba_ram_datain
- cdm_ras_des_tba_ram_wea
- cdm_ras_des_tba_ram_ena
- cdm_ras_des_tba_ram_enb
cdm_ras_des_tba_ram_addra[(RASDES_ O Port A write address for the RAM in RAS D.E.S. time based analysis
TBA_RAM_ADDR_WIDTH-1):0] register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_tba_ram_wea &
cdm_ras_des_tba_ram_ena are asserted
cdm_ras_des_tba_ram_addrb[(RASDES_ O Port B read address for the RAM in RAS D.E.S. time based analysis
TBA_RAM_ADDR_WIDTH-1):0] register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_tba_ram_enb is asserted
cdm_ras_des_tba_ram_datain[(RASDES_ O Port A write data for the RAM in RAS D.E.S. time based analysis
TBA_RAM_DATA_WIDTH-1):0] register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: cdm_ras_des_tba_ram_wea &
cdm_ras_des_tba_ram_ena are asserted
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PCI Express SW Controller Databook RAS D.E.S. Time-Based Analysis RAM Signals
cdm_ras_des_tba_ram_wea O Port A write enable for the RAM in RAS D.E.S. time based analysis
register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cdm_ras_des_tba_ram_ena O Port A access enable for the RAM in RAS D.E.S. time based analysis
register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cdm_ras_des_tba_ram_enb O Port B access enable for the RAM in RAS D.E.S. time based analysis
register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cdm_ras_des_tba_ram_dataout[(RASDES I Port B read data from the RAM that used in RAS D.E.S. time based
_TBA_RAM_DATA_WIDTH-1):0] analysis register.
Exists: (CX_RAM_AT_TOP_IF) && (CX_RAS_DES_TBA_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
Synopsys, Inc.
cii_lbc_halt - - lbc_cii_hv
cii_lbc_override_en - - lbc_cii_hdr_poisoned
cii_lbc_override_data - - lbc_cii_hdr_type
- lbc_cii_hdr_first_be
- lbc_cii_hdr_tag
- lbc_cii_hdr_req_id
- lbc_cii_hdr_addr
- lbc_cii_hdr_bus_num
- lbc_cii_hdr_dev_num
- lbc_cii_hdr_func_num
- lbc_cii_dv
- lbc_cii_data
lbc_cii_hv O Indicates that the header information outputs and lbc_cii_dv signal of
CII are valid. For more details, see the "Advanced LBC and DBI Usage"
advanced information chapter in the Databook.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
lbc_cii_hdr_poisoned O The Poisoned (EP) bit in the received TLP header on CII.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted
lbc_cii_hdr_type[4:0] O The Type field in the received TLP header on CII. Only the following TLP
Type can be appeared on CII.
■ 00100b: Configuration Read/Write Type0
■ 00101b: Configuration Read/Write Type1 (SRIOV configuration
only)
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted
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PCI Express SW Controller Databook Configuration Intercept Interface (CII) Signals
lbc_cii_hdr_first_be[3:0] O The first dword byte enable field in the received TLP header on CII.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted
Synopsys, Inc.
lbc_cii_dv O Indicates that the data information outputs of CII are valid. This signal is
asserted only for a configuration Write request.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted
lbc_cii_data[31:0] O Received TLP payload data from the link partner to your application
client. The data is in little endian format. The first received payload byte
is in [7:0].
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_dv is asserted
cii_lbc_halt I Flow control input signal. When cii_lbc_halt is asserted, the controller
halts processing of CFG requests for the CDM and ELBI configuration
spaces. For more details, see the "Advanced LBC and DBI Usage"
advanced information chapter in the Databook.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted
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PCI Express SW Controller Databook Configuration Intercept Interface (CII) Signals
cii_lbc_override_en I Override enable. When your application logic asserts this input, the
controller overrides the CfgWr payload or CfgRd completion using the
data supplied by your application logic on cii_lbc_override_data. For
more details, see the "Advanced LBC and DBI Usage" advanced
information chapter in the Databook.
Exists: CX_CONFIG_INTERCEPT_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: lbc_cii_hv is asserted
Synopsys, Inc.
- cfg_reg_serren
- cfg_cor_err_rpt_en
- cfg_nf_err_rpt_en
- cfg_f_err_rpt_en
cfg_nf_err_rpt_en[(NF-1):0] O PF's Non-Fatal Error Reporting Enable registers value in Device Control
Register of PCIe Capability, for sending ERR_MSG of external VFs.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_f_err_rpt_en[(NF-1):0] O PF's Fatal Error Reporting Enable registers value in Device Control
Register of PCIe Capability, for sending ERR_MSG of external VFs.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook PHY Register Bus Interface Signals
app_hold_phy_rst - - en_phy_reg_clk_g
phy_reg_clk_ug - - phy_cr_para_wr_en
phy_reg_clk_g - - phy_cr_para_rd_en
phy_reg_rst_n - - phy_cr_para_addr
phy_cr_para_ack - - phy_cr_para_wr_data
phy_cr_para_rdata -
app_hold_phy_rst I Set this signal to one before the de-assertion of power on reset to hold
the PHY in reset. This can be used to configure your PHY. Synopsys
PHYs can be configured through the PHY Viewport if desired. Please tie
this port to zero if your design does not need this feature.
Exists: Always
Synchronous To: aux_clk_g,{aux_clk}
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
phy_reg_clk_ug I Ungated clock for the PHY register interface. This clock should be
always active when you need to access the PHY registers through the
PHY register bus interface(PRBI). The maximum frequency of the clock
is 100 MHz.
Note:For Synopsys PHYs supporting Control Register (CR) Parallel
Interface, this signal should not be connected to the PHY if the PHY
registers are accessed through the PRBI. You should connect
phy_reg_clk_g to the PHY.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: N/A
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
phy_reg_clk_g I This clock is gated by en_phy_reg_clk_g for the PHY Register Bus
Interface.
Note:For Synopsys PHYs supporting Control Register (CR) Parallel
Interface, this clock should be used as cr_para_clk.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: N/A
Registered: N/A
Power Domain: PD_VAUX
Active State: N/A
Validated by: Not validated by another signal
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PCI Express SW Controller Databook PHY Register Bus Interface Signals
phy_cr_para_wr_en[(PHY_VPT_NUM-1):0 O Control Register (CR) write enable. When this signal is asserted, data
] on phy_cr_para_wr_data is written to the address referenced on
phy_cr_para_addr. This signal is asserted for a single cycle.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: phy_reg_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
phy_cr_para_rd_en[(PHY_VPT_NUM-1):0 O Control Register (CR) read enable. When this signal is asserted, data is
] read from the address referenced on phy_cr_para_addr and provided
on phy_cr_para_rd_data. This signal is asserted for a single cycle.
Exists: CX_PHY_VIEWPORT_ENABLE
Synchronous To: phy_reg_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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- cfg_vf_ats_stu
- cfg_vf_ats_cache_en
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PCI Express SW Controller Databook SII: BDF Signals
app_dev_num -
app_bus_num -
app_dev_num[4:0] I Device number. Your application must drive this signal to set the device
number in the Requester ID for RC port and Switch DSP port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
app_bus_num[7:0] I Bus number. Your application must drive this signal to set the bus
number in the Requester ID for RC port and Switch DSP port.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
app_dpc_rp_busy - - core_in_dpc
app_dpc_err_valid - - cfg_dpc_int_msg_num
app_dpc_err_bus - - cfg_dpc_rp_ext_dpc
app_dpc_impspec_log - - cfg_dpc_poison_tlp_egr_blk_support
app_flush_ack - - cfg_dpc_sw_trig_support
- cfg_dpc_rp_pio_log_size
- cfg_dpc_dl_active_err_cor_support
- cfg_dpc_trig_en
- cfg_dpc_cpl_cntrl
- cfg_dpc_int_en
- cfg_dpc_err_cor_en
- cfg_dpc_poison_tlp_egr_block_en
- cfg_dpc_sw_trigger
- cfg_dpc_dl_active_err_cor_en
- rstctl_core_flush_req
app_dpc_rp_busy I DPC Root Port Busy . When Set, it indicates that the Root Port is busy
with internal activity. DPC is event triggered. Used to update the
corresponding DPC Status register field.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: DPC Signals
app_dpc_err_bus[5:0] I The type of error that your application detected which triggered DPC.
The controller uses app_dpc_err_bus to set the corresponding bits in
the RP PIO Status Register:
■ app_dpc_err_bus[0]: Configuration Request
■ app_dpc_err_bus[1]: I/O Request
■ app_dpc_err_bus[2]: Memory Request
■ app_dpc_err_bus[3]: received UR Completion
■ app_dpc_err_bus[4]: received CA Completion
■ app_dpc_err_bus[5]: Completion Timeout
Used to update DPC RP PIO Status Registe
Exists: (CX_DPC_ENABLE) && (CX_DPC_RP_PIO_EXTNS)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_dpc_rp_ext_dpc O RP Extensions for DPC. If Set, this bit indicates that a Root Port
supports a defined set of DPC Extensions that are specific to Root
Ports.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
cfg_dpc_poison_tlp_egr_blk_support O Poisoned TLP Egress Blocking Supported. If Set, this bit indicates that
the Root Port or Switch Downstream Port supports the ability to block
the transmission of a poisoned TLP from its Egress Port.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
cfg_dpc_sw_trig_support O DPC Software Triggering Supported. If Set, this bit indicates that a Root
Port or Switch Downstream Port supports the ability for software to
trigger DPC.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
cfg_dpc_rp_pio_log_size[3:0] O RP PIO Log Size. This field indicates how many DWORDs are allocated
for the RP PIO log registers comprised by the RP PIO Header Log, the
RP PIO ImpSpec Log and RP PIO TLP Prefix Log.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: DPC Signals
cfg_dpc_dl_active_err_cor_support O DL_Active ERR_COR Signaling Supported. If Set, this bit indicates that
the Root Port or Switch Downstream Port supports the ability to signal
with ERR_COR when the Link transitions to the DL_Active state.
Exists: CX_DPC_ENABLE
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
Synopsys, Inc.
rstctl_core_flush_req O Flush request after LTSSM has been directed to DISABLE state.
Exists: (!AXI_RADM_SEG_BUF_ENABLE &&
FLUSH_CNTRL_ENABLE)
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High (level)
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: TLP Bypass Internal Error Reporting Signals
- cfg_uncor_internal_err_sts
- cfg_rcvr_overflow_err_sts
- cfg_fc_protocol_err_sts
- cfg_mlf_tlp_err_sts
- cfg_surprise_down_er_sts
- cfg_dl_protocol_err_sts
- cfg_ecrc_err_sts
- cfg_corrected_internal_err_sts
- cfg_replay_number_rollover_err_sts
- cfg_replay_timer_timeout_err_sts
- cfg_bad_dllp_err_sts
- cfg_bad_tlp_err_sts
- cfg_rcvr_err_sts
cfg_uncor_internal_err_sts O Indication from the controller that the controller has detected an
Uncorrectable Internal Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_rcvr_overflow_err_sts O Indication from the controller that the controller has detected an
Receiver Overflow Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_fc_protocol_err_sts O Indication from the controller that the controller has detected an Flow
Control Protocol Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
cfg_mlf_tlp_err_sts O Indication from the controller that the controller detected an Malformed
TLP Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_surprise_down_er_sts O Indication from the controller that the controller detected an Surprise
Down Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_dl_protocol_err_sts O Indication from the controller that the controller detected an Data Link
Protocol Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_ecrc_err_sts O Indication from the controller that the controller detected an ECRC
Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_corrected_internal_err_sts O Indication from the controller that the controller detected an Corrected
Internal Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
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PCI Express SW Controller Databook SII: TLP Bypass Internal Error Reporting Signals
cfg_replay_timer_timeout_err_sts O Indication from the controller that the controller detected an Replay
Timer Timeout.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_bad_dllp_err_sts O Indication from the controller that the controller detected an Bad DLLP
Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_bad_tlp_err_sts O Indication from the controller that the controller detected an Bad TLP
Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
cfg_rcvr_err_sts O Indication from the controller that the controller detected an Receiver
Error.
Exists: Always
Synchronous To: aux_clk_g
Registered: N/A
Power Domain: PD_VAUX
Active State: High
Validated by: Not validated by another signal
Synopsys, Inc.
6
Parameter Descriptions
This chapter details all the configuration parameters. You can use the coreConsultant GUI configuration
reports to determine the complete configuration state of the controller. Some expressions might refer to
TCL functions or procedures (sometimes identified as <functionof>) that coreConsultant uses to make
calculations. The exact formula used by these TCL functions is not provided in this chapter. However, when
you configure the controller in coreConsultant, all TCL functions and parameters are evaluated completely;
and the resulting values are displayed where appropriate in the coreConsultant GUI reports.
The parameter descriptions in this chapter include the Enabled: attribute which indicates the values
required to be set on other parameters before you can change the value of this parameter.
These tables define all of the configuration options for this component.
■ “Main Features Config Parameters” on page 633
■ “Basic Features Config / PCIe Basic Features Config Parameters” on page 637
■ “Basic Features Config / Common Basic Features Config Parameters” on page 649
■ “DMA Configuration Parameters” on page 657
■ “Basic AXI Config Parameters” on page 659
■ “Basic AXI Config / PCIe TAGs and AXI IDs Parameters” on page 666
■ “Basic AXI Config / PCIe and AHB TAGs Parameters” on page 668
■ “Device-Wide Optional Non-PCIe Config Parameters” on page 669
■ “Advanced AXI Config / Advanced AHB Config Parameters” on page 696
■ “Advanced AXI Config / Advanced AXI Config Parameters” on page 699
■ “Device-Wide PCIe Features and Capabilities Config / MSI/MSI-X Capability Parameters” on page
703
■ “Device-Wide PCIe Features and Capabilities Config / PCIe Capability Parameters” on page 705
■ “Device-Wide PCIe Features and Capabilities Config / PF Extended Capabilities Parameters” on page
714
■ “Device-Wide PCIe Features and Capabilities Config / VC Capability Parameters” on page 718
■ “Device-Wide PCIe Features and Capabilities Config / Slot ID Capability Parameters” on page 719
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PCI Express SW Controller Databook Parameter Descriptions
■ “Device-Wide PCIe Features and Capabilities Config / AtomicOp Support Options Parameters” on
page 720
■ “Device-Wide PCIe Features and Capabilities Config / Readiness Support Options Parameters” on
page 722
■ “Device-Wide PCIe Features and Capabilities Config / Lightweight Notification Support Options
Parameters” on page 725
■ “Device-Wide PCIe Features and Capabilities Config / Other Optional PCIe Features Parameters” on
page 726
■ “Device-Wide PCIe Features and Capabilities Config / SR-IOV Related Features Parameters” on page
728
■ “Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities Parameters” on page
730
■ “Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability Parameters”
on page 738
■ “Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM Capability / L1
Substates Capability Register Defaults Parameters” on page 740
■ “Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support Parameters” on page 741
■ “Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support / PASID Capability
Register Defaults Parameters” on page 742
■ “Device-Wide PCIe Features and Capabilities Config / Precision Time Management Support Options
Parameters” on page 743
■ “Device-Wide PCIe Features and Capabilities Config / Secondary PCIe Extended Capability Param-
eters” on page 744
■ “Device-Wide PCIe Features and Capabilities Config / CCIX Transport DVSEC Parameters” on page
746
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Express Capability
Parameters” on page 749
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / MSI-X Register Config-
uration (PF0) Parameters” on page 750
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Advanced Error
Register Configuration Parameters” on page 752
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / TLP Processing Hints
Register Configuration (PF0) Parameters” on page 753
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ATS Register Config-
uration (PF0) Parameters” on page 754
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ACS Register Config-
uration (PF0) Parameters” on page 755
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Lightweight Notifica-
tion Configuration (PF0) Parameters” on page 758
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Readiness Configura-
tion (PF0) Parameters” on page 759
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Power Management
Register Configuration Parameters” on page 762
Synopsys, Inc.
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Register Configu-
ration Parameters” on page 764
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI Register Configu-
ration / PF0 PCI Register Defaults Parameters” on page 767
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / BAR Setup For Phys-
ical Function 0 (PF0) Parameters” on page 769
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / SR-IOV Register
Configuration PF0 Parameters” on page 789
■ “Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / Virtual Function BARs
for PF0 Parameters” on page 791
■ “Advanced RAM Config Parameters” on page 799
■ “Advanced PHY Config / General Options Parameters” on page 811
■ “Advanced PHY Config / PHY Timing Parameters” on page 814
■ “Advanced PHY Config / Gen3 PHY Equalization Config Parameters” on page 816
■ “Advanced PHY Config / Gen4 PHY Equalization Config Parameters” on page 821
■ “Advanced PHY Config / Gen5 PHY Equalization Config Parameters” on page 825
■ “Advanced PHY Config / PHY Lane Margining Config Parameters” on page 829
■ “Advanced PHY Config / PHY Message Bus Config Parameters” on page 832
■ “Advanced Transmit Config Parameters” on page 833
■ “Advanced Pipeline Config Parameters” on page 839
■ “Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters” on page 847
■ “Advanced Buffer Config / Segmented-Buffer Options Parameters” on page 850
■ “Advanced Buffer Config / Ordering Rules Configuration (Segmented-Buffer) Parameters” on page
851
■ “Advanced Buffer Config / Receive Serialization Queue Parameters” on page 852
■ “Advanced RX Queue Credit and Size Config / Cplq_Mng Calculator Parameters” on page 853
■ “Advanced RX Queue Credit and Size Config / VC 0 Parameters” on page 855
■ “Advanced RX Queue Credit and Size Config / VC 1 Parameters” on page 861
■ “Advanced RAS Config Parameters” on page 868
■ “Memory Map Parameters” on page 870
■ “Automotive Features Selection Parameters” on page 872
■ “CXS Configuration Parameters” on page 873
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PCI Express SW Controller Databook Main Features Config Parameters
Label Description
Core Type
Device Type Select the Device Type of the PCIe controller. You can choose among: EP : Endpoint
port, RC : Root complex port, DM : Dual Mode port (pin-selectable EP/RC port), and
SW : Switch port (pin-selectable upstream/downstream switch port). This selection
must be in line with your current license key.
Values:
■ EP (0)
■ RC (1)
■ DM (2)
■ SW (3)
■ NOT_SET (99)
Default Value: 99 (NOT_SET)
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CC_DEVICE_TYPE
PCIe EP Device Type Select the EP Device Type. You can choose between EP and EP_LEGACY.
Values:
■ PCIE_EP (0x0)
■ PCIE_EP_LEGACY (0x1)
Default Value: PCIE_EP
Enabled: CC_DEVICE_TYPE==CC_EP
Parameter Name: CX_EP_DEVICE_TYPE
PCIe Modes Supported You can configure the controller to support Conventional PCIe or M-PCIe. You can also
configure the controller to support both Conventional PCIe and M-PCIe modes by
choosing the Selectable PHY setting.
Values:
■ Single Conventional PCIe (0)
■ Single M-PCIe (1)
■ Selectable PHY (2)
Default Value: Single Conventional PCIe
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_PCIE_MODE
Synopsys, Inc.
Label Description
AXI Bridge
AMBA Enable Use the AXI bridge to interface to your application. For more details, see the
Databook. Additional configuration panes will become visible when you set the
AMBA_INTERFACE configuration parameter.
Values:
■ None (0)
■ Rsvd (1)
■ AXI3 (2)
■ AXI4 (3)
Default Value: None
Enabled: (!(CC_DEVICE_TYPE==CC_SW))
Parameter Type: Feature Setting
Parameter Name: AMBA_INTERFACE
Embedded DMA
DMA Enable Enable the embedded DMA controller. For more information, see the 'DMA' chapter of
the Databook. An additional configuration pane will become visible when you set the
CC_DMA_ENABLE configuration parameter.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (!(CC_DEVICE_TYPE==CC_SW))
Parameter Type: Feature Setting
Parameter Name: CC_DMA_ENABLE
Multifunction
Number of Functions Number of (physical) functions to support (in EP mode). There is a complete set of all
of the 'Function/BAR Configuration Parameters' parameters for each of the
CX_NFUNC functions. The additional configuration panes for each additional function
will become visible when you set the CX_NFUNC configuration parameter to a value
greater than 1. CX_ARI_ENABLE must be 1 when you have more than 8 functions.
Values: 1, ..., 32
Default Value: 1
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Feature Setting
Parameter Name: CX_NFUNC
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PCI Express SW Controller Databook Main Features Config Parameters
Label Description
Support ARI Alternate Routing ID (ARI) Capability enable. For more details, see the Databook.
Values:
■ false (0)
■ true (1)
Default Value: CX_SRIOV_ENABLE
Enabled: ((CC_DEVICE_TYPE==CC_EP || CC_DEVICE_TYPE==CC_DM) &&
!CX_SRIOV_ENABLE)
Parameter Type: Feature Setting
Parameter Name: CX_ARI_ENABLE
Individual Bus Number Per Determines if all functions use the same bus number (of function #0) or if they use the
Function individual bus numbers assigned to them by host software. Determines the size of the
cfg_pbus_num and cfg_pbus_dev_num buses: one set of bits for all functions or
separate bit-fields for each configured function. Not applicable when
CX_ARI_ENABLE=1.
■ True: Use individual bus numbers
■ False: Use same bus number
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW &&
CX_ARI_ENABLE!=1 && CX_NW<8
Parameter Type: Feature Setting
Parameter Name: MULTI_DEVICE_AND_BUS_PER_FUNC_EN
CCIX Features
Support CCIX Transport Protocol Configure the controller to support CCIX Transport Protocol.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_CCIX_ENABLE
Support ESM Mode Specifies if the PHY supports ESM (20.0 GT/s and 25 GT/s) Mode.
Values:
■ false (0)
■ true (1)
Default Value: CX_CCIX_ENABLE==1
Enabled: CX_CCIX_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CCIX_ESM_SUPPORT
Synopsys, Inc.
Label Description
Support CCIX TLP Interface Specifies if CCIX Interface and optimized TLP is supported.
Values:
■ false (0)
■ true (1)
Default Value: CX_CCIX_ENABLE==1
Enabled: CX_CCIX_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CCIX_INTERFACE_ENABLE
Support CXS Interface Configure the controller to support CXS Interface. The controller does not support
CXS Interface for switch device.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_CCIX_INTERFACE_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_ENABLE
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PCI Express SW Controller Databook Basic Features Config / PCIe Basic Features Config Parameters
Label Description
Phy Type
Phy Selection Select the type of PHY you are using. PHYs are instantiated outside the core,
interfacing through the standard PIPE I/F. You must select the "Custom PHY" option
and follow the configuration guidelines presented in the section "Integrating the
controller with the PHY" in the User Guide.
A PHY simulation-only model is also supplied by Synopsys. This block cannot be
implemented and it is provided for simulation purposes only. You might temporarily use
this for simulation purposes until you receive a simulation model from your PHY
vendor. Note that different PHY models may have different configuration requirements.
Please review your configuration settings when switching between the example PHY
and the PHY model provided by your PHY vendor.
Values:
■ Example PIPE PHY (8)
■ Custom PHY (7)
Default Value: Example PIPE PHY
Enabled: (!(CX_PCIE_MODE == SINGLE_MPCIE))
Parameter Type: Feature Setting
Parameter Name: PHY_TYPE
Max PCIe Speed Maximum supported link speed that the controller supports.
Values:
■ Gen1 (2.5GT/s) (1)
■ Gen2 (5.0GT/s) (2)
■ Gen3 (8.0GT/s) (3)
■ Gen4 (16.0GT/s) (4)
■ Gen5 (32.0GT/s) (5)
Default Value: Gen1 (2.5GT/s)
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_MAX_PCIE_SPEED
Core-Phy Combination Read Only parameter to indicate PHY-MAC combination is supported or not
Values:
■ Not Supported (0)
■ Supported (1)
Default Value: function_of (CX_MAX_PCIE_SPEED CX_MAC_SMODE_GEN1
CX_MAC_SMODE_GEN2 CX_MAC_SMODE_GEN3 CX_MAC_SMODE_GEN4
CX_MAC_SMODE_GEN5 CX_PHY_SMODE_GEN1 CX_PHY_SMODE_GEN2
CX_PHY_SMODE_GEN3 CX_PHY_SMODE_GEN4 CX_PHY_SMODE_GEN5)
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_MAC_PHY_FREQ_VALID
Synopsys, Inc.
Label Description
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Label Description
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Label Description
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Label Description
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Label Description
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PCI Express SW Controller Databook Basic Features Config / PCIe Basic Features Config Parameters
Label Description
Maximum Link Width Maximum number of lanes that the controller supports. For full details of what
combinations of modes, frequencies and link widths are supported for each core, see
Table 1-1 in the "Frequency, Speed, and Width Support" section in the Product
Overview chapter of the Databook. This parameter becomes a read-only parameter
and takes the same value as the maximum of {CM_TXNL, CM_RXNL} if Single
M-PCIe or Selectable PHY modes are enabled.
Values:
■ x1 (1)
■ x2 (2)
■ x4 (4)
■ x8 (8)
■ x16 (16)
Default Value: (CX_S_CPCIE_MODE) ? 4 : (CM_TXNL_GUI > CM_RXNL_GUI) ?
CM_TXNL_GUI : CM_RXNL_GUI
Enabled: ((CX_PCIE_MODE == SINGLE_CPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_NL
Phy Rx multi-bit startblock Enables PIPE Rx multi-bit startblock Mode for 8s/16s.
When disabled and PIPE width is 8s/16s, the Controller only accepts 64-bit-aligned
SKP-OS in Gen3/4/5 speed.
When enabled and PIPE width is 8s/16s, the Controller can accept 32-bit-aligned
SKP-OS in Gen3/4/5 Speed. Possible SKP-OS length is 32/64/96/128/160/192/224-bit
considering two retimers on the link.
Values:
■ Disabled (0)
■ Enabled (1)
Default Value: (((CX_PHY_FREQ == FREQ_125) && (CX_PHY_GEN2_MODE ==
GEN2_DF) && (CX_PHY_GEN3_MODE == GEN3_DW) && (CX_PHY_GEN4_MODE
== GEN4_DW) && (CX_PHY_INTERFACE == V7_INTERFACE)) ? 1 : 0==1) ? 1 : 0
Enabled: (CX_MAX_PCIE_SPEED>=3 && (CX_PHY_SMODE_GEN3>=8 ||
CX_PHY_SMODE_GEN4>=8 || CX_PHY_SMODE_GEN5>=8))
Parameter Type: Feature Setting
Parameter Name: CX_PIPERX_MULTI_BLOCK
Synopsys, Inc.
Label Description
Freq Step (b/w PHY and Core) If this automatically-derived parameter is defined, then a module called freq_step
(workspace/src/common/freq_step.v) is placed in between the PIPE I/O and the core's
internal pip interface. This module steps up/down the signals to/from the pipe
interface. For example, the controller can run at 62.5 MHz (4 symbols per clock) and
the pipe can run at 250 MHz (1 symbol per clock). This read-only parameter is derived
automatically. For more details, see 'Frequency, Speed and Width Support' in the
Product Overview chapter of Databook.
Values:
■ No (0)
■ Yes (1)
Default Value: (CX_MAC_SMODE_GEN1 != CX_PHY_SMODE_GEN1) ||
(CX_MAC_SMODE_GEN2 != CX_PHY_SMODE_GEN2) ||
(CX_MAC_SMODE_GEN3 != CX_PHY_SMODE_GEN3) ||
(CX_MAC_SMODE_GEN4 != CX_PHY_SMODE_GEN4) ||
(CX_MAC_SMODE_GEN5 != CX_PHY_SMODE_GEN5) ||
(CX_PIPERX_MULTI_BLOCK==1)
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_FREQ_STEP_EN
Freq Step (b/w PL and DL) Specifies if the controller supports for frequency step module between the Physical
Layer and the DataLink Layer.
Values:
■ No (0)
■ Yes(1:1) (1)
■ Yes(1:2) (2)
■ Yes(1:4) (4)
Default Value: No
Enabled: SNPS_RSVDPARAM_15
Parameter Name: CX_FREQ_STEP_DL
Datapath Width (PL) Specifies the width of the datapath in dwords. Displayed in bits. This read-only
parameter is derived automatically as CX_NL * CX_NB , rounded up to 1, 2, 4, or 8.
For more details, see the "Frequency, Speed, and Width Support" section in the
Product Overview chapter of the Databook. For the definition of CX_NB, see the
description of "Core PIPE Lane Width" (CX_PIPE_WIDTH_).
Values:
■ 32-bit (1)
■ 64-bit (2)
■ 128-bit (4)
■ 256-bit (8)
■ 512-bit (16)
Default Value: [calc_get_datapath CX_NB CX_NL]
Enabled: Always
Parameter Name: CX_PL_NW
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PCI Express SW Controller Databook Basic Features Config / PCIe Basic Features Config Parameters
Label Description
Datapath Width (DL/TL/ADM) Specifies the width of the datapath in dwords. Displayed in bits. This read-only
parameter is derived automatically as CX_NL * CX_DL_NB , rounded up to 1, 2, 4, or
8. For more details, see the "Frequency, Speed, and Width Support" section in the
Product Overview chapter of the Databook. For the definition of CX_NB, see the
description of "Core PIPE Lane Width" (CX_PIPE_WIDTH_).
Values:
■ 32-bit (1)
■ 64-bit (2)
■ 128-bit (4)
■ 256-bit (8)
■ 512-bit (16)
Default Value: [calc_get_datapath CX_DL_NB CX_NL]
Enabled: Always
Parameter Name: CX_NW
PIPE Spec
■ PIPE 4.4.1
❑ Use mac_phy_powerdown signal for L1 substate/L1.CPM transition
❑ Use Message Bus Interface for Lane Margining for Gen4 data rate
■ PIPE 5.1.1
❑ Use mac_phy_powerdown signal for L1 substate/L1.CPM transition
Contact your PHY vendor for guidelines on PIPE Spec Version. Refer to the User
Guidefor guidelines on how to configure this parameter for Synopsys PHYs.
Values:
■ PIPE4.2 and below (0)
■ PIPE4.3 (1)
■ PIPE4.4.1 (2)
■ PIPE5.1.1 (3)
Default Value: (CX_GEN5_SPEED || CX_CCIX_ESM_SUPPORT) ? 2 :
[<functionof>]
Enabled: CX_S_CPCIE_MODE || CX_SEL_PHY_MODE
Parameter Type: Feature Setting
Parameter Name: CX_PIPE_VER
Synopsys, Inc.
Label Description
Physical Layer features Enables the following PCIe Base Spec 4.0 features.
■ EIEOS Format change
■ LTSSM change for Retimer
■ Fault isolation
■ SKP OS format change
■ Compliance Pattern Update
■ Physical Layer 16GT/s Capability register
Values: 0, 1
Default Value: CX_GEN4_MODE != GEN4_DISABLED
Enabled: 0
Parameter Name: CX_GEN4_SPEC07
Max number of Retimer Specifies maximum number of Retimers that can be present in your system. This
setting impacts default buffer size of Retry, SOT buffer and Receive queue.
Values: 0x0, 0x1, 0x2
Default Value: ((CX_GEN4_MODE != GEN4_DISABLED)==1) ? 2 : 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_MAX_RETIMER
Total Retimer Latency (Symbol Specifies total round trip Latency of Retimer. The default value is calculated from
times) CX_MAX_RETIMER setting and reference Retimer latency table in PCIe Base Spec.
This setting impacts retry buffer auto-sizing and default credits of Receive queue. If
you know Latency value of Retimer in your system, you should adjust the value.
Otherwise, use the default setting.
Values: 0, ..., 2048
Default Value: [<functionof> CX_MAX_RETIMER CX_SRIS_SUPPORT
CX_MAX_MTU CX_GEN5_SPEED CX_GEN4_SPEED CX_GEN3_SPEED
CX_GEN2_SPEED]
Enabled: Always
Parameter Name: CX_RETIMER_LATENCY
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PCI Express SW Controller Databook Basic Features Config / PCIe Basic Features Config Parameters
Label Description
Data Link Feature Enabled The Data Link Feature Capability is an optional Extended Capability that is required for
Downstream Ports that support 16.0 GTs. It is optional in other Downstream Ports. It is
optional in Functions associated with an Upstream Port. It is not applicable in
Functions that are not associated with a Port (e.g. Root Complex Integrated Endpoints,
Root Complex Event Collectors). Ports that implement this protocol contain the Data
Link Feature Extended Capability as described in Section 7.37 of the PCIe
Specification 4.0.
Values:
■ false (0)
■ true (1)
Default Value: CX_GEN4_SPEED || FC_SCALE_EN
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: DL_FEATURE_EN
Scaled Flow Control Enabled Link performance can be affected when there are insufficient flow control credits
available to account for the Link round trip time. This effect becomes more noticeable
at higher Link speeds and the limitation of 127 header credits and 2047 data credits
can limit performance. The Scaled Flow Control mechanism is designed to address
this limitation. Scaled Flow control is described in Section 3.4.2 of the PCIe
Specification 4.0.
Values:
■ false (0)
■ true (1)
Default Value: CX_GEN4_MODE != GEN4_DISABLED
Enabled: (!(CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Feature Setting
Parameter Name: FC_SCALE_EN
10-Bit Tag Configure the controller to support the extended tag range using a 10-bit tag field.
Values: 0, 1
Default Value: (((CX_GEN4_SPEED_VALUE == 1) || (CX_MAX_TAG > 255) ||
(CX_REMOTE_MAX_TAG > 255)) && (AMBA_INTERFACE != 1))? 1: 0
Enabled: AMBA_INTERFACE != 1 && CX_GEN4_SPEED_VALUE == 0
Parameter Type: Feature Setting
Parameter Name: CX_10BITS_TAG
Support Equalization bypass to When enabled, the controller supports Equalization bypass to highest rate.
highest rate Values: 0x0, 0x1
Default Value: CX_MAX_PCIE_SPEED >= 5
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Feature Setting
Parameter Name: CX_SKIP_LOWER_RATE_EQ
Synopsys, Inc.
Label Description
Support No Equalization Needed When enabled, the controller supports No Equalization Needed. Contact your PHY
vendor for the value that you should use.
Values: 0x0, 0x1
Default Value: 0x0
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Feature Setting
Parameter Name: CX_NO_EQ_NEEDED
Request Transmitter Precode When enabled, the controller will request the remote transmitter to use Precoding by
setting the Precoding Request bit in the EQ TS it transmits prior to entry to
Recovery.Speed.
Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_MAX_PCIE_SPEED >= 5
Enabled: CX_MAX_PCIE_SPEED >= 5
Parameter Type: Register Default Setting
Parameter Name: CX_DEFAULT_TX_PRECODE_REQ
Default Value for Gen5 Loopback Default value for Loopback to do Equalization at Gen5 rate.
EQ Values: 0x0, 0x1
Default Value: CX_MAX_PCIE_SPEED >= 5
Enabled: CX_MAX_PCIE_SPEED >= 5
Parameter Type: Feature Setting
Parameter Name: CX_DEFAULT_GEN5_EQ_FOR_LOOPBACK
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PCI Express SW Controller Databook Basic Features Config / Common Basic Features Config Parameters
Label Description
PCIe Max Payload Supported The largest packet payload (Maximum Transfer Unit) that the device will support.
Specified in bytes and not dwords. This is distinct from the maximum operating
payload (Max_Payload_Size) which may be set by software. This value is used to set
memory sizes and places other restrictions on the size of structures. The device will
support any valid payload size equal to or smaller than the value specified here.
Values: 128, 256, 512, 1024, 2048, 4096
Default Value: 256
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_MAX_MTU
Synopsys, Inc.
Label Description
Max Outbound NP Requests Specifies the maximum number of simultaneous outbound PCIe non-posted requests
in total for all functions. The default value is sufficient for typical endpoint applications.
This is used to size:
■ the Receive 'Completion Timeout Look-Up Table'
■ the completion Header Queue RAM when you configure completions in
store-and-forward or cut-through modes
The controller can always accept 8-bit tags (IDs 0 to 255) from the PCIe wire or your
application, regardless of the value of this parameter.
Note:The value range in the GUI is displayed as CX_MAX_TAG+1. The actual
parameter value in the RTL represents the maximum tag number because the tags are
numbered 0 to CX_MAX_TAG
Values:
■ 2 (1)
■ 4 (3)
■ 8 (7)
■ 16 (15)
■ 32 (31)
■ 64 (63)
■ 128 (127)
■ 256 (255)
■ 512 (511)
■ 768 (767)
Default Value: RECOMMENDED_TAGS
Enabled: ((CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Performance Setting
Parameter Name: CX_MAX_TAG
Address Translation
Internal Address Translation Unit Enables the instantiation of the internal address translation unit (iATU). Refer to
'Internal Address Translation (iATU)' section of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_INTERNAL_ATU_ENABLE
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PCI Express SW Controller Databook Basic Features Config / Common Basic Features Config Parameters
Label Description
Number of Outbound Address Specifies the number of address regions to be mapped by the internal Address
Translation Regions Translation Unit in the outbound direction. Refer to 'Internal Address Translation (iATU)'
section of the Databook.
Values: 0, ..., 256
Default Value: 2
Enabled: CX_INTERNAL_ATU_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ATU_NUM_OUTBOUND_REGIONS
Number of Inbound Address Specifies the number of address regions to be mapped by the internal Address
Translation Regions Translation Unit in the inbound direction. Refer to 'Internal Address Translation (iATU)'
section of the Databook.
Values: 0, ..., 256
Default Value: 2
Enabled: CX_INTERNAL_ATU_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ATU_NUM_INBOUND_REGIONS
Minimum size of an Address Specifies the minimum size of an address translation region. For example, if set to 64
Translation Region kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address
regions are aligned on 64 kB boundaries. Smaller Regions require more levels of
decode logic. Refer to 'Internal Address Translation (iATU)' section of the Databook.
Values:
■ 4k (4096)
■ 8k (8192)
■ 16k (16384)
■ 32k (32768)
■ 64k (65536)
Default Value: 64k
Enabled: CX_INTERNAL_ATU_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ATU_MIN_REGION_SIZE
Synopsys, Inc.
Label Description
Maximum size of an Address Specifies the maximum allowable size of an Address Translation Region in iATU for
Translation Region both inbound and outbound TLPs. This parameter determines the number of
programmable bits in the iATU Upper Limit Address Register for both inbound and
outbound. For more information, refer to 'Internal Address Translation (iATU)' section
of the Databook.
Values:
■ 4G (0)
■ 8G (1)
■ 16G (2)
■ 32G (3)
■ 64G (4)
■ 128GB (5)
■ 256GB (6)
■ 512GB (7)
■ 1TB (8)
■ 2TB (9)
■ 4TB (10)
■ 8TB (11)
■ 16TB (12)
■ 32TB (13)
■ 64TB (14)
■ 128TB (15)
■ 256TB (16)
■ 512TB (17)
■ 1PB (18)
■ 2PB (19)
■ 4PB (20)
■ 8PB (21)
■ 16PB (22)
■ 32PB (23)
■ 64PB (24)
■ 128PB (25)
■ 256PB (26)
■ 512PB (27)
■ 1EB (28)
■ 2EB (29)
■ 4EB (30)
■ 8EB (31)
■ 16EB (32)
Default Value: 4G
Enabled: CX_INTERNAL_ATU_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ATU_MAX_REGION_SIZE
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PCI Express SW Controller Databook Basic Features Config / Common Basic Features Config Parameters
Label Description
Receive Posted Queue Mode The queue mode for the posted TLP receive queue for VC0.
(VC0) ■ Bypass: There is no receive queue in this mode, your application must be able to
accept all traffic as back-pressure is disabled in the mode.
■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
■ Cut-through: TLPs are stored into queue and presented to your application at the
same time it is being stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
■ Cut Thru (0x2)
■ Bypass (0x4)
Default Value: Store/Fwd
Enabled: (!(CX_NW>=8 && CX_RADMQ_MODE!=2))
Parameter Type: Feature Setting
Parameter Name: RADM_P_QMODE_VC0
Receive Non-Posted Queue The queue mode for the non-posted TLP receive queue for VC0.
Mode (VC0) ■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
Default Value: CX_RADMQ_MODE==0 ? RADM_P_QMODE_VC0 : 1
Enabled: (CX_RADMQ_MODE!=0 && !(CX_NW>=8 && CX_RADMQ_MODE!=2))
Parameter Type: Feature Setting
Parameter Name: RADM_NP_QMODE_VC0
Synopsys, Inc.
Label Description
Receive Completions Queue The queue mode for the completion tlp receive queue for VC0.
Mode (VC0) ■ Bypass: There is no receive queue in this mode, your application must be able to
accept all traffic as back-pressure is disabled in the mode.
■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
■ Cut-through: TLPs are stored into queue and presented to your application at the
same time it is being stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
■ Cut Thru (0x2)
■ Bypass (0x4)
Default Value: (CC_DEVICE_TYPE==CC_SW || CX_NW>=8) ? 1 : 4
Enabled: (!(CX_NW>=8 && CX_RADMQ_MODE!=2))
Parameter Type: Feature Setting
Parameter Name: RADM_CPL_QMODE_VC0
Completion Queue Management Enable the NP throttle that halts the client interface if there is not enough space for the
Feature CPL in the RADM_CPLQ.
Values: 0, 1
Default Value: (CC_DEVICE_TYPE!=CC_SW) && !(CX_P2P_ENABLE) &&
TRGT1_POPULATE && (RADM_CPL_QMODE_VC0<4)
Enabled: ((CC_DEVICE_TYPE!=CC_SW) && TRGT1_POPULATE &&
(RADM_CPL_QMODE_VC0<4))
Parameter Type: Feature Setting
Parameter Name: CX_CPLQ_MANAGEMENT_ENABLE
Technology
FPGA Select this option if you are implementing the controller in an FPGA. This will add the
required pipelining (and corresponding logic to control pipelined logic) to enable the
synthesis tool to meet FPGA timing. For more details, see the 'Synthesizing the Core
for an FPGA' section of the User Guidefor details on FPGA implementation.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: DWC_PCIE_FPGA
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PCI Express SW Controller Databook Basic Features Config / Common Basic Features Config Parameters
Label Description
Use External RAMs Determines if RAMs are instantiated internally, or RAM top-level interface is added for
connection of external RAM modules. External RAM might be preferable if you are
doing RAM layout separately. For more details, see the 'RAM Requirements' section in
the Architecture chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: DWC_PCIE_FPGA ? 0 :1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RAM_AT_TOP_IF
RAM Type Selects the type of RAM when internal RAM is used.
■ Simple: Customer-supplied simple synchronous RAM.
■ DesignWare: Synopsys DesignWare Library Synthesizable flip-flop based SRAM
for sizes up to 256 X 256.
■ FPGA RAM: FPGA RAM resources.
For details on RAM locations and how to integrate the RAM modules, see the 'RAM
Requirements' section in the Architecture chapter of the Databook.
■ Only applicable when CX_RAM_AT_TOP_IF is 0 (Internal)
■ Forced to FPGA RAM when FPGA is 1
Values:
■ Simple (0)
■ DesignWare (1)
■ FPGA RAM (2)
Default Value: DWC_PCIE_FPGA ? 2 : 0
Enabled: !DWC_PCIE_FPGA && !CX_RAM_AT_TOP_IF
Parameter Type: Feature Setting
Parameter Name: CX_RAM_TYPE
Individual Pipeline Control Enable independent control of inter-module pipelines to trade-off latency and gates for
ease of timing closure. Additional configuration panes will become visible when you
set this parameter.
Values:
■ Disable (0)
■ Enable (1)
Default Value: Disable
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_CUSTOM_PIPELINING
Synopsys, Inc.
Label Description
Technology Speed The speed of the target technology relative to the clock frequency and architecture.
Possible values are SLOW or FAST. When you have selected "Individual Pipeline
Control" (CX_CUSTOM_PIPELINING set to "1"), then this parameter sets the default
for many of the individual inter-module pipeline enabling parameters to "1" when
CX_TECHNOLOGY is SLOW. This parameter is forced to SLOW when you are using
an FPGA (DWC_PCIE_FPGA parameter set to "1"). An ASIC technology might be
FAST if running at 125 MHz, but the SLOW setting might be needed to meet timing at
250 MHz in an x8/x16 architecture.
Values:
■ SLOW (0x0)
■ FAST (0x2)
Default Value: DWC_PCIE_FPGA ? 0 : 2
Enabled: !DWC_PCIE_FPGA || (CX_CUSTOM_PIPELINING==0)
Parameter Type: Performance Setting
Parameter Name: CX_TECHNOLOGY
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PCI Express SW Controller Databook DMA Configuration Parameters
Label Description
Basic Features
Number of DMA Write Channels Number of write channels implemented in the DMA logic. A DMA write copies data
from your local application to the remote link partner. For more information, see the
'DMA' chapter of the Databook.
Values: 1, 2, 3, 4, 5, 6, 7, 8
Default Value: 2
Enabled: CC_DMA_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_NUM_DMA_WR_CHAN
Number of DMA Read Channels Number of read channels implemented in the DMA logic. A DMA read copies data
from the remote link partner to your local application. For more information, see the
'DMA' chapter of the Databook.
Values: 1, 2, 3, 4, 5, 6, 7, 8
Default Value: 2
Enabled: CC_DMA_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_NUM_DMA_RD_CHAN
Advanced Features
Number of DMA Read PCIe Tags Specifies how many of the CX_MAX_TAG+1 PCIe tags are reserved for DMA MRd
generation.
■ CC_NUM_DMA_RD_TAG of the CX_MAX_TAG+1 tags are reserved for use by
the DMA controller (and are no longer available to your application) for generation
of non-posted DMA traffic. These are in the number range CX_MAX_TAG +1
-CC_NUM_DMA_RD_TAG to CX_MAX_TAG.
■ The remaining CX_MAX_TAG +1 - CC_NUM_DMA_RD_TAG tags are assigned to
non-DMA transfers. These are in the number range 0 to CX_MAX_TAG
-CC_NUM_DMA_RD_TAG.
This parameter is also used to size the DMA Read buffer. The minimum value for
CX_MAX_TAG is "3" when DMA is enabled.
Values: 2, 4, 8, 16, 32, 64, 128
Default Value: (CX_MAX_TAG==3) ? 2 : (CX_MAX_TAG==7) ? 4 :
(CX_MAX_TAG==15) ? 8 : (CX_MAX_TAG==31) ? 16 : (CX_MAX_TAG==63) ? 32 :
(CX_MAX_TAG==127) ? 64 : (CX_MAX_TAG>=255) ? 128 : 2
Enabled: CC_DMA_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_NUM_DMA_RD_TAG
Synopsys, Inc.
Label Description
DMA Handshake Enable Enable DMA Handshake feature. The Handshake feature is available for each DMA
Write/Read channel. For more information, see the 'DMA' chapter of the Databook
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DMA_ENABLE
Parameter Name: CC_DMA_HSHAKE
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PCI Express SW Controller Databook Basic AXI Config Parameters
Label Description
Support Slave Wrap Bursts Enable support of wrapping bursts at the AXI bridge slave. For more details, see the
"Supported AXI Burst Operations" section in the "AXI Bridge Module" chapter of the
Databook.
Values: 0, 1
Default Value: 0
Enabled: AMBA_INTERFACE>=2
Parameter Type: Feature Setting
Parameter Name: CC_SLV_WRAP_ENABLE
Max Number of Outstanding AXI Specifies the maximum number of outstanding AXI Slave NP Write Requests.
Slave NP Write Requests To enable P writes to pass NP writes (and avoid deadlocks by allowing peer-to-peer
posted traffic to flow freely through the RC); the controller uses a "Slave Non-Posted
Write Set-Aside Buffer" to offload the NP writes from the AXI Write Channel when NP
reads are stalled. Offloading NP writes thereby avoids blocking of P on the AXI Write
Channel. You configure the maximum number of offloaded NP writes using this
parameter.
Values: 2, 4, 8, 16, 32, 64
Default Value: 32
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Feature Setting
Parameter Name: CC_SLV_NUM_OUTSTND_CPU_WR_REQ
Master Address Width Specifies the width of the AXI master address bus (excluding parity bits [AXI only] if
any)
Values:
■ 32 (32)
■ 64 (64)
Default Value: CC_DTIM_ENABLE ? 64 : (AHB_POPULATED ?
SLAVE_BUS_ADDR_WIDTH : 32)
Enabled: (MASTER_POPULATED && (AXI_POPULATED || AHB_POPULATED))
Parameter Type: Feature Setting
Parameter Name: MASTER_BUS_ADDR_WIDTH
Master Data Width Specifies the width of the AXI master databus (excluding parity bits [AXI only] if any)
Values: 32, 64, 128, 256, 512
Default Value: AHB_POPULATED ? SLAVE_BUS_DATA_WIDTH :
PCIE_CORE_DATA_BUS_WD
Enabled: MASTER_POPULATED
Parameter Type: Feature Setting
Parameter Name: MASTER_BUS_DATA_WIDTH
Synopsys, Inc.
Label Description
Slave Address Width Specifies the width of the AXI slave address bus (excluding parity bits [AXI only] if any)
Values:
■ 32 (32)
■ 64 (64)
Default Value: CC_DTIM_ENABLE ? 64 : 32
Enabled: (SLAVE_POPULATED && (AXI_POPULATED || AHB_POPULATED))
Parameter Type: Feature Setting
Parameter Name: SLAVE_BUS_ADDR_WIDTH
Slave Data Width Specifies the width of the AXI slave data bus (excluding parity bits [AXI only] if any).
Values: 32, 64, 128, 256, 512
Default Value: CX_NW * 32
Enabled: SLAVE_POPULATED
Parameter Type: Feature Setting
Parameter Name: SLAVE_BUS_DATA_WIDTH
Integrated MSI Reception Module Instantiate the iMSI-RX: Integrated MSI Receiver in the AXI bridge to detect and
Enable terminate inbound MSI TLPs. For more details, see the Interrupt section in the
"Controller Operations" chapter of the Databook.
Values: 0, 1
Default Value: 0
Enabled: ((CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_DM) &&
AMBA_INTERFACE!=0)
Parameter Type: Feature Setting
Parameter Name: CX_MSI_CTRL_ENABLE
AXI MSI Controller FIFO Depth AXI MSI interrupt controller FIFO depth. Number of maximum interrupt vectors AXI
MSI controller can hold before halting the target interface.
Values: 2, 3, 4, 5
Default Value: 2
Enabled: ((CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_DM) &&
CX_MSI_CTRL_EN)
Parameter Type: Feature Setting
Parameter Name: CX_MSI_CTRL_FIFO_DEPTH
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PCI Express SW Controller Databook Basic AXI Config Parameters
Label Description
AXI Clocking
Asynchronous AHB Clock Include asynchronous clock crossing circuitry in AHB bridge. The AHB bridge
assumes that hclk is asynchronous to core_clk and it implements the appropriate clock
crossings using pre-existing FIFOs and inserting extra FIFOs when necessary.
■ When your AHB clock is synchronous to core_clk then you can eliminate all unnec-
essary clock crossing circuitry by unsetting this parameter.
■ When you are using a dynamic frequency controller (Gen/Gear 2/3), the frequency
of core_clk changes across speed modes. In this case, your AHB clock cannot be
synchronous to core_clk and you cannot set AHB_CLK_DIFF_ENABLE to "0".
■ In addition, M-PCIe mode doesn't support synchronous core_clk and bridge clock
frequencies because the M-PCIe core_clk frequency regularly changes between
rate A and B frequencies.
Values: 0, 1
Default Value: AMBA_INTERFACE==1
Enabled: AMBA_INTERFACE==1
Parameter Type: Feature Setting
Parameter Name: AHB_CLK_DIFF_ENABLE
Asynchronous AXI Slave Clock Include slave asynchronous clock crossing circuitry in AXI bridge. The AXI bridge
assumes that slv_aclk and dbislv_aclk are asynchronous to core_clk and it
implements the appropriate clock crossings using pre-existing FIFOs and inserting
extra FIFOs when necessary.
■ When your AXI clocks are synchronous to core_clk then you can eliminate all
unnecessary clock crossing circuitry by unsetting the SLV_CLK_DIFF_ENABLE
configuration parameter.
■ When you are using a dynamic frequency Gen/Gear 2/3 core, the frequency of
core_clk changes across speed modes. In this case, your AXI clock cannot be
synchronous to core_clk and you cannot set SLV_CLK_DIFF_ENABLE to "0".
■ In addition, M-PCIe mode doesn't support synchronous core_clk and bridge clock
frequencies because the M-PCIe core_clk frequency regularly changes between
rate A and B frequencies.
Values: 0, 1
Default Value: (AXI_POPULATED && SLAVE_POPULATED) ||
AHB_CLK_DIFF_ENABLE
Enabled: AXI_POPULATED && SLAVE_POPULATED
Parameter Type: Feature Setting
Parameter Name: SLV_CLK_DIFF_ENABLE
Synopsys, Inc.
Label Description
Asynchronous AXI Master Clock Include master asynchronous clock crossing circuitry in AXI bridge. The AXI bridge
assumes that mstr_aclk is asynchronous to core_clk and it implements the appropriate
clock crossings using pre-existing FIFOs and inserting extra FIFOs when necessary.
■ When your AXI clock is synchronous to core_clk then you can eliminate all unnec-
essary clock crossing circuitry by unsetting the MSTR_CLK_DIFF_ENABLE config-
uration parameter.
■ When you are using a dynamic frequency Gen/Gear 2/3 core, the frequency of
core_clk changes across speed modes. In this case, your AXI clock cannot be
synchronous to core_clk and you cannot set MSTR_CLK_DIFF_ENABLE to "0".
■ In addition, M-PCIe mode doesn't support synchronous core_clk and bridge clock
frequencies because the M-PCIe core_clk frequency regularly changes between
rate A and B frequencies.
Values: 0, 1
Default Value: (AXI_POPULATED && MASTER_POPULATED) ||
AHB_CLK_DIFF_ENABLE
Enabled: AXI_POPULATED && MASTER_POPULATED
Parameter Type: Feature Setting
Parameter Name: MSTR_CLK_DIFF_ENABLE
Slave Interface Burst Length Specifies the maximum burst length (in beats) of an AXI transfer at the slave interface.
An application master may execute any burst up to a maximum byte size given by
CC_SLV_BURST_LEN * (CC_SLV_BUS_DATA_WIDTH / 8) bytes. This parameter
controls the default size of the slave request decomposer Data RAM inside the AXI
bridge based on the maximum MemWr transfer size. This parameter uses the unit of
burst beat.
Values: 8, 16, 32, 64, 128, 256
Default Value: (AHB_POPULATED && (SLAVE_BUS_DATA_WIDTH==32))? 32 : 16
Enabled: SLAVE_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_SLV_BURST_LEN
AHB/AXI Slave MTU Slave Maximum Transfer Unit. The application master (at the AXI Slave Interface) must
not request or write more than CC_SLV_MTU bytes in a single AXI burst. This value is
used to set memory sizes in the bridge (slave request decomposer data FIFO and
slave response composer). This parameter is derived automatically as
CC_SLV_BURST_LEN * (SLAVE_BUS_DATA_WIDTH / 8) and is read-only.
Values: -2147483648, ..., 2147483647
Default Value: ((CC_SLV_BURST_LEN*SLAVE_BUS_DATA_WIDTH/8) > 4096) ?
4096 : (CC_SLV_BURST_LEN*SLAVE_BUS_DATA_WIDTH/8)
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CC_SLV_MTU
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PCI Express SW Controller Databook Basic AXI Config Parameters
Label Description
Master Interface Burst Length Specifies the maximum burst length (in beats) of an AXI transfer at the master
interface.
■ A value < MASTER_BUS_DATA_WIDTH/8 forces MSTR_FIXED_SIZE_EN-
ABLE=1 because the master cannot produce a sufficiently long burst of bytes.
Therefore the master uses dword access and not byte access for narrow or NCBE
reads; which means that such accesses to non-prefetchable memory might result
in corrupting not-to-be-read data.
■ A value of 8 also forces MSTR_FIXED_SIZE_ENABLE=1.
AXI Note:The value of 8 is only possible if MASTER_BUS_DATA_WIDTH > 32
because the minimum allowable master burst transfer size (CC_MSTR_MTU) is 64
bytes.
Values: 8, 16, 32, 64, 128, 256
Default Value: 16
Enabled: (MASTER_POPULATED && !(AHB_POPULATED &&
(CC_MSTR_BURST_TYPE == 0)))
Parameter Type: Performance Setting
Parameter Name: CC_MSTR_BURST_LEN
AHB/AXI Master MTU Master Maximum Transfer Unit. The bridge master will not request or write more than
CC_MSTR_MTU bytes in a single AXI burst. This parameter is derived automatically
as max. {64, CC_MSTR_BURST_LEN * (MASTER_BUS_DATA_WIDTH / 8) } and is
read-only.
Values: 64, ..., 4096
Default Value: ((CC_MSTR_BURST_LEN*MASTER_BUS_DATA_WIDTH/8) >= 64) ?
(CC_MSTR_BURST_LEN*MASTER_BUS_DATA_WIDTH/8) : 64
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CC_MSTR_MTU
Master Page Boundary Bit Specifies an address page boundary of 128, 256, 512, 1K, 2K or 4K (bytes).
■ The AXI bridge ensures that the inbound request will not cross the selected page
boundary when driven onto the AXI master interface.
■ The Master Page Boundary (CC_MSTR_PAGE_BOUNDARY_BYTES) is calcu-
lated as 2 ^ (CC_MSTR_PAGE_BOUNDARY_PW-1).
■ For more details, see "Decomposition" in the Databook.
Note:The Master Page Boundary { 2 ^ (CC_MSTR_PAGE_BOUNDARY_PW-1) } must
be >= max{ CC_MSTR_MTU , CC_MSTR_RD_REQ_SIZE}
Values: 8, ..., 13
Default Value: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3)) ? 13 : 11
Enabled: MASTER_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_MSTR_PAGE_BOUNDARY_PW
Synopsys, Inc.
Label Description
Master Page Boundary For more details, see description of Master Page Boundary Bit
(CC_MSTR_PAGE_BOUNDARY_PW).
Note:This parameter is derived automatically as 2 ^
(CC_MSTR_PAGE_BOUNDARY_PW-1) and is read-only.
Values: -2147483648, ..., 2147483647
Default Value: [calc_inv_log2 [<functionof> CC_MSTR_PAGE_BOUNDARY_PW -1]]
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CC_MSTR_PAGE_BOUNDARY_BYTES
PCIe Max Payload Supported This parameter is a read-only reflection of the CX_MAX_MTU parameter.
Values: 0, ..., 65535
Default Value: CX_MAX_MTU
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_MAX_MTU_
AXI DBI
Dedicated DBI Slave Enable Enables the AXI Slave DBI interface. For more details, see the "Local Bus Controller
(LBC)" section of the Databook.
Values: 0, 1
Default Value: AMBA_POPULATED && !SHARED_DBI_ENABLED
Enabled: AMBA_POPULATED && !SHARED_DBI_ENABLED
Parameter Type: Feature Setting
Parameter Name: DBI_4SLAVE_POPULATED
Shared DBI Slave Enable Indicates that the slave interface for PCIe outbound traffic is also used for DBI access.
For more details, see the "Local Bus Controller (LBC)" section in the "Controller
Operations" chapter of the Databook. >Note:Valid for AXI only but cannot be enabled
in EP/DM when (CX_ARI_ENABLE=1 or CX_SRIOV_ENABLE=1)
Values: 0, 1
Default Value: 0
Enabled: (AXI_POPULATED && (!CX_AMBA_ARI_OR_IOV ||
SLAVE_BUS_ADDR_WIDTH_IS_64))
Parameter Type: Feature Setting
Parameter Name: SHARED_DBI_ENABLED
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Label Description
DBI Slave Address Width Specifies the width of the dedicated DBI slave address bus. This is a read-only
parameter.
Values:
■ 32 (32)
■ 33 (33)
Default Value: CX_ARI_ENABLE ? 33 : 32
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CC_DBI_SLV_BUS_ADDR_WIDTH
DBI Slave Data Width Specifies the width of the dedicated DBI slave databus.
Values: 32, 64, 128
Default Value: 32
Enabled: ((AMBA_INTERFACE==1))
Parameter Type: Feature Setting
Parameter Name: CC_DBI_SLV_BUS_DATA_WIDTH
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6.6 Basic AXI Config / PCIe TAGs and AXI IDs Parameters
Table 6-6 Basic AXI Config / PCIe TAGs and AXI IDs Parameters
Label Description
Slave
Max Outbound NP Requests This parameter is a read-only reflection of the CX_MAX_TAG parameter.
Values:
■ 2 (1)
■ 4 (3)
■ 8 (7)
■ 16 (15)
■ 32 (31)
■ 64 (63)
■ 128 (127)
■ 256 (255)
■ 512 (511)
■ 768 (767)
Default Value: CX_MAX_TAG
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_MAX_TAG_
AHB/AXI Slave Tags The maximum number of non-posted AXI requests issued to the bridge slave that are
outstanding at one time over the PCIe link. For more details, see "Outbound Bridge
Tag Management" in the "AXI Bridge Module" chapter of the Databook.
■ For AXI, the default value is CX_MAX_TAG+1. Note that CX_MAX_TAG
represents the number of PCIe TAGs minus 1.
■ When DMA is enabled, the default value for AXI is (CX_MAX_TAG +1)/2.
AHB Note:This parameter is derived automatically and is read-only.
Values: 2, 4, 8, 16, 32, 64, 128, 256
Default Value: ((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=2)) ? 2 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=4)) ? 4 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=8)) ? 8 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=16)) ? 16 :
(CC_DMA_ENABLE_VALUE==1) ? ((CX_MAX_TAG==3) ? 2 : (CX_MAX_TAG==7) ?
4 : (CX_MAX_TAG==15) ? 8 : (CX_MAX_TAG==31) ? 16 : (CX_MAX_TAG==63) ? 32
: (CX_MAX_TAG==127) ? 64 : (CX_MAX_TAG>=255) ? 128 : 2) :
((CX_MAX_TAG<=255) ? CX_MAX_TAG + 1 : 256)
Enabled: SLAVE_POPULATED && (AHB_ENABLED==0)
Parameter Type: Performance Setting
Parameter Name: CC_MAX_SLV_TAG
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Label Description
AXI High Priority Master IDs Represents the maximum number of AXI master IDs and the maximum number of
outstanding NP transactions the AXI High Priority master can handle. This value must
be smaller than CC_MAX_MSTR_TAGS_AXI. The Low Priority master will handle
(CC_MAX_MSTR_TAGS_AXI-CC_MAX_MSTRH_TAGS_AXI). NOTE: This parameter
is only visible when High Priority Master is enabled.
Values: 1, ..., (CC_MAX_MSTR_TAGS_AXI-1)
Default Value: CC_MAX_MSTR_TAGS_AXI/2
Enabled: CC_HP_MASTER
Parameter Type: Performance Setting
Parameter Name: CC_MAX_MSTRH_TAGS_AXI
Master
AXI Master IDs Represents the maximum number of AXI master IDs and the maximum number of
outstanding NP transactions the AXI bridge can handle. It is used to size the master
completion RAM which can be large if CC_MAX_MSTR_TAGS_AXI is large. You
should set CC_MAX_MSTR_TAGS_AXI to the minimum number of outstanding AXI
requests that are required to saturate the AXI bus and/or supply the throughput
required by the core. If decomposition occurs, the number of simultaneously
outstanding AXI requests is larger than this value. For more details, see the 'Inbound
Bridge Tag Management' section in the AXI Bridge chapter of the Databook. This
parameter is used to size the master ID busses with the value
log2{CC_MAX_MSTR_TAGS_AXI}.
Values: 2, 4, 8, 16, 32, 64, 128, 256
Default Value: 32
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Performance Setting
Parameter Name: CC_MAX_MSTR_TAGS_AXI
Synopsys, Inc.
Label Description
Slave
Max Outbound NP Requests This parameter is a read-only reflection of the CX_MAX_TAG parameter.
Values:
■ 2 (1)
■ 4 (3)
■ 8 (7)
■ 16 (15)
■ 32 (31)
■ 64 (63)
■ 128 (127)
■ 256 (255)
■ 512 (511)
■ 768 (767)
Default Value: CX_MAX_TAG
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_MAX_TAG_
AHB/AXI Slave Tags The maximum number of non-posted AXI requests issued to the bridge slave that are
outstanding at one time over the PCIe link. For more details, see "Outbound Bridge
Tag Management" in the "AXI Bridge Module" chapter of the Databook.
■ For AXI, the default value is CX_MAX_TAG+1. Note that CX_MAX_TAG
represents the number of PCIe TAGs minus 1.
■ When DMA is enabled, the default value for AXI is (CX_MAX_TAG +1)/2.
AHB Note:This parameter is derived automatically and is read-only.
Values: 2, 4, 8, 16, 32, 64, 128, 256
Default Value: ((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=2)) ? 2 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=4)) ? 4 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=8)) ? 8 :
((AHB_ENABLED==1) && (CC_AHB_SNUM_MASTERS<=16)) ? 16 :
(CC_DMA_ENABLE_VALUE==1) ? ((CX_MAX_TAG==3) ? 2 : (CX_MAX_TAG==7) ?
4 : (CX_MAX_TAG==15) ? 8 : (CX_MAX_TAG==31) ? 16 : (CX_MAX_TAG==63) ? 32
: (CX_MAX_TAG==127) ? 64 : (CX_MAX_TAG>=255) ? 128 : 2) :
((CX_MAX_TAG<=255) ? CX_MAX_TAG + 1 : 256)
Enabled: SLAVE_POPULATED && (AHB_ENABLED==0)
Parameter Type: Performance Setting
Parameter Name: CC_MAX_SLV_TAG
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Label Description
Target Completion LUT Enable Enable the Target Completion Lookup Table to be connected internally between the
RTRGT1 and XALI0/1/2 interfaces. This feature provides two functions:
■ The application does not need to provide certain TLP header information when
transmitting completions on XALI0/1/2 because the controller stores and tracks the
information in the internal Target Completion Lookup Table.
■ When the application has not generated a completion for an incoming request
within the required time interval, then the Target Completion Timeout indicates that
a Timeout has occurred.
The Target Completion Lookup Table (and Target Completion Timeout event) should
not be confused with the Completion Lookup table (and Completion Timeout event)
described in 'Received Completion TLP Processing' in the Databook. For more details,
see the 'Target Completion Lookup Table' section of the "Signal Interfaces" chapter of
the Databook. The size of the this LUT is controlled using the 'Max Forwarded NP
Requests' (CX_REMOTE_MAX_TAG) parameter.Note:This feature is not available if
Peer-to-Peer support is enabled.Note:When the AXI bridge is used
(AMBA_INTERFACE=1, 2 or 3) or when DMA is enabled, the Target Completion
Lookup Table is automatically activated.
Values:
■ false (0)
■ true (1)
Default Value: (CC_DMA_ENABLE) ? 1 : (AMBA_POPULATED) ? 1 : 0
Enabled: ((TRGT1_POPULATE==1 && !(CC_DMA_ENABLE) &&
CC_DEVICE_TYPE!=CC_SW && CX_P2P_ENABLE==0 &&
AMBA_POPULATED==0))
Parameter Type: Feature Setting
Parameter Name: TRGT_CPL_LUT_EN
Synopsys, Inc.
Label Description
Max Forwarded NP Requests The function depends on the nature of the application interface.
■ AXI:You should leave this parameter at its default value.
■ Native core:Specifies the maximum number of received non-posted requests that
the controller will forward to your application at one time, when the Target Comple-
tion LUT (TRGT_CPL_LUT_EN) is enabled. The default value is sufficient for
typical applications. It does not control the number of non-posted requests that the
controller can receive and buffer from the PCIe wire, which is controlled by flow
control credits.
Values:
■ 2_Tags (1)
■ 4_Tags (3)
■ 8_Tags (7)
■ 16_Tags (15)
■ 32_Tags (31)
■ 64_Tags (63)
■ 128_Tags (127)
■ 256_Tags (255)
■ 512_Tags (511)
■ 1024_Tags (1023)
Default Value: CC_HP_MASTER ? CC_MAX_MSTR_TAGS_AXI-1
:AHB_POPULATED ? 1 : (AXI_POPULATED ? CC_MAX_MSTR_TAGS - 1 :
((CX_MAX_TAG == 767) ? 1023 : CX_MAX_TAG))
Enabled: ((AMBA_POPULATED) ? 0 : (TRGT_CPL_LUT_EN))
Parameter Type: Performance Setting
Parameter Name: CX_REMOTE_MAX_TAG
Enable Address Alignment When enabled (and input client*_addr_align_en input is asserted), the controller
supports address alignment and generates the first and last byte enables (FBE, LBE)
based on the address and number of bytes of the TLP requested from the client
interface. When CX_ECRC_EN is not set, GLOB_ADDR_ALIGN_EN should normally
be disabled. However, if your application requires this to be enabled, then the address
alignment pin (client0/1/2_addr_align_en) should only be high for those TLPs without
ECRC. For TLPs with ECRC that are being transmitted by the Application, the address
alignment pin (client0/1/2_addr_align_en) should be de-asserted for that TLP. For
more information, see 'Transmit Address Alignment' section in the "Signal
Descriptions" chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: !AMBA_POPULATED && CX_P2P_ENABLE==0
Parameter Type: Feature Setting
Parameter Name: GLOB_ADDR_ALIGN_EN
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Label Description
Byte Count Storage Determines whether or not to store the byte count in the receive completion LUT. If the
controller does not a receive a completion for each request, then the completion
timeout mechanism will terminate the request. It will also indicate on the
radm_timeout_cpl_len[11:0] output port, the number of bytes remaining to be
delivered when the completion timed out. When the byte count is not stored in the LUT,
the controller is unable to detect when it is receiving a completion with an incorrect
byte count field. Therefore completions with incorrect byte count will be treated as valid
completions instead of being treated as unexpected completions. The controller will
not detect missing completions and the receive completion LUT will not timeout.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_CPL_LUT_STORE_BYTE_CNT
Application Return CRD Enable Include optional top-level ports for the application to update the Flow Control credits
counters. The optional ports are the app_*_ca ports on the SII (see 'System
Information Interface (SII)' section of the "Signal Descriptions" chapter Databookfor
more details).
Note:The application is not expected to return completion credits since completion
credits are infinite according to the PCI Express 3.1 Specification.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: APP_RETURN_CRD_EN
Lane/Link Options
Enable Manual Lane Flip Include support for manual lane flip. For more information, see the 'Lane Reversal'
(Conventional PCIe) chapter in the Databook. Include the tx_lane_flip_en and rx_lane_flip_en inputs to
manually control TX/RX Lane Reversal. M-PCIe doesn't support this feature.
Values:
■ false (0)
■ true (1)
Default Value: ((CX_LANE_REVERSE || CX_GEN5_SPEED) && CX_NL > 1) ? 1 : 0
Enabled: (!(CX_PCIE_MODE == SINGLE_MPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_LANE_FLIP_CTRL_EN
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Label Description
Enable Auto Lane Flip and Include support for auto lane flip and reversal. When you set this parameter, the
Reversal controller implements logic to:
■ flip the lanes autonomously in Detect LTSSM state when lane0 is not detected, and
■ reverse the lanes autonomously in Configuration LTSSM state when logical lane0
receives TS ordered sets with lane number different from '0'.
For more information, see the description of the AUTO_LANE_FLIP_CTRL_EN
register in the Register Descriptionsdocument and 'Lane Reversal' chapter in the
Databook.
Values:
■ false (0)
■ true (1)
Default Value: (CX_LANE_FLIP_CTRL_EN) ? 1 : 0
Enabled: CX_LANE_FLIP_CTRL_EN
Parameter Type: Feature Setting
Parameter Name: CX_AUTO_LANE_FLIP_CTRL_EN
Enable Partial Auto Lane Flip and Enables support for partial auto flipping or reversal of the lanes.
Reversal ■ Full flip or reversal: Lane0 is connected to Lane NL-1.
■ Partial flip or reversal: Lane0 is connected to either Lane NL/2-1 or Lane NL/4-1 or
Lane NL/8-1 etc.
For more information, see the 'Lane Reversal' chapter in the Databook.
Values:
■ Full (0)
■ Full or Partial (1)
■ Full and Partial (2)
Default Value: (CX_LANE_REVERSE) ? 2 : 1
Enabled: CX_AUTO_LANE_FLIP_CTRL_EN
Parameter Type: Feature Setting
Parameter Name: CX_AUTO_LANE_FLIP_MUX_ARCH
Enable Forced Lane Flip When this parameter is set to true, and FORCE_LANE_FLIP field of
GEN2_CTRL_OFF register is set to 1, you can forcefully connect the physical lane
specified in LANE_UNDER_TEST field of GEN2_CTRL_OFF register to logical Lane0
of the controller after reset. Only the physical lane specified in LANE_UNDER_TEST
can be flipped to logical Lane0, starting from Detect LTSSM state. That is, only x1 can
be formed, all the other physical lanes are turned off.
Values:
■ false (0)
■ true (1)
Default Value: CX_LANE_FLIP_CTRL_EN
Enabled: CX_LANE_FLIP_CTRL_EN
Parameter Type: Feature Setting
Parameter Name: CX_FORCE_LANE_FLIP_EN
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Label Description
Default Link Number Default Link Number value that the Upstream Device advertises to the Downstream
Link partner over the TS sequence. It is also the default value for the Link Number field
in the 'Port Force Link Register'. This register is used to force the link to the state
specified by the Link State field through a link re-negotiation. For more details, see the
Registers chapter of the Databook. M-PCIe doesn't have this feature. M-PCIe doesn't
support this feature.
Values: 0x0, ..., 0xff
Default Value: 0x4
Enabled: CX_CPCIE_ENABLE && CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_LINK_NUM
Disable Lane Deskew Disable the deskewing mechanism. Disable the deskewing mechanism only if
connecting to a multi-Lane PHY that implements Lane-to-Lane deskewing. For more
details, see the "Lane Deskew" chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_NL == 1
Enabled: ((CX_NL > 1))
Parameter Type: Feature Setting
Parameter Name: CX_DESKEW_DISABLE
Deskew Fifo Depth for C-PCIe Specifies the depth of fifos used in the deskew logic for C-PCIe. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 2, ..., 25
Default Value:
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Label Description
Deskew Fifo Depth for C-PCIe (CX_CCIX_ESM_SUPPORT == 1) && (CX_MAX_PCIE_SPEED == 5) && (CX_NB ==
...(cont.) 4) ? 14 : (CX_CCIX_ESM_SUPPORT == 1) && (CX_NB == 2) ? 22 :
(CX_CCIX_ESM_SUPPORT == 1) && (CX_NB == 4) ? 13 :
(CX_CCIX_ESM_SUPPORT == 1) && (CX_NB == 16) ? 12 :
(CX_MAX_PCIE_SPEED == 5) && (CX_NB == 4) ? 14 : (CX_MAX_PCIE_SPEED ==
5) && (CX_NB == 8) ? 12 : (CX_MAX_PCIE_SPEED == 4) &&
(CX_GEN4_DYNAMIC_WIDTH == 1) && (CX_NB == 16) ? 12 :
(CX_MAX_PCIE_SPEED == 4) && (CX_GEN4_DYNAMIC_WIDTH == 1) && (CX_NB
== 8 ) ? 14 : (CX_MAX_PCIE_SPEED == 4) && (CX_GEN4_DYNAMIC_FREQ == 1)
&& (CX_NB == 4 ) ? 12 : (CX_MAX_PCIE_SPEED == 4) &&
(CX_GEN4_DYNAMIC_FREQ == 1) && (CX_NB == 2 ) ? 20 :
(CX_MAX_PCIE_SPEED == 3) && (CX_GEN3_DYNAMIC_WIDTH == 1) && (CX_NB
== 8 ) ? 12 : (CX_MAX_PCIE_SPEED == 3) && (CX_GEN3_DYNAMIC_WIDTH == 1)
&& (CX_NB == 4 ) ? 14 : (CX_MAX_PCIE_SPEED == 3) &&
(CX_GEN3_DYNAMIC_FREQ == 1) && (CX_NB == 4 ) ? 11 :
(CX_MAX_PCIE_SPEED == 3) && (CX_GEN3_DYNAMIC_FREQ == 1) && (CX_NB
== 2 ) ? 12 : (CX_MAX_PCIE_SPEED == 3) && (CX_GEN3_DYNAMIC_FREQ == 1)
&& (CX_NB == 1 ) ? 19 : (CX_MAX_PCIE_SPEED == 2) &&
(CX_GEN2_DYNAMIC_WIDTH == 1) && (CX_NB == 4 ) ? 12 :
(CX_MAX_PCIE_SPEED == 2) && (CX_GEN2_DYNAMIC_WIDTH == 1) && (CX_NB
== 2 ) ? 14 : (CX_MAX_PCIE_SPEED == 2) && (CX_GEN2_DYNAMIC_FREQ == 1)
&& (CX_NB == 4 ) ? 11 : (CX_MAX_PCIE_SPEED == 2) &&
(CX_GEN2_DYNAMIC_FREQ == 1) && (CX_NB == 2 ) ? 12 :
(CX_MAX_PCIE_SPEED == 2) && (CX_GEN2_DYNAMIC_FREQ == 1) && (CX_NB
== 1 ) ? 14 : (CX_MAX_PCIE_SPEED == 1) && (CX_GEN2_MODE ==
GEN2_DISABLED) && (CX_NB == 4 ) ? 11 : (CX_MAX_PCIE_SPEED == 1) &&
(CX_GEN2_MODE == GEN2_DISABLED) && (CX_NB == 2 ) ? 12 :
(CX_MAX_PCIE_SPEED == 1) && (CX_GEN2_MODE == GEN2_DISABLED) &&
(CX_NB == 1 ) ? 14 : 14
Enabled: (!(CX_PCIE_MODE == SINGLE_MPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_DESKEW_DEPTH_CPCIE
+ Gen1 Wire Skew (Lrx-skew ns) This is read-only parameter to indicate how much wire skew for Gen1 speed your
deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: 20
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_GEN1_NS
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Label Description
+ Gen2 Wire Skew (Lrx-skew ns) This is read-only parameter to indicate how much wire skew for Gen2 speed your
deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 2) :
CX_S_CPCIE_MODE ? (CX_GEN2_MODE != GEN2_DISABLED) : 0)==1) ? 8 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_GEN2_NS
+ Gen3 Wire Skew (Lrx-skew ns) This is read-only parameter to indicate how much wire skew for Gen3 speed your
deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0)==1) ? 6 : 0
Enabled: CX_GEN3_SPEED==1 && SNPS_RSVDPARAM_32==1
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_GEN3_NS
+ Gen4 Wire Skew (Lrx-skew ns) This is read-only parameter to indicate how much wire skew for Gen4 speed your
deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: ((CX_GEN4_MODE != GEN4_DISABLED)==1) ? 5 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_GEN4_NS
+ Gen5 Wire Skew (Lrx-skew ns) This is read-only parameter to indicate how much wire skew for Gen5 speed your
deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: ((CX_MAX_PCIE_SPEED >= 5)==1) ? 5 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_GEN5_NS
+ CCIX ESM 20G Wire Skew This is read-only parameter to indicate how much wire skew for CCIX ESM 20G speed
(Lrx-skew ns) your deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details,
see the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: (CX_CCIX_ESM_SUPPORT==1) ? 4 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_CCIX20G_NS
Synopsys, Inc.
Label Description
+ CCIX ESM 25G Wire Skew This is read-only parameter to indicate how much wire skew for CCIX ESM 25G speed
(Lrx-skew ns) your deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details,
see the "Lane Deskew" chapter of the Databook.
Values: 0, ..., 60
Default Value: (CX_CCIX_ESM_SUPPORT==1) ? 4 : 0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_WIRE_SKEW_CCIX25G_NS
+ Gen1 PHY Skew (pipe_clk This is read-only parameter to indicate how much PHY skew for Gen1 speed your
cycles) deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 ) ? 0 :
(CX_SKEW_PIPEIF_GEN1_PCLK - CX_WIRE_SKEW_GEN1_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_GEN1_PCLK
+ Gen2 PHY Skew (pipe_clk This is read-only parameter to indicate how much PHY skew for Gen2 speed your
cycles) deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 || CX_GEN2_SPEED==0 )
? 0 : (CX_SKEW_PIPEIF_GEN2_PCLK - CX_WIRE_SKEW_GEN2_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_GEN2_PCLK
+ Gen3 PHY Skew (pipe_clk This is read-only parameter to indicate how much PHY skew for Gen3 speed your
cycles) deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 || CX_GEN3_SPEED==0 )
? 0 : (CX_SKEW_PIPEIF_GEN3_PCLK - CX_WIRE_SKEW_GEN3_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_GEN3_PCLK
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Label Description
+ Gen4 PHY Skew (pipe_clk This is read-only parameter to indicate how much PHY skew for Gen4 speed your
cycles) deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 || CX_GEN4_SPEED==0 )
? 0 : (CX_SKEW_PIPEIF_GEN4_PCLK - CX_WIRE_SKEW_GEN4_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_GEN4_PCLK
+ Gen5 PHY Skew (pipe_clk This is read-only parameter to indicate how much PHY skew for Gen5 speed your
cycles) deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details, see
the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 || CX_GEN5_SPEED==0 )
? 0 : (CX_SKEW_PIPEIF_GEN5_PCLK - CX_WIRE_SKEW_GEN5_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_GEN5_PCLK
+ CCIX ESM 20G PHY Skew This is read-only parameter to indicate how much PHY skew for CCIX ESM 20G speed
(pipe_clk cycles) your deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details,
see the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 ||
CX_CCIX_ESM_SUPPORT==0 ) ? 0 : (CX_SKEW_PIPEIF_CCIX20G_PCLK -
CX_WIRE_SKEW_CCIX20G_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_CCIX20G_PCLK
+ CCIX ESM 25G PHY Skew This is read-only parameter to indicate how much PHY skew for CCIX ESM 25G speed
(pipe_clk cycles) your deskew buffer setting (CX_DESKEW_DEPTH_CPCIE) ensures. For more details,
see the "Lane Deskew" chapter of the Databook.
Values: -2147483648, ..., 2147483647
Default Value: CX_DESKEW_DISABLE==1 || CX_NL==1 ||
CX_CCIX_ESM_SUPPORT==0 ) ? 0 : (CX_SKEW_PIPEIF_CCIX25G_PCLK -
CX_WIRE_SKEW_CCIX25G_PCLK
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_PHY_SKEW_CCIX25G_PCLK
Synopsys, Inc.
Label Description
+ Margin for Deskew Buffer This is read-only parameter to indicate how much margin your deskew buffer setting
Setting (CX_DESKEW_DEPTH_CPCIE) has. For more details, see the "Lane Deskew"
chapter of the Databook.
Values: 0, ..., 10
Default Value: 1
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_SKEW_MAC_MARGIN_CORECLK
Default Gen1/2 Replay Timer Default value for the 'Timer Modifier for Replay Timer' field in the 'Timer Control and
Adjustment Max Function Number' register. Each increment in this value increases the replay timer
by 64. For more details, see the 'Transmit Replay' section of the Controller Operations
chapter in the Databook.This parameter is for conventional PCIe mode.
Values: 0x0, ..., 0x1f
Default Value:
((CX_MAX_NFTS*4)/CX_NB)+(CX_CPCIE_INTERNAL_DELAY*3))/64 +
(((((CX_MAX_NFTS*4)/CX_NB)+(CX_CPCIE_INTERNAL_DELAY*3))%64) ? 1 : 0
Enabled: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE ))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_REPLAY_ADJ
Default Gen3/4/5 Replay Timer Default value (in Gen3/4/5 mode) for the 'Timer Modifier for Replay Timer' field in the
Adjustment 'Timer Control and Max Function Number' register at Gen3/4/5 speed. Must consider
an EIEOS is transmitted after every 32 FTS. Each increment in this value increases
the replay timer by 256. For more details, see the 'Transmit Replay' section of the
Controller Operations chapter in the Databook. M-PCIe doesn't support this feature.
Values: 0x0, ..., 0x1f
Default Value: ((CX_MAX_NFTS*65)/(CX_NB*1024)) +
((CX_MAX_NFTS*65)/(CX_NB*32768)) + ((CX_CPCIE_INTERNAL_DELAY*3)/256) +
3
Enabled: CX_GEN3_SPEED == 1 && CX_CPCIE_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_REPLAY_ADJ
Default FC Watch Dog Disable Default value of the Disable FC Watchdog Timer bit of the 'Symbol Timer Register and
Filter Mask 1' Register, in the 'Registers' section of the Databook.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: DEFAULT_FC_WATCH_DOG_DISABLE
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Label Description
Cfg Directed Speed Change Enables the controller to initiate a Gen1 -> Gen2 and Gen2 -> Gen3 speed change
after the link is initialized. Only applicable for Gen2 or Gen3 configured cores. This is
the default value of the "Directed Speed Change" field of the "Link width and Speed
Change Control" register. M-PCIe doesn't support this feature.
Values: 0, 1
Default Value: 0
Enabled: ((CX_S_MPCIE_MODE) ? 0 : CX_GEN2_SPEED)
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN2_SPEED_CHANGE
Power Gating
Power Gating/UPF Support Enables support for power gating using the UPF flow.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CX_CPCIE_ENABLE || SNPS_RSVDPARAM_9 ||
!CM_SNPS_MPHY_ENABLE) && !(AMBA_INTERFACE==1))
Parameter Type: Feature Setting
Parameter Name: CX_ENHANCED_PM_EN
Power Gating/PHY Support Enable power gating support in the PHY. When setting this parameter the PHY UPF
will be read in during PHY interoperability testing. If using a third party PHY, you need
to setup the PHY UPF following the guidelines provided in the User Guide, "Integrating
the controller with the PHY".
Values:
■ false (0)
■ true (1)
Default Value: CX_ENHANCED_PM_EN
Enabled: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE ))
Parameter Type: Feature Setting
Parameter Name: CX_PHY_ENHANCED_PM_EN
VAUX Available Indicates that VAUX power domain is available in L2 when VMAIN is removed.
Values: 0, 1
Default Value: 0
Enabled: CX_ENHANCED_PM_EN || CX_PHY_ENHANCED_PM_EN
Parameter Type: Feature Setting
Parameter Name: CX_EXISTS_VAUX
Synopsys, Inc.
Label Description
PHY L2 Power Gating Enable Indicates that power gating is supported in the PHY in L2
Values: 0, 1
Default Value: CX_L2_PG_EN
Enabled: CX_PHY_ENHANCED_PM_EN && CX_EXISTS_VAUX
Parameter Type: Feature Setting
Parameter Name: CX_PHY_L2_PG_EN
PHY L1 Power Gating Enable Enable support for power-gating L1 sub-states (L1.2) in C-PCIe PHY.
Values: 0, 1
Default Value: CX_L12_PG_EN
Enabled: ((CX_PHY_ENHANCED_PM_EN) && (CX_L1_SUBSTATES_ENABLE))
Parameter Type: Feature Setting
Parameter Name: CX_PHY_L1_PG_EN
L1 Power Gating Enable Enable support for power-gating L1 sub-states (L1.2) in C-PCIe or L1 in M-PCIe. If you
want to disable L1 power gating in real-time, set app_l1_pwr_off_en =0.
Values: 0, 1
Default Value: 0
Enabled: ((CX_ENHANCED_PM_EN) && (CX_L1_SUBSTATES_ENABLE ||
CX_MPCIE_ENABLE))
Parameter Type: Feature Setting
Parameter Name: CX_L12_PG_EN
L1 Power Gating Mode Select always-on power islands or retention registers for L1 power gating. If you want
to disable L1 power gating, set app_l1_pwr_off_en =0.
Values:
■ Power Islands (0)
■ Retention Registers (1)
Default Value: Power Islands
Enabled: (CX_L12_PG_EN && (CX_L1_SUBSTATES_ENABLE ||
CX_MPCIE_ENABLE))
Parameter Type: Feature Setting
Parameter Name: CX_L1_RETENTION
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Label Description
L1 Retention Register Type This parameter determines the type of retention register inferred in the UPF file for L1
power gating.
Values:
■ Single Pin Retention (1)
■ Balloon Retention (2)
Default Value: Balloon Retention
Enabled: CX_L1_RETENTION
Parameter Type: Feature Setting
Parameter Name: CX_RETENTION_TYPE
L2 Level Shifter Enable Enable level shifting on the boundary between VAUX and VMAIN power domains
Values: 0, 1
Default Value: 0
Enabled: CX_ENHANCED_PM_EN && CX_L2_PG_EN
Parameter Type: Feature Setting
Parameter Name: CX_LEVEL_SHIFT_EN
Power Switch Enable Polarity Determine the polarity and naming of the power switch enable output.
■ 0: pm_en_vmain_n
■ 1: pm_en_vmain
Values:
■ LOW (0)
■ HIGH (1)
Default Value: LOW
Enabled: CX_L12_PG_EN
Parameter Type: Feature Setting
Parameter Name: CX_PSW_EN_ACTIVE_LOW
Save/Restore M-PHY Registers Enable saving/restoring of M-PHY registers during L1 power removal when M-PHY
power is off.
Values: 0, 1
Default Value: (CX_MPCIE_ENABLE && CX_ENHANCED_PM_EN &&
CM_SNPS_MPHY_ENABLE && SNPS_RSVDPARAM_9) ? 1 : 0
Enabled: CX_ENHANCED_PM_EN && CX_MPCIE_ENABLE &&
SNPS_RSVDPARAM_9
Parameter Type: Feature Setting
Parameter Name: CM_STORE_MPHY_ATTR_ENABLE
Synopsys, Inc.
Label Description
Power Switch Acknowledge If this bit is set to 0 the power management logic will wait for the power switch
Handhshake after PERST# acknowledge to be deasserted after PERST# is asserted. If this bit is set to 1 the
power management logic does not check the power switch acknowledge after
PERST# is asserted.
Values: 0, 1
Default Value: 0
Enabled: CX_L2_PG_EN
Parameter Type: Feature Setting
Parameter Name: CX_VMAIN_ACK_CTRL_RST_VALUE
ASPM Options
L1 Entry Latency Default value for the L1 Entrance Latency of the 'Ack Frequency and L0-L1 ASPM
Control' register. For more details, see the Registers section of the Databook. The
default value is acceptable unless a Custom or Generic PHY is used.
Values:
■ 1 us (0x0)
■ 2 us (0x1)
■ 4 us (0x2)
■ 8 us (0x3)
■ 16 us (0x4)
Default Value: 8 us
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L1_ENTR_LATENCY
L0S Entry Latency Default value for the L0s Entrance Latency field of the 'Ack Frequency and L0-L1
ASPM Control' register. For more details, see the Registers section of the Databook.
The default value is acceptable unless a Custom or Generic PHY is used. In M-PCIe,
this parameter is applicable to the STALL state in L0.
Values:
■ 1 us (0x0)
■ 2 us (0x1)
■ 3 us (0x2)
■ 4 us (0x3)
■ 5 us (0x4)
■ 6 us (0x5)
■ 7 us (0x6)
■ also 7us (0x7)
Default Value: 4 us
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L0S_ENTR_LATENCY
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Label Description
Enable ASPM L1 Timeout Enable the ASPM L1 timer so that the controller will automatically go to L1 when the
timer expires and the conditions in the PCI Express 3.1 Specificationare met. If you
disable the APSM L1 timer, the application can request L1 entry by asserting
app_req_entr_l1. The ASPM L1 timer should be larger than the L0s timer. Otherwise,
ASPM L0s and L1 timeout may not function properly.
Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_PL_MODE != 1
Enabled: CX_PL_MODE != 1
Parameter Type: Feature Setting
Parameter Name: CX_ASPM_TIMEOUT_ENTR_L1_EN
Error Detection
Enable ECRC Support Include the ECRC generation and checking hardware. This is distinct from the
software control that may be used to enable or disable ECRC.When disabled, ECRC
checking and insertion logic will not be included in the controller in order to reduce
gates. This is especially important for large architectures, in which these blocks can
consume timing margin as well as area. May be disabled for smaller gate size if the
controller is placed in a system where it's guaranteed that received TLPs don't contain
ECRC andyour application does not transmit ECRC from the application (client)
interfaces.
Values:
■ false (0)
■ true (1)
Default Value: CX_ADM_ADAPTOR_ENABLE==1 ? 0 : 1
Enabled: (TRGT1_POPULATE && !(AMBA_POPULATED) && !(CC_DMA_ENABLE))
Parameter Type: Feature Setting
Parameter Name: CX_ECRC_ENABLE
Synopsys, Inc.
Label Description
Enable ECRC Stripping Include ECRC stripping hardware. If enabled, the controller strips ECRC from all
incoming packets. The controller always strips the ECRC when you have selected the
AHB/AXI bridge module, or when DMA controller is selected. The controller never
strips the ECRC when you enable CX_P2P_ENABLE.
Values:
■ false (0)
■ true (1)
Default Value: !(TRGT1_POPULATE) || (CX_RAM_PROTECTION_MODE==2 &&
CX_RADMQ_MODE!=2) || (CX_ECRC_ENABLE && CC_DEVICE_TYPE!=CC_SW
&& !(CX_P2P_ENABLE)) || (( (RADM_NP_QMODE_VC0==2) ||
(RADM_NP_QMODE_VC1==2) || (RADM_NP_QMODE_VC2==2) ||
(RADM_NP_QMODE_VC3==2) || (RADM_NP_QMODE_VC4==2) ||
(RADM_NP_QMODE_VC5==2) || (RADM_NP_QMODE_VC6==2) ||
(RADM_NP_QMODE_VC7==2)) && (ARC_WIDTH==32)) ||
CX_CPLQ_MANAGEMENT_ENABLE
Enabled: (TRGT1_POPULATE && !(AMBA_POPULATED) && !(CC_DMA_ENABLE)
&& !(CC_DEVICE_TYPE==CC_SW) && !(CX_P2P_ENABLE) &&
!(CX_RAM_PROTECTION_MODE==2 && CX_RADMQ_MODE!=2) && !( (
(RADM_NP_QMODE_VC0==2) || (RADM_NP_QMODE_VC1==2) ||
(RADM_NP_QMODE_VC2==2) || (RADM_NP_QMODE_VC3==2) ||
(RADM_NP_QMODE_VC4==2) || (RADM_NP_QMODE_VC5==2) ||
(RADM_NP_QMODE_VC6==2) || (RADM_NP_QMODE_VC7==2)) &&
(ARC_WIDTH==32)) || CX_CPLQ_MANAGEMENT_ENABLE )
Parameter Type: Feature Setting
Parameter Name: CX_ECRC_STRIP_ENABLE
Include 3rd Client Interface Determines whether to include top-level ports for the optional third application transmit
client interface (XALI2).
Values:
■ false (0)
■ true (1)
Default Value: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3)) ? 1 : 0
Enabled: (!(AMBA_INTERFACE!=0))
Parameter Type: Feature Setting
Parameter Name: CLIENT2_POPULATED
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Label Description
Enable Diagnostic Bus Enables routing of diag_status_bus and diag_ctrl_bus signals to the SII interface. For
more details, see 'SII: Diagnostic Control Signals' in the "Signal Descriptions" chapter
of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: CX_RAS_DES_ENABLE
Enabled: !CX_RAS_DES_ENABLE
Parameter Type: Feature Setting
Parameter Name: DIAGNOSTIC_ENABLE
Application Error Reporting Determines whether to include input ports for application-detected error reporting. For
more details, see the "Application Error Reporting Interface" section on the " Advanced
Error Handling For Received TLPs" chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: CX_DPC_ENABLE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: APP_RETURN_ERR_EN
DBI ReadOnly Write Enable Default value of the DBI Read-Only Write Enable port logic register. For more details,
see the "Register Configuration Space" chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_DBI_RO_WR_EN
Disable Port Logic wire side write When set will disable write access to port logic space from the wire.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_PL_WIRE_WR_DISABLE
Synopsys, Inc.
Label Description
ELBI Address Bus Width Defines the width of the ELBI address bus for the Local Bus Controller (LBC). Only
12-bits are needed to access the 4KB (1K DWORDS) of the PCI Express
Configuration space per function. However, in order to access more than 4 KB of ELBI
register space, the default value of CX_LBC_EXT_AW can be increased up to a
maximum of 32. Refer to 'Local Bus Controller (LBC)' section in the Architecture
chapter of the Databook.
Values: 12, ..., (FLT_Q_ADDR_WIDTH<=32) ? FLT_Q_ADDR_WIDTH : 32
Default Value: 32
Enabled: ((CC_DEVICE_TYPE!=CC_RC))
Parameter Type: Feature Setting
Parameter Name: CX_LBC_EXT_AW
ELBI Data Bus Width Defines the width of the ELBI databus for the Local Bus Controller (LBC) in dwords.
There are 32 or 64 bits of ext_lbc_din for each function in your controller configuration.
(128 bits is planned for future release).
Values:
■ 32-bit (1)
■ 64-bit (2)
Default Value: 32-bit
Enabled: ((CC_DEVICE_TYPE!=CC_RC))
Parameter Type: Feature Setting
Parameter Name: CX_LBC_NW
DBI Full Access with BAR and Provide support to allow DBI full access with BAR number and function number.
Function Number Setting the DBI_MULTI_FUNC_BAR_EN configuration parameter allows the DBI
interface to direct an access to a particular BAR#. This helps the ELBI application logic
to fully decode an access to the ELBI space when multiple BARs have been mapped
to RTRGT0 and need to be accessed via the DBI. By default,
DBI_MULTI_FUNCT_BAR_EN is set to 0, indicating a single BAR at the ELBI. Refer to
'Local Bus Controller (LBC)' section in the Architecture chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: MSIX_TABLE_EN
Enabled: ((CC_DEVICE_TYPE!=CC_RC) && (CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Feature Setting
Parameter Name: DBI_MULTI_FUNC_BAR_EN
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Label Description
Application Configuration This configuration parameter is deprecated and should no longer be used. Specifies
Register Address the default value of register CONFIG_LIMIT_REG. It specifies a limit above which
incoming configuration requests will be routed to the destination interface defined by
TARGET_ABOVE_CONFIG_LIMIT. The CONFIG_LIMIT parameter is normally set to
a limit that divides the core's configuration space registers from the application's
configuration space registers. The controller LBC module uses this limit to direct a
configuration request to the CDM or ELBI/RTRGT1. The application must set a proper
value based on its extended configuration registers. For more details, see the 'Local
Bus Controller (LBC)' section in the Controller Operations chapter of the Databook.
■ This value indicates a DWORD address and not a byte address.
■ The default setting of 0x3FF corresponds to the 4K upper limit of configuration
space and so TRGT0 will consume all CFG transactions by default.
CONFIG_LIMIT must be set to a value lower than this is have an effect.
Normally, you would never set this to less than 0xD00 which is the top of the Synopsys
Port Logic register space. Note: Superseded by the Configuration Intercept
Controller(CIC) interface, enabled when CX_CONFIG_INTERCEPT_ENABLE=1. The
CIC provides a much more flexible way for the application to control routing of
configuration transactions.
Values: 0x0, ..., 0x3ff
Default Value: 0x3ff
Enabled: CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: CONFIG_LIMIT
Synopsys, Inc.
Label Description
Memory Map Port Logic Enables routing of memory (non-CFG) transactions to the port logic (PL) configuration
Registers registers. This is memory mapping of the PL register space. PL registers (which by
default are accessed by CFG requests) can also (at the same time) be accessed by
MEM requests through the use of the ENABLE_MEM_MAP_PL_REG,
PL_FUNC_NUM and PL_BAR_NUM configuration parameters. These can be used to
map the PL registers to any BAR of any function. All MEM requests that match
PL_BAR_NUM (when ENABLE_MEM_MAP_PL_REG=1) and whose address offset is
in the range 0x700-0x8FF will be routed to the PL registers. The BAR corresponding to
PL_BAR_NUM must also be mapped/assigned to RTRGT0. For more details, see the
"Local Bus Controller (LBC)" section in the "Controller Operations" chapter of the
Databook.
Values: 0, 1
Default Value: 0
Enabled: CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: ENABLE_MEM_MAP_PL_REG
Port Logic Function Indicates which function is used to map the Port Logic configuration registers into
memory space. For more details, see the ENABLE_MEM_MAP_PL_REG parameter.
Values: 0, ..., 7
Default Value: 0
Enabled: ENABLE_MEM_MAP_PL_REG==1
Parameter Type: Feature Setting
Parameter Name: PL_FUNC_NUM
Port Logic BAR Indicates which BAR is used to map the Port Logic configuration registers into memory
space. For more details, see the ENABLE_MEM_MAP_PL_REG parameter.
Values:
■ BAR0 (0)
■ BAR1 (1)
■ BAR2 (2)
■ BAR3 (3)
■ BAR4 (4)
■ BAR5 (5)
Default Value: BAR0
Enabled: ENABLE_MEM_MAP_PL_REG==1
Parameter Type: Feature Setting
Parameter Name: PL_BAR_NUM
Port Logic Register Address Limit Indicates the limit address for BAR matched memory mapped Port Logic configuration
registers.
Values: 2304, ..., 3104
Default Value: 3104
Enabled: ENABLE_MEM_MAP_PL_REG==1
Parameter Type: Feature Setting
Parameter Name: PL_LIMIT
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Label Description
Configuration Intercept Enable Enables Configuration Intercept feature. Allows your application logic to modify the
behavior of Rx CFG requests that are accessing the core's internal registers. For more
details, see the "Advanced LBC and DBI Usage" chapter in the Databook. This is an
advanced feature that is only required in exceptional applications.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: CX_CONFIG_INTERCEPT_ENABLE
Memory Map ATU UNROLL Enables routing of memory (non-CFG) transactions to the Unroll ATU configuration
Registers registers. Unroll registers can be accessed by MEM requests through the use of the
ENABLE_MEM_MAP_UNROLL_ATU_REG, UNROLL_FUNC_NUM and
UNROLL_BAR_NUM configuration parameters. These can be used to map the
UNROLL registers to any BAR of any function. All MEM requests that match
UNROLL_BAR_NUM (when ENABLE_MEM_MAP_UNROLL_ATU_REG=1) and
whose address offset is in the range
UNROLL_ATU_OFFSET_BAR-UNROLL_ATU_OFFSET_BAR+UNROLL_ATU_SIZE
will be routed to the UNROLL registers. The BAR corresponding to
UNROLL_BAR_NUM must also be mapped/assigned to RTRGT0. For more details,
see the "Local Bus Controller (LBC)" section in the "Controller Operations" chapter of
the Databook.
Values: 0, 1
Default Value: 0
Enabled: CC_DEVICE_TYPE!=CC_RC && CX_INTERNAL_ATU_ENABLE &&
CC_UNROLL_ENABLE
Parameter Type: Feature Setting
Parameter Name: ENABLE_MEM_MAP_UNROLL_ATU_REG
Offset BAR address for ATU Indicates the offset BAR address to allocate the UNROLL ATU configuration registers
UNROLL Registers into memory space.
Values: 0x0, ..., 0xffffffffffffffff
Default Value: 0x1200
Enabled: ENABLE_MEM_MAP_UNROLL_ATU_REG==1
Parameter Type: Feature Setting
Parameter Name: UNROLL_ATU_OFFSET_BAR
Synopsys, Inc.
Label Description
Memory Map DMA UNROLL Enables routing of memory (non-CFG) transactions to the Unroll DMA configuration
Registers registers. Unroll DMA registers can be accessed by MEM requests through the use of
the ENABLE_MEM_MAP_UNROLL_DMA_REG, UNROLL_FUNC_NUM and
UNROLL_BAR_NUM configuration parameters. These can be used to map the
UNROLL registers to any BAR of any function. All MEM requests that match
UNROLL_BAR_NUM (when ENABLE_MEM_MAP_UNROLL_DMA_REG=1) and
whose address offset is in the range
UNROLL_DMA_OFFSET_BAR-UNROLL_DMA_OFFSET_BAR+UNROLL_DMA_SIZ
E will be routed to the UNROLL registers. The BAR corresponding to
UNROLL_BAR_NUM must also be mapped/assigned to RTRGT0. For more details,
see the "Local Bus Controller (LBC)" section in the "Controller Operations" chapter of
the Databook.
Values: 0, 1
Default Value: 0
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DMA_ENABLE &&
CC_UNROLL_ENABLE
Parameter Type: Feature Setting
Parameter Name: ENABLE_MEM_MAP_UNROLL_DMA_REG
Offset BAR address for DMA Indicates the offset BAR address to allocate the UNROLL DMA configuration registers
UNROLL Registers into memory space.
Values: 0x0, ..., 0xffffffffffffffff
Default Value: 0x1000
Enabled: ENABLE_MEM_MAP_UNROLL_DMA_REG
Parameter Type: Feature Setting
Parameter Name: UNROLL_DMA_OFFSET_BAR
UNROLL Function Indicates which function is used to map the Unroll configuration registers into memory
space. For more details, see the ENABLE_MEM_MAP_UNROLL_ATU_REG or
ENABLE_MEM_MAP_UNROLL_DMA_REG parameter.
Values: 0, ..., 7
Default Value: 0
Enabled: ENABLE_MEM_MAP_UNROLL_ATU_REG==1 ||
ENABLE_MEM_MAP_UNROLL_DMA_REG==1
Parameter Type: Feature Setting
Parameter Name: UNROLL_FUNC_NUM
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PCI Express SW Controller Databook Device-Wide Optional Non-PCIe Config Parameters
Label Description
UNROLL BAR Indicates which BAR is used to map the UNROLL configuration registers into memory
space. For more details, see the ENABLE_MEM_MAP_UNROLL_ATU_REG or
ENABLE_MEM_MAP_UNROLL_DMA_REG parameter.
Values:
■ BAR0 (0)
■ BAR1 (1)
■ BAR2 (2)
■ BAR3 (3)
■ BAR4 (4)
■ BAR5 (5)
Default Value: BAR0
Enabled: ENABLE_MEM_MAP_UNROLL_ATU_REG==1 ||
ENABLE_MEM_MAP_UNROLL_DMA_REG==1
Parameter Type: Feature Setting
Parameter Name: UNROLL_BAR_NUM
Number of Address Bits Passed Indicates the number of address bits that are passed through the receive queues and
to the Application are sent to the application on the RTRGT1 interface (radm_trgt1_addr).
■ DM/RC: The default is 64. the minimum number of bits allowed is normally 32.
■ SW: The default is 64 and the parameter is read-only.
■ EP: The default is 64 when VENDOR_MESSAGE_SUPPORT |
DEFAULT_TARGET | ((CX_INTERNAL_ATU_ENABLE | ADDR_TRANSLA-
TION_SUPPORT_EN) & CX_CLIENT_PAR_MODE !=0 ), otherwise 32. The
minimum number of bits allowed is normally 32.
Values: 26, ..., 64
Default Value: (VENDOR_MESSAGE_SUPPORT || DEFAULT_TARGET ||
(CC_DEVICE_TYPE!=CC_EP) || ADDR_TRANSLATION_SUPPORT_EN &&
(CX_CLIENT_PAR_MODE!=0 || ECC_PROTECTION_EN!=0)) ? 64 : 32
Enabled: !(VENDOR_MESSAGE_SUPPORT || DEFAULT_TARGET ||
(CC_DEVICE_TYPE==CC_SW) || ADDR_TRANSLATION_SUPPORT_EN &&
(CX_CLIENT_PAR_MODE!=0 || ECC_PROTECTION_EN!=0))
Parameter Type: Feature Setting
Parameter Name: FLT_Q_ADDR_WIDTH
Synopsys, Inc.
Label Description
Application Receives Full When you want to route the third header dword of received messages to your
Message Header application interface (RRTRGT1 or AXI bridge master interface), then you must
manually set FLT_Q_ADDR_WIDTH to 64 bits, or set this parameter to "1". Setting this
parameter to "1" forces FLT_Q_ADDR_WIDTH to 64 bits. This adds gates and makes
some RAMs wider. The complete message header is always routed to the SII interface
regardless of this parameter setting.
Values:
■ false (0)
■ true (1)
Default Value: CX_CCIX_INTERFACE_ENABLE
Enabled: CC_DEVICE_TYPE==CC_EP
Parameter Type: Feature Setting
Parameter Name: VENDOR_MESSAGE_SUPPORT
Terminate Received Messages Drop message TLPs and do not pass them to the application on RTRGT1. The
controller processes received messages and decodes the header before sending it to
the application logic on the System Information Interface (SII). By default, received
messages are dropped silently and not passed to the application on RTRGT1. To have
all decoded messages also sent to the application then do not set this parameter.
■ True: Discard message after decoding
■ False: Pass message TLP to application on RTRGT1
Note: When The "Receive Posted Queue Mode" is Bypass (RADM_P_QMODE_VC0
= 0x4), received messages are not dropped and are always passed to the application
irrespective of the setting of this parameter.
For more details, see "Routing of Received Messages to SII and optionally to
Application" in the "Message Reception" section in the Controller Operations chapter
of the Databook. Your application can override the value of this option at runtime by
writing to the 'Symbol Timer Register and Filter Mask Register 1'. These registers
allow you to override any decisions (regarding MSG routing) made at configuration
time by the FLT_DROP_MSG, DEFAULT_FILTER_MASK_1 and
DEFAULT_FILTER_MASK_2 configuration parameters.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: FLT_DROP_MSG
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PCI Express SW Controller Databook Device-Wide Optional Non-PCIe Config Parameters
Label Description
Receive Filter Rule Mask Default value for Filter Mask Register 1 ('Symbol Timer Register and Filter Mask
Register 1 Register 1'). This register is used to set the number of symbol times to wait between
transmitting SKP ordered sets, and also to mask the RADM Filtering and Error
Handling Rules. There are several mask bits used to turn off the filtering and error
handling rules. For more details, see the 'Receive Filtering' section in Controller
Operations chapter of the Databook.
Values: 0x0, ..., 0xffff
Default Value: (FLT_DROP_MSG ? 0 : 0x2000) | (CX_SRIOV_ENABLE ? 0x0008 : 0)
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_FILTER_MASK_1
Receive Filter Rule Mask Default value for 'Filter Mask Register 2'. This register is used to mask the RADM
Register 2 Filtering and Error Handling Rules. There are several mask bits used to turn off the
filtering and error handling rules. For more details, see the 'Receive Filtering' section in
Controller Operations chapter of the Databook.
Values: 0x0, ..., 0xffffffff
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_FILTER_MASK_2
Mask Completion Timeout Errors Mask detection of completion timeout errors. When selected, the controller will not
automatically report completion timeout errors. Your application must check for
completion timeouts and report them using the app_err_bus input signal on the
application error return interface. The 'Application Error Reporting'
(APP_RETURN_ERR_EN) parameter must be enabled to activate the application
error return interface.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: APP_RETURN_ERR_EN==1
Parameter Type: Feature Setting
Parameter Name: CPL_TIMEOUT_ERR_MASK
Synopsys, Inc.
Label Description
Enable Optional Checks Adds optional protocol checks including byte enable and flow control. Violations of the
byte enable check (Section 2.2.5 of the PCIe Specification) and the address/length
check (Section 2.2.7 of the PCIe Specification) will be treated as malformed TLPs.
Also, violations of the various flow control checks will result in a Flow Control Protocol
Error (FCPE). Flow control checks are described in Section 2.6.1 of the PCIe
Specification.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: ENABLE_OPTIONAL_CHECKS
Forward Errored-TLPs To Forward all incoming I/O or MEM requests with UR/CA/CRS status to your application.
Application By default, all such requests are dropped in store-and-forward mode (after
corresponding error reporting). A completion with UR status will be generated for
non-posted requests. For more details, see the description of the DEFAULT_TARGET
port logic register. See also the "ECRC Handling" and "Request TLP Routing Rules" in
the "Receive Routing" sections in the "Controller Operations" chapter of the Databook.
■ When you set this parameter, you should also set CX_MASK_UR_CA_4_TRGT1
■ This parameter sets the default value of the DEFAULT_TARGET field in the
MISC_CONTROL_1_OFF port logic register.
■ This parameter only applies to EP, DM in EP mode, or SW in USP mode. It does
not apply to a DSP.
Values:
■ Drop (0x0)
■ Forward (0x1)
Default Value: Drop
Enabled: TRGT1_POPULATE==1 && CC_DEVICE_TYPE!=CC_RC
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_TARGET
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PCI Express SW Controller Databook Device-Wide Optional Non-PCIe Config Parameters
Label Description
Suppress Errors for Forwarded Suppress error logging, Error Message generation, and CPL generation (for
Unsupported Requests non-posted requests) for requests TLPs with UR filtering status that you have chosen
to forward to the application (when you set the DEFAULT_TARGET field). For more
details, refer to the description of the UR_CA_MASK_4_TRGT1 field, "ECRC
Handling" and "Request TLP Routing Rules" in the "Receive Routing" section in the
"Controller Operations" chapter of the Databook.
■ This parameter sets the default value of the UR_CA_MASK_4_TRGT1 field in the
MISC_CONTROL_1_OFF port logic register.
■ You should set this if you have set the DEFAULT_TARGET parameter to '1'.
■ This parameter only applies to EP, or DM in EP mode. It does not apply to a DSP.
Values:
■ Report_UR_ERR (0x0)
■ Suppress_UR_ERR (0x1)
Default Value: Report_UR_ERR
Enabled: CC_DEVICE_TYPE!=CC_SW && CC_DEVICE_TYPE!=CC_RC
Parameter Type: Feature Setting
Parameter Name: CX_MASK_UR_CA_4_TRGT1
Indicate ECRC Error Using Passes the ECRC error notification to your application on the corresponding
Application I/O radm_<trgt1|cpl|byp>_ecrc_err output. Otherwise the controller will not assert the
output when it receives a TLP with an ECRC error.
■ This parameter is only used for queues configured in cut-through or
store-and-forward mode. It does not apply to bypass mode.
■ The default setting of this parameter is sufficient for most applications. For more
details, see the 'Error Detection For Received TLPs' section in the 'Controller Oper-
ations' chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_RADMQ_MODE==2 && AMBA_INTERFACE==0
Parameter Type: Feature Setting
Parameter Name: ECRC_ERR_PASS_THROUGH
Synopsys, Inc.
Label Description
General Options
AHB Endianness Mode Selection Selects Endianness for the AHB interface.
■ Little: Static Little Endian
■ Big: Static Big Endian
■ Dynamic: Pin Selectable
For more details, see 'Endianess Support' in the AHB section of the Databook.
Values:
■ Little (0)
■ Big (1)
■ Dynamic (2)
Default Value: Little
Enabled: AMBA_INTERFACE==1
Parameter Type: Feature Setting
Parameter Name: AHB_ENDIANNESS
Number Masters connected to Indicates the number of AHB masters that access the PCIe bridge slave. This is used
Slave to determine the number of internal bridge tags to support SPLIT_RETRY response.
For more details, see the AHB section of the Databook.
Note:AHB only.
Values: 4, 8, 16
Default Value: 4
Enabled: AHB_POPULATED && SLAVE_POPULATED && SPLIT_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CC_SLV_NUM_MASTERS
AHB Slave Response Mode Selects Normal or SPLIT-RETRY response for the AHB slave interface. When the
normal data slave is configured for SPLIT-RETRY response mode, the dedicated DBI
slave (if present) will still operate in NORMAL response mode by keeping
dbi_hready_resp low. For more details, see the AHB section of the Databook.
Note:There is no SPLIT-RETRY support for the DBI slave.
Values:
■ Normal (0)
■ SPLIT_RETRY (1)
Default Value: Normal
Enabled: AMBA_INTERFACE==1
Parameter Type: Feature Setting
Parameter Name: CC_RESPONSE_MODE
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PCI Express SW Controller Databook Advanced AXI Config / Advanced AHB Config Parameters
Label Description
AHB Slave Enables an immediate error response from the slave and DBI slave for an illegal AHB
access. For more details see the slv_hresp signal description in the Databook. If the
parameter RETURN_ERR_RESP is set then the bridge slave interface will perform
immediate error checking on the slave interface protocol signals (slv_hsize, slv_haddr,
slv_req_misc_info[25:22]) and return an ERROR status on slv_hresp immediately. It
will not transmit the outbound request TLP. The following two checks are done:
■ HSIZE check. For example, for a data width of 32-bits you will get an immediate
ERROR response if slv_hsize is not 0,1 or 2.
■ CFG & I/O transfers are checked for byte enable, hsize and address alignment.
For more details, see the "Zero-Byte Transfers Over the AHB Bridge (Flush
Semantics)2 section of the Databook. The recommended setting for this parameter is
"True".
Values:
■ False (0)
■ True (1)
Default Value: True
Enabled: AHB_POPULATED && SLAVE_POPULATED
Parameter Type: Feature Setting
Parameter Name: RETURN_ERR_RESP
AHB Master Burst Type Specifies whether the master interface will generate defined
(SINGLE/INCR4/INCR8/INCR16) or undefined length INCR bursts. For more details,
see the AHB section of the Databook. Value range:
■ 0 : Fixed (Defined Length)
■ 1 : Unspecified (Undefined Length)
Note:AHB only.
Values:
■ Fixed (0)
■ Unspecified (1)
Default Value: Unspecified
Enabled: MASTER_POPULATED && AHB_POPULATED
Parameter Type: Feature Setting
Parameter Name: CC_MSTR_BURST_TYPE
Synopsys, Inc.
Label Description
Master Request's DATA FIFO Specifies AHB Master Request Data FIFO Queue depth in words. The word width is
Queue Depth either CC_CORE_DATA_BUS_WD+1 or CC_MSTR_BUS_DATA_WIDTH+1. The
default value is sufficient for most applications.
Values: -2147483648, ..., 2147483647
Default Value: (MASTER_POPULATED) ? (MASTER_BUS_DATA_WIDTH >
PCIE_CORE_DATA_BUS_WD ?
((AMBA_DECOMPOSER_DEF_DEPTH_FACTOR*CC_MSTR_MTU)/(CC_MSTR_N
W*4)+2) :
((AMBA_DECOMPOSER_DEF_DEPTH_FACTOR*CC_MSTR_MTU)/(CX_NW*4)+2))
:4
Enabled: AHB_POPULATED && MASTER_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_RADMX_DECOMPOSER_DATAQ_DP
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PCI Express SW Controller Databook Advanced AXI Config / Advanced AXI Config Parameters
Label Description
DTIM Enable Enables the Root Ports Distributed Translation Interface Master (DTIM). The DTI
Master interfaces to an external Memory Management Unit (MMU). The MMU
provides address translation functions for the memory accessing PCIe AXI masters.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_DM) &&
MASTER_POPULATED
Parameter Type: Feature Setting
Parameter Name: CC_DTIM_ENABLE
Root Port ID The Root Port ID determines the upper 16-bits of the PCIe DTIM Stream ID (SID).
Values: 0x0, ..., 0xffff
Default Value: 0xffff
Enabled: CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_ROOT_PORT_ID
DTIM Translation Request This parameter indicates the maximum number of translation request tokens
Tokens Requested requested by the DTI Master, i.e. the maximum number of DTI-ATS translation
requests outstanding at any point in time. It is used to flow control the number of
outstanding translation requests sent by the DTI Master AXI4-Stream Master.
Values: 1, ..., 256
Default Value: 32
Enabled: CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_DTIM_NUM_TRANS_TOKENS_REQUESTED
DTIM Invalidate Request Tokens This parameter indicates the maximum number of invalidate request tokens granted by
Granted the DTI Master, i.e. the maximum number of DTI-ATS invalidate requests outstanding
at any point in time. It is used to determine the depth of the DTI Master AXI4-Stream
Slave Request queue.
Values: 4, 8, 16
Default Value: 16
Enabled: CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_DTIM_NUM_INV_TOKENS_GRANTED
Synopsys, Inc.
Label Description
DTIM PCIe Max Num The maximum number of outstanding PCIe invalidate requests that can be sent on the
Outstanding Invalidate Requests wire. The theoretical maximum is 32 requests per BDF.
Values: 16, 32, 64, 128, 256
Default Value: 32
Enabled: CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CC_DTIM_PCIE_MAX_NUM_INV_REQ
AXI Slave ID Width Specifies the width of the AXI slave interface ID bus. You can increase or decrease
CC_SLV_BUS_ID_WIDTH but your application master must never issue more than
CC_MAX_SLV_TAG different AXI ID's (for non-posted requests) because the bridge is
still only configured to handle CC_MAX_SLV_TAG different AXI ID's.
CC_SLV_BUS_ID_WIDTH sets the width of each entry in the Slave Response
Application-Tag Look Up Table, but it does not determine the number of available
TAGs. Default value is ceil [log2{CC_MAX_SLV_TAG}]. For more details, see
"Increasing Size of AXI Slave ID Bus" in the AXI chapter of the Databook.)
Values: 1, ..., 32
Default Value: [calc_log2 CC_MAX_SLV_TAG]
Enabled: SLAVE_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_SLV_BUS_ID_WIDTH
AXI Slave Multiple Requests per Enable support for multiple request per AXI ID on the AXI Slave
ID Enable Values: 0, 1
Default Value: 1
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Feature Setting
Parameter Name: CC_AXI_SLV_MULTIPLE_REQ_PER_ID_EN
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PCI Express SW Controller Databook Advanced AXI Config / Advanced AXI Config Parameters
Label Description
AXI Master Fixed Size Transfer Specifies that the AXI master interface will (under certain conditions) do a single
Enable bus-wide access when doing narrow read transfers rather than multiple byte-wide
accesses. When you set CC_MSTR_BURST_LEN to <
MASTER_BUS_DATA_WIDTH/8, then MSTR_FIXED_SIZE_ENABLE=1 because the
master cannot produce a sufficiently long burst of bytes. Therefore the master uses
dword access and not byte access for narrow or NCBE reads; which means that such
accesses to non-prefetchable memory might result in corrupting not-to-be-read data.
For more details on this and other restrictions, see the description of the
CC_MSTR_BURST_LEN parameter and the 'Supported AXI Transfer Sizes' section in
the AXI chapter of the Databook.
Values: 0, 1
Default Value: (((CC_MSTR_BURST_LEN==8) &&
(MASTER_BUS_DATA_WIDTH==64)) || (CC_MSTR_BURST_LEN <
MASTER_BUS_DATA_WIDTH/8)) ? 1 : 0
Enabled: (AXI_POPULATED && MASTER_POPULATED &&
!((CC_MSTR_BURST_LEN==8) && (MASTER_BUS_DATA_WIDTH==64)))
Parameter Type: Performance Setting
Parameter Name: MSTR_FIXED_SIZE_ENABLE
AXI Master Sub Bus Size Read Specifies that the master performs a narrow read transfer in one beat when the PCIe
Enable request size is a power of two and the AXI address is AXI transfer-size aligned. For
more details, see "Supported AXI Transfer Sizes" section of the Databook.
Note:AXI only.
Values: 0, 1
Default Value: 0
Enabled: AXI_POPULATED && MASTER_POPULATED
Parameter Type: Performance Setting
Parameter Name: MSTR_SUB_BUS_SIZE_READ_ENABLE
AXI Master Sub Bus Size Write Specifies that the master performs a narrow write transfer in one beat when the PCIe
Enable request size is a power of two and the AXI address is AXI transfer-size aligned. For
more details, see "Supported AXI Transfer Sizes" section of the Databook.
Note:AXI only.
Values: 0, 1
Default Value: 0
Enabled: AXI_POPULATED && MASTER_POPULATED
Parameter Type: Performance Setting
Parameter Name: MSTR_SUB_BUS_SIZE_WRITE_ENABLE
Synopsys, Inc.
Label Description
AXI Master NCBE Read Specifies that the master does not decompose NCBE read requests into a stream of
Decompose Disable single-byte requests. For more details, see 'Non Contiguous Byte Enable (NCBE)
Support' section of the Databook.
■ 0: Enables read NCBE decomposition into single-byte requests.
■ 1: Disables read NCBE decomposition into single-byte requests.
Values: 0, 1
Default Value: !MSTR_SUB_BUS_SIZE_READ_ENABLE &&
MSTR_FIXED_SIZE_ENABLE
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_AXI_NCBE_NODECOMP
AXI Master Read Response Enable support for interleaved read responses on the AXI Master
Interleaving Enable Values: 0, 1
Default Value: 1
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Feature Setting
Parameter Name: CX_AXI_MSTR_RD_RSP_INTERLEAVING_EN
Inbound Posted Tracker Enable Enables Inbound Posted Tracker. Allows P to pass P on multi-VC configuration. Allows
RO CPL and NP ordering disabling features.
Values: 0, 1
Default Value: CC_HP_MASTER
Enabled: AMBA_INTERFACE > 1
Parameter Type: Feature Setting
Parameter Name: CC_IB_WREQ_PTRK_EN
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / MSI/MSI-X Capability
Label Description
MSI/MSI-X
MSI IO Enable Include optional top-level ports for MSI, as listed in 'Message Signaled Interrupt (MSI)
Interface' section of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: MSI_CAP_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: MSI_IO
Default Multiple MSI Capability Default value for the Multiple Message Capable field in the 'MSI Control Register'.
Values: 0x0, ..., 0x5
Default Value: 0x0
Enabled: MSI_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_MULTI_MSI_CAPABLE
Synopsys, Inc.
Label Description
Default Extended Message Data Default value for the Extended Message Data Capable field in the 'MSI Control
for MSI Capability Register'.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: MSI_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_EXT_MSI_DATA_CAPABLE
Enable Integrated MSI-X Implements the MSI-X generation logic with the data/address table and PBA in the
Generation Module core. For more details, see the Interrupts section in the "Controller Operations" chapter
of the Databook. Not available when Extensible Virtual Function
(CX_EXTENSIBLE_VFUNC) is enabled.
Values: 0, 1
Default Value: 0
Enabled: (((CC_DEVICE_TYPE==CC_EP) || (CC_DEVICE_TYPE==CC_DM)) &&
!CX_EXTENSIBLE_VFUNC)
Parameter Name: MSIX_TABLE_EN
MSI-X IO Enable Include optional top-level ports for MSI-X, as listed in the 'MSI-X Interface' section of
the Databook. If included, the MSI-X ports are used only when the controller is
operating as an upstream port.
Values:
■ false (0x0)
■ true (0x1)
Default Value: MSIX_CAP_ENABLE
Enabled: MSIX_CAP_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: MSIX_IO
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / PCIe Capability Parameters
Label Description
PCIe Capability
CRS Software Visibility Default Default value for the CRS Software Visibility bit in the Root Capabilities Register.
Values: 0x0, 0x1
Default Value: 0x1
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_CRS_SW_VISIBILITY_CAP
ASPM Latencies
L0S Exit Latency Default value for the L0s Exit Latency field in the 'Link Capabilities Register'. M-PCIe
doesn't use this parameter.
Values:
■ Less than 64ns (0x0)
■ 64ns to less than 128ns (0x1)
■ 128ns to less than 256ns (0x2)
■ 256ns to less than 512ns (0x3)
■ 512ns to less than 1us (0x4)
■ 1us to less than 2us (0x5)
■ 2us to 4us (0x6)
■ More than 4us (0x7)
Default Value: [calc_cal_nfts ((CX_GEN2_SPEED==1) ? ((DEFAULT_GEN2_N_FTS
> CX_MAX_NFTS_TMP) ? DEFAULT_GEN2_N_FTS : CX_MAX_NFTS_TMP) :
CX_MAX_NFTS_TMP) ]
Enabled: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE ))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L0S_EXIT_LATENCY
Synopsys, Inc.
Label Description
L0S Exit Latency (Common Default value for the L0s Exit Latency field in the 'Link Capabilities Register', when
Clock) common clock is used. Common Clock operation cannot be fully enabled (through the
Common Clock Configuration field of the Link Control register) unless you observe the
following configuration parameter relationships:
■ CX_NFTS != CX_COMM_NFTS
■ DEFAULT_L0S_EXIT_LATENCY != DEFAULT_COMM_L0S_EXIT_LATENCY
■ DEFAULT_L1_EXIT_LATENCY != DEFAULT_COMM_L1_EXIT_LATENCY
M-PCIe doesn't use this parameter.
Values:
■ Less than 64ns (0x0)
■ 64ns to less than 128ns (0x1)
■ 128ns to less than 256ns (0x2)
■ 256ns to less than 512ns (0x3)
■ 512ns to less than 1us (0x4)
■ 1us to less than 2us (0x5)
■ 2us to 4us (0x6)
■ More than 4us (0x7)
Default Value: [calc_cal_nfts CX_COMM_NFTS ]
Enabled: SLOT_CLK_CONFIG && CX_CPCIE_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_COMM_L0S_EXIT_LATENCY
L1 Exit Latency Default value for the L1 Exit Latency field in the 'Link Capabilities Register'. This
parameter represents a characteristic of the PHY being used. It measures the total
time from when the controller initiates a transition from P1 to P0 until the PHY begins
providing valid receive data to the core. This parameter is for conventional PCIe mode
only.
Values:
■ Less than 1us (0x0)
■ 1us to less than 2us (0x1)
■ 2us to less than 4us (0x2)
■ 4us to less than 8us (0x3)
■ 8us to less than 16us (0x4)
■ 16us to less than 32us (0x5)
■ 32us to 64us (0x6)
■ More than 64us (0x7)
Default Value: 32us to 64us
Enabled: CX_S_CPCIE_MODE || CX_SEL_PHY_MODE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L1_EXIT_LATENCY
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / PCIe Capability Parameters
Label Description
L1 Exit Latency (common clk) Default value for the L1 Exit Latency field in the 'Link Capabilities Register', when
common clock is used. It measures the total time from when the controller initiates a
transition from P1 to P0 until the PHY begins providing valid receive data to the core.
Common Clock operation cannot be fully enabled (through the Common Clock
Configuration field of the Link Control register) unless you observe the following
configuration parameter relationships:
■ CX_NFTS != CX_COMM_NFTS
■ DEFAULT_L0S_EXIT_LATENCY != DEFAULT_COMM_L0S_EXIT_LATENCY
■ DEFAULT_L1_EXIT_LATENCY != DEFAULT_COMM_L1_EXIT_LATENCY
This parameter is for Conventional PCIe mode only.
Values:
■ Less than 1us (0x0)
■ 1us to less than 2us (0x1)
■ 2us to less than 4us (0x2)
■ 4us to less than 8us (0x3)
■ 8us to less than 16us (0x4)
■ 16us to less than 32us (0x5)
■ 32us to 64us (0x6)
■ More than 64us (0x7)
Default Value: 32us to 64us
Enabled: CX_CPCIE_ENABLE && SLOT_CLK_CONFIG
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_COMM_L1_EXIT_LATENCY
Use Platform Reference Clock Default value for the Slot Clock Configuration bit in the Link Status register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: SLOT_CLK_CONFIG
Synopsys, Inc.
Label Description
Active State Link PM Support Default value for the Active State Link PM Support field in the Link Capabilities
register. When SRIS is supported, L0s is not supported and must not be advertised in
the Capability register. M-PCIe doesn't use the L0s state, and therefore bit[0] of the
Active State Link PM Support field is hardwired to "0" even when you select any value
here.
Values:
■ No ASPM Support (0)
■ L0s Supported (1)
■ L1 Supported (2)
■ L0s and L1 Supported (3)
Default Value: ((CX_SRIS_SUPPORT && !CX_ADM_ADAPTOR_ENABLE)? 2 :
(CX_ADM_ADAPTOR_ENABLE)) ? 0 : 3
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: AS_LINK_PM_SUPT
Endpoint L0s Acceptable Latency Default value for the Endpoint L0s Acceptable Latency field in the 'Device Capabilities
Register'. This should be >= DEFAULT_L0S_EXIT_LATENCY (or
DEFAULT_COMM_L0S_EXIT_LATENCY), and you must ensure that there is sufficient
buffering in your EP for this latency setting. M-PCIe doesn't use this feature.
Values:
■ Less than 64ns (0x0)
■ 64ns to less than 128ns (0x1)
■ 128ns to less than 256ns (0x2)
■ 256ns to less than 512ns (0x3)
■ 512ns to less than 1us (0x4)
■ 1us to less than 2us (0x5)
■ 2us to 4us (0x6)
■ More than 4us (0x7)
Default Value: More than 4us
Enabled: CX_CPCIE_ENABLE && CC_DEVICE_TYPE!=CC_RC &&
CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_EP_L0S_ACCPT_LATENCY
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Label Description
Endpoint L1 Acceptable Latency Default value for the Endpoint L1 Acceptable Latency field in the 'Device Capabilities
Register.' This should be >= DEFAULT_L1_EXIT_LATENCY (or
DEFAULT_COMM_L1_EXIT_LATENCY), and you must ensure that there is sufficient
buffering in your EP for this latency setting. This parameter is for conventional PCIe
mode only.
Values:
■ Less than 1us (0x0)
■ 1us to less than 2us (0x1)
■ 2us to less than 4us (0x2)
■ 4us to less than 8us (0x3)
■ 8us to less than 16us (0x4)
■ 16us to less than 32us (0x5)
■ 32us to 64us (0x6)
■ More than 64us (0x7)
Default Value: More than 64us
Enabled: CX_CPCIE_ENABLE && CC_DEVICE_TYPE!=CC_RC &&
CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_EP_L1_ACCPT_LATENCY
ASPM Optionality Compliance Software uses this bit to determine whether to enable ASPM or whether to run ASPM
compliance tests
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: ASPM_OPTIONALITY_COMPLIANCE
Misc
Port Number Default value for the Port Number field in the Link Capabilities Register.
Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: PORT_NUM
Synopsys, Inc.
Label Description
RCB Support Support the ability of configuration software to indicate the Read Completion Boundary
value.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: CC_DEVICE_TYPE==CC_EP || CC_DEVICE_TYPE==CC_DM
Parameter Type: Register Default Setting
Parameter Name: CX_RCB_SUPPORT
Slot Control
Physical Slot Number Default value for the Physical Slot Number field in the Slot Capabilities Register.
Values: 0x0, ..., 0x1fff
Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_PHY_SLOT_NUM
Slot Power Limit Scale Default value for the Slot Power Limit Scale field in the Slot Capabilities Register.
Values:
■ "1.0x" (0x0)
■ "0.1x" (0x1)
■ "0.01x" (0x2)
■ "0.001x" (0x3)
Default Value: "1.0x"
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SET_SLOT_PWR_LIMIT_SCALE
Slot Power Limit Value Default value for the Slot Power Limit Value field in the Slot Capabilities Register.
Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SET_SLOT_PWR_LIMIT_VAL
Slot is Hot-Plug Capable Default value for the Hot-Plug Capable bit in the Slot Capabilities Register. When set
indicates that this slot is capable of supporting
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_HP_CAPABLE
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Label Description
Slot Support Hot-Plug Surprise Default value for the Hot-Plug Surprise bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_HP_SURPRISE
Disable Hot-Plug Software Default value for the No Command Complete Support bit in the Slot Capabilities
Notification Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_NO_CC_SUPPORT
Electromechanical Interlock Default value for the Electromechanical Interlock Present bit in the Slot Capabilities
Implemented Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_EML_PRESENT
Slot Power Indicator Present Default value for the Power Indicator Present bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_PWR_IND_PRESENT
Synopsys, Inc.
Label Description
Slot Attention Indicator Present Default value for the Attention Indicator Present bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_ATTEN_IND_PRESENT
Slot MRL Sensor Present Default value for the MRL Sensor Present bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_MRL_SENSOR_PRESENT
Slot Power Controller Present Default value for the Power Controller Present bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_PWR_CTRL_PRESENT
Slot Attention Button Present Default value for the Attention Button Present bit in the Slot Capabilities Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_ATTEN_BUTTON_PRESENT
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Label Description
Surprise Down
Surprise Down Error Reporting Adds optional protocol check capability for Surprise Down Error Reporting.
Enabled Downstream Ports that are Surprise Down Error Reporting Capable (Section 7.8.6 of
the PCIe Specification) must treat this transition from DL_Active to DL_Inactive as a
Surprise Down error, except in the cases presented in (Section 3.2.1 of the PCIe
Specification) where this error detection is blocked.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Feature Setting
Parameter Name: SURPRISE_LINK_DOWN_SUPPORTED
Clock PM
Clock PM Support Default value for the Clock Power Management bit in the Link Capabilities Register.
Values: 0x0, 0x1
Default Value: 0x0
Enabled: (CX_PIPE_VER==0 && CX_L1_SUBSTATES_ENABLE==0) ? 0 : 1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_CLK_PM_CAP
Synopsys, Inc.
Label Description
PF Extended Capabilities
Advanced Error Reporting (AER) Support PCI Express Advanced Error Reporting. Required if ECRC or ARI are
Enable enabled. If you want to disable this parameter, you must first disable
CX_ECRC_ENABLE and CX_ARI_ENABLE.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: CX_ECRC_ENABLE==0 && CX_ARI_ENABLE==0
Parameter Type: Feature Setting
Parameter Name: AER_ENABLE
+ Device Serial Number (1st DW) Specifies the first 32 bits of the device serial number
Values: 0x0, ..., 0xffffffff
Default Value: 0x0
Enabled: SERIAL_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_SN_DW1
+ Device Serial Number (2nd Specifies the second 32 bits of the device serial number
DW) Values: 0x0, ..., 0xffffffff
Default Value: 0x0
Enabled: SERIAL_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_SN_DW2
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Label Description
+ Power Budget System Default value for the System Allocated bit in the Power Budget Capability register.
Allocated Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: PWR_BUDGET_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_PWR_BUDGET_SYS_ALLOC
Address Translation Services Support PCI-SIG ATS (address translation services) and allow your application to
Support use/set the Address Type (AT) field and No Write (NW) fields of the TLP header. For
more details, see the 'PCI-SIG Address Translation Services (ATS)' section of the
Databook. For generic application<->system address translation, see the 'Address
Translation Services (ATS)' section of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: CC_DTIM_ENABLE
Enabled: (CC_DEVICE_TYPE!=CC_SW) && !CC_DTIM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ATS_ENABLE
Synopsys, Inc.
Label Description
Access Control Services Support Support PCI-SIG ACS (Access Control Services) and allow your application to use/set
the access control mechanism. For more details, see the Access Control Services
chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CC_DEVICE_TYPE!=CC_EP) || (CX_SRIOV_ENABLE || (CX_NFUNC >
1) ))
Parameter Type: Feature Setting
Parameter Name: CX_ACS_ENABLE
Latency Tolerance Reporting Support the Latency Tolerance Reporting Mechanism. For more details see the
(LTR) "Messages" section in the "Controller Operations" chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting.
Parameter Name: CX_LTR_M_ENABLE
TLP Processing Hints Support TLP Processing Hints. For more details, see the TLP Processing Hints
section in the Core Operations chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_SW
Parameter Type: Feature Setting.
Parameter Name: CX_TPH_ENABLE
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Label Description
Dynamic Power Allocation (DPA) Function:Support the Dynamic Power Allocation (DPA) capability.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ( (CC_DEVICE_TYPE!=CC_RC) && (CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Feature Setting
Parameter Name: CX_DPA_ENABLE
+ DPA Maximum Substate Function:The default value of the maximum substate number which is the total
number of supported substates minus one. A value of 0 indicates support for one
substate. This value represents the maximum configurable value of the Substate_Max
field in the DPA Capability register. A write to this register field through the DBI will not
be able to alter this to a larger value.
Values: 0x0, ..., 0x1f
Default Value: 0x1f
Enabled: ((CC_DEVICE_TYPE!=CC_RC) && (CC_DEVICE_TYPE!=CC_SW) &&
CX_DPA_ENABLE)
Parameter Type: Feature Setting
Parameter Name: DEFAULT_DPA_SUBSTATE_MAX
ARI Forwarding When set, Alternate Routing ID (ARI) Forwarding is supported and the ARI Forwarding
Supported field in the PCIe Device Capabilities 2 Register is set.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Feature Setting
Parameter Name: CX_ARI_FWD_CAP
Synopsys, Inc.
Label Description
Number of Virtual Channels The number of Virtual Channels (VCs) to be supported. The controller supports up to
eight VCs.
Values: 1, 2, 3, 4, 5, 6, 7, 8
Default Value: 1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_NVC
Virtual Channel Support Support PCIe virtual channel Capability (required if there are multiple VCs).
Values:
■ false (0x0)
■ true (0x1)
Default Value: (CX_NVC==1) ? 0 : 1
Enabled: ((CX_NVC==1))
Parameter Type: Feature Setting
Parameter Name: VC_ENABLE
VC Arbitration Capability Default value for the VC Arbitration Capability field in the Port VC Capability Register
2.
Values: 0x0, ..., 0xf
Default Value: 0x1
Enabled: ((VC_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_VC_ARB_32
Low Priority Extended VC Count Default value for the Low Priority Extended VC Count field in the Port VC Capability
Register 1.
Values: 0x0, ..., CX_NVC
Default Value: 0x0
Enabled: (((VC_ENABLE==1)))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_LOW_PRI_EXT_VC_CNT
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Label Description
Slot ID Capability
Slot First In Chassis Default value for the "First In Chassis" field in the Slot Numbering Capabilities
Register.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: ((SLOT_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: FIRST_IN_CHASSIS
Slot Number Default value for the "Add-In Card Slots Provided" field in the Slot Numbering
Capabilities Register.
Values: 0x0, ..., 0x1f
Default Value: 0x0
Enabled: SLOT_CAP_ENABLE==1
Parameter Name: SLOT_NUM
Synopsys, Inc.
Label Description
32-bit AtomicOp Completer Support Completion of Atomic Ops with a 32-bit operand size.
Support Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_ATOMIC_ENABLE
Enabled: !AMBA_POPULATED && CX_ATOMIC_ENABLE
Parameter Type: Feature Setting.
Parameter Name: CX_ATOMIC_32_CPL_EN
64-bit AtomicOp Completer Support Completion of Atomic Ops with a 64-bit operand size.
Support Values:
■ false (0x0)
■ true (0x1)
Default Value: CX_ATOMIC_ENABLE
Enabled: !AMBA_POPULATED && CX_ATOMIC_ENABLE
Parameter Type: Feature Setting.
Parameter Name: CX_ATOMIC_64_CPL_EN
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Label Description
128-bit CAS Completer Support Support Completion of Compare and Swap Atomic Ops with a 128-bit operand size.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: !AMBA_POPULATED && CX_ATOMIC_ENABLE
Parameter Type: Feature Setting.
Parameter Name: CX_ATOMIC_128_CAS_EN
Synopsys, Inc.
Label Description
General Options
Support Immediate Readiness Enable Immediate Readiness support in the core. When you set the Immediate
Readiness bit in the PCI header Status Register, the function is configuration-ready.
Software is exempt from all requirements to delay configuration accesses following any
type of reset or exit from low-power states. The function will always respond to a valid
configuration request targeting the function with a completion indicating successful
completion status, and not CRS. For more details, see Readiness Notifications in the
Controller Operations chapter of the Databook.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RN_IMM_EN
RTR Capability Supported Enable Readiness Time Reporting support in the core. RTR provides an optional
mechanism for describing the time required for a device or function to become
configuration-ready. Software is permitted to issue requests to the device or function
(following any type of reset or exit from low-power states) after waiting for the time
advertised in this capability and need not wait for the (longer) times required
elsewhere. The function will then respond to a valid configuration request targeting the
function with a completion indicating successful completion status, and not CRS. For
more details, see Readiness Notifications in the Controller Operations chapter of the
Databook.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RN_RTR_EN
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / Readiness Support Options
Label Description
FRS/DRS Options
Function Readiness Status (FRS) Enable FRS support in the core. FRS provides an optional mechanism for messaging
Support the host software when a function has become configuration-ready. The controller
autonomously sends a Vendor-Defined Type 1 Message (VDM) with no payload
following reset or exit from low-power states. Software is permitted to issue requests to
the function (following any type of reset or exit from low-power states) after receiving
an FRS message from this function and need not wait for the (longer) times required
elsewhere. The function will then respond to a valid configuration request targeting the
function with a completion indicating successful completion status, and not CRS. For
more details, see Readiness Notifications in the Controller Operations chapter of the
Databook.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RN_FRS_SUPPORTED
Device Readiness Status (DRS) Enable DRS support in the core. DRS provides an optional mechanism for messaging
Support the host software when a device has become configuration-ready. The controller
autonomously sends a Vendor-Defined Type 1 Message (VDM) with no payload
following reset or exit from low-power states. Software is permitted to issue requests to
the device (following any type of reset or exit from low-power states) after receiving an
DRS message from this device and need not wait for the (longer) times required
elsewhere. The device will then respond to a valid configuration request targeting the
device with a completion indicating successful completion status, and not CRS. For
more details, see Readiness Notifications in the Controller Operations chapter of the
Databook.
Values: 0, 1
Default Value: CX_RN_FRS_SUPPORTED==1
Enabled: CX_RN_FRS_SUPPORTED==0
Parameter Type: Feature Setting
Parameter Name: CX_RN_DRS_SUPPORTED
FRS Queue Max Depth Sets the maximum FRS queue depth in root ports (Must be at least 4 for greater than
128 bit Datapath Width).
Values: 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800
Default Value: 0x8
Enabled: (CX_RN_FRS_SUPPORTED==1 && (CC_DEVICE_TYPE==CC_RC ||
CC_DEVICE_TYPE==CC_DM))
Parameter Type: Performance Setting
Parameter Name: CX_RN_FRS_QUEUE_MAX_DEPTH
Synopsys, Inc.
Label Description
FRS Queue Interrupt Message Default for the FRS_INT_MESSAGE_NUMBER field in the FRSQ_CAP_OFF register.
Number Values: 0, ..., 31
Default Value: 0
Enabled: (CX_RN_FRS_SUPPORTED==1 && (CC_DEVICE_TYPE==CC_RC ||
CC_DEVICE_TYPE==CC_DM))
Parameter Type: Register Default Setting
Parameter Name: CX_RN_FRS_INT_MSG_NUM
FRS Queue Interrupt Enable Default for the FRS_INTERRUPT_ENABLE field in the
FRSQ_CONTROL_FRSQ_STATUS_OFF register.
Values: 0, 1
Default Value: 0
Enabled: (CX_RN_FRS_SUPPORTED==1 && (CC_DEVICE_TYPE==CC_RC ||
CC_DEVICE_TYPE==CC_DM))
Parameter Type: Register Default Setting
Parameter Name: CX_RN_FRS_INT_ENABLE
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Label Description
Lightweight Notification Enable When enabled, the controller supports the Lightweight Notification capability.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (CC_DEVICE_TYPE!=CC_SW && (AMBA_INTERFACE!=1) &&
CX_RADMQ_MODE==2)
Parameter Name: CX_LN_ENABLE
Synopsys, Inc.
6.19 Device-Wide PCIe Features and Capabilities Config / Other Optional PCIe
Features Parameters
Table 6-19 Device-Wide PCIe Features and Capabilities Config / Other Optional PCIe Features Parameters
Label Description
ID Based Ordering Support ID Based Ordering (IDO). The controller does not perform any additional
ordering when ID-based ordering (IDO) is enabled. Your application is expected to do
any IDO.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (CC_DEVICE_TYPE!=CC_SW) && !AHB_POPULATED
Parameter Type: Feature Setting.
Parameter Name: CX_IDO_ENABLE
Completion Timeout Ranges Support Completion Timeout Ranges. For more details, see 'Completion Timeout
Enable Range' section in the 'Controller Operations' chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Feature Setting
Parameter Name: CX_CPL_TO_RANGES_ENABLE
Vital Product Data (VPD) Include Vital Product Data (VPD) capability structure
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: VPD_CAP_ENABLE
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / Other Optional PCIe Features
Label Description
Optimized Buffer Flush/Fill Type Indicates if the device supports Optimized Buffer Flush/Fill (OBFF) using the WAKE#
Supported signal, messages or both.
Values:
■ Not Supported (0)
■ OBFF Messages Only (1)
■ WAKE# Signalling Only (2)
■ WAKE# Signalling and OBFF Messages (3)
Default Value: Not Supported
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_OBFF_SUPPORT
Enable Crosslink Support Enables support for the controller to negotiate a crosslink, with a switch from EP to RC
and RC to EP. When a port negotiates a crosslink connection, the port changes its
behavior from a downstream port to an upstream port and visa versa. Crosslink is
supported only in DM and SW cores because these products support both upstream
and downstream ports. For more details, see Databook. M-PCIe doesn't support this
feature.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (CX_CPCIE_ENABLE && (CC_DEVICE_TYPE==CC_DM ||
CC_DEVICE_TYPE==CC_SW))
Parameter Type: Feature Setting
Parameter Name: CX_CROSSLINK_ENABLE
Peer-to-peer Support Support peer-to-peer transactions in RC. For more details, see 'Peer-to-Peer Support
(P2P)' in the Databook.
Values: 0, 1
Default Value: 0
Enabled: ((CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_DM) &&
(AMBA_INTERFACE==0) && (CC_DMA_ENABLE==0))
Parameter Type: Feature Setting
Parameter Name: CX_P2P_ENABLE
SRIS Support When enabled, the controller implements logic for Separate Reference Clocks with
Independent SSC (SRIS). Gen5 port must support SRIS/non-SRIS mode selection
mechanism.
Values:
■ false (0)
■ true (1)
Default Value: CX_MAX_PCIE_SPEED >= 5
Enabled: (!(CX_PCIE_MODE == SINGLE_MPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_SRIS_SUPPORT
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Label Description
Support SR-IOV SR-IOV Capability enable. For more details, see the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CC_DEVICE_TYPE==CC_EP || CC_DEVICE_TYPE==CC_DM))
Parameter Type: Feature Setting
Parameter Name: CX_SRIOV_ENABLE
Function Level Reset Support Enables controller support for Function Level Reset (FLR). For more details, see the
Databook.
Values:
■ false (0)
■ true (1)
Default Value: CX_SRIOV_ENABLE
Enabled: ((CC_DEVICE_TYPE==CC_EP || CC_DEVICE_TYPE==CC_DM) &&
!CX_SRIOV_ENABLE)
Parameter Type: Feature Setting
Parameter Name: CX_FLR_ENABLE
Number of Virtual Functions. Read-only parameter that specifies the total number of virtual functions supported by
the controller. When CX_EXTENSIBLE_VFUNC=1, it is the total of both internal VFs
and external VFs.
Values: 2, ..., SNPS_RSVDPARAM_24
Default Value: Sum(CX_MAX_VF_i, i=0..CX_NFUNC-1)
Enabled: false
Parameter Name: CX_NVFUNC
External Virtual Function Enables the Extensible Virtual function which allows you to implement VFs capability
Registers registers in your application logic. For more details, see the SRIOV section in the
Controller Operations chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_EXTENSIBLE_VFUNC
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / SR-IOV Related Features
Label Description
Number of (Internal) Virtual The total number of VF registers implemented internally in the controller.
Functions. ■ Normally, this is a read-only parameter that specifies the total number of virtual
functions supported by the controller.
■ When CX_EXTENSIBLE_VFUNC=1, it is a writable parameter that specifies the
total number of virtual functions implemented internally in the controller. Internal
VFs are mapped from the lowest function number; that is, PF0_VF1.
For more details, see the SR-IOV section in the Controller Operations chapter of the
Databook.
Values: 0, ..., SNPS_RSVDPARAM_23
Default Value: CX_EXTENSIBLE_VFUNC ? 0 : CX_NVFUNC
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_INTERNAL_NVFUNC
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Label Description
VF Capabilities/Features
Virtual Function Dependency Enables support for VF dependency link. Valid only if CX_NFUNC >1.
Link Support Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && (CX_NFUNC > 1)
Parameter Type: Feature Setting
Parameter Name: CX_VF_DEPENDENCY_LINK_SUPP
VF Power Management Enable Power Management Capability for virtual functions. Not available if Extensible
Capability Virtual Function (CX_EXTENSIBLE_VFUNC) is enabled.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && !CX_EXTENSIBLE_VFUNC
Parameter Type: Feature Setting
Parameter Name: VF_PM_CAP_ENABLE
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities
Label Description
VF TPH Steering Tag Table Size TLP Processing Hints Steering Tag Table Size for virtual functions.
■ All Virtual functions have the same table size set by this parameter.
■ Software reads this field to determine the ST Table Size N, which is encoded as
N-1. For example, a returned value of 00000000011 indicates a table size of 4.
■ There is an upper limit of 64 entries when the ST Table is located in the TPH
Requester Capability structure.
Values: 1, ..., 2048
Default Value: 1
Enabled: (VF_TPH_ENABLE && (TPH_ST_TABLE_LOC_0 != 0))
Parameter Type: Feature Setting
Parameter Name: VF_TPH_ST_TABLE_SIZE
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Label Description
VF TPH Steering Tag Table Size TLP Processing Hints Steering Tag Table Size for external virtual functions.
■ All Virtual functions have the same table size set by this parameter.
■ Software reads this field to determine the ST Table Size N, which is encoded as
N-1. For example, a returned value of 00000000011 indicates a table size of 4.
■ There is an upper limit of 64 entries when the ST Table is located in the TPH
Requester Capability structure.
Values: 1, ..., 2048
Default Value: 1
Enabled: (EXT_VF_TPH_ENABLE && (TPH_ST_TABLE_LOC_0 != 0))
Parameter Type: Feature Setting
Parameter Name: EXT_VF_TPH_ST_TABLE_SIZE
VF MSI/MSI-X Capabilities
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities
Label Description
VF MSI-X Table BIR (PF#i) Default value for the Table BAR Indicator Register (BIR) field in the VF MSI-X Table
(for n = 0; n <= CX_NFUNC-1) Offset and BIR Register. Indicates which BAR is used to map the MSI-X Table into
memory space.
Values:
■ BAR0 (0x0)
■ BAR1 (0x1)
■ BAR2 (0x2)
■ BAR3 (0x3)
■ BAR4 (0x4)
■ BAR5 (0x5)
Default Value: BAR0
Enabled: VF_MSIX_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_MSIX_TABLE_BIR_n
VF MSI-X Table Offset (PF#i) Default value for the Table Offset field in the VF MSI-X Table Offset and BIR Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1fffffff
Default Value: 0x0
Enabled: ((VF_MSIX_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: VF_MSIX_TABLE_OFFSET_n
VF MSI-X PBA BIR (PF#i) Default value for the Pending Bit Array (PBA) BAR Indicator Register (BIR) field in the
(for n = 0; n <= CX_NFUNC-1) VF MSI-X PBA Offset and BIR Register. Indicates which BAR is used to map the
MSI-X PBA into memory space.
Values:
■ BAR0 (0x0)
■ BAR1 (0x1)
■ BAR2 (0x2)
■ BAR3 (0x3)
■ BAR4 (0x4)
■ BAR5 (0x5)
Default Value: BAR0
Enabled: VF_MSIX_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_MSIX_PBA_BIR_n
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Label Description
VF MSI-X PBA Offset (PF#i) Default value for the PBA Offset field in the VF MSI-X PBA Offset and BIR Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1fffffff
Default Value: 0x0
Enabled: ((VF_MSIX_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: VF_MSIX_PBA_OFFSET_n
VF Readiness Capabilities
VF Immediate Readiness Enable Immediate Readiness support for VFs in the core. When you set the
Support Immediate Readiness bit in the PCI header Status Register, the function is
configuration-ready. Software is exempt from all requirements to delay configuration
accesses following any type of reset or exit from low-power states. The function will
always respond to a valid configuration request targeting the function with a
completion indicating successful completion status, and not CRS. For more details,
see Readiness Notifications in the Controller Operations chapter of the Databook.
Values: 0, 1
Default Value: CX_RN_IMM_EN==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Enabled: CX_RN_IMM_EN==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: VF_IMM_ENABLE
VF Lightweight Notification When enabled, controller supports Lightweight Notification Capability for VFs.
Enable Values: 0, 1
Default Value: CX_LN_ENABLE==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Enabled: CX_LN_ENABLE==1 && CX_SRIOV_ENABLE==1 &&
INTERNAL_VF_ENABLE==1
Parameter Name: VF_LN_ENABLE
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities
Label Description
VF Features
VF Stride Always 1 Enable logic optimization when you never use a VF stride greater than one. For more
details, see the Single Root I/O Virtualization (SR-IOV) section in the Databook. You
should enable this parameter when possible to save gates and ease timing closure.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE
Parameter Type: Performance Setting
Parameter Name: CX_VF_STRIDE_ALWAYS_ONE
Programmable VF allocation Enable programmable allocation of VFs to PFs. For more details, see the
Programmable Virtual Function Allocation section in the Databook. You should disable
this parameter when you do not need it, to save gates and ease timing closure.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: DYNAMIC_VF_ENABLE
External VF RTR Capability Readiness Time Reporting Capability external for virtual functions.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC && CX_RN_RTR_EN
Parameter Type: Feature Setting
Parameter Name: EXT_VF_RTR_ENABLE
External VF ACS Capability Enable Access Control Services for external virtual functions. This parameter cannot
be enabled in this version.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: EXT_VF_ACS_ENABLE
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Label Description
External VF Immediate Readiness Time Reporting Capability for external virtual functions.
Readiness Capability Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_SRIOV_ENABLE && CX_EXTENSIBLE_VFUNC && CX_RN_IMM_EN
Parameter Type: Feature Setting
Parameter Name: EXT_VF_IMM_ENABLE
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / VF Extended Capabilities
Label Description
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Label Description
L1 Substates Capability
L1 Substates Support Enable support for L1 substates. For more details, see the Power Management section
of the Databook. M-PCIe doesn't support this feature.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CX_S_CPCIE_MODE || CX_SEL_PHY_MODE ))
Parameter Type: Feature Setting
Parameter Name: CX_L1_SUBSTATES_ENABLE
Configure Other Register Select here if you want to configure the defaults for the L1 substates capability register.
Defaults An extra window will appear under this page. To access it, click the plus/minus symbol
in the hierarchy view on the left panel. This is optional but not usually recommended.
You can also change these register defaults using the DBI before (or after) the link
comes up.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_L1_SUBSTATES_DEFAULTS_VISIBLE
L1 Substate signaling This is read-only parameter to indicate whether the core uses mac_phy_powerdown
signal for L1-Substate transition or uses legacy side-band interface signals. You can
change the setting by CX_PIPE_VER parameter located in "Basic Feature Config".
Values:
■ Side band (0)
■ PowerDown (1)
Default Value: CX_PIPE_VER>=1
Enabled: SNPS_RSVDPARAM_25
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_SUPPORT
Bypass Asynchronous Power Bypass the handshake between phystatus and AsyncPowerChangeAck in P1.1 or
Change Handshake P1.2 powerdown state when your PHY vendor does not support it.
Values: 0, 1
Default Value: 0
Enabled: CX_PIPE43_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_ASYNC_HS_BYPASS
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / L1 Substates/L1.CPM
Label Description
P1.CPM Encoding Powerdown state encoding on the mac_phy_powerdown[3:0] output for P1.CPM.
Contact your PHY vendor for the value that you should use.
Values: 0x0, ..., 0xf
Default Value: 0x4
Enabled: CX_PIPE43_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P1CPM_ENCODING
P1.1 Encoding Powerdown state encoding on the mac_phy_powerdown[3:0] output for P1.1. Contact
your PHY vendor for the value that you should use.
Values: 0x4, ..., 0xf
Default Value: 0x5
Enabled: CX_PIPE43_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P1_1_ENCODING
P1.2 Encoding Powerdown state encoding on the mac_phy_powerdown[3:0] output for P1.2. Contact
your PHY vendor for the value that you should use.
Values: 0x4, ..., 0xf
Default Value: 0x6
Enabled: CX_PIPE43_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P1_2_ENCODING
P1.CPM Entry Sequence Specifies P1.CPM Entry sequence. Contact your PHY vendor for the sequence that
you should use.
■ 0: P0 -> P1 -> P1.CPM
■ 1: P0 -> P1.CPM
Values: 0, 1
Default Value: 0
Enabled: CX_PIPE43_SUPPORT
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P0_P1CPM
P1.1 and P1.2 Exit Sequence Specifies P1.1 and P1.2 Exit sequence. Contact your PHY vendor for the sequence
that you should use.
■ 0: P1.1(P1.2) -> P1
■ 1: P1.1(P1.2) -> P1.CPM -> P1
Values: 0, 1
Default Value: 0
Enabled: CX_PIPE43_SUPPORT && CX_L1_SUBSTATES_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P1CPM_P1
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Label Description
Default Aux Clock Frequency The frequency (in MHz) of the aux_clk that is supplied by the application during low
[MHz] power states. This parameter is used to set the default value of the Auxiliary Clock
Frequency Control Port Logic Register
Values: 1, ..., 1000
Default Value: 10
Enabled: CX_L1_SUBSTATES_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_AUX_CLK_FREQ
Default Port Common Mode Default value of the Port Common_Mode_Restore_Time field in the L1 Substates
Restore Time [us] Capability register. For downstream ports, it is also the default value of the Common
Mode Restore Time field in the L1 Substates Control 1 register.
Values: 0, ..., 255
Default Value: 10
Enabled: CX_L1_SUBSTATES_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L1SUB_PORT_T_COMM_MODE
Default Port Power ON Time Default value of the Port T_POWER_ON Scale field in the L1 Substates Capability
Scale register.
Values:
■ 2 us (0x0)
■ 10 us (0x1)
■ 100 us (0x2)
Default Value: 2 us
Enabled: CX_L1_SUBSTATES_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L1SUB_PORT_T_POWER_ON_SCALE
Default Port Power ON Time Default value of the Port T_POWER_ON Value field in the L1 Substates Capability
Value register.
Values: 0, ..., 31
Default Value: 5
Enabled: CX_L1_SUBSTATES_ENABLE
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_L1SUB_PORT_T_POWER_ON_VALUE
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support
6.24 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support
Parameters
Table 6-24 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support Parameters
Label Description
Number of Prefixes The number of TLP Prefixes that the controller supports. When CX_NPRFX is greater
than zero, then each function in the PCIe controller supports the extended FMT field in
TLP prefixes and headers. When CX_NPRFX is zero, then the extended FMT field is
not supported. Range: 0-8 (excluding 1,2,3 as a switch support that supports prefixes
must support up to four End-End TLP Prefixes).
Values: 0, 1, 2, 3, 4, 5, 6, 7
Default Value: 0
Enabled: Always
Parameter Type: Feature Setting.
Parameter Name: CX_NPRFX
Support PRG PASID Prefix Any PRG Response Message with PASID capability for untranslated addresses, is
required to have a PASID TLP Prefix.
Values: 0, 1
Default Value: 0
Enabled: CX_PASID_ENABLE
Parameter Type: Feature Setting.
Parameter Name: CX_PRG_PASID_REQUIRED
Configure Other Register Select here if you want to configure the defaults for the PASID capability register. An
Defaults extra window will appear under this page. To access it, click the plus/minus symbol in
the hierarchy view on the left panel. This is optional but not usually recommended. You
can also change these register defaults using the DBI before (or after) the link comes
up.
Values: 0, 1
Default Value: 0
Enabled: (CX_PASID_ENABLE && (CC_DEVICE_TYPE!=CC_RC) &&
(CC_DEVICE_TYPE!=CC_SW))
Parameter Name: CX_PASID_DEFAULTS_VISIBLE
Synopsys, Inc.
6.25 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support /
PASID Capability Register Defaults Parameters
Table 6-25 Device-Wide PCIe Features and Capabilities Config / TLP Prefix Support / PASID Capability
Register Defaults Parameters
Label Description
Default Max PASID Width The default value for the width of the PASID field supported by the endpoint.
■ n indicates support for PASID values 0 through (2^n)-1.
■ 0 indicates support for a single PASID.
■ 20 indicates support for all PASID values (20 bits).
Values: 0, ..., 20
Default Value: 0
Enabled: (CX_PASID_ENABLE && (CC_DEVICE_TYPE!=CC_RC) &&
(CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_MAX_PASID_WDTH
Default Privileged Mode Support The default value for Privileged Mode Supported.
■ 1: Endpoint supports operating in Privileged and Non-Privileged modes, and
supports sending requests that have the Privileged Mode Requested bit Set.
■ 0: Endpoint will never Set the Privileged Mode Requested bit.
Values: 0, 1
Default Value: 1
Enabled: (CX_PASID_ENABLE && (CC_DEVICE_TYPE!=CC_RC) &&
(CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_PRVLGD_MODE_SPPRT
Default Execute Permission The default value for Execute Permission Supported.
Support ■ 1: Endpoint supports sending TLPs that have the Execute Requested bit Set.
■ 0: Endpoint will never Set the Execute Requested bit.
Values: 0, 1
Default Value: 1
Enabled: (CX_PASID_ENABLE && (CC_DEVICE_TYPE!=CC_RC) &&
(CC_DEVICE_TYPE!=CC_SW))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_EXCT_PRMSSN_SPPRT
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / Precision Time Management
Label Description
Precision Time Measurement When enabled, the core supports the Precision Time Measurement capability.
Enable Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: ((CX_PCIE_MODE == SINGLE_CPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_PTM_ENABLE
PTM External Master Time When enabled, the PTM local clock may be updated via an External Master Time
input.
Values:
■ false (0)
■ true (1)
Default Value: (CC_DEVICE_TYPE==CC_EP) ? 0 : 1
Enabled: CX_PTM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_PTM_EXTERNAL_MASTER_TIME
PTM Local Clock Granularity Set Local Clock Granularity for PTM.
Values: 0x0, ..., 0xff
Default Value: (CX_PTM_ROOT_CAPABLE==0) ? 0 : (CX_FREQ == FREQ_500) ?
2: (CX_FREQ == FREQ_250) ? 4 : (CX_FREQ == FREQ_125) ? 8 : (CX_FREQ ==
FREQ_62_5) ? 16 : 32
Enabled: CX_PTM_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_PTM_LOCAL_CLK_GRAN
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Label Description
USP 8G Rx Preset Hint Upstream Port 8.0 GT/s Receiver Preset Hint
Values: 0x0, ..., 0x7
Default Value: 0x7
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_USP_RX_PRESET_HINT0
DSP 8G Rx Preset Hint Downstream Port 8.0 GT/s Receiver Preset Hint
Values: 0x0, ..., 0x7
Default Value: 0x7
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_DSP_RX_PRESET_HINT0
USP 16G Rx Preset Hint Upstream Port 16.0 GT/s Receiver Preset Hint
Values: 0x0, ..., 0x7
Default Value: 0x7
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_USP_16G_RX_PRESET_HINT0
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / Secondary PCIe Extended
Label Description
DSP 16G Rx Preset Hint Downstream Port 16.0 GT/s Receiver Preset Hint
Values: 0x0, ..., 0x7
Default Value: 0x7
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_DSP_16G_RX_PRESET_HINT0
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Label Description
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PCI Express SW Controller Databook Device-Wide PCIe Features and Capabilities Config / CCIX Transport DVSEC
Label Description
ESM re-calibration is needed Specifies if ESM re-calibration is needed after ESM Data Rate is updated
after ESM Data Rate is updated Values:
■ Not needed (0)
■ Needed (1)
Default Value: Not needed
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_CX_CCIX_ESM_RECAL_NEEDED
ESM Reach Length for ESM Data Specifies the reach length for ESM Data Rate1
Rate1 Values:
■ Short Reach(SR) (0)
■ Long Reach(LR) (1)
■ SR and LR (2)
Default Value: Short Reach(SR)
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_CX_CCIX_ESM_REACH_LENGTH
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Label Description
ESM Extended EQ2 timeout for Specifies the ESM Extended EQ Phase2 timeout value for USP ESM Data Rate1
USP Values:
■ 24ms/32ms (0)
■ 50ms/58ms (1)
■ 100ms/108ms (2)
■ 200ms/208ms (3)
■ 400ms/408ms (4)
■ 600ms/608ms (5)
Default Value: 24ms/32ms
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_CX_CCIX_ESM_EXT_EQ2_USP_TIMEOUT
ESM Extended EQ3 timeout for Specifies the ESM Extended EQ Phase3 timeout value for DSP ESM Data Rate1
DSP Values:
■ 24ms/32ms (0)
■ 50ms/58ms (1)
■ 100ms/108ms (2)
■ 200ms/208ms (3)
■ 400ms/408ms (4)
■ 600ms/608ms (5)
Default Value: 24ms/32ms
Enabled: CX_CCIX_ESM_SUPPORT
Parameter Type: Feature Setting
Parameter Name: DEFAULT_CX_CCIX_ESM_EXT_EQ3_DSP_TIMEOUT
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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI
Label Description
PCIe Capabilities Interrupt Default value for the Interrupt Message Number field in the PCI Express Capabilities
Message Number (PF#i) Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1f
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: PCIE_CAP_INT_MSG_NUM_n
Is Port Connected to Slot (PF#i) Indicates that the PCI Express link associated with this Port is connected to a slot.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_EP
Parameter Type: Register Default Setting
Parameter Name: SLOT_IMPLEMENTED_n
Support No-Snoop (PF#i) Default value for the Enable No Snoop bit in the Device Control Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_NO_SNOOP_SUPPORTED_n
Enable Root RCB (PF#i) Default value for the Read Completion Boundary (RCB) bit in the Link Control
(for n = 0; n <= CX_NFUNC-1) Register.
Values:
■ 64-bytes (0x0)
■ 128-bytes (0x1)
Default Value: 64-bytes
Enabled: CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_DM
Parameter Type: Register Default Setting
Parameter Name: ROOT_RCB_n
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Label Description
MSI-X Table Size (PF#i) Default value for the MSI-X Table Size field in the MSI-X Control Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x7ff
Default Value: 0x0
Enabled: MSIX_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: MSIX_TABLE_SIZE_n
MSI-X Table BIR (PF#i) Default value for the Table BAR Indicator Register (BIR) field in the MSI-X Table Offset
(for n = 0; n <= CX_NFUNC-1) and BIR Register.
Values:
■ BAR0 (0x0)
■ BAR1 (0x1)
■ BAR2 (0x2)
■ BAR3 (0x3)
■ BAR4 (0x4)
■ BAR5 (0x5)
Default Value: BAR0
Enabled: MSIX_CAP_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: MSIX_TABLE_BIR_n
MSI-X Table Offset (PF#i) Default value for the Table Offset field in the MSI-X Table Offset and BIR Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1fffffff
Default Value: 0x0
Enabled: ((MSIX_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: MSIX_TABLE_OFFSET_n
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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) /
Label Description
MSI-X PBA BIR (PF#i) Default value for the Pending Bit Array (PBA) BIR field in the MSI-X PBA Offset and
(for n = 0; n <= CX_NFUNC-1) BIR Register.
Values:
■ BAR0 (0x0)
■ BAR1 (0x1)
■ BAR2 (0x2)
■ BAR3 (0x3)
■ BAR4 (0x4)
■ BAR5 (0x5)
Default Value: BAR0
Enabled: ((MSIX_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: MSIX_PBA_BIR_n
MSI-X PBA Offset (PF#i) Default value for the PBA Offset field in the MSI-X PBA Offset and BIR Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1fffffff
Default Value: 0x0
Enabled: ((MSIX_CAP_ENABLE==1))
Parameter Type: Register Default Setting
Parameter Name: MSIX_PBA_OFFSET_n
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Label Description
Default ECRC Check Capability Default value for the ECRC Check Capable bit in the Advanced Capabilities and
(PF#i) Control Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: (CX_ECRC_ENABLE==1) ? 1 : 0
Enabled: CX_ECRC_ENABLE==1 && AER_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_ECRC_CHK_CAP_n
Default ECRC Generation Default value for the ECRC Generation Capability bit in the Advanced Capabilities and
Capability (PF#i) Control Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: (CX_ECRC_ENABLE==1) ? 1 : 0
Enabled: CX_ECRC_ENABLE==1 && AER_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_ECRC_GEN_CAP_n
Advanced Error Interrupt Default value for the Advanced Error Interrupt Message Number field of the Root Error
Message Number (PF#i) Status Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1f
Default Value: 0x0
Enabled: AER_ENABLE==1 && CC_DEVICE_TYPE!=CC_EP &&
CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: AER_INT_MSG_NUM_n
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Label Description
Interrupt Vector Mode Support TLP Processing Hints supports Interrupt Vector Mode. If set indicates that the function
(PF#i) supports the Interrupt Vector Mode of operation.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_TPH_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: TPH_IVEC_n
Device Specific Mode Support TLP Processing Hints supports Device Specific Mode. If set indicates that the function
(PF#i) supports the Device Specific Mode of operation.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: CX_TPH_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: TPH_DS_n
Steering Tag Table Location TLP Processing Hints Steering Tag Table Location. Value indicates if and where the
(PF#i) ST Table is located.
(for n = 0; n <= CX_NFUNC-1) Values:
■ Not Present (0)
■ TPH Requester Capability Structure (1)
■ MSI-X Table Structure (2)
Default Value: Not Present
Enabled: (CX_TPH_ENABLE==1 && (TPH_DS_0 || TPH_IVEC_0))
Parameter Type: Feature Setting
Parameter Name: TPH_ST_TABLE_LOC_n
Steering Tag Table Size (PF#i) TLP Processing Hints Steering Tag Table Size. Software reads this field to determine
(for n = 0; n <= CX_NFUNC-1) the ST Table Size N, which is encoded as N-1. For example, a returned value of
00000000011 indicates a table size of 4.
Values: 1, ..., 2048
Default Value: 1
Enabled: (CX_TPH_ENABLE==1 && (TPH_ST_TABLE_LOC_0 != 0))
Parameter Type: Feature Setting
Parameter Name: TPH_ST_TABLE_SIZE_n
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Label Description
ATS Invalidate Queue Depth The number of Invalidate Requests that the Function can accept before putting
(PF#i) backpressure on the upstream connection. A value of 0 indicates the function can
(for n = 0; n <= CX_NFUNC-1) accept 32 Invalidate requests.
Values: 0, ..., 31
Default Value: 0
Enabled: CX_ATS_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: ATS_INV_Q_DPTH_n
ATS Smallest Translation Unit This value indicates to the Function the minimum number of 4096-byte blocks that is
(PF#i) indicated in a Translation Completion or Invalidate Request. This is a power of 2
(for n = 0; n <= CX_NFUNC-1) multiplier and the number of blocks is 2^STU. A value of 0 indicates 1 block and a
value of 31 indicates 2^31 blocks (or 8 TB total).
Values: 0, ..., 31
Default Value: 0
Enabled: CX_ATS_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: ATS_STU_n
ATS Global Invalidate Supported This is the default value (after reset) of the Global Invalidate Supported bit field in the
ATS Capability register. If set, the function supports Invalidation Requests that have
the Global Invalidate bit set. If clear, the function ignores the Global Invalidate bit in all
Invalidate Requests. This bit is 0b if the function does not support the PASID TLP
Prefix.
Values: 0x0, 0x1
Default Value: 0x0
Enabled: CX_ATS_ENABLE && CX_PASID_ENABLE
Parameter Type: Feature Setting
Parameter Name: DEFAULT_ATS_GLOBAL_INVAL_SPPRT
PRS Outstanding Capacity (PF#i) Register default for PRS Outstanding Capacity in PF0. For more details, see the
(for n = 0; n <= CX_NFUNC-1) PRS_OUTSTANDING_CAPACITY field in the PRS_REQ_CAPACITY_REG register.
Values: 0x0, ..., 0xffffffff
Default Value: 0x1
Enabled: (CX_PRS_ENABLE==1) && (CC_DEVICE_TYPE != CC_SW) &&
(CC_DEVICE_TYPE != CC_RC)
Parameter Type: Register Default Setting
Parameter Name: CX_PRS_OUTSTANDING_CAPACITY_VALUE_n
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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ACS
Label Description
ACS Source Validation This is the default value (after reset) of the ACS Source Validation bit field in the ACS
Supported (PF0) Capability register in PF0. A value of 1, indicates that the component implements ACS
Source Validation.
Values: 0x0, 0x1
Default Value: CC_DEVICE_TYPE!=CC_EP
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_SRC_VALID
ACS Translation Blocking This is the default value (after reset) of the ACS Translation Blocking bit field in the
Supported (PF0) ACS Capability register in PF0. A value of 1, indicates that the component implements
ACS Translation Blocking.
Values: 0x0, 0x1
Default Value: CC_DEVICE_TYPE!=CC_EP
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_AT_BLOCK
ACS P2P Request Redirect This is the default value (after reset) of the ACS P2P Request Redirect bit field in the
(PF#i) ACS Capability register in PF0. A value of 1, indicates that the component implements
(for n = 0; n <= CX_NFUNC-1) ACS P2P Request Redirect.
Values: 0x0, 0x1
Default Value: 0x1
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_P2P_REQ_REDIRECT_n
ACS P2P Completion Redirect This is the default value (after reset) of the ACS P2P Completion Redirect bit field in
(PF#i) the ACS Capability register in PF0. A value of 1, indicates that the component
(for n = 0; n <= CX_NFUNC-1) implements ACS P2P Completion Redirect.
Values: 0x0, 0x1
Default Value: 0x1
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_P2P_COMPL_REDIRECT_n
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Label Description
ACS Upstream Forwarding This is the default value (after reset) of the ACS Upstream Forwarding bit field in the
Supported (PF0) ACS Capability register in PF0. A value of 1, indicates that the component implements
ACS Upstream Forwarding.
Values: 0x0, 0x1
Default Value: CC_DEVICE_TYPE!=CC_EP
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_UP_FORWARD
ACS P2P Egress Control (PF#i) This is the default value (after reset) of the ACS P2P Egress Control bit field in the
(for n = 0; n <= CX_NFUNC-1) ACS Capability register in PF0. A value of 1, indicates that the component implements
ACS P2P Egress Control.
Values: 0x0, 0x1
Default Value: 0x1
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_P2P_EGRESS_CTRL_n
ACS Direct Translated P2P This is the default value (after reset) of the ACS Direct Translated P2P bit field in the
(PF#i) ACS Capability register in PF0. A value of 1, indicates that the component implements
(for n = 0; n <= CX_NFUNC-1) ACS Direct Translated P2P.
Values: 0x0, 0x1
Default Value: CC_DEVICE_TYPE==CC_SW || ((CC_DEVICE_TYPE==CC_DM ||
CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_EP) &&
(CX_ATS_ENABLE==1))
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_P2P_DIRECT_TRANSL_n
ACS Egress Control Vector Size This is the default value (after reset) of the Egress Control Vector Size field in the ACS
(PF#i) Capability register in PF0. Encodes 01h-FFh directly indicate the number of applicable
(for n = 0; n <= CX_NFUNC-1) bits in the Egress Control Vector; the encoding 00h indicates 256 bits.
Values: 0x0, ..., 0xff
Default Value: CC_DEVICE_TYPE==CC_SW || CC_DEVICE_TYPE==CC_RC) ?
0x4 : (CX_ACS_FUNC_GRP ? 0x8 : ((CX_NFUNC > 1 || CX_SRIOV_ENABLE) ?
CX_NFUNC : 0x4)
Enabled: CX_ACS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_ACS_EGRESS_CTRL_SIZE_n
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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / ACS
Label Description
Upstream Port ACS Egress This determines the default value of the read only bits in the Upstream Port Egress
Control Vector Mask (PF#i) Control Vector (after reset) in PF0. Set bits to 1 to indicate Read Only.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
Default Value: [<functionof> CX_ACS_FUNC_GRP 0]
Enabled: (CX_ACS_ENABLE && (CC_DEVICE_TYPE==CC_EP ||
CC_DEVICE_TYPE==CC_DM))
Parameter Type: Feature Setting
Parameter Name: CX_ACS_UP_EGRESS_CTRL_MASK_n
Downstream Port ACS Egress This determines the default value of the read only bits in the Downstream Port Egress
Control Vector Mask (PF#i) Control Vector (after reset) in PF0. Set bits to 1 to indicate Read Only.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
Default Value: 0x1
Enabled: CX_ACS_ENABLE && CC_DEVICE_TYPE!=CC_EP
Parameter Type: Feature Setting
Parameter Name: CX_ACS_DW_EGRESS_CTRL_MASK_n
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Label Description
LN Registration Max Default This parameter sets the default of the LNR_REGISTRATION_MAX field in the
(PF#i) LNR_CAP_OFF register for PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x1f
Default Value: 0x0
Enabled: CX_LN_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: CX_LN_REG_MAX_VALUE_n
LNR-128 Supported Default This parameter sets the default of the LNR_128_SUPPORTED field in the
(PF#i) LNR_CAP_OFF register for PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: CX_LN_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: CX_LN_128_SUPPORTED_VALUE_n
LNR-64 Supported Default (PF#i) This parameter sets the default of the LNR_64_SUPPORTED field in the
(for n = 0; n <= CX_NFUNC-1) LNR_CAP_OFF register for PF0.
Values: 0x0, 0x1
Default Value: 0x0
Enabled: CX_LN_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: CX_LN_64_SUPPORTED_VALUE_n
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Label Description
Immediate Readiness (PF#i) Enable Immediate Readiness support in the controller for PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_IMM_EN==1
Enabled: CX_RN_IMM_EN==1
Parameter Type: Feature Setting
Parameter Name: CX_RN_IMM_VALUE_n
Immediate Readiness D0 (PF#i) Enable Immediate Readiness on Return to D0 support in the controller for PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_IMM_EN==1
Enabled: CX_RN_IMM_EN==1
Parameter Type: Feature Setting
Parameter Name: CX_RN_IMM_D0_VALUE_n
RTR Valid (PF#i) Register default for RTR Valid field in PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_RTR_EN==1
Enabled: CX_RN_RTR_EN==1
Parameter Type: Register Default Setting
Parameter Name: CX_RN_RTR_VALID_n
RTR DL Up Time (PF#i) Register default for RTR DL Up Time field in PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: 0x0
Enabled: CX_RN_RTR_EN==1
Parameter Type: Register Default Setting
Parameter Name: CX_RN_RTR_DL_UP_VALUE_n
RTR Reset Time (PF#i) Register default for RTR Reset Time field in PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: 0x0
Enabled: CX_RN_RTR_EN==1
Parameter Type: Register Default Setting
Parameter Name: CX_RN_RTR_RESET_VALUE_n
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Label Description
RTR D3hot to D0 Time (PF#i) Register default for RTR D3hot to D0 Time field in PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x80a
Default Value: 0x0
Enabled: CX_RN_RTR_EN==1
Parameter Type: Register Default Setting
Parameter Name: CX_RN_RTR_D3D0_VALUE_n
RTR FLR Time (PF#i) Register default for RTR FLR Time field in PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: 0x0
Enabled: CX_RN_RTR_EN==1 && CX_FLR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: CX_RN_RTR_FLR_VALUE_n
VF RTR Valid (PF#i) Register default for RTR Valid field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_RTR_VALID_0 && VF_RTR_ENABLE
Enabled: VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_RN_RTR_VALID_n
VF Reset Time (PF#i) Register default for RTR Reset Time field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: CX_RN_RTR_RESET_VALUE_0
Enabled: VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_RN_RTR_RESET_VALUE_n
VF D3hot to D0 Time (PF#i) Register default for RTR D3hot to D0 Time field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0x80a
Default Value: CX_RN_RTR_D3D0_VALUE_0
Enabled: VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_RN_RTR_D3D0_VALUE_n
VF FLR Time (PF#i) Register default for RTR FLR Time field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: CX_RN_RTR_FLR_VALUE_0
Enabled: VF_RTR_ENABLE==1 && CX_FLR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: VF_RN_RTR_FLR_VALUE_n
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Label Description
External VF RTR Valid (PF#i) Register default for RTR Valid field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_RTR_VALID_0 && EXT_VF_RTR_ENABLE
Enabled: EXT_VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: EXT_VF_RN_RTR_VALID_n
External VF Reset Time (PF#i) Register default for RTR Reset Time field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: CX_RN_RTR_RESET_VALUE_0
Enabled: EXT_VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: EXT_VF_RN_RTR_RESET_VALUE_n
External VF D3hot to D0 Time Register default for RTR D3hot to D0 Time field in PF0 VFs.
(PF#i) Values: 0x0, ..., 0x80a
(for n = 0; n <= CX_NFUNC-1) Default Value: CX_RN_RTR_D3D0_VALUE_0
Enabled: EXT_VF_RTR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: EXT_VF_RN_RTR_D3D0_VALUE_n
External VF FLR Time (PF#i) Register default for RTR FLR Time field in PF0 VFs.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xa1e
Default Value: CX_RN_RTR_FLR_VALUE_0
Enabled: EXT_VF_RTR_ENABLE==1 && CX_FLR_ENABLE==1
Parameter Type: Register Default Setting
Parameter Name: EXT_VF_RN_RTR_FLR_VALUE_n
FRS Supported (PF#i) Function Readiness Status messaging supported for function PF0.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_RN_FRS_SUPPORTED==1
Enabled: CX_RN_FRS_SUPPORTED==1
Parameter Type: Feature Setting
Parameter Name: CX_RN_FRS_VALUE_n
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Label Description
PME Support (PF#i) Default value for the PME_Support field in the Power Management Capabilities
(for n = 0; n <= CX_NFUNC-1) Register.
Values: 0x0, ..., 0x1f
Default Value: 0x1b
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: PME_SUPPORT_n
D1 Support (PF#i) Default value for the D1 Support bit in the Power Management Capabilities Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: D1_SUPPORT_n
D2 Support (PF#i) Default value for the D2 Support bit in the Power Management Capabilities Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: D2_SUPPORT_n
Device Specific Initialization Default value for the Device Specific Initialization (DSI) bit in the Power Management
(PF#i) Capabilities Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEV_SPEC_INIT_n
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Label Description
Auxiliary Current (PF#i) Default value for the Aux Current field in the Power Management Capabilities Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ 0mA (0x0)
■ 55mA (0x1)
■ 100mA (0x2)
■ 160mA (0x3)
■ 220mA (0x4)
■ 270mA (0x5)
■ 320mA (0x6)
■ 375mA (0x7)
Default Value: 375mA
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: AUX_CURRENT_n
No Reset on D3hot->D0 Default value for the No Soft Reset bit in the Power Management Control and Status
Transition (PF#i) Register. When set, you should not reset any controller registers when transitioning
(for n = 0; n <= CX_NFUNC-1) from D3hot to D0. Therefore, you should not assert the non_sticky_rst_n and
sticky_rst_n inputs.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_NO_SOFT_RESET_n
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Label Description
Device Identification Number Default value for the Device ID field in the Device ID and Vendor ID Register.
(PF#i) Values: 0x0, ..., 0xffff
(for n = 0; n <= CX_NFUNC-1) Default Value: 0xabcd
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_DEVICE_ID_n
Vendor Identification Number Default value for the Vendor ID field in the Device ID and Vendor ID Register.
(PF#i) Values: 0x0, ..., 0xffff
(for n = 0; n <= CX_NFUNC-1) Default Value: 0x16c3
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_VENDOR_ID_n
Device Revision Number (PF#i) Default value for the Revision ID field in the Revision ID Register
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xff
Default Value: 0x1
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_REVISION_ID_n
Subsystem Device ID (PF#i) Default value for the Subsystem ID field in the Subsystem ID and Subsystem Vendor
(for n = 0; n <= CX_NFUNC-1) ID Register.
Values: 0x0, ..., 0xffff
Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: SUBSYS_DEV_ID_n
Subsystem Vendor ID (PF#i) Default value for the Subsystem Vendor ID field in the Subsystem ID and Subsystem
(for n = 0; n <= CX_NFUNC-1) Vendor ID Register.
Values: 0x0, ..., 0xffff
Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: SUBSYS_VENDOR_ID_n
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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) / PCI
Label Description
Include ROM BAR (PF#i) Include the expansion ROM BAR registers.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: ROM_BAR_ENABLED_n
ROM BAR Mask (PF#i) Determines the default of the Expansion ROM BAR Mask register.
(for n = 0; n <= CX_NFUNC-1) ■ The BAR Mask register specifies which bits of the Expansion ROM BAR are
non-writable by host software, which determines the size of the BAR.
■ The maximum value for ROM_MASK_N is 0xFFFFFF because the maximum
space that can be claimed by an Expansion ROM BAR is 16 MB.
■ For example: 32'hFFFF =BAR size of 2^16.
Values: 0x7ff, ..., 0xffffff
Default Value: 0xffff
Enabled: ROM_BAR_ENABLED_n==1
Parameter Type: Register Default Setting
Parameter Name: ROM_MASK_n
Programmable ROM BAR Mask Determines if the Expansion ROM BAR Mask register is writable by application
(PF#i) software. If writing to a Expansion ROM BAR Mask register is enabled, your
(for n = 0; n <= CX_NFUNC-1) application can write to the Expansion ROM BAR Mask register through the DBI by
asserting dbi_cs2 in addition to dbi_cs.
Values: 0x0, 0x1
Default Value: 0x0
Enabled: ROM_BAR_ENABLED_n==1
Parameter Type: Feature Setting
Parameter Name: ROM_MASK_WRITABLE_n
Specify ROM BAR Target Direct incoming requests that pass filtering and match the Expansion ROM BAR to
Interface (PF#i) either RTRGT0 or RTRGT1.
(for n = 0; n <= CX_NFUNC-1) ■ For example, setting ROM_FUNC0_BAR0_TARGET_MAP to 1 maps all incoming
requests for the Expansion ROM BAR of function 0 to RTRGT1.
■ If TRGT1_POPULATE =0 (no RTRGT1 interface), then the map-by-BAR parame-
ters have no effect; all requests that pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: ROM_BAR_ENABLED_n==1 && TRGT1_POPULATE==1
Parameter Type: Feature Setting
Parameter Name: ROM_FUNCn_TARGET_MAP
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Label Description
Configure Other PCI Register Select here if you want to configure the defaults for the other PCI Standard Header
Defaults (PF#i) registers. An extra window will appear under this page. To access it, click the
(for n = 0; n <= CX_NFUNC-1) plus/minus symbol in the hierarchy view on the left panel. This is optional but not
usually recommended. You can also change these register defaults using the DBI
before (or after) the link comes up.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: CX_PCI_HEADER_DEFAULTS_VISIBLE_n
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Label Description
Base Class Code (PF#i) Default value for the Base Class Code field in the Class Code Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: BASE_CLASS_CODE_n
Sub Class Code (PF#i) Default value for the Subclass Code field in the Class Code Register.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: SUB_CLASS_CODE_n
Programming Interface Code Default value for the Programming Interface field in the Class Code Register.
(PF#i) Values: 0x0, ..., 0xff
(for n = 0; n <= CX_NFUNC-1) Default Value: 0x0
Enabled: Always
Parameter Type: Register Default Setting
Parameter Name: IF_CODE_n
CardBus CIS Address Pointer Default value for the CardBus CIS Pointer Register.
(PF#i) Values: 0x0, ..., 0xffff
(for n = 0; n <= CX_NFUNC-1) Default Value: 0x0
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: CARDBUS_CIS_PTR_n
Interrupt Pin (PF#i) Default value for the Interrupt Pin Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ None (0x0)
■ INTA (0x1)
■ INTB (0x2)
■ INTC (0x3)
■ INTD (0x4)
Default Value: INTA
Enabled: CC_DEVICE_TYPE!=CC_RC && CC_DEVICE_TYPE!=CC_SW
Parameter Type: Register Default Setting
Parameter Name: INT_PIN_MAPPING_n
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Label Description
IO Address Decode (PF#i) Default value for the 32-Bit I/O Space bit in the I/O Base and I/O Limit Register.
(for n = 0; n <= CX_NFUNC-1) Values:
■ 16-bit (0x0)
■ 32-bit (0x1)
Default Value: CC_DEVICE_TYPE==CC_SW
Enabled: (!(CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW))
Parameter Type: Register Default Setting
Parameter Name: IO_DECODE_32_n
Memory Address Decode (PF#i) Default value for the 64-Bit Memory Addressing bit in the Prefetchable Memory Base
(for n = 0; n <= CX_NFUNC-1) and Limit Register.
Values:
■ 32-bit (0x0)
■ 64-bit (0x1)
Default Value: CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW ||
CC_DEVICE_TYPE==CC_DM
Enabled: CC_DEVICE_TYPE==CC_RC || CC_DEVICE_TYPE==CC_SW ||
CC_DEVICE_TYPE==CC_DM
Parameter Type: Register Default Setting
Parameter Name: MEM_DECODE_64_n
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Label Description
BAR_0 / BAR_1
BAR_0 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: Memory
Enabled: BAR0_ENABLED_n==1
Parameter Type: Register Default Setting
Parameter Name: MEM0_SPACE_DECODER_n
BAR_0 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR0_ENABLED_n==1 && MEM0_SPACE_DECODER_n==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE0_n
BAR_0 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: (MEM0_SPACE_DECODER_0==1 || BAR0_ENABLED_0==0) ? 0 : 2
Enabled: BAR0_ENABLED_n==1 && MEM0_SPACE_DECODER_n==0
Parameter Type: Register Default Setting
Parameter Name: BAR0_TYPE_n
Synopsys, Inc.
Label Description
RBAR0 Usable Resource Sizes Indicates usable resource sizes for BAR0.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR0 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: CX_BAR0_RESIZABLE_n==1
Parameter Type: Feature Setting
Parameter Name: CX_BAR0_RESOURCE_AVAIL_n
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Label Description
BAR_0 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffffffffffff
Default Value: CX_BAR0_RESIZABLE_n==1 ? [pcie_cc_bar_mask
CX_BAR0_RESOURCE_AVAIL_n] : MEM0_SPACE_DECODER_n==1 ? 0xFF :
0xFFFFF
Enabled: BAR0_ENABLED_n==1 && MEM0_SPACE_DECODER_n==0 &&
CX_BAR0_RESIZABLE_n==0
Parameter Type: Register Default Setting
Parameter Name: BAR0_MASK_n
Specify Target Interface for Direct incoming Requests that pass filtering and match BAR_0 to either RTRGT0 or
BAR_0 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR0_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: BAR0_ENABLED_n==1 && TRGT1_POPULATE==1
Parameter Type: Feature Setting
Parameter Name: MEM_FUNCn_BAR0_TARGET_MAP
BAR_1 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: Memory
Enabled: BAR1_ENABLED_0==1
Parameter Type: Register Default Setting
Parameter Name: MEM1_SPACE_DECODER_n
Synopsys, Inc.
Label Description
BAR_1 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR1_ENABLED_0==1 && MEM1_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE1_n
BAR_1 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: BAR1_TYPE_n
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Label Description
RBAR1 Usable Resource Sizes Indicates usable resource sizes for BAR1.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR1 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfff0
Default Value: 0x10
Enabled: CX_BAR1_RESIZABLE_0==1
Parameter Type: Register Default Setting
Parameter Name: CX_BAR1_RESOURCE_AVAIL_n
BAR_1 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffff
Default Value: CX_BAR1_RESIZABLE_0==1 ? [calc_bar_mask
CX_BAR1_RESOURCE_AVAIL_0] : MEM1_SPACE_DECODER_0==1 ? 0xFF :
0xFFFF
Enabled: BAR1_ENABLED_0==1 && MEM1_SPACE_DECODER_0==0 &&
CX_BAR1_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR1_MASK_n
Specify Target Interface for Direct incoming requests that pass filtering and match BAR_1 to either RTRGT0 or
BAR_1 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR1_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR1 of function 0 to RTRGT1. If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: ((BAR1_ENABLED_0==1 && TRGT1_POPULATE==1) &&
CC_DEVICE_TYPE!=CC_RC)
Parameter Type: Register Default Setting
Parameter Name: MEM_FUNCn_BAR1_TARGET_MAP
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Label Description
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Label Description
Synopsys, Inc.
Label Description
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Label Description
BAR_2 / BAR_3
BAR_2 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: Memory
Enabled: BAR2_ENABLED_0==1
Parameter Type: Register Default Setting
Parameter Name: MEM2_SPACE_DECODER_n
BAR_2 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR2_ENABLED_0==1 && MEM2_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE2_n
Synopsys, Inc.
Label Description
BAR_2 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: BAR2_ENABLED_0==1 && MEM2_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR2_TYPE_n
RBAR2 Usable Resource Sizes Indicates usable resource sizes for BAR2.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR2 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: CX_BAR2_RESIZABLE_0==1
Parameter Type: Register Default Setting
Parameter Name: CX_BAR2_RESOURCE_AVAIL_n
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Label Description
BAR_2 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffffffffffff
Default Value: CX_BAR2_RESIZABLE_0==1 ? [calc_bar_mask
CX_BAR2_RESOURCE_AVAIL_0] : MEM2_SPACE_DECODER_0==1 ? 0xFF :
0xFFFFF
Enabled: BAR2_ENABLED_0==1 && MEM2_SPACE_DECODER_0==0 &&
CX_BAR2_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR2_MASK_n
Specify Target Interface for Direct incoming requests that pass filtering and match BAR_2 to either RTRGT0 or
BAR_2 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR2_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR2 of function 0 to RTRGT1. If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: BAR2_ENABLED_0==1 && TRGT1_POPULATE==1
Parameter Type: Feature Setting
Parameter Name: MEM_FUNCn_BAR2_TARGET_MAP
BAR_3 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: Memory
Enabled: BAR3_ENABLED_0==1
Parameter Type: Register Default Setting
Parameter Name: MEM3_SPACE_DECODER_n
Synopsys, Inc.
Label Description
BAR_3 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR3_ENABLED_0==1 && MEM3_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE3_n
BAR_3 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: BAR3_TYPE_n
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Label Description
RBAR3 Usable Resource Sizes Indicates usable resource sizes for BAR3.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR3 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfff0
Default Value: 0x10
Enabled: CX_BAR3_RESIZABLE_0==1
Parameter Type: Register Default Setting
Parameter Name: CX_BAR3_RESOURCE_AVAIL_n
BAR_3 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffff
Default Value: CX_BAR3_RESIZABLE_0==1 ? [calc_bar_mask
CX_BAR3_RESOURCE_AVAIL_0] : MEM3_SPACE_DECODER_0==1 ? 0xFF :
0xFFFF
Enabled: BAR3_ENABLED_0==1 && MEM3_SPACE_DECODER_0==0 &&
CX_BAR3_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR3_MASK_n
Specify Target Interface for Direct incoming requests that pass filtering and match BAR_3 to either RTRGT0 or
BAR_3 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR3_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR3 of function 0 to RTRGT1.If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: BAR3_ENABLED_0==1 && TRGT1_POPULATE==1
Parameter Type: Register Default Setting
Parameter Name: MEM_FUNCn_BAR3_TARGET_MAP
Synopsys, Inc.
Label Description
BAR_4 / BAR_5
BAR_4 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: CC_DEVICE_TYPE!=CC_RC && BAR4_ENABLED_0==1
Enabled: BAR4_ENABLED_0==1
Parameter Type: Register Default Setting
Parameter Name: MEM4_SPACE_DECODER_n
BAR_4 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR4_ENABLED_0==1 && MEM4_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE4_n
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Label Description
BAR_4 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: BAR4_ENABLED_0==1 && MEM4_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR4_TYPE_n
RBAR4 Usable Resource Sizes Indicates usable resource sizes for BAR4.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR4 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfffffffffff0
Default Value: 0x10
Enabled: CX_BAR4_RESIZABLE_0==1
Parameter Type: Register Default Setting
Parameter Name: CX_BAR4_RESOURCE_AVAIL_n
Synopsys, Inc.
Label Description
BAR_4 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffffffffffff
Default Value: CX_BAR4_RESIZABLE_0==1 ? [calc_bar_mask
CX_BAR4_RESOURCE_AVAIL_0] : MEM4_SPACE_DECODER_0==1 ? 0xFF :
0xFFF
Enabled: BAR4_ENABLED_0==1 && MEM4_SPACE_DECODER_0==0 &&
CX_BAR4_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR4_MASK_n
Specify Target Interface for Direct incoming requests that pass filtering and match BAR_4 to either RTRGT0 or
BAR_4 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR4_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR4 of function 0 to RTRGT1. If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: BAR4_ENABLED_0==1 && TRGT1_POPULATE==1
Parameter Type: Feature Setting
Parameter Name: MEM_FUNCn_BAR4_TARGET_MAP
BAR_5 is Memory or I/O (PF#i) Determines whether the BAR is for memory or I/O (bit 0 of the BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ Memory (0x0)
■ I/O (0x1)
Default Value: Memory
Enabled: BAR5_ENABLED_0==1
Parameter Type: Register Default Setting
Parameter Name: MEM5_SPACE_DECODER_n
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Label Description
BAR_5 is Prefetchable (PF#i) Determines if a memory BAR is for prefetchable memory (bit 3 of a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: 0x0
Enabled: BAR5_ENABLED_0==1 && MEM5_SPACE_DECODER_0==0
Parameter Type: Register Default Setting
Parameter Name: PREFETCHABLE5_n
BAR_5 Bit Size (PF#i) Determines the type as 32-bit or 64-bit; (bits [2:1] for a memory BAR).
(for n = 0; n <= CX_NFUNC-1) Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: BAR5_TYPE_n
Synopsys, Inc.
Label Description
RBAR5 Usable Resource Sizes Indicates usable resource sizes for BAR5.
(PF#i) ■ 3-0: RsvdP
(for n = 0; n <= CX_NFUNC-1)
■ 4: 1MB
■ 5: 2MB
■ .
■ .
■ .
■ 22: 256GB
■ 23: 512GB
■ 31-24: RsvdP
Example: 0x00000030 indicates that BAR5 will operate correctly with the BAR sized to
either 1MB or 2MB.
Values: 0x10, ..., 0xfff0
Default Value: 0x10
Enabled: CX_BAR5_RESIZABLE_0==1
Parameter Type: Register Default Setting
Parameter Name: CX_BAR5_RESOURCE_AVAIL_n
BAR_5 Mask (PF#i) Determines the default value of the BAR Mask register. The BAR Mask register
(for n = 0; n <= CX_NFUNC-1) specifies which bits of the BAR are non-writable by host software, which determines
the size of the BAR. When the BAR is Resizable (BARn_SIZING_SCHEME_N =2),
then the default value of this mask is determined from the
CX_BARn_RESOURCE_AVAIL_N parameter.
Values: 0xff, ..., 0xffffffff
Default Value: CX_BAR5_RESIZABLE_0==1 ? [calc_bar_mask
CX_BAR5_RESOURCE_AVAIL_0] : MEM5_SPACE_DECODER_0==1 ? 0xFF :
0xFFFF
Enabled: BAR5_ENABLED_0==1 && MEM5_SPACE_DECODER_0==0 &&
CX_BAR5_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: BAR5_MASK_n
Specify Target Interface for Direct incoming requests that pass filtering and match BAR_5 to either RTRGT0 or
BAR_5 (PF#i) RTRGT1. For example, setting MEM_FUNC0_BAR5_TARGET_MAP to 1 maps all
(for n = 0; n <= CX_NFUNC-1) incoming requests for BAR5 of function 0 to RTRGT1. If TRGT1_POPULATE = 0 (no
RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests that
pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: BAR5_ENABLED_0==1 && TRGT1_POPULATE==1
Parameter Type: Feature Setting
Parameter Name: MEM_FUNCn_BAR5_TARGET_MAP
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Label Description
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Label Description
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Label Description
Number of Virtual Functions Number of virtual functions supported for this physical function. Default value of the
(PF#i) InitialVFs field in the SR-IOV Capability registers. When Extensible Virtual Function
(for n = 0; n <= CX_NFUNC) (CX_EXTENSIBLE_VFUNC) is enabled, this parameter indicates the total of both
internal VFs and external VFs.
Values: 0x0, ..., SNPS_RSVDPARAM_24
Default Value: 0x2
Enabled: CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_MAX_VF_n
Virtual Function Dependency Specifies the 8-bit VF dependency link for the PF. Valid only if CX_NFUNC>1 and
Link (PF#i) CX_VF_DEPENDENCY_LINK_SUPP=1.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: CX_VF_DEPENDENCY_LINK_SUPP && CX_SRIOV_ENABLE &&
(CX_NFUNC > 1)
Parameter Type: Feature Setting
Parameter Name: CX_VF_DEPENDENCY_LINK_n
First VF Offset with ARI (PF#i) Specifies the Routing ID offset of the first VF in this physical function in an ARI capable
(for n = 0; n <= CX_NFUNC-1) hierarchy. When CX_VF_STRIDE_ALWAYS_ONE=1 this parameter is disabled
because it is not used.
Values: 0x0, ..., 0xffff
Default Value: (CX_NFUNC>=17) ? 32 : (CX_NFUNC>=9) ? 16 : (CX_NFUNC>=5) ?
8 : (CX_NFUNC>=3) ? 4 : CX_NFUNC
Enabled: CX_SRIOV_ENABLE && !CX_VF_STRIDE_ALWAYS_ONE
Parameter Type: Register Default Setting
Parameter Name: FIRST_VF_OFFSET_ARI_CAP_HIER1_n
First VF Offset without ARI (PF#i) Specifies the Routing ID offset of the first VF in this physical function in a non-ARI
(for n = 0; n <= CX_NFUNC-1) capable hierarchy. When CX_VF_STRIDE_ALWAYS_ONE=1 this parameter is
disabled because it is not used.
Values: 0x0, ..., 0xffff
Default Value: 0x100
Enabled: CX_SRIOV_ENABLE && !CX_VF_STRIDE_ALWAYS_ONE
Parameter Type: Register Default Setting
Parameter Name: FIRST_VF_OFFSET_ARI_CAP_HIER0_n
Synopsys, Inc.
Label Description
VF Stride with ARI (PF#i) Specifies the Routing ID stride from one VF to the next one in this physical function in
(for n = 0; n <= CX_NFUNC-1) an ARI capable hierarchy
Values: 0x0, ..., 0xffff
Default Value: CX_VF_STRIDE_ALWAYS_ONE) ? 1 : ((CX_NFUNC>=17) ? 32 :
(CX_NFUNC>=9) ? 16 : (CX_NFUNC>=5) ? 8 : (CX_NFUNC>=3) ? 4 : CX_NFUNC
Enabled: CX_SRIOV_ENABLE && !CX_VF_STRIDE_ALWAYS_ONE
Parameter Type: Register Default Setting
Parameter Name: VF_STRIDE_ARI_CAP_HIER1_n
VF Stride without ARI (PF#i) Specifies the Routing ID offset from one VF to the next one in this physical function in
(for n = 0; n <= CX_NFUNC-1) a non-ARI capable hierarchy
Values: 0x0, ..., 0xffff
Default Value: (CX_VF_STRIDE_ALWAYS_ONE) ? 0x0001 : 0x0100
Enabled: CX_SRIOV_ENABLE && !CX_VF_STRIDE_ALWAYS_ONE
Parameter Type: Register Default Setting
Parameter Name: VF_STRIDE_ARI_CAP_HIER0_n
Virtual Function Device Specifies the 16-bit virtual function Device ID for this physical function. It may be
Identification Number (PF#i) different from the physical function's.
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, ..., 0xffff
Default Value: CX_DEVICE_ID_0
Enabled: CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: CX_VF_DEVICE_ID_n
Virtual Function Supported Page Specifies the 32-bit supported page sizes for virtual functions for the physical function.
Sizes (PF#i) Values: 0x553, ..., 0xffff
(for n = 0; n <= CX_NFUNC-1) Default Value: 0x553
Enabled: CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: CX_VF_SUPP_PAGE_SIZE_n
ARI Capable Hierarchy Only present in PF0. Read Only Zero in other PFs. Specifies if ARI Capable Hierarchy
Preserved (PF#i) bit is preserved across certain power state transitions
(for n = 0; n <= CX_NFUNC-1) Values: 0x0, 0x1
Default Value: CX_SRIOV_ENABLE
Enabled: CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: CX_ARI_CAP_HIER_PRSVD_n
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Label Description
PF#i VF BAR_0 is Prefetchable Virtual Function BAR0 Memory Prefetchable. When set indicates VF BAR0 Memory
(for n = 0; n <= CX_NFUNC-1) BAR is a prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR0_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE0_n
PF#i VF BAR_0 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: (VF_BAR0_ENABLED_0==0) ? 0 : 2
Enabled: VF_BAR0_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_BAR0_TYPE_n
PF#i VF BAR_0 Mask Virtual Function BAR0 Mask. Determines the default of the VF BAR Mask register. The
(for n = 0; n <= CX_NFUNC-1) VF BAR Mask register specifies which bits of the VF BAR are non-writable by host
software, which determines the size of the BAR.
Values: 0xff, ..., 0xffffffffffffffff
Default Value: VF_BAR0_RESIZABLE_0==1?[calc_bar_mask
VF_BAR0_RESOURCE_AVAIL_0]:(VF_BAR0_TYPE_0==0 ? 0xFFFF : 0xFFFFF)
Enabled: VF_BAR0_ENABLED_0==1 && CX_SRIOV_ENABLE &&
VF_BAR0_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR0_MASK_n
Synopsys, Inc.
Label Description
Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_0 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Note:This feature is not applicable for RC.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: ((VF_BAR0_ENABLED_0==1 && TRGT1_POPULATE==1) &&
CC_DEVICE_TYPE!=CC_RC) && CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MEM_FUNCn_BAR0_TARGET_MAP
PF#i VF BAR_1 is Prefetchable Virtual Function BAR1 Memory Prefetchable. When set indicates VF BAR1 Memory
(for n = 0; n <= CX_NFUNC-1) BAR is a prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR1_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE1_n
PF#i VF BAR_1 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR1_TYPE_n
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Label Description
PF#i VF BAR_1 Mask Virtual Function BAR1 Mask. Determines the default of the VF BAR Mask register. The
(for n = 0; n <= CX_NFUNC-1) VF BAR Mask register specifies which bits of the VF BAR are non-writable by host
software, which determines the size of the BAR
Values: 0xff, ..., 0xffffffff
Default Value: VF_BAR1_RESIZABLE_0==1?[calc_bar_mask
VF_BAR1_RESOURCE_AVAIL_0]: 0xFFFF
Enabled: VF_BAR1_ENABLED_0==1 && CX_SRIOV_ENABLE &&
VF_BAR1_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR1_MASK_n
Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_1 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Note:This feature is not applicable for RC.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: ((VF_BAR1_ENABLED_0==1 && TRGT1_POPULATE==1) &&
CC_DEVICE_TYPE!=CC_RC) && CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MEM_FUNCn_BAR1_TARGET_MAP
PF#i VF BAR_2 is Prefetchable BAR2 Memory Prefetchable. When set indicates VF BAR2 Memory BAR is a
(for n = 0; n <= CX_NFUNC-1) prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR2_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE2_n
Synopsys, Inc.
Label Description
PF#i VF BAR_2 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: VF_BAR2_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_BAR2_TYPE_n
Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_2 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: VF_BAR2_ENABLED_0==1 && TRGT1_POPULATE==1 &&
CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_MEM_FUNCn_BAR2_TARGET_MAP
PF#i VF BAR_3 is Prefetchable Virtual Function BAR3 Memory Prefetchable. When set indicates VF BAR3 Memory
(for n = 0; n <= CX_NFUNC-1) BAR is a prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR3_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE3_n
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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) /
Label Description
PF#i VF BAR_3 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR3_TYPE_n
PF#i VF BAR_3 Mask Virtual Function BAR3 Mask. Determines the default of the VF BAR Mask register. The
(for n = 0; n <= CX_NFUNC-1) VF BAR Mask register specifies which bits of the VF BAR are non-writable by host
software, which determines the size of the BAR
Values: 0xff, ..., 0xffffffff
Default Value: VF_BAR3_RESIZABLE_0==1?[calc_bar_mask
VF_BAR3_RESOURCE_AVAIL_0]: 0xFFFF
Enabled: VF_BAR3_ENABLED_0==1 && CX_SRIOV_ENABLE &&
VF_BAR3_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR3_MASK_n
Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_3 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: VF_BAR3_ENABLED_0==1 && TRGT1_POPULATE==1 &&
CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MEM_FUNCn_BAR3_TARGET_MAP
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Label Description
PF#i VF BAR_4 is Prefetchable Virtual Function BAR4 Memory Prefetchable. When set indicates VF BAR4 Memory
(for n = 0; n <= CX_NFUNC-1) BAR is a prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR4_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE4_n
PF#i VF BAR_4 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: VF_BAR4_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_BAR4_TYPE_n
PF#i VF BAR_4 Mask Virtual Function BAR4 Mask. Determines the default of the VF BAR Mask register. The
(for n = 0; n <= CX_NFUNC-1) VF BAR Mask register specifies which bits of the VF BAR are non-writable by host
software, which determines the size of the BAR
Values: 0xff, ..., 0xffffffffffffffff
Default Value: VF_BAR4_RESIZABLE_0==1?[calc_bar_mask
VF_BAR4_RESOURCE_AVAIL_0]: 0xFFF
Enabled: VF_BAR4_ENABLED_0==1 && CX_SRIOV_ENABLE &&
VF_BAR4_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR4_MASK_n
Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_4 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: VF_BAR4_ENABLED_0==1 && TRGT1_POPULATE==1 &&
CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MEM_FUNCn_BAR4_TARGET_MAP
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PCI Express SW Controller Databook Per-Function PCIe Capabilities and BAR Config / Physical Function 0 (PF0) /
Label Description
PF#i VF BAR_5 is Prefetchable Virtual Function BAR5 Memory Prefetchable. When set indicates VF BAR5 Memory
(for n = 0; n <= CX_NFUNC-1) BAR is a prefetchable BAR
Values: 0x0, 0x1
Default Value: 0x0
Enabled: VF_BAR5_ENABLED_0==1 && CX_SRIOV_ENABLE
Parameter Type: Register Default Setting
Parameter Name: VF_PREFETCHABLE5_n
PF#i VF BAR_5 Bit Size Determines the BAR type as 32-bit or 64-bit in function 0; (bits [2:1] for a memory
(for n = 0; n <= CX_NFUNC-1) BAR).
Values:
■ 32-bit (0x0)
■ 64-bit (0x2)
Default Value: 32-bit
Enabled: 0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR5_TYPE_n
PF#i VF BAR_5 Mask Virtual Function BAR5 Mask. Determines the default of the VF BAR Mask register. The
(for n = 0; n <= CX_NFUNC-1) VF BAR Mask register specifies which bits of the VF BAR are non-writable by host
software, which determines the size of the BAR
Values: 0xff, ..., 0xffffffff
Default Value: VF_BAR5_RESIZABLE_0==1?[calc_bar_mask
VF_BAR5_RESOURCE_AVAIL_0]: 0xFFFF
Enabled: VF_BAR5_ENABLED_0==1 && CX_SRIOV_ENABLE &&
VF_BAR5_RESIZABLE_0==0
Parameter Type: Register Default Setting
Parameter Name: VF_BAR5_MASK_n
Synopsys, Inc.
Label Description
Specify Target Interface for PF#i Direct incoming requests that pass filtering and match this VF BAR to either RTRGT0
VF BAR_5 or RTRGT1. For example, setting VF_MEM_FUNC0_BAR0_TARGET_MAP to 1 maps
(for n = 0; n <= CX_NFUNC-1) all incoming requests for VF BAR0 of function 0 to RTRGT1. If TRGT1_POPULATE =0
(no RTRGT1 interface), then the map-by-BAR parameters have no effect; all requests
that pass filtering are routed to RTRGT0.
Values:
■ Target_0 (0x0)
■ Target_1 (0x1)
Default Value: (TRGT1_POPULATE==1) ? 1 : 0
Enabled: VF_BAR5_ENABLED_0==1 && TRGT1_POPULATE==1 &&
CX_SRIOV_ENABLE
Parameter Type: Feature Setting
Parameter Name: VF_MEM_FUNCn_BAR5_TARGET_MAP
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PCI Express SW Controller Databook Advanced RAM Config Parameters
Label Description
RAM Timing
Single Port RAM Read Access Specifies the single port RAM read access time. Used by the synthesis.
Time [ps] Values: -2147483648, ..., 2147483647
Default Value: 800
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: RAM1P_RD_ACCESS
Single Port RAM Address/Data Specifies the single port RAM data setup. Used by the synthesis".
Setup Time [ps] Values: -2147483648, ..., 2147483647
Default Value: 350
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: RAM1P_ADDR_SU
Dual Port RAM Read Access Specifies the dual port RAM read access time. Used by the synthesis.
Time [ps] Values: -2147483648, ..., 2147483647
Default Value: 600
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: RAM2P_RD_ACCESS
Dual Port RAM Address/Data Specifies the dual port RAM data setup. Used by the synthesis.
Setup Time [ps] Values: -2147483648, ..., 2147483647
Default Value: 350
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: RAM2P_ADDR_SU
Synopsys, Inc.
Label Description
RAM Architecture
Single-port RAM model There are two possible architectures for the single-port RAMs used in the PCIe core:
architecture a) with a registered read port data output and b) with a registered read port address
input. coreConsultant will use this parameter to select the architecture used in the
single-port RAM models. It has no effect on the RTL implementation. Note: when
DesignWare RAMs are selected only registered read port data architecture is
supported for single-port RAMs
■ 0: Registered read port data output RAM model
■ 1: Registered read port address input RAM model
Values:
■ Registered Read Port Data Output (0)
■ Registered Read Port Address Input (1)
Default Value: Registered Read Port Data Output
Enabled: !(CX_RAM_TYPE==1)
Parameter Type: Feature Setting
Parameter Name: RAM1P_ARCH
Dual-port RAM model There are two possible architectures for the dual-port RAMs used in the PCIe core: a)
architecture with a registered read port data output and b) with a registered read port address
input. coreConsultant will use this parameter to select the architecture used in the
dual-port RAM models. It has no effect on the RTL implementation.
■ 0: Registered read port data output RAM model
■ 1: Registered read port address input RAM model
Values:
■ Registered Read Port Data Output (0)
■ Registered Read Port Address Input (1)
Default Value: Registered Read Port Data Output
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RAM2P_ARCH
Receive Queue RAM Output Specifies if a pipeline is inserted for the Receive Data/Header Queue RAM output
Pipeline signals.
This is a read-only signal for informational purposes. A non-optional read data retiming
register is always inserted on the RAM outputs.
Values:
■ No (0)
■ Yes (1)
Default Value: Yes
Enabled: 0
Parameter Type: Performance Setting
Parameter Name: CX_RAMQRAM_REGOUT_
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PCI Express SW Controller Databook Advanced RAM Config Parameters
Label Description
SOT RAM Output Pipeline Specifies if a pipeline is inserted for the SOT RAM output signals.
Values:
■ No (0)
■ Yes (1)
Default Value: ((CX_MAX_CORECLK_FREQ >= 500) && CX_RASDP > 0) ||
(CX_MAX_CORECLK_FREQ > 500)
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_RETRYSOTRAM_REGOUT
Retry RAM Output Pipeline Specifies if a pipeline is inserted for the Retry RAM output signals.
Values:
■ No (0)
■ Yes (1)
Default Value: ((CX_MAX_CORECLK_FREQ >= 500) && CX_RASDP > 0) ||
(CX_MAX_CORECLK_FREQ > 500)
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_RETRYRAM_REGOUT
RADM Receive Queue RAM Specifies the Receive Queue Header and Data RAM read cycle latency. The controller
Read Cycle Latency samples the read data CX_RADM_RAM_RD_LATENCY clock cycles after the read
address is valid at the Header/Data RADM RAM interface.
Note:The RAM read data is always retimed/registered.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_RADMQ_MODE==2
Parameter Type: Performance Setting
Parameter Name: CX_RADM_RAM_RD_LATENCY
Synopsys, Inc.
Label Description
Receive Serialization Queue Specifies the Receive Serialization Queue RAM read cycle latency. The controller
RAM Read Cycle Latency samples the read data CX_RADM_FORMQ_RAM_RD_LATENCY clock cycles after
the read address is valid at the RADM FORMQ RAM interface.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_NW==16
Parameter Type: Performance Setting
Parameter Name: CX_RADM_FORMQ_RAM_RD_LATENCY
Retry RAM Read Cycle Latency Specifies the Retry RAM read cycle latency. The controller samples the read data
CX_RETRY_RAM_RD_LATENCY clock cycles after the read address is valid. The
default of '1' corresponds to the typical read cycle access time for synchronous
memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
Default Value: 1 Cycle
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_RETRY_RAM_RD_LATENCY
SOT RAM Read Cycle Latency Specifies the Retry SOT RAM read cycle latency. The controller samples the read data
CX_RETRY_SOT_RAM_RD_LATENCY clock cycles after the read address is valid.
The default of '1' corresponds to the typical read cycle access time for synchronous
memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
Default Value: 1 Cycle
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_RETRY_SOT_RAM_RD_LATENCY
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PCI Express SW Controller Databook Advanced RAM Config Parameters
Label Description
AXI Master Completion Buffer Specifies the MCB RAM read cycle latency. The controller samples the read data
RAM Read Latency CC_MSTR_CPL_SEG_BUF_RAM_RD_LATENCY clock cycles after the read address
is valid. The default of '1' corresponds to the typical read cycle access time for
synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_MSTR_CPL_SEG_BUF_RAM_RD_LATENCY
AXI Slave Completion Composer Specifies the AXI Slave Completion Composer RAM read cycle latency. The controller
RAM Read Latency samples the read data CC_OB_CCMP_DATA_RAM_RD_LATENCY clock cycles after
the read address is valid. The default of '1' corresponds to the typical read cycle
access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Performance Setting
Parameter Name: CC_OB_CCMP_DATA_RAM_RD_LATENCY
AXI Slave Completion Composer Specifies the AXI Slave Completion Composer CDC RAM read cycle latency. The
CDC RAM Read Latency controller samples the read data CC_OB_CPL_C2A_CDC_RAM_RD_LATENCY clock
cycles after the read address is valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: SLV_CLK_DIFF_ENABLE && SLAVE_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_OB_CPL_C2A_CDC_RAM_RD_LATENCY
Synopsys, Inc.
Label Description
AXI Slave Posted Decomposer Specifies the AXI Slave Posted Decomposer RAM read cycle latency. The controller
RAM Read Latency samples the read data CC_OB_PDCMP_RAM_RD_LATENCY clock cycles after the
read address is valid. The default of '1' corresponds to the typical read cycle access
time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_OB_PDCMP_RAM_RD_LATENCY
AXI Slave Non-Posted Specifies the AXI Slave Non-Posted decomposer RAM read cycle latency. The
decomposer RAM Read Latency controller samples the read data CC_OB_NPDCMP_RAM_RD_LATENCY clock
cycles after the read address is valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_OB_NPDCMP_RAM_RD_LATENCY
AXI Slave Non-Posted Write Specifies the AXI Slave Non-Posted Write Set-Aside Buffer read cycle latency. The
Set-Aside Buffer Read Latency controller samples the read data CC_SLV_NPW_SAB_RAM_RD_LATENCY clock
cycles after the read address is valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_SLV_NPW_SAB_RAM_RD_LATENCY
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PCI Express SW Controller Databook Advanced RAM Config Parameters
Label Description
AXI Master Completion Buffer Specifies the AXI Master Completion Buffer CDC RAM read cycle latency. The
CDC RAM Read Latency controller samples the read data CC_MSTR_CPL_A2C_CDC_RAM_RD_LATENCY
clock cycles after the read address is valid. The default of '1' corresponds to the typical
read cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MASTER_POPULATED && AXI_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_IB_MCPL_CDC_RAM_RD_LATENCY
AXI Inbound Read Request CDC Specifies the AXI Inbound Read Request CDC RAM read cycle latency. The controller
RAM Read Latency samples the read data CC_IB_RD_REQ_CDC_RAM_RD_LATENCY clock cycles
after the read address is valid. The default of '1' corresponds to the typical read cycle
access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: SLV_CLK_DIFF_ENABLE && SLAVE_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_IB_RD_REQ_CDC_RAM_RD_LATENCY
AXI Inbound Write Request CDC Specifies the AXI Inbound Write Request CDC RAM read cycle latency. The controller
RAM Read Latency samples the read data CC_IB_WR_REQ_CDC_RAM_RD_LATENCY clock cycles
after the read address is valid. The default of '1' corresponds to the typical read cycle
access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: SLV_CLK_DIFF_ENABLE && SLAVE_POPULATED
Parameter Type: Performance Setting
Parameter Name: CC_IB_WR_REQ_CDC_RAM_RD_LATENCY
Synopsys, Inc.
Label Description
AXI Inbound Write Posted Specifies the AXI Inbound Write Posted Request Tracker RAM read cycle latency. The
Request Tracker RAM Read controller samples the read data CC_IB_WR_REQ_PTRK_RAM_RD_LATENCY clock
Latency cycles after the read address is valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: ((AMBA_INTERFACE==2) || (AMBA_INTERFACE==3))
Parameter Type: Performance Setting
Parameter Name: CC_IB_WR_REQ_PTRK_RAM_RD_LATENCY
DTIM AXI Stream Slave Request Specifies the DTIM AXI Stream Slave Request Queue RAM read cycle latency. The
Queue RAM Read Cycle Latency controller samples the read data CX_DTIM_REQQ_RAM_RD_LATENCY clock cycles
after the read address is valid at the DTIM AXI Stream Slave Request Queue RAM
interface.
Note:The RAM read data is always retimed/registered.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CC_DTIM_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_DTIM_REQQ_RAM_RD_LATENCY
MSIX Table RAM Read Cycle Specifies the internal MSIX table RAM read cycle latency. The controller samples the
Latency read data CX_MSIX_TABLE_RAM_RD_LATENCY clock cycles after the read address
is valid at the MSIX table RAM interface.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: MSIX_TABLE_EN==1
Parameter Type: Performance Setting
Parameter Name: CX_MSIX_TABLE_RAM_RD_LATENCY
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PCI Express SW Controller Databook Advanced RAM Config Parameters
Label Description
eDMA Read engine Linked List Specifies the RAM latency of the eDMA Linked List Controller of the Read engine. The
Controller RAM Read Cycle controller samples the read data CC_IF_RDCTRL_LL_RAM_LATENCY clock cycles
Latency after the read address been valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_RDCTRL_LL_RAM_LATENCY
eDMA Write engine Linked List Specifies the RAM latency of the eDMA Linked List Controller of the Write engine. The
Controller RAM Read Cycle controller samples the read data CC_IF_WRCTRL_LL_RAM_LATENCY clock cycles
Latency after the read address been valid. The default of '1' corresponds to the typical read
cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_WRCTRL_LL_RAM_LATENCY
eDMA Write engine Pre-Fetched Specifies the RAM latency of the eDMA Pre-Fetched Descriptor Queue of the Write
Descriptor Queue RAM Read engine. The controller samples the read data
Cycle Latency CC_IF_WRCTX_LLQ_OVERLAY_RAM_LATENCY clock cycles after the read
address been valid. The default of '1' corresponds to the typical read cycle access time
for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_WRCTX_LLQ_OVERLAY_RAM_LATENCY
Synopsys, Inc.
Label Description
eDMA Read engine Pre-Fetched Specifies the RAM latency of the eDMA Pre-Fetched Descriptor Queue of the Read
Descriptor Queue RAM Read engine. The controller samples the read data
Cycle Latency CC_IF_RDCTX_LLQ_OVERLAY_RAM_LATENCY clock cycles after the read address
been valid. The default of '1' corresponds to the typical read cycle access time for
synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_RDCTX_LLQ_OVERLAY_RAM_LATENCY
eDMA Read engine Memory Specifies the RAM latency of the eDMA Memory Read Context LUT of the Read
Read Context LUT RAM Read engine. The controller samples the read data CC_IF_RD_CTXC2W_RAM_LATENCY
Cycle Latency clock cycles after the read address been valid. The default of '1' corresponds to the
typical read cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_RD_CTXC2W_RAM_LATENCY
eDMA Write engine Memory Specifies the RAM latency of the eDMA Memory Read Context LUT of the Write
Read Context LUT RAM Read engine. The controller samples the read data CC_IF_WR_CTXC2W_RAM_LATENCY
Cycle Latency clock cycles after the read address been valid. The default of '1' corresponds to the
typical read cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_WR_CTXC2W_RAM_LATENCY
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PCI Express SW Controller Databook Advanced RAM Config Parameters
Label Description
eDMA Read engine Memory Specifies the RAM latency of the eDMA Memory Write Context LUT of the Read
Write Context LUT RAM Read engine. The controller samples the read data CC_IF_RD_CTXSTSH_RAM_LATENCY
Cycle Latency clock cycles after the read address been valid. The default of '1' corresponds to the
typical read cycle access time for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_RD_CTXSTSH_RAM_LATENCY
eDMA Write engine Memory Specifies the RAM latency of the eDMA Memory Write Context LUT of the Write
Write Context LUT RAM Read engine. The controller samples the read data
Cycle Latency CC_IF_WR_CTXSTSH_RAM_LATENCY clock cycles after the read address been
valid. The default of '1' corresponds to the typical read cycle access time for
synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_WR_CTXSTSH_RAM_LATENCY
eDMA Read engine MSI setup Specifies the RAM latency of the MSI setup of the Read engine. The controller
RAM Read Cycle Latency samples the read data CC_IF_RD_MSI_RAM_LATENCY clock cycles after the read
address been valid. The default of '1' corresponds to the typical read cycle access time
for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_RD_MSI_RAM_LATENCY
Synopsys, Inc.
Label Description
eDMA Write engine MSI setup Specifies the RAM latency of the MSI setup of the Write engine. The controller
RAM Read Cycle Latency samples the read data CC_IF_WR_MSI_RAM_LATENCY clock cycles after the read
address been valid. The default of '1' corresponds to the typical read cycle access time
for synchronous memories.
Values:
■ 1 Cycle (1)
■ 2 Cycles (2)
■ 3 Cycles (3)
■ 4 Cycles (4)
Default Value: 1 Cycle
Enabled: CX_DMA_PF_ENABLE
Parameter Type: Performance Setting
Parameter Name: CC_IF_WR_MSI_RAM_LATENCY
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PCI Express SW Controller Databook Advanced PHY Config / General Options Parameters
Label Description
General Options
Elasticity Buffer Mode Determines Elasticity Buffer Mode. Contact your PHY vendor for the value that you
should use. Only applicable to configurations not using a Frequency Step.
Values:
■ Nominal Half Full Buffer Mode (0)
■ Nominal Empty Buffer Mode (1)
Default Value: [<functionof>] && (CX_FREQ_STEP_EN==0 ||
CX_PIPERX_MULTI_BLOCK==1) && CX_GEN3_SPEED
Enabled: (CX_CPCIE_ENABLE==1 && (CX_FREQ_STEP_EN==0 ||
CX_PIPERX_MULTI_BLOCK==1) && CX_GEN3_SPEED)
Parameter Type: Feature Setting
Parameter Name: CX_PIPE_HYBRID_MODE
Selectable De-emphasis Selectable De-emphasis. Only for Gen2 downstream ports operating at 5 GT/s. This
bit selects the level of de-emphasis the link operates at. M-PCIe doesn't support this
feature.
Values:
■ -6 dB (0x0)
■ -3.5 dB (0x1)
Default Value: -6 dB
Enabled: CX_GEN2_SPEED==1 && CX_CPCIE_ENABLE &&
CC_DEVICE_TYPE!=CC_EP
Parameter Type: Feature Setting
Parameter Name: SEL_DE_EMPHASIS
Max PCLK frequency (MHz) Frequency (in MHz) of the max_pclk output clock from the PHY. Contact your PHY
vendor for the value that you should use.
Values:
■ MaxPclk not available (0)
■ 250 MHz (250)
■ 500 MHz (500)
■ 1 GHz (1000)
■ 2 GHz (2000)
■ 4 GHz (4000)
Default Value: MaxPclk not available
Enabled: Always
Parameter Name: CX_PHY_MAX_PCLK_FREQ_MHZ
Synopsys, Inc.
Label Description
RxStandby Control
RxStandby Signal Default Default value of RxStandby signal (mac_phy_rxstandby) on all lanes after reset.
Note: Contact your PHY vendor for guidelines on how to properly configure the
RxStandby behavior. Refer to the User Guidefor guidelines on how to configure this
parameter for Synopsys PHYs.
Values:
■ 0 (0x0)
■ 1 (0x1)
Default Value: PHY_TYPE==CC_GENERIC_PHY
Enabled: CX_CPCIE_ENABLE && PHY_TYPE!=CC_GENERIC_PHY
Parameter Type: Feature Setting
Parameter Name: CX_RXSTANDBY_DEFAULT
RxStandby Signal Operation Bits 0..5 determine if the controller asserts the RxStandby signal
Control (mac_phy_rxstandby) in the indicated condition.
Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake.
■ [0]: Rx EIOS and subsequent T TX-IDLE-MIN
■ [1]: Rate Change
■ [2]: Inactive lane for upconfigure/downconfigure
■ [3]: PowerDown=P1,P1.CPM,P1.1,P1.2 or P2 (When CX_PIPE43_SUPPORT==1,
this bit must be set to 0)
■ [4]: RxL0s.Idle
■ [5]: EI Infer in L0
■ [6]: Execute RxStandby/RxStandbyStatus Handshake
Note: Contact your PHY vendor for guidelines on how to properly configure the
RxStandby behavior. Refer to the User Guidefor guidelines on how to configure this
parameter for Synopsys PHYs.
Values: 0x0, ..., 0x7f
Default Value: (PHY_TYPE==CC_GENERIC_PHY) ? 0x7F :
(SNPS_RSVDPARAM_26) ? 0x7F : 0x44
Enabled: CX_CPCIE_ENABLE && PHY_TYPE!=CC_GENERIC_PHY
Parameter Type: Feature Setting
Parameter Name: CX_RXSTANDBY_CONTROL
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PCI Express SW Controller Databook Advanced PHY Config / General Options Parameters
Label Description
PHY Register Viewport and Enables PHY register viewport and PRBI/CRPI for Synpsys PHY. The controller
PRBI/CRPI. implements the PHY register viewport in its Port Logic register space, and the Register
Bus Interface (PRBI) which communicates with the Phy's Control Register Parallel
Interface (CRPI), to enable access to registers in the PHY. The PHY registers can be
indirectly written to and read from through a configuration wire access or local DBI
access. This feature can be used with Synopsys PHYs that have the Control Register
Parallel Interface and not for PIPE Message Bus Interface. For more details, see "PHY
Port Logic Registers" in the "Register Module, LBC, and DBI" section in the Controller
Operations chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: !(CX_PL_REG_DISABLE) && CX_CPCIE_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_PHY_VIEWPORT_ENABLE
P2.NoBeacon Enable Enable support for P2.NoBeacon. When this parameter is set, mac_phy_powerdown
drives P2.NoBeacon encoding, instead of P2 encoding, when the link goes to L2.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_PIPE_VER>=1
Parameter Type: Feature Setting
Parameter Name: CX_P2NOBEACON_ENABLE
P2.CPM Encoding Powerdown state encoding on the mac_phy_powerdown[3:0] output for P2.NoBeacon.
Contact your PHY vendor for the value that you should use.
Values: 0x0, ..., 0xf
Default Value: 0xf
Enabled: CX_P2NOBEACON_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: CX_PIPE43_P2NOBEACON_ENCODING
Synopsys, Inc.
Label Description
PHY Timing
Number of Fast Training (NFTS) Specifies the number of Fast Training Sequences the controller advertises during link
Sequences training. This is used to inform the link partner of the cores ability to recover
synchronization after a low power state. This number should come from your PHY
vendor. This parameter sets the default value of the N_FTS field of the 'Ack Frequency
and L0-L1 ASPM Control Register' in the Register section of the Databook. M-PCIe
doesn't use this parameter.
Values: 1, ..., 255
Default Value: ((CX_MAX_PCIE_SPEED==1) ? CX_PHY_NB_GEN1 :
(CX_MAX_PCIE_SPEED==2) ? CX_PHY_NB_GEN2 : (CX_MAX_PCIE_SPEED==3)
? CX_PHY_NB_GEN3 : (CX_MAX_PCIE_SPEED==4) ? CX_PHY_NB_GEN4 :
(CX_MAX_PCIE_SPEED==5) ? CX_PHY_NB_GEN5 : CX_PHY_NB_GEN5>8) ? 32 :
15
Enabled: CX_S_CPCIE_MODE || CX_SEL_PHY_MODE
Parameter Type: Register Default Setting
Parameter Name: CX_NFTS
NFTS when using common clock Specifies the number of Fast Training Sequences (NFTS) the controller advertises
during link training, when common clock configuration is set.
This parameter sets the default value of the 'Common Clock N_FTS' field of the 'Ack
Frequency and L0-L1 ASPM Control Register' in the Register section of the Databook.
Common Clock operation cannot be fully enabled (through the Common Clock
Configuration field of the Link Control register) unless you observe the following
configuration parameter relationships:
■ CX_NFTS != CX_COMM_NFTS
■ DEFAULT_L0S_EXIT_LATENCY != DEFAULT_COMM_L0S_EXIT_LATENCY
■ DEFAULT_L1_EXIT_LATENCY != DEFAULT_COMM_L1_EXIT_LATENCY
Default value is set automatically unless Custom PHY or Sample PHY is used. M-PCIe
doesn't use this parameter.
Values: 1, ..., 255
Default Value: CX_NFTS
Enabled: CX_CPCIE_ENABLE && SLOT_CLK_CONFIG
Parameter Type: Register Default Setting
Parameter Name: CX_COMM_NFTS
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PCI Express SW Controller Databook Advanced PHY Config / PHY Timing Parameters
Label Description
NFTS Sequences at 5 Gb/s Specifies the number of Fast Training Sequences (NFTS) the controller advertises
during link training when running at Gen 2 speed. This is used to inform the link
partner the cores ability to recover synchronization after a low power state. This
number should come from your PHY vendor. This parameter is for Conventional PCIe
mode only; M-PCIe doesn't use this parameter.
Values: 0, ..., 255
Default Value: CX_NFTS
Enabled: (CX_CPCIE_ENABLE && (CX_GEN2_SPEED == 1))
Parameter Type: Feature Setting
Parameter Name: DEFAULT_GEN2_N_FTS
PHY Tx Delay PHY Transmitter delay in clock cycles. This must be specified by your PHY provider
and is the (worst case) delay in PIPE clock cycles from the PIPE interface to the TX
Phy serial pins. This parameter in conjunction with 'PHY Rx Delay' is used to calculate
the delay in getting an ACK DLLP back from the link partner, for a TLP sent by your
core. It is then used to calculate the size of the Retry Buffer. This parameter is for
Conventional PCIe mode only; M-PCIe doesn't use this parameter.
Values: 0, ..., 500
Default Value: 6
Enabled: CX_S_CPCIE_MODE || CX_SEL_PHY_MODE
Parameter Type: Feature Setting
Parameter Name: CX_PHY_TX_DELAY_PHY
PHY Rx Delay PHY Receiver delay in clock cycles. This must be specified by your PHY provider and
is the (worst case) delay in PIPE clock cycles from the RX Phy serial pins to the PIPE
interface. This parameter in conjunction with 'PHY Tx Delay' is used to calculate the
delay in getting an ACK DLLP back from the link partner, for a TLP sent by your
controller It is then used to calculate the size of the Retry Buffer. This parameter is for
Conventional PCIe mode only ; M-PCIe doesn't use this parameter.
Values: 0, ..., 500
Default Value: 14
Enabled: CX_S_CPCIE_MODE || CX_SEL_PHY_MODE
Parameter Type: Feature Setting
Parameter Name: CX_PHY_RX_DELAY_PHY
Synopsys, Inc.
Label Description
General Config
Gen3 controller as EQ Master When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the
Asserts RxEqEval for PHY to do PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset
Rx adaptation and Evaluation request.
Regardless of Rx TS1s Detection This is the default of the RXEQ_RGRDLESS_RXTS field in GEN3_RELATED_OFF
when in Gen3 mode.
Values:
■ No (0)
■ Yes (1)
Default Value: Yes
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_RXEQ_RGRDLESS_RXTS
Gen3 EQ Include Initial FOM Gen3 EQ Include Initial FOM. Include or not the FOM feedback from the initial preset
evaluation performed in the EQ Master, when finding the highest FOM among all
preset evaluations.
■ 0: Do not include
■ 1: Include
This is the default of the GEN3_EQ_FOM_INC_INITIAL_EVAL field in
GEN3_EQ_CONTROL_OFF when in Gen3 mode.
Values: 0, 1
Default Value: 0
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FOM_INC_INITIAL_EVAL
Gen3 EQ Preset Request Vector Gen3 EQ Preset Request Vector. Requesting of Presets during the initial part of the
EQ Master Phase. Encoding scheme is as follows:
■ Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase.
■ Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase.
This is the default of the GEN3_EQ_PSET_REQ_VEC field in
GEN3_EQ_CONTROL_OFF when in Gen3 mode. You must contact your PHY vendor
to ensure 24 ms timeout does not occur in presets (FOM) requests in EQ master
phase.
Values: 0x0, ..., 0x7ff
Default Value: 0x59f
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_PSET_REQ_VEC
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PCI Express SW Controller Databook Advanced PHY Config / Gen3 PHY Equalization Config Parameters
Label Description
Gen3 EQ Master Phase Exit Gen3 EQ Master Phase Exit Mode After 24 ms Timeout
Mode ■ 0b: Exit to Recovery.Speed state
■ 1b: Exit to EQ Phase 3 for USP controller or Recovery.RcvrLock state for DSP core
This is the default of the GEN3_EQ_PHASE23_EXIT_MODE field in
GEN3_EQ_CONTROL_OFF when in Gen3 mode. Setting to '1b' affects Direction
Change EQ Feedback Mode. EQ requests for Figure Of Merit mode complete before
24 ms timeout. See DEFAULT_GEN3_EQ_PSET_REQ_VEC for more.
Values:
■ To Recovery.Speed (0)
■ To EQ 3 for USP or to Recovery.RcvrLock for DSP (1)
Default Value: To Recovery.Speed
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_PHASE23_EXIT_MODE
Synopsys, Inc.
Label Description
Gen3/Gen4/Gen5 EQ Presets to For Gen3/Gen4/Gen5 equalization, there are three possible implementations for the
Coefficients Mapping Modes mapping of presets to coefficients:
■ Dynamic PHY: The coefficients are dynamically mapped in the PHY.
■ Dynamic MAC: The coefficients are dynamically mapped in the MAC.
■ Programmable Table: The coefficients are programmed in a table by your applica-
tion.
The coefficients obtained from a preset are then used to drive the
mac_phy_txdeemph[17:0] output in the transmit path of the relevant port.
Note:Gen3 and Gen4 cannot use different mapping modes.
Values:
■ Dynamic PHY (0)
■ Dynamic MAC (1)
■ Programmable Table (2)
Default Value: Dynamic PHY
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Feature Setting
Parameter Name: CX_GEN3_EQ_PSET_COEF_MAP_MODE
Gen3 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local FS Value Table, this parameter is used to set the default local Full Swing (FS) value for Gen3
data rate. The FS value is specific to the PHY implementation. It is needed by the
controller because it is advertised during Gen3 equalization Phase 1, and it is used to
determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section 4.2.3.1 of the PCI Express Base Specification, Rev 3.0. This is
the default of the GEN3_EQ_LOCAL_FS field in GEN3_EQ_LOCAL_FS_LF_OFF
when in Gen3 mode.
Values: 12, ..., 63
Default Value: 48
Enabled: CX_GEN3_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_LOCAL_FS
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PCI Express SW Controller Databook Advanced PHY Config / Gen3 PHY Equalization Config Parameters
Label Description
Gen3 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local LF Value Table, this parameter is used to set the default local Low Frequency (LF) value for
Gen3 data rate. The LF value is specific to the PHY implementation. It is needed by
the controller because it is advertised during Gen3 equalization Phase1, and it is used
to determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section 4.2.3.1 of the PCI Express Base Specification, Rev 3.0. This is
the default of the GEN3_EQ_LOCAL_LF field in GEN3_EQ_LOCAL_FS_LF_OFF
when in Gen3 mode.
Values: 0, ..., 63
Default Value: 24
Enabled: CX_GEN3_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_LOCAL_LF
Gen3 EQ Coefficient When enabled the controller implements additional logic for checking that the fine
Convergence Support tuning process of the remote transmitter that is executed during Phase 2 (when
controller is USP) or Phase 3 (core is DSP) is converging toward a stable point. This
setting is both for Gen3 and Gen4. Gen3 and Gen4 cannot have different settings.
Values:
■ false (0)
■ true (1)
Default Value: CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0
Enabled: ((CX_SEL_PHY_MODE ? (CX_MAX_CPCIE_SPEED >= 3) :
CX_S_CPCIE_MODE ? (CX_GEN3_MODE != GEN3_DISABLED) : 0))
Parameter Type: Feature Setting
Parameter Name: CX_GEN3_EQ_COEF_CONV_SUPPORTED
Synopsys, Inc.
Label Description
Gen3 EQ Convergence Window Gen3 EQ Convergence Window Aperture for C+1. Post-cursor coefficients maximum
Aperture for C+1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen3 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN3_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA
Gen3 EQ Convergence Window Gen3 EQ Convergence Window Aperture for C-1. Pre-cursor coefficients maximum
Aperture for C-1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen3 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN3_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA
Gen3 EQ Convergence Window Gen3 EQ Convergence Window Depth. Number of consecutive evaluations
Depth considered in Phase 2/3 when determining if optimal coefficients have been found.
This is the default of the GEN3_EQ_FMDC_N_EVALS field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen3 mode.
Values: 0, ..., 16
Default Value: 2
Enabled: (CX_GEN3_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FMDC_N_EVALS
Gen3 EQ Minimum Time (in ms) Gen3 EQ Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in
To Remain in EQ Master Phase EQ Master phase for at least this amount of time, before starting to check for
convergence of the coefficients. This is the default of the
GEN3_EQ_FMDC_T_MIN_PHASE23 field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen3 mode.
Values: 0, ..., 24
Default Value: 0
Enabled: (CX_GEN3_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN3_EQ_FMDC_T_MIN_PHASE23
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PCI Express SW Controller Databook Advanced PHY Config / Gen4 PHY Equalization Config Parameters
Label Description
General Config
Gen4 controller as EQ Master When set to '1', the controller as Gen4 EQ master asserts RxEqEval to instruct the
Asserts RxEqEval for PHY to do PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset
Rx Adaptation and Evaluation request.
Regardless of Rx TS1s Detection This is the default of the RXEQ_RGRDLESS_RXTS field in GEN3_RELATED_OFF
when in Gen4 mode.
Values:
■ No (0)
■ Yes (1)
Default Value: Yes
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_RXEQ_RGRDLESS_RXTS
Gen4 EQ Include Initial FOM Gen4 EQ Include Initial FOM. Include or not the FOM feedback from the initial preset
evaluation performed in the EQ Master, when finding the highest FOM among all
preset evaluations.
■ 0: Do not include
■ 1: Include
This is the default of the GEN3_EQ_FOM_INC_INITIAL_EVAL field in
GEN3_EQ_CONTROL_OFF when in Gen4 mode.
Values: 0, 1
Default Value: 0
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FOM_INC_INITIAL_EVAL
Gen4 EQ Preset Request Vector Gen4 EQ Preset Request Vector. Requesting of Presets during the initial part of the
EQ Master Phase. Encoding scheme is as follows:
■ Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase.
■ Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase.
This is the default of the GEN3_EQ_PSET_REQ_VEC field in
GEN3_EQ_CONTROL_OFF when in Gen4 mode. You must contact your PHY vendor
to ensure 24 ms timeout does not occur in presets (FOM) requests in EQ master
phase.
Values: 0x0, ..., 0x7ff
Default Value: 0x59f
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_PSET_REQ_VEC
Synopsys, Inc.
Label Description
Gen4 EQ Master Phase Exit Gen4 EQ Master Phase Exit Mode After 24 ms Timeout
Mode ■ 0b: Exit to Recovery.Speed state
■ 1b: Exit to EQ Phase 3 for USP controller or Recovery.RcvrLock state for DSP core
This is the default of the GEN3_EQ_PHASE23_EXIT_MODE field in
GEN3_EQ_CONTROL_OFF when in Gen4 mode. Setting to '1b' affects Direction
Change EQ Feedback Mode. EQ requests for Figure Of Merit mode complete before
24 ms timeout. See DEFAULT_GEN4_EQ_PSET_REQ_VEC for more.
Values:
■ To Recovery.Speed (0)
■ To EQ 3 for USP or to Recovery.RcvrLock for DSP (1)
Default Value: To Recovery.Speed
Enabled: ((CX_GEN4_MODE != GEN4_DISABLED))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_PHASE23_EXIT_MODE
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PCI Express SW Controller Databook Advanced PHY Config / Gen4 PHY Equalization Config Parameters
Label Description
Gen4 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local FS Value Table, this parameter is used to set the default local Full Swing (FS) value for Gen4
data rate. The FS value is specific to the PHY implementation. It is needed by the
controller because it is advertised during Gen4 equalization Phase 1, and it is used to
determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section TBD of the PCI Express Base Specification, Rev 4.0. This is the
default of the GEN3_EQ_LOCAL_FS field in GEN3_EQ_LOCAL_FS_LF_OFF when
in Gen4 mode.
Values: 12, ..., 63
Default Value: 48
Enabled: CX_GEN4_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_LOCAL_FS
Gen4 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local LF Value Table, this parameter is used to set the default local Low Frequency (LF) value for
Gen4 data rate. The LF value is specific to the PHY implementation. It is needed by
the controller because it is advertised during Gen4 equalization Phase1, and it is used
to determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section TBD of the PCI Express Base Specification, Rev 4.0. This is the
default of the GEN3_EQ_LOCAL_LF field in GEN3_EQ_LOCAL_FS_LF_OFF when in
Gen4 mode.
Values: 0, ..., 63
Default Value: 24
Enabled: CX_GEN4_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_LOCAL_LF
Gen4 EQ Convergence Window Gen4 EQ Convergence Window Aperture for C+1. Post-cursor coefficients maximum
Aperture for C+1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen4 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN4_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FMDC_MAX_POST_CUSROR_DELTA
Synopsys, Inc.
Label Description
Gen4 EQ Convergence Window Gen4 EQ Convergence Window Aperture for C-1. Pre-cursor coefficients maximum
Aperture for C-1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen4 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN4_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FMDC_MAX_PRE_CUSROR_DELTA
Gen4 EQ Convergence Window Gen4 EQ Convergence Window Depth. Number of consecutive evaluations
Depth considered in Phase 2/3 when determining if optimal coefficients have been found.
This is the default of the GEN3_EQ_FMDC_N_EVALS field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen4 mode.
Values: 0, ..., 16
Default Value: 2
Enabled: (CX_GEN4_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FMDC_N_EVALS
Gen4 EQ Minimum Time (in ms) Gen4 EQ Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in
To Remain in EQ Master Phase EQ Master phase for at least this amount of time, before starting to check for
convergence of the coefficients. This is the default of the
GEN3_EQ_FMDC_T_MIN_PHASE23 field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen4 mode.
Values: 0, ..., 24
Default Value: 0
Enabled: (CX_GEN4_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN4_EQ_FMDC_T_MIN_PHASE23
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PCI Express SW Controller Databook Advanced PHY Config / Gen5 PHY Equalization Config Parameters
Label Description
General Config
Gen5 controller as EQ Master When set to '1', the controller as Gen5 EQ master asserts RxEqEval to instruct the
Asserts RxEqEval for PHY to do PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset
Rx Adaptation and Evaluation request.
Regardless of Rx TS1s Detection This is the default of the RXEQ_RGRDLESS_RXTS field in GEN3_RELATED_OFF
when in Gen5 mode.
Values:
■ No (0)
■ Yes (1)
Default Value: Yes
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_RXEQ_RGRDLESS_RXTS
Gen5 EQ Include Initial FOM Gen5 EQ Include Initial FOM. Include or not the FOM feedback from the initial preset
evaluation performed in the EQ Master, when finding the highest FOM among all
preset evaluations.
■ 0: Do not include
■ 1: Include
This is the default of the GEN3_EQ_FOM_INC_INITIAL_EVAL field in
GEN3_EQ_CONTROL_OFF when in Gen5 mode.
Values: 0, 1
Default Value: 0
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FOM_INC_INITIAL_EVAL
Gen5 EQ Preset Request Vector Gen5 EQ Preset Request Vector. Requesting of Presets during the initial part of the
EQ Master Phase. Encoding scheme is as follows:
■ Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase.
■ Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase.
This is the default of the GEN3_EQ_PSET_REQ_VEC field in
GEN3_EQ_CONTROL_OFF when in Gen5 mode. You must contact your PHY vendor
to ensure 24 ms timeout does not occur in presets (FOM) requests in EQ master
phase.
Values: 0x0, ..., 0x7ff
Default Value: 0x59f
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_PSET_REQ_VEC
Synopsys, Inc.
Label Description
Gen5 EQ Master Phase Exit Gen5 EQ Master Phase Exit Mode After 24 ms Timeout
Mode ■ 0b: Exit to Recovery.Speed state
■ 1b: Exit to EQ Phase 3 for USP controller or Recovery.RcvrLock state for DSP core
This is the default of the GEN3_EQ_PHASE23_EXIT_MODE field in
GEN3_EQ_CONTROL_OFF when in Gen5 mode. Setting to '1b' affects Direction
Change EQ Feedback Mode. EQ requests for Figure Of Merit mode complete before
24 ms timeout. See DEFAULT_GEN5_EQ_PSET_REQ_VEC for more.
Values:
■ To Recovery.Speed (0)
■ To EQ 3 for USP or to Recovery.RcvrLock for DSP (1)
Default Value: To Recovery.Speed
Enabled: ((CX_MAX_PCIE_SPEED >= 5))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_PHASE23_EXIT_MODE
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PCI Express SW Controller Databook Advanced PHY Config / Gen5 PHY Equalization Config Parameters
Label Description
Gen5 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local FS Value Table, this parameter is used to set the default local Full Swing (FS) value for Gen5
data rate. The FS value is specific to the PHY implementation. It is needed by the
controller because it is advertised during Gen5 equalization Phase 1, and it is used to
determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section TBD of the PCI Express Base Specification, Rev 5.0. This is the
default of the GEN3_EQ_LOCAL_FS field in GEN3_EQ_LOCAL_FS_LF_OFF when
in Gen5 mode.
Values: 12, ..., 63
Default Value: 48
Enabled: CX_GEN5_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_LOCAL_FS
Gen5 EQ Programmable Default When the Gen3 Equalization Presets to Coefficients Mapping Mode is Programmable
Local LF Value Table, this parameter is used to set the default local Low Frequency (LF) value for
Gen5 data rate. The LF value is specific to the PHY implementation. It is needed by
the controller because it is advertised during Gen5 equalization Phase1, and it is used
to determine if the coefficients meet the rules, as described in Rules for Transmitter
Coefficients, section TBD of the PCI Express Base Specification, Rev 5.0. This is the
default of the GEN3_EQ_LOCAL_LF field in GEN3_EQ_LOCAL_FS_LF_OFF when in
Gen5 mode.
Values: 0, ..., 63
Default Value: 24
Enabled: CX_GEN5_SPEED && CX_GEN3_EQ_PSET_COEF_MAP_MODE==2
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_LOCAL_LF
Gen5 EQ Convergence Window Gen5 EQ Convergence Window Aperture for C+1. Post-cursor coefficients maximum
Aperture for C+1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen5 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN5_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FMDC_MAX_POST_CUSROR_DELTA
Synopsys, Inc.
Label Description
Gen5 EQ Convergence Window Gen5 EQ Convergence Window Aperture for C-1. Pre-cursor coefficients maximum
Aperture for C-1. delta within the convergence window depth. This is the default of the
GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen5 mode.
Values: 0, ..., 15
Default Value: 0
Enabled: (CX_GEN5_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FMDC_MAX_PRE_CUSROR_DELTA
Gen5 EQ Convergence Window Gen5 EQ Convergence Window Depth. Number of consecutive evaluations
Depth considered in Phase 2/3 when determining if optimal coefficients have been found.
This is the default of the GEN3_EQ_FMDC_N_EVALS field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen5 mode.
Values: 0, ..., 16
Default Value: 2
Enabled: (CX_GEN5_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FMDC_N_EVALS
Gen5 EQ Minimum Time (in ms) Gen5 EQ Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in
To Remain in EQ Master Phase EQ Master phase for at least this amount of time, before starting to check for
convergence of the coefficients. This is the default of the
GEN3_EQ_FMDC_T_MIN_PHASE23 field in
GEN3_EQ_FB_MODE_DIR_CHANGE_OFF when in Gen5 mode.
Values: 0, ..., 24
Default Value: 0
Enabled: (CX_GEN5_SPEED && (CX_GEN3_EQ_COEF_CONV_SUPPORTED ==
1))
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_GEN5_EQ_FMDC_T_MIN_PHASE23
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PCI Express SW Controller Databook Advanced PHY Config / PHY Lane Margining Config Parameters
Label Description
Lane Margining
Number of Time Steps from Number of time steps from default (MNumTimingSteps). This is an implementation
Default (MNumTimingSteps) specific parameter specified in PCI Express Base Specification. Contact your PHY
vendor for the value that you should use.
Values: 6, ..., 63
Default Value: 6
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_NUM_TIMING_STEPS
Offset from Default at Maximum Offset from default at maximum step value (MMaxTimingOffset). This is an
Step Value (MMaxTimingOffset) implementation specific parameter specified in PCI Express Base Specification.
Contact your PHY vendor for the value that you should use.
Values: 0, ..., 50
Default Value: 20
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_MAX_TIMING_OFFSET
Number of Voltage Steps from Number of voltage steps from default (MNumVoltageSteps). This is an implementation
Default (MNumVoltageSteps) specific parameter specified in PCI Express Base Specification. Contact your PHY
vendor for the value that you should use.
Values: 32, ..., 127
Default Value: 32
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_NUM_VOLTAGE_STEPS
Offset from Default at Maximum Offset from default at maximum step value as percentage of one volt
Step Value as Percentage of One (MMaxVoltageOffset). This is an implementation specific parameter specified in PCI
Volt (MMaxVoltageOffset) Express Base Specification. Contact your PHY vendor for the value that you should
use.
Values: 0, ..., 50
Default Value: 5
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_MAX_VOLTAGE_OFFSET
Synopsys, Inc.
Label Description
The Ratio of Bits Tested to Bits The ratio of bits tested to bits received during voltage margining
Received During Voltage (MSamplingRateVoltage). This is an implementation specific parameter specified in
Margining PCI Express Base Specification. Contact your PHY vendor for the value that you
(MSamplingRateVoltage) should use. Note that if MIndErrorSampler = 0, the core always reports
MSamplingRateVoltage=0x3F regardless of this parameter value when the core
receives Report MSamplingRateVoltage Command from System Software.
Values: 0, ..., 63
Default Value: 0
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_SAMPLE_RATE_VOLTAGE
The Ratio of Bits Tested to Bits The ratio of bits tested to bits received during timing margining
Received During Timing (MSamplingRateTiming). This is an implementation specific parameter specified in
Margining PCI Express Base Specification. Contact your PHY vendor for the value that you
(MSamplingRateTiming) should use. Note that if MIndErrorSampler = 0, the core always reports
MSamplingRateTiming=0x3F regardless of this parameter value when the core
receives Report MSamplingRateTiming Command from System Software.
Values: 0, ..., 63
Default Value: 0
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_SAMPLE_RATE_TIMING
Independent Left/Right Timing Independent left/right timing margin supported (MIndLeftRightTiming). This is an
Margin Supported implementation specific parameter specified in PCI Express Base Specification.
(MIndLeftRightTiming) Contact your PHY vendor for the value that you should use.
Values: 0, 1
Default Value: 1
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_IND_LEFT_RIGHT_TIMING
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PCI Express SW Controller Databook Advanced PHY Config / PHY Lane Margining Config Parameters
Label Description
Independent Up and Down Independent up and down voltage margining supported (MIndUpDownVoltage). This is
Voltage Margining Supported an implementation specific parameter specified in PCI Express Base Specification.
(MIndUpDownVoltage) Contact your PHY vendor for the value that you should use.
Values: 0, 1
Default Value: 1
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_IND_UP_DOWN_VOLTAGE
Independent Error Sampler Indicates Error sampler is independent (MIndErrorSampler). This is an implementation
(MIndErrorSampler) specific parameter specified in PCI Express Base Specification. Contact your PHY
vendor for the value that you should use.
Values: 0, 1
Default Value: 1
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_IND_ERROR_SAMPLER
Sample Reporting Method Indicates whether a sample frequency is supported (1) or a sample count is supported
(MSampleReportingMethod) (0) (MSampleReportingMethod). This is an implementation specific parameter
specified in PCI Express Base Specification. Contact your PHY vendor for the value
that you should use. Note that if MIndErrorSampler = 0, the core always reports
MSampleReportingMethod=1 regardless of this parameter value when the core
receives Report Margin Control Capabilities Command from System Software.
Values: 0, 1
Default Value: 0
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_SAMPLE_REPORTING_METHOD
Maximum Number of Lanes that Maximum number of lanes minus 1 that can be margined at the same time
can be Margined at the Same (MMaxLanes). This is an implementation specific parameter specified in PCI Express
Time (MMaxLanes) Base Specification. Contact your PHY vendor for the value that you should use.
Values: 0, ..., 31
Default Value: 1
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RXMARGIN_MAXLANES
Margining Uses Driver Software Default value of Margining Uses Driver Software. This is an implementation specific
parameter specified in PCI Express Base Specification. Contact your PHY vendor for
the value that you should use.
Values: 0, 1
Default Value: 0
Enabled: SNPS_RSVDPARAM_22
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_MARGINING_USES_DRIVER_SOFTWARE
Synopsys, Inc.
Label Description
Message Bus
RX Message Bus Write Buffer Default value of RX Message Bus Write Buffer Depth. This is an implementation
Depth specific parameter specified in PIPE Specification. Contact your PHY vendor for the
value that you should use.
Values: 0, ..., 15
Default Value: (CX_PIPE51_SUPPORT) ? 5 : (CX_PIPE44_SUPPORT) ? 2 : 0
Enabled: (CX_GEN4_SPEED && CX_PIPE44_SUPPORT) || CX_PIPE51_SUPPORT
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH
TX Message Bus Min Write Default value of TX Message Bus Minimum Write Buffer Depth. This is an
Buffer Depth implementation specific parameter specified in PIPE Specification. Contact your PHY
vendor for the value that you should use.
Values: 0, ..., 8
Default Value: (CX_PIPE51_SUPPORT) ? 5 : (CX_PIPE44_SUPPORT) ? 2 : 0
Enabled: (CX_GEN4_SPEED && CX_PIPE44_SUPPORT) || CX_PIPE51_SUPPORT
Parameter Type: Register Default Setting
Parameter Name: DEFAULT_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH
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PCI Express SW Controller Databook Advanced Transmit Config Parameters
Label Description
CX_BLOCK_VDM_TLP Block transmit of VDM Messages when in a non-D0 state. For more details, see the
'Power Management' section of the Architecture chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_BLOCK_VDM_TLP
Block CCIX Transmit Interface Block outbound transactions on CCIX interface when in low power modes. For more
details, see the 'Power Management' section of the Architecture chapter of the
Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: AMBA_INTERFACE==0 && CC_DEVICE_TYPE!=CC_RC &&
CX_CCIX_INTERFACE_ENABLE==1
Parameter Type: Feature Setting
Parameter Name: CX_CCIX_BLOCK_NEW_TLP
General Config
Block Client 0 Interface Block outbound transactions on XALI0 when in low power modes. For more details,
see the 'Power Management' section of the Architecture chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_CLIENT0_BLOCK_NEW_TLP
Synopsys, Inc.
Label Description
Block Client 1 Interface Block outbound transactions on XALI1 when in low power modes. For more details,
see the 'Power Management' section of the Architecture chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_CLIENT1_BLOCK_NEW_TLP
Block Client 2 Interface Block outbound transactions on XALI2 when in low power modes. For more details,
see the 'Power Management' section of the Architecture chapter of the Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: false
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_CLIENT2_BLOCK_NEW_TLP
Populate ports for available credit Include top-level ports to provide available credit information to the application. For
buses more details, see 'SII: Transmit Control Signals' section of the Databook. This
parameter enables the population of output ports for application monitoring of run-time
available credit information for VCn buses:
■ xadm_ph_cdts [NVC*8-1:0] : available VC0-VCn header posted credits
■ xadm_nph_cdts [NVC*8-1:0] : available VC0-VCn header non-posted credits
■ xadm_cplh_cdts [NVC*8-1:0] : available VC0-VCn header completion credits
■ xadm_pd_cdts [NVC*12-1:0] : available VC0-VCn data posted credits
■ xadm_npd_cdts [NVC*12-1:0] : available VC0-VCn data non-posted credits
■ xadm_cpld_cdts [NVC*12-1:0] : available VC0-VCn data completion credits
Information for lower order VCs is presented on the lower-order bits.
Values: 0, 1
Default Value: 0
Enabled: ((AMBA_INTERFACE==0))
Parameter Type: Feature Setting
Parameter Name: XADM_CRD_EN
Client Interface TLP pullback Enable the transmit clients to cancel a TLP that is currently submitted for transmission.
feature Values:
■ false (0)
■ true (1)
Default Value: (CC_DMA_ENABLE && (AMBA_INTERFACE!=0)) ? 1 : 0
Enabled: ((AMBA_INTERFACE==0))
Parameter Type: Feature Setting
Parameter Name: CLIENT_PULLBACK
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PCI Express SW Controller Databook Advanced Transmit Config Parameters
Label Description
Transmit Client Arbitration Selects the arbitration method for transmitted TLPs, as described in the "Transmit TLP
Scheme Arbitration" section of the Databook.
■ 0: VC Based. Provides a VC based programmable weighted round robin arbitration
(WRR) using two different arbitration methods for the two groups of VCs.
■ 1: Round Robin (RR). Provides round robin arbitration between the three transmit
clients. This is the default method.
■ 2: Strict Priority. Provides strict priority between the three transmit clients. XALI0 is
lowest, XALI1 is higher, XALI2 (if implemented) is highest.
You can only change this parameter when CX_NVC >1.
Values:
■ VC Based (0)
■ Round Robin (1)
■ Strict Priority (2)
Default Value: Round Robin
Enabled: CX_NVC > 1
Parameter Type: Feature Setting
Parameter Name: CX_XADM_ARB_MODE
Enable LPVC WRR Weights Determines whether the WRR arbitration VC weight values in VC Transmit Arbitration
Writable Register 1 and VC Transmit Arbitration Register 2 (in the register section of the
Databook) are writable through the DBI.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: CX_LPVC_WRR_WEIGHT_WRITABLE
VC ID #0 Weight WRR Weighting for VC ID #0. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0xf
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC0
Synopsys, Inc.
Label Description
VC ID #1 Weight WRR Weighting for VC ID #1. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC1
VC ID #2 Weight WRR Weighting for VC ID #2. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC2
VC ID #3 Weight WRR Weighting for VC ID #3. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC3
VC ID #4 Weight WRR Weighting for VC ID #4. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC4
VC ID #5 Weight WRR Weighting for VC ID #5. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC5
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PCI Express SW Controller Databook Advanced Transmit Config Parameters
Label Description
VC ID #6 Weight WRR Weighting for VC ID #6. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC6
VC ID #7 Weight WRR Weighting for VC ID #7. If LPVC WRR Weights Writable is true, your application
can change the value by writing to VC Transmit Arbitration Register 1 (in the register
section of the Databook) through the DBI.
Values: 0x0, ..., 0x7f
Default Value: 0x0
Enabled: VC_ENABLE==1 && CX_XADM_ARB_MODE==0
Parameter Type: Feature Setting
Parameter Name: LPVC_WRR_WEIGHT_VC7
Transmit Completion
Compare Completion Credit Enable the controller to compare the actual size of a requested Completion (as
opposed to a maximum size Completion) against available Completion credits before
transmitting the Completion. This parameter saves gates and improves timing when
set to false.
■ Typically, an EP must have enough buffer space to receive all CPL data before it
sends a MRd transaction. Therefore, an RC may assume infinite CPL credits.
■ There is no need to compare the CPL length with available CPL credits. Therefore,
setting this parameter to false can save gate count by eliminating the compare
logic.
■ If a PCIe device has specific or more strict requirement for checking a peer compo-
nents CplD buffer capability, it sets a threshold that at least 8 CplD credits are avail-
able before a PCIe device can transmit a CPLD.
Values: 0, 1
Default Value: 1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CPL_LEN_CMP_ENABLE
Transmit Posted
Compare Posted Credit Enable the controller to compare the size of a requested posted payload length against
available posted credits before transmitting the posted TLP.
Values: 0, 1
Default Value: 1
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: P_LEN_CMP_ENABLE
Synopsys, Inc.
Label Description
Populate ports to allow the Application credit control. For more details, see 'SII: Transmit Control Signals' section
application to control credit usage of the Databook. This parameter enables the application to control credits used
from internal MSG/CPL internally by the controller for internally generated MSG/CPL.
Values: 0, 1
Default Value: 0
Enabled: ((AMBA_INTERFACE==0) && (CX_CCIX_INTERFACE_ENABLE==0))
Parameter Type: Feature Setting
Parameter Name: APP_CREDIT_CTRL
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PCI Express SW Controller Databook Advanced Pipeline Config Parameters
Label Description
Pipeline Latencies
RDLH TLP Extract Input Input pipeline stage to RDLH TLP extraction module
Values:
■ 0 (0)
■ 1 (1)
Default Value: 1
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RDLH_REGIN
CRC Pipeline Depth - XTLH CRC Pipeline Latency value for xtlh. This value represents the number of pipeline
stages needed to calculate and compare ECRC. core supported latencies: 1,2
Values:
■ 1 (1)
■ 2 (2)
Default Value: 1 + ((CX_NW > 1) ? ((CX_TECHNOLOGY == 0) || ((CX_GEN4_MODE
== GEN4_DF) && CX_NW==16) || (CX_MAX_CORECLK_FREQ > 500)) : 0)
Enabled: CX_CUSTOM_PIPELINING && (CX_NW > 1)
Parameter Name: CX_CRC_LATENCY_XTLH
CRC Pipeline Depth - RTLH CRC Pipeline Latency value for rtlh. This value represents the number of pipeline
stages needed to calculate and compare ECRC. core supported latencies: 1,2
Values:
■ 1 (1)
■ 2 (2)
Default Value: 1 + ((CX_NW > 1) ? ((CX_TECHNOLOGY == 0) || ((CX_GEN4_MODE
== GEN4_DF) && CX_NW==16) || (CX_MAX_CORECLK_FREQ > 500)) : 0)
Enabled: CX_CUSTOM_PIPELINING && (CX_NW > 1)
Parameter Name: CX_CRC_LATENCY_RTLH
CRC Pipeline Depth - XDLH CRC Pipeline Latency value for xdlh. This value represents the number of pipeline
stages needed to calculate and compare LCRC. core supported latencies: 1,2
Values:
■ 1 (1)
■ 2 (2)
Default Value: 1 + ((CX_NW > 1) ? ((CX_TECHNOLOGY == 0) || ((CX_GEN4_MODE
== GEN4_DF) && CX_NW==16) || ((CX_MAX_CORECLK_FREQ >= 500) &&
CX_RASDP > 0) || (CX_MAX_CORECLK_FREQ > 500)) : 0)
Enabled: CX_CUSTOM_PIPELINING && (CX_NW > 1)
Parameter Name: CX_CRC_LATENCY_XDLH
Synopsys, Inc.
Label Description
CRC Pipeline Depth - RDLH CRC Pipeline Latency value for rdlh. This value represents the number of pipeline
stages needed to calculate and compare LCRC. core supported latencies: 1,2
Values:
■ 1 (1)
■ 2 (2)
Default Value: 1 + ((CX_NW > 1) ? ((CX_TECHNOLOGY == 0) || ((CX_GEN4_MODE
== GEN4_DF) && CX_NW==16) || (CX_MAX_CORECLK_FREQ > 500)) : 0)
Enabled: CX_CUSTOM_PIPELINING && (CX_NW > 1)
Parameter Name: CX_CRC_LATENCY_RDLH
LTSSM This parameter adds selected pipelines in the LTSSM, providing trade-off of latency
and gates for ease of timing closure. This parameter is for Conventional PCIe mode
only; M-PCIe doesn't use this parameter.
Values: 0, 1
Default Value: (CX_TECHNOLOGY == 0) && !CX_MPCIE_ENABLE
Enabled: CX_CUSTOM_PIPELINING && !CX_MPCIE_ENABLE
Parameter Type: Performance Setting
Parameter Name: CX_SMLH_PIPELINE_LTSSM
Retry Buffer Retry Buffer Pipeline Latency value. This value represents the number of pipeline
stages used in retry buffer, providing trade-off of latency and gates for ease of timing
closure.
Values: 0, 1
Default Value: (CX_TECHNOLOGY == 0) || ((CX_GEN2_MODE == 0) &&
(CX_FREQ == 1) && (ARC_WIDTH < 128))
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_XDLH_PIPELINE_RBUF
Transmit Flow Control Transmit Flow Control Calculations Pipeline Enable, providing trade-off of latency and
Calculations gates for ease of timing closure.
Values: 0, 1
Default Value: (CX_TECHNOLOGY == 0) || ((CX_GEN2_MODE == 0) &&
(CX_FREQ == 1) && (ARC_WIDTH == 32))
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_XADM_FC_PIPELINE
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Label Description
Receive Serialization Queue Inserts a pipeline at the Receive Serialization Queue RAM write interface.
Write Pipeline Values: 0, 1
Default Value: CX_TECHNOLOGY==0 || (CX_MAX_CORECLK_FREQ >= 1000) ||
(CX_RASDP_EN && ((CX_GEN2_MODE==GEN2_DF && CX_FREQ==FREQ_250)
|| (CX_GEN3_MODE==GEN3_DF && CX_FREQ==FREQ_125) ||
(CX_GEN4_MODE==GEN4_DF && CX_FREQ==FREQ_62_5)))
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RADM_FORMQ_WR_REGOUT
Receive MAC Layer (RML) Specifies insertion of register pipeline at the inputs of RMLH Packet finder, providing
Packet Finder Input trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ([<functionof> CX_NB CX_NL] >= 128) ? (CX_GEN3_MODE == 0) ? 1
: ((CX_TECHNOLOGY == 0) ? 1 : 0) : 0
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RMLH_PKT_FINDER_REGIN
Receive MAC Layer (RML) PIPE Specifies insertion of register pipeline at the outputs of RMLH PIPE, providing trade-off
Output of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: (CX_MPCIE_ENABLE) ? 1 : (CX_TECHNOLOGY == 2) ? ((((CX_NB
== 1) || (CX_GEN2_SPEED)) & (CX_NL > 1)) ? 1:0) : 1
Enabled: CX_CUSTOM_PIPELINING && !CX_MPCIE_ENABLE
Parameter Type: Performance Setting
Parameter Name: CX_RMLH_PIPE_REGOUT
Receive MAC Layer (RML) Specifies insertion of register pipeline at the Input of Deskew, providing trade-off of
Deskew Input latency and gates for ease of timing closure.
Values: 0, 1
Default Value: 0
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RMLH_DESKEW_REGIN
Receive Data Link Layer (RDL) Specifies insertion of register pipeline at the outputs of RDLH TLP Extract, providing
TLP Extract Output trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0)) ? 1 : ((((CX_NB == 1) ||
(CX_2ND_SPEED)) & (CX_NL > 4)) ? 1: 0)
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RDLH_TLP_EXTRACT_REGOUT
Synopsys, Inc.
Label Description
Receive Transaction Layer (RTL) Insert a pipeline at the output of the Receive Transaction Layer TLP extraction module.
TLP Extraction Values: 0, 1
Default Value: 1
Enabled: CX_RTLH_SIMPLE_EXTRACT && CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RTLH_TLP_EXTRACT_REGOUT
Receive Transaction Layer (RTL) Specifies insertion of a local register pipeline for Flow Control credit check calculation
TLP FC credit check in the Receive Transaction Layer TLP check module for ease of timing closure.
Values: 0, 1
Default Value: (CX_TECHNOLOGY == 0) || (CX_MAX_CORECLK_FREQ > 781)) &&
(CX_NW==16) && (CX_RASDP>2
Enabled: CX_RTLH_SIMPLE_EXTRACT && CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RTLH_FC_CHECK_REGOUT
Receive Header and Data Queue Insert a pipeline at the Receive Header and Data Queue RAM Write interfaces.
Write RAM Outputs Values: 0, 1
Default Value: CX_TECHNOLOGY==0 || (CX_MAX_CORECLK_FREQ > 500)
Enabled: CX_RADMQ_MODE==2 && CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_RADM_RAM_WR_REGOUT
Receive Input Queue Manager Specifies insertion of register pipeline at the output of the receive queue input queue
Output manager before the receive queue RAM inputs, providing trade-off of latency and
gates for ease of timing closure.
Values: 0, 1
Default Value: 1
Enabled: CX_RADMQ_MODE==2
Parameter Type: Performance Setting
Parameter Name: CX_RADM_INQ_MGR_REGOUT
Transmit Transaction Layer (XTL) Specifies insertion of register pipeline at the outputs of XTLH, providing trade-off of
Output latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ((CX_ECRC_ENABLE == 1) || ((CX_RASDP > 0) && (CX_NW <= 2)))
? 1 : ((((CX_NB == 1) || (CX_2ND_SPEED)) & (CX_NL > 1)) ? 1: 0)
Enabled: (CX_CUSTOM_PIPELINING && !CX_ECRC_ENABLE &&
!((CX_RASDP>0) && (CX_NW <= 2)))
Parameter Type: Performance Setting
Parameter Name: CX_XTLH_CTRL_REGOUT
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PCI Express SW Controller Databook Advanced Pipeline Config Parameters
Label Description
Transmit Data Link Layer (XDL) Specifies insertion of register pipeline at the outputs of XDLH, providing trade-off of
Output latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0)) ? 1 : 1
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_XDLH_TLP_REGOUT
Transmit MAC Layer (XML) PIPE Specifies insertion of register pipeline at the outputs of XMLH PIPE, providing trade-off
Output of latency and gates for ease of timing closure. For M-PCIe, applies to the Layer1 to
PIPE RMMI adapter interface.
Values: 0, 1
Default Value: (CX_MPCIE_ENABLE)? 0 : ((CX_TECHNOLOGY == 0)) ? 1 : 0
Enabled: CX_CUSTOM_PIPELINING && !CX_MPCIE_ENABLE
Parameter Type: Performance Setting
Parameter Name: CX_XMLH_PIPE_REGOUT
Transmit MAC Layer (XML) Specifies insertion of register pipeline at the outputs of XMLH Precoding, providing
Precoding Output trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0)) ? 0 : 0
Enabled: CX_CUSTOM_PIPELINING && !CX_MPCIE_ENABLE &&
CX_GEN5_SPEED
Parameter Type: Performance Setting
Parameter Name: CX_XMLH_PRECODING_REGOUT
Error Log Output Specifies insertion of register pipeline at the Outputs Error Log, providing trade-off of
latency and gates for ease of timing closure.
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0) || (CX_SRIOV_ENABLE &&
CX_NVFUNC>32)) ? 1 : 0
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_ERROR_LOG_REGOUT
Synopsys, Inc.
Label Description
Receive Filter To Receive Queue Specifies insertion of register pipeline between receive filter and receive queue input
manager, providing trade-off of latency and gates for ease of timing closure.
Values: 0, ..., 2
Default Value: (CX_INTERNAL_ATU_ENABLE &&
((CX_ATU_NUM_INBOUND_REGIONS > 32 ) || (CX_RASDP!=0 &&
CX_MAX_CORECLK_FREQ > 500))) ? 2 :
ADDR_TRANSLATION_SUPPORT_EN||SATA_CAP_ENABLE||CX_GEN3_DYNAMIC
_FREQ
Enabled: (CX_CUSTOM_PIPELINING==1 &&
(ADDR_TRANSLATION_SUPPORT_EN==0 && SATA_CAP_ENABLE==0 ||
CX_INTERNAL_ATU_ENABLE))
Parameter Type: Performance Setting
Parameter Name: CX_FLT_Q_REGOUT
Radm_bypass pipeline Specifies insertion of register pipeline in the radm_bypass interface, providing trade-off
of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: CX_RASDP > 0) || (CX_MAX_CORECLK_FREQ > 500) ||
(CX_INTERNAL_ATU_ENABLE && AMBA_INTERFACE==0
Enabled: Always
Parameter Type: Performance Setting
Parameter Name: CX_RADM_BYPASS_REGOUT
XADM Hdr/Data Align To Output Specifies insertion of register pipeline before XADM output formation providing
Formation trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: (CX_INTERNAL_ATU_ENABLE &&
CX_ATU_NUM_OUTBOUND_REGIONS > 32) || (CX_RAS_DES_EINJ_ENABLE)
Enabled: CX_CUSTOM_PIPELINING==1
Parameter Type: Performance Setting
Parameter Name: CX_XADM_FORMATION_REGIN
Pfvf_to_vfindex To RADM Filter Specifies insertion of a local register pipeline for the pfvf_to_vfindex output in the
Output RADM_FILTER providing area trade off for ease of timing closure.
Values: 0, 1
Default Value: CX_CRC_LATENCY_RTLH && CX_SRIOV_ENABLE &&
CX_NVFUNC>32
Enabled: CX_CRC_LATENCY_RTLH && CX_SRIOV_ENABLE
Parameter Type: Performance Setting
Parameter Name: VFINDEX_CALC_REGOUT
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PCI Express SW Controller Databook Advanced Pipeline Config Parameters
Label Description
Rid_to_pfvf Inputs Specifies insertion of register pipeline for the rid_to_pfvf module inputs in the
RADM_FILTER and RADM_CPL_LUT blocks, providing trade-off of latency and gates
for ease of timing closure.
Values: 0, 1
Default Value: CX_SRIOV_ENABLE && DWC_PCIE_FPGA
Enabled: CX_CUSTOM_PIPELINING==1 && CX_SRIOV_ENABLE
Parameter Type: Performance Setting
Parameter Name: CX_RID_REGIN
Rid_to_pfvf Outputs Specifies insertion of register pipeline for the rid_to_pfvf module output in the
RADM_FILTER and RADM_CPL_LUT blocks, providing trade-off of latency and gates
for ease of timing closure.
Values: 0, 1
Default Value: CX_SRIOV_ENABLE || RADM_VFINDEX_REGOUT
Enabled: CX_CUSTOM_PIPELINING==1 && CX_ARI_ENABLE &&
!RADM_VFINDEX_REGOUT
Parameter Type: Performance Setting
Parameter Name: CX_RID_REGOUT
Vendor MSI Interface Inputs Specifies insertion of an input register pipeline for the Vendor MSI interface
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0) || (CX_SRIOV_ENABLE ==1)) ? 1 : 0
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_VEN_MSI_REGIN
Application Error Return Interface Specifies insertion of an input register pipeline for the Application Error Return
Inputs interface
Values: 0, 1
Default Value: ((CX_TECHNOLOGY == 0) || (CX_SRIOV_ENABLE ==1) ||
(CX_MAX_CORECLK_FREQ > 500)) ? 1 : 0
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_APP_ERR_REGIN
Lane Flip RX Input Specifies insertion of register pipeline at the inputs of Lane Flip block signals from
PHY, providing trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: (CX_MAX_CORECLK_FREQ >= 500)
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_LANEFLIP_RX_REGIN
Synopsys, Inc.
Label Description
Lane Flip TX Output Specifies insertion of register pipeline at the outputs of Lane Flip block signals to PHY,
providing trade-off of latency and gates for ease of timing closure.
Values: 0, 1
Default Value: (CX_MAX_CORECLK_FREQ >= 500)
Enabled: CX_CUSTOM_PIPELINING
Parameter Type: Performance Setting
Parameter Name: CX_LANEFLIP_TX_REGOUT
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PCI Express SW Controller Databook Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters
6.53 Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters
Table 6-53 Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters
Label Description
General Configuration
Enable Auto Size of Retry Buffer Enable or disable automatic size calculation for the retry buffer.:
■ True: Enable Auto Size: The sizes of the retry buffer and SOT buffer are automati-
cally calculated based on the "Maximum Payload Size Supported value", the link
width, and device latencies.
■ False: Disable Auto Size: Automatic buffer sizing is disabled. The value that you
enter for Retry Buffer Depth (CX_RBUF_DEPTH) directly sets the depth of the retry
buffer.
For more details, see the "Transmit Replay" section of the "Architecture" chapter of the
Databook.
Values:
■ false (0x0)
■ true (0x1)
Default Value: true
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RBUF_AUTOSIZE
Internal Delay / Link Partner Read-only parameter that indicates the sum of the MAC/PHY delays, used for retry
Delay buffer auto-sizing, AckNak Timer adjustment and replay timer adjustment.
Values: 0, ..., 2048
Default Value: (CX_S_CPCIE_MODE) ? CX_CPCIE_INTERNAL_DELAY :
(CX_S_MPCIE_MODE) ? CM_MPCIE_INTERNAL_DELAY :
(CX_CPCIE_INTERNAL_DELAY > CM_MPCIE_INTERNAL_DELAY) ?
CX_CPCIE_INTERNAL_DELAY : CM_MPCIE_INTERNAL_DELAY
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_INTERNAL_DELAY
Total Retimer Latency (Symbol Read-only parameter that indicate total round trip Latency of Retimer calculated from
times) CX_MAX_RETIMER setting and reference Retimer latency table in PCIe Base Spec,
used for retry buffer auto-sizing.
Values: -2147483648, ..., 2147483647
Default Value: CX_RETIMER_LATENCY
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RETIMER_LATENCY2
Synopsys, Inc.
Label Description
Retry Buffer Depth The depth of the retry buffer. When retry buffer auto-sizing is enabled
(CX_RBUF_AUTOSIZE), "Retry Buffer Depth" is read-only and indicates the
automatically calculated depth of the retry buffer. When retry buffer auto-sizing is
disabled, "Retry Buffer Depth" is the user-specified depth of the retry buffer. Note that
if the autosize feature is disabled, then the minimum value specified must be large
enough to allow normal operation. The default value is the automatically calculated
value. For more details, see the 'Transmit Replay' section of the Architecture chapter of
the Databook.
Values: SNPS_RSVDPARAM_30, ..., 4294967295
Default Value: [calc_rbuf_depth CX_DL_NB CX_NL CX_MAX_MTU
CX_ECRC_ENABLE CX_TLP_PREFIX_ENABLE_VALUE CX_NPRFX
CX_INTERNAL_DELAY CX_MAX_L0S_LTIME CX_GEN5_SPEED
CX_GEN4_SPEED CX_GEN3_SPEED CX_5GTS_SPEED
CX_RETIMER_LATENCY]
Enabled: ((!CX_RBUF_AUTOSIZE))
Parameter Type: Feature Setting
Parameter Name: CX_RBUF_DEPTH
Retry Buffer Width Read-only parameter that indicates the width of the retry buffer.
Values: 34, ..., 686
Default Value: RBUF_PROT_WD + [calc_rbuf_width CX_DL_NB CX_NL
CX_TLP_PREFIX_ENABLE CX_GEN3_SPEED]
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RBUF_WIDTH
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PCI Express SW Controller Databook Advanced Buffer Config / Retry and SOT Buffer Worksheet Parameters
Label Description
Minimum SOT Depth When retry buffer auto-sizing is enabled, the value displayed here corresponds to the
number of minimum-sized TLPs (3 DWORDs) that can reside in the retry buffer.
■ The 'Start Of TLP (SOT)' buffer stores the starting address of each unacknowl-
edged TLP stored in the retry buffer.
■ The SOT buffer requires one entry for each TLP that can be stored in the retry
buffer.
■ The selected retry buffer size determines the size of the SOT buffer.
■ The actual SOT buffer depth is a combination of the value displayed here and the
additional requirements that the actual SOT buffer depth must be at least 32 and
must be a power of 2.
When retry buffer auto-sizing is disabled, 'Minimum SOT Depth' is the user-specified
depth of the SOT buffer.
■ The selected size must allow the retry buffer to store the maximum number of
shortest TLPs (3 DWORDs).
■ The actual SOT buffer depth (SOTBUF_DEPTH) is calculated by adjusting
CX_SOTBUF_DEPTH to be at least 32, and rounding up to the next power-of-2.
For more details, see the 'Transmit Replay' section of the 'Architecture' chapter of the
Databook.
Values: -2147483648, ..., 2147483647
Default Value: [calc_sot_depth CX_DL_NB CX_NL CX_MAX_MTU
CX_ECRC_ENABLE CX_TLP_PREFIX_ENABLE_VALUE CX_NPRFX
CX_INTERNAL_DELAY CX_MAX_L0S_LTIME CX_GEN5_SPEED
CX_GEN4_SPEED CX_GEN3_SPEED CX_5GTS_SPEED
CX_RETIMER_LATENCY]
Enabled: ((CX_RBUF_AUTOSIZE==0))
Parameter Type: Feature Setting
Parameter Name: CX_SOTBUF_DEPTH
SOT Buffer Depth Read-only parameter that indicates the depth of the SOT buffer.
Values: 32, ..., 4294967295
Default Value: [calc_sotbuf_depth CX_DL_NB CX_NL CX_MAX_MTU
CX_ECRC_ENABLE CX_TLP_PREFIX_ENABLE_VALUE CX_NPRFX
CX_INTERNAL_DELAY CX_MAX_L0S_LTIME CX_RBUF_AUTOSIZE
CX_SOTBUF_DEPTH CX_GEN5_SPEED CX_GEN4_SPEED CX_GEN3_SPEED
CX_5GTS_SPEED CX_RETIMER_LATENCY]
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: SOTBUF_DEPTH
SOT Buffer Width Read-only parameter that indicates the width of the SOT buffer.
Values: 0, ..., 4294967295
Default Value: CX_RAS_EN ? ( CX_RAS_SOTBUF_PROT_WD +[calc_log2
CX_RBUF_DEPTH] ) : [calc_log2 CX_RBUF_DEPTH]
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: SOTBUF_WIDTH
Synopsys, Inc.
Label Description
Segmented-Buffer Options
Receive VC Arbitration The VC arbitration scheme for sending received TLPs to your application.
■ Strict Priority: Higher number VC IDs have higher priority
■ Round Robin: Round robin arbitration between VCs
Notes:
■ This parameter is only applicable when CX_NVC > 1.
■ It is possible to change the VC Arbitration Scheme (during device setup by soft-
ware) by writing to the VC_ORDERING_RX_Q field in the VC0_P_RX_Q_C-
TRL_OFF register.
Values:
■ Round Robin (0x0)
■ Strict Priority (0x1)
Default Value: Round Robin
Enabled: CX_RADMQ_MODE==2
Parameter Type: Register Default Setting
Parameter Name: CX_RADM_STRICT_VC_PRIORITY
Enable Dynamic FC Credit Enable your application to update the advertised FC credit values by writing to the VC0
Adjustment Posted Receive Queue Control port logic register.
Values:
■ false (0)
■ true (1)
Default Value: FC_SCALE_EN
Enabled: CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: CX_DYNAMIC_FC_CREDIT
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PCI Express SW Controller Databook Advanced Buffer Config / Ordering Rules Configuration (Segmented-Buffer)
Label Description
Support Relaxed Ordering Allows completions to be sent to your application out of order. For more details, see
Receive Queues in the Architecture chapter of the Databook.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RELAXED_ORDER_SUPPORT
Ordering Rules Specifies the ordering scheme for sending received TLPs to the application:
■ 0: Strict Priority: The priority order is Posted, then Completion, then Non-Posted
■ 1: PCI Ordering Rules: The arbitration is according to the ordering rules in the PCI
Express 3.1 Specification.
For more details, see the "Native Core Receive Ordering Schemes" section in the
"Advanced Ordering Information" appendix of the Databook. It is possible to change
the ordering rules used (by software) by writing to the appropriate queue control
register 'TLP Type Ordering'.
Values:
■ Strict Priority (0x0)
■ PCIe Ordering Rules (0x1)
Default Value: PCIe Ordering Rules
Enabled: CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: CX_RADM_ORDERING_RULES
Synopsys, Inc.
Label Description
Enable Receive Serialization The Receive Serialization Queue Size Configuration feature applies to 512-bit data
Queue Size Configuration width configurations and allows the size of the serialization queue to be adjusted while
maintaining throughput at the application interface.
Values: 0, 1
Default Value: 0
Enabled: CX_NW==16
Parameter Type: Feature Setting
Parameter Name: RX_SERIALIZATION_Q_CTRL
Queue Size (% of the available This is the size of the serialization queue relative to the storage capacity of the credit
TLP buffer space ) queues expressed as a percentage of credit queue size. The serialisation queue
margin is excluded.
Values: 0, ..., 100
Default Value: CX_NW==16 ? [<functionof> CX_RADM_RXQ_NUM_QDWS >
CX_RADM_SERQ_OPT_AF_NUM_QDWS] ? [<functionof> [<functionof>
CX_RADM_SERQ_OPT_AF_NUM_QDWS_PER_RAM*100]
CX_RADM_RXQ_NUM_QDWS_PER_SERQ_RAM] : 100 : 1
Enabled: RX_SERIALIZATION_Q_CTRL
Parameter Type: Feature Setting
Parameter Name: CX_RADM_SERQ_TO_RXQ_SIZE_RATIO
Queue Size (Bytes) Receive Serialization Queue size expressed in Bytes (additional control bits, parity
bits, etc. are not considered)
Values: -2147483648, ..., 2147483647
Default Value:
(CX_RADM_SERQ_AF_NUM_QDWS_PER_RAM*CX_RADM_SERQ_NUM_RAMS)*
16
Enabled: Always
Parameter Name: CX_RADM_SERQ_AF_NUM_BYTES
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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / Cplq_Mng Calculator Parameters
6.57 Advanced RX Queue Credit and Size Config / Cplq_Mng Calculator Param-
eters
Table 6-57 Advanced RX Queue Credit and Size Config / Cplq_Mng Calculator Parameters
Label Description
Round Trip Latency[ns] Specifies your expected Round Trip Latency in ns. Includes:
■ Local Controller and PHY latencies
■ Remote Controller and PHY latencies
■ Retimers
■ Response time of the remote side
Values: 0, ..., 65535
Default Value: 500
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: ROUND_TRIP_LATENCY
TLP Efficiency[%] Specifies the TLP Efficiency in %. Smaller payload has less data efficiency
(Data/(Hdr+Data)) and therefore requires less data buffer.
Values: 0, ..., 65535
Default Value: 100*CX_MAX_MTU/(CX_MAX_MTU+20)
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: TLP_EFFICIENCY
Critical Request size[bytes] Specifies the smallest request size for which you want to maintain throughput. Used to
calculate the recommended number of TAGs
(CPLQ_MNG_DDP/MIN_RD_REQ_SIZE). Recommended size equal to or greater
than 64 bytes.
Values: 32, 64, 128, 256, 512, 1024, 2048, 4096
Default Value: 64
Enabled: Always
Parameter Name: MIN_RD_REQ_SIZE
Recommended number of TAGs Recommended number of TAGs based on Latency and Critical Request Size
specified.
Values: 0, ..., 65535
Default Value: [<functionof> CPLQ_MNG_DDP MIN_RD_REQ_SIZE]
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: RECOMMENDED_TAGS
Synopsys, Inc.
Label Description
Header Completion Queue Specifies the size of the Completion Data Queue/RAM in hdr units without the
size[Hdr] overhead needed by the Queue logic. Derived from the number of TAGs. Does not
account for all possible split completions scenarios.
Values: 0, ..., 65535
Default Value: 2*(CX_MAX_TAG+1)
Enabled: CX_CPLQ_MANAGEMENT_ENABLE
Parameter Type: Feature Setting
Parameter Name: CPLQ_MNG_HDP
Data Completion Queue Specifies the size of the Completion Data Queue/RAM in bytes without the overhead
size[bytes] needed by the Queue logic. This is a recommendation based on your bandwidth, max
TLP size and expected latency. The Completion Queue Management feature can
result in throttling of outbound read request. It is your responsibility to guarantee
sufficient completion queue buffer to meet your performance requirements.
Values: 0, ..., 65535
Default Value: [<functionof> CX_MAX_PCIE_SPEED CX_NL
ROUND_TRIP_LATENCY TLP_EFFICIENCY CX_APP_RD_REQ_SIZE CX_NW
RADM_CPL_QMODE_VC0]
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CPLQ_MNG_DDP
Header Completion Queue Specifies the depth of the completion header queue including overhead for queue
Depth[Hdr/CX_NHQ] logic.
Values: 0, ..., 65535
Default Value: RADM_CPLQ_HDP_VC0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CPLQ_MNG_TOTAL_HDP
Data Completion Queue Specifies the depth of the completion data queue including overhead for queue logic.
Depth[NW] Values: 0, ..., 65535
Default Value: RADM_CPLQ_DDP_VC0
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CPLQ_MNG_TOTAL_DDP
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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / VC 0 Parameters
Label Description
Hdr Scale Factor Initial VC0 Posted header scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HSCALE_VC0
Hdr Credits The number of posted TLP header credits to advertise for VC0.
Values: 0, ..., 127
Default Value: RADM_P_QMODE_VC0==4 ? 0 : CX_CALC_HDEPTH / CX_HSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HCRD_VC0
Data Scale Factor Initial VC0 Posted data scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_DSCALE == 16) ? 3 : (CX_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DSCALE_VC0
Data Credits The number posted TLP data credits to advertise for VC0.
Values: 0, ..., 2047
Default Value: RADM_P_QMODE_VC0 ==4 ? 0 : CX_CALC_DDEPTH /
CX_DSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DCRD_VC0
Synopsys, Inc.
Label Description
Hdr Scale Factor Initial VC0 Non-Posted header scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HSCALE_VC0
Hdr Credits The number non-posted TLP header credits to advertise for VC0.
Values: 1, ..., 127
Default Value: (CX_CALC_HDEPTH==0) ? 1 : CX_CALC_HDEPTH / CX_HSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HCRD_VC0
Data Scale Factor Initial VC0 Non-Posted data scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_NP_DSCALE == 16) ? 3 : (CX_NP_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DSCALE_VC0
Data Credits The number non-posted TLP data credits to advertise for VC0.
Values: 1, ..., 2047
Default Value: (CX_NP_CALC_DDEPTH==0) ? 1 : CX_NP_CALC_DDEPTH /
CX_NP_DSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DCRD_VC0
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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / VC 0 Parameters
Label Description
Hdr Scale Factor Initial VC0 Completion header scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HSCALE_VC0
Hdr Credits The number completion TLP header credits to advertise for VC0.
Values: 0, ..., 127
Default Value: (RADM_CPL_QMODE_VC0==4 || CC_DEVICE_TYPE!=CC_SW) ? 0
: CX_CALC_HDEPTH / CX_HSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HCRD_VC0
Data Scale Factor Initial VC0 Completion data scaling factor to advertise Flow Control credit width.
Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_DSCALE == 16) ? 3 : (CX_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DSCALE_VC0
Data Credits The number of completion TLP data credits to advertise for VC0.
Values: 0, ..., 2047
Default Value: (RADM_CPL_QMODE_VC0==4 || CC_DEVICE_TYPE!=CC_SW) ? 0
: CX_CALC_DDEPTH / CX_DSCALE
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DCRD_VC0
Synopsys, Inc.
Label Description
Additional VC 0 Options
Max Outbound Read Request This parameter is used to set the depth of the receive completion data queue
For Buffered CPLs (CX_CPLQ_DDP_VC*) when completions are in store-and-forward or cut-through
modes, and completion credits are infinite.
■ It is the maximum individualMRd size that your application makes.
■ For more details, see the Receive Queues section in the Architecture chapter of the
Databook.
Values: 32, 64, 128, 256, 512, 1024, 2048, 4096
Default Value: !AMBA_POPULATED ? CX_MAX_MTU : (CC_DMA_ENABLE ?
CX_MAX_APP_RD_REQ_SIZE_AMBA_DMA : CC_SLV_MTU)
Enabled: !AMBA_POPULATED && (RADM_CPL_QMODE_VC0!=4)
Parameter Name: CX_APP_RD_REQ_SIZE
Hdr Specifies the depth of the Posted Header Queue/RAM. The number of entries in the
Posted Header buffer for VC0. This option is read-only if the queue is bypassed. Note:
for 256-bit configurations this depth corresponds to one half of the total header storage
capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: (RADM_P_QMODE_VC0==4) ? (CX_RADMQ_MODE==2) ?
RADM_SEG_BUF_MIN_DPT : 0 : [<functionof> CX_RADMQ_MODE
RADM_PQ_HCRD_VC0 RADM_NPQ_HCRD_VC0 RADM_CPLQ_HCRD_VC0
RADM_CPL_QMODE_VC0 CX_NHQ CUT_THROUGH_INVOLVED CX_MAX_TAG
CX_APP_RD_REQ_SIZE CX_RCB RADM_PQ_HSCALE_VC0]
Enabled: RADM_P_QMODE_VC0!=4 && RADM_DEPTH_DECOUPLE_VC0==1
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HDP_VC0
Data Specifies the depth of the Posted Data Queue/RAM. The number of entries in the
Posted Data buffer for VC0. This option is read-only if the queue is bypassed. Note: for
256-bit configurations this depth corresponds to one half of the total data storage
capacity for this particular queue type; for 512-bit configurations this depth
corresponds to one quarter of the total data storage capacity for this particular queue
type.
Values: 0, ..., 65535
Default Value: RADM_P_QMODE_VC0==4 ? (CX_RADMQ_MODE==2) ?
RADM_SEG_BUF_MIN_DPT : 0 : [<functionof> CX_RADMQ_MODE
RADM_PQ_HCRD_VC0 RADM_PQ_DCRD_VC0 RADM_NPQ_HCRD_VC0
RADM_NPQ_DCRD_VC0 RADM_CPLQ_HDP_VC0 RADM_CPLQ_DCRD_VC0
RADM_CPL_QMODE_VC0 CX_NW CX_NHQ CC_DEVICE_TYPE CC_SW
CX_ECRC_STRIP_ENABLE RADM_SEG_BUF_CT_DPT_ADJ CX_MAX_TAG
CX_APP_RD_REQ_SIZE RADM_PQ_DSCALE_VC0 RADM_PQ_HSCALE_VC0]
Enabled: RADM_P_QMODE_VC0!=4 && RADM_DEPTH_DECOUPLE_VC0==1
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DDP_VC0
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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / VC 0 Parameters
Label Description
Hdr Specifies the depth of the Non-Posted Header Queue/RAM. The number of entries in
the Non-Posted Header buffer for VC0. Note: for 256-bit configurations this depth
corresponds to one half of the total header storage capacity for this particular queue
type.
Values: 0, ..., 65535
Default Value: (CX_RADMQ_MODE==0 || RADM_NP_QMODE_VC0==4) ?
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 : [<functionof>
CX_RADMQ_MODE RADM_NPQ_HCRD_VC0 CUT_THROUGH_INVOLVED
CX_NHQ RADM_NPQ_HSCALE_VC0]
Enabled: CX_RADMQ_MODE!=0 && RADM_NP_QMODE_VC0!=4 &&
RADM_DEPTH_DECOUPLE_VC0==1
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HDP_VC0
Data Specifies the depth of the Non-Posted Data Queue/RAM. The number of entries in the
Non-Posted Data buffer for VC0. Note: for 256-bit configurations this depth
corresponds to one half of the total data storage capacity for this particular queue type;
for 512-bit configurations this depth corresponds to one quarter of the total data
storage capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: (CX_RADMQ_MODE==0 || RADM_NP_QMODE_VC0==4) ?
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 : [<functionof> 0
CX_RADMQ_MODE RADM_NPQ_HCRD_VC0 RADM_NPQ_DCRD_VC0
CUT_THROUGH_INVOLVED CX_NW CX_NHQ CC_DEVICE_TYPE CC_SW
CX_ECRC_STRIP_ENABLE RADM_NPQ_DSCALE_VC0
RADM_NPQ_HSCALE_VC0]
Enabled: CX_RADMQ_MODE!=0 && RADM_NP_QMODE_VC0!=4 &&
RADM_DEPTH_DECOUPLE_VC0==1
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DDP_VC0
Synopsys, Inc.
Label Description
Hdr Specifies the depth of the Completion Header Queue/RAM. The number of entries in
the Completion Header buffer for VC0. This option is read-only for all DMA and/or
AMBA configs and also if the queue is bypassed. Note: for 256-bit configurations this
depth corresponds to one half of the total header storage capacity for this particular
queue type.
Values: 0, ..., 65535
Default Value: (CX_RADMQ_MODE==0 || RADM_CPL_QMODE_VC0==4) ?
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 : [<functionof>
CX_CPLQ_MANAGEMENT_ENABLE CPLQ_MNG_HDP CX_RADMQ_MODE
RADM_CPLQ_HCRD_VC0 CUT_THROUGH_INVOLVED CX_NHQ CX_MAX_TAG
CX_APP_RD_REQ_SIZE CX_RCB RADM_CPLQ_HSCALE_VC0]
Enabled: (AMBA_INTERFACE == 0 && CC_DMA_ENABLE == 0) &&
CX_RADMQ_MODE!=0 && RADM_CPL_QMODE_VC0!=4 &&
(RADM_DEPTH_DECOUPLE_VC0==1 || RADM_CPLQ_HCRD_VC0 == 0)
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HDP_VC0
Data Specifies the depth of the Completion Data Queue/RAM. The number of entries in the
Completion Data buffer for VC0. This option is read-only for all DMA and/or AMBA
configs and also if the queue is bypassed. Note: for 256-bit configurations this depth
corresponds to one half of the total data storage capacity for this particular queue type;
for 512-bit configurations this depth corresponds to one quarter of the total data
storage capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: (CX_RADMQ_MODE==0 || RADM_CPL_QMODE_VC0==4) ?
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 : [<functionof>
CX_CPLQ_MANAGEMENT_ENABLE CPLQ_MNG_DDP CX_RADMQ_MODE
RADM_CPLQ_HDP_VC0 RADM_CPLQ_DCRD_VC0 CUT_THROUGH_INVOLVED
CX_NHQ CX_NW CX_MAX_TAG CX_APP_RD_REQ_SIZE CC_DEVICE_TYPE
CC_SW CX_ECRC_STRIP_ENABLE RADM_SEG_BUF_CT_DPT_ADJ
RADM_CPLQ_DSCALE_VC0 RADM_CPLQ_HSCALE_VC0]
Enabled: (AMBA_INTERFACE == 0 && CC_DMA_ENABLE == 0) &&
CX_RADMQ_MODE!=0 && RADM_CPL_QMODE_VC0!=4 &&
(RADM_DEPTH_DECOUPLE_VC0==1 || RADM_CPLQ_DCRD_VC0 == 0)
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DDP_VC0
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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / VC 1 Parameters
Label Description
P Q Mode (VC#i) The queue mode for the posted tlp receive queue for VC1.
(for n = 1; n <= CX_NVC) ■ Bypass: There is no receive queue in this mode, your application must be able to
accept all traffic as back-pressure is disabled in the mode.
■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
■ Cut-through: TLPs are stored into queue and presented to your application at the
same time it is being stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
■ Cut Thru (0x2)
■ Bypass (0x4)
Default Value: RADM_P_QMODE_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_P_QMODE_VCn
P Header Scaling Factor (VC#i) Initial VC1 Posted header scaling factor to advertise Flow Control credit width.
(for n = 1; n <= CX_NVC) Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HSCALE_VCn
P Data Scaling Factor (VC#i) Initial VC1 Posted data scaling factor to advertise Flow Control credit width.
(for n = 1; n <= CX_NVC) Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_DSCALE == 16) ? 3 : (CX_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DSCALE_VCn
Synopsys, Inc.
Label Description
P Data Credits (VC#i) Specifies the # of Posted Data Credits to Advertise. One data credit = 128 bits of data
(for n = 1; n <= CX_NVC) Values: 0, ..., 2047
Default Value: CX_NVC<=1 || RADM_P_QMODE_VC1==4 ? 0 :
RADM_PQ_DCRD_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DCRD_VCn
NP Q Mode (VC#i) The queue mode for the non-posted TLP receive queue for VC1.
(for n = 1; n <= CX_NVC) ■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
Default Value: RADM_NP_QMODE_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_NP_QMODE_VCn
NP Header Scaling Factor (VC#i) Initial VC1 Non-Posted header scaling factor to advertise Flow Control credit width.
(for n = 1; n <= CX_NVC) Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HSCALE_VCn
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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / VC 1 Parameters
Label Description
NP Data Scaling Factor (VC#i) Initial VC1 Non-Posted data scaling factor to advertise Flow Control credit width.
(for n = 1; n <= CX_NVC) Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_NP_DSCALE == 16) ? 3 : (CX_NP_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DSCALE_VCn
NP Data Credits (VC#i) Specifies the # of Non-Posted Data Credits to Advertise. One data credit = 128 bits of
(for n = 1; n <= CX_NVC) data
Values: 1, ..., 2047
Default Value: CX_ATOMIC_ENABLE ? (CX_NVC<=1) ? 1 :
RADM_NPQ_DCRD_VC0 : (RADM_NPQ_DSCALE_VC0 > 1) ? 512 : 1
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DCRD_VCn
CPL Q Mode (VC#i) The queue mode for the completion tlp receive queue for VC1.
(for n = 1; n <= CX_NVC) ■ Bypass: There is no receive queue in this mode, your application must be able to
accept all traffic as back-pressure is disabled in the mode.
■ Store-and-forward: TLPs are stored into queue; TLP is advertised only after the full
TLP is stored into the queue.
■ Cut-through: TLPs are stored into queue and presented to your application at the
same time it is being stored into the queue.
For more details, see "Receive Queue Buffers" in the Architecture chapter of the
Databook.
Values:
■ Store/Fwd (0x1)
■ Cut Thru (0x2)
■ Bypass (0x4)
Default Value: RADM_CPL_QMODE_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_CPL_QMODE_VCn
Synopsys, Inc.
Label Description
CPL Header Scaling Factor Initial VC1 Completion header scaling factor to advertise Flow Control credit width.
(VC#i) Values:
(for n = 1; n <= CX_NVC)
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_HSCALE == 16) ? 3 : (CX_HSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HSCALE_VCn
CPL Data Scaling Factor (VC#i) Initial VC1 Completion data scaling factor to advertise Flow Control credit width.
(for n = 1; n <= CX_NVC) Values:
■ 1 (0x1)
■ 4 (0x2)
■ 16 (0x3)
Default Value: (CX_DSCALE == 16) ? 3 : (CX_DSCALE == 4) ? 2 : 1
Enabled: FC_SCALE_EN
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DSCALE_VCn
CPL Header Credits (VC#i) Specifies the # of Completion Hdr Credits to Advertise.
(for n = 1; n <= CX_NVC) Values: 0, ..., 127
Default Value: (CX_NVC<=1 || RADM_CPL_QMODE_VC1==4) ? 0 :
RADM_CPLQ_HCRD_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HCRD_VCn
CPL Data Credits (VC#i) Specifies the # of Completion Data Credits to Advertise. One data credit = 128 bits of
(for n = 1; n <= CX_NVC) data
Values: 0, ..., 2047
Default Value: (CX_NVC<=1 || RADM_CPL_QMODE_VC1==4) ? 0 :
RADM_CPLQ_DCRD_VC0
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DCRD_VCn
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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / VC 1 Parameters
Label Description
P Header Queue Depth (VC#i) Specifies the depth of the Posted Header Queue/RAM. The number of entries in the
(for n = 1; n <= CX_NVC) Posted Header buffer for VC1. This option is read-only if the queue is bypassed. Note:
for 256-bit configurations this depth corresponds to one half of the total header storage
capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_P_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof>
CX_RADMQ_MODE RADM_PQ_HCRD_VC1 CX_NHQ
CUT_THROUGH_INVOLVED RADM_PQ_HSCALE_VC1]
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2 && RADM_P_QMODE_VC1!=4
&& RADM_DEPTH_DECOUPLE_VC1==1
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_HDP_VCn
P Data Queue Depth (VC#i) Specifies the depth of the Posted Data Queue/RAM. The number of entries in the
(for n = 1; n <= CX_NVC) Posted Data buffer for VC1. This option is read-only if the queue is bypassed. Note: for
256-bit configurations this depth corresponds to one half of the total data storage
capacity for this particular queue type; for 512-bit configurations this depth
corresponds to one quarter of the total data storage capacity for this particular queue
type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_P_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof>
RADM_PQ_HCRD_VC1 RADM_PQ_DCRD_VC1 CX_NW CX_NHQ
CC_DEVICE_TYPE CC_SW CX_ECRC_STRIP_ENABLE
RADM_SEG_BUF_CT_DPT_ADJ RADM_PQ_DSCALE_VC1
RADM_PQ_HSCALE_VC1]
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2 && RADM_P_QMODE_VC1!=4
&& RADM_DEPTH_DECOUPLE_VC1==1
Parameter Type: Feature Setting
Parameter Name: RADM_PQ_DDP_VCn
NP Header Queue Depth (VC#i) Specifies the depth of the Non-Posted Header Queue/RAM. The number of entries in
(for n = 1; n <= CX_NVC) the Non-Posted Header buffer for VC1. Note: for 256-bit configurations this depth
corresponds to one half of the total header storage capacity for this particular queue
type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_NP_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof>
CX_RADMQ_MODE RADM_NPQ_HCRD_VC1 CUT_THROUGH_INVOLVED
CX_NHQ RADM_NPQ_HSCALE_VC1]
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2 && RADM_NP_QMODE_VC1!=4
&& RADM_DEPTH_DECOUPLE_VC1==1
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_HDP_VCn
Synopsys, Inc.
Label Description
NP Data Queue Depth (VC#i) Specifies the depth of the Non-Posted Data Queue/RAM. The number of entries in the
(for n = 1; n <= CX_NVC) Non-Posted Data buffer for VC1. Note: for 256-bit configurations this depth
corresponds to one half of the total data storage capacity for this particular queue type;
for 512-bit configurations this depth corresponds to one quarter of the total data
storage capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_NP_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof> 1
CX_RADMQ_MODE RADM_NPQ_HCRD_VC1 RADM_NPQ_DCRD_VC1
CUT_THROUGH_INVOLVED CX_NW CX_NHQ CC_DEVICE_TYPE CC_SW
CX_ECRC_STRIP_ENABLE RADM_NPQ_DSCALE_VC1
RADM_NPQ_HSCALE_VC1]
Enabled: CX_NVC>1 && CX_RADMQ_MODE==2 && RADM_NP_QMODE_VC1!=4
&& RADM_DEPTH_DECOUPLE_VC1==1
Parameter Type: Feature Setting
Parameter Name: RADM_NPQ_DDP_VCn
CPL Header Queue Depth (VC#i) Specifies the depth of the Completion Header Queue/RAM. The number of entries in
(for n = 1; n <= CX_NVC) the Completion Header buffer for VC1. This option is read-only for all DMA and/or
AMBA configs and also if the queue is bypassed. Note: for 256-bit configurations this
depth corresponds to one half of the total header storage capacity for this particular
queue type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_CPL_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof>
CX_CPLQ_MANAGEMENT_ENABLE CPLQ_MNG_HDP CX_RADMQ_MODE
RADM_CPLQ_HCRD_VC1 CUT_THROUGH_INVOLVED CX_NHQ CX_MAX_TAG
CX_APP_RD_REQ_SIZE CX_RCB RADM_CPLQ_HSCALE_VC1]
Enabled: (AMBA_INTERFACE == 0 && CC_DMA_ENABLE == 0) && CX_NVC>1 &&
CX_RADMQ_MODE==2 && RADM_CPL_QMODE_VC1!=4 &&
(RADM_DEPTH_DECOUPLE_VC1==1 || RADM_CPLQ_HCRD_VC1 == 0)
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_HDP_VCn
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PCI Express SW Controller Databook Advanced RX Queue Credit and Size Config / VC 1 Parameters
Label Description
CPL Data Queue Depth (VC#i) Specifies the depth of the Completion Data Queue/RAM. The number of entries in the
(for n = 1; n <= CX_NVC) Completion Data buffer for VC1. This option is read-only for all DMA and/or AMBA
configs and also if the queue is bypassed. Note: for 256-bit configurations this depth
corresponds to one half of the total data storage capacity for this particular queue type;
for 512-bit configurations this depth corresponds to one quarter of the total data
storage capacity for this particular queue type.
Values: 0, ..., 65535
Default Value: CX_NVC<=1 ? 0 : RADM_CPL_QMODE_VC1==4 ? (
(CX_RADMQ_MODE==2) ? RADM_SEG_BUF_MIN_DPT : 0 ) : [<functionof>
CX_CPLQ_MANAGEMENT_ENABLE CPLQ_MNG_DDP CX_RADMQ_MODE
RADM_CPLQ_HDP_VC1 RADM_CPLQ_DCRD_VC1 CUT_THROUGH_INVOLVED
CX_NHQ CX_NW CX_MAX_TAG CX_APP_RD_REQ_SIZE CC_DEVICE_TYPE
CC_SW CX_ECRC_STRIP_ENABLE RADM_SEG_BUF_CT_DPT_ADJ
RADM_CPLQ_DSCALE_VC1 RADM_CPLQ_HSCALE_VC1]
Enabled: (AMBA_INTERFACE == 0 && CC_DMA_ENABLE == 0) && CX_NVC>1 &&
CX_RADMQ_MODE==2 && RADM_CPL_QMODE_VC1!=4 &&
(RADM_DEPTH_DECOUPLE_VC1==1 || RADM_CPLQ_DCRD_VC1 == 0)
Parameter Type: Feature Setting
Parameter Name: RADM_CPLQ_DDP_VCn
Synopsys, Inc.
Label Description
RAS D.E.S feature enable Enables RAS D.E.S functions (debug functions, error injection and statistical analysis).
Values:
■ false (0)
■ true (1)
Default Value: (CX_AUTOMOTIVE_ENABLE==1)? 1: 0
Enabled: Always
Parameter Type: Feature Setting
Parameter Name: CX_RAS_DES_ENABLE
- Time Based Analysis Enables RAS D.E.S time based analysis function.
Values:
■ false (0)
■ true (1)
Default Value: CX_RAS_DES_ENABLE
Enabled: CX_RAS_DES_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_RAS_DES_TBA_ENABLE
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PCI Express SW Controller Databook Advanced RAS Config Parameters
Label Description
- Debug Signals Enable Determines whether to include the debug signals that provide RAS D.E.S. feature
information in top-level ports.
Values:
■ false (0)
■ true (1)
Default Value: CX_RAS_DES_ENABLE
Enabled: CX_RAS_DES_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_RAS_DES_DBGIO_ENABLE
Synopsys, Inc.
Label Description
Memory Map
Memory Map Position The register map of an upstream port (as determined by device_type[3:0]) is different
to that of a downstream port. When generating DocBook XML or HTML register
reports, coreConsultant uses this parameter to determine which memory map to
generate. This parameter has no effect on the RTL implementation.
■ 0: Upstream Port
■ 1: Downstream Port
Values:
■ Upstream Port (0)
■ Downstream Port (1)
Default Value: (CC_DEVICE_TYPE==CC_RC) || (CC_DEVICE_TYPE==CC_DM) ||
(CC_DEVICE_TYPE==CC_SW)
Enabled: ((CC_DEVICE_TYPE==CC_SW || CC_DEVICE_TYPE==CC_DM))
Parameter Name: CX_MEMORY_MAP_POSITION
Memory Map View Specifies the current memory map view. There are two buses that can access the
controller's register space: DBI and WIRE (over PCIe protocol). The register map as
perceived from the remote link partner (wire view) is different to that of the local
application (DBI view). For example, many registers that are RO over the wire are also
RW over the DBI. When generating DocBook XML or HTML register reports,
coreConsultant uses this parameter to determine which memory map view to
generate. This parameter has no effect on the RTL implementation.
■ 0: DBI
■ 1: WIRE
■ 2: DBI2
Values:
■ DBI (0)
■ WIRE (1)
■ DBI2 (2)
Default Value: DBI
Enabled: Always
Parameter Name: CX_MEMORY_MAP_VIEW
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PCI Express SW Controller Databook Memory Map Parameters
Label Description
Memory Map Unroll View Specifies whether to generate unroll (that is, iATU and DMA registers only) DocBook
XML or HTML register reports or not. coreConsultant uses this parameter to determine
whether to generate the unroll (that is, iATU and DMA registers only) register report or
not. This parameter has no effect on the RTL implementation.
■ 0: NO_UNROLL
■ 1: UNROLL
Values:
■ NO_UNROLL (0)
■ UNROLL (1)
Default Value: NO_UNROLL
Enabled: (CC_UNROLL_ENABLE && (CX_MEMORY_MAP_VIEW <2))
Parameter Name: CX_UNROLL_VIEW
Synopsys, Inc.
Label Description
CDM Register Checking Enable When enabled, the core contains CDM Register Checking feature.
Values:
■ false (0)
■ true (1)
Default Value: (CX_AUTOMOTIVE_ENABLE==1)? 1: 0
Enabled: ((CX_PCIE_MODE == SINGLE_CPCIE))
Parameter Type: Feature Setting
Parameter Name: CX_CDM_REG_CHK_EN
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PCI Express SW Controller Databook CXS Configuration Parameters
Label Description
CXS Synchronous Design If set to True, this parameter results in a CXS implementation using a single clock
domain. The PCIe IP clock (core_clk) is used to drive CXS interface.
Values:
■ false (0)
■ true (1)
Default Value: CX_CXS_DATAFLITWIDTH==CX_CXS_CCIXDATAWIDTH
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_SYNCHRONOUS
CXS Synchronous Design Specifies the maximum operating frequency of CXS Controller (MHz). The default
value is the Core and CXS Data Flit width ratio of the Core clock frequency.
Values: -2147483648, ..., 2147483647
Default Value:
int((CX_CXS_CCIXDATAWIDTH*1.0/CX_CXS_DATAFLITWIDTH)*CX_MAX_COREC
LK_FREQ)
Enabled: CX_CXS_ENABLE && !CX_CXS_SYNCHRONOUS
Parameter Type: Feature Setting
Parameter Name: CX_CXS_FREQUENCY
CXS Data Flit Width Configures CXS Data Flit Width (maps to CXSDATAFLITWIDTH in CXS specification).
Values: 256, 512, 1024
Default Value: (((CX_NW == 16) ? 512 : (CX_NW == 8) ? 256 : 128)==512) ? 512 :
256
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_DATAFLITWIDTH
CXS Maximum Packets per Flit Maximum number of packets that can be present in a single flit of data (maps to
CXSMAXPKTPERFLIT in CXS specification).
Values: 2, 3, 4
Default Value: (CX_CXS_DATAFLITWIDTH==256) ? 2 : 4
Enabled: (CX_CXS_ENABLE && (CX_CXS_DATAFLITWIDTH>256))
Parameter Type: Feature Setting
Parameter Name: CX_CXS_MAXPKTPERFLIT
Synopsys, Inc.
Label Description
CXS Receiver Continuous Data If set to True, this receiver requires that after a packet is started it is completed in
consecutive cycles if enough credits are available (maps to CXSCONTINUOUSDATA
in CXS specification).
Note:Once this parameter is set to True, this attribute may not be overwritten through
CXS Receiver configuration register.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RX_CONTINUOUSDATA
CXS Transmitter Continuous If set to True, this transmitter will not begin a packet until it can deliver the complete
Data packet in consecutive cycles as long as credits are available (maps to
CXSCONTINUOUSDATA in CXS specification).
Note:This parameter only sets the Store-Forward mode default value in CXS
Transmitter configuration register which may be overwritten later.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_TX_CONTINUOUSDATA
CXS Receiver Error Full Packet If set to True, this receiver requires that the length of every packet (including packets
ending with EndError) match the packet length specified in the packet header (maps to
CXSERRORFULLPKT in CXS specification).
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RX_ERRORFULLPKT
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Label Description
CXS Transmitter Error Full Packet If set to True, if this transmitter is unable to complete a packet and must end the packet
with an EndError indication, the transmitter will send the number of bytes specified in
the packet header before ending the packet (maps to CXSERRORFULLPKT in CXS
specification).
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_CXS_TX_ERRORFULLPKT
CXS Receiver Data Check Configures data check support on CXSRXDATA, CXSRXCNTL (maps to
CXSDATACHECK in CXS specification): 0 - None 1 - Odd Parity; 1 bit per byte on
CXSDATA and 1 bit for CXSCNTL 2 - SECDED: ECC on a 64-bit granularity; 8 bits per
64 bits of data and 8 bits for CXSCNTL (zero extended to 64 bits) The default value of
this parameter is derived from CX_RASDP setting.
Values:
■ None (0)
■ Odd Parity (1)
■ SECDED (2)
Default Value: (CX_CXS_ENABLE && (CX_RASDP > 0)) ? (CX_RASDP-1) : 0
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RX_DATACHECK
CXS Transmitter Data Check Configures data check support on CXSTXDATA, CXSTXCNTL (maps to
CXSDATACHECK in CXS specification): 0 - None 1 - Odd Parity; 1 bit per byte on
CXSDATA and 1 bit for CXSCNTL 2 - SECDED: ECC on a 64-bit granularity; 8 bits per
64 bits of data and 8 bits for CXSCNTL (zero extended to 64 bits) The default value of
this parameter is derived from CX_RASDP setting.
Values:
■ None (0)
■ Odd Parity (1)
■ SECDED (2)
Default Value: (CX_CXS_ENABLE && (CX_RASDP > 0)) ? (CX_RASDP-1) : 0
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_TX_DATACHECK
Synopsys, Inc.
Label Description
CXS Receiver Signal Replication Signal replication on CXSRXVALID, CXSRXCRDGNT, CXSRXCRDRTN (maps to
CXSREPLICATION in CXS specification). Duplicate: CXSRXVALIDCHK,
CXSRXCRDGNTCHK, and CXSRXCRDRTNCHK are each single bit signals
duplicating the value of the corresponding control signal. Triplicate:
CXSRXVALIDCHK, CXSRXCRDGNTCHK, and CXSRXCRDRTNCHK are each
two-bit signals with each of the 2 bits having the same value as the corresponding
control signal.
Values:
■ None (0)
■ Duplicate (1)
■ Triplicate (2)
Default Value: None
Enabled: 0
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RX_REPLICATION
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PCI Express SW Controller Databook CXS Configuration Parameters
Label Description
CXS Transmitter Output Register Enable output register on CXS Transmitter Data/Control bus outputs.
Enable Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_TX_OUTPUT_REG
CXS RX/TX FIFO RAM Read CXS RX/TX FIFO RAM Read Latency.
Latency Values: 1, 2
Default Value: 1
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RAM_READ_LATENCY
CXS RX/TX FIFO RAM Pipeline Enable pipeline register on CXS RX/TX FIFO RAM output.
Enable Values:
■ false (0)
■ true (1)
Default Value: (CX_CXS_RAM_READ_LATENCY > 1) ? 0 : 1
Enabled: CX_CXS_ENABLE
Parameter Type: Feature Setting
Parameter Name: CX_CXS_RAM_PIPELINE_ENABLE
Synopsys, Inc.
7
Cache Coherent Interconnect for Accelerators
(CCIX)
This section discusses the CCIX PCIe controller. The following topics are discussed:
■ “CCIX PCIe Controller Overview” on page 879
■ “CCIX PCIe Controller Operation” on page 884
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PCI Express SW Controller Databook CCIX PCIe Controller Overview
Application (Native or
Interfaces AXI)
CCIX PCIe
Transaction Layer Transaction Layer
CCIX
Physical Layer(MAC)
Physical Layer(MAC)
Customer Logic
PCIe Protocol PCI Express Link
Synopsys Implementation (PCIe)
CCIX Protocol
Synopsys Implementation (CCIX)
Synopsys, Inc.
■ CCIX Transport DVSEC containing CCIX specific Control and Status Registers (CSRs) for CCIX
Physical, Data Link and Transaction Layers.
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PCI Express SW Controller Databook Frequency, Speed, and Width Support
■ The analysis must be disabled while the link is in the ESM mode.
■ The result of Group 1 (Throughput) is incorrect if the analysis is enabled while Enable Opti-
mized TLP Generation and Reception bit is 1.
■ The group 0 works correctly.
❑ Error Injection
■ Error Injection Control 6 (Packet Error) cannot insert errors into the TLPs transmitted from the
XALI_CCIX interface.
■ The CCIX PCIe controller does not implement CCIX Protocol DVSEC registers. You must implement
them externally.
❑ If the device type is RC, they should be connected directly to the application’s interconnect.
❑ If the device type is not RC, they can be connected to the ELBI.
❑ Regardless of the device type, the PCI capability list must be updated through the DBI read only
write feature to write the offset of the CCIX Protocol DVSEC. For more information on DBI read
only write feature, see “Writing to Read-Only Registers” on page 103).
PHY Type PCIe Express Mode ESM Mode CCIX Speed Mode
Synopsys, Inc.
PHY Type PCIe Express Mode ESM Mode CCIX Speed Mode
125,
250,
(500 or 1000), ccix1_2s ccix2_2s_df ccix3_2s_df ccix4_2s_df NA x8 x16 NA
(1000 or 1250
or 1562.5)
CCIX ESM 62.5, 125,
20/25 (250 or 500),
Configuration (500 or 625 or ccix1_4s ccix2_4s_df ccix3_4s_df ccix4_4s_df NA x4 x8 x16
781.25)
125, 250,
(250 or 500),
ccix_2s ccix_2s ccix_4s ccix_4s g5_4s x4 x8 x16
(500 or 625 or
781.25), 1000
a. The ccix value indicates the CCIX speed mode. The s value indicates the number of 8-bit symbols processed per clock cycle per
lane by the CCIX PCIe controller PIPE interface, in the indicated speed mode. df indicates dynamic frequency.
b. The value in each cell indicates the maximum link width supported. You can configure the controller with a link width up to this
value, and coreConsultant automatically calculates the datapath width.
c. For license scheme information, see the “Checking License Requirements” section in the DWC PCI Express Controller Installation
Guide.
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PCI Express SW Controller Databook Frequency, Speed, and Width Support
PHY
ccix1_2s
ccix1_2s ccix1_4s ccix1_1s ccix2_2s
ccix2_2s ccix2_4s ccix2_1s ccix3_4s
ccix3_2s ccix3_4s ccix3_4s ccix4_4s
Controller ccix4_2s ccix4_4s ccix4_4s g5_4s
ccix1_2s
ccix2_2s
ccix3_2s
ccix4_2s
ccix1_4s
ccix2_4s
ccix3_4s
ccix4_4s
ccix1_2s
ccix2_2s
ccix3_4s
ccix4_4s
g5_4s
Synopsys, Inc.
The initial speed change sequence to attain ESM data rate is as follows:
1. PCIe compliant phase
a. Physical Link is fully compliant to PCI Express Base Specification, Revision 4.0, Version 1.0.
b. Initial transition to LTSSM L0 state operating at 16.0 GT/s data rate.
c. Link-Up to DL_Active state and Flow Control Initialization is complete.
2. Software based discovery and PHY Calibration in L1 state
a. Your application probes the ESM Data Rate Capabilities of the link partner to determine data rates
and configures the ESM Data Rate 0/1 (ESM_DATA_RATE0/ESM_DATA_RATE1) fields of the ESM
Control register (ESM_CNTL_REG).
b. Your application transitions the link to 2.5 GT/s data rate.
c. Your application probes the ESM Data Rate Capabilities of the link partner to determine the Link
Reach Target and configures the Link Reach Target (LINK_REACH_TARGET) of the controller. Based
on the value of LINK_REACH_TARGET, the ESM Extended Equalization Phase3 Timeout (ESM_EX-
T_EQ3_DSP_TIMEOUT)and ESM Extended Equalization Phase2 Timeout (ESM_EXT_EQ2_USP_-
TIMEOUT) fields of the ESM Control register are programmed.
d. Your application queries ESM Mandatory Data Rate Capabilities and ESM Optional Data Rate
Capabilities registers of the link partner, and sets the selected data rates into the Rate Capabilities
of the link partner to determine data rates and configures the ESM Data Rate 0/1 (ESM_-
DATA_RATE0/ESM_DATA_RATE1) fields of the ESM Control register (ESM_CNTL_REG).
e. Your application sets ESM Perform Calibration (ESM_PERFORM_CAL) field of ESM Control Register
for the link partner as well as the controller.
f. Your application drives link to L1 state using L1-PM mechanism.
g. MAC requests PHY calibration on all lanes using the M2P_MessageBus.
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PCI Express SW Controller Databook CCIX Extended Speed Mode Overview
h. PHY performs calibration and acknowledges the calibration complete on all the non-turn-off lanes
to MAC using the P2M_MessageBus.
i. MAC collects the calibration complete on all the non-turn-off lanes. If it is back on all the
non-turn-off lanes, the controller sets the Calibration Complete field (ESM_CALIB_CMPLT) of ESM
status register (ESM_STAT_REG) to 1.
j. Your application drives an exit from L1 state, using the L1-PM mechanism, after the predeter-
mined
ESM Calibration Time has expired.
k. On exit from L1 state, your application must check the Calibration Complete field (ESM_CALIB_C-
MPLT) of the ESM status register (ESM_STAT_REG) on both sides of the link.
i. If ESM_CALIB_CMPLT =0, ESM transition is discontinued and the remaining steps are not
performed.
ii. If ESM_CALIB_CMPLT =1, your application must set the ESM Enable (ESM_ENABLE) field of the
ESM Control register (ESM_CNTL_REG) for both the link partners.
3. Link transition to selected ESM Data Rates
a. Your application sets Target Link Speed and Link Retrain on DSP.
b. In this step, Data Rate change occurs based on PCI Express LTSSM.
Synopsys, Inc.
Perform Calibration
PCI Express Target Link Speed 0001: 2.5GT/s 0100: ESM Data Rate1
Capability
Link Retrain
Link Control
MAC LTSSM L0 L1 Rec L0 Rec Rec.Speed Rec.EQ Rec L0 Rec Rec.Speed Rec.EQ Rec L0
PowerDown[3:0] P0 P1 P0
PIPE Phystatus
Calib ration
P2M_MessageBus[7:0] AK AK AK AK
Complete
AK
■ If the PHY is Long Reach Capable, that is, CCIX_TP_CAP_REG.ESM_REACH_LENGTH =01b, the
controller uses the ESM Extended Timeout value (ESM_EXT_EQ3_DSP_TIMEOUT/ESM_EXT_EQ2_US-
P_TIMEOUT) in the ESM Control Register as the EQ fine tuning time. For all other values of
ESM_REACH_LENGTH, the controller uses the PCIe specification defined timeout value as the EQ fine
tuning time. After timeout, the controller moves to Recovery.Speed LTSSM state.
■ Your application must clear the Quick Equalization Timeout Select (QUICK_EQ_TIMEOUT) field in the
ESM Control register (ESM_CNTL_REG) if the ESM Data Rate1 is achieved after Hot Reset.
Your application can drive quick EQ by performing the following steps (the quick EQ redo has higher
priority than the link reach target):
■ Ensure that the link is in ESM Data Rate1.
■ Probe the ESM Quick Equalization value of the link partner.
■ Initiate a Hot Reset.
■ Set QUICK_EQ_TIMEOUT value in ESM_CNTL_REG register.
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PCI Express SW Controller Databook PIPE Interface
The link performs a quick EQ redo (if the QUICK_EQ_TIMEOUT is not 0) by using the quick EQ timeout
(ESM_QUICK_EQ_TIMEOUT) value in the EQ phase 2/3 at ESM Data Rate1.
Your application can drive EQ redo by using Perform EQ (PERFORM_EQ) field of PCIe Link Control 3
(LINK_CONTROL3_REG) register.
■ Extended EIEOS format used for ESM Data Rate1 (20.0/25.0 GT/s).
■ Control SKP OS format used for ESM Data Rate1 (20.0/25.0 GT/s) and ESM Data Rate0 (16.0 GT/s).
■ PCI Express 8.0 GT/s LTSSM rules reused for ESM Data Rate0.
■ PCI Express 16.0 GT/s LTSSM rules reused for ESM Data Rate1.
Synopsys, Inc.
This section describes PIPE Specification for PCI Express, Version 4.4.1 enhancements for supporting ESM
operation.
■ The controller provides ESM Data Rate information through PIPE message bus.
❑ When the value of ESM Data Rate0/1 (ESM_DATA_RATE0/ESM_DATA_RATE1) or ESM Enable
(ESM_ENABLE) fields in the ESM_CNTL_REG register changes, the controller generates a write trans-
action to the PHY to update this information.
❑ For more information, see “PIPE Message Bus Enhancements to Support ESM Data Rate” on page
889.
■ Calibration handshake in L1 state is done through PIPE message bus. For more information, see “Cali-
bration in P1/L1 state” on page 888.
■ Link Reach Target can be Long Reach (LR) or Short Reach (SR).
■ PCIe rate change protocol is used for ESM Operation.
Your application can drive Calibration in L1 state by performing the following steps.
1. Disable ASPM and L1 substates on both USP and DSP when link enters Gen1 rate.
2. Read the maximum of ESM Calibration Time values from CCIX Transport Capabilities Register on DSP
and USP as the upper limit time for calibration.
3. Set ESM Perform Calibration to initiate calibration.
4. Drive the Link to L1 state using L1-PM mechanism.
5. The controller generates write transaction to set Calibration Request field through PIPE message bus
6. The PHY generates Write Ack command to the controller.
7. The PHY optionally performs calibration for upcoming ESM Data rates.
8. The PHY can turn off PCLK after Step 6.
9. PCLK must be turned on only after the PHY completes the calibration.
10. The PHY generates write transaction to set Calibration Complete through PIPE message bus. If PHY
does not need calibration, your application must set Calibration Complete for the PIPE.
11. The controller generates Write Ack command to the PHY.
12. Your application drives the link to exit L1 using L1-PM mechanism after ESM Calibration timeout.
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PCI Express SW Controller Databook PIPE Interface
Active
PHY Cal ibrati on Stat e
PowerDown[3:0] P0 P1 P0
Phystatus
PIPE
Calibrati
M2P_MessageB us[7:0] on Req
AK
Calibration
P2M_MessageB us[7:0] AK
Complete
Table 7-68 describes the PHY register enhancements and Table 7-69 describes the MAC register
enhancements to support ESM Data Rate.
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Different error detection rules apply to TLPs received on the PCIe VC and on CCIX VC. Traffic Class (TC)
label on received TLPs is used to steer the traffic either to PCIe VC or CCIX VC. To switch between PCIe
compatible TLP format and CCIX optimized TLP format use CCIX_EN_OPT_TLP_GEN_RECPT field of the
CCIX_TL_CNTL_REG register. CCIX TLPs are processed as per the CCIX Transport Specification, good CCIX
TLPs are passed to the CCIX TRGT1 interface.
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PCI Express SW Controller Databook CCIX Transaction Layer Receiver Operation
7.2.3.2 Rx VC Arbitration
The ordering between the CCIX VC and the PCIe VC is achieved using TRGT1 packet Grant/Halt signals
(radm_grant_tlp_type/trgt1_radm_pkt_halt).
■ radm_grant_tlp_type indicates the type of TLP received, CCIX TLP (both the PCIe Compatible
TLP/CCIX Optimized TLPs) or PCIe TLP. trgt1_radm_pkt_halt[cfg_ccix_vc_re-
source*3+:1] controls the CCIX VC and PCIe VC arbitration. For more information on the usage of
the TRGT1 Packet Grant/Halt signals, see “TRGT1 Packet Grant and Halt” on page 291.
■ While the CCIX TLPs are being forwarded to your application through the TRGT1_CCIX interface, the
RTRGT1 interface does not forward the TLPs to your application. Similarly, TRGT1_CCIX never
forwards the TLPs to your application while TLPs are being forwarded to your application through
RTRGT1 interface. Therefore, halting of the TRGT1_CCIX interface by ccix_radm_halt or RTRGT1
interface by trgt1_radm_halt affects the bandwidth of both the interfaces.
■ radm_grant_tlp_type[cfg_ccix_vc_resource*3+1+:2] is never asserted when the
Non-Posted / Completion buffers on the CCIX VC are in the store-and-forward mode.
■ If the AMBA bridge is enabled, trgt1_radm_pkt_halt[cfg_ccix_vc_resource*3+:1] must be
controlled by your application. The other bits of trgt1_radm_pkt_halt must be 0.
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8
Embedded EndPoint (Switch DSP Integrated
EndPoint)
This section describes the Embedded EndPoint solution provided by Synopsys which is currently available
through Statement of Work (SoW) flow. The following topics are discussed:
■ “Overview” on page 893
■ “Advantages of Embedded EndPoint Solution Over Pipe Connected EndPoint” on page 895
■ “Embedded EndPoint Delivery Flow” on page 896
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PCI Express SW Controller Databook Overview
8.1 Overview
Embedded EndPoint or Switch DSP integrated EndPoint is a complete solution which consists of PCIe
Switch DSP connected to PCIe EndPoint using glue logic (bypassing the need to have a physical link
between the Switch DSP and EndPoint), clock and reset logic, RAMs, and merged synthesis constraints.
EP Subsystem SW Subsystem
EP SW
(dwc_pcie_ctl) (dwc_pcie_ctl)
EP SW
Clock and Clock and
Reset Reset
EP RAMs SW RAMs
You can re-purpose the Embedded EndPoint solution to work with different designs and different
architectures. Figure 8-5 describes a scenario in which the same Embedded EndPoint solution can be
re-used to connect to SATA AHCI, Giga Ethernet, and NVMe Controller.
PIPE
Switch Switch
USP USP
Switch Fabric
Switch
Embedded Embedded Embedded
DSP
EndPoint EndPoint EndPoint
PIPE
PCIe Gen3
AXI
AXI
AXI
PHY x1
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Features
■ Full Multifunction Support
■ Supported PCIe controller features
❑ All the PCIe controller supported datapath widths
❑ Native/AXI interface
❑ SR-IOV
❑ Embedded DMA
❑ MSIX
❑ FLR
❑ LTR
❑ AER
■ Most of the application layer controller features can be supported without modifications
Architecture
Figure 8-6 describes the Embedded EndPoint architecture.
DWC_pcie_ctl
XADM RADM
CXPL EMULATION
Downstream Port
CXPL EMULATION
Upstream Port
RADM XADM
DWC_pcie_ctl
The CXPL emulation module connects the downstream port and upstream port XADM and RADM
modules and emulates the PCIe layers and PHY. The RADM and XADM modules are the same as the ones
present in EndPoint and Switch products.
Power Management
■ PCIe controller power management is supported for Embedded EndPoints as well.
■ ASPM support is under development.
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PCI Express SW Controller Databook Advantages of Embedded EndPoint Solution Over Pipe Connected EndPoint
Area (Kgates)
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PCI Express SW Controller Databook Advanced Information: Gen3/4/5 Equalization Details and Example
A
Advanced Information: Gen3/4/5 Equalization
This appendix discusses advanced aspects of Gen3 or above equalization operation, and also provides a
usage example. The terms MAC and PCIe controller are used interchangeably in this section. The following
topics are discussed:
■ “Equalization Overview and Synopsys-Specific Features” on page 898
■ “Detailed Equalization Procedure” on page 907
■ “Usage Example” on page 915
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PCI Express SW Controller Databook Equalization Overview and Synopsys-Specific Features
LEC Register
M M M M
A A A A
C TS2 OS C C C
P RX P P RX P
TX TX
H Equalizer H H Equalizer H
Equalizer Equalizer
Y Y Y Y
TS2 OS
P P P P
RX TX RX TX
H H H H
Equalizer Equalizer Equalizer Equalizer
Y Y Y Y
TS2 OS
M M M M
A A A A
C C C C
PHASE 2 8.0 GT/s USP Adapting DSP TX Coefficients PHASE 3 8.0 GT/s DSP Adapting USP TX Coefficients
DOWNSTREAM PORT : EQ SLAVE DOWNSTREAM PORT : EQ MASTER
M M M M
Coefficient
A Apply A A A
Adaptation
C Coefficients C C TS OS C
Engine
P P P FOM/DIR P
TX C-1 , C0, C+1
H H H H
Equalizer
Y Y Y Y
P P P P
TX
H H H H
FOM/DIR C-1, C0, C+1 Equalizer
Y Y Y Y
Coefficient TS OS
M M M Apply M
Adaptation A A
A A Coefficients
Engine
C C C C
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■ When a downstream port is redoing equalization from the Gen3 or above speed L0
Note state and its PHY mapping time from presets to coefficients is greater than the dura-
tion of two TS ordered sets (OS); the controller does not strictly follow the specification
requirement: “The Port must ensure that no more than 2 TS1 OS with EC=00b are
transmitted due to being in Recovery.RcvrLock before starting to transmit the TS1 OS
required by Recovery.Equalization.” However, this does not impact any functionalities
in the controller if the mapping time is less than the duration of 8 TS OS.
■ If the PHY's mapping time is greater than the duration of 8 TS OS, the controller
cannot prevent transmitting 8 or more TS1 OS with EC=00b, which is interpreted by
the remote partner side as a condition to go to Recovery.RcvrCfg instead of
Recovery.Equalization. This defeats the intent of redoing equalization. This should
never happen because the PHY typically takes less than the duration of two TS OS to
complete the mapping.
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PCI Express SW Controller Databook Coefficient Tuning Feedback Modes
Figure A-2 Preset Mapping Modes (Symbolic Representation; not Actual Implementation)
DOWNSTREAM PORT
LEC[3:0]
1 0
Phase 1
PSET_COEF_MAP_MODE
“Use Preset” bit
0 1 2
1 TS1
Phase 1 ||
0 1
Phase 2/3 && ! “Use Preset”
3x6
P P
TX C-1, C0 , C+1
H H
Equalizer
Y Y
P P
H H
FOM/DIR
Y Y
M Coefficient TS1 M
A Adaptation A
C Engine C
UPSTREAM PORT
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the highest FOM. This can be considered coarse or rough tuning as the only possible coefficient sets are
those specified in the preset table in the PCIe specification. If your PHY does not support FOM, then it is
expected that your PHY returns a constant value on phy_mac_fomfeedback for each preset request (if
any), and the final preset is used as the starting point for the DIR process.
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PCI Express SW Controller Databook Coefficient Tuning Feedback Modes
Figure A-3 Representational (Not Actual) Flowchart Showing the Sequence of Major Operations for EQ Master
Calculate next
Preset
coefficient and
Request Vector
request remote
In Gen 3 EQ
TX to use it
Control register
= 0x0
No
Store DIR
feedback from
Start FOM local PHY
Request
remote TX to Use
advanced
use next No convergence
preset
support
Yes
Store FOM
value from local
PHY DIR Store coefficient
feedback is 0
and delta
for all
lanes
More
Yes Presets To
Try
Settling criteria
No
No matched
Select preset
with highest Yes
FOM and
request remote
TX to use it .
Gen3 EQ
Control register ->
Feedback Mode =
0x0
End
No
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PCI Express SW Controller Databook Other Features and Limitations
transmitter, requested and evaluated in the last N attempts have a maximum delta that does not exceed a
value D. The convergence parameters N and D are programmable and correspond respectively to the
Convergence Windows Depth and Convergence Window Aperture fields in the Gen3 EQ Direction Change
Feedback Mode Control Register (GEN3_EQ_FB_MODE_DIR_CHANGE_OFF). To prevent premature
convergence, the criteria also require that a minimum time T has elapsed from when the EQ Master phase
has started. The value of this timer T is programmable in the Gen3 EQ Direction Change Feedback Mode
Control Register (GEN3_EQ_FB_MODE_DIR_CHANGE_OFF).
Notes:
■ When step 2 and 3 are skipped, the incremental adjustments of the coefficients in step 4 starts from the
settings that the remote transmitter has used to enter phase 2 or phase 3. When step 2 and 3 are
executed, the incremental adjustments of the coefficients start from the final preset requested in step 3.
■ For step 3, it is also possible to choose (using the Include Initial FOM field in the Gen3 EQ Control
Register GEN3_EQ_CONTROL_OFF), whether to include or not the FOM feedback from the evaluation
performed in Step 1, when finding the highest FOM among all Preset evaluations.
■ Typically this mode is used in conjunction with zero, or at most one preset selected in the Preset
Request Vector field, such that no more than one evaluation is performed in step 2.
Bits Default
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The Gen3 EQ Presets to Coefficients Mapping registers are programmed through a register indirect
addressing scheme (using an index register) to reduce the address footprint in the PCI Express extended
configuration space. This register is only used when you set the Gen3 Equalization Presets to Coefficients
Mapping Mode to Programmable Table, by setting the CX_GEN3_EQ_PSET_COEF_MAP_MODE configuration
parameter to 2. The default value for each register is given in Table A-2.
0 round(DEFAULT_GEN3_EQ_LOCAL_FS/4) 0
1 round(DEFAULT_GEN3_EQ_LOCAL_FS/6) 0
2 round(DEFAULT_GEN3_EQ_LOCAL_FS/5) 0
3 round(DEFAULT_GEN3_EQ_LOCAL_FS/8) 0
4 0 0
5 0 round(DEFAULT_GEN3_EQ_LOCAL_FS/10)
6 0 round(DEFAULT_GEN3_EQ_LOCAL_FS/8)
7 round(DEFAULT_GEN3_EQ_LOCAL_FS/5) round(DEFAULT_GEN3_EQ_LOCAL_FS/10)
9 0 round(DEFAULT_GEN3_EQ_LOCAL_FS/6)
round((DEFAULT_GEN3_EQ_LOCAL_FS -
10 0
DEFAULT_GEN3_EQ_LOCAL_LF)/2)
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PCI Express SW Controller Databook Detailed Equalization Procedure
Eq Eq Eq Eq
RcvrCfg Speed RcvrLock Phase 0 Phase 1 Phase 2 Phase 3
done | (24ms &
e3
p23_exit_mode
as
ph
& USP)
Legend: = USP only DS P)
2_
ode &
se
xi t_m
ha
s&p
|| (2 4m
DSP / USP do ne
Programming of Presets
When negotiating to Gen3 speed, before the first speed change to Gen3, the DSP must be programmed with
the preset values for its own transmitter and receiver (local presets) and the preset values for the USP
(remote presets). The values are independent for each lane and are programmed in the corresponding LEC
of the Secondary PCIe Extended capability.
When negotiating to Gen4 speed, before the first speed change to Gen4, the DSP must be programmed with
the preset values for its own transmitter and receiver (local presets) and the preset values for the USP
(remote presets). The USP can be programmed with the preset values for the transmitter preset values for
the DSP (remote presets). The values are independent for each lane and are programmed in the
corresponding LEC2 of the Secondary PCIe Extended capability.
A.2.2 Recovery.RcvrCfg
When negotiating to Gen3 speed, before the speed change to Gen3 data rate, each component is required to
enter Recovery from L0. In Recovery.RcvrCfg the DSP sends eqTS2s to the USP with the preset fields
reflecting the values programmed in the LEC registers. The USP is required to latch the preset fields in
received eqTS2s and report the latched values as RO fields in the LEC registers.
When negotiating to Gen4 speed, before the speed change to Gen4 data rate, each component is required to
enter Recovery from L0. In Recovery.RcvrCfg the DSP sends 8geqTS2s to the USP with the preset fields
reflecting the values programmed in the LEC2 registers. The USP is required to latch the preset fields in
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received 8geqTS2s and report the latched values as RO fields in the LEC2 registers. If “Upstream Port Send
8GT/s EQ TS2 Disable” (in GEN3_RELATED_OFF) for Gen4 is set to 0b, the USP controller sends 8geqTS2s to
the DSP with transmitter preset fields reflecting the values programmed in the LEC2 registers. The DSP is
required to latch the preset fields in received 8geqTS2s.
A.2.3 Recovery.Speed
In preparation for the speed change to Gen3 or above the PCIe controller asserts mac_phy_txelecidle to
the PHY and updates mac_phy_rate[1:0] to 2’b10(Gen3) or 2'b11(Gen4) to request a data rate change.
The request returning phy_mac_phystatus. Following phy_mac_phystatus the PCIe controller updates
the internal data rate variable (used in LTSSM) to match the requested data rate on mac_phy_rate.
At this point the PHY asserts valid values on phy_mac_localfs[5:0] and phy_mac_locallf[5:0].
These values correspond to FS and LF in use by the PHY transmitter. The PCIe controller uses these values
to check that the coefficients—corresponding to the preset that must be initially used at Gen3 data rate
(obtained from the eqTS2s for USP or from the LEC for DSP) or Gen4 data rate (obtained from the 8geqTS2s
for USP/DSP or from the LEC2 for DSP) —are legal according to the rules in chapter 4.2.3.1 of the PCI
Express Base Specification, Revision 4.0, Version 1.0. The same LF and FS values are also advertised through
ec1TS1s to the remote link partner during phase 1 of the equalization procedure.
To obtain the coefficients corresponding to the initial preset, the PCIe controller requests the PHY to
perform the conversion, by configuring CX_GEN3_EQ_PSET_COEF_MAP_MODE to Dynamic PHY. This is
done by asserting mac_phy_getlocal_pset_coef with mac_phy_local_pset_index[3:0] set to the
encoding of the preset. When the PHY responds with phy_mac_local_tx_coef_valid, the PCIe
controller checks that the values on phy_mac_local_tx_pset_coef[17:0]are legal, and if legal, it
reflects the same values into mac_phy_txdeemph[17:0].
When the values on phy_mac_local_tx_pset_coef[17:0]are not legal, the PCIe controller drives
mac_phy_txdeemph[17:0] with the coefficients that correspond to P4, that is, {6'b0,
phy_mac_localfs[5:0], 6'b0}. The controller also drives mac_phy_rxpresethint[2:0] with the
receiver preset Hints obtained from the eqTS2s(for Gen3)/ 8geqTS2s (for Gen4) for USP, or from the LEC
(for Gen3) / LEC2(for Gen4) for DSP. The controller uses the same mechanism for “Dynamic MAC” and
“Programmable Table”, but the mac_phy_getlocal_pset_coef / mac_phy_local_pset_index[3:0],
and phy_mac_local_tx_coef_valid / phy_mac_local_tx_pset_coef[17:0] signals are not used. In
these modes, the PCIe controller uses internal signals to do the preset-to-coefficients mapping and legality
check. The coefficients are encoded as coefficient[17:0] ={[5:0], [5:0], [5:0]} ={C+1, C0,
C-1} ={post-cursor, cursor, pre-cursor}.
A.2.4 Recovery.RcvrLock
This LTSSM state is entered after Recovery.Speed. Both sides of the link transmit ec0TS1s. When the LTSSM
determines that the equalization procedure must be performed, the next state is Recovery.Equalization.
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PCI Express SW Controller Databook Recovery.Equalization Phase 1
Note: phy_mac_localfs and phy_mac_locallf represent the LF and FS values of the local transmitter in
the USP, but mac_phy_fs and mac_phy_lf represent the LF and FS values of the remote transmitter.
The PHY can use the remote LF and FS to determine how to adjust the coefficients of the remote transmitter
during phase 2. The procedure moves to phase 1 after receiving two ec1TS1s. The PCIe controller asserts the
smlh_ltssm_state_rcvry_eq signal for the complete equalization state, including EQ phases 0, 1, 2, and
3.
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■ RST: this is the default state. Entered when the LTSSM is not in phase 2. The PCIe controller resets to
the inactive state (zero) all these phase 2 specific inputs to the PHY: mac_phy_rxeqeval, mac_phy_-
invalid_req, mac_phy_rxeqinprogress.
■ INIT: the controller asserts mac_phy_rxeqinprogress, latches the preset and coefficients in use on the
remote side from the received ec2TS1s, and initializes the internal registers containing the preset and
coefficients to be evaluated by the local receiver.If EQ_EIEOS_CNT field of GEN3_RELATED_OFF
Register is set to '1', the next state is EVAL, else the next state is WAIT_REI.
■ Wait_REI:
Rgardless_RxTS Mode: The next state is EVAL, as the controller asserts mac_phy_rxeqeval regardless
of the fact that RX TS1s are detected or not. The REI bit is set to '1' only when any lane asserts mac_-
phy_rxeqeval.
Legacy Mode: If all active lanes are sending TS1s with REI bit set to '1' or there is a 2ms timeout, the next
state is EVAL. The condition that all active lanes are sending TS1s with REI bit set to '1' is dependent
on whether all the active lanes achieve Block Alignment after the remote partner applies the new EQ
settings to its transmitter or not. This is done to filter out scenarios which fail EQ evaluation.
For example, if the controller detects TS1s on any lane and sends TS1s with REI bit set to the remote
partner, the remote partner immediately sends an EIEOS after 65536 TS1s across all lanes; as a result
of this, lanes without Block Alignment may not obtain Block Alignment for the new EQ settings.
If EQ_EIEOS_CNT field of GEN3_RELATED_OFF Register is set to '0' during PHY's evaluation of active
lanes losing Block Alignment (phy_mac_rxvalid =0), the controller transmits TS1s with REI bit reset
to '0' on all active lanes so that the PHY can obtain Block Alignment again.
■ EVAL:
Rgardless_RxTS Mode: After 500ns timeout since new request the controller asserts mac_phy_rx-
eqeval to instruct the PHY to evaluate the current remote transmitter settings. After all lanes involved
have indicated completion of the evaluation cycle with phy_mac_phystatus, the controller
de-asserts mac_phy_rxeqeval immediately. If all lanes involved detected TS1s after 1us timeout
since new request or 2ms timeout the next state is FEEDBACK.
Legacy Mode: the controller immediately asserts mac_phy_rxeqeval. After all involved lanes have
received phy_mac_phystatus the next state is FEEDBACK.
All modes: during the evaluation cycle if any lane involved does not received phy_mac_phystatus
after 2ms timeout and GEN3_EQ_EVAL_2MS_DISABLE field of GEN3_EQ_CONTROL_OFF Register is set
to ‘0’, or 24ms timeout, the next state is ABORT.
Depending upon the cause of transition to EVAL state, the following action should be taken with
respect to coefficients:
❑ If the EVAL state is entered because of a valid request (accepted by remote partner), then latch the
coefficients in use by remote transmitter.
❑ If the EVAL state is entered because of an invalid request (rejected by remote partner) or 2ms
timeout (no reject or accept is received), then do not latch the coefficients. Latching the coefficients
causes phy_mac_dirfeedback[5:0] to generate new coefficients based on valid coefficients
during transition from the final preset request to the first coefficients request.
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PCI Express SW Controller Databook Recovery.Equalization Phase 2
Figure A-5 EQ Master Flowchart Showing the Sequence of Operations in Phase 2 when PCIe Controller is USP
RST
Phase 2 No
Yes
S EXIT INIT
U EXIT
REI disable ?
Yes
No
WAIT_REI
EVAL
timeout
500ns No
Yes
rxeqeval <= 1
Yes
accept Yes
No pset_accept
<= 1
reject Yes
No pset_reject
<= 1
SKIP_EVAL
phystatus
Yes asserted all &&
timeout_1us
rxeqeval <= 0
Yes pset_accept ||
No phystatus||
pset_reject
timeout 2ms No
No
timeout 2ms
ti meout 2ms &&
!t im eout _2ms _dis Yes ABORT
Yes
No
No
pset_reject
<= 1 timeout 24ms Yes
No
state==EVAL Yes
?
No
FEEDBACK
Yes optimal
No
NEWCOEF
Yes
REQ
WAITRESP
Yes
RXEQ_RLESS_RXTS
&& FOM ?
No pset_accept <= 1
TIMEOUT_REQ
accept Yes
No
No
No
No
No
Yes
pset_reject <= 1
■ FEEDBACK: the controller de-asserts mac_phy_rxeqeval. When the Preset Request Vector field of
the Gen3 EQ Control Register GEN3_EQ_CONTROL_OFF has any bits set, the LTSSM moves to
NEWCOEFF and executes loops so that each preset in the Preset Request Vector field is requested and
evaluated. When all presets are requested and evaluated, then a final preset with the highest FOM
from phy_mac_fomfeedback[7:0] is requested.
❑ If the final preset request is rejected by the remote partner, and if the feedback mode is FOM, then
the next state is EXIT (with unsuccessful status), else if the final preset request is accepted by the
remote partner, next state is EXIT (with successful status).
❑ When the Preset Request Vector field is 0 (no preset request) or the feedback mode is Direction
Change after all preset requests, then the controller evaluates the feedback provided by the PHY
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on phy_mac_dirfeedback. It then determines from that feedback, if the current settings of the
remote transmitter are optimal. When they are optimal, the next state is EXIT (with successful
status), otherwise the next state is NEWCOEF.
■ NEWCOEF:
❑ For preset requests, the requested preset value is determined by right-shifting the 16-bit Preset
Request Vector field of the Gen3 EQ Control Register (GEN3_EQ_CONTROL_OFF) until bit[0] is 1.
This right-shifted number becomes the requested preset value. If the preset is found, the next state
is REQ.
❑ For coefficients requests, new coefficients for evaluation are calculated by applying the direction
change feedback to the current coefficients under evaluation. If the results satisfies the rules from
4.2.3.1 in the PCI Express Base Specification, Revision 4.0, Version 1.0, the next state is REQ, else it is
INV REQ.
■ REQ: the PCIe controller transmits ec2TS1s (preset/coefficients request by setting Use Preset bit to
1/0) to request the remote link partner to change the transmitter settings to the new preset or coeffi-
cients calculated in the previous state. Next state is WAITRESP.
■ WAITRESP:
Rgardless_RxTS: The next state is EVAL where the controller asserts mac_phy_rxeqeval after 500ns
timeout and start detecting TS1s after 1us timeout since new preset request.
Legacy Mode: The controller monitors the received ec2TS1s (after 1us timeout since new request), to
determine if the remote link partner has accepted the request to change its transmitter settings.
❑ If the request is accepted and EQ_EIEOS_CNT field of GEN3_RELATED_OFF Register is set to '1', the
next state is EVAL.
❑ If the request is accepted and EQ_EIEOS_CNT field of GEN3_RELATED_OFF Register is set to '0', the
next state is WAIT_REI.
❑ If the request is rejected and it is a FOM request, the next state is SKIP_EVAL.
❑ If the request is rejected and it is a DIR request, the next state is INV REQ.
❑ If request is FOM after a 2ms timeout the next state is SKIP_EVAL.
❑ If request is DIR after 2ms timeout the next state is TIMEOUT_REQ.
❑ Otherwise after 24ms timeout the next state is EXIT with unsuccessful status.
■ SKIP_EVAL: this state does not assert mac_phy_rxeqeval for the PHY to perform evaluation, as the
requested preset is rejected or does not work on the lane. The next state is FEEDBACK to seek the next
new preset after all active lanes (excluding the SKIP_EVAL lanes) complete evaluation. Otherwise,
after 24ms timeout the next state is EXIT with unsuccessful status.
■ TIMEOUT_REQ: this state is used to prepare the request needed to restore the last successful coeffi-
cients into the remote transmitter. The next state is REQ.
■ INV REQ: this state is used to assert mac_phy_invalid_req to indicate to the PHY, that the feedback
on the latest evaluation generated an invalid set of coefficients for the remote link partner.
The next state is EVAL if EQ_EIEOS_CNT field of GEN3_RELATED_OFF Register is set to '1'; Else, the
next state is WAIT_REI. The evaluation on the current set of coefficients is repeated (the PCIe
controller does not request through ec2TS1s any change to the remote transmitter settings in this case)
to give the PHY an opportunity to provide a different feedback on the same set of coefficients.
■ ABORT: this state is entered when the controller needs to abort an evaluation cycle (because of 2ms1
or 24ms timeout while mac_phy_rxeqeval is asserted, and the PHY has not yet terminated the eval-
1. GEN3_EQ_EVAL_2MS_DISABLE field of the GEN3_EQ_CONTROL_OFF register is set to ‘0’; its default value is ‘1’.
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PCI Express SW Controller Databook Recovery.Equalization Phase 2
uation with phy_mac_phystatus).The controller asserts the mac_phy_rxeqeval signal and then
waits for the PHY to acknowledge with phy_mac_phystatus. The next state is EXIT with unsuc-
cessful status, after the PHY responds on phy_mac_phystatus or a timeout.
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Figure A-6 EQ Slave Flowchart Showing Sequence of Operations in Phase 2 when PCIe Controller is DSP
RST
Phase 2 No
Yes
WAIT REQ
Yes Preset
PSET2 No
COEF
legal No
Yes
CHANGE
TXDEEMPH
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PCI Express SW Controller Databook Usage Example
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with phy_mac_fomfeedback[7:0] =8d188 within 2ms, the controller moves to FEEDBACK and
then to NEWCOEFF.
i. In NEWCOEFF, latch FOM =8d188 and its corresponding preset 2, as 188 is larger than 12 (you
must find the preset with highest FOM). Then find out the second requested preset 5 and repeat
steps f, g, and h. Assuming phy_mac_fomfeedback[7:0] =8d66 for the last request preset 5. As
phy_mac_fomfeedback =66 is not the highest FOM, you must to do one more preset request, that
is, final preset request for the preset 2 again as the preset 2 has highest FOM =8d188. After WAIT-
RESP, next state is EVAL.
j. In EVAL, mac_phy_rxeqeval =1, latch coefficients received in TS1s from the remote partner that
are the coefficients in use by the remote partner. Assuming the latched coefficients= 18h00f80. After
receiving phy_mac_phystatus from PHY with phy_mac_dirfeedback =6b010101, move to
FEEDBACK to do coefficients requests. All the preset requests are completed.
k. In FEEDBACK, mac_phy_rxeqeval =0. Cannot get optimal settings as the programmed number
of consecutive coefficients evaluations is 3. So far in the coefficients evaluation process, it is 0. Next
state is NEWCOEFF.
l. In NEWCOEFF, need to calculate new coefficients. The current coefficients are =18h00f80, then C-1
=6b000000, C0 =6b111110, C+1 =6b000000. Because phy_mac_dirfeedback =6b010101, so the
new coefficients are C-1 =6b000001, C+1 =6b000001, C0 =(mac_phy_fs C-1 C+1) =(6h2b 1 1) =6h29.
The new coefficients =18h01a41. Now check the new coefficients legality (“4.2.3.1 Rules for Trans-
mitter Coefficients” section of the PCI Express Base Specification, Revision 4.0, Version 1.0).
Note: C0 is calculated, so ignore phy_mac_dirfeedback[3:2].
■ |C-1| =1 <= Floor (FS/4) =Floor (43/4) =10. So it is legal.
■ |C-1| + C0 + |C+1| =43 =FS =43. So it is legal.
■ C0 - |C-1| - |C+1| =41 >= LF =6h12 =18. So it is legal
Next state is REQ.
m. In REQ, reset and start 2ms timer. Set Use Preset bit to 0 and place the new coefficients C-1, C0 and
C+1 into the correct TS1 fields, and send TS1s to the remote partner. Next state is WAITRESP.
n. In WAITRESP, assuming accept is received in the response TS1s from the remote partner within
2ms. Next state is EVAL.
o. In EVAL, mac_phy_rxeqeval =1, the number of evaluation increments by 1 and push C-1 =1
and C+1 =1 into coefficient queues. Waiting for phy_mac_phystatus back from PHY. Assuming
phy_mac_phystatus is asserted back with phy_mac_dirfeedback =6b010001within 2ms, then
move to FEEDBACK and repeat steps k, l, m, and n.
p. After re-enter EVAL, mac_phy_rxeqeval =1. The number of consecutive evaluations is 2 and
C-1 =2 and C+1 =2 are pushed into the queues. Waiting for phy_mac_phystatus back from PHY.
Assuming phy_mac_phystatus is asserted back with phy_mac_dirfeedback
=6b011110within 2ms, then move to FEEDBACK and repeat steps k, l, m, and n.
q. After re-entering EVAL, mac_phy_rxeqeval =1, and the number of consecutive evaluations is
3, and C-1 =1 and C+1 =3 are pushed into queues. Waiting for phy_mac_phystatus back from
PHY. Assuming phy_mac_phystatus is asserted back with phy_mac_dirfeedback =6b101000
within 2ms, then move to FEEDBACK.
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PCI Express SW Controller Databook Usage Example
r. In FEEDBACK, mac_phy_rxeqeval =0, assuming the time spent on the phase in the EQ master
so far is 9ms, you must find out if the optimal settings are reached as the number of consecutive
evaluations reaches 3 (the programmed number of consecutive coefficients evaluations).
i. For C-1, three coefficients (1, 2, 1) are pushed into its queue. So the delta for C-1 is (2-1) =1.
ii. For C+1, three coefficients (1, 2, 3) are pushed into its queue. So the delta for C+1 is (3-1) =2.
Because the programmed maximum delta for C-1 and C+1 is 1, the delta 2 in the queue for C+1
window does not satisfy the programmed maximum delta. In addition, the time for the conver-
gence check does not satisfy the programmed minimum time 10ms because it is 9ms by now. So
the controller can proceed with the next request. Repeat l, m, and n.
s. After re-entering EVAL, mac_phy_rxeqeval =1, the number of consecutive evaluations is 3 and C-1
=1 and C+1 =2 are pushed into queues. Waiting for phy_mac_phystatus back from PHY.
Assuming phy_mac_phystatus is asserted back with phy_mac_dirfeedback
=6b010110within 2ms, then move to FEEDBACK.
t. In FEEDBACK, mac_phy_rxeqeval =0, assuming the time spent on the phase in the EQ master
so far is 10.5ms. You must find out if the optimal settings are reached as the number of consecutive
evaluations reaches 3.
i. For C-1, three latest coefficients (2, 1, 1) are pushed into its queue. So the delta for C-1 is (2-1) =1.
ii. For C+1, three latest coefficients (2, 3, 2) are pushed into its queue. So the delta for C+1 is (3-2)
=1.
Because the programmed maximum delta for C-1 and C+1 is 1, the delta in the both queues for C-1
and C+1 window does satisfy the programmed maximum delta. The time for the convergence
check also satisfies the programmed minimum time of 10ms because it is 10.5ms by now. Next
state is EXIT.
u. In EXIT, mac_phy_rxeqinprogress =0, the successful status bit for the phase is set to 1. The
PCIe controller moves to the phase3 for USP or Recovery.RcvrLock for DSP.
EQ Slave
■ Hardware Configuration
❑ CX_GEN3_EQ_PSET_COEF_MAP_MODE =0 (Dynamic PHY)
■ Mapping and Applying
a. Assuming phy_mac_localfs =6’h3e and phy_mac_locallf =6’h11 are already set before the
port changes to Gen3 or above rate.
b. When the controller enters EQ slave, the state machine shown in Figure A-6 on page 914 moves to
WAITREQ state, transmitter sends TS1s with the preset and coefficients in use. If two consecutive
TS1s with EC[1:0] =2b11 for USP or EC[1:0] =2b10 for DSP have been received in the beginning of
the phase, or two consecutive TS1s (with EC[1:0] =2b11 for USP or EC[1:0] =2b10 for DSP) with a
preset (Use Preset bit =1) different from the last two TS1s with the same EC[1:0] have been received,
next state is PSET2COEF.
c. In PSET2COEF, assuming the received request preset =4b0011, the PCIe controller asserts mac_-
phy_getlocal_pset_coef for one cycle with mac_phy_local_pset_index[3:0] =4b0011 to
PHY. Waiting for coefficients mapped back from PHY. A few cycles later, PHY completes mapping
and asserts phy_mac_local_tx_coef_valid back with phy_mac_local_tx_pset_coef
=18h0a885(C-1 =6b000101, C0 =6b100010, C+1 =6b001010) for one cycle. Next state is CHAN-
GETXDEEMPH.
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d. In CHANGETXDEEMPH, the controller needs to check the coefficients legality (“4.2.3.1 Rules for
Transmitter Coefficients” section of the PCI Express Base Specification, Revision 4.0, Version 1.0).
■ |C-1| =5 <= Floor (FS/4) =Floor (62/4) =15. It is legal.
■ |C-1| + C0 + |C+1| =(5 + 34 + 10) =49 !=FS =62. It is illegal.
So phy_mac_local_tx_pset_coef =18h0a885 is not supplied to mac_phy_txde-
emph[17:0]because the coefficients are illegal (invalid). mac_phy_txdeemph[17:0] is left
unchanged. The EQ slave sends EC TS1s with reject and preset =4b0011 in the TS1 fields back to
the remote partner. The remote partner receives the reject and can do the next preset request with
preset =4b1001. The EQ slave receives two EC TS1s with preset =4b1001 different from the last
preset =4b0011, moves to PSET2COEFF.
e. In PSET2COEF, the PCIe controller asserts mac_phy_getlocal_pset_coef for one cycle with
mac_phy_local_pset_index[3:0] =4b1001to PHY. Waiting for coefficients mapped back
from PHY. A few cycles later, PHY completes mapping and asserts phy_mac_local_tx_co-
ef_valid for one cycle with phy_mac_local_tx_pset_coef =18h06c08 (C-1 =6b001000, C0
=6b110000, C+1 =6b000110) back. Next state is CHANGETXDEEMPH.
f. In CHANGETXDEEMPH, the controller checks the coefficients legality first.
■ |C-1| =8 < =Floor (FS/4) =Floor (62/4) =15. It is legal.
■ |C-1| + C0 + |C+1| =(8 + 48 + 6) =62 =FS =62. It is legal.
■ C0 - |C-1| - |C+1| =(48 - 8 - 6) =34 >=LF =17. It is legal.
So phy_mac_local_tx_pset_coef =18h06c08 is supplied to mac_phy_txde-
emph[17:0]because it satisfies the three rules. PHY detects the change on mac_phy_txde-
emph[17:0]and applies it to its transmitter. The EQ slave sends EC TS1s with accept and preset
=4b1001 in the TS1 fields back to the remote partner. The remote partner receives the accept and
starts to do evaluation. After evaluation, the remote partner might not reach optimal settings and
can continue the next preset request or coefficient request until reaching optimal settings. If it is
preset request, repeat steps b-to-f. If the remote partner reaches optimal settings, it moves to the
next EQ phase and send TS1s with EC[1:0] =2b11 for USP or EC[1:0] =2b00 for DSP. The EQ
slave receives TS1s with EC[1:0] =2b11 for DSP or EC[1:0] =2b00 for USP and moves to
Recovery state for USP or EQ phase 3 for DSP. The successful status is set to 1 for this phase.
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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes
B
Advanced Information: Lane Reversal and
Broken Lanes
This appendix illustrates how the controller uses the lane reversal and lane flip functions to form links and
gives several example using an x8 PCIe controller with an x8 or x4 link partner.
CX_LANE_FLIP_CTRL_EN = 1
CX_AUTO_LANE_FLIP_CTRL_EN =1
CX_AUTO_LANE_FLIP_MUX_ARCH = 2
6 6
2
5 5
1
4 4 Logical Lane0
0
Remote Link
Partner
3 3
2 2
1 1
0 0 Physical Lane 0
Logical Lane0
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Table B-1 Lane Reversal and Lane Flipping Configuration Options (All Enabled by Default)
Note:
■ Lane0 always refers to physical lane0, as determined by its location in the PIPE interface which is [7:0] or [15:0].
■ Full flip is when Logical Lane0 is connected to Lane NL-1.
■ Partial flip is when Logical Lane0 is connected to either Lane NL/2-1, or Lane NL/4-1, or Lane NL/8-1, and so on.
Note: To use any of these features you must set the configuration parameter CX_LANE_FLIP_CTRL_EN=1 and the
AUTO_LANE_FLIP_CTRL_EN field in GEN2_CTRL_OFF =1.
Note: Flip: When the LTSSM transitions to DETECT_WAIT, meaning that some lanes are detected in DETECT_ACT,
but not all; and lane0 is not detected, the LTSSM autonomously activates a lane flip operation.
Note: Reversal: When the LTSSM transitions to Configuration state and Logical Lane0 receives TS Ordered Sets
with lane number different from '0', the LTSSM automatically performs a lane reversal.
Note: To use this feature you must set the PRE_DET_LANE field in GEN2_CTRL_OFF to 0.
When its value is '0, auto-flip is based on detected lanes and auto-reversal is based on Lane0's lane number in the
received TS Ordered Sets. When its value is not '0', auto-lane multiplexer is based on the programmed value (only
one instantiated multiplexer).
Connection to x2 and x1 link partners work similarly. For more information, see “Link Establishment” on
page 83. It is assumed that you have set the following configuration parameters and register field:
■ CX_LANE_FLIP_CTRL_EN =1
■ CX_AUTO_LANE_FLIP_CTRL_EN =1
■ CX_AUTO_LANE_FLIP_MUX_ARCH =2
■ AUTO_LANE_FLIP_CTRL_EN =1 in GEN2_CTRL_OFF register
■ PRE_DET_LANE =0 in GEN2_CTRL_OFF register
Some of the case examples in this appendix require the programming of the Predetermined Lane for Auto
Flip field (PRE_DET_LANE) in the GEN2_CTRL_OFF port logic register. This field defines which physical lane
is connected to logical Lane0 by the flip operation performed in Detect.
When its value is '0, auto-flip is based on detected lanes and auto-reversal is based on lane0's lane number in
the received TS Ordered Sets. When its value is not '0', auto-lane multiplexer is based on the programmed
value (only one instantiated multiplexer).
Allowed values are:
■ 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1,
depending on which lane is detected
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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes
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7 7
7
6 6
6
5 5
5
4 4
4
3 3
3
2 2
2
1 1
1
0 0 Physical Lane 0
0
Logical Lane0 Logical Lane0
Remote Link
Reversal Mux Flip Mux Partner
7 7 Logical Lane0
0
6 6
1
5 5
2
4 4
3
3 3
4
2 2
5
1 1
6
0 0 Physical Lane 0
7
Logical Lane0
Remote Link
Reversal Mux Flip Mux Partner
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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes
7 7
6 6
5 5
4 4
3 3
3
2 2
2
1 1
1
0 0 Physical Lane 0
0
Logical Lane0 Logical Lane0
Remote Link
Reversal Mux Flip Mux Partner
7 7
6 6
5 5
4 4
3 3 Logical Lane0
0
2 2
1
1 1
2
0 0 Physical Lane 0
3
Logical Lane0
Remote Link
Reversal Mux Flip Mux Partner
Synopsys, Inc.
7 7 Logical Lane0
0
6 6
1
5 5
2
4 4
3
Remote Link
Partner
3 3
2 2
7 7
3
6 6
2
5 5
1
4 4 Logical Lane0
0
Remote Link
Partner
3 3
2 2
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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes
7 7 PAD PAD
7
6 6 PAD PAD
6
5 5 PAD PAD
5
4 4 PAD PAD
4
3 3
3
2 2
2
1 1
1
0 0
0
Remote Link
Reversal Mux Flip Mux Partner
7 7
0
6 6
1
5 5
2
4 4
3
3 3 PAD PAD
4
2 2 PAD PAD
5
1 1 PAD PAD
6
0 0 PAD PAD
7
Remote Link
Reversal Mux Flip Mux Partner
Synopsys, Inc.
7 7
6 6
5 5
4 4
3 3 PAD PAD
3
2 2 PAD PAD
2
1 1
1
0 0
0
Remote Link
Reversal Mux Flip Mux Partner
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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes
LTSSM LTSSM
(Config) (Detect)
7 7
6 6
5 5
4 4
3 3
0
2 2
1
1 1 PAD PAD
2
0 0 PAD PAD
3
Remote Link
Reversal Mux Flip Mux Partner
7 7 PAD PAD
3
6 6 PAD PAD
2
5 5
1
4 4
0
Remote Link
Partner
3 3
2 2
Not supported.
Synopsys, Inc.
7 7
0
6 6
1
PAD PAD
5 5
2
PAD PAD
4 4
3
Remote Link
Partner
3 3
2 2
1 1
0 0
LTSSM LTSSM
(Config) (Detect)
7 7
If auto-flip is enabled, the core
attempts to detect all lanes. When it
sees Lane0 and Lane NL-1 are not
detected, it autonomously auto-flips
(partial) to Lane NL/2 -1.
6 6
PRE_DET_LANE =0 and therefore all
lanes are used for detection.
5 5
4 4
3 3
3
2 2
2
1 1
x2 link also possible 1
depending upon
features of the
remote link partner.
0 0 Physical Lane 0
Logical Lane0
X 0
Remote Link
Reversal Mux Flip Mux Partner
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PCI Express SW Controller Databook Advanced Information: Lane Reversal and Broken Lanes
If auto-flip is enabled
PRE_DET_LANE[15:13] = 3 to “force” a full flip.
6 6
6
5 5
5
4 4
4
3 3
3
2 2
x2, x4 link also possible if : 2
• The remote link partner supports
it, and
• The controller uses manual lane
flip (GEN2_CTRL_OFF. 1 1
1
AUTO_LANE_FLIP_CTRL_EN
= 0), and manual Tx and Rx
lane reversal (tx_lane_flip_en
=1, rx_lane_flip_en = 1)
0 0 Physical Lane0
0
Logical Lane0 X
Remote Link
Reversal Mux Flip Mux Partner
If auto-flip is enabled
PRE_DET_LANE[15:13] = 2 to “force” a partial flip to NL/2-1 .
Without this register setting, the core will not perform this flip,
because Lane 0 is correctly detected.
LTSSM LTSSM
(Config) (Detect)
7 7
6 6
5 5
4 4
Synopsys, Inc.
If auto-flip is enabled
PRE_DET_LANE[15:13] =1 to “force” the core a
partial flip to NL/4-1.
LTSSM LTSSM
(Config) (Detect)
7 7
6 6
5 5
4 4
3 3
2 2
Physical Lane0
0 0
0
Logical Lane0 X
Remote Link
Reversal Mux Flip Mux Partner
LTSSM LTSSM
(Config) (Detect)
7 7
6 6
5 5
4 4
3 3 1
2 2 0
Remote Link
Partner
1 1
0 0
Logical Lane0
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PCI Express SW Controller Databook Advanced Information: Loopback
C
Advanced Information: Loopback
The controller supports local and remote digital loopback. The following topics are discussed:
■ “Overview”
■ “Local Digital Loopback (PIPE/RMMI)” on page 933
■ “Local Analog Loopback” on page 935
■ “Remote Digital Loopback” on page 936
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C.1 Overview
The controller supports local digital and analog loopback modes without the need for a remote link partner,
as shown in Figure C-1 and Figure C-2. You can use this mode for chip production test, or in any other
scenario where you do not have a remote link partner. It also supports remote digital loopback with a
remote link partner acting as the loopback slave, as shown in Figure C-3. You can use this mode for board
debug, BER testing, system debug, or in any other scenario where you have a remote link partner.
Loopback in the controller operates on a per link basis only. You cannot operate it on a per lane basis. The
loopback implementation overrides LinkUp to one (it should be zero according to the specification), and
allows the link to initialize as if it is in L0.
For Gen5 with CCIX ESM configurations and the LTSSM transition is from L0 -> Recovery ->
Configuration.Linkwidth.Start -> Loopback.Entry. If ESM enabled on both sides of the link and the test
scenario tries to achieve ESM Data Rate1 in loopback on the link, then before loopback master initiates
loopback entry, it must set Max Link Speed and Target Link Speed to Gen4 rate (Loopback Slave Max and
Target Link Speed can be Gen5 or Gen4 rate).
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PCI Express SW Controller Databook Local Digital Loopback (PIPE/RMMI)
Figure C-1 Components Involved in Digital Local Loopback Without a Link Partner
Controller Core
TLP
your generated traffic
TS1
LOOP B A CK_E NA B LE=1
PIPE/
P IP E_LOOP B A CK =1 LTSSM RMMI
P IP E_LOOP B A CK_CONTROL_OFF
register
1
TLP
1. This feature is automatically enabled. The CX_PIPE_LOOPBACK_EN hidden configuration parameter is set by default to 1.
Synopsys, Inc.
state. Transmitted TLPs are subject to credit checks as if the link is fully operational. Received TLPs are
subject to error checking and filter checks as it the link is operating in L0 state.
Message Considerations
When the port is an upstream port (USP), you must not enable error message generation. When an error
occurs on the PCIe link, and you have enabled error message generation, the USP generates an Error
message. Traffic generated by the port is looped back to itself, and as an USP does not expect to receive
messages, it generates an additional message, and so on.
A DSP must automatically send a Set_Slot_Power_Limit message when it enters L0, so the message is sent
and is received by the port itself. A DSP does not expect to receive a Set_Slot_Power_Limit message.
Therefore, it is detected as an invalid message, and the unsupported request detected bit in Device Status
register is be set.
When the port is a downstream port (DSP), then internally generated messages are mixed together with
traffic generation by your application on the XALI0/1/2 interfaces .
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PCI Express SW Controller Databook Local Analog Loopback
Figure C-2 Components Involved in Analog Local Loopback Without a Link Partner
Loopback Master
Controller Core
TLP
PIPE
PORT _LINK_CTRL_OFF
register
TLP
PCS PHY
your looped -back traffic
Synopsys, Inc.
Figure C-3 Components Involved in Remote Digital Loopback with a Link Partner
Loopback MASTER
Controller Core
Loopback SLAVE
TLP
Controller Core
your generated traffic
PCS 0
PHY PHY PCS
1
TS1
PIPE
PIPE
TS1
TLP
LOOP B A CK_E NA B LE= 1 mac_phy_txdetectrx_loopback=0
LTSSM
mac_phy_txdetectrx_loopback=1
LTSSM
PORT _LINK_CTRL_OFF
register Loopback Enable=0
TLP 1
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PCI Express SW Controller Databook Exiting Remote Loopback
Message Considerations
When the loopback master is an upstream port (USP), you must not enable error message generation. When
an error occurs on the PCIe link, and you have enabled Error message generation, the USP generates an
Error message. Traffic generated by the master is looped back to itself by the slave, and as an USP does not
expect to receive messages, it generates an additional message, and so on.
A DSP must automatically send a Set_Slot_Power_Limit message when it enters L0, so the message is sent
and is received by the master itself. A DSP does not expect to receive a Set_Slot_Power_Limit message.
Therefore, it is detected as an invalid message, and the unsupported request detected bit in Device Status
register is be set.
When the loopback master is a downstream port (DSP), then internally generated messages are mixed
together with traffic generation by your application on the XALI0/1/2 interfaces .
Gen3 Consideration
According to section 4.2.3. Link Equalization Procedure for 8.0 GT/s Data Rate of the PCI Express Base
Specification, Revision 4.0, Version 1.0, the loopback master is responsible for communicating the Transmitter
and receiver settings it wants the slave to use. It does this through the:
■ EQ TS1 Ordered Sets it transmits in the 2.5 GT/s or 5.0 GT/s data rate
■ Preset or Coefficient TS1 Ordered Sets it transmits in the 8.0 GT/s data rate
The Synopsys implementation of loopback does not support the changing of Preset and Coefficient values
in the Loopback.entry LTSSM state.
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D
Advanced Information: Lane Deskew
This appendix discusses lane-lane deskew by the RX path of the controller. It is a reference for calculating
the maximum theoretical deskew buffer depth; which you can set to a different value based on your PHY
and system requirements. You can disable the deskewing mechanism by setting the CX_DESKEW_DISABLE
configuration parameter. This could be used, for example, when connecting to a multi-lane PHY that
implements lane-lane deskewing.
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PCI Express SW Controller Databook Conventional PCIe Deskew Requirements
■ In releases prior to 4.50a, the deskew buffer depth is calculated from CX_MAX-
Note _SKEW_NUM which has two options only (“Shallow” and “Deep”). Therefore, it is not
possible to select a deeper depth if required.
■ In 4.50a, the CX_MAX_SKEW_NUM parameter is not visible in the coreConsultant GUI.
For existing configurations, you can continue to set it in your configuration batch file. For
new configurations, you can configure lane deskew capabilities using the new
CX_DESKEW_DEPTH_CPCIE parameter.
■ From 4.60a onwards:
❑ The default of the CX_DESKEW_DEPTH_CPCIE parameter is calculated based on
the E12/C8/C10 Synopsys PHY.
❑ The coreConsultant GUI displays (as a read-only parameter) the maximum allowable
PHY skew based on the value of CX_DESKEW_DEPTH_CPCIE.
❑ It is expected that you confirm this PHY skew value with your PHY vendor and
adjust CX_DESKEW_DEPTH_CPCIE accordingly.
❑ The coreConsultant GUI also displays (as read-only parameters) the individual system
skew components used in the total skew calculation.
A multi-lane controller configuration removes lane-lane skew using a deskew buffer. The maximum
possible amount of PIPE lane-lane skew (as measured at the RX deskew buffer in the controller) is
comprised of the following four components:
■ Wire Skew: This is the maximum skew (LRX-SKEW) allowed by PCIe specification at the PHY RX I/O
pads. Added by the channel (physical link) or repeater delay differences.
■ PCS Skew: Assumes that the PHY skew (measured at PHY RX I/O and PIPE Rx interfaces) is
comprised of at least the following components:
❑ SKP symbol insertion/deletion
❑ Gen3/4 sync header removal skew
The sync header removal skew for Gen3/4 configuration accounts for the difference in symbol lock
timing between the lanes. phy_mac_rxdatavalid de-assertion timing can vary between the
lanes.
❑ PHY implementation-specific CDC skew
❑ PHY implementation-specific de-serializer skew
❑ PHY implementation-specific symbol aligner skew
■ MAC Component: 2*core_clk cycles for data processing. For some configurations, an additional
core_clk period is added.
■ Safety Margin: One core_clk period.
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Skew Components
Gen1 20 2 or 3a
Gen2 8 2 or 3
Consult your PHY vendor
Gen3 6 2 1
Gen4 5 2
Gen5 5 2
a. For on Gen1/2 2s/4s configuration an additional core_clk cycle is added because the COM symbol is not always on byte0.
CX_DESKEW_DEPTH_CPCIE
1
2 Wire Skew
3 PHY Skew
4 Safety Margin
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PCI Express SW Controller Databook Advanced Information: Clock and Data Crossing (CDC)
E
Advanced Information: Clock and Data
Crossing (CDC)
This appendix discusses aspects of clock and data crossing. The following topics are discussed:
■ “CDC Overview”
■ “Port Clocking and Input Synchonizers” on page 943
■ “CDC Reports” on page 944
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PCI Express SW Controller Databook Port Clocking and Input Synchonizers
Synchronizing
Input Name Clocka Note
phy_clk_req_n aux_clk
phy_mac_pclkack_n aux_clk
clkreq_in_n aux_clk
perst_n aux_clk
ack_en_vmain aux_clk
phy_mac_rxelecidle aux_clk
a. These signals are syncronized using aux_clk and can be driven/supplied asynchronously to the controller in certain
low-power modes. The presence of aux_clk in the SynchronousTo attribute for these signals identify the syncronizing
clock.
Synopsys, Inc.
0
data[1] 1
Logic
0
data[0] 1
data_enable
src_clk
dest_clk
The controller uses a library of design-specific CDC parts that are mapped to the standard DesignWare
library parts in http://www.synopsys.com/dw/buildingblock.php as follows:
DWC_pcie_bcm01.v DW_minmax
DWC_pcie_bcm05.v DW_fifoctl_if
DWC_pcie_bcm06.v DW_fifoctl_s1_df
DWC_pcie_bcm07.v DW_fifoctl_s2_sf
DWC_pcie_bcm21.va DW_sync
DWC_pcie_bcm22.v DW_pulse_sync
DWC_pcie_bcm23.v DW_pulseack_sync
DWC_pcie_bcm41.v DW_sync
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PCI Express SW Controller Databook CDC Reports
DWC_pcie_bcm43.v DW_8b10b_dec
DWC_pcie_bcm44.v DW_8b10b_enc
DWC_pcie_bcm46_a.v DW_ecc
DWC_pcie_bcm46_b.v DW_ecc
DWC_pcie_bcm46_c.v DW_ecc
DWC_pcie_bcm46_d.v DW_ecc
DWC_pcie_bcm46_e.v DW_ecc
DWC_pcie_bcm48.v DW_crc_p
DWC_pcie_bcm53.v DW_arb_2t
DWC_pcie_bcm55.v DW_arb_rr
DWC_pcie_bcm57.v DW_ram_r_w_s_dff
DWC_pcie_bcm60.v DW_ram_rw_a_ff
DWC_pcie_bcm62.v DW_ram__2r_w_a_ff
DWC_pcie_bcm64.v DW_fifo_s1_df
DWC_pcie_bcm65.v DW_fifo_s1_sf
DWC_pcie_bcmmod57.v DW_ram_r_w_s_dff
DWC_pcie_bcmmod65.v DW_fifo_s1_sf
Metastability Simulation
The CDC synchronizer parts have a behavioral metastability model to simulate metastability mis-sampling
across the clock domain. By passing in the DW_MODEL_MISSAMPLES parameter, the part randomly
mis-samples data transitions across the clock domain, thereby stressing the CDC design. This stressing
highlights areas of the design prone to error caused by divergence and re-convergence as the CDC signals is
skewed by the mis-sampling algorithm.
Synopsys, Inc.
F
Advanced Information: Reset Domain
Crossing (RDC)
The PCIe controller has a number of primary inputs which are asynchronous resets. Some of these resets are
asserted independent of each other, that is, a particular flip-flop can be reset while a flip-flop in its fan-out
cone is not being reset. This scenario can lead to metastability in the destination flip-flop due to the fact that
the start point is reset asynchronously. This issue can be identified by performing reset domain crossing
analysis on the design.
Table F-1 describes the conditions under which the PCIe controller asynchronous resets are asserted.
pwr_rst_n Asserted
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PCI Express SW Controller Databook Advanced Information: Reset Domain Crossing (RDC)
■ Cold Reset: It is a full power on reset cycle during which all resets are asserted. Hence there are no
reset domain crossing issues.
■ Fundamental Reset: It is similar to a Cold Reset except that the pwr_rst_n is not asserted. Reset
domain crossing issues are avoided in fundamental reset, by asserting the controller’s resets synchro-
nous to aux_clk, since all registers reset by pwr_rst_n are clocking by aux_clk.
■ Hot Reset: It may give reset domain crossing issues. The pwr_rst_n, sticky_rst_n,
phy_reg_rst_n, and ret_sticky_rst_n inputs are not asserted, since there are potential reset
domain crossing issues due to the active resets (For example, core_rst_n to pwr_rst_n) during hot
reset.
In the PCIe controller clock-gating during reset assertion is used to ensure that there are no clocks running
during the link down reset event.
■ All controller clocks are gated off in the clock and reset block, when the controller indicates a pending
hot reset, by asserting link_req_rst_not.
■ The resets are only asserted after the clocks have been gated off.
■ The resets are de-asserted after the clocks have been enabled.
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G
Advanced Information: VC-Based Arbitration
This appendix discusses VC-Based Arbitration. For an overview of TLP transmit arbitration mechanisms see
“Transmit TLP Arbitration” on page 87. The following topics are discussed:
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PCI Express SW Controller Databook VC-Based Arbitration Overview
■ 0: VC Based. Provides VC based programmable weighted round robin arbitration (WRR) using two
different arbitration methods for the two groups of VCs:
❑ Strict Priority for the High-Priority VC (HPVC) group
❑ RR or WRR for the Low-Priority VC (LPVC) group
Between the two groups of VCs, arbitration is as follows:
■ The HPVC group is always the highest priority. Within the HPVC group, priority order is by
VC id. The highest VC id has the highest priority. Ties within the HPVC are resolved by
client-based Strict Priority arbitration; XALI0 has lowest, XALI1 higher, and XALI2 (if imple-
mented) highest priority.
■ The LPVC group is of lower priority than the HPVC group. Within the LPVC group, priority is
determined by RR or WRR arbitration as described later. Ties within the LPVC group are
resolved by client-based RR arbitration.
Note: This scheme operates in a manner similar to that described in Section 7.11 of the PCI
Express Base Specification, Revision 4.0, Version 1.0, but provides a different software interface.
This scheme does not have a VC arbitration table, the weights are programmed through port
logic registers.
■ 1: Round Robin (RR). Provides round robin arbitration between the three transmit clients. This is the
default method.
■ 2: Strict Priority. Provides strict priority between the three transmit clients. XALI0 is lowest, XALI1 is
higher, XALI2 (if implemented) is highest.
The value of the Low Priority Extended VC Count field of “Port VC Capability Register 1” determines the
number of VCs (in addition to VC0) that are in the LPVC group. All other VCs are in the HPVC group.
Between the two groups of VCs, arbitration is as follows:
1. The HPVC group is always the highest priority. Within the HPVC group, priority order is by VC id.
The highest VC id has the highest priority.
2. The LPVC group is of lower priority than the HPVC group. Within the LPVC group, priority is deter-
mined by round robin or WRR arbitration as described in the following sections. Ties within the LPVC
group are resolved by client-based round robin arbitration.
Synopsys, Inc.
❑ The VC Arbitration Select field in port VC Control Register (selects the arbitration scheme).
■ The weight assigned to each VC in the LPVC group, as programmed in VC Transmit Arbitration
Register 1 and VC Transmit Arbitration Register 2. The sum of all the programmed weight values must
equal the number of phases in the selected WRR arbitration scheme. For example, for 64-phase arbi-
tration, the total of the weights assigned to all the VCs in the LPVC group must be 64.
VC-based round robin arbitration is a special case of VC-based WRR in which the weights are equal for all
VCs in the LPVC group.
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PCI Express SW Controller Databook VC-Based WRR Arbitration Programming Examples
The register programming in steps 3-5 is a combination of default register value selection
Note
during hardware configuration and (optionally) update of the register values at runtime through
the DBI. Setting the VC Arbitration Select field (RW) in step 6 is a function of configuration
software.
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PCI Express SW Controller Databook Setting Up 5 VCs in the LPVC Group, 2 VCs in HPVC Group
Synopsys, Inc.
H
Advanced Information: Advanced Filtering
This appendix discusses advanced features and operation associated with “Receive Filtering” on page 94.
You should first read to familiarize yourself with basic information on the filtering and routing of received
TLPs. The following topics are discussed:
■ “Filtering Rules” on page 955
■ “Filtering Algorithm” on page 958
■ “Upstream Port Routing Overview” on page 960
■ “Request TLP Routing Rules” on page 963
■ “Processing Illegal CFG TLPs and CFG1-CFG0 Conversion in Each PCI Express Port Type” on page
966
■ For more information on advanced routing of TLPs with errors, see “Advanced Information:
Note Advanced Error Handling for Received TLPs” on page 981.
■
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PCI Express SW Controller Databook Filtering Rules
TLP Type
Downstream Port:
Address does not meet any of the following conditions:
1. MEM: Outside of the memory range AND prefetchable
memory range as determined by the corresponding Base and
Limit fields in the Type-1 header.
UR
2. I/O: Outside of the I/O range as determined by the I/O Base
and Limit fields in the Type-1 header.
3. The filter mask CX_FLT_MASK_UR_OUTSIDE_BAR bit is set,
which treats out-of-bar TLPs as supported requests and
indicates a special application requirement
1. For non-posted TLPs, this filter result also determines the status of the completion that the controller sends back to the
requester.
Synopsys, Inc.
TLP Type
Upstream Port:
Address does not meet any of the following conditions:
1. Within any configured memory BAR.
2. MEM: Inside of the memory range OR prefetchable memory
range as determined by the corresponding Base and Limit fields
in the Type-1 header. UR
3. I/O: Inside of the I/O range as determined by the I/O Base and
Limit fields in the Type-1 header.
4. The filter mask CX_FLT_MASK_UR_OUTSIDE_BAR bit is set,
which treats out-of-bar TLPs as supported requests and
indicates a special application requirement
TLP is targeted for local resources, and not for forwarding, and
CA CA CA CA
ECRC error is detected.
A complete list of the filtering checks can be referenced in the descriptions of Symbol Timer Register and
Filter Mask 1 register (SYMBOL_TIMER_FILTER_1_OFF) and Filter Mask 2 register (FILTER_MASK_2_OFF).
Completions are not filtered inside the SW RADM filter. It is assumed that the SW does not generate a
request locally.
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PCI Express SW Controller Databook Filtering Rules
Applications can dynamically program a bit in the filter mask CX_FLT_MASK_HANDLE_FLUSH bit to turn
on/off this rule. If the controller is programmed to handle the flush, it is the completer’s task to return CPL
status.
When the controller receives a four DWORD TLP with the LSB of the format field set to 1 and
Note the upper 32 bits set to 0x0, then it processes the TLP as a three DWORD TLP.
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PCI Express SW Controller Databook Filtering Algorithm
!valid_at_lut_addr ||
!func_match ||
!reqid_match ||
tag_err ||
!byte_cnt_match || FALSE
!low_addr_match
TRUE
C1 C2 C3
TRUE
Does
the completion
Is there a current outstanding
NO
Does the completion have
NO Requester ID match the YES O1 unexpected_cpl_err = 1 unexpected_cpl_err = 0
current outstanding
request for that TAG? ecrc error?
Requester ID for
that TAG?
YES NO (!byte_cnt_match ||
YES
!low_addr_match) &&
!LUT[TAG].memrd_req
||!attr_match || !tc_match
||!LUT[TAG].cfg_req && FALSE
valid_at_lut_addr = 1 valid_at_lut_addr = 0
status_crs
YES NO TRUE
C4 C5 C6
Does
bus and device
number of the completion Does the TRUE
YES YES Does the current YES
Requester ID match the current outstanding attr for
outstanding tc for that TAG
current outstanding that TAG match the
Requester ID completion attr field?
match the completion tc
field?
O2 cpl_mlf_err = 0 cpl_mlf_err = 0
for that TAG?
NO NO NO
unexpected_cpl_err ||
cpl_ecrc_err ||
cpl_mlf_err FALSE
NO NO NO O3 cpl_abort = 1 cpl_abort = 0
C7 C8 C9 Cpl_abort==1
FALSE
NO NO NO
TRUE
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BAR memory region must always be outside the memory range as determined by the
Note corresponding Base and Limit fields in the Type-1 header.
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PCI Express SW Controller Databook Upstream Port Routing Overview
Figure H-2 Default Request TLP Routing (assuming no TLPs with CA/CRS/UR error status)
controller
config CDM TRGT0 CFG0
data
LBC
TRGT1 CFG1
TRGT1 MEM/IO
C
X
Type-1 Mem
P
& IO Base L
& Limit
Checks
TRGT1 MEM
BAR Address
Check
BAR
TRGT1
SII MSG
The possible destinations of a completion TLP are TRGT1 and Discard. Completions are not filtered inside
the switch filter. This is under an assumption that the switch does not generate a request locally. If an
embedded EP is involved in a switch application, there should be some modifications based on the
requirements of your application.
For more information on switches, see “Introduction to PCIe Switches” on page 894.
Synopsys, Inc.
TRGT1 CFG1
controller
config CDM TRGT0 0
data D
LBC M
0 U CFG0
ELBI TRGT0 D X
(external M 1
application U
registers) X register address >
TRGT1 1
CONFIG_LIMIT_REG
TARGET_ABOVE_CONFIG_LIMIT_REG
TRGT0 0
D
M
U MEM
X
TRGT1 1
C
BAR Address X
Check P
BAR L
BAR# of matched BAR
MEM_FUNC0_BAR1_TARGET_MAP
MEM_FUNC0_BAR0_TARGET_MAP
TRGT1 MEM/IO
Type-1 Mem
& IO Base
& Limit
Checks
TRGT1
SII MSG
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PCI Express SW Controller Databook Request TLP Routing Rules
■ In many cases, the standard routing rules can be masked or ignored by setting the corre-
Hint sponding bit in the Symbol Timer and Filter Mask 1 register (SYMBOL_TIMER_FIL-
TER_1_OFF) and Filter Mask 2 register (FILTER_MASK_2_OFF).
■ For message routing see, “Routing of Received Messages” on page 999.
By default, when the controller detects an error1 in a received TLP, it normally performs the following:
■ Discards the TLP
■ Generates a completion (for non-posted requests) with the completion status set to CA or UR
■ Sets the status in the PCI-compatible Status register
■ Sets the status in the AER registers (when you enable AER)
■ Generates an error message (upstream port only)
Vendor Vendor
MSG MSG Other
Routing Rule MEM CFG0 CFG1 aI/O Type0 Type1 MSG
1. Excluding TLPs targeted for forwarding (and not for local resources) that have ECRC errors.
Synopsys, Inc.
Vendor Vendor
MSG MSG Other
Routing Rule MEM CFG0 CFG1 aI/O Type0 Type1 MSG
Vendor Vendor
MSG MSG Other
a
Routing Rule MRd MWr CFG I/O Type0 Type1 MSG
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PCI Express SW Controller Databook Request TLP Routing Rules
Vendor Vendor
MSG MSG Other
a
Routing Rule MRd MWr CFG I/O Type0 Type1 MSG
Synopsys, Inc.
H.5 Processing Illegal CFG TLPs and CFG1-CFG0 Conversion in Each PCI
Express Port Type
Routing IDs, requester IDs, and completer IDs are 16-bit identifiers traditionally composed of three fields:
an 8-bit bus number, a 5-bit device number, and a 3-bit function number. Configuration requests always
move downstream, and never travel across a peer-to-peer connection. An RC or SW downstream port (DSP)
never receives configuration requests.
Receive Checking
The controller responds with UR, to CfgRd0 requests with incorrect function number, it never checks the
Bus.Device numbers.
Conversion
The controller never does conversion of CFG1 to CFG0. Your application must do the conversion where
necessary.
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PCI Express SW Controller Databook SW Downstream Port (DSP)
■ CFG1 requests addressing bus numbers between secondary bus number (exclusive) and Subordinate
Bus Number (inclusive) are forwarded as CFG1 requests.
Conversion
The controller never does conversion of CFG1 to CFG0. Your application must do the conversion where
necessary.
Synopsys, Inc.
I
Advanced Information: Advanced Ordering
Information
This appendix discusses advanced features and operation of ordering. The following topics are discussed.
■ “PCIe Ordering Rules”
■ “Inbound (Receive) Order Enforcement” on page 971
■ “Outbound (Transmit) Order Enforcement” on page 973
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PCI Express SW Controller Databook PCIe Ordering Rules
CPLS CPLS
EP
RC PS
RAM PD PD
RAM
(dest) Master
PD1 PD2 CPLS1 PD3 PDn CPLS2 (source)
time=0
Producer: The master in the EP is taking data from the local source RAM and writing it into the destination RAM in the RC. This posted data is indicated as P D. The
master writes to the ‘finished’ flag in the status register after it has written the last PD.
Consumer: The CPU in the RC is polling the status register in the EP, checking if the master is finished producing the data. These polling/read requests are indicated
as NP S. The corresponding completion is indicated as CPL S.
Producer-Consumer Model: The CPLS must not pass any P D, or else the CPU starts to consume the data before it is fully produced. Therefore the EP, any
intermediate SW, and RC queues must obey this rule.
The rule does not need to be applied to P TLPs and CPLs that are not part of this Producer-Consumer sequence, for example, RC CPU CFG reads to unrelated
functions in the EP. You should set the relaxed ordering (RO) bit for these requests to ‘1'.
If there is an element in your system that is not enforcing the “CPL must not pass P” rule (for example, if the CPL receive queue in the RC is in bypass mode), you must
use an alternative method for communicating status between a producer and a consumer; use interrupts or place the data being read-from/written-to in a different
location in your PCIe system .
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a. Or be blocked by
b. Combination of requester ID and tag
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PCI Express SW Controller Databook Inbound (Receive) Order Enforcement
Strict ordering, or round robin ordering, between TLPs of different VCs is used. In strict
Note
ordering, the higher numbered VCs are given a higher priority. You can set the VC arbitration
scheme during configuration using the CX_RADM_STRICT_VC_PRIORITY parameter or by
software by writing to the VC_ORDERING_RX_Q field in the VC0_P_RX_Q_CTRL_OFF
register.
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Synopsys recommends that you select the PCIe Ordering scheme and not this legacy
Note
ordering scheme.
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PCI Express SW Controller Databook Outbound (Transmit) Order Enforcement
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J
Advanced Information: Advanced LBC and
DBI Usage
This appendix discusses advanced features and operation of the “Local Bus Controller (LBC)” on page 104.
This following topics are covered in this section:
■ “Configuration Intercept Controller (CIC) for USP” on page 976
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PCI Express SW Controller Databook Programming Examples: CDM / ELBI Register Space Access Through DBI
J.1 Programming Examples: CDM / ELBI Register Space Access Through DBI
This section discusses advanced features and operation of “Data Bus Interface (DBI) Access” on page 111.
The following topics are discussed:
■ “Access From DBI (Native) (USP)” on page 975
■ “Access From Native DBI (DSP)” on page 975
Synopsys, Inc.
RX PIPE
Application RBYP
2 1
Logic: RADM
Receive TRGT1
CII.monitor 3
CII.halt 4 CIC
CII.override 5
CPU DBI 7
CXPL PHY
CDM Core
Registers
Request flow
Completion flow
XADM 8
TX PIPE
3 CIC indicates receipt of CFG request and presents TLP header and data (CfgWr) on CII
CIC: Your application can optionally halt/stall the progress of the CFG request (example: allow time for
4
housekeeping)
5 CIC: Your application can optionally modify CfgWr payload (or the CfgRd CPL data, step 7).
7 LBC forms completion TLPs with response received from internal registers in CDM (optionally modified by CIC)
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PCI Express SW Controller Databook Configuration Intercept Controller (CIC) for USP
lbc_cii_hv
lbc_cii_hdr_poisoned
lbc_cii_hdr_type[4:0]
lbc_cii_hdr_fbe[3:0]
lbc_cii_hdr_tag[7:0]
lbc_cii_hdr_req_id[15:0]
lbc_cii_hdr_addr[11:0] VLD VLD
lbc_cii_hdr_bus_num[7:0]
lbc_cii_hdr_dev_num[4:0]
lbc_cii_hdr_func_num[(PF_WD-1):0]
SRIOV: lbc_cii_hdr_vfunc_num[(VF_WD-2):0]
SRIOV: lbc_cii_hdr_vfunc_active
lbc_cii_dv
lbc_cii_data[31:0] VLD
cii_lbc_halt
When you want to halt configuration request and do house keeping tasks first:
■ Keep cii_lbc_halt =1
■ The controller provides notification on lbc_cii_* and waits for cii_lbc_halt =0
■ Perform DBI accesses to CDM while (lbc_cii_hv =1 & cii_lbc_halt =1)
■ Set cii_lbc_halt =0
When you want to override CfgWr request or CfgWr/CfgRd completion payload data:
■ Keep cii_lbc_halt =1
■ The controller provides notification on lbc_cii_* and waits for cii_lbc_halt =0
■ Set cic_lbc_override_en =1
■ Provide override data on cic_lbc_override_data
■ Set cii_lbc_halt =0
The controller only provides a notification on the CII for error-free packets that pass all Rx
Note
filtering rules successfully.
Synopsys, Inc.
K
Advanced Information: How to Tie Off Unused
Lanes
When the link width of the PHY is smaller than the link width of the controller, you must tie off the unused
lanes of the controller’s PIPE (or RMMI) interface. This appendix describes the procedure to tie-off the
unused lanes of the controller’s PIPE (or RMMI) interface. In this appendix, connection between a four-lane
controller and one-lane PHY is used as an example to explain the procedure to tie off unused lanes.
■ This appendix only gives general guidelines, and pointers to aspects of unused lanes that
Caution you must be aware of.
■ Synopsys accepts no responsibility for any PCIe IP controller and PHY integration deci-
sions made by you as a consequence of accessing this appendix.
■ The example in this appendix is not simulated or verified by Synopsys.
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PCI Express SW Controller Databook Conventional PCIe
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Software Configuration
When there are unused lanes in a system, you must reprogram the following registers through the DBI. For
this example, where a 4-lane controller is connected to a 1-lane PHY:
■ Reprogram LINK_CAPABLE field of the PORT_LINK_CTRL_OFF register to 6h1 from 6h7.
This is used by the LTSSM in Detect.
■ Reprogram NUM_OF_LANES[8:0] field of the GEN2_CTRL_OFF register to 9h1 from 9h4.
This indicates to the LTSSM, the number of lanes to check for exiting from L2.Idle or Polling.Active.
■ Reprogram PCIE_CAP_MAX_LINK_WIDTH field of the LINK_CAPABILITIES_REG register to 6h1 from
6h4.
This enables the RC to determine the Maximum Link Width for this port.
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PCI Express SW Controller Databook Advanced Information: Advanced Error Handling for Received TLPs
L
Advanced Information: Advanced Error
This appendix discusses advanced features and operation associated with “Error Handling” on page 97.
You should first read to familiarize yourself with basic information on the filtering and routing of received
errored-TLPs. The following advanced topics are discussed in this appendix:
■ “Routing of Request TLPs with Errors” on page 982
■ “Routing of Completions with Errors” on page 986
■ “Application Error Reporting Interface” on page 990
For more information on advanced routing and filtering, see “Advanced Information: Advanced
Note Filtering and Routing of TLPs” on page 954.
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Figure L-1 Overview of Routing For TLPs with Errors in Store-and- Forward Mode
Layer 3 Checks
ECRC Check
Other TLP
Checks
Malformed
Header
Checks
Malformed
Data Checks
Unsupported
Request
Check
DLLP
Checks
1
Internally Discarded
Store-Fwd
RX TLP Buffer 0 Application I/F
1. A switch forwards all TLPs that are destined for other PCIe components except when a layer 1 or 2 DLLP check fails or the
TLP is malformed.
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PCI Express SW Controller Databook Routing of Request TLPs with Errors
a. Can be redirected to your application logic when the DEFAULT_TARGET (USP only) field in the MISC_CONTROL_1_OFF
register is ‘1’.
b. If CX_FLT_MASK_ECRC_DISCARD =1, the TLP is forwarded to your application logic. In additionradm_trgt1_ecrc_err is
asserted if ECRC_ERR_PASS_THROUGH =1. The radm_trgt1_tlp_abort signal is never asserted.
Figure L-2 Overview of Routing For TLPs with Errors in Bypass Mode
Layer 3 Checks
Other TLP
Checks
Malformed
Header radm_*_tlp_abort
Checks @ radm_*_eot or
radm_*_hv
Malformed
Data Checks
Unsupported
Request
Check
DLLP radm_*_dllp_abort
Checks @ radm_*_eot
RX TLP
1
Internally Discarded
Bypass
0 Application I/F
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a. If Layer 3 checks fail, then controller discards the request and does not assert radm_bypass_dllp_abort.
b. If CX_FLT_MASK_ECRC_DISCARD =1, then TLP is forwarded to your application logic and radm_bypass_ecrc_err is asserted
(if ECRC_ERR_PASS_THROUGH =1). TLPs with errors are generally dropped unless the CX_FLT_MASK_ECRC_DISCARD
filter rule is set, but because an ECRC error occurs at the end of the TLP, a TLP in cut-through mode with an ECRC error must
be passed through. Note that cut-through mode decays into store-and-forward mode when the queues become full; if there is
more than one TLP in the buffer when the queue is in cut-through mode, the TLPs being received are treated the same as
store-and-forward mode. Only the first TLP in the queue behaves in cut-through mode.
radm_*_tlp_abort radm_*_eota The error is non-correctable. You should not expect the TLP to be replayed.
The error is correctable. You can normallyb expect the DLLP to be replayed.
Some DLL error conditions such as a missing end delimiter (EOT) can
radm_*_dllp_abort radm_*_eot
cause your applications receive buffer to overflow. Your application must
implement some EOT timeout detect logic.
radm_*_ecrc_err radm_*_eot The error is non-correctable. You should not expect the TLP to be replayed.
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PCI Express SW Controller Databook Routing of Request TLPs with Errors
When an LCRC error occurs on an inbound request which contains an ECRC, and the
Attention controller forwards the TLP to your application (queue is in bypass or cut-through), the
radm_trgt1_dwen outputs are not accurate on the last beat (eot) of the TLP when the TLP
payload (excluding ECRC) is not a multiple of the controller datapath width.
You must discard all data from this TLP including the additional data because
radm_*_dllp_abort is active on radm_*_eot.
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Figure L-3 Overview of Routing For Completion TLPs with Errors in Store-and- Forward Mode
Layer 3 Checks
ECRC Check
Other TLP
Checks
Malformed
Header
Checks
Malformed
Data Checks
DLLP
Checks
1
Internally Discarded
Store-Fwd
RX TLP Buffer 0 Application I/F
1. A switch forwards all TLPs that are destined for other PCIe components except when a layer-1 or layer-2 DLLP check fails
or the TLP is malformed.
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PCI Express SW Controller Databook Routing of Completions with Errors
a. Endpoint only.
b. If CX_FLT_MASK_CPL_ECRC_DISCARD =1, then the TLP is forwarded to your application logic. In additionrad-
m_trgt1_ecrc_err is asserted if ECRC_ERR_PASS_THROUGH =1. radm_trgt1_tlp_abort is never asserted.
c. Completion timeout: Requester information is returned on CPL Timeout interface.
d. Poisoned: radm_trgt1_ep is asserted.
In general when the controller detects an error in a received completion, it continues to forward the
completion to your application, and asserts the *tlp_abort or *dllp_abortsignals to indicate that your
application should drop the TLP and rollback its buffer pointers. Exceptions to this are detailed in Table L-5.
Synopsys, Inc.
Figure L-4 Overview of Routing For Completion TLPs with Errors in Bypass/Cut-Through Mode
Layer 3 Checks
Other TLP
Checks
Malformed
Header radm_*_tlp_abort
Checks @ radm_*_eot or
radm_*_hv
Malformed
Data Checks
DLLP radm_*_dllp_abort
Checks @ radm_*_eot
RX TLP
1
Internally Discarded
Bypass
0 Application I/F
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PCI Express SW Controller Databook Routing of Completions with Errors
radm_*_tlp_abort radm_*_eota The error is non-correctable. You should not expect the TLP to be replayed.
The error is correctable. You can normallyb expect the DLLP to be replayed.
Some DLL error conditions such as a missing end delimiter (EOT) can
radm_*_dllp_abort radm_*_eot
cause your applications receive buffer to overflow. Your application must
implement some EOT timeout detect logic.
radm_*_ecrc_err radm_*_eot The error is non-correctable. You should not expect the TLP to be replayed.
When an LCRC error occurs on an inbound request which contains an ECRC, and the
Attention controller forwards the TLP to your application (queue is in bypass or cut-through), the
radm_trgt1_dwen outputs are not accurate on the last beat (eot) of the TLP when the TLP
payload (excluding ECRC) is not a multiple of the controller datapath width.
You must discard all data from this TLP including the additional data because
radm_*_dllp_abort is active on radm_*_eot.
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Core
Receive
Optional DLL Layer
Error Reporting detected
Interface errors Core
(app _err_* / app_hdr_* inputs ) Receive
TL Layer
To
Receive
Buffers
PCIe
Status
and AER
Registers
Error
Message
Generation
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PCI Express SW Controller Databook Application Error Reporting Interface
Core
Receive
Optional DLL Layer
Error Reporting detected
Interface errors Core
(app _err_* / app_hdr_* inputs ) Receive
TL Layer
To
Receive
Buffers
PCIe
Status
and AER
Registers
You must set the APP_RETURN_ERR_EN configuration parameter to enable the Application Error Reporting
Interface.
8: AtomicOp Egress Blocked: only valid when CX_ATOMIC_ROUTING_EN =1. AER Uncorrectable [24]
11: TLP Prefix Blocked Error Status: only valid for RC and when CX_NPRFX > 0. AER Correctable [25]
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12: ACS Violation: only valid when CX_ACS_ENABLE =1. AER Uncorrectable[21]
When you report an error on this interface at the same time (exact same clock cycle) as when
Attention the controller is reporting an error internally, then there is a potential for Header Log Overflow
to occur, as described in 6.2.4.2. “Multiple Error Handling” in the PCI Express Base
Specification, Revision 4.0, Version 1.0. The controller can only log one TLP header per
function, and in this scenario it discards the header from the controller. However, both error
bits are set in the Uncorrectable Error Status register, assuming that they are of different
types.
You can also turn off the filter rules and perform your own error checking for all TLPs. For more
information, see “Routing of Request TLPs with Errors” on page 982. This is not a recommended mode of
operation.
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PCI Express SW Controller Databook Advanced Information: Calculating Gen1 PCI Express Throughput
M
Advanced Information: Calculating Gen1 PCI
Express Throughput
This appendix defines the throughput calculation (primarily) with respect to the PCI Express controller in
Gen1 2.5 GT/s mode, and provides guidelines to enable you to meet your desired throughput by selecting
the appropriate configuration parameters from those supplied with the controller.
This appendix describes the throughput calculation, parameters that impact the calculation (such as the
maximum payload size selection), and matching-up the appropriate application interface to obtain the best
system performance from the controller. The following topics are discussed.
■ “PCI Express Bandwidth and Throughput”
■ “Effective Throughput” on page 996
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x1 250
x2 500
x4 1000
x8 2000
x16 4000
Table M-2 Throughput for Data Widths with a 125 MHz Clock
Data Path Width (Bits) Max Throughput @ 125 MHz (MB/s) Lane Width
32 250 x1
32 500 x2
64 1000 x4
128 2000 x8
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PCI Express SW Controller Databook Configuring the PCI Express Controller with Respect to Throughput
Table M-3 Throughput for Data Widths with a 250 MHz Clock
Data Path Width (Bits) Max Throughput @ 250 MHz (MB/s) Lane Width
32 1000 x4
64 2000 x8
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Figure M-1 TLP Packet (with associated Data Link Layer overhead bytes)
Table M-4 summarizes throughput calculations based on a payload size from 16 to 4K bytes.
■ A 128-byte payload size yields about 67% of the net throughput. Increasing the payload
Note size to 512 bytes increases the net throughput to 76%.
■ Increasing the payload size from 512 bytes to 4096 bytes, and using the smaller three
DWORD header, only contributes an increase of 3% in the net throughput, and the storage
requirements are more than doubled.
■ In addition, a large payload size might have an impact on performance due to re-transmis-
sion of TLPs.
■ Therefore, 256-byte and 512-byte payload sizes are the most popular choices. Most chip
sets support 128 -byte or 256-byte payload sizes, with 512 bytes gaining in popularity.
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PCI Express SW Controller Databook Effect of Link Layer Flow Control and ACK/NAK DLLPs
A breakdown of the theoretical throughput for your specific configuration is available in the coreConsultant
GUI “Report” tab.
Percent
Bytes Result Throughput
Typical One ACK plus one FC per 1.4 (256 byte payload)
1.4*280 / (1.4*280 + 2*8) 96%
Packet bytes of data => 2 DLLPs per 1.4 packets
Best One ACK plus one FC per 4096 bytes of data => 2
4116 / (4116 + 2*8) 99%
Packet DLLP per data packet
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N
Advanced Information: Advanced Routing of
Received Messages
This appendix discusses advanced features and operation associated with “Message Reception” on page
164. You should first read to familiarize yourself with basic information on the filtering and routing of
received message TLPs.
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PCI Express SW Controller Databook Routing of Received Messages
a. For the masking (of the dropping) of Vendor messages, it is not possible to differentiate between Vendor Message without
Payload (Msg) and Vendor Message with Payload (MsgD).
b. Vendor Type0 Messages are dropped with UR error reporting.
Full information of the Filter Mask Registers are in Symbol Timer and Filter Mask 1 register
(SYMBOL_TIMER_FILTER_1_OFF) and Filter Mask 2 register (FILTER_MASK_2_OFF).
Figure N-1 Received 3rd and 4th Message Header Byte Mapping at Interfaces
Byte 15 is in position [7:0]
4-DW Header ? for 4-DWORD headers
TRGT1
0 0x0
8-11
63
FLT_Q_ADDR_WIDTH
1
32 bytes 8-11
31
0
P
0 I
bytes 12-15 P
1 Core
Logic E
For 256-bit c onfigurations , this interfac e is 128-bits
wide. S ee I/O des c ription for more details .
63 bytes 8-11
32
SII.MESSAGE
(radm_msg_payload ) 31 bytes 12-15
0
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PCI Express SW Controller Databook Advanced Information: Replay Buffer Sizing
O
Advanced Information: Replay Buffer Sizing
This appendix explains how coreConsultant automatically calculates the size of the “Transmit Replay” on
page 91. The retry buffer should be large enough so that, under normal operating conditions, back-to-back
transmission of maximum sized packets (of size CX_MAX_MTU) is never throttled by a full retry buffer.
Normal operating conditions mean ACK DLLPs are received as opposed to NAK DLLPs. In determining
the optimal buffer size, one must consider the following components which are additive:
1. The remote ACK_NAK latency timer starts when the last symbol of a TLP is received. Therefore one
maximum sized packet from the local device must be stored in the replay buffer to accumulate transmit
TLP data.
2. An Ack DLLP is not scheduled by the remote device until its ACK_NAK latency timer has expired.
During the time interval between start and expiry of the ACK_NAK latency, the replay buffer must
have additional space to accumulate transmit TLP data.
3. When the ACK_NAK latency timer expires in the remote device, there is a delay to the transmission of
the Ack DLLP if the remote device has just started transmitting a TLP packet. Therefore additional
space to store a remote maximum sized packet needs to be added to the local replay buffer size to accu-
mulate transmit TLP data.
4. The L0s exit latency required by the device's receiver.
5. The delays caused by the:
a. Transmission of a TLP by the local device.
b. Processing of TLP by the remote device.
c. Transmission of a Ack DLLP by the remote device.
d. Processing of a Ack DLLP by the local device.
e. Round trip latency of Re-timer device (if present). This latency is calculated from CX_MAX_RE-
TIMER value.
The equation to derive this depth is as follows. The label in each {} represents the contribution by each factor
detailed in the previous numbered list:
depth =data_size{1} + data_size{3} + (larger of(l0s_adj{4} or
retimer_latency{5.e})+ ack_lat_limit{2} + remote_dly_factor{5.b and 5.c})/cx_nb +
cx_internal_delay{5.a and 5.d}
where:
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■ data_size{1} and data_size{3} are both the CX_MAX_MTU size expressed in units of controller
data width. For example, a 1024 byte CX_MAX_MTUfor a 128-bit controller is 1024*8/128 =64 entries.
■ l0s_adj{4}is (CX_NFTS+1)*4because there are four symbols in a fast training sequence (FTS).
■ ack_lat_limit{2} comes directly from Tables 3-7,3-8, and 3-9 of the PCI Express Base Specification,
Revision 4.0, Version 1.0.
■ cx_nb is the number of symbols processed at the PIPE interface per lane For example, the value is two
symbols (16-bit PIPE) for a Gen2 controller running at 250 MHz.
■ remote_dly_factor{5.b and 5.c} are the MAC and PHY delays (Tx and Rx) in the remote device.
To model this, Synopsys uses the PCI Express Base Specification, Revision 4.0, Version 1.0 recommenda-
tion of a constant value of 19 Symbol Times for 2.5 GT/s mode operation, 70 Symbol Times for 5.0
GT/s mode operation, and 115 Symbol Times for 8.0 GT/s and 16 GT/s mode operation.
■ cx_internal_delay{5.a and 5.d}are the MAC and PHY delays (Tx and Rx) of the local device.
It is possible that this equation gives a retry buffer depth which is too large for your requirements. For
example, referring to item {3}, this can happen if the maximum packet size that is transmitted by the
remote device is smaller than CX_MAX_MTU of the local device (the equation assumes these are the same)
OR
you choose to trade off some temporal drop in performance versus back pressure on the local transmit client
interface for the retry buffer depth.
For more information on the actual parameters used, see “Parameter Descriptions”.
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PCI Express SW Controller Databook Advanced Information: Endianness
P
Advanced Information: Endianness
PCIe transfers information as a serialized stream of bytes. At the byte level, information is transmitted and
received over the wire with the leftmost byte (byte 0 in Figure P-1) being transmitted first. However,
endianness is only relevant when considering the arrangement of bytes within (for example) a DWORD.
Reading the PCI Express Base Specification, Revision 4.0, Version 1.0, it is possible to interpret parts of the TLP
header byte ordering as big endian. For example, the most significant byte of the address field is transferred
first so that it may be used for early address decode. However, the arrangement of the payload (data) is little
endian.
Figure P-1 PCIe Express Specification Byte Ordering (Four DWORD Header)
In a similar way, the controller implements the headers1 as big endian and the datapath2 as little endian.
Figure P-2 shows the example of a 32-bit controller, where:
■ First payload byte (byte 16 in Figure P-1 or Figure P-2, and byte 12 in Figure P-3) is at location (7:0)
■ First address byte (byte 15 in Figure P-1 or Figure P-2, and byte 11 in Figure P-3) is at location (31:24)
Figure P-2 Synopsys Controller Internal Byte Ordering (Four DWORD Header)
1. Including header address and message data bytes on the following interfaces: radm_bypass_addr, radm_trgt1_addr,
client0_tlp_addr, radm_msg_payload, and ven_msg_data.
2. Including payload bytes on the following interfaces: radm_cpl_data, radm_bypass_data, radm_trgt1_data, and
client0_tlp_data.
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Figure P-3 Synopsys Controller Internal Byte Ordering (Three DWORD Header)
Therefore, you do not have to do byte reordering in your application. The controller exactly maps the
address bus to the address header field, and the data to the payload. Taking the example of
client0_tlp_addr, the bits in this address bus map directly to the address bits in the TLP header. The
third and fourth DWORDs of the header are mapped as follows:
■ 3-DWORD header
❑ Third DWORD (bytes 8-11) =client0_tlp_addr[31:0]
❑ Therefore, bits [7:0] are mapped to byte 11 which is the lowest eight bits of the TLP header address.
■ 4-DWORD header
❑ Third DWORD (bytes 8-11) =client0_tlp_addr[63:32]
❑ Fourth DWORD (bytes 12-15) =client0_tlp_addr[31:0]
❑ Therefore, bits [7:0] are mapped to byte 15 which is the lowest eight bits of the TLP header address.
This simple I/O bus bit mapping to TLP header byte mapping also applies to radm_bypass_addr,
radm_trgt1_addr, radm_msg_payload, and ven_msg_data.
Figure P-4 Transmitted 3rd and 4th Message Header Byte Mapping at Interfaces
SII.MESSAGE 31 bytes 12-15
(app _msg_*) 0
0
63 bytes 8-11
VMI
(ven_msg_data) 32
31 bytes 12-15
0
P
XALI0/1/2 Core I
Logic P
63 E
1
32 bytes 8-11
31
0
0
0x0 0
bytes 12-15
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PCI Express SW Controller Databook Advanced Information: Endianness
The optional TLP prefixes are implemented as little endian. Using the example of a controller
Note
with just one prefix, this means that client0_tlp_prfx[31:0] has byte 0 (the byte with the
FMT and Type fields) of the prefix in the lower byte position of the DWORD
client0_tlp_prfx[31:0]. That is, FMT =bits 7:5, and Type =bits 4:0
Synopsys, Inc.
Q
Introduction to PCIe Switches
PCI Express provides a high speed, low-pin count, serial, chip-to-chip interface. PCI Express is a
point-to-point interface, so switches are used for fan-out. Figures Q-1 shows a switch connecting four
endpoints to a processor and chip-set.
You can build a PCI Express switch by adding your switch core logic to the pre-verified, configurable
DesignWare digital and mixed-signal IP.
The following topics are discussed:
■ “Switch Architecture” on page 1008
■ “Digital IP” on page 1010
■ “Mixed Signal IP” on page 1011
■ “Switch Application Logic Summary” on page 1012
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PCI Express SW Controller Databook Introduction to PCIe Switches
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Figure Q-2 A PCIe Switch Chip Includes User logic and IP Blocks
The digital IP (closest to the processor) in the Figure Q-2 is the “upstream,” or “upstream facing” switch
port. The other instances (1 to 32) of digital IPs are “downstream” or “downstream facing” ports.
Each of the PCIe links shown can be of different widths. For example, the upper link can be x4 (4 lanes
wide), while the other links are x1. Each unit of width provides 2.5 Gb/second of raw throughput at Gen1
speed, 5.0 Gb/second of raw throughput at Gen2 speed, and 8.0 Bits/second of raw throughput at Gen3
speed.
The switch application logic includes:
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PCI Express SW Controller Databook Switch Architecture
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Q.2 Digital IP
The switch port digital IP as shown in Figure Q-3 implements most of the PCI Express protocol. The IP
includes the physical, link, and transaction protocol layers. The IP performs all the required character and
packet-level encoding, decoding, error checking, automatic retransmission, credit and remote buffer space
checking, packet building and power management.
When you instantiate the IP in your design, an input pin is available to configure the controller as either an
upstream or a downstream port.
Figure Q-3 PCI Express Digital (Switch controller) and Mixed Signal IP (PHY)
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PCI Express SW Controller Databook Mixed Signal IP
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PCI Express SW Controller Databook Routing, Arbitration, and Response Logic
How do I decide if a Type 1 configuration packet is directed at one of the downstream switch ports?
You can examine the bus number in the packet address field. To the host software, the downstream switch
ports appear as devices on a numbered bus. This bus number is assigned by the host software, and is
displayed on the secondary bus number signals of the upstream switch port; you can compare it to the bus
number in the configuration packet.
Note: You must use the upstream port’s secondary bus signals, and not the downstream port’s primary bus
signals, which might be temporarily “out of sync” during bus number configuration.
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You can examine the device number in the packet address field. When you build your switch design, you
assign each downstream switch port a unique device number.
How do I direct a configuration request if the bus number does not match the switch’s internal bus number?
Each of the downstream switch ports displays the range of bus numbers to be found “below” that port on
the Secondary and Subordinate Bus Number signals (see Figure Q-5). You can use this range to transmit the
configuration request through the correct downstream port.
Note: If the bus number in the configuration request matches the Secondary Bus Number, then you must
change the configuration request type from 1 to 0 before you transmit the request through the downstream
port.
Figure Q-5 Each Switch Port Displays the Downstream Bus Numbers
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PCI Express SW Controller Databook Routing, Arbitration, and Response Logic
What happens if the bus and device numbers of the configuration request do not match any of the internal ports and do
not match the range of any of the downstream ports beyond the switch?
This is a system software error. You should respond with an unsupported request status using the upstream
switch port’s Application Error Reporting signals.
Note: This “error” occurs during system initialization, when the host software checks to see how many
downstream ports are present on the switch.
How does my switch core logic “capture” bus numbers for downstream switch ports?
Whenever your switch core logic executes a configuration register write, you must also write the bus
number from the configuration request into the downstream switch port’s primary bus number register.
This is a simple transaction on the port’s DBI interface.
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PCI Express SW Controller Databook Packet Buffering
■ Advantages: Receive buffering uses the controller’s receive buffers and logic, which includes circuitry
for PCI Express ordering rules. The receive buffers also handle all PCI Express credit (buffer space)
reporting requirements, and arbitrate between packet types and virtual channels. No additional
transmit buffers are required.
The controller transmit clients arbitrate between packet sources for you.
■ Disadvantages: If you halt a packet from an input port, all other packets from that port might be
blocked. If the blocking lasts for a longer time, you might violate PCI Express protocol rules, which
require certain packets to pass others (to avoid deadlock).
Transmit Side Buffering
If you choose transmit buffering, you use packet buffers at each switch port’s transmit client. There is
generally one transmit buffer per packet source at each switch port. Each of these buffers in turn includes a
memory area for each packet type (posted, non-posted, completion).
■ Advantages: If you provide one transmit buffer per packet type per switch port, you can allow smaller
packets to pass blocked larger packets.
In the scheme shown in Figure Q-7, the digital IP performs arbitration between receive packet ports.
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■ Disadvantages: You must add buffering and buffering logic, including logic for PCI Express ordering
rules, and deletion of partially received bad packets.
Switch Core Buffering
Switch core buffering is the most complex, but most powerful packet storage scheme.
You can provide very large amounts of storage, combine on-chip and off-chip memory, and reallocate
memory freely at system startup time to handle different applications.
You can also reallocate storage during packet transfer if you are careful with PCI Express credit
management.
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PCI Express SW Controller Databook Power Management
3. A downstream port can detect an error condition, and determine (based on internal register settings)
that an error message should be transmitted upstream. A pin for each type of message (correctable,
uncorrectable, fatal) is available.
If one of the error signals is asserted to active state, the switch application logic should construct the
corresponding message TLP, and send it to the upstream port.
Synopsys, Inc.
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PCI Express SW Controller Databook Reset and Link Down
Figure Q-8 Legacy Interrupts are Combined in Your Switch core Logic
Synopsys, Inc.
Both of these types of arbitration are described in the PCI Express Base Specification, Revision 4.0, Version 1.0
along with optional and required features.
You might be able to use the built in VC and port arbitration in the switch port.
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PCI Express SW Controller Databook Advanced Switch Feature Summary
Synopsys, Inc.
The Synopsys digital IP includes the signals and registers required for hot plug support. The IP also signals
your switch core when a message is required due to a change in hot plug state.
Q.5.8 Bifurcation
You might have downstream signals on your switch chip that you would like to use in a flexible manner, for
example, a set of signals that can be either a single x8 PCIe link, or two independent x4 links. This is known
as bifurcation.
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PCI Express SW Controller Databook Non-Standard Switch Feature Summary
For more information on PCIe systems, see “Processing Illegal CFG TLPs and CFG1-CFG0
Hint Conversion in Each PCI Express Port Type” on page 966 in the “Advanced Information:
Advanced Filtering and Routing of TLPs” on page 954.
Synopsys, Inc.
R
Advanced Information: Area, Power Esti-
Synopsys provides area and power consumption figures for several example configurations1 of the
controller at the following location:
http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/5.40a/doc/PCIe_Gate_Count_ASIC.pdf
The information provided here is intended to be used only as a guideline. For more information, contact
your Synopsys representative.
Synopsys provides RAM size figures for over 500 configurations of the controller at
https://www.synopsys.com/dw/doc.php/iip/DWC_pcie/5.40a/doc/PCIe_RAM_Size_ASIC.pdf.
Synopsys recommends that you use coreConsultant to generate the RAM size report for your configuration.
1. The configurations used are the default configurations, except for the parameters that are listed in the tables.
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PCI Express SW Controller Databook Area Estimation
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Component Description
The switching power of a driving cell is the power dissipated by the charging and discharging of the
Switch Power load capacitance at the output of the cell. The total load capacitance at the output of a driving cell
is the sum of the net and gate capacitances on the driving output.
Leakage power is the power dissipated by a cell when it is not switching, that is, when it is inactive
Leakage Power
or static.
Internal power is the dynamic power dissipated within the boundary of a cell. It includes the power
dissipation due to charging or discharging of capacitances internal to the cell during switching; and
Internal Power
the power dissipation due to the momentary short circuit between the P and N transistors of a gate
while both are turned on.
Table R-2 estimates L0S power as a percentage of L0 power which is Total Power in the reports. The power
consumption in L1.1, L1.2, and L2 is approximately equal to Leakage Power; and L1 power is approximately
equal to L0s power.
Gen Mode
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PCI Express SW Controller Databook RAM Sizing
Synopsys, Inc.
S
Advanced Information: Flow Control Credit
Calculation
This appendix explains how coreConsultant automatically calculates the default buffer sizes and credits for
each TLP type from the number of lanes, the controller datapath width, the maximum PCIe payload
(CX_MAX_MTU), flow control (FC) update latencies, internal delays, and the PHY latency. For more
information on flow control, see “Flow Control” on page 176.
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PCI Express SW Controller Databook Calculation of Flow Control Latency
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S.2 Calculation of Initial Flow Control Credits and Receive Buffer Sizes
The number of credits advertised should be large enough so that under normal operating conditions,
back-to-back transmission of maximum sized packets (MTUs) is never throttled by a lack of credits. In
determining the optimal credit advertisement, one must consider the following components which are
additive:
1. The fact that the flow control latency timer starts when the last symbol of a TLP is received. Therefore
one maximum sized packet from the local device must be stored in the receive buffer to accumulate
received TLP data.
2. The fact that a flow control update DLLP is not scheduled by the local device until its flow control
latency timer has expired. During the time interval between start and expiry of the flow control latency
timer, the receive buffer must have additional space to accumulate received TLP data.
3. The delays caused by the:
a. Transmission of a TLP by remote device.
b. Processing of TLP by local device.
c. Transmission of FC update by local device.
d. Receiving FC update by remote device.
e. Round trip latency of Re-timer device (if present). This latency is calculated from CX_MAX_RE-
TIMER value.
As an example, the equations to derive posted data credits are as follows where the label in each {}
represents the contribution to each factor detailed in the above list:
depth =(calc_bytes)/(4*CX_NW)/4
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PCI Express SW Controller Databook Calculation of Initial Flow Control Credits and Receive Buffer Sizes
❑ delays in the local device between receiving the EOT and starting the flow control latency timer.
❑ delays associated from the time the flow control latency timer expires until the controller receives
the flow control packet.
■ The number of bytes calculated is rounded up to next MTU so that the device advertises at least
another full MTU worth of bytes/credits. This helps to reduce credit starvation.
4. Default Non-Posted data credits (RADM_NPQ_DCRD_VC0) should be a fraction of the Non-Posted header
credits because Non-Posted TLPs with data, that is, I/O and Configuration Write Transactions, occur
infrequently (and Atomic Ops occur slightly more frequently).
■ RADM_NPQ_DCRD_VC0 is set to be ½ RADM_NPQ_HCRD_VC0 if Atomic Ops are enabled, or ¼ RADM_N-
PQ_HCRD_VC0 otherwise.
■ Additionally enabled VCs in configurations where AtomicOps are not enabled, do not have I/O or
Configuration Write Transactions, and thus require no data credits (RADM_NPQ_DCRD_VC(1-7)).
It is possible that these equations result in a number of credits (and a resulting receive queue depth) which
is too large for your requirements, or you choose to trade off some temporal drop in performance versus
back pressure on the remote transmitter for receive buffer depth. You can always advertise more than the
default number of credits if you want to continue to offload the wire in the presence of application halting.
Taking the case of Non-Posted header credits (RADM_NPQ_HCRD_VC(0-7)), a conservative approach is used
for the default calculation, and the total amount that can be transmitted during a Flow Control update
window is selected to ensure saturation of the datapath. This however does not take into consideration the
number of Non-Posted requests the application can handle; which is dependent on impacting factors such
as the application response time, the link latency, the credit return latency, and the number of available
Tags.
A more efficient approach can be taken by connecting the amount of Non-Posted header credits to the
number of outstanding requests supported, along with an additional margin to account for packets
currently in flight.
A general rule of thumb is:
■ If the Target Completion Lookup Table (TRGT_CPL_LUT_EN) is full, the controller must have returned
the Non-Posted credits associated with the transactions in the LUT already.
❑ Therefore, in a full LUT situation there are already CX_REMOTE_MAX_TAG Non-Posted requests in
the queues waiting to be offloaded.
■ If the LUT is not full it implies that Non-Posted requests are being completed at a rate sufficient to
prevent LUT full.
❑ In this case it is only necessary to ensure that there are sufficient credits in flight to prevent starva-
tion.
■ Ideally the LUT should run close to full.
❑ Advertising approximately the same number of credits as concurrent requests that can be handled
is a good balance, allowing a few extra credits to account for delays across the link.
■ Applications which do not use the Target Completion Lookup Table are likely to have a similar
concept to CX_REMOTE_MAX_TAG.
For example, it can be shown that for the case of 256-byte requests with a 1us round trip time, 32 tags are
sufficient to keep an X4 link saturated. Adding additional tags or credits only increases RAM sizes and area
without providing any further performance boost.
Synopsys, Inc.
T
Advanced Information: Serialization Queue
The TLP Serialization Queue resides between Layer3 and the Virtual Channel TLP Receive Queues as
shown in Figure 1. Figure T-1.
The TLP Serialization Queue is used to consume one or more TLPs from the Transaction Layer (Layer3) in a
single cycle and to send TLPs in series to the application (RTRGT1, RBYP), through the VC TLP Receive
Queues. The number of TLPs to process in a single cycle depends on the TLP length. For example, for a
stream of TLPs with 3 DWORDs of header the maximum number of TLPs to process in a single cycle is 4.
Depending on the mix of TLP length's the amount of data stored in the Serialization Queue can increase or
decrease over time. For more information on how the data stored in the queue increases and decrease
depending on the TLP length, see “Data Rates” on page 1036.
Over time TLPs can accumulate and cause the Serialization Queue to overflow, unless its size is set to the
VC TLP Receive Queue size. However, allowing the Serialization Queue to buffer up this amount of data
has no benefit in terms of TLP throughput at the application interfaces (RTRGT1/RBYP). The application
can offload only one TLP at a time and therefore in the presence of short TLPs cannot keep pace with the
maximum throughput on the wire.
To minimize the RAM footprint, without any performance penalty, you can significantly reduce the
Serialization Queue size and maintain throughput at the application interface.
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PCI Express SW Controller Databook Advanced Information: Serialization Queue Almost Full Threshold
To prevent the reduced Serialization Queue from overflowing the controller takes advantage of the Data
Link layers ACK/NACK protocol. At a certain threshold or water mark, named ALMOST_FULL, the
Serialization Queue masks incoming TLPs and schedules the transmission of a NACK. The NACK sequence
number indicates the last good TLP received. The remote link partner purges all acknowledged TLPs from
its replay buffer and replays all other TLPs stored in the buffer in order. While the incoming TLPs are being
masked the Serialization Queue continues to send TLPs to the VC TLP Receive Queues. Note: halting the
RTRGT1 interface has no impact on the transfer of these TLPs. When the amount of data stored in the queue
drops below ALMOST_FULL the Serialization Queue unmasks incoming TLPs enabling the replayed TLPs to
be stored in the queue.
The following topics are discussed:
■ “Serialization Queue Almost Full Threshold”
■ “Serialization Queue Input and Output Data Rates” on page 1043
Synopsys, Inc.
Figure T-2 Serialization Queue Accumulation Rate = 3.33 QDWORDs/cycle (No Prefix)
DW15 d i h
h i h
h d i
h h i
i h d QDW7H/D D
i h h QDW6H/D H H D QDW3D
d i h QDW5H/D D QDW2D
i h h QDW0H/D H H
d i h time
Notes:
h i h (a) Lower Case lettering implies DWORDs (DW)
h d i (b) Upper case lettering implies QDWORDs (QDW)
DW0 h h i (c) p/P = Prefix, h/H = Header, d/D=Data, i=Idle
(d) CX_NW expresses the width of the data path in DWORDs
time
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PCI Express SW Controller Databook Data Rates
i QDW5P/H/D D QDW2D
h i time
p i Notes:
i d (a) Lower Case lettering implies DWORDs (DW)
(b) Upper case lettering implies QDWORDs (QDW)
DW0 i h (c) p/P = Prefix, h/H = Header, d/D=Data, i=Idle
(d) CX_NW expresses the width of the data path in DWORDs
time
Figure T-4 and Figure T-5 describe how streams of TLPs, with and without prefixes, dissipate in the
Serialization Queue. The fastest TLP dissipation rate without prefixes occurs for a stream TLPs consisting of
3 Header DWORDs and 16 Data DWORDs. The input data rate is 3.81 QDWORDs/cycle; the output data
rate is 5 QDWORDs/cycle. The fastest TLP dissipation rate with TLP Prefixes occurs for a TLP stream of 7
Prefix DWORDs, 3 Header DWORDs and 16 Data DWORDs. The input data rate is 4 QDWORDs/cycle; the
output data rate is 7 QDWORDs/cycle.
Figure T-4 Serialization Queue Dissipation Rate = 1.19 QDWORDs/cycle (No Prefix)
DW15 d d
d d
d d
d d
d d QDW7H/D
d d QDW6H/D D D QDW3D D D
i d d QDW5H/D D QDW2D D D
i d d QDW4H/D H D Serialization QDW1D D D
/CX_NW Layer 3
d h d QDW3H/D Queue QDW0D D D
d h d QDW2H/D D D QDWH H H
d h d QDW1H/D time
d i d QDW0H/D D D H
d i d time
Notes:
d d h
(a) Lower Case lettering implies DWORDs (DW)
d d h (b) Upper case lettering implies QDWORDs (QDW)
DW0 d d h (c) p/P = Prefix, h/H = Header, d/D=Data, i=Idle
time (d) CX_NW expresses the width of the data path in DWORDs
Synopsys, Inc.
p d p Notes:
p d p (a) Lower Case lettering implies DWORDs (DW)
(b) Upper case lettering implies QDWORDs (QDW)
DW0 p d p (c) p/P = Prefix, h/H = Header, d/D=Data, i=Idle
(d) CX_NW expresses the width of the data path in DWORDs
time
The QDWORD input and output rate is determined by the following equations:
Input Rate (QDWORDs per cycle)
= (Number of TLP per cycle)*(Number of QDWORDs per TLP)
= NW/(PDW + HDW + DDW + TLP Overhead)*(PQDW + HQDW + DQDW)
Output Rate (QDWORDs per cycle)
= (Tota Number of TLP QWORDs)/(Number of cycles to offload the TLP data QDWORDs)
= (PQDW + HQDW + DQDW)/ ROUNDUP(DQDW/(NW/4))
Where:
■ NW is the width of the data path in DWORDs
■ PDW is the TLP prefix length in DWORDs
■ HDW is the TLP header length in DWORDs
■ DDW is the TLP data length in DWORDs
■ PQDW is the TLP prefix length in QDWORDs
■ HQDW is the TLP header length in QDWORDs
■ DQDW is the TLP data length in QDWORDs, and
■ TLP Overhead is the TLP overhead stripped by the lower layers (Layer1 tokens and Layer2 LCRC).
For example, a TLP stream of 1 prefix DWORD, 3 header DWORDs, and 1 data DWORD results in the
following input and output QDWORD rates:
Input Rate
= 16/(1+3+1+2)*(1+1+1)
= 6.86 QDWORDs/cycle
Output Rate
= (1+1+1)/1
= 3 QDWORDs/cycle
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PCI Express SW Controller Databook NACK Request to Replayed TLP Latency
A TLP stream consisting of 3 header DWORDs and 16 data DWORDs results in the following input and
output QDWORD rates:
Input Rate
= 16/(3+16+2)*(1+4)
= 3.81 QDWORDs/cycle
Output Rate
= (1+4)/1
= 5 QDWORDs/cycle
The increase or decrease in the number of QDWORDs stored in the queue can be expressed by the following
equations:
Constant = (PDW + HDW + DDW + 2)% CX_NW =0
Increase = (PDW + HDW + DDW + 2)% CX_NW >0 and <=(PDW + HDW + 2)
Decrease = (PDW + HDW + DDW + 2)% CX_NW >(PDW + HDW + 2) or (DDW =0)
For a table of input and output data rates for various TLP lengths see “Serialization Queue Input and
Output Data Rates” on page 1043.
The ALMOST_FULL threshold is reached for any given stream of TLPs such that over time the input rate is
greater than the output rate.
Note: These formulae are based on a stream of fixed length TLPs.
Synopsys, Inc.
Figure T-6 NACK Request to First Replayed TLP at Input to Serialization Queue
F G H I J
TLP’s
Layer 2
DLLP’s
E D C B A
Remote Device
Local Device
CX_PHY_RX_DELAY_PHY CX_RETIMER_LATENCY / 2 CX_PHY_TX_DELAY_PHY
The round trip time from transmission of the Nack to the first replayed TLP at the input to the serialization queue depends on the
following latencies:
A Local Layer2 NACK request to PIPE latency: This is known by design and is set to 9 core clock cycles.
B
The Local PHY TX latency (CX_PHY_TX_DELAY_PHY): This is the worst case delay from the PIPE interface to the TX PHY serial
pins, expressed in PIPE clock cycles. It is specified by your PHY provider and passed at build time through coreConsultant.
C
Local to Remote Link Retimer latency (CX_RETIMER_LATENCY/2): This is the worst case delay through the Retimers, expressed
in symbols times. Its value defaults to the maximum delay specified in the PCIe Base Specification.
D
Remote PHY Rx latency: This is the worst case delay from the Rx PHY serial pins to the PIPE interface, expressed in PIPE clock
cycles. It is matched to the Local PHY Rx latency, CX_PHY_RX_DELAY_PHY.
E
Remote NACK DLLP to replay request latency: This is extrapolated from the Local NACK DLLP to replay request latency. It is known
by design and has a value of 10 core clock cycles.
F
Remote replay request to PIPE latency: This is extrapolated from the Local Remote replay request to PIPE latency. It is known by
design and has a maximum value of 28 core clock cycles.
G
Remote PHY TX latency: This is the worst case delay from the PIPE interface to the TX PHY serial pins, expressed in PIPE clock cycles.
It is matched to the Local PHY TX latency, CX_PHY_TX_DELAY_PHY.
H
Remote to Local Link Retimer latency (CX_RETIMER_LATENCY/2): This is the worst case delay through the Retimers, expressed
in symbols times. Its value defaults to the maximum delay specified in the PCIe Base Specification.
I
Local PHY Rx latency (CX_PHY_RX_DELAY_PHY): This is the worst case delay from the Rx PHY serial pins to the PIPE interface,
expressed in PIPE clock cycles. It is specified by your PHY provider and passed at build time through coreConsultant.
J Local PIPE to Serialization Queue latency: This is known by design and has maximum value of 16 core clock cycles.
In summary, the latency from the transmission of the NACK, to the first replayed TLP at the input, to the
serialization queue in controller clock cycles is:
NACK_TO_RPLYD_TLP =
(2 *(Core Clock to PIPE Clock Frequency Ratio
*(CX_PHY_TX_DELAY_PHY + CX_PHY_RX_DELAY_PHY)))
+(Symbol Time * CX_RETIMER_LATENCY/Core Clock Period) + 68
Note: 2s (16-bit) and 4s (32-bit) Controller-PHY Dynamic Frequency combinations are supported. For 2s the
Controller Clock to PIPE Clock frequency ratio is 1:2, for 4s it is 1:1.
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PCI Express SW Controller Databook Almost Full Threshold Calculation
0 5 1400 22400
1 to 4 6 1680 26880
4 to 7 7 1960 31360
You can adjust the auto-calculated almost full threshold through the coreConsultant "Receive Serialization
Queue" configuration page as shown in Figure T-7.
Synopsys, Inc.
ALMOST_FULL or Serialization Queue size is presented as a percentage of the available TLP buffer space,
that is, as a percentage of the configured TLP Receive Queue size. The auto-calculated value is the optimal
threshold to ensure TLPs are sent to the application without impacting performance, and is the default
value. To increase ALMOST_FULL, you must tick the "Enable Receive Serialization Size Configuration" tick
box prior to modifying its value.
Note: If the wire data rate is greater than the Serialization Queue output data rate then increasing the almost
full threshold only serves to extend the time before the NACK is sent. If the wire data rate is not sustained
over time, then increasing the almost full threshold can reduce the transmission frequency of the NACKs.
Refer to “Serialization Queue Input and Output Data Rates” on page 1043 for the number of fixed length
TLPs required to reach ALMOST_FULL, for a given NACK request to replayed TLP latency.
Note: To prevent the controller from sending overflow prevention related NACKs you must set
ALMOST_FULL to 100% of the configured TLP Receive Queue size.
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PCI Express SW Controller Databook Serialization Queue Input and Output Data Rates
Figure T-8 Serialization Queue Input and Output Data Rates (No Prefixes)
Synopsys, Inc.
Figure T-9 shows the input and output QDWORD data rates for streams of TLPs of various DWORD
lengths, with 1 prefix supported.
Figure T-9 Serialization Queue Input and Output Data Rates (1 Prefix)
Figure T-10 shows the input and output QDWORD data rates for streams of TLPs of various DWORD
lengths, with 7 prefixes supported.
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PCI Express SW Controller Databook Serialization Queue Input and Output Data Rates
Figure T-10 Serialization Queue Input and Output Data Rates (7 Prefixes)
Synopsys, Inc.
U
Internal Parameter Descriptions
Provides a description of the internal parameters that might be indirectly referenced in expressions in the
Signals, Parameters, or Registers chapters. These parameters are not visible in the coreConsultant GUI and
most of them are derived automatically from visible parameters.You must not set any of these parameters
directly.
Some expressions might refer to TCL functions or procedures (sometimes identified as function_of) that
coreConsultant uses to make calculations. The exact formula used by these TCL functions is not provided in
this chapter. However, when you configure the core in coreConsultant, all TCL functions and parameters
are evaluated completely; and the resulting values are displayed where appropriate in the coreConsultant
GUI reports.
Table U-1 Internal Parameters
ACS_CTRL_VEC_WD_0 ((CX_ACS_P2P_EGRESS_CTRL_0) *
((CX_ACS_EGRESS_CTRL_SIZE_0 == 0) ? 256 :
CX_ACS_EGRESS_CTRL_SIZE_0))
ADDR_TRANSLATION_SUPPORT_EN (CX_INTERNAL_ATU_ENABLE)
AHB_ENABLED AHB_POPULATED
AMBA_DECOMPOSER_DEF_DEPTH_FACTOR 2
AMBA_POPULATED AMBA_INTERFACE ! =0
APP_PAR_ERR_OUT_EN (CX_RAS_EN)
ATOMIC_ROUTING_SUP CX_ATOMIC_ROUTING_EN
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PCI Express SW Controller Databook Internal Parameter Descriptions
ATS_RX_ENABLE_VALUE ATS_RX_ENABLE
ATTR_WD FLT_Q_ATTR_WIDTH
ATU_IN_REGIONS CX_ATU_NUM_INBOUND_REGIONS
ATU_IN_SINGLE_TRGT_ADDR_ENABLE CX_INTERNAL_ATU_ENABLE
BUSNUM_WD CX_BUSNUM_WD
CC_DM 2
CC_DMA_ENABLE_VALUE CC_DMA_ENABLE
CC_DTIM_DATA_WD 160
CC_DTIM_NUM_BYTES_PER_BEAT (CC_DTIM_DATA_WD/8)
CC_DTIM_RAW_INTF_WD CC_DTIM_DATA_WD +
CC_DTIM_NUM_BYTES_PER_BEAT + 1
CC_EP 0
CC_GENERIC_PHY 8
CC_HP_MASTER 0
Synopsys, Inc.
CC_IN64 {(AMBA_INTERFACE ! = 0) ?
(MASTER_BUS_ADDR_WIDTH > 32) :
(FLT_Q_ADDR_WIDTH > 32)}
CCIX_ESM_SUPPORT_VALUE CX_CCIX_ESM_SUPPORT
CCIX_HDR_PROT_WD CX_RASDP_CCIX_HDR_PROT_WD
CCIX_HDR_WD CX_RASDP_CCIX_HDR_WD
CCIX_INTERFACE_ENABLE_VALUE CX_CCIX_INTERFACE_ENABLE
CCIX_VC_RESOURCE (CX_NVC-1)
CC_LEGACY_DMA_MAP 1
CC_LINK_TIMEOUT_PERIOD_DEFAULT 50
CC_MAX_MSTR_TAGS_AHB 1
CC_MSTR_NW (MASTER_BUS_DATA_WIDTH/32)
CC_MSTR_RD_REQ_SIZE (CC_MSTR_BURST_LEN*MASTER_BUS_DATA_WIDTH/8
)
CC_RC 1
CC_SW 3
C_G1_SYNC_SI ( ! CM_HSGEAR1_SPEED) ? 0 :
(MPHY_C_HSG1_SYNC_LENGTH > 31) ?
2^(MPHY_C_HSG1_SYNC_LENGTH-32) :
MPHY_C_HSG1_SYNC_LENGTH
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PCI Express SW Controller Databook Internal Parameter Descriptions
C_G2_SYNC_SI ( ! CM_HSGEAR2_SPEED) ? 0 :
(MPHY_C_HSG2_SYNC_LENGTH > 31) ?
2^(MPHY_C_HSG2_SYNC_LENGTH-32) :
MPHY_C_HSG2_SYNC_LENGTH
C_G3_SYNC_SI ( ! CM_HSGEAR3_SPEED) ? 0 :
(MPHY_C_HSG3_SYNC_LENGTH > 31) ?
2^(MPHY_C_HSG3_SYNC_LENGTH-32) :
MPHY_C_HSG3_SYNC_LENGTH
CLIENT1_POPULATED 1
CM_HSGEAR1_SPEED 1
CM_MAX_SYNC_TIME_D4 CM_MAX_SYNC_TIME/4
Synopsys, Inc.
CM_PHY_TX_DELAY_MAC 5
CX_10BITS_TAG_REQ_VALUE (CX_10BITS_TAG_REQ == 1) ? 1: 0
CX_10BITS_TAG_VALUE (CX_10BITS_TAG == 1) ? 1: 0
CX_ADM_ADAPTOR_ENABLE (CX_PL_MODE == 1)
CX_ADM_ADAPTOR_RADM_PIPE_STAGES 16
CX_ARI_FWD_ENABLE CX_ARI_FWD_CAP
CX_ATU_CTRL_EN CX_INTERNAL_ATU_ENABLE
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PCI Express SW Controller Databook Internal Parameter Descriptions
CX_ATU_INCR_RGN_SIZE ((AMBA_INTERFACE ! = 0) ?
((CX_ATU_MAX_REGION_SIZE>0) &&
AMBA_INTERFACE ! = 1 &&
SLAVE_BUS_ADDR_WIDTH>32):CX_ATU_MAX_REGION
_SIZE>0)
CX_ATU_SLOC_CBUF ATU_IN_SINGLE_TRGT_ADDR_ENABLE
CX_BUSNUM_WD (MULTI_DEVICE_AND_BUS_PER_FUNC_EN == 0) ? 8 :
(CX_NFUNC*8)
CX_CCIX_RX_WD (CX_CCIX_INTERFACE_ENABLE) ? 1 : 0
Synopsys, Inc.
CX_CXPL_EN (CX_PL_MODE == 0)
CX_CXS_CNTLCHKWIDTH ((CX_CXS_RX_DATACHECK == 2) ? 8 :
((CX_CXS_RX_DATACHECK == 1) ? 1 :
((CX_CXS_TX_DATACHECK == 2) ? 8 : 1)))
CX_CXS_DATACHKWIDTH (CX_CXS_DATAFLITWIDTH/8)
CX_CXS_RX_BUFF_DATAW (CXS_FLIT_LOWER_DATA_WIDTH ?
(CX_CXS_CCIXDATAWIDTH +
CX_CXS_RX_CCIXCNTLWIDTH + (CX_RAS_EN ?
(CX_CXS_CCIXDATAWIDTH/8 + 8) : 0)) :
(CX_CXS_DATAFLITWIDTH + CX_CXS_CNTLWIDTH +
(CX_RAS_EN ? (CX_CXS_DATACHKWIDTH + 8) : 0)) )
CX_CXS_RX_BUFF_DEPTH (CX_CXS_RX_BUFF_FIFO_DEPTH +
CX_CXS_RX_MEM_DEPTH_ADJ)
CX_CXS_RX_BUFF_FIFO_DEPTH (CX_CXS_RX_CREDITS + 1 +
((CX_CXS_RX_CONTINUOUSDATA &&
(CXS_FLIT_EQUALS_DATA_WIDTH ==1)) ? 0 :
(4096/(CXS_FLIT_LOWER_DATA_WIDTH ?
CX_CXS_CCIXDATAWIDTH :
CX_CXS_DATAFLITWIDTH))))
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PCI Express SW Controller Databook Internal Parameter Descriptions
CX_CXS_TX_BUFF_DATAW (CXS_FLIT_LOWER_DATA_WIDTH ?
(CX_CXS_CCIXDATAWIDTH +
CX_CXS_TX_CCIXCNTLWIDTH + (CX_RAS_EN ?
(CX_CXS_CCIXDATAWIDTH/8 + 8) : 0)) :
(CX_CXS_DATAFLITWIDTH + CX_CXS_CNTLWIDTH +
(CX_RAS_EN ? (CX_CXS_DATACHKWIDTH + 8) : 0)) )
CX_CXS_TX_BUFF_DEPTH (4*(4096/(CXS_FLIT_LOWER_DATA_WIDTH ?
CX_CXS_CCIXDATAWIDTH :
CX_CXS_DATAFLITWIDTH)))
CX_CXS_TX_CCIXCNTLWIDTH ((CXS_FLIT_EQUALS_DATA_WIDTH ?
CX_CXS_MAXPKTPERFLIT : 1)*(3 + ([function_of:
CX_CXS_CCIXDATAWIDTH]-5) + ([pcie_cc_logbase2
CX_CXS_CCIXDATAWIDTH]-7)))
CX_DEFAULT_EQ_BYPASS_HIGHEST_RATE_SUPPORT CX_SKIP_LOWER_RATE_EQ
CX_DEFAULT_GEN5_TX_MOD_CMPL_PATTERN_FOR_L CX_DEFAULT_GEN5_EQ_FOR_LOOPBACK
OOPBACK
CX_DEFAULT_LANE_UNDER_TEST 0
CX_DEFAULT_MOD_TS_PCIE_SUPPORT 0
CX_DEFAULT_NO_EQ_NEEDED_SUPPORT CX_NO_EQ_NEEDED
CX_DEVNUM_WD (MULTI_DEVICE_AND_BUS_PER_FUNC_EN == 0) ? 5 :
(CX_NFUNC*5)
CX_DIAG_STATUS_BUS_WD (CX_RADM_DIAG_STATUS_BUS_WD +
CX_XADM_DIAG_STATUS_BUS_WD +
CX_CDM_DIAG_STATUS_BUS_WD +
CX_PM_DIAG_STATUS_BUS_WD +
CX_CXPL_DIAG_STATUS_BUS_WD)
CX_DMA_CHANNEL_GROUP_ENABLE 0
CX_DMA_PF_ENABLE 0
CX_DMA_RD_LLQ 1
CX_DMA_WR_LLQ 1
CX_DPC_ENABLE 0
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CX_DPC_ENABLE_VALUE CX_DPC_ENABLE
CX_DPC_RP_PIO_EXTNS 0
CX_DPC_RP_PIO_EXTNS_VALUE CX_DPC_RP_PIO_EXTNS
CX_ECC_PIPE_EN 0
CX_EXTDPC_ENABLE 0
CX_FLR_ENABLE_VALUE CX_FLR_ENABLE
CX_GEN2_MODE (CX_MAX_PCIE_SPEED<2) ? 2 :
(CX_MAC_SMODE_GEN1 ==1) &&
(CX_MAC_SMODE_GEN2 ==2) ? 1 :
(CX_MAC_SMODE_GEN1 ==2) &&
(CX_MAC_SMODE_GEN2 ==4) ? 1 :
(CX_MAC_SMODE_GEN1 ==1) &&
(CX_MAC_SMODE_GEN2 ==1) ? 0 :
(CX_MAC_SMODE_GEN1 ==2) &&
(CX_MAC_SMODE_GEN2 ==2) ? 0 :
(CX_MAC_SMODE_GEN1 ==4) &&
(CX_MAC_SMODE_GEN2 ==4) ? 0 : 2
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PCI Express SW Controller Databook Internal Parameter Descriptions
CX_GEN3_MODE (CX_MAX_PCIE_SPEED<3) ? 2 :
(CX_MAC_SMODE_GEN2 ==2) &&
(CX_MAC_SMODE_GEN3 ==4) ? 1 :
(CX_MAC_SMODE_GEN2 ==4) &&
(CX_MAC_SMODE_GEN3 ==8) ? 1 :
(CX_MAC_SMODE_GEN2 ==4) &&
(CX_MAC_SMODE_GEN3 ==16) ? 4 :
(CX_MAC_SMODE_GEN2 ==1) &&
(CX_MAC_SMODE_GEN3 ==1) ? 0 :
(CX_MAC_SMODE_GEN2 ==1) &&
(CX_MAC_SMODE_GEN3 ==4) ? 4 :
(CX_MAC_SMODE_GEN2 ==2) &&
(CX_MAC_SMODE_GEN3 ==2) ? 0 :
(CX_MAC_SMODE_GEN2 ==4) &&
(CX_MAC_SMODE_GEN3 ==4) ? 0 : 2
CX_GEN3_SPEED_VALUE CX_GEN3_SPEED
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CX_GEN4_MODE (CX_MAX_PCIE_SPEED<4) ? 2 :
(CX_MAC_SMODE_GEN3 ==2) &&
(CX_MAC_SMODE_GEN4 ==4) ? 1 :
(CX_MAC_SMODE_GEN3 ==4) &&
(CX_MAC_SMODE_GEN4 ==8) ? 1 :
(CX_MAC_SMODE_GEN3 ==8) &&
(CX_MAC_SMODE_GEN4 ==16) ? 1 :
(CX_MAC_SMODE_GEN3 ==1) &&
(CX_MAC_SMODE_GEN4 ==1) ? 0 :
(CX_MAC_SMODE_GEN3 ==2) &&
(CX_MAC_SMODE_GEN4 ==2) ? 0 :
(CX_MAC_SMODE_GEN3 ==4) &&
(CX_MAC_SMODE_GEN4 ==4) ? 0 :
(CX_MAC_SMODE_GEN3 ==8) &&
(CX_MAC_SMODE_GEN4 ==8) ? 0 :
(CX_MAC_SMODE_GEN3 ==16) &&
(CX_MAC_SMODE_GEN4 ==16) ? 0 : 2
CX_GEN4_SPEC07_PLCAP (CX_GEN4_SPEC07)
CX_GEN4_SPEED_VALUE CX_GEN4_SPEED
CX_IDO_ENABLE_VALUE CX_IDO_ENABLE
CX_INTERNAL_ERR_REPORTING CX_INTERNAL_ERR_REPORTING_EN
CX_INTERNAL_ERR_REPORTING_EN 1
CX_L1_PG_ENABLE CX_L12_PG_EN
CX_LANE_REVERSE (CX_S_MPCIE_MODE) ? 0 : 1
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PCI Express SW Controller Databook Internal Parameter Descriptions
CX_LN_VALUE CX_LN_ENABLE
CX_LTR_M_ENABLE_VALUE CX_LTR_M_ENABLE
CX_LTSSM_EMU_WD 6+5
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CX_MAX_DELAY_LAYER2_LAYER3 16
CX_MSI_CTRL_EN CX_MSI_CTRL_ENABLE
CX_NB (CX_NB_GEN5)
CX_NB_GEN1 (CX_MAC_SMODE_GEN1)
CX_NL_M_1 CX_NL-1
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CX_NUM_DMA_RD_CHAN CC_NUM_DMA_RD_CHAN
CX_NUM_DMA_WR_CHAN CC_NUM_DMA_WR_CHAN
CX_NVFUNC_NUM_WD {CX_NVFUNC_WD}
CX_NW_GTR_4_VALUE CX_NW_GTR_4
CX_P2P_ENABLE_VALUE CX_P2P_ENABLE
CX_PCIE_BRIDGE CX_PCIE_BRIDGE_ENABLE
CX_PCIE_BRIDGE_ENABLE 0
CX_PHY_GEN2_DP (CX_PHY_2S_DYN_PACE == 1)
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PCI Express SW Controller Databook Internal Parameter Descriptions
CX_PHY_GEN2_MODE (CX_MAX_PCIE_SPEED<2) ? 2 :
(CX_PHY_SMODE_GEN1 ==1) &&
(CX_PHY_SMODE_GEN2 ==2) ? 1 :
(CX_PHY_SMODE_GEN1 ==2) &&
(CX_PHY_SMODE_GEN2 ==4) ? 1 :
(CX_PHY_SMODE_GEN1 ==1) &&
(CX_PHY_SMODE_GEN2 ==1) ? 0 :
(CX_PHY_SMODE_GEN1 ==2) &&
(CX_PHY_SMODE_GEN2 ==2) ? 0 :
(CX_PHY_SMODE_GEN1 ==4) &&
(CX_PHY_SMODE_GEN2 ==4) ? 0 :
(CX_PHY_SMODE_GEN1 ==202) &&
(CX_PHY_SMODE_GEN2 ==202) ? 0 :
(CX_PHY_SMODE_GEN1 ==102) &&
(CX_PHY_SMODE_GEN2 ==1) ? 1 : 2
CX_PHY_GEN3_MODE (CX_MAX_PCIE_SPEED<3) ? 2 :
(CX_PHY_SMODE_GEN2 ==1) &&
(CX_PHY_SMODE_GEN3 ==2) ? 1 :
(CX_PHY_SMODE_GEN2 ==2) &&
(CX_PHY_SMODE_GEN3 ==4) ? 1 :
(CX_PHY_SMODE_GEN2 ==4) &&
(CX_PHY_SMODE_GEN3 ==8) ? 1 :
(CX_PHY_SMODE_GEN2 ==1) &&
(CX_PHY_SMODE_GEN3 ==4) ? 4 :
(CX_PHY_SMODE_GEN2 ==4) &&
(CX_PHY_SMODE_GEN3 ==16) ? 4 :
(CX_PHY_SMODE_GEN2 ==1) &&
(CX_PHY_SMODE_GEN3 ==1) ? 0 :
(CX_PHY_SMODE_GEN2 ==2) &&
(CX_PHY_SMODE_GEN3 ==2) ? 0 :
(CX_PHY_SMODE_GEN2 ==4) &&
(CX_PHY_SMODE_GEN3 ==4) ? 0 :
(CX_PHY_SMODE_GEN2 ==202) &&
(CX_PHY_SMODE_GEN3 ==2) ? 3 : 2
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CX_PHY_GEN4_MODE (CX_MAX_PCIE_SPEED<4) ? 2 :
(CX_PHY_SMODE_GEN3 < CX_PHY_SMODE_GEN4) ? 1
: (CX_PHY_SMODE_GEN3 ==1) &&
(CX_PHY_SMODE_GEN4 ==2) ? 1 :
(CX_PHY_SMODE_GEN3 ==2) &&
(CX_PHY_SMODE_GEN4 ==4) ? 1 :
(CX_PHY_SMODE_GEN3 ==4) &&
(CX_PHY_SMODE_GEN4 ==8) ? 1 :
(CX_PHY_SMODE_GEN3 ==1) &&
(CX_PHY_SMODE_GEN4 ==1) ? 0 :
(CX_PHY_SMODE_GEN3 ==2) &&
(CX_PHY_SMODE_GEN4 ==2) ? 0 :
(CX_PHY_SMODE_GEN3 ==4) &&
(CX_PHY_SMODE_GEN4 ==4) ? 0 :
(CX_PHY_SMODE_GEN3 ==8) &&
(CX_PHY_SMODE_GEN4 ==8) ? 0 :
(CX_PHY_SMODE_GEN3 ==16) &&
(CX_PHY_SMODE_GEN4 ==16) ? 0 : 2
CX_PHY_INTERFACE (CX_GEN3_SPEED_VALUE == 1)
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PCI Express SW Controller Databook Internal Parameter Descriptions
CX_PHY_NUM_MACROS [function]
CX_PHY_PDOWN_WD 4
CX_PHY_RX_DELAY_MAC 4
CX_PHY_TX_DELAY_MAC 4
CX_PHY_TXEI_WD (CX_PIPE51_SUPPORT) ? 4 : 1
CX_PHY_VIEWPORT_DATA 16
CX_PIPE44_SUPPORT (CX_PIPE_VER>=2)
CX_PIPE51_LOW_PIN_COUNT (CX_PIPE51_SUPPORT)
CX_PIPE51_SUPPORT (CX_PIPE_VER>=3)
CX_PIPE_LOOPBACK_EN (CX_S_MPCIE_MODE ? 0 : 1)
CX_PL16G_ENABLE (CX_GEN4_SPEC07_PLCAP)
CX_PL32G_ENABLE (CX_GEN5_SPEED)
CX_PL_MODE 0
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CX_PL_REG_DISABLE 0
CX_PTM_REQUESTER_VALUE CX_PTM_REQUESTER_CAPABLE
CX_PTM_RESPONDER_VALUE CX_PTM_RESPONDER_CAPABLE
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PCI Express SW Controller Databook Internal Parameter Descriptions
CX_RADM_FORMQ_NQW CX_RADM_SERQ_NUM_RAMS
CX_RADM_FORMQ_QDW_RAM_PW CX_RADM_SERQ_QDW_RAM_PW
CX_RADM_ORDERING_RULES_VC0 CX_RADM_ORDERING_RULES
CX_RADM_ORDERING_RULES_VC1 CX_RADM_ORDERING_RULES
Synopsys, Inc.
CX_RADM_RXQ_NUM_QDWS CX_RADM_HDRQ_DEPTH +
CX_RADM_DATAQ_DEPTH*(CX_NW/4)
CX_RADM_SBUF_DATAQ_CTRLQ_WD RADM_EOT_WD
CX_RADM_SBUF_DATAQ_DATA_WD (32*CX_NW)/CX_NDQ
CX_RADM_SBUF_DATAQ_RAM_WD
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PCI Express SW Controller Databook Internal Parameter Descriptions
CX_RADM_SERQ_AF_NUM_QDWS CX_RADM_SERQ_AF_NUM_QDWS_PER_RAM*CX_RAD
M_SERQ_NUM_RAMS
CX_RADM_SERQ_AF_NUM_QDWS_PER_RAM {[function_of: [
CX_RADM_RXQ_NUM_QDWS_PER_SERQ_RAM *
CX_RADM_SERQ_TO_RXQ_SIZE_RATIO] 100]}
CX_RADM_SERQ_QDW_RAM_DP {CX_RADM_SERQ_AF_NUM_QDWS_PER_RAM +
CX_RADM_SERQ_MARGIN_NUM_QDWS_PER_RAM}
CX_RAM_PROTECTION_MODE 0
CX_RAS_DES_EC_G0_BW 4
CX_RAS_DES_EC_G1_BW 8
CX_RAS_DES_EC_G2_BW 8
CX_RAS_DES_EC_G3_BW 8
CX_RAS_DES_EC_G4_BW 4
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CX_RAS_DES_EC_G5_BW 32
CX_RAS_DES_EC_G6_BW 32
CX_RAS_DES_EC_G7_BW 32
CX_RAS_DES_EC_INFO_CMN_BW 171
CX_RAS_DES_EC_INFO_PLN_BW 13
CX_RAS_DES_EC_RAM_DATA_WIDTH 64
CX_RAS_DES_SD_INFO_CMN_BW 79
CX_RAS_DES_SD_INFO_PLN_BW 205
CX_RAS_DES_SD_INFO_PVC_BW 240
CX_RAS_DES_TBA_INFO_CMN_BW 7
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PCI Express SW Controller Databook Internal Parameter Descriptions
CX_RASDP_CCIX_HDR_WD 128
CX_RAS_EXT_IF 0
Synopsys, Inc.
CX_RBARS_INCLUDED {[ PortCfg::is_rbar_enabled ]}
CX_RP_PIO_IMPSPEC 0
CX_RTLH_SIMPLE_EXTRACT CX_RTLH_SIMPLE_EXTRACT_ENABLE
CX_RXMARGIN_RATE_MODE_ENABLE 0
CXSCNTLCHKWIDTH CX_CXS_CNTLCHKWIDTH
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PCI Express SW Controller Databook Internal Parameter Descriptions
CXSCNTLWIDTH CX_CXS_CNTLWIDTH
CXSDATACHKWIDTH CX_CXS_DATACHKWIDTH
CXSDATAFLITWIDTH CX_CXS_DATAFLITWIDTH
CXS_FLIT_EQUALS_DATA_WIDTH (CX_CXS_DATAFLITWIDTH
==CX_CXS_CCIXDATAWIDTH)
CXS_FLIT_LOWER_DATA_WIDTH (CX_CXS_DATAFLITWIDTH<CX_CXS_CCIXDATAWIDTH)
CX_SKEW_MAC_IMPLE_CCIX20G_CORECLK 2
CX_SKEW_MAC_IMPLE_CCIX25G_CORECLK 2
CX_SKEW_MAC_IMPLE_GEN3_CORECLK 2
CX_SKEW_MAC_IMPLE_GEN4_CORECLK 2
CX_SKEW_MAC_IMPLE_GEN5_CORECLK 2
CX_SKEW_PIPEIF_CCIX20G_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_CCIX20G_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)
CX_SKEW_PIPEIF_CCIX25G_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_CCIX25G_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)
CX_SKEW_PIPEIF_GEN1_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_GEN1_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)
CX_SKEW_PIPEIF_GEN2_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_GEN2_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)
Synopsys, Inc.
CX_SKEW_PIPEIF_GEN3_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_GEN3_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)
CX_SKEW_PIPEIF_GEN4_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_GEN4_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)
CX_SKEW_PIPEIF_GEN5_CORECLK (CX_DESKEW_DEPTH_CPCIE -
CX_SKEW_MAC_IMPLE_GEN5_CORECLK -
CX_SKEW_MAC_MARGIN_CORECLK)
CX_SRIOV_ENABLE_VALUE CX_SRIOV_ENABLE
CXS_RX_BUFF_ADDRW CX_CXS_RX_BUFF_ADDRW
CXS_RX_BUFF_DATAW CX_CXS_RX_BUFF_DATAW
CXSRXREPWIDTH CX_CXS_RX_REPLICATION
CXS_TX_BUFF_ADDRW CX_CXS_TX_BUFF_ADDRW
CXS_TX_BUFF_DATAW CX_CXS_TX_BUFF_DATAW
CXSTXREPWIDTH CX_CXS_TX_REPLICATION
CX_TLP_PREFIX_ENABLE (CX_NPRFX == 0) ? 0 : 1
CX_TLP_PREFIX_ENABLE_VALUE CX_TLP_PREFIX_ENABLE
CX_TPH_ENABLE_VALUE CX_TPH_ENABLE
CX_VF_RBARS_INCLUDED {[ PortCfg::is_vfrbar_enabled ]}
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PCI Express SW Controller Databook Internal Parameter Descriptions
DATA_PAR_WD TRGT_DATA_PROT_WD
DCRD_WD SCALED_FC_SUPPORTED ? 16 : 12
DEFAULT_ACK_FREQUENCY 8'h0
DEFAULT_DO_DESKEW_FOR_SRIS CX_SRIS_SUPPORT
DEFAULT_DSP_16G_RX_PRESET_HINT1 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT10 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT11 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT12 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT13 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT14 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT15 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT2 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT3 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT4 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT5 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
Synopsys, Inc.
DEFAULT_DSP_16G_RX_PRESET_HINT6 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT7 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT8 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_RX_PRESET_HINT9 (DEFAULT_DSP_16G_RX_PRESET_HINT0)
DEFAULT_DSP_16G_TX_PRESET1 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET10 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET11 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET12 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET13 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET14 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET15 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET2 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET3 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET4 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET5 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET6 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET7 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET8 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_16G_TX_PRESET9 (DEFAULT_DSP_16G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET1 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET10 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET11 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET12 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET13 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET14 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET15 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET2 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET3 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET4 (DEFAULT_DSP_32G_TX_PRESET0)
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PCI Express SW Controller Databook Internal Parameter Descriptions
DEFAULT_DSP_32G_TX_PRESET5 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET6 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET7 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET8 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_32G_TX_PRESET9 (DEFAULT_DSP_32G_TX_PRESET0)
DEFAULT_DSP_RX_PRESET_HINT1 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT10 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT11 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT12 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT13 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT14 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT15 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT2 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT3 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT4 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT5 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT6 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT7 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT8 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_RX_PRESET_HINT9 (DEFAULT_DSP_RX_PRESET_HINT0)
DEFAULT_DSP_TX_PRESET1 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET10 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET11 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET12 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET13 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET14 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET15 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET2 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET3 (DEFAULT_DSP_TX_PRESET0)
Synopsys, Inc.
DEFAULT_DSP_TX_PRESET4 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET5 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET6 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET7 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET8 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_DSP_TX_PRESET9 (DEFAULT_DSP_TX_PRESET0)
DEFAULT_ESM_DSP_TX_PRESET_20G1 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G10 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G11 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G12 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G13 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G14 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G15 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G2 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G3 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G4 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G5 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G6 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G7 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G8 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_20G9 (DEFAULT_ESM_DSP_TX_PRESET_20G0)
DEFAULT_ESM_DSP_TX_PRESET_25G1 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G10 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G11 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G12 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G13 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G14 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G15 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G2 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
Synopsys, Inc.
1076 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions
DEFAULT_ESM_DSP_TX_PRESET_25G3 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G4 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G5 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G6 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G7 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G8 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_DSP_TX_PRESET_25G9 (DEFAULT_ESM_DSP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_20G1 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G10 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G11 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G12 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G13 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G14 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G15 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G2 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G3 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G4 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G5 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G6 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G7 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G8 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_20G9 (DEFAULT_ESM_USP_TX_PRESET_20G0)
DEFAULT_ESM_USP_TX_PRESET_25G1 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G10 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G11 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G12 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G13 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G14 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G15 (DEFAULT_ESM_USP_TX_PRESET_25G0)
Synopsys, Inc.
DEFAULT_ESM_USP_TX_PRESET_25G2 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G3 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G4 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G5 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G6 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G7 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G8 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_ESM_USP_TX_PRESET_25G9 (DEFAULT_ESM_USP_TX_PRESET_25G0)
DEFAULT_EXT_TAG_FIELD_SUPPORTED_0 (CX_MAX_TAG>31) ? 1 : 0
DEFAULT_FAST_LINK_SCALING_FACTOR 0
DEFAULT_GEN2_TXSWING 0
DEFAULT_GEN3_AUTONOMOUS_EQ_REQ_DISABLE 0
DEFAULT_GEN3_EQ_EVAL_2MS_DISABLE 1
DEFAULT_GEN3_LOWER_RATE_EQ_REDO_ENABLE CX_GEN3_SPEED
DEFAULT_GEN3_REQ_SEND_CONSECUTIVE_EIEOS_F 1
OR_PSET_MAP
DEFAULT_GEN3_RXEQ_PH01_EN 0
DEFAULT_GEN3_ZRXDC_NONCOMPL 1
DEFAULT_GEN4_USP_SEND_8GT_EQ_TS2_DISABLE 1
DEFAULT_LANE_SKEW_OFF_26 CX_PIPE_HYBRID_MODE
DEFAULT_PHANTOM_FUNC_SUPPORTED_0 2'h0
DEFAULT_RXMARGIN_RATE_MODE CX_RXMARGIN_RATE_MODE_ENABLE
DEFAULT_RX_SERIALIZATION_Q_ALMOST_FULL_THR CX_RADM_SERQ_AF_NUM_QDWS
ESHOLD
DEFAULT_SURPRISE_DOWN_RPT_CAP SURPRISE_LINK_DOWN_SUPPORTED
DEFAULT_USP_16G_RX_PRESET_HINT1 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT10 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT11 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT12 (DEFAULT_USP_16G_RX_PRESET_HINT0)
Synopsys, Inc.
1078 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions
DEFAULT_USP_16G_RX_PRESET_HINT13 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT14 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT15 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT2 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT3 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT4 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT5 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT6 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT7 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT8 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_RX_PRESET_HINT9 (DEFAULT_USP_16G_RX_PRESET_HINT0)
DEFAULT_USP_16G_TX_PRESET1 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET10 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET11 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET12 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET13 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET14 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET15 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET2 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET3 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET4 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET5 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET6 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET7 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET8 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_16G_TX_PRESET9 (DEFAULT_USP_16G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET1 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET10 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET11 (DEFAULT_USP_32G_TX_PRESET0)
Synopsys, Inc.
DEFAULT_USP_32G_TX_PRESET12 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET13 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET14 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET15 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET2 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET3 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET4 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET5 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET6 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET7 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET8 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_32G_TX_PRESET9 (DEFAULT_USP_32G_TX_PRESET0)
DEFAULT_USP_RX_PRESET_HINT1 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT10 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT11 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT12 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT13 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT14 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT15 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT2 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT3 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT4 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT5 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT6 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT7 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT8 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_RX_PRESET_HINT9 (DEFAULT_USP_RX_PRESET_HINT0)
DEFAULT_USP_TX_PRESET1 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET10 (DEFAULT_USP_TX_PRESET0)
Synopsys, Inc.
1080 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions
DEFAULT_USP_TX_PRESET11 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET12 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET13 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET14 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET15 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET2 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET3 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET4 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET5 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET6 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET7 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET8 (DEFAULT_USP_TX_PRESET0)
DEFAULT_USP_TX_PRESET9 (DEFAULT_USP_TX_PRESET0)
DEVNUM_WD CX_DEVNUM_WD
DIRFEEDBACK_WD 6
DL_FEATURE_SUPPORTED DL_FEATURE_EN
DPC_CAP_INT_MSG_NUM 5'h0
DTIM_ATS_SID_LWR_WD DC_DTIM_ATS_SID_LWR_WD
DTIM_DATA_WD CC_DTIM_DATA_WD
DTIM_INTF_PROT_WD CC_DTIM_INTF_PROT_WD
DTIM_NUM_BYTES_PER_BEAT CC_DTIM_NUM_BYTES_PER_BEAT
DUAL_CMPCIE 2
DW (CC_DEVICE_TYPE ==CC_EP) ?
(RADM_PARBITS_OUT_VALUE ? (32*NW) +
DATA_PAR_WD : (32*NW) ) : (32*NW)
Synopsys, Inc.
ERR_BUS_WD 13 + CX_DPC_ENABLE_VALUE
EXT_VF_TPH_ENABLE EXT_VF_TPH_ENABLE_VALUE
FLT_Q_ATTR_WIDTH CX_IDO_ENABLE ? 3 : 2
FLT_Q_AT_WIDTH ATS_RX_ENABLE ? 2 : 0
FLT_Q_BCM_WIDTH 1
FLT_Q_BYTE_CNT_WIDTH 12
FLT_Q_CMPLTR_ID_WIDTH 16
FLT_Q_CPL_LAST_WIDTH 1
FLT_Q_CPL_LOWER_ADDR_WIDTH 7
FLT_Q_CPL_STATUS_WIDTH 3
FLT_Q_DESTINATION_WIDTH 2
FLT_Q_DW_LENGTH_WIDTH 10
FLT_Q_EP_WIDTH 1
FLT_Q_FMT_WIDTH 2
FLT_Q_FRSTDW_BE_WIDTH 4
FLT_Q_HDR_RSVD_DW0_WIDTH CX_RX_HEADER_RSVD_ENABLE*8
FLT_Q_HDR_RSVD_DW2_WIDTH CX_RX_HEADER_RSVD_ENABLE
Synopsys, Inc.
1082 SolvNet Synopsys, Inc. 5.40a
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PCI Express SW Controller Databook Internal Parameter Descriptions
FLT_Q_IO_REQ_IN_RANGE_WIDTH 1
FLT_Q_LN_WIDTH CX_LN_ENABLE ? 1 : 0
FLT_Q_LSTDW_BE_WIDTH 4
FLT_Q_REQID_WIDTH 16
FLT_Q_SATA_WIDTH SATA_CAP_ENABLE ? 1 : 0
FLT_Q_TAG_WIDTH CX_TAG_SIZE
FLT_Q_TC_WIDTH 3
FLT_Q_TD_WIDTH 1
FLT_Q_TH_WIDTH CX_TPH_ENABLE ? 1 : 0
FLT_Q_TYPE_WIDTH 5
FOMFEEDBACK_WD 8
FREQ_125 2
FREQ_250 1
FREQ_500 0
FREQ_62_5 3
FULL_SWING 0
G1_PREPARE_SI ( ! CM_HSGEAR1_SPEED) ? 0 :
MPHY_HSG1_PREPARE_LENGTH
G2_PREPARE_SI ( ! CM_HSGEAR2_SPEED) ? 0 :
MPHY_HSG2_PREPARE_LENGTH*2
G3_PREPARE_SI ( ! CM_HSGEAR3_SPEED) ? 0 :
MPHY_HSG3_PREPARE_LENGTH*4
GEN2_DF 0
Synopsys, Inc.
GEN2_DISABLED 2
GEN2_DW 1
GEN3_DF 0
GEN3_DISABLED 2
GEN3_DP 3
GEN3_DW 1
GEN4_DF 0
GEN4_DISABLED 2
GEN4_DW 1
HCRD_WD SCALED_FC_SUPPORTED ? 12 : 8
INT_NVF CX_INTERNAL_NVFUNC
LBC_EXT_AW CX_LBC_EXT_AW
LTSSM_EMU_IN_WD CX_LTSSM_EMU_WD
LTSSM_EMU_OUT_WD CX_LTSSM_EMU_WD
MASTER_POPULATED (AMBA_POPULATED)
MSI_PVM_EN_VALUE MSI_PVM_EN
Synopsys, Inc.
1084 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions
NC_G1_SYNC_SI ( ! CM_HSGEAR1_SPEED) ? 0 :
(MPHY_NC_HSG1_SYNC_LENGTH > 31) ?
2^(MPHY_NC_HSG1_SYNC_LENGTH-32) :
MPHY_NC_HSG1_SYNC_LENGTH
NC_G2_SYNC_SI ( ! CM_HSGEAR2_SPEED) ? 0 :
(MPHY_NC_HSG2_SYNC_LENGTH > 31) ?
2^(MPHY_NC_HSG2_SYNC_LENGTH-32) :
MPHY_NC_HSG2_SYNC_LENGTH
NC_G3_SYNC_SI ( ! CM_HSGEAR3_SPEED) ? 0 :
(MPHY_NC_HSG3_SYNC_LENGTH > 31) ?
2^(MPHY_NC_HSG3_SYNC_LENGTH-32) :
MPHY_NC_HSG3_SYNC_LENGTH
NDQ CX_NDQ
NF CX_NFUNC
NHQ CX_NHQ
NL CX_NL
NQW CX_RADM_FORMQ_NQW
NVC CX_NVC
NVF CX_NVFUNC
NW CX_NW
NW_PRFX CX_NPRFX
ORIG_DATA_WD PHY_NB * 8
PCIE_ATS_INV_REQ_ITAG_WD DC_PCIE_ATS_INV_REQ_ITAG_WD
PCLK_RATE_WD (CX_CCIX_ESM_SUPPORT) ? 4 : 3
PDWN_WIDTH CX_PHY_PDOWN_WD
PF_WD CX_NFUNC_WD
Synopsys, Inc.
PHY_NB CX_PHY_NB
PHY_RXSB_WD CX_PHY_RXSB_WD
PHY_RXSH_WD CX_PHY_RXSH_WD
PHY_TXEI_WD CX_PHY_TXEI_WD
PHY_VPT_DATA CX_PHY_VIEWPORT_DATA
PHY_VPT_NUM CX_PHY_NUM_MACROS
PIPE_INTERFACE 1
PM_MST_WD 5
PM_SLV_WD 5
PRFX_PAR_WD CX_PRFX_PAR_WD
PRFX_W_PAR CX_TLP_PREFIX_ENABLE_VALUE ?
FLT_Q_PRFX_WIDTH : 32
P_R_WD PCLK_RATE_WD
RADM_DEPTH_DECOUPLE_VC0 0
RADM_DLLP_ABORT_WD CUT_THROUGH_INVOLVED
RADM_ECRC_ERR_WD ECRC_ERR_PASS_THROUGH
RADM_EOT_WD 1
RADM_PARBITS_OUT 0
RADM_PARBITS_OUT_VALUE RADM_PARBITS_OUT
Synopsys, Inc.
1086 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions
RADM_PQ_D_ADDRBITS CX_RADM_PQ_D_ADDRBITS
RADM_PQ_DWD RADM_DATAQ_WD/CX_NDQ
RADM_PQ_H_ADDRBITS CX_RADM_PQ_H_ADDRBITS
RADM_PQ_H_DATABITS CX_RADM_PQ_H_DATABITS
RADM_PQ_H_DATABITS_O CX_RADM_PQ_H_DATABITS_OUT
RADM_Q_DATABITS CX_RADM_Q_DATABITS
RADM_Q_DATABITS_O CX_RADM_Q_DATABITS_OUT
RADM_Q_D_CTRLBITS CX_RADM_Q_D_CTRLBITS
RADM_Q_H_CTRLBITS CX_RADM_Q_H_CTRLBITS
RADM_RFC_OUT_WD CX_ADM_RFC_WD
RADM_SEG_BUF_MIN_DPT 3
RADM_TLP_ABORT_WD 1
RADM_VFINDEX_REGOUT (VFINDEX_CALC_REGOUT)
RAM_PW CX_RADM_FORMQ_QDW_RAM_PW
RAM_WD CX_RADM_FORMQ_QDW_RAM_WD
RAS_DEFAULT_NULLIFY_EN 1
Synopsys, Inc.
RASDES_EC_INFO_CM CX_RAS_DES_EC_INFO_CMN_BW
RASDES_EC_INFO_PL CX_RAS_DES_EC_INFO_PLN_BW
RASDES_EC_RAM_ADDR_WIDTH CX_RAS_DES_EC_RAM_ADDR_WIDTH
RASDES_EC_RAM_DATA_WIDTH CX_RAS_DES_EC_RAM_DATA_WIDTH
RASDES_SD_INFO_CM CX_RAS_DES_SD_INFO_CMN_BW
RASDES_SD_INFO_PL CX_RAS_DES_SD_INFO_PLN_BW
RASDES_SD_INFO_PV CX_RAS_DES_SD_INFO_PVC_BW
RASDES_TBA_INFO_CM CX_RAS_DES_TBA_INFO_CMN_BW
RASDES_TBA_RAM_ADDR_WIDTH CX_RAS_DES_TBA_RAM_ADDR_WIDTH
RASDES_TBA_RAM_DATA_WIDTH CX_RAS_DES_TBA_RAM_DATA_WIDTH
RASDP_BYPASS_HDR_PROT_WD CX_RASDP_BYPASS_HDR_PROT_WD
RASDP_DATAQ_ERR_SYND_WD CX_RADM_SBUF_DATAQ_PROT_WD
RASDP_FORMQ_ERR_SYND_WD CX_RASDP_FORMQ_ERR_SYND_WD
RASDP_HDRQ_ERR_SYND_WD CX_RASDP_HDRQ_ERR_SYND_WD
RASDP_RBUF_ERR_SYND_WD RBUF_PROT_WD
RASDP_SOTBUF_ERR_SYND_WD CX_RAS_SOTBUF_PROT_WD
RASDP_TRGT1_HDR_PROT_WD CX_RASDP_TRGT1_HDR_PROT_WD
RAS_PCIE_HDR_PROT_WD CX_RAS_PCIE_HDR_PROT_WD
RATE_WIDTH CX_PHY_RATE_WD
RIO_POPULATED 0
RTLH_RAMD_IN_WD CX_ADM_TLH_WD
RX_PSET_WD 3
Synopsys, Inc.
1088 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions
SATA_CAP_ENABLE 1'b0
SCALED_FC_SUPPORTED FC_SCALE_EN
S_CFG_COMPLETE 6'h0B
S_CFG_IDLE 6'h0C
S_CFG_LANENUM_ACEPT 6'h0A
S_CFG_LINKWD_ACEPT 6'h08
S_CFG_LINKWD_START 6'h07
S_DETECT_ACT 6'h01
S_DETECT_QUIET 6'h00
S_DETECT_WAIT 6'h06
S_DISABLED 6'h19
S_DISABLED_ENTRY 6'h17
S_DISABLED_IDLE 6'h18
SERDES_DATA_WD PHY_NB * 10
S_HOT_RESET 6'h1F
S_HOT_RESET_ENTRY 6'h1E
SINGLE_CPCIE 0
SINGLE_MPCIE 1
S_L0 6'h11
S_L0S 6'h12
S_L123_SEND_EIDLE 6'h13
S_L1_EXIT 6'h2C
S_L1_IDLE 6'h14
S_L2_IDLE 6'h15
S_L2_WAKE 6'h16
SLAVE_POPULATED (AMBA_POPULATED)
S_LPBK_ACTIVE 6'h1B
Synopsys, Inc.
S_LPBK_ENTRY 6'h1A
S_LPBK_EXIT 6'h1C
S_LPBK_EXIT_TIMEOUT 6'h1D
SNPS_RSVDPARAM_15 0
SNPS_RSVDPARAM_17 0
SNPS_RSVDPARAM_21 0
SNPS_RSVDPARAM_22 (CX_GEN4_SPEC07_RM)
SNPS_RSVDPARAM_25 0
SNPS_RSVDPARAM_26 0
SNPS_RSVDPARAM_26_VALUE SNPS_RSVDPARAM_26
SNPS_RSVDPARAM_28 CX_PIPE_MSGBUS_SUPPORT ||
CX_PIPE_LEGACY_MSGBUS_SUPPORT
SNPS_RSVDPARAM_29 0
SNPS_RSVDPARAM_31 0
SNPS_RSVDPARAM_32 0
SNPS_RSVDPARAM_33 0
SNPS_RSVDPARAM_35 0
SNPS_RSVDPARAM_4 CX_DMA_PF_ENABLE
SNPS_RSVDPARAM_9 0
Synopsys, Inc.
1090 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions
SOTBUF_PW SOTBUF_L2DEPTH
SOTBUF_WD SOTBUF_WIDTH
SPEED_DISABLED 2
SPEED_DW 1
S_POLL_ACTIVE 6'h02
S_POLL_COMPLIANCE 6'h03
S_POLL_CONFIG 6'h04
S_PRE_DETECT_QUIET 6'h05
S_RCVRY_EQ0 6'h20
S_RCVRY_EQ1 6'h21
S_RCVRY_EQ2 6'h22
S_RCVRY_EQ3 6'h23
S_RCVRY_IDLE 6'h10
S_RCVRY_LOCK 6'h0D
S_RCVRY_RCVRCFG 6'h0F
S_RCVRY_SPEED 6'h0E
TRGT1_POPULATE 1
Synopsys, Inc.
TX_COEF_WD 18
TX_CRSR_WD 6
TX_DEEMPH_WD CX_PHY_TXDEEMPH_WD
TX_FS_WD 6
TX_PSET_WD 4
V7_INTERFACE 2
VF_AER_EN VF_AER_ENABLE
VF_PASID_ENABLE 0
VF_TPH_ENABLE VF_TPH_ENABLE_VALUE
Synopsys, Inc.
1092 SolvNet Synopsys, Inc. 5.40a
DesignWare.com March 2019
PCI Express SW Controller Databook Internal Parameter Descriptions
WIDTH_WIDTH CX_PHY_WIDTH_WD
XADM_RFC_IN_WD CX_ADM_RFC_WD
XADM_XTLH_OUT_WD CX_ADM_TLH_WD
Synopsys, Inc.