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CA EC208 Assignment1 Feb 2024

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62 views2 pages

CA EC208 Assignment1 Feb 2024

Uploaded by

apolloop6t9
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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COMPUTER ARCHITECTURE (EC208)

ASSIGNMENT 1

Max. Marks: 20 Submission Deadline: March 01, 2024

1. Design an arithmetic circuit with one selection variable S and two n-bit data inputs A
and B. The circuit generates the following four arithmetic operations in conjunction
with the input carry Cin. Draw the logic diagram for the first two stages.
S Cin=0 Cin=1
0 D =A + B (add) D =A + 1 (increment)
1 D =A - 1 (decrement) D = A + 𝐵̅ + 1 (subtract)
[3](CO1, CO5)

2. The operations to be performed with a flip-flop F (not used in the basic computer) are
specified by the following register transfer statements:
xT3: F  1 ; Set F to 1
yT1: F 0 ; Clear F to 0
zT2: F 𝐹̅ ; Complement F
wT5: F G; Transfer value of G to F
Otherwise, the content of F must not change. Draw the logic diagram showing the
connections of the gates that form the control functions and the inputs of flip-flop F.
Use a JK flip-flop and minimize the number of gates. [3](CO1, CO5)

3. An output program resides in memory starting from address 2300. It is executed after
the computer recognizes an interrupt when FGO becomes a 1 (while lEN = 1).
a. What instruction must be placed at address 1?
b. What must be the last two instructions of the output program? [2](CO1)

4. The content of PC in the basic computer is 3AF (all numbers are in hexadecimal). The
content of AC is 7EC3. The content of memory at address 3AF is 932E. The content of
memory at address 32E is 09AC. The content of memory at address 9AC is 8B9F.
a. What is the instruction that will be fetched and executed next?
b. Show the binary operation that will be performed in the AC when the instruction is
executed.
c. Give the contents of registers PC, AR, DR, AC, and IR in hexadecimal and the
values of E, I, and the sequence counter SC in binary at the end of the instruction
cycle. [3](CO1)

5. Propose a hardwired control unit (block diagram) consisting of IR, two decoders, a
sequence counter, and logic gates. Also draw a timing diagram assuming that sequence
counter is cleared to 0 at time T3 if decoder signal D2 is active.
D2T3: SC ← 0
[3](CO5)
6. An instruction is stored at location 300 with its address field at location 301. The
address field has the value 400. A processor register R1 contains the number 200.
Evaluate the effective address if the addressing mode of the instruction is: (CO1, CO5)
a. Immediate
b. Relative
c. Register indirect
d. Index with R1 as the index register [2](CO1)

7. A computer responds to an interrupt request signal by pushing onto the stack the
contents of PC and the current PSW (Program Status Word). It then reads a new PSW
from memory from a location given by an interrupt address symbolized by IAD. The
first address of the service program is taken from memory from at location IAD + 1.
a. List the sequence of microoperations for the interrupt cycle.
b. List the sequence of microoperations for the return from interrupt instruction
[4](CO1)

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