Electronic Devices and Circuits

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 Metal Oxide Semiconductor Field
Effect Transistors (MOSFET)
• Three terminal device
• Source, Drain, Gate
• Basic Operation:
• Voltage between two terminals controls the flow of current in the third terminal
• Applications:
• Amplification, Digital Logic, Memory
• Smaller in size
• Easy to manufacture
• Less power consumption
• MOSFET technology allows the placement of billions of transistor on a single IC
• As compared to BJT, it is more widely used in electronic circuits
• We will study enhancement type MOSFET
• Two types
• N-channel or NMOS
• P-channel or PMOS

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N-Channel Enhancement MOSFET
Physical Structure

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Microelectronic Circuits, Sixth Sedra/Smith Copyright © 2010 by
Edition Oxford University Press, Inc.
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 Operation with Zero Gate Voltage
• With zero voltage applied to
gate, two back-to-back
diodes exist in series
between drain and source.
• “They” prevent current
conduction from drain to
source when a voltage vDS is
applied.
– yielding very high
resistance (1012ohms)
 Figure 5.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the
substrate beneath the gate.

Microelectronic Circuits, Sixth Sedra/Smith Copyright © 2010 by

Edition Oxford University Press, Inc.
 Creating a Channel for
Current Flow
• Q: What happens if (1) source
and drain are grounded and (2)
positive voltage is applied to
gate? Refer to figure to right.
– step #1: vGS is applied to the
gate terminal, causing a
positive build up of positive
charge along metal electrode.
– step #2: This “build up”
causes free holes to be
repelled from region of p-
type substrate under gate.
Figure : The enhancement-type NMOS transistor
with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
Oxford University Publishing
Microelectronic Circuits by Adel S. beneath the gate
Sedra and Kenneth C. Smith
Q: What happens if (1) source and drain are grounded and (2) positive voltage
is applied to gate? Refer to figure to right.

• step #3: This “migration”

results in the uncovering of
negative bound charges,
originally neutralized by the
free holes
• step #4: The positive gate
voltage also attracts
electrons from the n+
source and drain regions
into the channel.
Figure : The enhancement-type NMOS transistor
with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
Oxford University Publishing
Microelectronic Circuits by Adel S. beneath the gate
Sedra and Kenneth C. Smith
 this induced channel is
also
Q: What happens if (1) source and drain are grounded and (2) knownvoltage
positive as an
is applied to gate? Refer to figure to right. inversion layer

• step #5: Once a sufficient

number of “these”
electrons accumulate, an n-
region is created…
– …connecting the source
and drain regions
• step #6: This provides path
for current flow between D
and S.

Figure: The enhancement-type NMOS transistor

with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
Oxford University Publishing
Microelectronic Circuits by Adel S. beneath the gate
Sedra and Kenneth C. Smith
 Threshold Voltage
• Represented by 𝑉𝑉𝑡𝑡
• Data sheet parameter
• minimum value of vGS required to form a
conducting channel between drain and source
• Vtn is used for n-channel MOSFET, Vtp is used
for p-channel

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 Overdrive Voltage (𝑉𝑉𝑜𝑜𝑜𝑜 )
• The excess of 𝑣𝑣𝐺𝐺𝐺𝐺 over 𝑉𝑉𝑡𝑡 is called overdrive
voltage
• 𝑉𝑉𝑜𝑜𝑜𝑜 = 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑡𝑡
• Also called effective voltage

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 Applying 𝑉𝑉𝐷𝐷𝐷𝐷 in the presence of 𝑉𝑉𝐺𝐺𝑆𝑆
• If 𝑉𝑉𝐺𝐺𝑆𝑆 < 𝑉𝑉𝑡𝑡 ,
• No current would flow, cut off
• If 𝑉𝑉𝐺𝐺𝑆𝑆 > 𝑉𝑉𝑡𝑡
• 𝑉𝑉𝐷𝐷𝐷𝐷 is small, less than 50mV
• 𝑉𝑉𝐷𝐷𝑆𝑆 > 50𝑚𝑚𝑚𝑚 but less than 𝑉𝑉𝑜𝑜𝑜𝑜
• 𝑉𝑉𝐷𝐷𝑆𝑆 > 𝑉𝑉𝑜𝑜𝑜𝑜

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 MOS Capacitance
• when positive vGS is applied, an electric field develops between the gate
electrode and induced n-channel – the conductivity of this channel is affected
by the strength of field
– SiO2 layer acts as dielectric
• oxide capacitance (Cox) – is the capacitance of the parallel plate capacitor per
unit gate area (F/m2)

𝜀𝜀𝑜𝑜𝑜𝑜 is permittivity of SiO2 =3.45𝐄𝐄−11 𝐹𝐹/𝑚𝑚

𝑡𝑡𝑜𝑜𝑜𝑜 is thickness of SiO2 layer
𝜀𝜀𝑜𝑜𝑜𝑜
• 𝐶𝐶𝑜𝑜𝑜𝑜 = in 𝐹𝐹/𝑚𝑚2
𝑡𝑡𝑜𝑜𝑜𝑜

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 Applying small 𝑉𝑉𝐷𝐷𝑆𝑆

Figure 4.3 An NMOS transistor with vGS > V t and with a small vDS applied. The device acts as a resistance whose value is
determined by vGS . Specifically, the channel conductance is proportional to vGS – V t’ and thus iD is proportional to (vGS – V t) vDS .
Note that the depletion region is not shown (for simplicity).
Microelectronic Circuits - Fifth
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Edition Sedra/Smith
 Applying small 𝑉𝑉𝐷𝐷𝑆𝑆
• Electrons are emitted from the source and move
to drain.
• Direction of conventional current is from drain to
source.
• Device acts like a linear resistor whose value is
controlled by 𝑣𝑣𝐺𝐺𝐺𝐺
• Linear relationship between current and voltage

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 Applying small 𝑉𝑉𝐷𝐷𝑆𝑆

• 𝜇𝜇𝑛𝑛 = 𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚 𝑜𝑜𝑜𝑜 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒

• 𝐶𝐶𝑜𝑜𝑜𝑜 = 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
𝑊𝑊
• 𝐿𝐿
= 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟
• 𝑘𝑘𝑛𝑛′ = 𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝
• 𝑘𝑘𝑛𝑛 = 𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝

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 Applying small 𝑣𝑣𝐷𝐷𝑆𝑆
• rDS is dependent on three factors
– process transconductance parameter for NMOS
(µnCox) – which is determined by the
manufacturing process
– aspect ratio (W/L) – which is dependent on size
requirements / allocations
– overdrive voltage (vOV) – which is applied by the
user

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 kn is known as NMOS-FET
transconductance parameter
and is defined as µnCoxW/L

1/rDS

low resistance, high vOV

high resistance, low vOV

Figure : The iD-vDS characteristics of the MOSFET. when the voltage
Oxford University Publishing
applied between drain and source VDS is kept small.
Microelectronic Circuits by Adel S.
Sedra and Kenneth C. Smith
21
 Effect of 𝑉𝑉𝑜𝑜𝑜𝑜 on channel
• As vOV grows, so does the depth of the n-
channel as well as its conductivity

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 Operation as 𝑣𝑣𝐷𝐷𝑆𝑆 is increased
𝑣𝑣𝐷𝐷𝐷𝐷 < 𝑉𝑉𝑜𝑜𝑜𝑜
• Current voltage
relationship is no longer
linear
• Triode region

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 Operation as 𝑣𝑣𝐷𝐷𝑆𝑆 ≥ 𝑉𝑉𝑜𝑜𝑜𝑜
• Current becomes constant
• Channel pinch off occurs
• MOSFET enters the saturation region
• Used as a voltage controlled current source.
• MOS is used as an amplifier
• Drain current is dependent on VGS and
independent of VDS

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 𝑊𝑊 1
triode: 𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑣𝑣𝑂𝑂𝑂𝑂 − 𝑣𝑣𝐷𝐷𝐷𝐷 𝑣𝑣𝐷𝐷𝐷𝐷 if 𝑣𝑣𝐷𝐷𝐷𝐷 < 𝑣𝑣𝑂𝑂𝑂𝑂
𝐿𝐿 2
𝑖𝑖𝐷𝐷 =
1 𝑊𝑊 2
saturation: 𝜇𝜇 𝐶𝐶 𝑣𝑣 otherwise
2 𝑛𝑛 𝑜𝑜𝑜𝑜 𝐿𝐿 𝑂𝑂𝑂𝑂

Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor
operated with vGS > V t.

Microelectronic Circuits - Fifth

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Edition Sedra/Smith
The iD-vDS Characteristics

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Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an
arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c)
Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device
operation is unimportant.
Microelectronic Circuits - Fifth
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Edition Sedra/Smith
Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of
current flow indicated. (b) The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V 2.

Microelectronic Circuits - Fifth

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Edition Sedra/Smith
 Effect of 𝑣𝑣𝐷𝐷𝑆𝑆 on the shape of channel
• 𝑣𝑣𝐷𝐷𝑆𝑆 is small
• channel is uniform
• 𝑣𝑣𝐷𝐷𝑆𝑆 < 𝑉𝑉𝑜𝑜𝑜𝑜
• Channel is tapered
• 𝑣𝑣𝐷𝐷𝑆𝑆 ≥ 𝑉𝑉𝑜𝑜𝑜𝑜
• Channel is pinched off

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Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – V t’ the channel is
pinched off at the drain end. Increasing vDS above vGS – V t has little effect (theoretically, no effect) on the channel’s shape.

Microelectronic Circuits - Fifth

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Edition Sedra/Smith
 Reason for non uniform channel
• Understand two parameters
1. Voltage drop across channel from drain to
source 𝑣𝑣𝐷𝐷𝑆𝑆
2. Voltage difference between gate and channel
𝑣𝑣𝐺𝐺𝐺𝐺

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 Reason for non uniform channel
• 𝑣𝑣𝐺𝐺𝐺𝐺 = 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑣𝑣𝐷𝐷𝐷𝐷
Condition for saturation
• 𝑣𝑣𝐷𝐷𝐷𝐷 > 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑡𝑡
• 𝑣𝑣𝐷𝐷 − 𝑣𝑣𝑆𝑆 > 𝑣𝑣𝐺𝐺 − 𝑣𝑣𝑆𝑆 − 𝑉𝑉𝑡𝑡
• 𝑣𝑣𝐷𝐷 > 𝑣𝑣𝐺𝐺 − 𝑉𝑉𝑡𝑡
• 𝑣𝑣𝐷𝐷 − 𝑣𝑣𝐺𝐺 > −𝑉𝑉𝑡𝑡
• 𝑣𝑣𝐷𝐷𝐷𝐷 > −𝑉𝑉𝑡𝑡
• −𝑣𝑣𝐺𝐺𝐺𝐺 > −𝑉𝑉𝑡𝑡
• 𝑣𝑣𝐺𝐺𝐺𝐺 < 𝑉𝑉𝑡𝑡 Triode Region
• 𝑣𝑣𝐺𝐺𝐺𝐺 > 𝑉𝑉𝑡𝑡
• 𝑣𝑣𝐺𝐺𝐺𝐺 = 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑡𝑡 = 𝑉𝑉𝑡𝑡 Edge of saturation

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 Reason for non uniform channel
• vGS is held constant at value greater than Vt.
• vDS is applied and appears as voltage drop across the length
of the n-channel.
• At the source end:
• 𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺𝐺𝐺
• At the drain end:
• 𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺𝑆𝑆 − 𝑉𝑉𝐷𝐷𝐷𝐷
• Going from drain to source, voltage drop at each point with
respect to source decreases linearly.

• For small values of vDS, one can still assume that voltage
between gate and n-channel is constant
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 Figure : Operation of MOSFET with vGS = Vt +
vOV as vDS is increased to vOV. At the drain end,
vGD decreases to Vt and the channel depth at
the drain-end reduces to zero (pinch-off). At
this point, the MOSFET enters saturation mode
of operation. Further increasing vDS (beyond
vOV) has no effect on the channel shape and iD
remains constant. 35
Oxford University Publishing
Microelectronic Circuits by Adel S.
Sedra and Kenneth C. Smith
37
𝑉𝑉𝐺𝐺 = 0
𝑉𝑉𝐺𝐺𝐺𝐺 = 0 − 0.5

𝑉𝑉𝐺𝐺𝐺𝐺 < 𝑉𝑉𝑡𝑡

Device in saturation

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𝑉𝑉𝐺𝐺 = +5𝑉𝑉
𝑉𝑉𝐷𝐷 = 0.1𝑉𝑉

𝑉𝑉𝐺𝐺𝐺𝐺 = 5 − 0.1
𝑉𝑉𝐺𝐺𝐺𝐺 > 𝑉𝑉𝑡𝑡
Device in triode region

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𝐼𝐼𝐺𝐺 = 0

Assume the device in saturation

mode
𝑉𝑉𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝐼𝐼𝐷𝐷 𝑅𝑅𝐷𝐷
𝐼𝐼𝐷𝐷 = 𝐼𝐼𝑆𝑆
𝑉𝑉𝑆𝑆 = 𝐼𝐼𝐷𝐷 𝑅𝑅𝑆𝑆

𝑉𝑉𝑆𝑆 = 0.89 × 6
𝑉𝑉𝑆𝑆 = 5.34𝑉𝑉

𝑉𝑉𝐺𝐺𝐺𝐺 = 5 − 5.34 𝑉𝑉𝐺𝐺𝐺𝐺 = 5 −7

Negative VGS is not
valid for NMOS
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