5-1

CAS303-Computer Organization (II)

Fall 2023- 2024
Weeks 8 & 9

EL-SAYED ABDEL-RAHMAN
[email protected]
OFFICE: EELU- AIN SHAMS CENTRE.
PHONE: 33318447

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-2

Chapter 5
BASIC COMPUTER ORGANIZATION
AND DESIGN

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 Introduction to MARIE 5-3
'Machine Architecture that is Really Intuitive and Easy”

 Introduction to MARIE and MARIE.js MARIE ('Machine

Architecture that is Really Intuitive and Easy') is a machine
architecture and assembly language served only for
educational purposes from The Essentials of Computer
Organization and Architecture (Linda Null, Julia Lobur). In
addition, the publisher provides a set of simulator programs
for the machine, written in Java. MARIE.js is a JavaScript
version implementation of MARIE. It aims to be as faithful to
the original Java programs as it can, while improving on
features to make concepts more intuitive and easier to
understand. In this book we will use MARIE.js this is
available at: https://marie-js.github.io/MARIE.js/ The basic
idea, is that the MARIE assembly language is a simple
implementation of the von Neumann architecture as shown
below.
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-4
Architecture & Organization

Structure and behavior of the computer as seen by the user.

 those
properties, which directly affect the logical working
of a program;
 the attributes, which are apparent to a programmer
Examples: instruction set and formats, techniques for
addressing memory, number of bits used to represent data.

 Organization: interconnection of operational units for

realizing the architectural specifications
• Determination of which hardware should be used and
• how the parts should be connected together

4
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-5
Architecture & Organization

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-6
BASIC COMPUTER ORGANIZATION AND DESIGN
• Instruction Codes

• Computer Registers

• Computer Instructions

• Timing and Control

• Instruction Cycle

• Memory Reference Instructions

• Input-Output and Interrupt

• Complete Computer Description

• Design of Basic Computer

• Design of Accumulator Logic

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-7
Computer Orgnaization

Computer hardware = registers + ALU + datapath (bus) + control

unit.

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-8
Chap. 5 Basic Computer Org. and Design
 In this chapter we introduce concept of a basic computer and
show how its operation can be specified with register transfer
statements.
 The organization of the computer is defined by its internal
registers, the timing and control structure and the set of
instructions that it uses.
 Although the basic computer presented in this chapter is very small
compared to commercial computers, it has the advantage of being
simple enough so we can demonstrate the design process without
too many complications.
 The internal organization of a digital system is defined by the
sequence of micro operations it performs on data stored in its
registers.
 The general-purpose digital computer is capable of executing
various micro operations and, in addition, can be instructed as to
what specific sequence of operations it must perform.
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-9
Chap. 5 Basic Computer Org. and Design

 The user of a computer can control the process by means of a program.

 A program is a set of instructions that specify the operations, operations
operands, and the sequence by which processing has to occur.

 A computer instruction is a binary code that specifies a sequence of

micro operations for the computer. Instruction codes together with data are
stored in memory.
 The computer reads each instruction from memory and places it in a
control register. The control then interprets the binary code of the
instructions and proceeds to execute it by issuing a sequence of micro
operations.
 Every computer has its own unique instruction set.

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-10
INTRODUCTION

 Every different processor has its own design

(different registers, buses, micro-operations, machine instructions, etc)
 Modern processor is a very complex device
 It contains
 Many registers
 Multiple arithmetic units, for both integer and floating point calculations
 The ability to pipeline several consecutive instructions to speed execution
 Etc.
Pipelining is one way of improving the overall processing performance of a processor.
This architectural approach allows the simultaneous execution of several instructions.
Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is
divided into stages and these stages are connected with one another to form a pipe like
structure. Instructions enter from one end and exit from another end.
 However, to understand how processors work, use a simplified processor
model
 This is similar to what real processors were like More than 30 years ago

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-11
Chap. 5 Basic Computer Org. and Design

 instruction code
 The ability to store and execute instructions, the stored program
concept, is the most important property of a general-purpose computer.
 An instruction code is a group of bits that instruct the computer to
perform a specific operation. 15 12 11 0

Op. Code Address

 It is usually divided into parts, each having its own particular

interpretation.
 The most basic part of an instruction code is its operation part.
 The operation code of an instruction is a group of bits that define such
operations as add, subtract, multiply, shift, and complement.

 The number of bits required for the operation code of an instruction

depends on the total number of operations available in the computer.
 3bit—> 2^3 = 8 operations, etc.
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-12
Chap. 5 Basic Computer Org. and Design

 5-1 Instruction Codes

 The user of a computer can control the process by means of a program
 A program is a set of instructions that specify the operations, operand, the
sequence(control)
 A instruction is a binary code that specifies a sequence of microoperations
 Instruction codes together with data are stored in memory(=Stored Program
Concept)
 The computer reads each instruction from memory and places it in a
Instruction control register. The control then interprets the binary code of the
Cycle instruction and proceeds to execute it by issuing a sequence of
microoperations.
 Instruction Code :
 A group of bits that instruct the computer to perform a specific operation
 It is usually divided into parts(refer to Fig. 5-1 instruction format) Instruction Format
 Operation Code : 15 12 11 0

 The most basic part of an instruction code Op. Code Address

 A group of bits that define such operations as add, subtract, multiply, shift, and
complement(bit 12-15 : 24 = 16 distinct operations)
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-13
Stored Program Organization

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-14
Computers that have a single- processor register

 Computers that have a single- processor register usually assign to it the

name accumulator and label it AC. The operation is performed with
the memory operand and the content of AC.

 If an operation in an instruction code does not need an operand from

memory, the rest of the bits in the instruction can be used for other
purposes. For example:
 operations such as clear AC, complement AC, and increment AC
operate on data stored in the AC register. They do not -need an operand
from memory. For these types of operations, the second part of the
instruction code (bits 0 through 11) is not needed for specifying a
memory address and can be used to specify other operations for the
computer.

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-15

 Stored Program Organization : Fig. 5-1

 The simplest way to organize a computer
» One processor register : AC(Accumulator)
 The operation is performed with the memory operand and the content of AC
» Instruction code format with two parts : Op. Code + Address
Exam)  Op. Code : specify 16 possible operations(4 bit)
Clear AC, Increment AC,  Address : specify the address of an operand(12 bit)
Complement AC, ...  If an operation in an instruction code does not need an operand from memory, the rest of the
bits in the instruction(address field) can be used for other purpose( instruction Tab. 5-2 25
instruction)
» Memory : 12 bit = 4096 word (Instruction and Data are stored)
 Store each instruction code(program) and operand (data) in 16-bit memory word

 Addressing Mode
 Immediate operand address :
» the second part of an instruction code(address field) specifies an operand
 Direct operand address : Fig. 5-2(b)
» the second part of an instruction code specifies the address of an operand
 Indirect operand address : Fig. 5-2(c)
I=0 : Direct,
I=1 : Indirect » the bits in the second part of the instruction designate an address of a memory word
in which the address of the operand is found (Pointer)
 One bit of the instruction code is used to distinguish between a direct and an
indirect address : Fig. 5-2(a)
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-16
Direct & indirect address

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-17

 Effective Address
 The address, that can be directly used without modification to access an operand for
a computation-type instruction, or as the target address for a branch-type instruction
 5-2 Computer Registers
 List of Registers for the Basic Computer : Tab. 5-1
 Basic computer registers and memory : Fig. 5-3
 Data Register(DR) : hold the operand(Data) read from memory
 Accumulator Register(AC) : general purpose processing register
 Instruction Register(IR) : hold the instruction read from memory
 Temporary Register(TR) : hold a temporary data during processing
 Address Register(AR) : hold a memory address, 12 bit width
 Program Counter(PC) : hold the address of the next instruction to be read from
memory after the current instruction is executed

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-18
Registers for the Basic Computer

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Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-19

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 Instruction codes
5-20
PROCESSOR REGISTERS

 A processor has many registers to hold instructions, addresses,

data, etc
 The processor has a register, the Program Counter (PC) that holds
the memory address of the next instruction
 Since the memory in the Basic Computer only has 4096 locations, the PC only
needs 12 bits
 In a direct or indirect addressing, the processor needs to keep track
of what locations in memory it is addressing: The Address Register
(AR) is used for this
 The AR is a 12 bit register in the Basic Computer
 When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The processor
then uses this value as data for its operation
 The Basic Computer has a single general purpose register – the
Accumulator (AC)

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 Instruction codes
5-21
PROCESSOR REGISTERS

 The significance of a general purpose register is that it can be used

for loading operands and storing results
 e.g. load AC with the contents of a specific memory location; store the contents of
AC into a specified memory location
 Often a processor will need a scratch register to store intermediate
results or other temporary data; in the Basic Computer this is the
Temporary Register (TR)
 The Basic Computer uses a very simple model of input/output (I/O)
operations
 Input devices are considered to send 8 bits of character data to the processor
 The processor can send 8 bits of character data to output devices
 The Input Register (INPR) holds an 8 bit character gotten from an
input device
 The Output Register (OUTR) holds an 8 bit character to be send to an
output device
 Input Register(INPR) : receive an 8-bit character from an input device
 Output Register(OUTR) : hold an 8-bit character for an output device
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-22
Common Bus System
 Common Bus System
 The basic computer has eight registers, a memory unit, and a control unit(in Sec. 5-
4)
 Paths must be provided to transfer information from one register to another and
between memory and registers
 A more efficient scheme for transferring information in a system with many
registers is to use a common bus(in Sec. 4-3)
 The connection of the registers and memory of the basic computer to a common
bus system : Fig. 5-4
 It is known that how to construct a bus system using multiplexers or three-
state buffer gates.
» The outputs of seven registers and memory are connected to the
common bus
» The specific output is selected by mux(S0, S1, S2) :
 Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6)

 When LD(Load Input) is enable, the particular register receives the

data from the bus
» Control Input : LD, INC, CLR, Write, Read
» Address Register : Address bus Bus address data).

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-23

» Accumulator(AC) : 3 Path
s2
 1) Register Microoperation : clear AC, s1 Bus
shfift AC,… Memory unit
s0
7
4096× 16 Address
 2) Data Register : add DR to AC, and
DR to AC(AC
Write Read
AR
1

LD INR CLR
 3) INPR : Device(Adder & Logic) PC 2
» Note) Two microoperations can be LD INR CLR

executed at the same time DR

3
LD INR CLR
DR  AC : s2 s1s0  100(4), DR(load)
AC  DR : DR  Adder & Logic  AC (load) Adder
and
E
AC 4
logic
LD INR CLR

INPR

IR 5

LD

TR
6
LD INR CLR

OUTR

Clock
LD

16-bit common bus

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 Registers
5-24
COMMON BUS SYSTEM

 The registers in the Basic Computer are connected using a bus

 This gives a savings in circuitry over complete connections
between registers.
 Three control lines, S2, S1, and S0 control which register the
bus selects as its input

 Either one of the registers will have its load signal activated, or
the memory will have its read signal activated
 Will determine where the data from the bus gets loaded
 The 12-bit registers, AR and PC, have 0’s loaded onto the bus
in the high order 4 bit positions
 When the 8-bit register OUTR is loaded from the bus, the data
comes from the low order 8 bits on the bus

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Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-25

 5-3 Computer Instruction

 3 Instruction Code Formats : Fig. 5-5
Hex Code
 Memory-reference instruction Symbol I=0 I=1 Description
» Opcode = 000  110 AND
ADD
0xxx 8xxx
1xxx 9xxx
And memory word to AC
Add memory word to AC
 I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
I=0 : Direct, 15 14 12 11 0 BUN 4xxx Cxxx Branch unconditionally
I=1 : Indirect BSA 5xxx Dxxx Branch and Save return address
I Opcode Address ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMS 7200 Complement AC
 Register-reference instruction CME 7100 Complement E
CIR 7080 Circulate right AC and E
» 7xxx (7800 ~ 7001) : CLA, CMA, …. CIL 7040 Circulate left AC and E
INC 7020 Increment AC
15 14 12 11 0 SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
0 1 1 1 Register Operation SZA 7004 Skip next instruction if AC zero
SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
 Input-Output instruction SKI F200 Skip on input flag
SKO F100 Skip on output flag
» Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, …. ION F080 Interrupt On
IOF F040 Interrupt Off
15 14 12 11 0

1 1 1 1 I/O Operation

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-26
3 Instruction Code Formats

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Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-27
3 Instruction Code

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Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 Instructions
5-28
INSTRUCTION SET COMPLETENESS
A set of instructions is said to be complete if the
computer includes a sufficient number of instructions in
each of the following categories: Arithmetic, logical and
shift instructions. A set of instructions for moving
information to and from memory and processor registers.

Instruction Set Completeness

Arithmetic, Logical, and shift : CMA, INC,
..
Moving information to and from memory
and AC : STA, LDA
Program control : BUN, BSA, ISZ
Input/Output : INP, OUT
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-29

CAS303-Computer Organization (II)

Fall 2021- 2022
Week 9

EL-SAYED ABDEL-RAHMAN
[email protected]
OFFICE: EELU- AIN SHAMS CENTRE.
PHONE: 33318447

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-30
Instruction Types

Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA (other than
ADD/AND?)
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 Instruction codes
5-31
CONTROL UNIT

 Control unit (CU) of a processor translates from machine

instructions to the control signals (for the microoperations) that
implement them

 Control units are implemented in one of two ways

 Hardwired Control
 CU is made up of sequential and combinational circuits to generate the
control signals
 Microprogrammed Control
 A control memory on the processor contains microprograms that activate
the necessary control signals

 We will consider a hardwired implementation of the control unit

for the Basic Computer

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-32

 5-4 Timing and Control

 Clock pulses
A master clock generator controls the timing for all registers in the basic

computer
 The clock pulses are applied to all F/Fs and registers in system
 The clock pulses do not change the state of a register unless the register
is enabled by a control signal
 The control signals are generated in the control unit : Fig. 5-6
» The control signals provide control inputs for the multiplexers in
the common bus, control inputs in processor registers, and
microoperations for the accumulator
 Two major types of control organization
 Hardwired Control : Chap. 5
» The control logic is implemented with gates, F/Fs, decoders, and
other digital circuits
» + Fast operation, - Wiring change(if the design has to be modified)

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-33

 Microprogrammed Control : Chap. 7

» The control information is stored in a control memory, and the control memory is
programmed to initiate the required sequence of microoperations
» + Any required change can be done by updating the microprogram in control memory,
- Slow operation Instruction register (IR)
15 14 13 12 11 - 0

 Control Unit : Fig. 5-6

 Control Unit = Control Logic Gate + 3× 8
decoder
Other inputs

3 X 8 Decoder + Instruction Register 7 6 5 4 3 2 1 0

+ Timing Signal I D0
.
.
 Timing Signal = 4 X 16 Decoder + D7 .
Control
Control
outputs
logic
4-bit Sequence Counter gates

T 15
 Control timing : Fig. 5-7 .
.
T0
» Sequence Counter is cleared when
.

.
.
.
15 14 1 0

.
.
.
D3T4 =1 : D3T4 : SC  0 4× 16
decoder
 Memory R/W cycle time > Clock
cycle time
Increment(INR)
4-bit
» . sequence
Clear(CLR)
counter
(SC)
Clock

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-34
Control timing

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Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-35
CONTROL UNIT HARDWARE

• Inputs to the control unit come from IR where an instruction read from the memory
unit is stored.
• A hardwired control is implemented in the example computer using:
> A 3 x 8 decoder to decode opcode bits 12-14 into signals D0, ..., D7;
> A 4-bit binary sequence counter (SC) to count from 0 to 15 to achieve time
sequencing;
> A 4 x 16 decoder to decode the output of the counter into 16 timing signals, T0, ...,
T15
> A flip-flop (I) to store the addressing mode bit in IR;
> A digital circuit with inputs—D0, ..., D7, T0, ..., T15, I, and address bits (11-0) in
IR—to generate control outputs supplied to control inputs and select signals of the
registers and the bus.
• Clocking principle: The binary counter goes through a cycle, 0000  0001  0010
 ...  1111  0000. Accordingly only one of T0, ..., T15 is 1 at each clock cycle, T0
 T1  T2  ...  T15  T0; all the other timing signals are 0.
• By setting the clear input (CLR) of SC at a clock cycle, say T3, we can achieve a 4-
cycle clock: T0  T1  T2  T3  T0.

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-36
Timing and Control

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Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-37
Example: Hardwired Control Unit
If the input register contains the value 1001010001010111 then we can
understand this instruction by understanding the values of its fields.

As, the 15th bit is 1. So, it represents indirect addressing mode.

12,13,14 bits of opcode are 001 which represent ADD operation. ADD operation also denoted
by D1.
0 to 11 bits are 010001010111 which represents the address of the operand.
If this instruction executed at Time T2. Then it can symbolically represent as D1T2 and SC
becomes Zero.
This instruction means that apply ADD operation on address (010001010111) of memory.
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-38

 Register transfer statement : T0 : AR  PC

 A transfer of the content of PC into AR if timing signal T0 is active

» 1) During T0 active, the content of PC is placed onto the bus ( S2 S1S0 )
» 2) LD(load) input of AR is enabled, the actual transfer occurs at the next positive
transition of the clock(T0 rising edge clock)
» 3) SC(sequence counter) is incremented : 0000(T0 )  0000(T1 ) T0 : Inactive
T1 : Active
 5-5 Instruction Cycle
 Instruction Cycle
 1) Instruction Fetch from Memory
Continue
 2) Instruction Decode
indefinitely
 3) Read Effective Address(if indirect addressing mode) unless HALT
 4) Instruction Execution instruction is
encountered
 5) Go to step 1) : Next Instruction[PC + 1]

 Instruction Fetch : T0, T1(Fig. 5-8)

T0 : A R  P C
T1 : IR  M [ A R ], P C  P C  1

 T0 = 1 T0 : AR  PC
» 1) Place the content of PC onto the bus by making the bus selection inputs S2S1S0=010
» 2) Transfer the content of the bus to AR by enabling the LD input of AR
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-39

 T1 = 1 T1 : IR  M [ A R ], P C  P C  1
» 1) Enable the read input memory
» 2) Place the content of memory onto the bus by making S2S1S0= 111
» 3) Transfer the content of the bus to IR by enable the LD input of IR
» 4) Increment PC by enabling the INR input of PC

 Instruction Decode : T2 T1=1 s2

0 1
T 2 : D 0 ,...., D 7  D e c o d e I R (1 2  1 4 ) , A R  I R ( 0  1 1 ) , I  I R (1 5 ) T0=1 s1
Bus 1 1
s0
Op.code Address Di/Indirect 0 1
Memory
Memory unit
unit 7

 IR(12-14) Fig. 5-6 D0 - D7 Address

Read

 Instruction Execution : T3, T4, T5, T6

IR (12  14 )
D7=1 Register(I=0) D7I’T3(Execute) Read effective
 111 AR 1
I/O (I=1) D7IT3 (Execute) Address
LD

D7=0 : Memory Ref. Indirect(I=1) D7’IT3( A R  M [ A R ] )

PC 2
Direct (I=0) nothing in T3
INR

 Flowchart for instruction cycle(Initial

IR 5
Configuration) : Fig. 5-9 LD

Clock

Common bus

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Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 Timing and control
5-40
TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

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Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-41

 Register Ref. Instruction

 r = D7I’T3 : Fig. 5-9 Flowchart for instruction cycle(initial)
 IR(i) = Bi IR(0 -11)
Start
SC 0
 B0 - B11 : 12Register Ref. Instruction
T0
(Tab. 5-3) AR PC

 5-6 Memory Ref. Instruction IR M[AR], PC PC+1

T1

IR(12,13,14)
3X8 D7 : Register or I/O = 1 = 111 Decode operation code in IR(12-14)
T2

AR IR(0-11), I I(15)
Decoder D6 - D0 : 7 Memory Ref.
Instruction(Tab. 5-4) (Register or I/O) = 1
I
0 = (Memory-reference

 AND to AC
(I/O) = 1 0 = (register) (indirect) = 1 0 = (direct)
D 0 T 4 : DR  M [ A R ] I I

D 0 T 5 : A C  A C  DR , SC  0 T3 T3 T3 T3

Execute Execute
 ADD to AC
AR M[AR] Nothing
input-output register-reference
instruction instruction
SC 0 SC 0
D 1T 4 : DR  M [ A R ]
Execute

D 1T 5 : A C  A C  DR , E  C o u t , SC  0 memory-reference
instruction
SC 0

 LDA : memory read

D 2 T 4 : DR  M [ A R ]
D 2 T 5 : A C  DR , SC  0
© Korea Univ. of Tech. & Edu.
Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-42

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-43

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.
 5-44

 STA : memory write Fig. 5-10 Example of BSA

D 3T 4 : M [ A R ]  A C , S C  0
PC = 10 0 BSA 135
 BUN : branch unconditionally PC = 21 next instruction
D 4T 4 : P C  A R , S C  0
 BSA : branch and save return address 135 21(return address)
PC = 136
D 5T 4 : M [ A R ]  P C , A R  A R  1 Subroutine
D 5T 5 : P C  A R , SC  0 1 BUN 135

 Return Address : save return address ( 135 21 )

 Subroutine Call : Fig. 5-10 D 5T 4 : M [135 ]  21( P C ), 136 ( A R )  135  1
 ISZ : increment and skip if zero D 5T 5 : 136 ( P C )  136 ( A R ), SC  0
D 6T4 : DR  M [ AR ]
D 6T5 : DR  DR  1
D 6T6 : M [ AR ]  DR , if ( DR  0 ) then ( PC  PC  1), SC  0

 Control Flowchart : Fig. 5-11

 Flowchart for the 7 memory reference instruction
» The longest instruction : ISZ(T6)
» 3 bit Sequence Counter

© Korea Univ. of Tech. & Edu.

Computer System Architecture Chap. 5 Basic Computer Organization and Design Dept. of Info. & Comm.