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Computer Architecture_Lecture 06

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fariha1117
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Computer Architecture

Lecture 06
Cache Memory
Instructor: Sultana Jahan Soheli
Assistant Professor, ICE, NSTU
Reference Books
• Computer Organization and Architecture:
Designing for Performance- William Stallings
(8th Edition)
– Any later edition is fine
Fully Associative Cache Organization
Fully Associative Cache Example
Fully Associative Cache Example

• Advantage and Disadvantages?


– Refer to textbook
Set-associative Mapping
Set-associative Mapping (2- way set.)
Varying Associativity over Cache Size
Replacement Algorithms
• Once the cache has been filled, when a new block
is brought into the cache, one of the existing
blocks must be replaced
• For direct mapping, there is only one possible line
for any particular block, and no choice is possible
• For the associative and set-associative
techniques, a replacement algorithm is needed
– To achieve high speed, such an algorithm must be
implemented in hardware
Replacement Algorithms
• Least Recently Used (LRU)
– Most effective
• First-in-First-Out (FIFO)
• Least Frequently Used (LFU)

• For details: Find the book and study!


Write Policy
• When a block that is resident in the cache is to be
replaced, there are two cases to consider
• If the old block in the cache has not been altered,
then it may be overwritten with a new block
without first writing out the old block
• If at least one write operation has been
performed on a word in that line of the cache,
then main memory must be updated by writing
the line of cache out to the block of memory
before bringing in the new block
Write Policy
• Two potential problems
• More than one device may have access to
main memory
• If multiple processors are attached to the
same bus and each processor has its own local
cache
Write Policies
• Write through
– Simplest of all
• Write back
– Minimizes memory writes (dirty bit or use bit)
Q. Consider a cache with a line size of 32 bytes and a
main memory that requires 30 ns to transfer a 4-byte
word. For any line that is written at least once before
being swapped out of the cache, what is the average
number of times that the line must be written before
being swapped out for a write-back cache to be more
efficient that a write through cache?
Write Policies
• In a bus organization in which more than one
device (typically a processor) has a cache and
main memory is shared, a new problem is
introduced
• If data in one cache are altered, this invalidates
not only the corresponding word in main
memory, but also that same word in other caches
• A system that prevents this problem is said to
maintain cache coherency
Write Policies
• Solutions:
– Bus watching with write through
– Hardware transparency
– Non-cacheable memory
Line Size
• Larger blocks reduce the number of blocks
that fit into a cache
– Because each block fetch overwrites older cache
contents, a small number of blocks results in data
being overwritten shortly after they are fetched
• As a block becomes larger, each additional
word is farther from the requested word and
therefore less likely to be needed in the near
future
Number of Caches
• Multilevel Caches: Off chip or On chip
– L1, L2 (Sometimes do not use system bus)
• Unified Versus Split Caches
• Advantage of Unified Cache
1) For a given cache size, a unified cache has a higher
hit rate than split caches because it balances the
load between instruction and data fetches
automatically
2) Only one cache needs to be designed and
implemented
Number of Caches
• Advantage of Unified Cache Split cache
– It eliminates contention for the cache between the
instruction fetch/decode unit and the execution unit
– This is important in any design that relies on the
pipelining of instructions
– Used in Superscalar Processors (e.g. Pentium and
PowerPC etc.)

• Practice the given problems!

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