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Vlsi Design

RTL to gds and cmos

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jayapreethaselvam
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14 views5 pages

Vlsi Design

RTL to gds and cmos

Uploaded by

jayapreethaselvam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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RTL-to-GDSII design flow is the standard process used in the semiconductor industry to

transform high-level design (RTL) into a physical layout (GDSII) that can be fabricated into
silicon chips.
The complete process can be divided into two parts:
1)Frontend 2)Backend

Design Specification: A document outlining functionality, performance, and


constraints of the chip.Defines goals for timing, power, and area.Acts as the
blueprint for the design.
 RTL Description: The design is described using Hardware Description
Languages (HDL) such as Verilog or VHDL. This RTL (Register Transfer Level)
code specifies the behaviour of the digital circuit in terms of data flow and control.
 Functional Verification: Ensures that the RTL description matches the
design specification. Here the code is simulated,in RTL Simulator and the
functionality of the design is verified. Once the functionality of code is correct and
verified by the verification engineers and if there is no bug found, the RTL code is
taken to the next stage which is logic synthesis.

Logic Synthesis: Logic synthesis is the process of converting a high-level


RTL description written in a HDL into a representation using logic gates from a
technology library.
It involves optimization for power, performance, and area based on
Logic Equivalence Check:Verifies that the Gate-Level Netlist is
functionally equivalent to the RTL description.
Place and Route: Placement-Standard cells and macros are positioned on
the chip based on the floorplan.Routing-Electrical connections (metal layers) are
created to interconnect the cells and blocks. The goal of PnR stage is to place all
the standard cells, Macros and I/O pads with minimal area, with minimal delay and
Route them together in such a way that there is no DRC (Design Rule Check)
error. The main stages are starting from Design Import, followed by FloorPlan,
Power Plan, Placement, CTS (Clock Tree Synthesis), and Routing.
 Physical Layout: Final physical arrangement of all components,
interconnects, and power distribution on the chip.Includes details such as via
placements, wire dimensions, and layer assignments. Cadence Innovus- Widely
used for placement, routing, and optimization.Synopsys IC Compiler- Used for
creating physical layouts.
Physical Verification: Ensuring that the chip layout is manufacturable and
meets all design requirements. Ensures that the physical layout adheres to:Design
Rule Checks (DRC): Verifies compliance with foundry rules for spacing, width,
etc.Layout Versus Schematic (LVS):Ensures the physical layout matches the
gate-level netlist.Parasitic Extraction: Captures the parasitics (resistance and
capacitance) introduced by physical layout and ensures timing and signal integrity.
GDSII File:The GDSII file(Graphic Data System),is the industry-standard
format for representing the physical layout of an integrated circuit (IC). It contains
Complementary Metal Oxide Semiconductor. This is one of the
most popular technology in the computer chip design industry.

PMOS NMOS
Key Features of CMOS Circuits
Connected Connected Pull Up Network: Contains pMOS transistors that
between Vdd and between Vss and pull the output to HIGH (Vdd) when active.
Output(logic 0) Output(logic 1)
Pull Down Network: Contains nMOS transistors that
pull the output to LOW (Gnd) when active.

Now let us consider an example(CMOS Inverter) to know


the Operation of CMOS
• The CMOS inverter consists of one PMOS and one
NMOS.
•Consider two cases
Input=Low(0)
PMOS is ON, allowing current to flow from Vdd to the output.
NMOS is OFF, isolating the output from the ground.
Output = HIGH (1).
Input=High(1)
PMOS is OFF, isolating the output from Vdd. NMOS is ON,
allowing current to flow from the output to ground.
Output = LOW (0).
•Only one transistor (PMOS or NMOS) conducts at a time, ensuring low
static power consumption.
•Switching power is consumed during transitions between states due to
charging and discharging of the load capacitance.
ADVANTAGES OF CMOS TECHNOLOGY Challenges
Low Power Consumption
Leakage Current
High Noise Immunity
Power Dissipation
Scalability Process Variability
High Integration Density

APPLICATION
1)Digital Circuits
2)Analog Circuits
3)Mixed Signal Circuits

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