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Lab

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Sourav kumar
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4 views2 pages

Lab

Uploaded by

Sourav kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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//121EC0290 Sourav Kumar Naik //121EC0290 Sourav Kumar Naik

module module d_ff_asyn_tb();


d_ff_asyn(d,en,reset,q,clk); input reg d,en,reset,clk;
d, en, reset; output q; reg q; input wire q;
clk; wire clk; d_ff_asyn uut(d,en,reset,q,clk);

always@(posedge clk|reset) initial clk =1;


begin initial d =0;
if(reset) initial en =1;
q<=0; initial reset =0; always
else if(en) #10 clk=~clk; always #15
begin reset = ~reset;
q<=d; //121ec1066
end always
end begin
endmodule d =0; #25;
d =1; #25;
end
endmodule

//121EC0290 Sourav Kumar Naik //121EC0290 Sourav Kumar Naik

module module d_ff_syn_tb();


d_ff_syn(d,en,reset,q,clk); input reg d,en,reset,clk;
d, en, reset; output q; reg q; input wire q;
clk; d_ff_syn uut(d,en,reset,q,clk);
wire clk;
always@(posedge clk) initial clk =1;
begin initial d =0;
if(reset) initial en =1;
q<=0; initial reset =0; always #5
else if(en) clk=~clk; always #15 reset
begin = ~reset;
q<=d; //121ec1066
end always
end begin
endmodule d =0; #20;
d =1; #20;
end
endmodule
//121EC0290 Sourav Kumar Naik //121EC0290 Sourav Kumar Naik

module module
Dlatch(d,en,reset,q); input Dlatch_tb(); reg
d,en,reset; output q; reg q; d,en,reset; wire q;
always@(d,reset,en) Dlatch uut(d,en,reset,q);
begin if(reset) q=0; initial en=1;
else if(en) begin q = initial reset =0; always
d; end #10 reset =~reset; initial
end begin
endmodule d=0;#10;
d=1;#20;
reset =1;
d=0;#20;
d=1;#20;
reset=0;
d=1;#20;
d=1;#20;
end
endmodule

//121EC0290 Sourav Kumar Naik //121EC0290 Sourav Kumar Naik

module register( module


input wire [3:0]d, register_tb(); wire
input wire reset, [3:0]q; reg [3:0]d;
input wire clk, reg clk; reg reset;
output reg [3:0]q register
); uut(d,reset,clk,q); initial
always@(posedge clk or posedge reset) begin reset =0;
begin clk=0; end always begin
if(reset) clk=~clk; #7;end always begin
q<=0; #20 reset=~reset;
else #2;reset=~reset;end
q<=d; always begin d
end = 4'b1100;#10; d
endmodule = 4'b1110;#10; d
= 4'b1000;#10;
end endmodule

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