Module 5

Module 5 -: Exploring Finite State Machine Models

Syllabus: Moore and Mealy Models, Design Procedure, Design with State
Equations, State Reduction methods and Assignment, Verilog implementation
of Moore and Mealy.

DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUIT

Finite State Machine (FSM) is a calculation model that can be executed with the help
of hardware otherwise software. FSM is also known as finite state automation.

FSM This is used for creating sequential logic as well as a few computer programs.
FSMs are used to solve the problems in fields like mathematics, games, linguistics,
and artificial intelligence.

In a system where specific inputs can cause specific changes in state that can be
signified with the help of FSMs.

Finite State Machine is having two types of model: Moore Model or Mealy Model.

Moore Model:

• A Moore model is a type of finite state machine (FSM), named after Edward F.
Moore in 1956.
• The Moore state machine block diagram consists of two parts namely
combinational logic as well as memory.
• In this case, the current inputs, as well as current states, will decide the next
states.
• Thus, depending on further states, this machine will generate the outputs. So,
the outputs of this will be applicable simply after the conversion of the state.
• The output is generated only from the current state variables.
• It's widely used in digital circuit design and computer science. The key
characteristic of a Moore model is that its outputs depend only on the current
state of the machine, not on the input.

Page 1 of 34
 Module 5

Mealy Model

• Mealy model is a type of finite state machine (FSM) used in the design of digital
circuits and systems.
• It is named after George H. Mealy, who introduced the concept in 1955.
• The Mealy model is characterized by the fact that its outputs depend on both
the current state and the current inputs.
• This is in contrast to the Moore model, where the outputs depend only on the
current state.
• The Mealy model is widely used in digital design because it can lead to more
compact and efficient designs compared to the Moore model, especially when
the output logic is complex.

Page 2 of 34
 Module 5

Steps of Design of a synchronous sequential circuit(Moore / Mealy):

1. From the specification of the statement Identify the number of states and
number of output & inputs. Mention the notation for the input & output.
2. Derive state diagram
• State representation will be like s0, s1…. or a ,b,…
3. Derive the state table
4. Reduce the number of states, if possible, Write reduced state table.
5. Identify the number of bits required to a state. Assign the binary values to each
state.
6. Identify the Flip Flop to be used and number of Flip Flop required. Mention the
notation for the FF.
7. Derive the transition table.
8. Draw the logic circuit using identified FF

No of state = 2; s0 = 0; s1=1
No of states = 3; S0=00; S1=01; S2=10
No of states =4; A=00; B=01; C=10; D=11
No of states are between 5 to 8; use 3 bits

Page 3 of 34
 Module 5

Problem 1: Design sequence detector to detect a serial input sequence of110 using
Moore Model.

Solution:
Step 1: State Diagram

State Diagram using Moore Model for sequence detector 011

Step 2: State Table

Present state Next state (NS) Output

(PS)
X=0 X=1 Y
a a b 0

b a c 0

c d c 0

d a b 1

Step 3: Sate Transition Table

Page 4 of 34
 Module 5

State Transition Table for sequence detector 011

Step 4: K MAP

Step 5: Circuit

Page 5 of 34
 Module 5

Circuit Diagram

Problem 2: Design a sequential circuit whose state tables are specified in the given
Table, using D flip-flops.

Table. State table of a sequential circuit.

Output
Present State Next State
Q0 Q1 x=0 x=1 x=0 x=1

00 00 01 0 0

01 00 10 0 0

10 11 10 0 0

11 00 01 0 1

Solution:

Excitation table for a D flip-flop.

Page 6 of 34
 Module 5

Output Transitions Flip-flop inputs

Q Q(next) D

0 0 0
0 1 1
1 0 0
1 1 1

1. Transition Table
Outpu
Present State Next State Input Flip-flop Inputs
t
Q0 Q1 Q0 Q1 x D0 D1
Z

00 00 0 0 0 0
00 01 1 0 1 0
01 00 0 0 0 0
01 10 1 1 0 0
10 11 0 1 1 0
10 10 1 1 0 0
11 00 0 0 0 0
11 01 1 0 1 1

2. K MAP

Page 7 of 34
 Module 5

The simplified Boolean expressions are:

D0 = Q0 * Q1' + Q0' * Q1 * x
D1 = Q0' * Q1' * x + Q0 * Q1 * x + Q0 * Q1' * x'
Z = Q 0 * Q1 * x

3. Circuit diagram

Problem 3: Design sequence detector to detect a serial input sequence of 110 using
Mealy Model.

Page 8 of 34
 Module 5

Solution:
Step 1: State Diagram

State Diagram using Mealy Model for sequence detector 110

Step 2: State Table

Present state Next state (NS) Output Y

(PS)
X=0 X=1 X=0 X=1
a a b 0 0

b a c 0 0

c a c 1 0

Step 3: Sate Transition Table

Page 9 of 34
 Module 5

Present
Input Next state Output
state (PS) Jb Kb Ja Ka
Qb Qa X (NS) Y
0 0 0 0 0 0 0 X 0 X

0 0 1 0 1 0 0 X 1 X

0 1 0 0 0 0 0 X X 1

0 1 1 1 0 0 1 X X 1

1 0 0 0 0 1 X 1 0 X

1 0 1 1 0 0 X 0 0 X

Step 4: K MAP

Step 5: Circuit

Page 10 of 34
 Module 5

Problem 4: Design the circuit for the given state diagram using D FF.

1. State Table:

Page 11 of 34
 Module 5

2. State assignment:
A – 00; B-01; C-10; D-11

3. Excitation Table

4. Derivation of output expression.

Page 12 of 34
 Module 5

5. Logic Circuit

Problem 5: Design a synchronous sequential circuit whose state diagram is shown

in Figure below. The type of flip-flop to be use is J-K.

Page 13 of 34
 Module 5

Solution:
From the state
diagram, we can generate the state table shown in Table 9. Note that there is
no output section for this circuit. Two flip-flops are needed to represent the four
states and are designated Q0Q1. The input variable is labelled as x.

Present State Next State

Q0 Q1 x=0 x=1

00 00 01
01 10 01
10 10 11
11 11 00

Transition Table:

Page 14 of 34
 Module 5

Present Flip-flop Inputs

Input Next State
State J0K J1K
x Q0 Q1
Q0 Q1 0 1

00 00 00 0X 0X
1 00 01 0X 1X
0 01 10 1X X1
1 01 01 0X X0
0 10 10 X0 0X
1 10 11 X0 1X
0 11 11 X0 X0
1 11 00 X1 X1

K MAP

The flip-flop input functions are derived:

J0 = Q1 * x' K 0 = Q1 * x
J1 = x K1 = Q0' * x' + Q0 * x = Q0 x
Note: the symbol is exclusive-NOR.

Circuit diagram:

Page 15 of 34
 Module 5

Problem 5:
Design a counter that has an Enable input When Enable=1 it increments through the
sequence 0,1,2,3,0,1,… with each clock tick. Enable=0 causes the counter to remain
in its current state.

1. First we create a state table and state diagram:

Next
Present Enable=0 Enable=0
n n n

Page 16 of 34
 Module 5

0 0 1
1 1 2
2 2 3
3 3 0

At each clock tick the counter increments by one if Enable=1. If Enable=0 it

remains in the current state. We have only shown the inputs because the
output is equal to the state.

2. A reasonable choice is to use the binary numbering system for each state.
With four states we need two bits. We will let n=n1n0, giving the state table:

Next
Present Enable=0 Enable=1
n1 n0 n1 n0 n1 n0
0 0 0 0 0 1
0 1 0 1 1 0
1 0 1 0 1 1
1 1 1 1 0 0

3. JK flip-flops excitation table

4. We need two flip-flops, one for each bit.

Enable Present Next Output

E Q1 Q0 Q1+1 Q0+1 J1 K1 J0 K0
0 0 0 0 0 0 X 0 X

Page 17 of 34
 Module 5

0 0 1 0 1 0 X X 0
0 1 0 1 0 X 0 0 X
0 1 1 1 1 X 0 X 0
1 0 0 0 1 0 X 1 X
1 0 1 1 0 1 X X 1
1 1 0 1 1 X 0 1 X
1 1 1 0 0 X 1 X 1

J0(E,n1,n0) = ∑m(5,6) + ∑d(1,3,5,7)

J1(E,n1,n0) = ∑m(5) + ∑d(2,3,6,7)

k0(E,n1,n0) = ∑m(5,7) + ∑d(0,2,4,6)

k1(E,n1,n0) = ∑m(7) + ∑d(0,1,4,5)

5. Karnaugh maps, using E for Enable.

This yields the functions:

J0(E,n1,n0)=E
K0(E,n1,n0)=E
Page 18 of 34
 Module 5

J1(E,n1,n0)=E⋅n0
K1(E,n1,n0)=E⋅n0
6. The circuit to implement this counter is:

STATE REDUCTION TECHNIQUE

Two methods:
1, Row Elimination Method
2. Implication method

Row Elimination Method:

• In this method, we first prepare a state table where at any given state the next
state and present output(s) are written for each combination of input(s).
• In the present problem there are only two possible values of input X = 0 and X
= I.

Page 19 of 34
 Module 5

• For 2 input circuits there will be 22 = 4 such combinations in this table.

• Now, two states are considered equivalent if they move to same or equivalent
state for every input combination and also generate same output.

Example 1:

Page 20 of 34
 Module 5

Example 2:

Consider the state table of a sequential circuit shown, Reduce the number
of states using row elimination Method

Present State Next State Output

Page 21 of 34
 Module 5

x=0 x=1 x=0 x=1

A B C 1 0
B F D 0 0
C D E 1 1
D F E 0 1
E A D 0 0
F B C 1 0

Step 1:

• It can be seen from the table that the present state A and F both
have the same next states, B (when x=0) and C (when x=1).
• Therefore, states A and F are equivalent.
• Thus, one of the states, A or F can be removed from the state table.
• We are removing F
• Replace F with A in the table

Output
Next State
Present State
x=0 x=1 x=0 x=1

A B C 1 0
B A D 0 0
C D E 1 1
D A E 0 1
E A D 0 0

Step 2:

• It is apparent that states B and E are equivalent.

• Removing E and replacing E's by B's results in the reduce table
below

Page 22 of 34
 Module 5

Output
Next State
Present State
x=0 x=1 x=0 x=1

A B C 1 0
B A D 0 0
C D B 1 1
D A B 0 1

• The removal of equivalent states has reduced the number of states in

the circuit from six to four.
• Two states are considered to be equivalent if and only if for every
input sequence the circuit produces the same output sequence
irrespective of which one of the two states is the starting state.

Example 3: State Reduction

Step 1:
• State e and g are equivalent.
• Remove state g.
• Replace g with e
Page 23 of 34
 Module 5

NS Output
PS
X=0 X=1 X=0 X=1
A a b 0 0
B c d 0 0
C a d 0 0
D e f 0 1
E a f 0 1
F e f 0 1
Step 2:
• State d and f are equivalent.
• Remove state f.
• Replace f with d

NS Output
PS
X=0 X=1 X=0 X=1
A a b 0 0
B c d 0 0
C a d 0 0
D e d 0 1
E a d 0 1

Example 4:

Page 24 of 34
 Module 5

Step 1:
• State d and e are equivalent.
• Remove state e.
• Replace e with d

NS Output
PS
X=0 X=1 X=0 X=1
a d b 0 0
b d a 0 0
c g f 0 1
d a d 1 0
f c b 0 0
g a d 1 0

Step 2:
• State d and g are equivalent.
• Remove state g.
• Replace g with d

Page 25 of 34
 Module 5

NS Output
PS
X=0 X=1 X=0 X=1
a d b 0 0
b d a 0 0
c d f 0 1
d a d 1 0
f c b 0 0

Implication Table Method

• Implication table provides a more systematic approach towards solution of a
complex state reduction problem.
• For n states in the initial description, we have n-l rows in implication table and
as many numbers of columns.
• The cross-point in an implication table is the location where a row and a
column meet.
• The conditions for equivalence between the states crossing each other are
tested.
• In Step 1, identify the states, which cannot be equivalent, as their outputs do
not match. This is denoted by putting a double-cross in respective cross points.
• In Step 2, for other cross points, we write necessary conditions for equivalence
of intersecting states.
• In Step 3, we use relationships obtained in Steps 1 and 2, especially the ones
represented by double cross and double tick mark and check if any other cross
points can be crossed or ticked.

Page 26 of 34
 Module 5

• In Step 4, we keep repeating Step 3 and cross or tick (if possible) as many
cross points in the implication table as possible.
• In Step 5, we check pair-wise equivalence starting from rightmost column e of
implication table.

Page 27 of 34
 Module 5

Row Elimination VS Implication Method

Row Elimination Implication

Simplifies the state transition table Determines if two states can be
by removing redundant states. merged based on their behavior.
Involves removing rows from the Uses implications to check if one
state transition table that state can lead to another under all
represent equivalent states. input conditions.
Identify and eliminate rows that Analyse pairs of states to see if
have identical outputs for all they behave the same for all
inputs. possible inputs.
Generally simpler and more Can be more complex, requiring a
straightforward, focusing on direct deeper analysis of state behaviour
comparisons. and transitions.

Page 28 of 34
 Module 5

Identifies pairs of states that can

Produces a reduced state
be merged, leading to a minimized
transition table with fewer states.
state machine.
Often used in conjunction with
Useful in the initial stages of state
other minimization techniques for
minimization.
thorough analysis.

Verilog Code:
Sequence detector to detect sequence as 1100 using Moore model
Verilog code

Present Next State Output

State X=0 X=1 Y
A A B 0
B A C 0
C D C 0
D E B 0
E A B 1

module MOORE12(clk, x, rst, y); // 1100 SEQUENCE FOR

MOORE
input clk;
input x;
input rst;
output reg y =0; //CRT_STATE A -> B NXT_STATE

parameter A= 3'b 000, B= 3'b 001, C= 3'b 010, D= 3'b 011, E= 3'b
100;

reg [2:0] crt_state;

reg [2:0] nxt_state;

always @ (negedge clk, negedge rst)

begin
if(rst==1)
crt_state <= A;

else
Page 29 of 34
 Module 5

crt_state <= nxt_state;

end
always@( x, crt_state)

case(crt_state)

A: begin
y=0;
if(x==0)
nxt_state <=A;
else
nxt_state <= B;
end

B: begin
y=0;
if(x==0)
nxt_state <=A;
else
nxt_state <= C;
end

C: begin
y=0;
if(x==0)
nxt_state <=D;
else
nxt_state <= C;
end

D: begin
y=0;
if(x==0)
nxt_state <=E;
else
nxt_state <= B;
end

E: begin
y=1;
if(x==0)
Page 30 of 34
 Module 5

nxt_state <=A;
else
nxt_state <= B;
end

default: nxt_state <=A;

endcase

endmodule

Test Bench:
initial begin
// Initialize Inputs
clk = 0;
x = 0;
rst = 1;

#100;
rst =0;

#50; x=1; #50; x=1; #50; x=0; #50; x=0;

#50; x=0; #50; x=0; #50; x=1; #50; x=1;
#50; x=1; #50; x=1; #50; x=0; #50; x=0;
#50; x=0; #50; x=1; #50; x=0; #50; x=0;
#50; x=1; #50; x=1; #50; x=0; #50; x=0;

end

always #25 clk = ~ clk;

endmodule

Page 31 of 34
 Module 5

Sequence detector to detect sequence as 0011 using Mealy model

Verilog code

module Mealy12(clk, x, rst, y); // 0011 SEQUENCE FOR MEALY

input clk;
input x;
input rst;
output reg y =0; //CRT_STATE A -> B NXT_STATE

parameter A= 2'b 00, B= 2'b 01, C= 2'b 10, D= 2'b 11;

reg [1:0] crt_state;

reg [1:0] nxt_state;

always @ (negedge clk, negedge rst)

begin
if(rst==1)
crt_state <= A;

else
crt_state <= nxt_state;

end

always@( x, crt_state)

case(crt_state)

A: begin
y=0;
if(x==0)
nxt_state <=B;

else
nxt_state <= A;

end

B: begin
y=0;
Page 32 of 34
 Module 5

if(x==0)
nxt_state <=C;
else
nxt_state <= A;
end

C: begin
y=0;
if(x==0)
nxt_state <=C;
else
nxt_state <= D;
end

D: begin

if(x==0)
begin
nxt_state <=B;
y=0;
end
else
begin
nxt_state <= A;
y=1;
end
end

default: nxt_state <=A;

endcase

endmodule

initial begin
// Initialize Inputs
clk = 0;
x = 0;
rst = 1;

#100;
rst =0;
Page 33 of 34
 Module 5

#50; x=0; #50; x=1; #50; x=1; #50; x=1;

#50; x=0; #50; x=0; #50; x=1; #50; x=1;
#50; x=1; #50; x=1; #50; x=0; #50; x=0;
#50; x=0; #50; x=0; #50; x=1; #50; x=1;
#50; x=1; #50; x=1; #50; x=0; #50; x=0;

end

always #25 clk = ~ clk;

endmodule

Page 34 of 34