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4 Dram

Memory Design and testing lecture 4

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3 views14 pages

4 Dram

Memory Design and testing lecture 4

Uploaded by

pluscommander972
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EEE 497:

VLSI Technology and System


Design
Memory-II:
Dynamic Random Access
Memory
Dr. Pooran Singh
Dept. of Electrical & Electronics Engineering (EEE)
Ecole Centrale School of Engineering,
1
Mahindra University
Read-Write Memories (RAM)
❑ STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential

❑ DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
2
IT DRAM cell

Only one transistor: Very high density


3
Hold operations in a DRAM cell
BL is precharged to VDD/2

BL

Logic (1): Charge stored in the capacitor and VS = QsCs

Logic (0): No-charge stored in the capacitor and VS = 0


4
Hold operations: Charge leakage

VS

Assuming a constant leakage current = IL


Retention time or hold time = th = (CS/IL)VS)

The memory need to be refreshed periodically


while storing the data
5
1-Transistor DRAM Cell
BL BL
WL WL

M1 M1
CS CS

CBL CBL

Write ‘1’: VBL = VDD Write ‘0’: VBL = 0


Cs is charged through M1 Cs is dis-charged through M1
Vs = (VWL – VthM1) = VDD - Vth Vs = 0
Boosting the WL can help
6
1-T DRAM Read Operation
VBL
BL
WL

VPRE
M1
CS

V(0)
CBL
Sense amp activated t
Word line activated

Read ‘0’:
VS = VBIT = 0 < VBL = V PRE Bit-lines are precharged to VPRE
Charge from CBL goes to CS
Often VPRE = VDD/2
7
1-T DRAM Read Operation
VBL V(1)
BL
WL

VPRE
M1 DV(1)
CS

V(0)
CBL
Sense amp activated t
Word line activated

Read ‘1’:
VS = V BIT = VDD > VBL = V PRE Bit-lines are precharged to VPRE
Charge from CS goes to CBL
Often VPRE = VDD/2
8
1-T DRAM Read Operation
BL
WL Bit-lines are precharged to VPRE
VPRE = VDD/2, Cell voltage = VS=VBIT
M1
CS V = VBL − VPRE
CSVBIT + CBLVPRE = VBL (CS + CBL )
CSVBIT + CBLVPRE
CBL =VBL =
CS + C BL
CSVBIT +CBLVPRE
charge before read operation = V = −VPRE
CS + C BL
Q = CSVBIT + CBLVPRE
CS
charge after read operation
= V = (VBIT −VPRE )
Q = CSVBL + CBLVBL CS + C BL
Voltage change at bit line
10
= V = VBL-VPRE
1-T DRAM Read Operation
Read '0' :VBIT = 0 = V = −0.5VDD CS (CS + CBL )
Read '1' :VBIT = VWL −Vth = VDD (assuming boosted WL)
= V = 0.5VDD CS (CS + CBL )
CS
= charge transfer ratio~1-10%
CS + CBL

Sense amplifier is a must for every bitline


for correct functionality

10
What happens to cell voltage?
VCELL = VBL −VBIT
CSVBIT + CBLVPRE
CSVBIT +C V = VBL (CS + C BL ) =VBL =
CS + C BL
BL PRE

CSVBIT + CBLVPRE CBL


= VCELL = −VBIT = (VPRE −VBIT )
CS + C BL CS + C BL

Cell voltage for bit storing ‘1’ reduces from VBIT = VWL-Vth
Cell voltage for bit storing ‘0’ increases from VBIT = 0

Read operation destroy the cell data


=> destructive read
11
What happens to cell voltage?

After reading original value


has to be restored.

Normally, after reading the


sense-amplifier output is
applied back to the BL and
WL is kept on.

=> Read and restore

12
DRAM Cell Observations
❑1T DRAM requires a sense amplifier for each bit line,
due to charge redistribution read-out.
❑DRAM memory cells are single ended in contrast to
SRAM cells.
❑The read-out of the 1T DRAM cell is destructive; read
and refresh operations are necessary for correct
operation.
❑1T DRAM cell requires presence of an extra capacitance
that must be explicitly included in the design.
❑When writing a “1” into a DRAM cell, a threshold voltage
is lost. This charge loss can be circumvented by
bootstrapping the word lines to a higher value than VDD
13
DRAM Sensing: Single Ended Sensing
V
VPRE DD

M M
PRE 2 4

Bus Out

C
C out
bus
M M
WL0 1 WL1 3

CS CS Inverter with trip


point ~ VPRE

Susceptible to noise at the bitline


16

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