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    21ECT701 Advance VLSI Revised Model QP

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    21ECT701 Advance VLSI Revised Model QP

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    suprithsuppi336
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    Vlsi important questions

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    Vlsi important questions

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    8 views3 pages

    21ECT701 Advance VLSI Revised Model QP

    Uploaded by

    suprithsuppi336
    Vlsi important questions

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 3

    (Page 1 of 2)

    21ECT701

    Dr. Ambedkar Institute of Technology

    Advanced VLSI
    (Model Paper)
    Time: 3 Hours Maximum Marks: 100

    Marks CO RBT
    level

    1. a. Analyze the working of CMOS SR latch circuit based on NOR gates 10 M CO1 L2
    b. Implement F = (A+BC)’ using Dynamic CMOS logic and explain its 10 M CO1 L3
    important characteristics.
    OR
    2. a. Describe the static behavior of the BiCMOS inverter. 10 M CO1 L2
    b. Explain the working of CMOS AOI realization of the JK Latch 10 M CO1 L2

    3. a. With neat block diagram and logical expressions illustrate addition 10 M CO2 L2
    with carry generation and propagation logic
    b. Describe with block diagram and expression the working principle of 10 M CO2 L2
    2’s complement multiplication.
    OR
    4. a. Describe the carry select adder with neat block diagram and logical 10 M CO2 L2
    expressions.

    b. Draw the flow chart of the ASIC design flow and explain the 10 M CO2 L3
    importance of each step.

    5. a. Compute the shortest path weights of the graph using Belman-Ford 10 M CO3 L2
    algorithm.

    Fig. 5a

    Dr. Ambedkar Institute of Technology, Bangalore – 560056


    (An Autonomous Institution Affiliated to Visvesvaraya Technological University, Belgaum)
    (Page 2 of 2)

    b. Consider the function f = ab + bc +ac. Compute ∂ f /∂ b, Cb(f) and 10 M CO3 L2


    Sb(f). Represent the function, Boolean difference, consensus and
    smoothing on the 3 dimension Boolean cube.
    OR
    6. a. Compute the shortest path weights of the graph shown in figure 6a by 10 M CO3 L3
    using Dijkstra Algorithm. Show all steps in brief. Indicate the shortest
    path on the graph

    Figure 6a.
    b. Given f = (a+b)c; g= bcd. For this pair, write the following diagrams 10 M CO3 L3
    i. ROBDD for the function f= (a+b)c with the variable order (a,b,c)
    ii. ROBDD for the function pair with the variable order (d,a,b,c)
    iii. Unique table for the ROBDD obtained in 2.

    7. a. Write a note on HDLS used for synthesis 10 M CO4 L2


    b. Explain the following with example i) Parse tree ii) Tree height 10 M CO4 L2
    reduction iii) Constant and variable propagation iv) Operator strength
    reduction.
    OR
    8. a. Write the VHDL and Verilog behavioral model of the circuit 10 M CO4 L2
    integrating a differential equation y ' ' +3 xy ' + y ' =0
    in the interval [0 , 0] with stepsize dx and initial values x ( 0 )=x ,
    y ( 0 )= y, y ' ( 0 )=u
    b. Draw the sequential graph for the model shown below 10 M CO4 L3
    x 1=x+ dx ;
    u 1=u−( 3∗x∗u∗dx )−( 3∗y∗dx ) ;
    y 1= y + x∗dx ;
    c=x 1<a ;

    9. a Describe the goals and objectives of Floor planning and placement in 10 M CO5 L2
    IC manufacturing.

    b. Illustrate min-cut placement algorithm. 10 M CO5 L2


    OR

    Dr. Ambedkar Institute of Technology, Bangalore – 560056


    (An Autonomous Institution Affiliated to Visvesvaraya Technological University, Belgaum)
    (Page 3 of 2)

    10 a. Describe the basic global routing methods involved in integrated 10 M CO5 L2


    . circuits.
    b. Briefly describe the iterative placement improvement methods used in 10 M CO5 L2
    the industry.

    Dr. Ambedkar Institute of Technology, Bangalore – 560056


    (An Autonomous Institution Affiliated to Visvesvaraya Technological University, Belgaum)

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