Scribd
Upload
6 views

Verrilog Programs 1

Uploaded by

Ram prasath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
6 views

Verrilog Programs 1

Uploaded by

Ram prasath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

1. Verilog code for full adder.

A full adder is a combinational circuit that takes three input a, b, c and generate output as
sum and carry. The full adder adds the three input producing two outputs sum and carry.
Let us say that the three input to the full adder are A,B,C then logical Expression for Sum
will be (A) xor (B) xor (C) . And the logical expression for carry will be AB+BC+AC.

Truth Table for Full adder


A B C sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Block diagram:

1|P ag e
Verilog code:

Behavioural Modeling Structural Modeling Dataflow Modeling


module full_adder (a,b,c,sum,cout); module full_adder (a,b,c,sum,cout); module full_adder (a,b,c,sum,cout);
input a,b,c; input a,b,c; input a,b,c;
output reg sum,cout; output reg sum,cout; output reg sum,cout;
wire w1,c1,c2,c3,out1; assign sum = (a ^ b ^ c );
always @(*) xor x1(w1,a,b); assign cout = (a & b ) |
begin xor x2(sum,w1,c); (b & c) | (a & c);
case ({a,b,c}) endmodule
3'b000: sum = 0; and a1(c1,a,b);
3'b001: sum = 1; and a2(c2,b,c);
3'b010: sum = 1; and a3(c3,a,c);
3'b011: sum = 0;
3'b100: sum = 1; or o1(out1,c1,c2);
3'b101: sum = 0; or o2(cout,out1,c3);
3'b110: sum = 0;
3'b111: sum = 1; endmodule
default : sum = 0;
endcase

case ({a,b,c})
3'b000: cout = 0;
3'b001: cout = 0;
3'b010: cout = 0;
3'b011: cout = 1;
3'b100: cout = 0;
3'b101: cout = 1;
3'b110: cout = 1;
3'b111: cout = 1;
default : cout = 0;
endcase
end
endmodule

2|P ag e
2. Verilog code for Ripple carry adder.

Structural Modeling Dataflow Modeling


module fulladder(X, Y, Ci, S, Co); module RCA(X, Y, Ci, S,
input X, Y, Ci; Co);
output S, Co; input [3:0] X, Y;
wire w1,w2,w3; input Ci;
xor G1(w1, X, Y); output [3:0] S;
xor G2(S, w1, Ci); output Co;
and G3(w2, w1, Ci); assign {Co, S} = X+Y+Ci;
and G4(w3, X, Y);
or G5(Co, w2, w3); endmodule
endmodule

module RCA(X, Y, Ci, S, Co);


input [3:0] X, Y;
input Ci;
output [3:0] S;
output Co;
wire w1, w2, w3;
fulladder u1(X[0], Y[0], Ci, S[0],w1);
fulladder u2(X[1], Y[1], w1, S[1], w2);
fulladder u3(X[2], Y[2], w2, S[2], w3);
fulladder u4(X[3], Y[3], w3, S[3], Co);
endmodule

3|P ag e
3. Verilog code for 8:1 Multiplexer

Behavioural Modeling Structural Modeling Dataflow Modeling


module module _8_1mux(d,s,y); module m81(output
out, input D0, D1, D2, D3, D4, D5,
_8_1_MUX_bm(d,s2,s1,s0,out input [7:0]d;
D6, D7, S0, S1, S2);
); input [2:0]s;
input [7:0]d; output y; assign S1bar=~S1;
input s2,s1,s0; wire [10:0]w; assign S0bar=~S0;
assign S2bar=~S2;
output reg out; not g1(w[0],s[0]);
always @ (d or s2 or s1 or s0) not g2(w[1],s[1]); assign out = (D0 & S2bar & S1bar &
case ({s2,s1,s0}) not g3(w[2],s[2]); S0bar) | (D1 & S2bar & S1bar & S0)
0 : out = d[0]; and g4(w[3],d[0],w[2],w[1],w[0]); | (D2 & S2bar & S1 & S0bar) | (D3
1 : out = d[1]; and g5(w[4],d[1],w[2],w[1],s[0]); & S2bar & S1 & S0) | (D4 & S2 &
S1bar & S0bar) | (D5 & S2 & S1bar
2 : out = d[2]; and g6(w[5],d[2],w[2],s[1],w[0]); & S0) | (D6 & S2 & S1 & S0bar) |
3 : out = d[3]; and g7(w[6],d[3],w[2],s[1],s[0]); (D7 & S2 & S1 & S0);
4 : out = d[4]; and g8(w[7],d[4],s[2],w[1],w[0]);
5 : out = d[5]; and g9(w[8],d[5],s[2],w[1],s[0]); endmodule
6 : out = d[6]; and g10(w[9],d[6],s[2],s[1],w[0]);
7 : out = d[7]; and g11(w[10],d[7],s[2],s[1],s[0]);
default : out = 1'bx; or g12(y, w[3], w[4], w[5], w[6], w[7],
endcase w[8], w[9], w[10]);
endmodule endmodule

4|P ag e
4. Verilog code for 2 bit magnitude comparator
Behavioural Modeling Structural Modeling Dataflow Modeling
module comp2bit(G,L,E,a,b); module module comparator_2bit ( a ,b ,equal
comparator_2bit_gatelevel(G,E,L,a,b) ,greater ,lower);
input a,b;
output G,L,E; output G,E,L; output equal ;
always @ (a or b) input [1:0]a,b; output greater ;
begin output lower ;
wire a1bar,a0bar,b1bar,b0bar;
if(a>b)
wire input [1:0] a ;
G=1,L=0, E=0; w1,w2,w3,w4,w5,w6,w7,w8,w9,w10; input [1:0] b ;
elseif(a<b) not n1(a1bar,a[1]);
G=0,L=1,E=0; not n2(a0bar,a[0]); assign equal = (a==b) ? 1 : 0;
else not n3(b1bar,b[1]); assign greater = (a>b) ? 1 : 0;
not n4(b0bar,b[0]); assign lower = (a<b) ? 1 : 0;
G=0,L=0,E=1;
endmodule and x1(w1,a[1],b1bar); endmodule
and x2(w2,a[1],a[0],b0bar);
and x3(w3,a[0],b1bar,b0bar);
and x4(w4,a1bar,a0bar,b1bar,b0bar);
and x5(w5,a1bar,a[0],b1bar,b[0]);
and x6(w6,a[1],a0bar,b[1],b0bar);
and x7(w7,a[1],a[0],b[1],b[0]);
and x8(w8,a1bar,b[1]);
and x9(w9,a1bar,a0bar,b[0]);
and x10(w10,a0bar,b[1],b[0]);

or x11(G,w1,w2,w3);
or x12(E,w4,w5,w6,w7);
or x13(L,w8,w9,w10);
endmodule;

5|P ag e

You might also like