AN976

Using the MSSP Module to Interface I2C™ Serial EEPROMs with PIC16 Devices

This application note is intended to serve as a

Author: Chris Parris reference for communicating with Microchip’s 24XXX
Microchip Technology Inc. series serial EEPROM devices with the use of the
MSSP module featured on many PIC16 family devices.
Source code for common data transfer modes is also
INTRODUCTION provided.

The 24XXX series serial EEPROMs from Microchip Figure 1 describes the hardware schematic for the
Technology are I2C™ compatible and have maximum interface between Microchip’s 24XXX series devices
clock frequencies ranging from 100 kHz to 1 MHz. The and the PIC16F877A PICmicro microcontroller. The
MSSP module available on many PICmicro® microcon- schematic shows the connections necessary between
trollers provides a very easy-to-use interface for the microcontroller and the serial EEPROM as tested,
communicating with the 24XXX series devices. The and the software was written assuming these connec-
largest benefit of using the MSSP module is that the tions. The SDA and SCL pins are open-drain terminals,
signal timings are handled through hardware rather and therefore require pull-up resistors to VCC (typically
than software. This allows the firmware to continue 10 kΩ for 100 kHz, and 2 kΩ for 400 kHz and 1 MHz).
executing while communication is handled in the back- Also, the WP pin is tied to ground because the write-
ground. This also means that an understanding of the protect feature is not used in the examples provided.
timing specifications associated with the I2C protocol is
not required in order to use the 24XXX series devices
in designs.

FIGURE 1: CIRCUIT FOR PIC16F877A AND 24XXX SERIES DEVICE

PDIP (600 MIL) MCLR 1 40 RB7
RA0 2 39 RB6
RA1 3 38 RB5
RA2 4 37 RB4
RA3 5 36 RB3
RA4 6 35 RB2
RA5 7 34 RB1
PIC16F877A

RE0 8 33 RB0
RE1 9 32 VDD
RE2 10 31 VSS
VDD 11 30 RD7
VSS 12 29 RD6
OSC1 13 28 RD5
OSC2 14 27 RD4
RC0 15 26 RC7
RC1 16 25 RC6
RC2 17 24 RC5
RC3/SCL 18 23 RC4/SDA
RD0 19 22 RD3
RD1 20 21 RD2

Vcc

A0 1 8 Vcc
24XXXXX

A1 2 7 WP 4.7K 4.7K
A2 3 6 SCL

Vss 4 5 SDA

*SDA and SCL require pull-up resistors (10 kΩ for 100 kHz, 2 kΩ for 400 kHz and 1 MHz).
Note that pins A0, A1 and A2 are not internally connected in some devices.

© 2005 Microchip Technology Inc. DS00976A-page 1

AN976
FIRMWARE DESCRIPTION
The purpose of the firmware is to show how to generate
specific I2C transactions using the MSSP module on a
PICmicro microcontroller. The configuration required
for I2C Master mode will be explained, as well as some
of the specific details of the I2C protocol. The focus is
to provide the designer with a strong understanding of
communication with the 24XXX series serial
EEPROMs using the MSSP module and I2C, thus
allowing for more complex programs to be written in the
future.
The firmware consists of a single assembly program,
organized into five sections:
- Initialization
- Byte Write
- Byte Read
- Page Write
- Sequential Read
The program also exhibits the Acknowledge polling
feature for detecting the completion of write cycles after
the byte write and page write operations. Read opera-
tions are located directly after each write operation,
thus allowing for verification that the data was properly
written. No method of displaying the input data is
provided, but an oscilloscope or a Microchip MPLAB®
ICD 2 could be used.
The code was tested using the 24LC256 serial
EEPROM. This device features 32K x 8 (256 Kbit) of
memory and 64-byte pages. The 24LC256 also
features a configurable, 3-bit address via the A2, A1
and A0 pins. For testing, these pins were all grounded
for an address of ‘000’. Oscilloscope screen shots are
labeled for ease in reading. The data sheet version of
the waveforms are shown below the oscilloscope
screen shots. All timings are designed to meet the 100
kHz specs, and a 10 MHz crystal oscillator is used to
clock the PIC16F877A. If a faster clock is used, the
code must be modified for the MSSP module to gener-
ate the correct clock frequency. All values represented
in this application note are hex values unless otherwise
noted.

DS00976A-page 2 © 2005 Microchip Technology Inc.

 AN976
INITIALIZATION
In order to configure the MSSP module for I2C Master SSP Control Register (SSPCON)
mode, several key registers on the PICmicro microcon-
troller need to be properly initialized. Code examples SSPCON is one of the Configuration registers for the
are shown for each. MSSP module. In I2C Master mode, the upper two bits
of SSPCON are indicator bits and should be cleared
initially. Also while in Master mode, the SCL Release
SSP Status Register (SSPSTAT)
Control bit (CKP) is not used. The SSP Enable bit
SSPSTAT holds all of the Status bits associated with (SSPEN) must be set in order to enable the serial port.
the MSSP module. In I2C mode, this includes indicators The mode is set using the SSPM3:SSPM0 bits, which
for Start/Stop bit detection, R/W information, etc. It also need to be ‘1000’ for I2C Master mode. This register is
contains the Slew Rate Control bit (SMP) and the configured using the code shown in Example 3.
SMBus Select bit (CKE). The source code provided
uses a 100 kHz clock for I2C, so the slew rate control is EXAMPLE 3: SSPCON CONFIGURATION
not used. Therefore, set the SMP bit to disable slew
rate control. Also, SMBus specific inputs are not being BANKSEL SSPCON ; Select bank 00
used, so clear the CKE bit to disable them. This is done MOVLW b’00101000’ ; Load WREG with
as shown in Example 1. ; 0x28
MOVWF SSPCON ; Copy value to
EXAMPLE 1: SSPSTAT CONFIGURATION ; SSPCON

BANKSEL SSPSTAT ; Select bank 01

CLRF SSPSTAT ; Disable SMBus SSP Control Register 2 (SSPCON2)
; inputs
BSF SSPSTAT,SMP ; Disable slew SSPCON2 is the other Configuration register used for
; rate control the MSSP module, and contains all of the sequence
enable bits. These bits are used to initiate the different
sequences associated with I2C operations. For exam-
ple, to generate a Start condition, the Start Condition
SSP Address Register (SSPADD)
Enable bit (SEN) is set. All of the SSPCON2 register
In I2C Master mode, SSPADD acts as the baud rate bits are cleared at POR, but not after other Resets.
generator reload value. Equation 1 shows how to cal- Therefore, it is good practice to clear the SSPCON2
culate the value for SSPADD, based on a desired bit register during the initialization routine, as in
rate and a known FOSC. In testing the example code Example 4.
provided, a 10 MHz crystal oscillator was used, and the
target bit rate was 100 kHz. Therefore, SSPADD EXAMPLE 4: SSPCON2 CONFIGURATION
needed to be set to 0x18. Example 2 shows how to do
this in code. BANKSEL SSPCON2 ; Select bank 01
CLRF SSPCON2 ; Clear control
EQUATION 1: SSPADD CALCULATION ; bits

F OSC ⎞
⎛ ------------------- Note that all of the examples shown in this section
-
⎝ BitRate⎠ make use of the BANKSEL directive, but SSPSTAT,
SSPADD = ------------------------- – 1 SSPADD and SSPCON2 all exist on Bank 1. There-
4 fore, it is more efficient to configure all of these regis-
ters together, so that only one BANKSEL directive is
required.
EXAMPLE 2: SSPADD CONFIGURATION

BANKSEL SSPADD ; Select bank 01

MOVLW 0x18 ; Load WREG with
; 0x18
MOVWF SSPADD ; Copy value to
; SSPADD

© 2005 Microchip Technology Inc. DS00976A-page 3

AN976
BYTE WRITE SEN bit (SSPCON2<0>). Before continuing with the
I2C operation, the PICmicro microcontroller must wait
The Byte Write operation has been broken down into for the SSPIF bit to be set by hardware, thus indicating
the following components: the Start condition and that the Start condition has been successfully
control byte, the word address, and the data byte and generated.
Stop condition. Note that, due to the size of the
After the Start bit has been sent, the control byte can be
24LC256, two bytes are used for the word address.
transmitted. To do so, first clear the SSPIF flag again,
However, some 24XXX series devices use only a
then simply write the control byte to SSPBUF. The
single byte for the word address.
MSSP module will automatically begin transferring the
All I2C commands must begin with a Start condition. data to the EEPROM device. The module will also
This consists of a high-to-low transition of the SDA line detect whether or not the device responded with an
while the clock (SCL) is high. After the Start condition, ACK bit, and will set the ACKSTAT bit (SSPCON2<6>)
the 8 bits of the control byte are clocked out, with data accordingly. Again, the PICmicro microcontroller must
being latched in on the rising edge of SCL. The device wait until the SSPIF bit has been set, indicating that the
code (0xA for the 24LC256), the block address (3 bits), MSSP module has finished, before continuing.
and the R/W bit make up the control byte. Next, the
EEPROM device must respond with an Acknowledge Start Bit and Control Byte Transmission
bit by pulling the SDA line low for the ninth clock cycle.
Before initiating the Start condition, the SSP Interrupt Figure 2 shows the details of the Start condition and the
Flag (SSPIF, PIR1<3>) must be cleared. Once this is control byte. The left marker shows the position of the
done, the Start condition can be initiated by setting the Start bit, whereas the right marker shows the ACK bit.

FIGURE 2: START BIT AND CONTROL BYTE

S
BUS ACTIVITY T
MASTER Control
A
R Byte
T
SDA LINE S1 0 1 0A AA
2 10 0
A
BUS ACTIVITY C
K

DS00976A-page 4 © 2005 Microchip Technology Inc.

 AN976
Sending the Word Address Figure 3 shows the two address bytes and correspond-
ing ACK bits. For reference, the previous ACK bit (in
After the EEPROM device has acknowledged receipt response to the control byte) is shown by the left
of the control byte, the master (PIC16F877A) begins marker. Note that the word address chosen for this
to transmit the word address. For the 24LC256, this application note is 0x5AA5.
is a 15-bit value, so two bytes must be transmitted for
the entire word address (the MSb of the high byte is
a “don’t care”), with the Most Significant Byte sent
first (note that some 24XXX series devices only use
a 1-byte word address). These bytes can be sent via
the MSSP module using the same method described
above for the control byte. After each byte of the word
address has been transmitted, the device must
respond with an Acknowledge bit.

FIGURE 3: WORD ADDRESS

BUS ACTIVITY
MASTER Address Address
High Byte Low Byte

SDA LINE x

A A
BUS ACTIVITY C C
K K
x = “don’t care” bit

© 2005 Microchip Technology Inc. DS00976A-page 5

AN976
Data Byte and Stop Bit Transmission PEN bit (SSPCON2<2>) is used for the Stop condition.
As with the Start condition, the PICmicro microcontrol-
Once the word address has been transmitted and the ler first clears the SSPIF bit, sets the PEN bit and then
last ACK bit has been received, the data byte can be waits for the SSPIF bit to be set by hardware.
sent. Once again, the EEPROM device must respond
with another ACK bit. After this has been received, the Figure 4 shows the transmission of the data byte, as
master generates a Stop condition. This consists of a well as the Stop condition indicating the end of the
low-to-high transition of SDA while the clock (SCL) is operation. Again, the left marker shows the previous
high. Initiating a Stop condition using the MSSP module ACK bit (that of the word address). The right marker
is similar to initiating a Start condition, except that the denotes the Stop condition.

FIGURE 4: DATA BYTE AND STOP BIT

BUS ACTIVITY S
MASTER T
Data O
P

SDA LINE P

A
C
BUS ACTIVITY K

DS00976A-page 6 © 2005 Microchip Technology Inc.

 AN976
ACKNOWLEDGE POLLING
The data sheets for the 24XXX series devices specify Acknowledge Polling Routine
a write cycle time (TWC), but the full time listed is not
always required. Because of this, using a measured The process of acknowledge polling consists of send-
write cycle delay is not always accurate, which leads to ing a Start condition and then a Write command to the
wasted time. Therefore, in order to transfer data as effi- EEPROM device, then simply checking to see if the
ciently as possible, it is highly recommended to use the ACK bit was received, via the ACKSTAT bit. If it was not
Acknowledge Polling feature. Since the 24XXX series received (i.e., if ACKSTAT is high), then the device is
devices will not acknowledge during a write cycle, the still performing its write cycle.
device can continuously be polled until an Acknowl- Figure 5 shows an example of acknowledge polling to
edge is received. This is done after the Stop condition check if a write operation has finished. In this example,
takes place to initiate the internal write cycle of the the device did not acknowledge the poll (the ACK bit is
device. high), which indicates that the write cycle has not yet
completed.

FIGURE 5: ACKNOWLEDGE POLLING ROUTINE (SHOWING NO ACK BIT)

BUS ACTIVITY S
T Control
MASTER A
R Byte
T
SDA LINE S1 0 1 0A AA
2 10 0
N
BUS ACTIVITY O
A
C
K

© 2005 Microchip Technology Inc. DS00976A-page 7

AN976
Response to Acknowledge Polling
Figure 6 shows the final acknowledge poll after a write
operation, in which the device responds with an ACK
bit, indicating that the write cycle has completed and
the device is ready to continue.

FIGURE 6: ACKNOWLEDGE POLLING FINISHED (SHOWING ACK BIT)

S
BUS ACTIVITY T
MASTER Control
A
R Byte
T
SDA LINE S1 0 1 0A AA
2 10 0
A
BUS ACTIVITY C
K

DS00976A-page 8 © 2005 Microchip Technology Inc.

 AN976
BYTE READ
In order to read data from the 24XXX series devices in Using the MSSP module, transmitting the first control
a random access manner, the byte read operation can byte and the word address is done in the same fashion
be used. It is similar to the byte write operation, but as for a byte write.
slightly more complex. The word address must still be
transmitted, and to do this, a control byte with the R/W Writing Word Address for Read
bit set low must be sent first. However, this conflicts
with the desired operation, that is, to read data. There- Figure 7 shows an example of the first control byte and
fore, after the word address has been sent, a new Start the word address of a byte read operation. The left
condition and a control byte with R/W set high must be marker indicates the Start bit and the right marker
transmitted. Note that a Stop condition is not generated indicates the ACK bit after receipt of the word address
after sending the word address. (0x5AA5 in this example). Once again, the R/W bit
must be low in order to transmit the word address.

FIGURE 7: BYTE READ (CONTROL BYTE AND ADDRESS)

BUS ACTIVITY S
T
MASTER A Control Address
R Byte High Byte
T
SDA LINE S1 0 1 0 AAA0 x
2 1 0
A A
C C
BUS ACTIVITY K K

© 2005 Microchip Technology Inc. DS00976A-page 9

AN976
Reading Data Byte Back read back from the 24XXX series device, the master
must respond back with a NO ACK bit. To do this,
After the word address has been transmitted, the SSPIF is cleared once more and the ACKEN bit is set,
Restart Enable bit (RSEN) is used to initiate a Restart sending out the NO ACK bit. This indicates to the
condition. Note that a Restart is very similar to a Start, device that no more data will be read. Finally, the
except that a Restart does not first check for a valid bus master generates a Stop condition to end the
condition (this is important since either SCL or SDA operation.
may be low at this point, which would cause an error
during an attempted Start condition). Also, as with initi- Figure 8 shows the control byte and data byte during
ating other bus conditions with the MSSP module, the the actual read part of the operation. A Restart condi-
SSPIF flag must be properly cleared and monitored tion is generated immediately after receipt of the previ-
during the sequence. The second control byte (with the ous ACK bit and is marked with the left marker. At the
R/W bit set) is transmitted as normal. end of the transfer, the master indicates that no more
data will be read by the use of the NO ACK bit (holding
In order to read the data byte, the ACKDT bit is first set SDA high in place of an ACK bit); this is shown by the
to indicate that a NO ACK should be sent. Then (after right marker. After the NO ACK bit has been sent, the
clearing SSPIF), the RCEN bit is set to initiate the read. master generates a Stop condition to end the
Once SSPIF is set by hardware, the data byte can be operation.
copied from SSPBUF. Once the data byte has been

FIGURE 8: BYTE READ (CONTROL BYTE AND DATA)

BUS ACTIVITY S
T S
MASTER A Control Data T
R Byte Byte O
T P
SDA LINE S 1 0 1 0 A A A1 P
2 1 0
A N
C O
BUS ACTIVITY K A
C
K

DS00976A-page 10 © 2005 Microchip Technology Inc.

 AN976
PAGE WRITE
A very useful method for increasing throughput when The page write operation is very similar to the byte write
writing large blocks of data is to use page write opera- operation. However, instead of generating a Stop
tions. All of the 24XXX series devices, with the excep- condition after the first data byte has been transmitted,
tion of the 24XX00, support page writes, and the page the master continues to send more data bytes, up to 1
size varies from 8 bytes to 128 bytes. Using the page page total. The 24XXX will automatically increment the
write feature, up to 1 full page of data can be written internal Address Pointer with receipt of each byte. As
consecutively with the control and word address bytes with the byte write operation, the internal write cycle is
being transmitted only once. It is very important to point initiated by the Stop condition.
out, however, that page write operations are limited to
writing bytes within a single physical page, regardless Sending Multiple Bytes Successively
of the number of bytes actually being written. Physical
page boundaries start at addresses which are integer Figure 9 shows two consecutive data bytes during a
multiples of the page size, and end at addresses which page write operation. The entire transfer cannot be
are [integer multiples of the page size] minus 1. Any shown legibly due to length, but this screen shot shows
attempts to write across a page boundary will result in the main difference between a page write and a byte
the data being wrapped back to the beginning of the write. Notice that after the device acknowledges the
current page, thus overwriting any data previously first data byte (0x10 in this example), the master
stored there. immediately begins transmitting the second data byte
(0x0F in this example).

FIGURE 9: PAGE WRITE (TWO CONSECUTIVE DATA BYTES)

BUS ACTIVITY
MASTER Data (n) Data (n + 1)

SDA LINE
A A A
BUS ACTIVITY C C C
K K K

© 2005 Microchip Technology Inc. DS00976A-page 11

AN976
SEQUENTIAL READ
Just as the page write operation exists to allow for more In order to do this with the MSSP module, the ACKDT
efficient write operations, the sequential read operation bit must be properly setup before initiating the Acknowl-
exists to allow for more efficient read operations. While edge via the ACKEN bit. Clearing the ACKDT bit
the page write is limited to writing within a single produces an ACK bit, whereas setting the ACKDT bit
physical page, the sequential read operation can read produces a NO ACK bit.
out the entire contents of memory in a single operation.
The sequential read operation is very similar to the byte Reading Data Bytes Successively
read operation, except that the master must pull SDA
Figure 10 shows the last two bytes of a 16-byte
low after receipt of each data byte to send an Acknowl-
sequential read operation. Note that the master pulls
edge bit back to the 24XXX series device. This ACK bit
SDA low to transmit an ACK bit after the first data byte,
indicates that more data is to be read. As long as this
but leaves SDA high to transmit a NO ACK bit after the
ACK bit is transmitted, the master can continue to read
final data byte. And as with all other operations, a Stop
back data without the need for generating Start/Stop
condition is generated to end the operation.
conditions or for sending more control/word address
bytes.

FIGURE 10: SEQUENTIAL READ (LAST TWO DATA BYTES)

BUS ACTIVITY S
T
MASTER Data n + (x-1) Data n + x O
P
SDA LINE P
A N
BUS ACTIVITY C O
K A
C
K

DS00976A-page 12 © 2005 Microchip Technology Inc.

 AN976
CONCLUSION
When communicating with the 24XXX series EEPROM
devices, there are many benefits of using the PICmicro
MSSP module over bit-banging through software. The
designer does not have to be familiar with the I2C
timing specifications, nor is the designer required to
write full software routines to provide I2C functionality.
This results in much shorter development time.
This application note illustrated the main characteris-
tics of I2C communications with Microchip’s 24XXX
series serial EEPROM devices with the use of the
PICmicro MSSP module. The assembly code provided
is highly portable and can be used with only minor
modifications, on many PIC16 family PICmicro micro-
controllers equipped with the MSSP module. The code
was tested on Microchip’s PICDEM™ 2 Plus
Demonstration Board with the connections shown in
Figure 1.

© 2005 Microchip Technology Inc. DS00976A-page 13

AN976
NOTES:

DS00976A-page 14 © 2005 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications. PRO MATE, PowerSmart, rfPIC, and SmartShunt are
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LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, PICMASTER, SEEVAL, SmartSensor and The Embedded
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Microchip disclaims all liability arising from this information and Microchip Technology Incorporated in the U.S.A.
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All other trademarks mentioned herein are property of their
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© 2005, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

© 2005 Microchip Technology Inc. DS00976A-page 15

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10/20/04

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