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Module 1 &2 Question Bank (BEC302)

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99 views2 pages

Module 1 &2 Question Bank (BEC302)

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videogenerator412
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© © All Rights Reserved
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Bapuji Educational Association®

BAPUJI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DAVANGERE-577 004


Department of Electronics & Communication Engineering

Course Title Digital System Design using Verilog Course Code BEC302

Q No. Module 1-Questions


1 Define Combinational Logic. Design a combinational logic circuit that generates an output indicating when
a majority of four inputs is true.
2 An electric motor powering a conveyer used to move material is to be turned on when one of two operators
is in position, if material is present to be moved and if the protective interlock switch is not open. Input and
output variables are to be expressed in binary; that is operator 1 is in position then the associated variable is
logic 1. The motor is running (ON) if its output variable is a 1, and the motor is off if the variable is a 0.
Write the truth table for the above design, simplify and realize output variable using logic gates.

3 Convert the following equations in to the proper canonical form and write its shortened decimal notation
f(a b c)=ab + a c + bc ii) f(a b c) = ( a+ b ) (b +c)
4 For the following Boolean function, list all the Implicants, Prime Implicants, and Essential Prime
Implicants. f (w x y z )=∑(5, 7, 8, 9, 13)
5 Simplify the following Boolean function using K Map
f (a b c d )=∑( 3, 4, 6,9, 11, 12, 13, 14, 15)
6 Simplify the following Boolean function using K Map
f (a b c d )=∑(2, 3, 4, 5, 13, 15)+ ∑d(8, 9, 10, 11)
7 Simplify the following Boolean function using K Map
f (a b c d )=∑(1,3,5,7,8,10,12,13,14)+ ∑d(4, 6, 15)
8 Simplify the following Boolean function using K Map
f (a b c d )= Π (0,1,4,5,8,9,11)+ ∑d(2,10)
9 Simplify the following Boolean function using K Map
f (a b c d )= Π (1,2, 3, 4,9,10)+ ∑d(0,14, 15)
10 Simplify the following Boolean function using Quine-McCluskey technique
f (a b c d )=∑(7, 9, 12, 13, 14, 15)+ ∑d(4, 11)
11 Simplify the following Boolean function using Quine-McCluskey technique
f (a b c d )=∑(3,4,5,7,10,12,14,15)+ ∑d(2)
12 Simplify the following Boolean function using Quine-McCluskey technique
f (a b c d )=∑(1,3,6,8,9,10,12,14)+ ∑d(7, 13)

Vision of the Department


To be in the forefront in providing quality technical education and research
in Electronics & Communication Engineering to produce skilled professionals to
cater to the challenges of the society
Bapuji Educational Association®
BAPUJI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DAVANGERE-577 004
Department of ElectronicsModule 2-Questions Engineering
& Communication
Q No.
1 Explain Binary Adder with K map and Logical representation of Sum and Carry.
2 Explain Carry lookahead Adder with General and Sigma blocks.
3 Explain 4 bit parallel Adder/Subtractor circuit.
4 Design a carry look ahead 4-bit parallel adder. Show that the time for addition is independent of the
length of operands
5 With neat block diagram Explain working of Decimal Adder.
6 Design and Implement 1 bit Comparator
7 Design and Implement 2 bit Comparator
8 Implement Full subtractor using 3 to 8 line Decoder with decoder having high outputs and active
low enable.
9 Realize the Boolean expression using 3:8 line decoder and two OR gates.
F1(x, y, z)=Σ(1, 2, 4, 5)
F2(x, y, z)= Σ(1,5,7)
10 Realize the Boolean expression using 3:8 line decoder and OR/NOR gates.
F1(x, y, z)=Σ(0,1, 5, 6,7)
F2(x, y, z)= Σ(1, 2, 3,6,7)
11 Realize the Boolean expression using 3:8 line decoder and OR/NOR gates.
F1(x, y, z)= Π(0,3, 5, 6,7)
F2(x, y, z)= Π (2, 3, 4, 5,7)
12 Implement Boolean expression using 8:1 MUX with a, b, c as select lines
F(a b c d)= Σ(0, 1,5,6,7, 9,10,15)
13 Implement the Boolean function F(a b c d)= Σ(0, 2, 4, 5,7, 9,10,14) using two 4:1 MUX with
variable a, b, as select lines in first level and one 2:1 MUX with variable c as select line in the
second level.
14 Implement D(w, x, y, z)= )= Σ(0, 1,2,4, 5, 7,8, 9,12,13) using 8:1 MUX.
15 Write the condensed truth table for a 4:2 line priority Encoderwith a valid output with the highest
priority given to the input having highest index. Determine the minimal sum equations for three
outputs.

Course Outcomes
CO1 Simplify Boolean functions using K-map and Quine-McCluskey minimization technique
Analyze and design for combinational logic circuit
CO2
Analyze the concepts of Flip Flops(SR, D,T and JK) and to design the synchronous sequential circuits
CO3
using Flip Flops
Model Combinational circuits (adders, subtractors, multiplexers) and sequential circuits using Verilog
CO4 descriptions
Revised Bloom’s Levels (RBL)
L1: Remembering L2: Understanding L3: Applying

Vision of the Department


To be in the forefront in providing quality technical education and research
in Electronics & Communication Engineering to produce skilled professionals to
cater to the challenges of the society

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