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Verilog code

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Vandana Ch
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8 views

Verilog code

Uploaded by

Vandana Ch
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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module TrafficSystem (

input wire clk,

input wire reset,

input wire helmet,

output reg [7:0] ascii,

output reg [3:0] count );

typedef enum reg [2:0] {

START = 3'b000,

CHECK_HELMET = 3'b001,

CONVERT_TEXT = 3'b010,

DISPLAY = 3'b011,

CHECK_COUNT = 3'b100,

COUNT_DOWN = 3'b101 }

state_t;

reg [2:0] current_state, next_state;

reg [7:0] ascii_numbers[0:255];

initial begin

ascii_numbers[0] = 8'h41;

ascii_numbers[1] = 8'h42;

count = 4'd5;

end

always @(posedge clk or posedge reset)

begin
if (reset)

begin

current_state <= START;

count <= 4'd5;

end

else

begin

current_state <= next_state;

end

end

always @(*)

begin

next_state = current_state;

ascii = 8'b0;

case (current_state)

START: begin

next_state = CHECK_HELMET;

end

CHECK_HELMET: begin

if (helmet)

begin

next_state = START;
end

else

begin

next_state = CONVERT_TEXT;

end

end

CONVERT_TEXT: begin

ascii = ascii_numbers[0];

next_state = DISPLAY;

end

DISPLAY: begin

ascii = ascii_numbers[1];

next_state = CHECK_COUNT;

end

CHECK_COUNT: begin

if (count == 0)

begin

next_state = START;

end

else

begin

next_state = COUNT_DOWN;
end

end

COUNT_DOWN: begin

count= count - 1;

if (count == 0)

begin

next_state = START;

end

else

begin

next_state = DISPLAY;

end

end

default: begin

next_state = START;
end
endcase
end

endmodule

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