COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE

ASSIGNMENT 3

Name: Student ID: Section:

1. Consider a sequence of memory address references given below. In the sequence, each word address is
provided in both the decimal and binary formats. Below each address, the relative time at which these
references occur is also listed. Memory contents and addresses are shown in the second table.

Now consider four different 8-byte caches shown below. Assume that each of the four caches was used
independently to facilitate memory access for the sequence above. For each cache type, assume that the
cache is initially empty. To insert a word into a cache block or set, use the following formulas:

Assume that the least-recently used (LRU) scheme is used where appropriate, where the least recently inserted
or accessed element is replaced on conflict. Also, when inserting an element into the cache, if there are multiple
empty slots for one index, you should insert the new element into the left-most slot (first available slot).

a) Use the direct-mapped cache to facilitate memory access for the memory sequence above. You should fill
in the binary form of the Tag values. Show the final contents of the cache in the table below, and compute
the hit rate and miss rate.

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ASSIGNMENT 3

Direct-Mapped Cache Summary

Hit Rate:
Miss Rate:

b) Use the 2-way set associative cache to facilitate memory access for the memory sequence above. You
should fill in the binary form of the Tag values. Show the final contents of the cache in the table below, and
compute the hit rate and miss rate.

2-way Set Associative Cache Summary

Hit Rate:
Miss Rate:
c) Use the 4-way set associative cache to facilitate memory access for the memory sequence above. You should
fill in the binary form of the Tag values. Show the final contents of the cache in the table below, and compute
the hit rate and miss rate.

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ASSIGNMENT 3

4-way Set Associative Cache Summary

Hit Rate:

Miss Rate:

d) Use the fully-associative cache to facilitate memory access for the memory sequence above. You should fill
in the binary form of the Tag values. Show the final contents of the cache in the table below, and compute
the hit rate and miss rate.

Fully Associative Cache Summary

Hit Rate:

Miss Rate:

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ASSIGNMENT 3

2. Fill in the following table for different caches. Assume all caches are direct mapped.

3. Assume a direct-mapped cache and data access sequence given below where the memory and its contents
are shown in the table on the right. Memory is byte addressed and addresses are given in decimal. Assume
five-bit addresses and a one-byte data block.

hits = hit rate =

misses = miss rate =

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ASSIGNMENT 3

4. Assume a direct-mapped cache and data access sequence given below where the memory and its contents
are shown in the table on the right. Memory is byte addressed and addresses are given in decimal. Assume
five-bit addresses and a two-byte data block.

hits = hit rate =

misses = miss rate =

5. Assume a 2-way set associative cache and data access sequence given below where the memory and its
contents are shown in the table on the right. Memory is byte addressed and addresses are given in
decimal. Assume five-bit addresses and a two-byte data block. You should assume that the replacement
policy used here is LRU (least recently used).

hits = hit rate =

misses = miss rate =

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ASSIGNMENT 3

6. Consider a sequence of memory access references given below. In the sequence, each address is provided
in the decimal format (dec) along with the operation (LDR or STR). Along with each address, the relative
time at which these references occur is also listed. Memory contents and addresses are shown in the
second table.

Now consider two different 2-word caches shown on the next page. Assume that each of the two caches
are used independently to facilitate memory access for the sequence above. For each cache type, assume
that the cache is initially empty.

Assume that the least-recently used (LRU) scheme is used where appropriate, where the least recently
inserted or accessed element is replaced on conflict. Also, when inserting an element into the cache, if there
are multiple empty slots for one index, you should insert the new element into the first available slot.

For parts (a) and (b) assume the initial memory contents are the ones given above. Update memory in the
space above for both parts (try to distinguish between the two if needed.)

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ASSIGNMENT 3

a) Use the direct-mapped cache shown below with a block size of two words to facilitate memory access for
the access sequence above. For write hits and misses use the write back and write allocate policies
respectively. You should fill in the binary form of the tag values and hex values for data. When you replace
any content in the cache, simply put a cross sign ( X ) to overwrite a value, and add the new value in the
available space. Show the final contents of the memory and cache below, and compute the hit and miss
rates.

b) Use the 2-way set associative cache shown below with a of block size two words to facilitate memory
access for the access sequence above. For write hits and misses use the write through and write around
policies respectively. You should fill in the binary form of the tag values and hex values for data. When you
replace any content in the cache, simply put a cross sign (x) to overwrite a value, and add the new value in
the available space. Show the final contents of the memory and cache below, and compute the hit and
miss rates.

c) Which of the above two caches performs better and why?

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ASSIGNMENT 3

7. Show the final data and tags of the direct-mapped cache shown below for the given memory contents and
data access sequence. As shown, you have 8-bit addresses and 4 bytes of data in each block. You can
assume write-through and write-allocate write strategies on write hits and misses respectively.

hits = hit rate =

misses = miss rate =

8. Fill the following, show final cache

Block size = _____ N = ______ Assoc = _____

hits = hit rate =

misses = miss rate =

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ASSIGNMENT 3

9. Assume a direct-mapped cache of size 8KB, each block having two 32-bit words. The system is based on
32-bit physical address and uses byte addressing. Find the total number of offsets, index and tag bits.

Off Set Bits =

10. Assume a 4-way set associative cache of size 16KB, each block having four 32-bit words. The system is
based on 32-bit physical address and uses byte addressing. Find the total number of offsets, index and tag
bits.

Off Set Bits =

11. Show final cache where block size =2, N = 4

hits = hit rate =

misses = miss rate =