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CS Topical Ch4 - Computer Architecture

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CS Topical Ch4 - Computer Architecture

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Aaymah Saeed O-1 Serenity

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Computer Architecture

Computer Science
Topical Past Papers A-I

Compiled By: Absar Moeen

Visiting Teacher
Supernova
Future World
City School
Lahore Grammer School

0321-5064875

Compiled By: Absar Moeen Page 1 of 187 of Worksheet

(d) The machines have a counter to record the number of cake tins filled. Each time a cake tin is
filled, the counter is increased by 1. The value is stored in an 8-bit register, the current value
is shown.

0 0 0 0 1 0 0 1

(i) Show the value of the binary number after another five cake tins have been filled.

[1]

(ii) The following table shows some assembly language instructions for a processor which
has one general purpose register, the Accumulator (ACC).

Instruction Explanation
Op code Operand
AND #n Bitwise AND operation of the contents of ACC with the
operand
AND <address> Bitwise AND operation of the contents of ACC with the
contents of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the
operand
XOR <address> Bitwise XOR operation of the contents of ACC with the
contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the
operand
OR <address> Bitwise OR operation of the contents of ACC with the
contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros
are introduced on the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros
are introduced on the left hand end.

At the end of each day, the register is reset to 0.

Write the assembly language statement to reset the register to 0.

...........................................................................................................................................

...................................................................................................................................... [2]

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12

(iii) A two-place logical shift to the left is performed on the binary number shown in
part (d).

Show the result of this logical shift.

[1]

(iv) State the mathematical result of a one-place logical shift to the right on a binary
number.

...........................................................................................................................................

...................................................................................................................................... [1]

(e) The factory servers run software that makes use of Artificial Intelligence (AI).

Explain how the use of AI can help improve the safety and efficiency of the factory.

...................................................................................................................................................

.............................................................................................................................................. [3]

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Question Answer Marks Guidance
4(d)(i) 1
9618/01

0 0 0 0 1 1 1 0

4(d)(iv) Division by 2 1
4(e) 1 mark per bullet to max 3 3 Any appropriate implication of AI related

Compiled By: Absar Moeen

e.g. to the scenario
• Machines can learn from past problems/mistakes
• … they can adapt to stop the same problem occurring again
• … they can learn to predict what might happen and raise an alert
• Machines can learn how to work more efficiently
• … when an action slows the system down, it can prevent this happening
again
• … when an action increases the speed of the system, it can repeat this
when necessary to improve the efficiency

Page 10 of 12
SPECIMEN
Cambridge International AS & A Level – Mark Scheme

Page 4 of 187 of Worksheet

For examination
from 2021
6

3 A processor has one general purpose register, the Accumulator (ACC), and several special
purpose registers.

(a) Complete the following description of the role of the registers in the fetch-execute cycle by
writing the missing registers.

The ........................................................................ holds the address of the next instruction

to be loaded. This address is sent to the ........................................................................ .

The ............................................................................ holds the data fetched from this address.

This data is sent to the ............................................................................ and the Control Unit

decodes the instruction’s opcode.

The ............................................................................ is incremented.

[5]

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7

(b) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to ACC
Indirect addressing: The address to be used is at the given address. Load the
LDI <address>
contents of this second address to ACC
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
Index Register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the number n to IX
MOV <register> Move the contents of the accumulator to the given register (IX)
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
Bits in ACC are shifted logically n places to the left. Zeros are introduced on
LSL #n
the right hand end
Bits in ACC are shifted logically n places to the right. Zeros are introduced on
LSR #n
the left hand end
<address> can be an absolute address or a symbolic address
# denotes a denary number, e.g. #123

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8

The current contents of the main memory and selected values from the ASCII character set
are shown.

Address Instruction ASCII code table (selected codes only)

200 LDD 365 ASCII code Character
201 CMP 366 65 A
202 JPE 209 66 B
203 INC ACC 67 C
204 STO 365 68 D
205 MOV IX
206 LDX 365
207 OUT
208 JMP 200
209 END

365 1
366 3
367 65
368 66
IX 0

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Complete the trace table for the program currently in main memory.

Instruction Memory address

ACC IX Output
address 365 366 367 368

1 3 65 66 0

[6]

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10

(c) (i) The Accumulator currently contains the binary number:

0 0 1 1 0 1 0 1

Write the contents of the Accumulator after the processor has executed the following
instruction:

LSL #2

[1]

(ii) The Accumulator currently contains the binary number:

0 0 1 1 0 1 0 1

Identify the mathematical operation that the following instruction will perform on the
contents of the accumulator.

LSR #3
...........................................................................................................................................

..................................................................................................................................... [1]

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PUBLISHED

Question Answer Marks

3(a) 1 mark for each completed statement 5

The Program Counter holds the address of the next instruction to be loaded.
This address is sent to the Memory Address Register.
The Memory Data Register holds the data fetched from this address. This
data is sent to the Current Instruction Register and the Control Unit
decodes the instruction’s opcode.
The Program Counter is incremented.

3(b) 1 mark for each shaded set of values 6

Instruction Memory address

ACC IX Output
address 365 366 367 368
1 3 65 66 0
200 1
201
202
203 2
204 2
205 2
206 65
207 A
208
200 2
201
202
203 3
204 3
205 3
206 66
207 B
208
200 3
201
202
209

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PUBLISHED

Question Answer Marks

3(c)(i) 1
1 1 0 1 0 1 0 0

3(c)(ii) 1 mark for correct answer 1

The number is divided by 8 (and only whole number retained)

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6

4 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
DEC <register> Subtract 1 from the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
IN Key in a character and store its ASCII value in ACC
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
# denotes a denary number, e.g. #123

The current contents of the main memory and selected values from the ASCII character set are:

Address Instruction ASCII code table (selected codes only)

70 IN ASCII code Character
71 CMP 100 65 A
72 JPE 80 66 B
73 CMP 101 67 C
74 JPE 76 68 D
75 JMP 80
76 LDD 102
77 INC ACC
78 STO 102
79 JMP 70
80 LDD 102
81 DEC ACC
82 STO 102
83 JMP 70

100 68
101 65
102 100

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7

(a) Complete the trace table for the program currently in main memory when the following
characters are input:

A D
Do not trace the program any further when the third input is required.

Instruction Memory address

ACC
address 100 101 102
68 65 100

[4]

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8

(b) Some bit manipulation instructions are shown in the table:

The contents of the memory address 300 are shown:

Bit Number 7 6 5 4 3 2 1 0

300 0 1 1 0 0 1 1 0

(i) The contents of memory address 300 represent an unsigned binary integer.

Write the denary value of the unsigned binary integer in memory address 300.

..................................................................................................................................... [1]

(ii) An assembly language program needs to test if bit number 2 in memory address 300
is a 1.

Complete the assembly language instruction to perform this test.

......................... #4
[1]

(iii) An assembly language program needs to set bit numbers 4, 5, 6 and 7 to 0, but keep
bits 0 to 3 with their existing values.

Write the assembly language instruction to perform this action.

...........................................................................................................................................

..................................................................................................................................... [2]

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9

5 Seth uses a computer for work.

(a) Complete the following descriptions of internal components of a computer by writing the
missing terms.

The ............................................................ transmits the signals to coordinate events based

on the electronic pulses of the ............................................................ .

The ............................................................ carries data to the components, while the

............................................................ carries the address where data needs to be written to

or read from.

The ............................................................ performs mathematical operations and

logical comparisons.
[5]

(b) Describe the ways in which the following factors can affect the performance of his laptop
computer.

Number of cores

...................................................................................................................................................

Clock speed

...................................................................................................................................................

...................................................................................................................................................
[4]

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PUBLISHED

Question Answer Marks

4(a) 1 mark for each shaded section / bullet point 4

• Load 65 into ACC

• Load 100 into ACC, increment and store in 102
• Load 68 into ACC
• Load 101 into ACC, decrement and store in 102

Memory address
Instruction
ACC
address
100 101 102

68 65 100

70 65

76 100

77 101

78 101

70 68

80 101

81 100

82 100

(70)

4(b)(i) 102 1

4(b)(ii) AND 1

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PUBLISHED

Question Answer Marks

4(b)(iii) 1 mark for AND, 1 mark for #15 2

AND #15

Question Answer Marks

5(a) 1 mark for each term correctly inserted 5

The control unit/bus transmits the signals to coordinate events based on the
pulses of the (system) clock.

The data bus carries data to components, while the address bus carries the
address where data is being written to or read from.

The arithmetic logic unit/ALU performs mathematical operations and logical

comparisons.

5(b) 1 mark per bullet point to max 3 per factor. max 4 overall. 4

Number of cores:
• Each core processes one instruction per clock pulse
• More/multiple cores mean that sequences of instructions can be split
between them
• … and so more than one instruction is executed per clock pulse // more
sequences of instructions can be run at the same time
• More cores decreases the time taken to complete task

Clock speed:
• Each instruction is executed on a clock pulse // one F-E cycle is run on
each clock pulse
• ... so the clock speed dictates the number of instructions that can be run
per second
• The faster the clock speed the more instructions can be run per second

5(c)(i) 1 mark per bullet point to max 2 2

• Cloud storage can be free (for small quantities )

• No need for separate (high capacity) storage devices // saves storage on
existing devices
• Can access data from any computer with internet access
• Most cloud data services will have in-built backup/disaster recovery
• Security could be better
• Can easily increase capacity
• Data can be easily shared

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11

6 (a) There are two errors in the following register transfer notation for the fetch‑execute cycle.

1 MAR [PC]

2 PC [PC] − 1

3 MDR [MAR]

4 CIR [MDR]

Complete the following table by:

• identifying the line number of each error
• describing the error
• writing the correct statement.

Line
Description of the error Correct statement
number

[4]

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12

(b) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
STO <address> Store the contents of ACC at the given address
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
IN Key in a character and store its ASCII value in ACC
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

The current contents of main memory are shown:

Address Data
100 00001111
101 11110000
102 01010101
103 11111111
104 00000000

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Each row of the following table shows the current contents of ACC in binary and the instruction
that will be performed on those contents.

Complete the table by writing the new contents of the ACC after the execution of each
instruction.

Current contents of the ACC Instruction New contents of the ACC

11111111 OR 101

00000000 XOR #15

10101010 LSR #2

01010101 AND 104

[4]

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PUBLISHED 2021

Question Answer Marks

6(a) 1 mark for identification of line and description of error 4

1 mark for the correct statement

Line
Description of the error Correct statement
number

2 Program Counter should be incremented,

PC ← [PC] + 1
not decremented

3 It should be the contents of the address in

MDR ← [[MAR]]
the MAR

6(b) 1 mark for each correct row 4

Current contents of the ACC Instruction New contents of the ACC

11111111 OR 101 11111111

00000000 XOR #15 00001111

10101010 LSR #2 00101010

01010101 AND 104 00000000

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13

8 The Von Neumann model for a computer system uses registers.

(a) Describe the role of the following special purpose registers in the fetch-execute (F-E) cycle.

(i) Memory Address Register (MAR) .....................................................................................

...........................................................................................................................................

Memory Data Register (MDR) ...........................................................................................

...........................................................................................................................................

...........................................................................................................................................
[4]

(ii) Another special purpose register is the Index Register.

Identify one other special purpose register used in the Von Neumann model for a
computer system.

...........................................................................................................................................

..................................................................................................................................... [1]

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14

(b) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
STO <address> Store the contents of ACC at the given address
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
IN Key in a character and store its ASCII value in ACC
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123

The current contents of main memory are shown:

Address Data
100 01010101
101 11110000
102 00001111
103 00000000
104 11111111

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15

(i) In the following table, each row shows the current contents of the ACC in binary and the
instruction that will be performed on those contents.

Complete the table by writing the new contents of the ACC after the execution of each
instruction.

Current contents of the ACC Instruction New contents of the ACC

01010101 XOR 101

11110000 AND 104

00001111 LSL #4

11111111 OR 102

[4]

(ii) The following table contains five assembly language instruction groups.

Write an appropriate assembly language instruction for each instruction group, using the
given instruction set. The first one has been completed for you.

Instruction Group Instruction

Data movement LDM #2

Input and output of data

Arithmetic operations

Unconditional and conditional instructions

Compare instructions

[4]

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(iii) The opcode LDM uses immediate addressing. The opcode LDD uses direct addressing.

Identify and describe one additional mode of addressing.

Mode of addressing ...........................................................................................................

Description ........................................................................................................................

...........................................................................................................................................

...........................................................................................................................................
[2]

Permission to reproduce items where third-party owned material protected by copyright is included has been sought and cleared where possible. Every
reasonable effort has been made by the publisher (UCLES) to trace copyright holders, but if any items requiring clearance have unwittingly been included, the
publisher will be pleased to make amends at the earliest possible opportunity.

To avoid the issue of disclosure of answer-related information to candidates, all copyright acknowledgements are reproduced online in the Cambridge
Assessment International Education Copyright Acknowledgements Booklet. This is produced for each series of examinations and is freely available to download
at www.cambridgeinternational.org after the live examination series.

Cambridge Assessment International Education is part of the Cambridge Assessment Group. Cambridge Assessment is the brand name of the University of
Cambridge Local Examinations Syndicate (UCLES), which itself is a department of the University of Cambridge.

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PUBLISHED 2021

Question Answer Marks

8(a)(i) 1 mark for each bullet point to max 2 for each register 4

MAR
• Stores the next address to be fetched
• ... held in the Program Counter (PC)
• The data at this address is then fetched

MDR
• Stores the data from the address pointed to by the MAR
• The data in it is copied to the Current Instruction Register (CIR)

8(a)(ii) 1 mark for a correct register 1

e.g.
Program Counter (PC)
Current Instruction Register (CIR)
Status register
Interrupt register

8(b)(i) 1 mark for each correct answer 4

Current contents of New contents of

Instruction
the ACC the ACC

01010101 XOR 101 1010 0101

11110000 AND 104 1111 0000

00001111 LSL #4 1111 0000

11111111 OR 102 1111 1111

8(b)(ii) 1 mark for each correct instruction 4

Instruction Group Instruction

Data movement LDM #2

Input and output of data IN / OUT

Arithmetic Operations INC ACC / INC IX

Unconditional and conditional instructions JPN 100 / JMP 100

Compare instructions CMP 100

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Question Answer Marks

8(b)(iii) 1 mark for name, 1 mark for description 2

• Indirect addressing
• the address to be used is at the given address

• Relative addressing
• the address to be used is an offset number of locations away, relative to
the address of the current instruction

• Indexed addressing
• form the address from the given address plus the contents of the index
register

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6 (a) A computer system is designed using the basic Von Neumann model.

(i) Describe the role of the registers in the Fetch-Execute (F-E) cycle.

...........................................................................................................................................

..................................................................................................................................... [5]

(ii) Describe when interrupts are detected in the F-E cycle and how the interrupts are
handled.

Detected ............................................................................................................................

...........................................................................................................................................

Handled .............................................................................................................................

...........................................................................................................................................

...........................................................................................................................................
[5]

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(b) Identify one factor that can affect the performance of the computer system and state how it
impacts the performance.

Factor .......................................................................................................................................

Impact .......................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................
[2]

Question 6 continues on the next page.

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14

(c) The table shows part of the instruction set for a processor. The processor has one general
purpose register, the Accumulator (ACC).

Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
XOR #n Bitwise XOR operation of the contents of ACC with the operand
OR #n Bitwise OR operation of the contents of ACC with the operand
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are
introduced on the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are
introduced on the left hand end
# denotes a denary number, e.g. #123

(i) Complete the register to show the result after the instruction AND #2 is executed.

[1]

(ii) Complete the register to show the result after the instruction OR #8 is executed.

[1]

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15

(iii) Complete the register to show the result after the operation LSL #4 is executed.

[1]

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Question Answer Marks

6(a)(i) 1 mark per bullet point to max 5 5

 The Program Counter (PC) holds the address of the next instruction …
 …and the contents are incremented / changed to the next address each
cycle
 The Memory Address Register (MAR) holds the address to fetch the data
(from the PC)
 The Memory Data Register (MDR) holds the data at the address in MAR
 The instruction is transferred to Current Instruction Register (CIR) for
decoding and execution

6(a)(ii) 1 mark for detection 5

 At the start/end of a FE cycle

1 mark for handling to max 4

 Priority is checked
 If lower priority than current process continue with F-E cycle
 If higher priority than current process …
 … state of current process is / registers are stored on stack
 Location / type of interrupt identified...
 …appropriate ISR is called to handle the interrupt
 When ISR finished, check for further interrupts (of high priority) / return to
step 1
 Otherwise load data from stack and continue with process

6(b) 1 mark for factor 1 mark for impact 2

e.g.
 Clock speed…
 …higher clock speed means more FE cycles per second

 Number of cores…
 …means more instructions can be carried out simultaneously
 Bus width …
 …allows the transfer of more data each time // allows more memory
locations to be directly accessed

 Cache …
 … the higher capacity the more frequently used instructions it can store
for fast access

6(c)(i) 0000 0000 1

6(c)(ii) 0110 1101 1

6(c)(iii) 1101 0000 1

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5

3 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC).

Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
Bitwise AND operation of the contents of ACC with the contents
AND <address>
of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
Bitwise XOR operation of the contents of ACC with the contents
XOR <address>
of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
Bitwise OR operation of the contents of ACC with the contents of
OR <address>
<address>
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123

(a) The ACC currently contains the following positive binary integer:

0 1 1 0 0 1 0 1

Write the bit manipulation instruction that would change the binary integer in ACC to:

1 1 1 1 1 1 1 1

Opcode ..................................................... Operand .....................................................

[2]

(b) The ACC currently contains the following positive binary integer:

0 1 1 0 0 1 0 1

Write the bit manipulation instruction that would change the binary integer in ACC to:

1 0 0 1 1 0 1 0

Opcode ..................................................... Operand .....................................................

[2]

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Question Answer Marks

3(a) 1 mark for correct opcode and 1 mark for corresponding operand 2

OR #255 // OR #154 // XOR #154

e.g.
 OR...
 ... #255

3(b) 1 mark for correct opcode and 1 mark for corresponding operand 2

XOR #255

e.g.
 XOR...
 ... #255

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5 (a) State what is meant by the stored program concept in the Von Neumann model of a
computer system.

...................................................................................................................................................

............................................................................................................................................. [1]

(b) A Central Processing Unit (CPU) contains several special purpose registers and other
components.

(i) State the role of the following registers.

Program Counter (PC) ......................................................................................................

...........................................................................................................................................

Index Register (IX) ............................................................................................................

...........................................................................................................................................

Status Register (SR) .........................................................................................................

...........................................................................................................................................

...........................................................................................................................................
[3]

(ii) Tick () one box in each row to identify the system bus used by each CPU component.

CPU component Data bus Address bus Control bus

System clock

Memory Address Register (MAR)

[1]

(iii) Describe the purpose of the Control Unit (CU) in a CPU.

...........................................................................................................................................

..................................................................................................................................... [2]

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(c) Describe the purpose of an interrupt in a computer system.

...................................................................................................................................................

............................................................................................................................................. [2]

(d) Identify two causes of a software interrupt.

1 ................................................................................................................................................

...................................................................................................................................................

2 ................................................................................................................................................

...................................................................................................................................................
[2]

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6 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given
address to ACC
LDX <address> Indexed addressing. Form the address from <address> + the
contents of the index register. Copy the contents of this calculated
address to ACC
LDR #n Immediate addressing. Load the number n to IX
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
ADD #n Add the denary number n to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP #n Compare the contents of ACC with number n
JPE <address> Following a compare instruction, jump to <address> if the
compare was True
JPN <address> Following a compare instruction, jump to <address> if the
compare was False
OUT Output to the screen the character whose ASCII value is stored in
ACC
END Return control to the operating system
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

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(a) The current contents of main memory and selected values from the ASCII character set are
given.

(i) Trace the program currently in memory using the trace table.

Instruction Memory address

ACC IX Output
Address Instruction address 100 101 110 111 112
77 LDR #0
0 0 66 65 35
78 LDX 110
79 CMP #35
80 JPE 92
81 ADD 100
82 STO 101
83 LDM #1
84 ADD 100
85 STO 100
86 INC IX
87 LDX 110
88 CMP #35
89 JPN 81
90 LDD 100
91 ADD #48
92 OUT
93 END
…
100 0
101 0
…
110 66
111 65
112 35

ASCII
Character
value
49 1
50 2
51 3
52 4

65 A
66 B
67 C
68 D

[4]
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(ii) The following instructions are repeated for your reference.

Instruction
Explanation
Opcode Operand
LDD <address> Direct addressing. Load the contents of the location at the given
address to ACC
STO <address> Store contents of ACC at the given address

State the purpose of this part of an assembly language program.

LDD 100
STO 165
LDD 101
STO 100
LDD 165
STO 101
...........................................................................................................................................

...........................................................................................................................................
[1]

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Question 6(b) begins on page 16.

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(b) The following table shows another part of the instruction set for the processor.

Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
AND Bn Bitwise AND operation of the contents of ACC with the binary number n
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR Bn Bitwise XOR operation of the contents of ACC with the binary number n
OR #n Bitwise OR operation of the contents of ACC with the operand
OR Bn Bitwise OR operation of the contents of ACC with the binary number n
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are
introduced on the left-hand end
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

(i) The current contents of the ACC are:

1 0 0 1 0 0 1 1

Show the result after the execution of the following instruction.

XOR B00011111
...........................................................................................................................................

...........................................................................................................................................

[1]

(ii) The current contents of the ACC are:

1 0 0 1 0 0 1 1

Show the result after the execution of the following instruction.

AND B11110000
...........................................................................................................................................

...........................................................................................................................................

[1]
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(iii) The current contents of the ACC are:

1 0 0 1 0 0 1 1

Show the result after the execution of the following instruction.

OR B11001100
...........................................................................................................................................

...........................................................................................................................................

[1]
(iv) The current contents of the ACC are:

1 0 0 1 0 0 1 1

Show the result after the execution of the following instruction.

LSR #2
...........................................................................................................................................

...........................................................................................................................................

[1]

(c) Tick (3) one or more boxes in each row to indicate whether the task is performed in the first
pass or the second pass of a two-pass assembler.

Task First pass Second pass

Remove comments.

Read the assembly language program one line at a time.

Generate the object code.

Check the opcode is in the instruction set.

[2]

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Question Answer Marks

5(a) Instructions and data are stored in the same memory space / in main 1
memory.

5(b)(i) 1 mark for each special purpose register: 3

Program Counter (PC):

• to store the address / location / memory location of the next instruction to
be fetched

Index Register (IX):

• to store a value that is added to an address to give another address

Status Register (SR):

• to store flags which are set by events // from the results of arithmetic and
logic operations and interrupt flags

5(b)(ii) 1 mark for both rows: 1

CPU component Data bus Address bus Control bus

System clock ✓

Memory Address Register (MAR) ✓

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Question Answer Marks

5(b)(iii) 1 mark for each bullet point (max 2): 2

• to coordinate / synchronise the actions of other components in the CPU

• to send / receive control signals along the control bus
• to manage the execution of instructions (in sequence)
• to control the communication between the components of the CPU

5(c) 1 mark for each bullet point: 2

• to send a signal from a device or process

• ... seeking the attention of the processor

5(d) 1 mark for each bullet point (max 2). 2

For example:
• division by zero // runtime error in a program
• attempt to access an invalid memory location
• array index out of bounds
• stack overflow

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Question Answer Marks

6(a)(i) 1 mark for each set of highlighted rows. 4

Instructio Memory address

ACC IX Output
n address 100 101 110 111 112
0 0 66 65 35
77 0
78 66
79
80
81
82 66
83 1
84
85 1
86 1
87 65
88
89
81 66
82
83 1
84 2
85 2
86 2
87 35
88
89
90 2
91 50
92 2
93

6(a)(ii) swaps the contents of memory address 100 and 101 1

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Question Answer Marks

6(b)(i) 1000 1100 1

6(b)(ii) 1001 0000 1

6(b)(iii) 1101 1111 1

6(b)(iv) 0010 0100 1

6(c) 1 mark for each pair of highlighted rows 2

Task First pass Second pass

Remove comments. ✓

Read the assembly language program one

✓ ✓
line at a time.

Generate the object code. ✓

Check the opcode is in the instruction set. ✓

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7 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
LDX <address> Indexed addressing. Form the address from <address> + the contents of the
index register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the number n to IX
STO <address> Store the contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
ADD #n Add the denary number n to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
JMP <address> Jump to the given address
CMP <address> Compare the contents of ACC with the contents of <address>
CMI <address> Indirect addressing. The address to be used is at the given address. Compare
the contents of ACC with the contents of this second address
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
END Return control to the operating system
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

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(a) Trace the program currently in memory using the trace table, stopping when line 90 is
executed for a second time.

Address Instruction Instruction Memory address

ACC IX
address 100 101 102 103 110 111 112
75 LDR #0

LDX 110 0 0 112 4 1 4 0

77 CMI 102

78 JPE 91

79 CMP 103

80 JPN 84

81 ADD 101

82 STO 101

83 JMP 86

84 INC ACC

85 STO 101

86 LDD 100

87 INC ACC

88 STO 100

89 INC IX

90 JMP 76

91 END

100 0

101 0

102 112

103 4

110 1

111 4

112 0

[5]

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(b) The following table shows another part of the instruction set for the processor.

Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR Bn Bitwise XOR operation of the contents of ACC with the binary number n
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right-hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left-hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

The contents of memory addresses 50 and 51 are shown:

Memory address Data value

50 01001101

51 10001111

(i) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

XOR B00011111

...........................................................................................................................................

[1]

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(ii) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

AND 50

...........................................................................................................................................

[1]

(iii) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

LSL #3

...........................................................................................................................................

[1]

(iv) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

OR 51

...........................................................................................................................................

[1]

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Description Register transfer notation

Copy the address of the next instruction into
the Memory Address Register.

Increment the Program Counter.

Copy the contents of the Memory Data

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Question Answer Marks

7(a) 1 mark for each set of highlighted rows. 5

Instruction Memory address

ACC IX
address 100 101 102 103 110 111 112
0 0 112 4 1 4 0
75 0
76 1
77
78
79
80
84 2
85 2
86 0
87 1
88 1
89 1
90
76 4
77
78
79
80
81 6
82 6
83
86 1
87 2
88 2
89 2
90

7(b)(i) 0100 1100 1

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Question Answer Marks

7(b)(ii) 0100 0001 1

7(b)(iii) 1001 1000 1

7(b)(iv) 1101 1111 1

7(c) 1 mark for each correct row: 3

Description Register transfer notation

Copy the address of the next instruction into

MAR  [PC]
the Memory Address Register.

Increment the Program Counter. PC  [PC] + 1

Copy the contents of the Memory Data

CIR  [MDR]
Register into the Current Instruction Register.

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6 An interrupt is generated when a key is pressed on a computer keyboard.

Explain how the computer handles this interrupt.

..........................................................................................................................................................

.................................................................................................................................................... [5]

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Question Answer Marks

6 1 mark each to max 5 5

 An interrupt flag is raised in the (interrupt) register

 At the end of the current FE cycle // at the start of the next FE cycle
 The system checks the interrupt register for higher priority interrupts
than current process
 If true, it stores the current contents of the registers on the stack
 The appropriate interrupt service routine (ISR) for the key press is
called
 The input data from the keyboard is processed
 The contents of the registers are restored from the stack
 ... and control is passed back to previous process

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3 A program is written in assembly language.

(a) The program is converted into machine code by a two‑pass assembler.

Draw one or more lines to identify the pass or passes in which each action takes place.

Action Pass

generates object code

first
reads the source code one line at a time

removes white space

second

adds labels to the symbol table

[3]

(b) Assembly language statements can use different modes of addressing.

Complete the following description of addressing modes.

............................................ addressing is when the operand holds the memory address of

the data.

............................................ addressing is when the operand holds a memory address that

stores the memory address of the data.

............................................ addressing is when the operand is the data.

[3]

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5 A student has purchased a new laptop.

(a) The laptop is designed using the Von Neumann model for a computer system.

Identify two types of signal that a control bus can transfer.

1 ................................................................................................................................................

2 ................................................................................................................................................
[2]

(b) Describe two ways the hardware of a laptop can be upgraded to improve the performance
and explain how each upgrade improves the performance.

1 ................................................................................................................................................

...................................................................................................................................................

2 ................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................
[4]

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(c) Peripherals are connected to the laptop using ports.

(i) A printer is connected to a Universal Serial Bus (USB) port.

Describe how data is transmitted through a USB port.

...........................................................................................................................................

..................................................................................................................................... [1]

(ii) A monitor is connected to the laptop using a different type of port.

Identify one other type of port that can be used to connect the monitor.

..................................................................................................................................... [1]

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Question Answer Marks

3(a) 1 mark for generates object code to second pass 3

1 mark for reads source code one line at a time to both boxes
1 mark for removes white space and adds labels to first pass
Action Pass

generates object code

first

reads the source code

one line at a time

removes white space second

adds labels to the

symbol table

3(b) 1 mark for each correct term 3

Direct addressing is when the operand holds the memory address of the data.
Indirect addressing is when the operand holds a memory address that stores
the memory address of the data.
Immediate addressing is when the operand is the data.

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Question Answer Marks

5(a) 1 mark each to max 2 2

Examples:
 Interrupt
 Timing
 Read
 Write

5(b) 1 mark for description; 1 mark for corresponding explanation 4

Examples
 Increase number of cores
 Each core can independently carry out a process at the same time // so
that more instructions are performed in parallel

 Increase RAM capacity

 ... allowing more applications to reside in memory at the same time,
saving disk access times

 Increase cache memory

 More data can be stored in fast access so less time is spent accessing
from RAM

 Increase clock speed

 More Fetch-Decode-Execute (FDE) cycles can run each second / per unit
time

5(c)(i) 1 mark for a correct answer 1

 1 bit is transferred at a time

 Can be synchronous or asynchronous
 USB-3 is full duplex and earlier versions are half-duplex

5(c)(ii) 1 mark for identification of a suitable port 1

Examples
 HDMI
 DisplayPort

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5

3 Five modes of addressing and five descriptions are shown below.

Draw a line to connect each mode of addressing to its correct description.

Mode of addressing Description

the operand is the address of the

direct
address of the value to be used

the operand is the address of the value

immediate
to be used

the operand is the offset from the

indexed current address where the value to be
used is stored

the operand plus the contents of the

indirect index register is the address of the value
to be used

relative the operand is the value to be used

[4]

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8 (a) Explain how the width of the data bus and system clock speed affect the performance of a
computer system.

Width of the data bus ................................................................................................................

...................................................................................................................................................

Clock speed ..............................................................................................................................

...................................................................................................................................................

...............................................................................................................................................[3]

(b) Most computers use Universal Serial Bus (USB) ports to allow the attachment of devices.

Describe two benefits of using USB ports.

1 ................................................................................................................................................

...................................................................................................................................................

2 ................................................................................................................................................

...............................................................................................................................................[2]

Put the stages into the correct sequence by writing the numbers 1 to 6 in the right hand
column.

Sequence
Description of stage
number
the instruction is copied from the Memory Data Register (MDR) and placed
in the Current Instruction Register (CIR)

the instruction is executed

the instruction is decoded

the address contained in the Program Counter (PC) is copied to the Memory
Address Register (MAR)
the value in the Program Counter (PC) is incremented so that it points to the
next instruction to be fetched
the instruction is copied from the memory location contained in the Memory
Address Register (MAR) and is placed in the Memory Data Register (MDR)
[6]

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Page 4 Mark Scheme Syllabus Paper
Cambridge International AS/A Level – May/June 2015 9608 12

the operand is the address of the

direct
address of the value to be used

the operand is the address of the value

immediate
to be used

the operand is the offset from the

indexed
current address where the value to be
used is stored

indirect the operand plus contents of index

relative the operand is the value to be used

[4]

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8 (a) maximum of 2 marks for data bus width and maximum of 2 marks for clock speed

data bus width

• the width of the data bus determines the number of bits that can be simultaneously
transferred
• increasing the width of the data bus increases the number of bits/amount of data that
can be moved at one time (or equivalent)
• …hence improving processing speed as fewer transfers are needed
• By example: e.g. double the width of the data bus moves 2x data per clock pulse

clock speed

• determines the number of cycles the CPU can execute per second
• increasing clock speed increases the number of operations/number of fetch-execute
cycles that can be carried out per unit of time
• ...however, there is a limit on clock speed because the heat generated by higher clock
speeds cannot be removed fast enough [3]

(b) Any two from:

• devices automatically detected and configured when first attached/plug and play
• it is nearly impossible to wrongly connect a device
• USB has become an industrial standard
• supported by many operating systems
• USB 3.0 allows full duplex data transfer
• later versions are backwards compatible with earlier USB systems
• allows power to be drawn to charge portable devices [2]

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the instruction is copied from the Memory Data Register (MDR) and placed
in the Current Instruction Register (CIR) 3

the instruction is executed 6

the instruction is decoded 5

the address contained in the Program Counter (PC) is copied to the

Memory Address Register (MAR) 1

the value in the Program Counter (PC) is incremented so that it points to

the next instruction to be fetched 4

the instruction is copied from the memory location contained in the Memory
Address Register (MAR) and is placed in the Memory Data Register (MDR) 2

[6]

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3

2 Assemblers translate from assembly language to machine code. Some assemblers scan the
assembly language program twice; these are referred to as two-pass assemblers.

The following table shows five activities performed by two-pass assemblers.

Write 1 or 2 to indicate whether the activity is carried out during the first pass or during the second
pass.

First pass or
Activity
second pass

any symbolic address is replaced by an absolute address

any directives are acted upon

any symbolic address is added to the symbolic address table

data items are converted into their binary equivalent

forward references are resolved

[5]

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5 (a) Name and describe three buses used in the von Neumann model.

Bus 1 .........................................................................................................................................

Description ................................................................................................................................

...................................................................................................................................................

Bus 2 .........................................................................................................................................

Description ................................................................................................................................

...................................................................................................................................................

Bus 3 .........................................................................................................................................

Description ................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................
[6]

(b) The sequence of operations shows, in register transfer notation, the fetch stage of the fetch-
execute cycle.

1 MAR ← [PC]
2 PC ← [PC] + 1
3 MDR ← [[MAR]]
4 CIR ← [MDR]

• [register] denotes contents of the specified register or memory location

• step 1 above is read as “the contents of the Program Counter are copied to the Memory
Address Register”

(i) Describe what is happening at step 2.

...........................................................................................................................................

...................................................................................................................................... [1]

(ii) Describe what is happening at step 3.

...........................................................................................................................................

...................................................................................................................................... [1]

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(iii) Describe what is happening at step 4.

...........................................................................................................................................

...................................................................................................................................... [1]

LDD 35

...................................................................................................................................................

.............................................................................................................................................. [2]

(d) (i) Explain what is meant by an interrupt.

...........................................................................................................................................

...................................................................................................................................... [2]

(ii) Explain the actions of the processor when an interrupt is detected.

...........................................................................................................................................

...................................................................................................................................... [4]

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14

7 The table shows assembly language instructions for a processor which has one general purpose
register, the Accumulator (ACC).

Instruction
Explanation
Op code Operand

LDD <address> Direct addressing. Load contents of given address to ACC

STO <address> Store the contents of ACC at the given address

Indirect addressing. The address to be used is at the given

LDI <address>
address. Load the contents of this second address to ACC

Indexed addressing. Form the address from <address> +

LDX <address> the contents of the index register. Copy the contents of this
calculated address to ACC

INC <register> Add 1 to contents of the register (ACC)

JMP <address> Jump to the given address

END Return control to operating system

The diagram shows the contents of the memory.

Main memory

120 0000 1001

121 0111 0101

122 1011 0110

123 1110 0100

124 0111 1111

125 0000 0001

126 0100 0001

127 0110 1001

200 1000 1000

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(a) (i) Show the contents of the Accumulator after execution of the instruction:

LDD 121

Accumulator:

[1]

(ii) Show the contents of the Accumulator after execution of the instruction:

LDI 124

Accumulator:

Explain how you arrived at your answer.

...........................................................................................................................................

...................................................................................................................................... [3]

(iii) Show the contents of the Accumulator after execution of the instruction:

LDX 120

Index Register: 0 0 0 0 0 1 1 0

Accumulator:

Explain how you arrived at your answer.

...........................................................................................................................................

...................................................................................................................................... [3]

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(b) Trace the assembly language program using the trace table.

300 LDD 321

301 INC
302 STO 323
303 LDI 307
304 INC
305 STO 322
306 END
307 320

320 49
321 36
322 0
323 0

Trace table:

Memory address
Accumulator
320 321 322 323

49 36 0 0

[6]

Permission to reproduce items where third-party owned material protected by copyright is included has been sought and cleared where possible. Every reasonable
effort has been made by the publisher (UCLES) to trace copyright holders, but if any items requiring clearance have unwittingly been included, the publisher will
be pleased to make amends at the earliest possible opportunity.

To avoid the issue of disclosure of answer-related information to candidates, all copyright acknowledgements are reproduced online in the Cambridge International
Examinations Copyright Acknowledgements Booklet. This is produced for each series of examinations and is freely available to download at www.cie.org.uk after
the live examination series.

Cambridge International Examinations is part of the Cambridge Assessment Group. Cambridge Assessment is the brand name of University of Cambridge Local
Examinations Syndicate (UCLES), which is itself a department of the University of Cambridge.

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2
Activity First pass or
second pass

any symbolic address is replaced by an absolute address 2

any directives are acted upon 1

any symbolic address is added to the symbolic address table 1

data items are converted into their binary equivalent 1

forward references are resolved 2

[5]

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Page 6 Mark Scheme Syllabus Paper
Cambridge International AS/A Level – May/June 2015 9608 13

5 (a) one mark for name of bus + one mark for description

address bus

• lines used to transfer address of memory or input/output location

• unidirectional bus

data bus

• used to transfer data between the processor and memory/input and output devices
• bidirectional bus

control bus

• used to transmit control signals

• e.g. read/write/fetch/ …
• dedicated bus since all timing signals are generated according to control signal [6]

(b) (i) the program counter is incremented [1]

(ii) the data stored at the address held in MAR is copied into the MDR [1]

(iii) the contents of the Memory Data Register is copied into the Current Instruction
Register [1]

(c) • the MAR is loaded with the operand of the instruction // loaded with 35
• the Accumulator is loaded with the contents of the address held in MAR
// the Accumulator is loaded with the contents of the address 35 [2]

(d) (i) • a signal

• from a device/program that it requires attention from the processor [2]

(ii) • at a point during the fetch-execute cycle …

• check for interrupt
• if an interrupt flag is set/ bit set in interrupt register
• all contents of registers are saved
• PC loaded with address of interrupt service routine [4]

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7 (a) (i)
Accumulator: 0 1 1 1 0 1 0 1
[1]

(ii)
Accumulator: 0 1 1 0 1 0 0 1
[1]

explanation

• content of 124 is 0 1 1 1 1 1 1 1
• this is equivalent to 127
• contents of 127 are 0 1 1 0 1 0 0 1 [2]

(iii)

Accumulator: 0 1 0 0 0 0 0 1
[1]

explanation

• index register value = 6

• 120 + 6 = 126
• contents of 126 placed in the accumulator [2]

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Page 9 Mark Scheme Syllabus Paper
Cambridge International AS/A Level – May/June 2015 9608 13

(b) 1 mark for each correct value in the table.

Accumulator Memory address

320 321 322 323

49 36 0 0

[6]

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3

2 (a)
Processor

Registers

System clock

B Control
unit ALU C
A

Main memory

The diagram above shows a simplified form of processor architecture.

Name the three buses labelled A, B and C.

A ...............................................................................................................................................

B ...............................................................................................................................................

C ...............................................................................................................................................
[3]

(b) State the role of each of the following special purpose registers used in a typical processor.

Program Counter ......................................................................................................................

...................................................................................................................................................

Memory Data Register ..............................................................................................................

...................................................................................................................................................

Current Instruction Register ......................................................................................................

...................................................................................................................................................

Memory Address Register ........................................................................................................

...................................................................................................................................................
[4]

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2 (a) A = control bus

B = address bus

C = data bus [3]

(b) Program Counter – stores the address of next instruction to be executed

Memory Data Register – stores the data in transit between memory and other registers //
holds the instruction before it is passed to the CIR

Current Instruction Register – stores the current instruction being executed

Memory Address Register – stores the address of the memory location which is about to be
accessed [4]

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7

6 (a) Describe the stored program concept for the basic Von Neumann model for a computer
system.

...................................................................................................................................................

...............................................................................................................................................[3]

(b) (i) Name the three types of bus used by a processor.

1 ........................................................................................................................................

2 ........................................................................................................................................

3 ........................................................................................................................................
[3]

(ii) State the function of the system clock in a processor.

...........................................................................................................................................

.......................................................................................................................................[1]

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Cambridge International AS/A Level – October/November 2015 9608 12

6 (a) Any three from:

– program must be resident in (main) memory to be executed

– program consists of a sequence of instructions
– which occupy a (contiguous) block of main memory
– instructions and data are indistinguishable
– each instruction is fetched, (decoded) and then executed
– instruction fetch and data operation cannot occur at the same time [3]

(b) (i) one mark each:

– control bus
– data bus
– address bus [3]

(ii) generates the timing signals/generates the signals to synchronise events in the
processor / fetch–(decode)–execute cycle [1]

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4

3 (a) Describe how special purpose registers are used in the fetch stage of the fetch-execute cycle.

...................................................................................................................................................

...............................................................................................................................................[4]

(b) Use the statements A, B, C and D to complete the description of how the fetch-execute cycle
handles an interrupt.

the address of the Interrupt Service Routine (ISR) is loaded to the Program
A
Counter (PC).
B the processor checks if there is an interrupt.
C when the ISR completes, the processor restores the register contents.
D the register contents are saved.

At the end of the cycle for the current instruction ............................ .

If the interrupt flag is set, ............................ , ............................ and ............................ .

The interrupted program continues its execution.

[4]

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9 The table shows assembly language instructions for a processor which has one general purpose
register, the Accumulator (ACC) and an index register (IX).

Instruction
Explanation

Op code Operand

LDD <address> Direct addressing. Load the contents of the given address to ACC.

LDX <address> Indexed addressing. Form the address from <address> + the contents of the
index register. Copy the contents of this calculated address to ACC.
STO <address> Store contents of ACC at the given address.

ADD <address> Add the contents of the given address to ACC.

INC <register> Add 1 to the contents of the register (ACC or IX).

DEC <register> Subtract 1 from the contents of the register (ACC or IX).

CMP <address> Compare contents of ACC with contents of <address>.

JPE <address> Following a compare instruction, jump to <address> if the compare was True.

JPN <address> Following a compare instruction, jump to <address> if the compare was
False.
JMP <address> Jump to the given address.

OUT Output to screen the character whose ASCII value is stored in ACC.

END Return control to the operating system.

(a) The diagram shows the current contents of a section of main memory and the index register:

60 0011 0010
61 0101 1101
62 0000 0100
63 1111 1001
64 0101 0101
65 1101 1111
66 0000 1101
67 0100 1101
68 0100 0101
69 0100 0011
...
1000 0110 1001

Index register: 0 0 0 0 1 0 0 0

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(i) Show the contents of the Accumulator after the execution of the instruction:

LDX 60

Accumulator:

Show how you obtained your answer.

...........................................................................................................................................

.......................................................................................................................................[2]

(ii) Show the contents of the index register after the execution of the instruction:

DEC IX

Index register:
[1]

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(b) Complete the trace table on the opposite page for the following assembly language program.

50 LDD 100

51 ADD 102

52 STO 103

53 LDX 100

54 ADD 100

55 CMP 101

56 JPE 58

57 JPN 59

58 OUT

59 INC IX

60 LDX 98

61 ADD 101

62 OUT

63 END

...

100 20

101 100

102 1

103 0

IX (Index Register) 1

Selected values from the ASCII character set:

ASCII Code 118 119 120 121 122 123 124 125
Character v w x y z { | }

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Trace table:

Memory address
Instruction Working ACC IX OUTPUT
address space 100 101 102 103

20 100 1 0 1

[7]

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3 (a) Four points from: [4]

• The Program Counter (PC) holds the address of the next instruction to be fetched
• The address in the Program Counter (PC) is copied to the Memory Address Register
(MAR)
• The Program Counter (PC) is incremented
• The instruction is copied to the Memory Data Register (MDR)
o …. from the address held in the Memory Address Register (MAR)
• The instruction from the Memory Data Register (MDR) is copied to the Current
Instruction Register (CIR)

(b) One mark for each statement or letter in the correct place. [4]

At the end of the cycle for the current instruction B

If the interrupt flag is set, D, A and C
The interrupted program continues its execution

At the end of the cycle for the current instruction the processor checks if there is an interrupt.
If the interrupt flag is set, the register contents are saved, the address of the Interrupt Service
Routine (ISR) is loaded to the Program Counter (PC) and when the ISR completes, the
processor restores the register contents.

The interrupted program continues its execution.

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9 (a) (i) One mark for the contents of the accumulator and one mark for the reason. [2]

Accumulator contents: 0100 0101

Reason:

Address is 60
Contents of the index register is 8
And 60 + 8 = 68 in denary gives the address
The contents of which is 0100 0101 in binary.

(ii) 0000 0111 [1]

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(b)

Memory address
Instruction Working OUTPUT
IX
address space ACC
100 101 102 103

20 100 1 0 1

50 20

51 21

52 21

53 100

54 120

59 2

60 20

61 120

62 'x'

One mark for each shaded block. [7]

• Contents of the Accumulator in first 2 lines (instruction addresses 50 and 51)

• Updating address 103 (instruction 52)
• Loading the Accumulator and addition (instructions 53 and 54)
• Not executing instruction 58
• Incrementing the index register (instruction 59)
• Loading the Accumulator and addition (instructions 60 and 61)
• Correct output of 'x' (instruction 62)

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5

4 The table shows assembly language instructions for a processor which has one general purpose
register, the Accumulator (ACC) and an index register (IX).

Instruction Explanation

Op code Operand

LDD <address> Direct addressing. Load the contents of the given address to ACC.
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
index register. Copy the contents of this calculated address to ACC.
STO <address> Store contents of ACC at the given address.

ADD <address> Add the contents of the given address to ACC.

INC <register> Add 1 to the contents of the register (ACC or IX).

DEC <register> Subtract 1 from the contents of the register (ACC or IX).

CMP <address> Compare contents of ACC with contents of <address>.

JPE <address> Following a compare instruction, jump to <address> if the compare was True.

JPN <address> Following a compare instruction, jump to <address> if the compare was False.

JMP <address> Jump to the given address.

OUT Output to screen the character whose ASCII value is stored in ACC.

END Return control to the operating system.

The diagram shows the contents of the index register:

Index register: 1 1 0 0 1 1 0 1

(a) Show the contents of the index register after the execution of the instruction:

INC IX

Index register:
[1]

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6

(b) Complete the trace table on the opposite page for the following assembly language program.

20 LDX 90

21 DEC ACC

22 STO 90

23 INC IX

24 LDX 90

25 DEC ACC

26 CMP 90

27 JPE 29

28 JPN 31

29 ADD 90

30 OUT

31 ADD 93

32 STO 93

33 OUT

34 END
:
:

90 2

91 90

92 55

93 34

IX 2

Selected values from the ASCII character set:

ASCII Code 65 66 67 68 69 70 71 72
Character A B C D E F G H

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7

Trace table:

Memory address
Working ACC IX OUTPUT
Instruction
space 90 91 92 93

2 90 55 34 2

[7]

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Cambridge International AS/A Level – May/June 2016 9608 13

4 (a) 11001110 [1]

(b) [7]

Working Memory address

Instruction ACC IX OUTPUT
space 90 91 92 93
2 90 55 34 2
20 55
21 54
22 54
23 3
24 34
25 33
26
27
28
31 67
32 67
33 'C'
34

One mark each for:

• Instruction 20
• Instructions 21 and 22
• Instruction 23
• Instructions 24 and 25
• Not executing instructions 29 and 30
• Instructions 31 and 32
• Correct output

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10

8 The table shows assembly language instructions for a processor which has one general purpose
register, the Accumulator (ACC) and an Index Register (IX).

Instruction
Explanation
Op code Operand
LDD <address> Direct addressing. Load the contents of the given address to ACC.
Indexed addressing. Form the address from <address> + the
LDX <address> contents of the index register. Copy the contents of this calculated
address to ACC.
STO <address> Store contents of ACC at the given address.
ADD <address> Add the contents of the given address to ACC.
CMP <address> Compare contents of ACC with contents of <address>
Following a compare instruction, jump to <address> if the compare
JPE <address>
was True.
Following a compare instruction, jump to <address> if the compare
JPN <address>
was False.
JMP <address> Jump to the given address.
Output to the screen the character whose ASCII value is stored in
OUT
ACC.
END Return control to the operating system.

The diagram shows the contents of the main memory:

Main memory
800 0110 0100
801 0111 1100
802 1001 0111
803 0111 0011
804 1001 0000
805 0011 1111
806 0000 1110
807 1110 1000
808 1000 1110
809 1100 0010
:
:
2000 1011 0101

(a) (i) Show the contents of the Accumulator after execution of the instruction:

LDD 802

Accumulator:
[1]

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11

(ii) Show the contents of the Accumulator after execution of the instruction:

LDX 800

Index Register: 0 0 0 0 1 0 0 1

Accumulator:

Explain how you arrived at your answer.

...........................................................................................................................................

.......................................................................................................................................[3]

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12

(b) (i) Complete the trace table below for the following assembly language program. This
program contains denary values.

100 LDD 800

101 ADD 801
102 STO 802
103 LDD 803
104 CMP 802
105 JPE 107
106 JPN 110
107 STO 802
108 OUT
109 JMP 112
110 LDD 801
111 OUT
112 END
:
:
800 40
801 50
802 0
803 90

Selected values from the ASCII character set:

ASCII code 40 50 80 90 100

Character ( 2 P Z d

Trace table:

Memory address
ACC OUTPUT
800 801 802 803

40 50 0 90

[4]

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13

(ii) There is a redundant instruction in the code in part (b)(i).

State the address of this instruction.

.......................................................................................................................................[1]

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8 (a) (i)
Accumulator: 1 0 0 1 0 1 1 1
[1]

(ii) One mark for answer and two marks for explanation

Accumulator: 1 1 0 0 0 0 1 0

• Index Register contains 1001 = 9

• 800 + 9 = 809 [3]

(b) (i) ONE mark for each correct row.

Memory address
ACC OUTPUT
800 801 802 803

40 50 0 90

90 90

[4]

(ii) 107 [1]

5 The table shows assembly language instructions for a processor that has one general purpose
register, the Accumulator (ACC) and an index register (IX).

Instruction
Explanation
Op Code Operand
Direct addressing. Load the contents of the given address to
LDD <address>
ACC.
Index addressing. Form the address from <address> +
LDX <address> the contents of the index register. Copy the contents of this
calculated address to ACC.
Indirect addressing. The address to be used is at the given
LDI <address>
address. Load the contents of this second address to ACC.

STO <address> Store the contents of ACC at the given address.

INC <register> Add 1 to contents of the register (ACC or IX).

ADD <address> Add the contents of the given address to the ACC.

END Return control to the operating system.

The diagram shows the contents of a section of main memory:

Main memory

100 0000 0010

101 1001 0011
102 0111 0011
103 0110 1011
104 0111 1110
105 1011 0001
106 0110 1000
107 0100 1011

200 1001 1110

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7

(a) (i) Show the contents of the Accumulator after the execution of the instruction:

LDD 102

ACC:
[1]

(ii) Show the contents of the Accumulator after the execution of the instruction:

LDX 101

IX: 0 0 0 0 0 1 0 0

ACC:

Explain how you arrived at your answer.

...........................................................................................................................................

.......................................................................................................................................[2]

(iii) Show the contents of the Accumulator after the execution of the instruction:

LDI 103

ACC:

Explain how you arrived at your answer.

...........................................................................................................................................

.......................................................................................................................................[3]

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8

(b) Complete the trace table below for the following assembly language program.

800 LDD 810

801 INC ACC

802 STO 812

803 LDD 811

804 ADD 812

805 STO 813

806 END

810 28
811 41
812 0
813 0

Trace table:

Memory address
ACC
810 811 812 813

28 41 0 0

[6]

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5 (a) (i)

0 1 1 1 0 0 1 1
[1]

(ii) ONE mark for Accumulator contents, ONE mark for the explanation.

1 0 1 1 0 0 0 1

• Index Register holds the value 4; 101 + 4 = 105 so load data from address 105
[2]

(iii) ONE mark for Accumulator contents, TWO marks for the explanation.

0 1 0 0 1 0 1 1

• Memory address 103 contains the value 107

• So address 107 is the address from which to load the data [3]

(b) ONE mark for each correct row.

Memory address

ACC 810 811 812 813

28 41 0 0

[6]

4 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC) and an Index Register (IX).

Instruction
Op code Op code Explanation
Operand
(mnemonic) (binary)
Immediate addressing. Load the denary number n to
LDM #n 0000 0001
ACC.
Direct addressing. Load the contents of the location
LDD <address> 0000 0010
at the given address to ACC.
Indirect addressing. At the given address is the
LDI <address> 0000 0101 address to be used. Load the contents of this second
address to ACC.
Indexed addressing. Form the address from
<address> + the contents of the Index Register
LDX <address> 0000 0110
(IX). Copy the contents of this calculated address to
ACC.
LDR #n 0000 0111 Immediate addressing. Load number n to IX.
STO <address> 0000 1111 Store the contents of ACC at the given address.

The following diagram shows the contents of a section of main memory and the Index Register (IX).

(a) Show the contents of the Accumulator (ACC) after each instruction is executed.

IX 0 0 0 0 0 0 1 1

Main
(i) LDM #500
Memory
Address contents
ACC ................................................................[1]
495 13
(ii) LDD 500
496 86
ACC ................................................................[1] 497 92

(iii) LDX 500 498 486

499 489
ACC ................................................................[1]
500 496
(iv) LDI 500 501 497
ACC ................................................................[1] 502 499
503 502

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9

(b) Each machine code instruction is encoded as 16-bits (8-bit op code followed by an 8-bit
operand).

Write the machine code for the following instructions:

LDM #17

LDX #97

[3]

...............................................................................................................................................[1]

(d) Computer scientists often write binary representations in hexadecimal.

(i) Write the hexadecimal representation for this instruction:

0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0

.......................................................................................................................................[2]

(ii) A second instruction has been written in hexadecimal as:

05 3F

Write the equivalent assembly language instruction, with the operand in denary.

.......................................................................................................................................[2]

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9608/11 Cambridge International AS/A Level – Mark Scheme May/June 2017
PUBLISHED

Question Answer Marks

4(a)(i) 500 1

4(a)(ii) 496 1

4(a)(iii) 502 1

4(a)(iv) 86 1

4(b) 3
0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1

0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1

Both correct op codes 1

Operand 0001 0001 1
Operand 0110 0001 1

4(c) 256 1

4(d)(i) 07 C2 2

07 1
C2 1

4(d)(ii) LDI 63 2

LDI 1
63 1

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5 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Op code Op code Explanation
Operand
(mnemonic) (binary)
Direct addressing. Load the contents of
LDD <address> 0001 0011 the location at the given address to the
Accumulator (ACC).
Indirect addressing. The address to be used is
LDI <address> 0001 0100 at the given address. Load the contents of this
second address to ACC.
Indexed addressing. Form the address from
<address> + the contents of the Index
LDX <address> 0001 0101
Register. Copy the contents of this calculated
address to ACC.
Immediate addressing. Load the denary
LDM #n 0001 0010
number n to ACC.
Immediate addressing. Load denary number n
LDR #n 0001 0110
to the Index Register (IX).
Store the contents of ACC at the given
STO <address> 0000 0111
address.

The following diagram shows the contents of a section of main memory and the Index Register (IX).

(a) Show the contents of the Accumulator (ACC) after each instruction is executed.

IX 0 0 0 0 0 1 1 0

(i) LDD 355

Main
ACC .................................................. [1] memory
Address contents
(ii) LDM #355
350
ACC .................................................. [1] 351 86

(iii) LDX 351 352

353
ACC .................................................. [1]
354
(iv) LDI 355 355 351
ACC .................................................. [1] 356
357 22
358

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(b) Each machine code instruction is encoded as 16 bits (8-bit op code followed by an 8-bit
operand).

Write the machine code for these instructions:

LDM #67

LDX #7

[3]

(c) Computer scientists often write binary representations in hexadecimal.

(i) Write the hexadecimal representation for the following instruction.

0 0 0 1 0 1 0 0 0 1 0 1 1 1 1 0

.......................................................................................................................................[2]

(ii) A second instruction has been written in hexadecimal as:

16 4D

Write the assembly language for this instruction with the operand in denary.

.......................................................................................................................................[2]

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Question Answer Marks

5(a)(iv) 86 1

5(b) Op code Operand 3

0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1

0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1

Both correct op codes 1

Operand 0100 0011 1
Operand 0000 0111 1

5(c)(i) 14 5E 2

14 1
5E 1

5(c)(ii) LDR #77 2

LDR 1
#77 1

Question Answer Marks

5(a)(i) 351 1

5(a)(ii) 355 1

5(a)(iii) 22 1

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4 (a) The diagram shows the components and buses found inside a typical Personal Computer
(PC).

General purpose
registers

D
Arithmetic Logic
E F
Unit (ALU)

Some components and buses only have labels A to F to identify them.

For each label, choose the appropriate title from the following list. The title for label D is
already given.

• Control bus
• System clock
• Data bus
• Control unit
• Main memory
• Secondary storage

A ...........................................................................................................................................

B ...........................................................................................................................................

C ...........................................................................................................................................

D Address bus

E ...........................................................................................................................................

F ...........................................................................................................................................
[5]

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(b) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Op code Op code Explanation
Operand
(mnemonic) (binary)
LDM #n 1100 0001 Immediate addressing. Load number n to ACC.
Direct addressing. Load the contents of the given
LDD <address> 1100 0010
address to ACC.
Relative addressing. Move to the address n locations
LDV #n 1100 0011 from the address of the current instruction. Load the
contents of this address to ACC.
STO <address> 1100 0100 Store the contents of ACC at the given address.
DEC 1100 0101 Decrement the contents of ACC.
Output the character corresponding to the ASCII
OUTCH 1100 0111
character code in ACC.
Following a compare instruction, jump to <address> if
JNE <address> 1110 0110
the compare was False.
JMP <address> 1110 0011 (Unconditionally) jump to the given address.
CMP #n 1110 0100 Compare the contents of ACC with number n.

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Complete the trace table for the following assembly language program.
Label Instruction
StartProg: LDV #CountDown
CMP Num1
ASCII code table (selected codes only)
JNE CarryOn
<Space> 3 B C X
JMP Finish
32 51 66 67 88
CarryOn: OUTCH
LDD CountDown
DEC
STO CountDown
JMP StartProg
Finish: LDM #88
OUTCH
END
CountDown: 15
32
51
67
Num1: 32

Trace table:

ACC CountDown OUTPUT

15
67 C
15

[5]

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The program has been copied here for you. The program now starts with a directive which
tells the assembler to load the first instruction of the program to address 100.
Label
ORG #0100
StartProg: LDV #CountDown
CMP Num1
JNE CarryOn
JMP Finish
CarryOn: OUTCH
LDD CountDown
DEC
STO CountDown
JMP StartProg
Finish: LDM #88
OUTCH
END
CountDown: 15
32
51
67
Num1: 32

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On the first pass of the two-pass process, the assembler adds entries to a symbol table.

The following symbol table shows the first eleven entries, part way through the first pass.

The circular labels show the order in which the assembler made the entries to the symbol
table.

Symbol table

Symbolic address Absolute address

StartProg 1 100 2

CountDown 3 UNKNOWN 4

Num1 5 UNKNOWN 6

CarryOn 7 UNKNOWN 8 104 11

Finish 9 UNKNOWN 10

Explain how the assembler made these entries to the symbol table.

...................................................................................................................................................

...............................................................................................................................................[3]

(d) The assembler software must then complete the second pass building up the executable file.

(i) Name the second table needed when the assembler software carries out the second
pass.

.......................................................................................................................................[1]

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The following shows two of the program instructions in machine code.

Machine code
Instruction Binary Hexadecimal
OUTCH 1100 0111 C7
JNE CarryOn A B

Each of the numbers A and B represents the complete instruction in two bytes, one byte for
the op code and one byte for the operand.

(ii) Use the following instruction set to write the numbers for A and B.

A (binary) ........................................................................................................................

B (hexadecimal) .............................................................................................................
[3]

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Question Answer Marks

4(a) A – System clock 5

B – Control unit
C – Main memory
E – Control bus
F – Data bus

4(b) ACC CountDown OUTPUT 5

15
67 C
15
14 14 (1)
51 3 (1) + (1)
14 (1)
13 13
32 (1)
88 X

4(c) Three marks from: Max 3

• The assembler scans the assembly language instructions in sequence

• When it meets a symbolic address checks to see if already in symbol table
• If not, it adds it to the symbol table in the symbolic address column
• If it is already in symbol table check if absolute address known
• If the absolute address is known, it is entered in the appropriate cell
• If the absolute address is not known mark / leave as unknown

4(d)(i) The op code / mnemonic / instruction table 1

4(d)(ii) A – 1110 0110 0110 1000 3

(1) (1)

B – E6 68 (1)

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8 The Von Neumann model uses a series of registers.

(a) Explain what is meant by the term register.

...................................................................................................................................................

...............................................................................................................................................[2]

(b) (i) Explain the purpose of the Memory Data Register (MDR).

...........................................................................................................................................

.......................................................................................................................................[2]

(ii) Name two registers, other than the MDR, that are used in the fetch-execute cycle.

Register 1 ..........................................................................................................................

Register 2 ..........................................................................................................................
[2]

(c) X is a register. The current contents of X are:

1 0 0 0 0 1 1 1

(i) The current contents of register X represent an unsigned binary integer.

Convert the value in X into denary.

.......................................................................................................................................[1]

(ii) The current contents of register X represent a Binary Coded Decimal.

Convert the value in X into denary.

.......................................................................................................................................[1]

(iii) The current contents of register X stores a two’s complement binary integer.

Convert the value in X into denary.

.......................................................................................................................................[1]

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Question Answer Marks

7(a) 1 mark for each input device to max 2 3

e.g.
• (Handheld) remote controller
• Joystick / Games pad / joypad
• Accelerometer
• Microphone
• Suitable sensor

1 mark for output

e.g.
• Motor/vibrator in joystick
• Speaker
• Screen/monitor /TV

7(b)(i) 1 mark for each difference to max 2 2

• RAM is volatile and ROM is non-volatile
• RAM can change and ROM (usually) can't be changed
• ROM is read only, RAM is read/write

7(b)(ii) 1 mark for example 1

e.g.
• Current game
• Currently running processes
• Current graphics/sound

7(b)(iii) 1 mark for an example 1

e.g.
• Start-up instructions / boot program
• Kernel of Operating System

Question Answer Marks

8(a) 1 mark per bullet to max 2 2

• Small piece / word of (fast) memory
• Part of the processor
• Temporary storage of data
• Data is about to be / has been processed

8(b)(i) 1 mark per bullet to max 2 2

• Stores / holds data / instruction when fetched from memory
• Stores / holds data which is being written to memory
• The location accessed is the address held in the Memory Address
Register (MAR)

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Question Answer Marks

8(b)(ii) 1 mark per bullet to max 2 2

• Current Instruction Register (CIR)
• Memory Address Register (MAR)
• Program Counter (PC)
• Accumulator (ACC)
• Index Register (IX)
• Status Register
• Interrupt Register

8(c)(i) 135 1

8(c)(ii) 87 1

8(c)(iii) –121 1

Question Answer Marks

8(a) 1 mark per bullet to max 2 2

• Small piece / word of (fast) memory
• Part of the processor
• Temporary storage of data
• Data is about to be / has been processed

8(b)(i) 1 mark per bullet to max 2 2

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4 The table shows assembly language instructions for a processor which has one general purpose
register, the Accumulator (ACC) and an index register (IX).

Instruction
Explanation
Op code Operand
Direct addressing. Load the contents of the location at the given
LDD <address>
address to ACC.
Indexed addressing. Form the address from <address> + the
LDX <address> contents of the Index Register. Copy the contents of this calculated
address to ACC.
LDR #n Immediate addressing. Load the number n to IX.
STO <address> Store contents of ACC at the given address.
ADD <address> Add the contents of the given address to ACC.
INC <register> Add 1 to the contents of the register (ACC or IX).
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
CMP <address> Compare contents of ACC with contents of <address>.
Following a compare instruction, jump to <address> if the compare
JPE <address>
was True.
Following a compare instruction, jump to <address> if the compare
JPN <address>
was False.
JMP <address> Jump to the given address.
OUT Output to the screen the character whose ASCII value is stored in ACC.
END Return control to the operating system.

(a) (i) State what is meant by direct addressing and indirect addressing.

Direct addressing ..............................................................................................................

...........................................................................................................................................

Indirect addressing ............................................................................................................

...........................................................................................................................................
[2]

(ii) Explain how the instruction ADD 20 can be interpreted as either direct or indirect
addressing.

Direct addressing ..............................................................................................................

...........................................................................................................................................

Indirect addressing ............................................................................................................

...........................................................................................................................................
[2]

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(b) The assembly language instructions in the following table use either symbolic addressing or
absolute addressing.

Tick (3) one box in each row to indicate whether the instruction uses symbolic or absolute
addressing.

Instruction Symbolic Absolute

ADD 90

CMP found

STO 20

[2]

(c) The current contents of a general purpose register (X) are:

X 1 0 1 1 1 0 1 0

(i) The contents of X represent an unsigned binary integer.

Convert the value in X into denary.

.......................................................................................................................................[1]

(ii) The contents of X represent an unsigned binary integer.

Convert the value in X into hexadecimal.

.......................................................................................................................................[1]

(iii) The contents of X represent a two’s complement binary integer.

Convert the value in X into denary.

.......................................................................................................................................[1]

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(d) The current contents of the main memory, Index Register (IX) and selected values from the
ASCII character set are provided with a copy of the instruction set.

Address Instruction ASCII code table (selected codes only)

70 LDX 200 ASCII code Character
71 OUT 127 ?
72 STO 203 128 !
73 LDD 204 129 “
74 INC ACC 130 *
75 STO 204 131 $
76 INC IX 132 &
77 LDX 200 133 %
78 CMP 203 134 /
79 JPN 81
Instruction set
80 OUT
81 LDD 204 Instruction
Op Explanation
82 CMP 205 Operand
code
83 JPN 74
Direct addressing. Load the contents of
84 END LDD <address>
the location at the given address to ACC.
… Indexed addressing. Form the address
from <address> + the contents of the
LDX <address>
200 130 Index Register. Copy the contents of this
calculated address to ACC.
201 133
Immediate addressing. Load the number
202 130 LDR #n
n to IX.
203 0 Store contents of ACC at the given
STO <address>
address.
204 0
Add the contents of the given address to
205 2 ADD <address>
ACC.
Add 1 to the contents of the register (ACC
INC <register>
or IX).
IX 0
Subtract 1 from the contents of the
DEC <register>
register (ACC or IX).
Compare contents of ACC with contents of
CMP <address>
<address>.
Following a compare instruction, jump to
JPE <address>
<address> if the compare was True.
Following a compare instruction, jump to
JPN <address>
<address> if the compare was False.
JMP <address> Jump to the given address.
Output to the screen the character whose
OUT
ASCII value is stored in ACC.
END Return control to the operating system.

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Complete the trace table for the given assembly language program.

Instruction Memory address

ACC IX OUTPUT
address 200 201 202 203 204 205

70 130 130 133 130 0 0 2 0

[8]

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Question Answer Marks

4(a)(ii) 1 mark per bullet point 2

Direct addressing:
• 20 is the address of the data

Indirect addressing:
• 20 is an address which holds the address where the data is stored

4(b) 1 mark for 1 correct tick 2

2 marks for 3 correct ticks

Instruction Symbolic Absolute

ADD 90 9

CMP found 9

STO 20 9

4(c)(i) 186 1

4(c)(ii) BA 1

4(c)(iii) –70 1

4(d) 1 mark per bullet point 8

• Outputting * (instruction 71)

• Storing 130 in 203 (instruction 72)
• Loading, incrementing accumulator and storing in 204 (instructions 73,
74 and 75)
• Incrementing Index Register (instruction 76)
• Loading 133, comparing and jumping to 81 (instructions 77, 78 and 79)
• Loading, comparing and jumping to 74 (instructions 81, 82 and 83)
• Incrementing accumulator, storing in 204 and incrementing index
register, loading 130 (instructions 74–79)
• Outputting * to end (instructions 80–84)

Question Answer Marks

4(a)(i) 1 mark for each type of addressing 2

Direct addressing
• The operand is the address where the data is stored

Indirect addressing
• The operand is an address, that address holds another address where
the data is stored

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Instruction Memory address IX (Index

address ACC Register) OUTPUT
200 201 202 203 204 205

70 130 130 133 130 0 0 2 0

71 *

72 130

73 0

74 1

75 1

76 1

77 133

81 1

74 2

75 2

76 2

77 130

80 *

81 2

82
83

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3 The following table shows assembly language instructions for a processor which has one general
purpose register, the Accumulator (ACC) and an Index Register (IX).

Instruction
Explanation
Op code Operand

LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC.
LDX <address> Indexed addressing. Form the address from <address> + the contents of the
Index Register. Copy the contents of this calculated address to ACC.
LDR #n Immediate addressing. Load the number n to IX.
STO <address> Store contents of ACC at the given address.
ADD <address> Add the contents of the given address to ACC.
INC <register> Add 1 to the contents of the register (ACC or IX).
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
CMP <address> Compare contents of ACC with contents of <address>.
JPE <address> Following compare instruction, jump to <address> if the compare was True.
JPN <address> Following compare instruction, jump to <address> if the compare was False.
JMP <address> Jump to the given address.
OUT Output to the screen the character whose ASCII value is stored in ACC.
END Return control to the operating system.

(a) (i) State what is meant by absolute addressing and symbolic addressing.

Absolute addressing ..........................................................................................................

...........................................................................................................................................

Symbolic addressing .........................................................................................................

...........................................................................................................................................
[2]

(ii) Give an example of an ADD instruction using both absolute addressing and symbolic
addressing.

Absolute addressing ..........................................................................................................

Symbolic addressing .........................................................................................................

[2]

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(b) (i) State what is meant by indexed addressing and immediate addressing.

Indexed addressing ...........................................................................................................

...........................................................................................................................................

Immediate addressing .......................................................................................................

...........................................................................................................................................
[2]

(ii) Give an example of an instruction that uses:

Indexed addressing ...........................................................................................................

Immediate addressing .......................................................................................................

[2]

(c) The current contents of a general purpose register (X) are:

X 1 1 0 0 0 0 0 1

(i) The contents of X represent an unsigned binary integer.

Convert the value in X into denary.

...................................................................................................................................... [1]

(ii) The contents of X represent an unsigned binary integer.

Convert the value in X into hexadecimal.

...................................................................................................................................... [1]

(iii) The contents of X represent a two’s complement binary integer.

Convert the value in X into denary.

...................................................................................................................................... [1]

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(d) The current contents of the main memory, Index Register (IX) and selected values from the
ASCII character set are:

Address Instruction ASCII code table (selected codes only)

40 LDD 100 ASCII code Character
41 CMP 104 300 /
42 JPE 54 301 *
43 LDX 100 302 -
44 CMP 105 303 +
45 JPN 47 304 ^
46 OUT 305 =
47 LDD 100
48 DEC ACC
49 STO 100
50 INC IX
51 JMP 41
52
53
54 END

100 2
101 302
102 303
103 303
104 0
105 303

IX 1

This is a copy of the instruction set.

Instruction
Explanation
Op code Operand

LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC.
LDX <address> Indexed addressing. Form the address from <address> + the contents of the
Index Register. Copy the contents of this calculated address to ACC.
LDR #n Immediate addressing. Load the number n to IX.
STO <address> Store contents of ACC at the given address.
ADD <address> Add the contents of the given address to ACC.
INC <register> Add 1 to the contents of the register (ACC or IX).
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
CMP <address> Compare contents of ACC with contents of <address>.
JPE <address> Following a compare instruction, jump to <address> if the compare was True.
JPN <address> Following a compare instruction, jump to <address> if the compare was False.
JMP <address> Jump to the given address.
OUT Output to the screen the character whose ASCII value is stored in ACC.
END Return control to the operating system.

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Complete the trace table for the given assembly language program.

Instruction Memory address

address ACC IX OUTPUT
100 101 102 103 104 105
2 302 303 303 0 303 1
40

[7]

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4 A student has written the steps of the fetch stage of the fetch-execute (FE) cycle in register transfer
notation. The student has made some errors.

Line 1 MDR [PC]

Line 2 PC PC + 1

Line 3 MDR [MAR]

Line 4 CIR PC

(a) Identify the line numbers of three errors that the student has made. Write the correct notation
for each error.

Line number of error Correct notation

[3]

(b) One stage of the FE cycle includes checking for interrupts.

(i) Give three different events that can generate an interrupt.

1 ........................................................................................................................................

2 ........................................................................................................................................

3 ........................................................................................................................................
[3]

(ii) Explain how interrupts are handled during the fetch-execute cycle.

...........................................................................................................................................

...................................................................................................................................... [5]
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(c) The processor uses buses in the FE cycle.

The diagram shows three buses and two descriptions.

Draw one line from each bus to its appropriate description.

Bus Description

Control bus
Unidirectional
(one direction)

Address bus

Bidirectional
(two directions)
Data bus

[2]

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Question Answer Marks

3(a)(i) 1 mark per bullet point 2

Absolute addressing:
• The operand is a numeric address // The numeric address is given //
referring directly to a memory location
Symbolic addressing:
• The operand is a word/symbol // A word/symbol represents the memory
location/address

3(a)(ii) 1 mark per example 2

Absolute addressing: For example, ADD 230

Symbolic addressing: For example, ADD num1

3(b)(i) 1 mark per bullet point 2

Indexed addressing:
• The address to be used is formed by:
operand + the contents of the Index Register (IX)

Immediate addressing:
• The operand is not an address // the operand is the actual value to be
loaded

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Question Answer Marks

3(b)(ii) 1 mark per example 2

Indexed: For example, LDX 20

Immediate: For example, ADD #20

3(c)(i) 193 1

3(c)(ii) C1 1

3(c)(iii) –63 1

3(d) 1 mark per bullet point 7

• Loading 2, comparing with 104 (instructions 40 and 41)

• Loading 302 (instruction 43)
• Comparing, and branching to 47 (instructions 44, 45)
• Loading, decrementing accumulator and storing (instructions 47, 48 and
49)
• Incrementing Index Register (instruction 50)
• Loading 303, comparing and outputting + (instructions 43–46)
• Loading, decrementing accumulator and storing, incrementing Index
Register and end (instructions 47–51, 41, 42 and 54)

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Question Answer Marks

Instruction Memory address

address IX OUTPUT
ACC
100 101 102 103 104 105
2 302 303 303 0 303 1
40 2

43 302

47 2

48 1

49 1

50 2

43 303

46 +

47 1

48 0

49 0

50 3

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Question Answer Marks

4(a) 1 mark per correct line, max 3 3

Line number of error Correct notation

1 MAR ← [PC]

3 MDR ← [ [MAR] ]

4 CIR ← [MDR]

2 PC ← [PC] + 1

4(b)(i) 1 mark for each event to max 3 3

For example:
• Hardware fault // Example of hardware fault
• I/O request // Example of I/O request
• Program/software error // Example of software error
• End of a time-slice

4(b)(ii) 1 mark per bullet point to max 5 5

• At the end of each fetch–execute cycle the processor checks for

interrupt(s)
• Check if an interrupt flag is set // Check if bit set in interrupt register
• Processor identifies source of interrupt
• Processor checks priority of interrupt
• If interrupt priority is high enough // Lower priority interrupts are disabled
• Processor saves current contents of registers
• Processor calls interrupt handler / Interrupt Service Routine (ISR)
• Address of ISR is loaded into Program Counter (PC)
• When servicing of interrupt complete, processor restores registers
• Lower priority interrupts are re-enabled
• Processor continues with next F–E cycle

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Question Answer Marks

4(c) 1 mark for 1 correct connection 2

2 marks for all 3 correct connections

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5 A simple program written in assembly language is translated using a two-pass assembler.

(a) The table contains some of the tasks performed by a two-pass assembler.

Tick (✓) one box in each row to indicate whether the task is performed at the first or second
pass. The first row has been completed for you.

Task First pass Second pass

Creation of symbol table ✓
Expansion of macros
Generation of object code
Removal of comments
[2]

(b) The processor’s instruction set can be grouped according to their function. For example, one
group is modes of addressing.

Identify two other groups of instructions.

1 ................................................................................................................................................

...................................................................................................................................................

2 ................................................................................................................................................

...................................................................................................................................................
[2]

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(c) The table shows assembly language instructions for a processor which has one general
purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Op code Operand
LDM #n Immediate addressing. Load the denary number n to ACC.
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC.
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
Index Register. Copy the contents of this calculated address to ACC.
LDR #n Immediate addressing. Load the denary number n to IX.
STO <address> Store contents of ACC at the given address.
ADD <address> Add the contents of the given address to ACC.
INC <register> Add 1 to the contents of the register (ACC or IX).
CMP #n Compare contents of ACC with denary number n.
JPE <address> Following a compare instruction, jump to <address> if the compare was True.
JPN <address> Following a compare instruction, jump to <address> if the compare was False.
JMP <address> Jump to the given address.
OUT Output to screen the character whose ASCII value is stored in ACC.
END Return control to the operating system.

The current contents of the main memory, Index Register (IX) and selected values from the
ASCII character set are:

Address Instruction ASCII code table (Selected codes only)

20 LDM #0 ASCII Code Character
21 STO 300
22 CMP #0 65 A
23 JPE 28 66 B
24 LDX 100 67 C
25 ADD 301
26 OUT 68 D
27 JMP 30 69 E
28 LDX 100 97 a
29 OUT
30 LDD 300 98 b
31 INC ACC 99 c
32 STO 300 100 d
33 INC IX
101 e
34 CMP #2
35 JPN 22
36 END
…
100 65
101 67
102 69
103 69
104 68
…
300
301 33

Trace the program currently in memory using the following trace table. The first instruction
has been completed for you.

Instruction Memory address

ACC IX OUTPUT
address 100 101 102 103 104 300 301

65 67 69 69 68 33 0

20 0

[8]

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Question Answer Marks

5(a) 1 mark for two correct ticks, 2 marks for three correct ticks 2

Task First pass Second pass

Creation of symbol table ✓

Expansion of macros ✓

Generation of object code ✓

Removal of comments ✓

5(b) 1 mark per bullet point to max 2 2

• Data movement
• Input and output of data
• Arithmetic operations
• Jump instructions
• Compare instructions

5(c) 1 mark per bullet point 8

• Storing 0 in 300 (line 21)

• Loading 65 (line 28)
• Outputting A (line 29)
• Loading 0 (line 30), incrementing ACC (line 31) and storing in 300
(line 32)
• Incrementing IX (line 33)
• Loading 67 (line 24) and adding 33 (line (25)
• Outputting d (line 26)
• Loading 1 (line 30), incrementing ACC (line 31), storing in 300 (line 32)
and incrementing IX (line 33)

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Memory address
Instruction
IX OUTPUT
address ACC 100 101 102 103 104 300 301

65 67 69 69 68 33 0

20 0

21 0

28 65

29 A

30 0

31 1

32 1

33 1

24 67

25 100

26 d

30 1

31 2

32 2

33 2

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5

3 The fetch-execute cycle is shown in register transfer notation.

01 MAR [PC]

02 PC [PC] - 1

03 MDR [MAR]

04 CIR [MAR]

(a) There are three errors in the fetch-execute cycle shown.

Identify the line number of each error and give the correction.

Line number ..............................................................................................................................

Correction .................................................................................................................................

Line number ..............................................................................................................................

Correction .................................................................................................................................

Line number ..............................................................................................................................

Correction .................................................................................................................................
[3]

(b) A processor’s instruction set can be grouped according to their function. For example, one
group is the input and output of data.

Identify two other groups of instructions.

1 ................................................................................................................................................

...................................................................................................................................................

2 ................................................................................................................................................

...................................................................................................................................................
[2]

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6

(c) The following table shows assembly language instructions for a processor which has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Op code Operand
LDM #n Immediate addressing. Load the denary number n to ACC
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
Index Register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the denary number n to IX
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP #n Compare contents of ACC with denary number n
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system

The current contents of the main memory, Index Register (IX) and selected values from the
ASCII character set are:

Address Instruction ASCII code table (Selected codes only)

50 LDM #0 ASCII code Character
51 STO 401
65 A
52 LDX 300
66 B
53 CMP #0
54 JPE 62 67 C
55 ADD 400 68 D
56 OUT 69 E
57 LDD 401
58 INC ACC
59 STO 401
60 INC IX
61 JMP 52
62 END
…
300 2
301 5
302 0
303 4
…
400 64
401

Trace the program currently in memory using the following trace table.
The first instruction has been completed for you.

Instruction Memory address

ACC IX OUTPUT
address 300 301 302 303 400 401

2 5 0 4 64 0

50 0

[8]

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Question Answer Marks

3(a) 1 mark for each error and correction 3

• Line 02 should be +1 not −1 // PC ← [PC] + 1

• Line 03 should be double brackets around MAR //
MDR ← [[MAR]]
• Line 04 should be MDR not MAR // CIR ← [MDR]

3(b) 1 mark for each group to max. 2 2

• Data movement
• Arithmetic operations
• (Unconditional and conditional) jump instructions
• Compare instructions
• Modes of addressing

3(c) 1 mark per bullet 8

• Storing 0 in 401 (line 51)

• Loading memory location 300, value 2 to ACC (line 52)
• Adding 64 to ACC to give 66 (line 55)
• Outputting B (line 56)
• Load 0 (line 57), increment ACC (line 58) and store 1 in 401 (line 59)
• Incrementing IX (line 60)
• Loading 5 (line 52), adding 64 (line 55), outputting E (line 56) loading 1
(line 57), incrementing ACC (line 58), storing 2 in 401 (line 59) and
incrementing IX (line 60)
• Load 0 (line 52) and end

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Instruction Memory address

ACC IX OUTPUT
address 300 301 302 303 400 401
2 5 0 4 64 0
50 0
51 0 [1]
52 2 [1]
53
54
55 66 [1]
56 B [1]
57 0
[1]
58 1
59 1
60 1 [1]
61
52 5
53
54
55 69
56 E [1]
57 1
58 2
59 2
60 2
61
52 0
53
[1]
54
62

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2

1 Von Neumann is an example of a computer architecture.

(a) The diagram has registers used in Von Neumann architecture on the left and descriptions on
the right.

Draw one line to match each register with its correct description.

Stores the data that has just been read from

memory, or is about to be written to memory
Current Instruction Register

Stores the instruction that is being decoded

and executed

Memory Address Register

Stores the address of the input device from

which the processor accesses the instruction

Program Counter
Stores the address of the next instruction to
be read

Memory Data Register

Stores the address of the memory location
about to be written to or read from

[4]

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3

(b) Many components of the computer system transfer data between them using buses. One
example of a bus is an address bus.

(i) Name two other buses that exist within a computer and give the purpose of each.

Bus 1 .................................................................................................................................

Purpose .............................................................................................................................

...........................................................................................................................................

Bus 2 .................................................................................................................................

Purpose .............................................................................................................................

...........................................................................................................................................

...........................................................................................................................................
[4]

(ii) State the benefit of increasing the address bus width from 16 bits to 32 bits.

...........................................................................................................................................

..................................................................................................................................... [1]

(c) The following statements describe features of a low-level language.

Complete the statements by writing the appropriate terms in the spaces.

A ........................................................... is a sequence of instructions that are given an

identifier. These instructions may need to be executed several times.

A ........................................................... is an instruction that tells the assembler to do

something. It is not a program instruction.

The processor’s instruction set can be put into several groups. One of these groups is

........................................................... .
[3]

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Question Answer Marks

1(a) 1 mark for each correct line 4

Stores the data that has just been

Current Instruction read from memory, or is about to be
Register written to memory

Stores the instruction that is being

Memory Address decoded and executed
Register

Stores the address of the input

device from which the processor
Program Counter accesses the instruction

Stores the address of the next

instruction to be read
Memory Data
Register Stores the address of the memory
location about to be written to or
read from

1(b)(i) 1 mark for naming, 1 mark for purpose for each bus 4
• Data bus
• Carries data between the processor and memory / carries data that is
currently being processed.

• Control bus
• Transmits signals between the control unit and the other components

1(b)(ii) Significant increase in the number of directly addressed memory locations // 1

increases the number of directly addressable memory locations from 216 to232

1(c) 1 mark for each correctly inserted term 3

A macro is a sequence of instructions that are given an identifier. These

instructions may need to be executed several times.

A directive is an instruction that tells the assembler to do something. It is not

a program instruction.

The processor’s instruction set can be put into several groups. One of these
groups is data movement // input and output // arithmetic operations //
jump instructions // compare instructions // modes of addressing.

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10

6 A processor has one general purpose register, the Accumulator (ACC), and an Index Register
(IX).

(a) The table gives three assembly language instructions for loading data into the ACC. It also
identifies the addressing mode used for each instruction.

Instruction Addressing mode

A LDM #193 Immediate
B LDD 193 Direct
C LDX 193 Indexed

(i) State the contents of the Accumulator after each of the instructions A, B and C are run.

A ........................................................................................................................................

...........................................................................................................................................

B ........................................................................................................................................

...........................................................................................................................................

C ........................................................................................................................................

...........................................................................................................................................
[3]

(ii) Name two other addressing modes.

1 ........................................................................................................................................

2 ........................................................................................................................................
[2]

(b) The ACC is a general purpose register. The IX is a special purpose register.

Identify two other special purpose registers used in the fetch-execute cycle and describe
their role in the cycle.

Register 1 .................................................................................................................................

Role ..........................................................................................................................................

...................................................................................................................................................

Register 2 .................................................................................................................................

Role ..........................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................
[4]
© UCLES 2020 9608/11/M/J/20
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PUBLISHED

Question Answer Marks

6(a)(i) 1 mark for each correct answer 3

A: The number 193

B: The data in memory location 193

C: The data in the memory location found by adding the contents of the IX to
193

6(a)(ii) 1 mark each correct answer 2

• Indirect
• Relative

Question Answer Marks

6(b) 1 mark for correctly naming register, 1 mark for appropriate role 4

• Program counter // PC
• Stores the address of the next instruction to be fetched

• Memory address register // MAR

• Stores the address where data/instruction is to be read from or saved to

• Memory data register // MDR

• Stores data that is about to be written to memory // Stores data that has
just been read from memory

• Current instruction register // CIR

• Stores the instruction that is currently being decoded/executed

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8

5 (a) The steps 1 to 6 describe the first pass of a two‑pass assembler.

The following three statements are used to complete the sequence of steps.

A If it is already in the symbol table, it checks to see if the absolute address is known

B When it meets a symbolic address, it checks to see if it is already in the symbol table

C If it is known, it is entered

Write one of the letters A, B or C in the appropriate step to complete the sequence.

1. The assembler reads the assembly language instructions

2. .........................

3. If it is not, it adds it to the symbol table

4. .........................

5. .........................

6. If it is not known, it is marked as unknown.

[2]

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9

(b) The assembler translates assembly code into machine code.

The table shows the denary values for three assembler op codes.

Op code Denary value

LDD 194
ADD 200
STO 205

(i) Convert the denary value for the op code LDD into 8‑bit binary.

[1]

(ii) Convert the denary value for the op code STO into hexadecimal.

..................................................................................................................................... [1]

(iii) State why the denary value for the op code ADD cannot be represented in 8‑bit two’s
complement form. Justify your answer.

...........................................................................................................................................

..................................................................................................................................... [2]

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10

(c) The table shows part of the instruction set for a processor. The processor has one general
purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Op code Operand
LDM #n Immediate addressing. Load the denary number n to ACC
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
Index Register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the denary number n to IX
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare contents of the address given with the contents of ACC
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
OUT Output to screen the character whose ASCII value is stored in ACC
END Return control to the operating system

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11

Complete the trace table for the following assembly language program. The first instruction
has been completed for you.

Address Instruction Memory address

Instruction
20 LDD 103 ACC
address 100 101 102 103
21 CMP 101
22 JPE 30 1 2 3 0

23 LDD 100 20 0
24 ADD 101
25 STO 100
26 LDD 103
27 INC ACC
28 STO 103
29 JMP 20
30 END

100 1
101 2
102 3
103 0

[6]
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Question Answer Marks

5(a) 1 mark for one letter in the correct place, 2 marks for all three correct 2

2 B
4 A
5 C

5(b)(i) 11000010 1

5(b)(ii) CD 1

5(b)(iii) 1 mark per bullet point to max 2 2

• The maximum range for an 8-bit two's complement binary number is −128
to +127
• … 200 is outside of the maximum range

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Question Answer Marks

5(c) 1 mark for each highlighted section block 6

Instruction Memory address

address ACC
100 101 102 103

1 2 3 0

20 0

23 1

24 3

25 3

26 0

27 1

28 1

20 1

23 3

24 5

25 5

26 1

27 2

28 2

20 2

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8

4 The following table shows assembly language instructions for a processor that has one general
purpose register, the Accumulator (ACC).

Instruction
Explanation
Op code Operand
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC.
LDM #n Immediate addressing. Load the denary number n to ACC.
Indirect addressing. The address to be used is at the given address. Load
LDI <address>
the contents of this second address to ACC.
CMP <address> Compare the contents of ACC with <address>.

STO <address> Store contents of ACC at the given address.

ADD <address> Add the contents of the given address to ACC.

SUB <address> Subtract the contents of the given address from the contents of ACC.

OUT Output to screen the character whose ASCII value is stored in ACC.

INC <register> Add 1 to the contents of the register (ACC or IX).

JPE <address> Following a compare instruction, jump to <address> if the compare was True.

END Return control to the operating system.

(a) The current contents of the main memory are:

Address Instruction
100 LDD 200
101 ADD 201
102 ADD 202
103 SUB 203
104 STO 204
105 END

200 10
201 20
202 5
203 6
204
205

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9

Tick (✓) one box to indicate which one of the following statements is true after program
execution.

Statements Tick (✓)

Memory location 204 contains 400
Memory location 204 contains 41
Memory location 204 contains 231
Memory location 204 contains 29
[1]

(b) The current contents of the main memory are:

Address Instruction
100 LDM #120
101 ADD 121
102 SUB 122
103 STO 120
104 END

120 10
121 2
122 4
123 6
124 8
125 10

Tick (✓) one box to indicate which one of the following statements is true after program
execution.

Statement Tick (✓)

Memory location 120 contains 135

Memory location 120 contains 118

Memory location 120 contains 0

Memory location 120 contains 16

[1]

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10

(c) The current contents of the main memory are:

Address Instruction
150 LDI 200
151 ADD 200
152 ADD 201
153 STO 205
154 END

200 202
201 203
202 201
203 200
204
205

Tick (✓) one box to indicate which one of the following statements is true after program
execution.

Statement Tick (✓)

Memory location 205 contains 607

Memory location 205 contains 601

Memory location 205 contains 603

Memory location 205 contains 606

[1]

(d) Identify two modes of addressing that are not used in parts (a), (b) or (c).

1 ................................................................................................................................................

2 ................................................................................................................................................
[2]

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11

(e) Assembly language instructions can be put into groups.

Tick (✓) one box on each row to indicate the appropriate instruction group for each assembly
language instruction.

Assembly language Data Jump Input and

Arithmetic
instruction movement instruction output of data

STO 120

JPE 200

ADD 3

LDD 20

INC ACC

OUT

[3]

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Question Answer Marks

4(a) 1 mark for tick in correct position 1

Statement Tick ()

Memory location 204 contains 400

Memory location 204 contains 41

Memory location 204 contains 231

Memory location 204 contains 29 

4(b) 1 mark for tick in correct position 1

Statement Tick ()

Memory location 120 contains 135

Memory location 120 contains 118 

Memory location 120 contains 0

Memory location 120 contains 16

4(c) 1 mark for tick in correct position 1

Statement Tick ()

Memory location 205 contains 607

Memory location 205 contains 601

Memory location 205 contains 603

Memory location 205 contains 606 

4(d) 1 mark per correct mode 2

• Indexed
• Relative

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Question Answer Marks

4(e) 1 mark for correct ticks in pairs of rows (shaded) 3

Assembly Input and

Data Jump
language Arithmetic output of
movement instruction
instruction data

STO 120 

JPE 200 

ADD 3 

LDD 20 

INC ACC 

OUT 

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3 (a) Complete the following statements about CPU architecture by filling in the missing terms.

The Von Neumann model for a computer system uses the ....................................... program
concept.

A program is a series of instructions that are saved in ....................................... .

The processor ....................................... each instruction, ....................................... it and then

....................................... it.

The processor uses several ....................................... to store the data and instructions from

the program because they can be accessed faster than main memory.
[6]

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(b) The following table shows assembly language instructions for a processor that has one
general purpose register, the Accumulator (ACC).

Instruction
Explanation
Op code Operand
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC.
LDM #n Immediate addressing. Load the denary number n to ACC.
Indirect addressing. The address to be used is at the given address. Load the
LDI <address>
contents of this second address to ACC.
STO <address> Store contents of ACC at the given address.

ADD <address> Add the contents of the given address to ACC.

CMP <address> Compare the contents of ACC with the contents of <address>.

OUT Output to screen the character whose ASCII value is stored in ACC.

INC <register> Add 1 to the contents of the register (ACC or IX).

JPE <address> Following a compare instruction, jump to <address> if the compare was True.
Following a compare instruction, jump to <address> if the compare was
JPN <address>
False.
END Return control to the operating system.

(i) The current contents of the

main memory are:

Address Instruction ASCII code table (Selected codes only)

50 LDD 80 ASCII Code Character
51 ADD 80 38 &
52 STO 80 39 ‘
53 LDD 82 40 (
54 INC ACC 41 )
55 STO 82 42 *
56 CMP 81
57 JPN 50
58 LDD 80
59 OUT
60 END

80 10
81 2
82 0

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Trace the program currently in memory using the following trace table.
The first instruction has been completed for you.

Instruction Memory address

ACC Output
address 80 81 82

10 2 0

50 10

[5]

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8

(ii) Assembly language instructions can be put into groups.

Tick (✓) one box in each column to identify the appropriate instruction group for each of
the three assembly language instructions.

Assembly language instruction

Instruction group
STO 80 JPN 50 INC ACC

Input and output of data

Data movement

Arithmetic operations

Unconditional and conditional jump instructions

Compare instructions

[3]

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Question Answer Marks

3(a) 1 mark for each correct term 6

Stored
Memory
Fetches
Decodes
Executes
Registers

The Von Neumann model uses the stored program concept.

The program is a series of instructions that are saved in memory.

The processor fetches each instruction, decodes it and then executes it.

The processor uses several registers to store the data and instructions from
the program because they can be accessed faster than main memory.

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Question Answer Marks

3(b)(i) 1 mark for each set of shaded rows 5

Instruction Memory address

ACC Output
address 80 81 82
10 2 0
50 10
51 20
52 20
53 0
54 1
55 1
56
57
50 20
51 40
52 40
53 1
54 2
55 2
56
57
58 40
59 (
60

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Question Answer Marks

3(b)(ii) 1 mark for each correct column. 3

Assembly language instruction

Instruction Group
STO 80 JPN 50 INC ACC

Input and output of data

Data movement 

Arithmetic operations 

Unconditional and conditional jump


instructions

Compare instructions

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6

3 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Op code Operand
LDD <address> Direct addressing. Load the content of the location at the given
address to ACC.
LDI <address> Indirect addressing. The address to be used is at the given
address. Load the contents of this second address to ACC.
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
CMP <address> Compare the contents of ACC with the contents of <address>.
JMP <address> Jump to the given address.
JPE <address> Following a compare instruction, jump to <address> if the
compare was True.
STO <address> Store the contents of ACC at the given address.
END Return control to the operating system.

The current contents of the main memory are:

Address Instruction
100 LDD 200
101 CMP 201
102 JPE 106
103 DEC ACC
104 STO 200
105 JMP 101
106 END

200 2
201 0
202 200

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7

(a) Trace the program currently in memory using the following trace table.

Memory address
Instruction
ACC
address
200 201 202

2 0 200

[3]

(b) The instruction in memory address 100 needs to be changed. It needs to use indirect
addressing to load the contents of memory address 200.

Give the new instruction to replace LDD 200.

............................................................................................................................................. [1]
© UCLES 2021 9608/11/M/J/21 [Turn over
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8

(c) Each instruction in the assembly language program is encoded in 16 bits (8-bit op code
followed by an 8-bit operand).

(i) The instruction CMP 201 has the operand 201.

Convert the operand 201 into 8-bit binary.

[1]

(ii) State the maximum number of op codes that can be represented using eight bits.

..................................................................................................................................... [1]

(d) The status register contains condition flags.

Identify three condition flags that can be set in the status register.

1 ................................................................................................................................................

2 ................................................................................................................................................

3 ................................................................................................................................................
[3]

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Question Answer Marks

3(a) 1 mark for each set of shaded rows 3

Memory Address
Instruction
ACC
Address
200 201 202

2 0 200

100 2

101

102

103 1

104 1

105

101

102

103 0

104 0

105

101

102

106

3(b) LDI 202 1

3(c)(i) 1100 1001 1

3(c)(ii) 256 1

Compiled By: Absar Moeen Page 171 of 187 of Worksheet
9608/11 Cambridge International AS & A Level – Mark Scheme May/June 2021
PUBLISHED

Question Answer Marks

3(d) 1 mark per bullet point to max 3 3

e.g.
• Zero
• Carry
• Overflow
• Sign/negative
• Compare results
• Parity

Compiled By: Absar Moeen Page 172 of 187 of Worksheet
3

2 The following diagram shows four register notations and seven descriptions.

Draw one line from each register notation to its most appropriate description.

Register notation Description

Holds the op code and operand of an

MDR instruction ready for it to be decoded

Holds the address of the next instruction to

be read

Holds flags that are set when the Arithmetic

CIR and Logic Unit (ALU) executes instructions

Holds data read from, or to be written to,

memory

MAR Holds the current value in the Index Register

Holds the address where data is to be

written to or read from

PC Holds the result of the last instruction

executed by the ALU
[4]

Compiled By: Absar Moeen Page 173 of 187 of Worksheet
4

3 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Op code Operand
Direct addressing. Load the contents of the location at the
LDD <address>
given address to ACC.
Indirect addressing. The address to be used is at the given
LDI <address>
address. Load the contents of this second address to ACC.
STO <address> Store the contents of ACC at the given address.

ADD <address> Add the contents of the given address to ACC.

INC <register> Add 1 to the contents of the register (ACC or IX).

JMP <address> Jump to the given address.

Compare the contents of ACC with the contents of
CMP <address>
<address>.
Following a compare instruction, jump to <address> if the
JPE <address>
compare was True.
END Return control to the operating system.

The current contents of the main memory are:

Address Instruction
50 LDI 103
51 CMP 101
52 JPE 59
53 ADD 102
54 STO 102
55 LDD 100
56 INC ACC
57 STO 100
58 JMP 51
59 ADD 102
60 STO 102
61 END

(a) Trace the program currently in memory using the following trace table.

Memory address
Instruction
ACC
address 100 101 102 103

1 3 0 100

[5]

Compiled By: Absar Moeen Page 175 of 187 of Worksheet
6

(b) The instruction in memory address 50 needs to be changed to use direct addressing to load
the contents of the memory location at address 100.

Give the new instruction to replace LDI 103.

............................................................................................................................................. [1]

(c) Each instruction in the assembly language program is encoded in 16 bits (8-bit op code
followed by an 8-bit operand).

(i) The instruction JPE 59 has the operand 59.

Convert the operand 59 into 8-bit binary.

[1]

(ii) Convert the denary value 59 into hexadecimal.

..................................................................................................................................... [1]

(d) The assembly language program uses direct and indirect addressing.

Identify two other modes of addressing used in an assembly language program.

1 ................................................................................................................................................

2 ................................................................................................................................................
[2]

Compiled By: Absar Moeen Page 176 of 187 of Worksheet
9608/12 Cambridge International AS & A Level – Mark Scheme May/June 2021
PUBLISHED

Question Answer Marks

2 1 mark for each register correctly described 4

Register Notation Description

Holds the op code and operand of an

MDR
instruction ready for it to be decoded

Holds the address of the next instruction

to be read

Holds flags that are set when the

CIR Arithmetic and Logic Unit (ALU) executes
instructions

Holds data read from, or to be written to,

memory

Holds the current value in the Index

MAR
Register

Holds the address where data is to be

written to or read from

Holds the result of the last instruction

PC
executed by the ALU

Compiled By: Absar Moeen Page 177 of 187 of Worksheet
9608/12 Cambridge International AS & A Level – Mark Scheme May/June 2021
PUBLISHED

Question Answer Marks

3(a) 1 Mark for each set of shaded rows 5

Memory Address
Instruction
ACC
Address 100 101 102 103

1 3 0 100

50 1

53 1

54 1

55 1

56 2

57 2

53 3

54 3

55 2

56 3

57 3

59 6

60 6

3(b) LDD 100 1

Compiled By: Absar Moeen Page 178 of 187 of Worksheet
9608/12 Cambridge International AS & A Level – Mark Scheme May/June 2021
PUBLISHED

Question Answer Marks

3(c)(i) 0011 1011 1

3(c)(ii) 3B 1

3(d) 1 mark each (max 2) 2

• Immediate
• Indexed
• Relative

Compiled By: Absar Moeen Page 179 of 187 of Worksheet
9

6 (a) Complete the following sentences that describe parts of a processor in a Von Neumann
model for a computer system.

There are ....................................... buses that transfer data between components in a

computer system.

The width of the ....................................... determines the number of directly accessible

memory locations.

The ....................................... sends signals on the ....................................... to direct the

operation of system components.

....................................... pulses are used to synchronise the components on the motherboard.

[5]

(b) Describe the stages of the fetch-execute (F-E) cycle.

...................................................................................................................................................

............................................................................................................................................. [5]

Compiled By: Absar Moeen Page 180 of 187 of Worksheet
12

8 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Op code Operand

Direct addressing. Load the contents of the location at the given

LDD <address>
address to the ACC

Indirect addressing. The address to be used is at the given address.

LDI <address>
Load the contents of this second address to the ACC
STO <address> Store the contents of the ACC at the given address

ADD <address> Add the contents of the given address to the ACC

INC <register> Add 1 to the contents of the register (ACC or IX)

JMP <address> Jump to the given address

The current contents of the main memory are:

Address Instruction

130 LDI 160

131 ADD 153

132 STO 153

133 LDD 160

134 INC ACC

135 STO 160

136 JMP 130

150 13

151 23

152 11

153 0

160 150

Compiled By: Absar Moeen Page 181 of 187 of Worksheet
13

Complete the trace table for two iterations of the loop.

Instruction Memory address

ACC
address 150 151 152 153 160
13 23 11 0 150

[4]

Compiled By: Absar Moeen Page 182 of 187 of Worksheet
9608/11 Cambridge International AS & A Level – Mark Scheme October/November
PUBLISHED 2021

Question Answer Marks

6(a) One mark for each term in bold. 5

There are three buses that transfer data between components in a computer
system.

The width of the address bus determines the number of directly accessible
memory locations.

The control unit sends signals on the control bus to direct the operation of
system components.

Clock pulses are used to synchronise the components on the motherboard.

6(b) One mark per bullet point to max 5 5

• The address in the program counter is the address of next item to be

fetched
• The address is copied into MAR ...
• …using the address bus
• The instruction from that address moved/copied from main memory to
MDR ...
• …using the data bus
• The instruction is transferred from MDR to CIR
• The processor’s instruction set is used to decode the instruction// the
instruction is decoded in the CIR
• …into op code and operand
• The processor executes the instruction // the processor processes the
data as required
• The address in PC is incremented ready for next loop

Compiled By: Absar Moeen Page 183 of 187 of Worksheet
9608/11 Cambridge International AS & A Level – Mark Scheme October/November
PUBLISHED 2021

Question Answer Marks

8 One mark for each set of rows (shaded and unshaded) 4

Instruction
ACC Memory address
address
150 151 152 153 160
13 23 11 0 150
130 13
131 13
132 13
133 150
134 151
135 151
136
130 23
131 36
132 36
133 151
134 152
135 152
136

Compiled By: Absar Moeen Page 184 of 187 of Worksheet
6

4 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction

Op Explanation
Operand
Code

Direct addressing. Load the contents of the location at the given

LDD <address>
address to ACC
CMP <address> Compare the contents of ACC with the contents of <address>

SUB <address> Subtract the contents of the given address from the ACC

INC <register> Add 1 to the contents of the register (ACC or IX)

DEC <register> Subtract 1 from the contents of the register (ACC or IX)

STO <address> Store contents of ACC at the given address

END Return control to the operating system

(a) The instructions in the processor’s instruction set can be grouped according to their function.

(i) Identify three different instruction groups from the instructions given in the table.

1 ........................................................................................................................................

2 ........................................................................................................................................

3 ........................................................................................................................................
[3]

(ii) Identify one instruction group not given in the table.

..................................................................................................................................... [1]

Compiled By: Absar Moeen Page 185 of 187 of Worksheet
7

(b) The following are four special purpose registers used in the processor:

• Program Counter (PC)

• Memory Data Register (MDR)

• Memory Address Register (MAR)

• Current Instruction Register (CIR)

Describe the purpose of any three registers from the four given.

Register 1 .................................................................................................................................

Description ................................................................................................................................

...................................................................................................................................................

Register 2 .................................................................................................................................

Description ................................................................................................................................

...................................................................................................................................................

Register 3 .................................................................................................................................

Description ................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................
[6]

Compiled By: Absar Moeen Page 186 of 187 of Worksheet
9608/12 Cambridge International AS & A Level – Mark Scheme October/November
PUBLISHED 2021

Question Answer Marks

4(a)(i) 1 mark per bullet point to max 2 3

• Compare instructions
• Arithmetic operations
• Data movement

4(a)(ii) 1 mark only from 1

• Unconditional and conditional jump instructions

• Input and output of data

4(b) 1 mark per bullet point to max 2 per register, max 6 in total 6

Program Counter
• Points to the address ...
• ... of the next instruction to be fetched
• So the address can be transferred to/from the MAR

Memory Address Register

• Points to the address where data to be fetched/stored is located
• So data can be transferred to/from the MDR

Memory Data Register

• Holds the data received from/ transmitted to memory
• So data can be received from/transmitted to the CIR

Current Instruction Register

• Holds the data received from the MDR
• CIR stores the current instruction being processed

Compiled By: Absar Moeen Page 187 of 187 of Worksheet

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