CS Topical Ch4 - Computer Architecture
CS Topical Ch4 - Computer Architecture
Computer Science
Topical Past Papers A-I
0321-5064875
(d) The machines have a counter to record the number of cake tins filled. Each time a cake tin is
filled, the counter is increased by 1. The value is stored in an 8-bit register, the current value
is shown.
0 0 0 0 1 0 0 1
(i) Show the value of the binary number after another five cake tins have been filled.
[1]
(ii) The following table shows some assembly language instructions for a processor which
has one general purpose register, the Accumulator (ACC).
Instruction Explanation
Op code Operand
AND #n Bitwise AND operation of the contents of ACC with the
operand
AND <address> Bitwise AND operation of the contents of ACC with the
contents of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the
operand
XOR <address> Bitwise XOR operation of the contents of ACC with the
contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the
operand
OR <address> Bitwise OR operation of the contents of ACC with the
contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros
are introduced on the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros
are introduced on the left hand end.
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...................................................................................................................................... [2]
(iii) A two-place logical shift to the left is performed on the binary number shown in
part (d).
[1]
(iv) State the mathematical result of a one-place logical shift to the right on a binary
number.
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(e) The factory servers run software that makes use of Artificial Intelligence (AI).
Explain how the use of AI can help improve the safety and efficiency of the factory.
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0 0 0 0 1 1 1 0
© UCLES 2018
4(d)(ii) 1 mark for opcode, 1 mark for operand 2
AND #0
4(d)(iii) 1
0 0 1 0 0 1 0 0
4(d)(iv) Division by 2 1
4(e) 1 mark per bullet to max 3 3 Any appropriate implication of AI related
Page 10 of 12
SPECIMEN
Cambridge International AS & A Level – Mark Scheme
3 A processor has one general purpose register, the Accumulator (ACC), and several special
purpose registers.
(a) Complete the following description of the role of the registers in the fetch-execute cycle by
writing the missing registers.
(b) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to ACC
Indirect addressing: The address to be used is at the given address. Load the
LDI <address>
contents of this second address to ACC
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
Index Register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the number n to IX
MOV <register> Move the contents of the accumulator to the given register (IX)
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
Bits in ACC are shifted logically n places to the left. Zeros are introduced on
LSL #n
the right hand end
Bits in ACC are shifted logically n places to the right. Zeros are introduced on
LSR #n
the left hand end
<address> can be an absolute address or a symbolic address
# denotes a denary number, e.g. #123
The current contents of the main memory and selected values from the ASCII character set
are shown.
365 1
366 3
367 65
368 66
IX 0
Complete the trace table for the program currently in main memory.
1 3 65 66 0
[6]
0 0 1 1 0 1 0 1
Write the contents of the Accumulator after the processor has executed the following
instruction:
LSL #2
[1]
0 0 1 1 0 1 0 1
Identify the mathematical operation that the following instruction will perform on the
contents of the accumulator.
LSR #3
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..................................................................................................................................... [1]
The Program Counter holds the address of the next instruction to be loaded.
This address is sent to the Memory Address Register.
The Memory Data Register holds the data fetched from this address. This
data is sent to the Current Instruction Register and the Control Unit
decodes the instruction’s opcode.
The Program Counter is incremented.
3(c)(i) 1
1 1 0 1 0 1 0 0
4 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
DEC <register> Subtract 1 from the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
IN Key in a character and store its ASCII value in ACC
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
# denotes a denary number, e.g. #123
The current contents of the main memory and selected values from the ASCII character set are:
100 68
101 65
102 100
(a) Complete the trace table for the program currently in main memory when the following
characters are input:
A D
Do not trace the program any further when the third input is required.
[4]
Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
<address> can be an absolute address or a symbolic address
# denotes a denary number, e.g. #123
Bit Number 7 6 5 4 3 2 1 0
300 0 1 1 0 0 1 1 0
(i) The contents of memory address 300 represent an unsigned binary integer.
Write the denary value of the unsigned binary integer in memory address 300.
..................................................................................................................................... [1]
(ii) An assembly language program needs to test if bit number 2 in memory address 300
is a 1.
......................... #4
[1]
(iii) An assembly language program needs to set bit numbers 4, 5, 6 and 7 to 0, but keep
bits 0 to 3 with their existing values.
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(a) Complete the following descriptions of internal components of a computer by writing the
missing terms.
or read from.
logical comparisons.
[5]
(b) Describe the ways in which the following factors can affect the performance of his laptop
computer.
Number of cores
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Clock speed
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[4]
Memory address
Instruction
ACC
address
100 101 102
68 65 100
70 65
71
72
73
74
76 100
77 101
78 101
79
70 68
71
72
80 101
81 100
82 100
83
(70)
4(b)(i) 102 1
4(b)(ii) AND 1
AND #15
The control unit/bus transmits the signals to coordinate events based on the
pulses of the (system) clock.
The data bus carries data to components, while the address bus carries the
address where data is being written to or read from.
5(b) 1 mark per bullet point to max 3 per factor. max 4 overall. 4
Number of cores:
• Each core processes one instruction per clock pulse
• More/multiple cores mean that sequences of instructions can be split
between them
• … and so more than one instruction is executed per clock pulse // more
sequences of instructions can be run at the same time
• More cores decreases the time taken to complete task
Clock speed:
• Each instruction is executed on a clock pulse // one F-E cycle is run on
each clock pulse
• ... so the clock speed dictates the number of instructions that can be run
per second
• The faster the clock speed the more instructions can be run per second
6 (a) There are two errors in the following register transfer notation for the fetch‑execute cycle.
1 MAR [PC]
2 PC [PC] − 1
3 MDR [MAR]
4 CIR [MDR]
Line
Description of the error Correct statement
number
[4]
(b) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
STO <address> Store the contents of ACC at the given address
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
IN Key in a character and store its ASCII value in ACC
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101
Address Data
100 00001111
101 11110000
102 01010101
103 11111111
104 00000000
Each row of the following table shows the current contents of ACC in binary and the instruction
that will be performed on those contents.
Complete the table by writing the new contents of the ACC after the execution of each
instruction.
11111111 OR 101
10101010 LSR #2
[4]
Line
Description of the error Correct statement
number
(a) Describe the role of the following special purpose registers in the fetch-execute (F-E) cycle.
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[4]
Identify one other special purpose register used in the Von Neumann model for a
computer system.
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(b) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
STO <address> Store the contents of ACC at the given address
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
IN Key in a character and store its ASCII value in ACC
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
Address Data
100 01010101
101 11110000
102 00001111
103 00000000
104 11111111
(i) In the following table, each row shows the current contents of the ACC in binary and the
instruction that will be performed on those contents.
Complete the table by writing the new contents of the ACC after the execution of each
instruction.
00001111 LSL #4
11111111 OR 102
[4]
(ii) The following table contains five assembly language instruction groups.
Write an appropriate assembly language instruction for each instruction group, using the
given instruction set. The first one has been completed for you.
Arithmetic operations
Compare instructions
[4]
(iii) The opcode LDM uses immediate addressing. The opcode LDD uses direct addressing.
Description ........................................................................................................................
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[2]
Permission to reproduce items where third-party owned material protected by copyright is included has been sought and cleared where possible. Every
reasonable effort has been made by the publisher (UCLES) to trace copyright holders, but if any items requiring clearance have unwittingly been included, the
publisher will be pleased to make amends at the earliest possible opportunity.
To avoid the issue of disclosure of answer-related information to candidates, all copyright acknowledgements are reproduced online in the Cambridge
Assessment International Education Copyright Acknowledgements Booklet. This is produced for each series of examinations and is freely available to download
at www.cambridgeinternational.org after the live examination series.
Cambridge Assessment International Education is part of the Cambridge Assessment Group. Cambridge Assessment is the brand name of the University of
Cambridge Local Examinations Syndicate (UCLES), which itself is a department of the University of Cambridge.
8(a)(i) 1 mark for each bullet point to max 2 for each register 4
MAR
• Stores the next address to be fetched
• ... held in the Program Counter (PC)
• The data at this address is then fetched
MDR
• Stores the data from the address pointed to by the MAR
• The data in it is copied to the Current Instruction Register (CIR)
• Indirect addressing
• the address to be used is at the given address
• Relative addressing
• the address to be used is an offset number of locations away, relative to
the address of the current instruction
• Indexed addressing
• form the address from the given address plus the contents of the index
register
6 (a) A computer system is designed using the basic Von Neumann model.
(i) Describe the role of the registers in the Fetch-Execute (F-E) cycle.
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(ii) Describe when interrupts are detected in the F-E cycle and how the interrupts are
handled.
Detected ............................................................................................................................
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Handled .............................................................................................................................
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[5]
(b) Identify one factor that can affect the performance of the computer system and state how it
impacts the performance.
Factor .......................................................................................................................................
Impact .......................................................................................................................................
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[2]
(c) The table shows part of the instruction set for a processor. The processor has one general
purpose register, the Accumulator (ACC).
Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
XOR #n Bitwise XOR operation of the contents of ACC with the operand
OR #n Bitwise OR operation of the contents of ACC with the operand
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are
introduced on the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are
introduced on the left hand end
# denotes a denary number, e.g. #123
(i) Complete the register to show the result after the instruction AND #2 is executed.
Register before: 0 1 1 0 1 1 0 1
Register after:
[1]
(ii) Complete the register to show the result after the instruction OR #8 is executed.
Register before: 0 1 1 0 1 1 0 1
Register after:
[1]
(iii) Complete the register to show the result after the operation LSL #4 is executed.
Register before: 0 1 1 0 1 1 0 1
Register after:
[1]
The Program Counter (PC) holds the address of the next instruction …
…and the contents are incremented / changed to the next address each
cycle
The Memory Address Register (MAR) holds the address to fetch the data
(from the PC)
The Memory Data Register (MDR) holds the data at the address in MAR
The instruction is transferred to Current Instruction Register (CIR) for
decoding and execution
Number of cores…
…means more instructions can be carried out simultaneously
Bus width …
…allows the transfer of more data each time // allows more memory
locations to be directly accessed
Cache …
… the higher capacity the more frequently used instructions it can store
for fast access
3 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC).
Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
Bitwise AND operation of the contents of ACC with the contents
AND <address>
of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
Bitwise XOR operation of the contents of ACC with the contents
XOR <address>
of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
Bitwise OR operation of the contents of ACC with the contents of
OR <address>
<address>
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123
(a) The ACC currently contains the following positive binary integer:
0 1 1 0 0 1 0 1
Write the bit manipulation instruction that would change the binary integer in ACC to:
1 1 1 1 1 1 1 1
(b) The ACC currently contains the following positive binary integer:
0 1 1 0 0 1 0 1
Write the bit manipulation instruction that would change the binary integer in ACC to:
1 0 0 1 1 0 1 0
3(a) 1 mark for correct opcode and 1 mark for corresponding operand 2
e.g.
OR...
... #255
3(b) 1 mark for correct opcode and 1 mark for corresponding operand 2
XOR #255
e.g.
XOR...
... #255
5 (a) State what is meant by the stored program concept in the Von Neumann model of a
computer system.
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(b) A Central Processing Unit (CPU) contains several special purpose registers and other
components.
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[3]
(ii) Tick () one box in each row to identify the system bus used by each CPU component.
System clock
[1]
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1 ................................................................................................................................................
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2 ................................................................................................................................................
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[2]
6 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given
address to ACC
LDX <address> Indexed addressing. Form the address from <address> + the
contents of the index register. Copy the contents of this calculated
address to ACC
LDR #n Immediate addressing. Load the number n to IX
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
ADD #n Add the denary number n to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP #n Compare the contents of ACC with number n
JPE <address> Following a compare instruction, jump to <address> if the
compare was True
JPN <address> Following a compare instruction, jump to <address> if the
compare was False
OUT Output to the screen the character whose ASCII value is stored in
ACC
END Return control to the operating system
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101
(a) The current contents of main memory and selected values from the ASCII character set are
given.
(i) Trace the program currently in memory using the trace table.
ASCII
Character
value
49 1
50 2
51 3
52 4
65 A
66 B
67 C
68 D
[4]
© UCLES 2022 9618/11/O/N/22 [Turn over
Compiled By: Absar Moeen Page 38 of 187 of Worksheet
14
Instruction
Explanation
Opcode Operand
LDD <address> Direct addressing. Load the contents of the location at the given
address to ACC
STO <address> Store contents of ACC at the given address
LDD 100
STO 165
LDD 101
STO 100
LDD 165
STO 101
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[1]
(b) The following table shows another part of the instruction set for the processor.
Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
AND Bn Bitwise AND operation of the contents of ACC with the binary number n
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR Bn Bitwise XOR operation of the contents of ACC with the binary number n
OR #n Bitwise OR operation of the contents of ACC with the operand
OR Bn Bitwise OR operation of the contents of ACC with the binary number n
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are
introduced on the left-hand end
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101
1 0 0 1 0 0 1 1
XOR B00011111
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[1]
1 0 0 1 0 0 1 1
AND B11110000
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[1]
© UCLES 2022 9618/11/O/N/22
Compiled By: Absar Moeen Page 41 of 187 of Worksheet
17
1 0 0 1 0 0 1 1
OR B11001100
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[1]
(iv) The current contents of the ACC are:
1 0 0 1 0 0 1 1
LSR #2
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[1]
(c) Tick (3) one or more boxes in each row to indicate whether the task is performed in the first
pass or the second pass of a two-pass assembler.
Remove comments.
[2]
5(a) Instructions and data are stored in the same memory space / in main 1
memory.
System clock ✓
Remove comments. ✓
7 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
LDX <address> Indexed addressing. Form the address from <address> + the contents of the
index register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the number n to IX
STO <address> Store the contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
ADD #n Add the denary number n to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
JMP <address> Jump to the given address
CMP <address> Compare the contents of ACC with the contents of <address>
CMI <address> Indirect addressing. The address to be used is at the given address. Compare
the contents of ACC with the contents of this second address
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
END Return control to the operating system
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101
(a) Trace the program currently in memory using the trace table, stopping when line 90 is
executed for a second time.
77 CMI 102
78 JPE 91
79 CMP 103
80 JPN 84
81 ADD 101
82 STO 101
83 JMP 86
84 INC ACC
85 STO 101
86 LDD 100
87 INC ACC
88 STO 100
89 INC IX
90 JMP 76
91 END
100 0
101 0
102 112
103 4
110 1
111 4
112 0
[5]
(b) The following table shows another part of the instruction set for the processor.
Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR Bn Bitwise XOR operation of the contents of ACC with the binary number n
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right-hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left-hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101
50 01001101
51 10001111
0 1 0 1 0 0 1 1
Show the contents of the ACC after the execution of the following instruction.
XOR B00011111
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[1]
0 1 0 1 0 0 1 1
Show the contents of the ACC after the execution of the following instruction.
AND 50
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[1]
0 1 0 1 0 0 1 1
Show the contents of the ACC after the execution of the following instruction.
LSL #3
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[1]
0 1 0 1 0 0 1 1
Show the contents of the ACC after the execution of the following instruction.
OR 51
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[1]
(c) Write the register transfer notation for each of the stages in the fetch-execute cycle described
in the table.
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Draw one or more lines to identify the pass or passes in which each action takes place.
Action Pass
first
reads the source code one line at a time
[3]
the data.
(a) The laptop is designed using the Von Neumann model for a computer system.
1 ................................................................................................................................................
2 ................................................................................................................................................
[2]
(b) Describe two ways the hardware of a laptop can be upgraded to improve the performance
and explain how each upgrade improves the performance.
1 ................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
2 ................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
[4]
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
..................................................................................................................................... [1]
Identify one other type of port that can be used to connect the monitor.
..................................................................................................................................... [1]
first
Direct addressing is when the operand holds the memory address of the data.
Indirect addressing is when the operand holds a memory address that stores
the memory address of the data.
Immediate addressing is when the operand is the data.
Examples:
Interrupt
Timing
Read
Write
Examples
Increase number of cores
Each core can independently carry out a process at the same time // so
that more instructions are performed in parallel
Examples
HDMI
DisplayPort
[4]
8 (a) Explain how the width of the data bus and system clock speed affect the performance of a
computer system.
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...............................................................................................................................................[3]
(b) Most computers use Universal Serial Bus (USB) ports to allow the attachment of devices.
1 ................................................................................................................................................
...................................................................................................................................................
2 ................................................................................................................................................
...............................................................................................................................................[2]
(c) The table shows six stages in the von Neumann fetch-execute cycle.
Put the stages into the correct sequence by writing the numbers 1 to 6 in the right hand
column.
Sequence
Description of stage
number
the instruction is copied from the Memory Data Register (MDR) and placed
in the Current Instruction Register (CIR)
the address contained in the Program Counter (PC) is copied to the Memory
Address Register (MAR)
the value in the Program Counter (PC) is incremented so that it points to the
next instruction to be fetched
the instruction is copied from the memory location contained in the Memory
Address Register (MAR) and is placed in the Memory Data Register (MDR)
[6]
[4]
• the width of the data bus determines the number of bits that can be simultaneously
transferred
• increasing the width of the data bus increases the number of bits/amount of data that
can be moved at one time (or equivalent)
• …hence improving processing speed as fewer transfers are needed
• By example: e.g. double the width of the data bus moves 2x data per clock pulse
clock speed
• determines the number of cycles the CPU can execute per second
• increasing clock speed increases the number of operations/number of fetch-execute
cycles that can be carried out per unit of time
• ...however, there is a limit on clock speed because the heat generated by higher clock
speeds cannot be removed fast enough [3]
• devices automatically detected and configured when first attached/plug and play
• it is nearly impossible to wrongly connect a device
• USB has become an industrial standard
• supported by many operating systems
• USB 3.0 allows full duplex data transfer
• later versions are backwards compatible with earlier USB systems
• allows power to be drawn to charge portable devices [2]
(c)
Sequence
Description of stage number
the instruction is copied from the Memory Data Register (MDR) and placed
in the Current Instruction Register (CIR) 3
the instruction is copied from the memory location contained in the Memory
Address Register (MAR) and is placed in the Memory Data Register (MDR) 2
[6]
2 Assemblers translate from assembly language to machine code. Some assemblers scan the
assembly language program twice; these are referred to as two-pass assemblers.
Write 1 or 2 to indicate whether the activity is carried out during the first pass or during the second
pass.
First pass or
Activity
second pass
[5]
5 (a) Name and describe three buses used in the von Neumann model.
Bus 1 .........................................................................................................................................
Description ................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
Bus 2 .........................................................................................................................................
Description ................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
Bus 3 .........................................................................................................................................
Description ................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
[6]
(b) The sequence of operations shows, in register transfer notation, the fetch stage of the fetch-
execute cycle.
1 MAR ← [PC]
2 PC ← [PC] + 1
3 MDR ← [[MAR]]
4 CIR ← [MDR]
...........................................................................................................................................
...................................................................................................................................... [1]
...........................................................................................................................................
...........................................................................................................................................
...................................................................................................................................... [1]
...........................................................................................................................................
...................................................................................................................................... [1]
(c) Describe what happens to the registers when the following instruction is executed:
LDD 35
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
.............................................................................................................................................. [2]
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...................................................................................................................................... [2]
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...................................................................................................................................... [4]
7 The table shows assembly language instructions for a processor which has one general purpose
register, the Accumulator (ACC).
Instruction
Explanation
Op code Operand
Main memory
(a) (i) Show the contents of the Accumulator after execution of the instruction:
LDD 121
Accumulator:
[1]
(ii) Show the contents of the Accumulator after execution of the instruction:
LDI 124
Accumulator:
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...................................................................................................................................... [3]
(iii) Show the contents of the Accumulator after execution of the instruction:
LDX 120
Index Register: 0 0 0 0 0 1 1 0
Accumulator:
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...................................................................................................................................... [3]
(b) Trace the assembly language program using the trace table.
320 49
321 36
322 0
323 0
Trace table:
Memory address
Accumulator
320 321 322 323
49 36 0 0
[6]
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be pleased to make amends at the earliest possible opportunity.
To avoid the issue of disclosure of answer-related information to candidates, all copyright acknowledgements are reproduced online in the Cambridge International
Examinations Copyright Acknowledgements Booklet. This is produced for each series of examinations and is freely available to download at www.cie.org.uk after
the live examination series.
Cambridge International Examinations is part of the Cambridge Assessment Group. Cambridge Assessment is the brand name of University of Cambridge Local
Examinations Syndicate (UCLES), which is itself a department of the University of Cambridge.
5 (a) one mark for name of bus + one mark for description
address bus
data bus
• used to transfer data between the processor and memory/input and output devices
• bidirectional bus
control bus
(ii) the data stored at the address held in MAR is copied into the MDR [1]
(iii) the contents of the Memory Data Register is copied into the Current Instruction
Register [1]
(c) • the MAR is loaded with the operand of the instruction // loaded with 35
• the Accumulator is loaded with the contents of the address held in MAR
// the Accumulator is loaded with the contents of the address 35 [2]
(ii)
Accumulator: 0 1 1 0 1 0 0 1
[1]
explanation
• content of 124 is 0 1 1 1 1 1 1 1
• this is equivalent to 127
• contents of 127 are 0 1 1 0 1 0 0 1 [2]
(iii)
Accumulator: 0 1 0 0 0 0 0 1
[1]
explanation
49 36 0 0
36
37
37
49
50
50
[6]
2 (a)
Processor
Registers
System clock
B Control
unit ALU C
A
Main memory
A ...............................................................................................................................................
B ...............................................................................................................................................
C ...............................................................................................................................................
[3]
(b) State the role of each of the following special purpose registers used in a typical processor.
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
[4]
B = address bus
Memory Data Register – stores the data in transit between memory and other registers //
holds the instruction before it is passed to the CIR
Memory Address Register – stores the address of the memory location which is about to be
accessed [4]
6 (a) Describe the stored program concept for the basic Von Neumann model for a computer
system.
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...............................................................................................................................................[3]
1 ........................................................................................................................................
2 ........................................................................................................................................
3 ........................................................................................................................................
[3]
...........................................................................................................................................
...........................................................................................................................................
.......................................................................................................................................[1]
– control bus
– data bus
– address bus [3]
(ii) generates the timing signals/generates the signals to synchronise events in the
processor / fetch–(decode)–execute cycle [1]
3 (a) Describe how special purpose registers are used in the fetch stage of the fetch-execute cycle.
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...............................................................................................................................................[4]
(b) Use the statements A, B, C and D to complete the description of how the fetch-execute cycle
handles an interrupt.
the address of the Interrupt Service Routine (ISR) is loaded to the Program
A
Counter (PC).
B the processor checks if there is an interrupt.
C when the ISR completes, the processor restores the register contents.
D the register contents are saved.
9 The table shows assembly language instructions for a processor which has one general purpose
register, the Accumulator (ACC) and an index register (IX).
Instruction
Explanation
Op code Operand
LDD <address> Direct addressing. Load the contents of the given address to ACC.
LDX <address> Indexed addressing. Form the address from <address> + the contents of the
index register. Copy the contents of this calculated address to ACC.
STO <address> Store contents of ACC at the given address.
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
JPE <address> Following a compare instruction, jump to <address> if the compare was True.
JPN <address> Following a compare instruction, jump to <address> if the compare was
False.
JMP <address> Jump to the given address.
OUT Output to screen the character whose ASCII value is stored in ACC.
(a) The diagram shows the current contents of a section of main memory and the index register:
60 0011 0010
61 0101 1101
62 0000 0100
63 1111 1001
64 0101 0101
65 1101 1111
66 0000 1101
67 0100 1101
68 0100 0101
69 0100 0011
...
1000 0110 1001
Index register: 0 0 0 0 1 0 0 0
(i) Show the contents of the Accumulator after the execution of the instruction:
LDX 60
Accumulator:
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
.......................................................................................................................................[2]
(ii) Show the contents of the index register after the execution of the instruction:
DEC IX
Index register:
[1]
(b) Complete the trace table on the opposite page for the following assembly language program.
50 LDD 100
51 ADD 102
52 STO 103
53 LDX 100
54 ADD 100
55 CMP 101
56 JPE 58
57 JPN 59
58 OUT
59 INC IX
60 LDX 98
61 ADD 101
62 OUT
63 END
...
100 20
101 100
102 1
103 0
IX (Index Register) 1
ASCII Code 118 119 120 121 122 123 124 125
Character v w x y z { | }
Trace table:
Memory address
Instruction Working ACC IX OUTPUT
address space 100 101 102 103
20 100 1 0 1
50
51
52
53
54
55
[7]
• The Program Counter (PC) holds the address of the next instruction to be fetched
• The address in the Program Counter (PC) is copied to the Memory Address Register
(MAR)
• The Program Counter (PC) is incremented
• The instruction is copied to the Memory Data Register (MDR)
o …. from the address held in the Memory Address Register (MAR)
• The instruction from the Memory Data Register (MDR) is copied to the Current
Instruction Register (CIR)
(b) One mark for each statement or letter in the correct place. [4]
At the end of the cycle for the current instruction the processor checks if there is an interrupt.
If the interrupt flag is set, the register contents are saved, the address of the Interrupt Service
Routine (ISR) is loaded to the Program Counter (PC) and when the ISR completes, the
processor restores the register contents.
Reason:
Address is 60
Contents of the index register is 8
And 60 + 8 = 68 in denary gives the address
The contents of which is 0100 0101 in binary.
(b)
Memory address
Instruction Working OUTPUT
IX
address space ACC
100 101 102 103
20 100 1 0 1
50 20
51 21
52 21
53 100
54 120
55
56
57
59 2
60 20
61 120
62 'x'
63
4 The table shows assembly language instructions for a processor which has one general purpose
register, the Accumulator (ACC) and an index register (IX).
Instruction Explanation
Op code Operand
LDD <address> Direct addressing. Load the contents of the given address to ACC.
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
index register. Copy the contents of this calculated address to ACC.
STO <address> Store contents of ACC at the given address.
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
JPE <address> Following a compare instruction, jump to <address> if the compare was True.
JPN <address> Following a compare instruction, jump to <address> if the compare was False.
OUT Output to screen the character whose ASCII value is stored in ACC.
Index register: 1 1 0 0 1 1 0 1
(a) Show the contents of the index register after the execution of the instruction:
INC IX
Index register:
[1]
(b) Complete the trace table on the opposite page for the following assembly language program.
20 LDX 90
21 DEC ACC
22 STO 90
23 INC IX
24 LDX 90
25 DEC ACC
26 CMP 90
27 JPE 29
28 JPN 31
29 ADD 90
30 OUT
31 ADD 93
32 STO 93
33 OUT
34 END
:
:
90 2
91 90
92 55
93 34
IX 2
ASCII Code 65 66 67 68 69 70 71 72
Character A B C D E F G H
Trace table:
Memory address
Working ACC IX OUTPUT
Instruction
space 90 91 92 93
2 90 55 34 2
20
21
22
23
24
25
26
[7]
(b) [7]
• Instruction 20
• Instructions 21 and 22
• Instruction 23
• Instructions 24 and 25
• Not executing instructions 29 and 30
• Instructions 31 and 32
• Correct output
8 The table shows assembly language instructions for a processor which has one general purpose
register, the Accumulator (ACC) and an Index Register (IX).
Instruction
Explanation
Op code Operand
LDD <address> Direct addressing. Load the contents of the given address to ACC.
Indexed addressing. Form the address from <address> + the
LDX <address> contents of the index register. Copy the contents of this calculated
address to ACC.
STO <address> Store contents of ACC at the given address.
ADD <address> Add the contents of the given address to ACC.
CMP <address> Compare contents of ACC with contents of <address>
Following a compare instruction, jump to <address> if the compare
JPE <address>
was True.
Following a compare instruction, jump to <address> if the compare
JPN <address>
was False.
JMP <address> Jump to the given address.
Output to the screen the character whose ASCII value is stored in
OUT
ACC.
END Return control to the operating system.
Main memory
800 0110 0100
801 0111 1100
802 1001 0111
803 0111 0011
804 1001 0000
805 0011 1111
806 0000 1110
807 1110 1000
808 1000 1110
809 1100 0010
:
:
2000 1011 0101
(a) (i) Show the contents of the Accumulator after execution of the instruction:
LDD 802
Accumulator:
[1]
(ii) Show the contents of the Accumulator after execution of the instruction:
LDX 800
Index Register: 0 0 0 0 1 0 0 1
Accumulator:
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
.......................................................................................................................................[3]
(b) (i) Complete the trace table below for the following assembly language program. This
program contains denary values.
Trace table:
Memory address
ACC OUTPUT
800 801 802 803
40 50 0 90
[4]
.......................................................................................................................................[1]
(ii) One mark for answer and two marks for explanation
Accumulator: 1 1 0 0 0 0 1 0
Memory address
ACC OUTPUT
800 801 802 803
40 50 0 90
40
90 90
90 90
[4]
© UCLES 2016
Compiled By: Absar Moeen Page 96 of 187 of Worksheet
6
5 The table shows assembly language instructions for a processor that has one general purpose
register, the Accumulator (ACC) and an index register (IX).
Instruction
Explanation
Op Code Operand
Direct addressing. Load the contents of the given address to
LDD <address>
ACC.
Index addressing. Form the address from <address> +
LDX <address> the contents of the index register. Copy the contents of this
calculated address to ACC.
Indirect addressing. The address to be used is at the given
LDI <address>
address. Load the contents of this second address to ACC.
ADD <address> Add the contents of the given address to the ACC.
Main memory
(a) (i) Show the contents of the Accumulator after the execution of the instruction:
LDD 102
ACC:
[1]
(ii) Show the contents of the Accumulator after the execution of the instruction:
LDX 101
IX: 0 0 0 0 0 1 0 0
ACC:
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
.......................................................................................................................................[2]
(iii) Show the contents of the Accumulator after the execution of the instruction:
LDI 103
ACC:
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
.......................................................................................................................................[3]
(b) Complete the trace table below for the following assembly language program.
806 END
810 28
811 41
812 0
813 0
Trace table:
Memory address
ACC
810 811 812 813
28 41 0 0
[6]
5 (a) (i)
0 1 1 1 0 0 1 1
[1]
(ii) ONE mark for Accumulator contents, ONE mark for the explanation.
1 0 1 1 0 0 0 1
• Index Register holds the value 4; 101 + 4 = 105 so load data from address 105
[2]
(iii) ONE mark for Accumulator contents, TWO marks for the explanation.
0 1 0 0 1 0 1 1
Memory address
28 41 0 0
28
29
29
41
70
70
[6]
© UCLES 2016
Compiled By: Absar Moeen Page 100 of 187 of Worksheet
8
4 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC) and an Index Register (IX).
Instruction
Op code Op code Explanation
Operand
(mnemonic) (binary)
Immediate addressing. Load the denary number n to
LDM #n 0000 0001
ACC.
Direct addressing. Load the contents of the location
LDD <address> 0000 0010
at the given address to ACC.
Indirect addressing. At the given address is the
LDI <address> 0000 0101 address to be used. Load the contents of this second
address to ACC.
Indexed addressing. Form the address from
<address> + the contents of the Index Register
LDX <address> 0000 0110
(IX). Copy the contents of this calculated address to
ACC.
LDR #n 0000 0111 Immediate addressing. Load number n to IX.
STO <address> 0000 1111 Store the contents of ACC at the given address.
The following diagram shows the contents of a section of main memory and the Index Register (IX).
(a) Show the contents of the Accumulator (ACC) after each instruction is executed.
IX 0 0 0 0 0 0 1 1
Main
(i) LDM #500
Memory
Address contents
ACC ................................................................[1]
495 13
(ii) LDD 500
496 86
ACC ................................................................[1] 497 92
(b) Each machine code instruction is encoded as 16-bits (8-bit op code followed by an 8-bit
operand).
LDM #17
LDX #97
[3]
(c) Using an 8-bit operand, state the maximum number of memory locations, in denary, that can
be directly addressed.
...............................................................................................................................................[1]
0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0
.......................................................................................................................................[2]
05 3F
Write the equivalent assembly language instruction, with the operand in denary.
.......................................................................................................................................[2]
4(a)(i) 500 1
4(a)(ii) 496 1
4(a)(iii) 502 1
4(a)(iv) 86 1
4(b) 3
0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1
0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1
4(c) 256 1
4(d)(i) 07 C2 2
07 1
C2 1
4(d)(ii) LDI 63 2
LDI 1
63 1
5 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Op code Op code Explanation
Operand
(mnemonic) (binary)
Direct addressing. Load the contents of
LDD <address> 0001 0011 the location at the given address to the
Accumulator (ACC).
Indirect addressing. The address to be used is
LDI <address> 0001 0100 at the given address. Load the contents of this
second address to ACC.
Indexed addressing. Form the address from
<address> + the contents of the Index
LDX <address> 0001 0101
Register. Copy the contents of this calculated
address to ACC.
Immediate addressing. Load the denary
LDM #n 0001 0010
number n to ACC.
Immediate addressing. Load denary number n
LDR #n 0001 0110
to the Index Register (IX).
Store the contents of ACC at the given
STO <address> 0000 0111
address.
The following diagram shows the contents of a section of main memory and the Index Register (IX).
(a) Show the contents of the Accumulator (ACC) after each instruction is executed.
IX 0 0 0 0 0 1 1 0
(b) Each machine code instruction is encoded as 16 bits (8-bit op code followed by an 8-bit
operand).
LDM #67
LDX #7
[3]
0 0 0 1 0 1 0 0 0 1 0 1 1 1 1 0
.......................................................................................................................................[2]
16 4D
Write the assembly language for this instruction with the operand in denary.
.......................................................................................................................................[2]
5(a)(iv) 86 1
0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1
0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1
5(c)(i) 14 5E 2
14 1
5E 1
LDR 1
#77 1
5(a)(i) 351 1
5(a)(ii) 355 1
5(a)(iii) 22 1
4 (a) The diagram shows the components and buses found inside a typical Personal Computer
(PC).
General purpose
registers
D
Arithmetic Logic
E F
Unit (ALU)
For each label, choose the appropriate title from the following list. The title for label D is
already given.
• Control bus
• System clock
• Data bus
• Control unit
• Main memory
• Secondary storage
A ...........................................................................................................................................
B ...........................................................................................................................................
C ...........................................................................................................................................
D Address bus
E ...........................................................................................................................................
F ...........................................................................................................................................
[5]
(b) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Op code Op code Explanation
Operand
(mnemonic) (binary)
LDM #n 1100 0001 Immediate addressing. Load number n to ACC.
Direct addressing. Load the contents of the given
LDD <address> 1100 0010
address to ACC.
Relative addressing. Move to the address n locations
LDV #n 1100 0011 from the address of the current instruction. Load the
contents of this address to ACC.
STO <address> 1100 0100 Store the contents of ACC at the given address.
DEC 1100 0101 Decrement the contents of ACC.
Output the character corresponding to the ASCII
OUTCH 1100 0111
character code in ACC.
Following a compare instruction, jump to <address> if
JNE <address> 1110 0110
the compare was False.
JMP <address> 1110 0011 (Unconditionally) jump to the given address.
CMP #n 1110 0100 Compare the contents of ACC with number n.
Complete the trace table for the following assembly language program.
Label Instruction
StartProg: LDV #CountDown
CMP Num1
ASCII code table (selected codes only)
JNE CarryOn
<Space> 3 B C X
JMP Finish
32 51 66 67 88
CarryOn: OUTCH
LDD CountDown
DEC
STO CountDown
JMP StartProg
Finish: LDM #88
OUTCH
END
CountDown: 15
32
51
67
Num1: 32
Trace table:
[5]
(c) The program given in part (b) is to be translated using a two-pass assembler.
The program has been copied here for you. The program now starts with a directive which
tells the assembler to load the first instruction of the program to address 100.
Label
ORG #0100
StartProg: LDV #CountDown
CMP Num1
JNE CarryOn
JMP Finish
CarryOn: OUTCH
LDD CountDown
DEC
STO CountDown
JMP StartProg
Finish: LDM #88
OUTCH
END
CountDown: 15
32
51
67
Num1: 32
On the first pass of the two-pass process, the assembler adds entries to a symbol table.
The following symbol table shows the first eleven entries, part way through the first pass.
The circular labels show the order in which the assembler made the entries to the symbol
table.
Symbol table
StartProg 1 100 2
CountDown 3 UNKNOWN 4
Num1 5 UNKNOWN 6
Finish 9 UNKNOWN 10
Explain how the assembler made these entries to the symbol table.
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...............................................................................................................................................[3]
(d) The assembler software must then complete the second pass building up the executable file.
(i) Name the second table needed when the assembler software carries out the second
pass.
.......................................................................................................................................[1]
Machine code
Instruction Binary Hexadecimal
OUTCH 1100 0111 C7
JNE CarryOn A B
Each of the numbers A and B represents the complete instruction in two bytes, one byte for
the op code and one byte for the operand.
(ii) Use the following instruction set to write the numbers for A and B.
A (binary) ........................................................................................................................
B (hexadecimal) .............................................................................................................
[3]
Instruction
Op code Op code Explanation
Operand
(mnemonic) (binary)
LDM #n 1100 0001 Immediate addressing. Load number n to ACC.
Direct addressing. Load the contents of the given
LDD <address> 1100 0010
address to ACC.
Relative addressing. Move to the address n locations
LDV #n 1100 0011 from the address of the current instruction. Load the
contents of this address to ACC.
STO <address> 1100 0100 Store the contents of ACC at the given address.
DEC 1100 0101 Decrement the contents of ACC.
Output the character corresponding to the ASCII
OUTCH 1100 0111
character code in ACC.
Following a compare instruction, jump to <address> if
JNE <address> 1110 0110
the compare was False.
JMP <address> 1110 0011 (Unconditionally) jump to the given address.
CMP #n 1110 0100 Compare the contents of ACC with number n.
B – E6 68 (1)
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...............................................................................................................................................[2]
(b) (i) Explain the purpose of the Memory Data Register (MDR).
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
.......................................................................................................................................[2]
(ii) Name two registers, other than the MDR, that are used in the fetch-execute cycle.
Register 1 ..........................................................................................................................
Register 2 ..........................................................................................................................
[2]
1 0 0 0 0 1 1 1
.......................................................................................................................................[1]
.......................................................................................................................................[1]
(iii) The current contents of register X stores a two’s complement binary integer.
.......................................................................................................................................[1]
8(c)(i) 135 1
8(c)(ii) 87 1
8(c)(iii) –121 1
4 The table shows assembly language instructions for a processor which has one general purpose
register, the Accumulator (ACC) and an index register (IX).
Instruction
Explanation
Op code Operand
Direct addressing. Load the contents of the location at the given
LDD <address>
address to ACC.
Indexed addressing. Form the address from <address> + the
LDX <address> contents of the Index Register. Copy the contents of this calculated
address to ACC.
LDR #n Immediate addressing. Load the number n to IX.
STO <address> Store contents of ACC at the given address.
ADD <address> Add the contents of the given address to ACC.
INC <register> Add 1 to the contents of the register (ACC or IX).
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
CMP <address> Compare contents of ACC with contents of <address>.
Following a compare instruction, jump to <address> if the compare
JPE <address>
was True.
Following a compare instruction, jump to <address> if the compare
JPN <address>
was False.
JMP <address> Jump to the given address.
OUT Output to the screen the character whose ASCII value is stored in ACC.
END Return control to the operating system.
(a) (i) State what is meant by direct addressing and indirect addressing.
...........................................................................................................................................
...........................................................................................................................................
[2]
(ii) Explain how the instruction ADD 20 can be interpreted as either direct or indirect
addressing.
...........................................................................................................................................
...........................................................................................................................................
[2]
(b) The assembly language instructions in the following table use either symbolic addressing or
absolute addressing.
Tick (3) one box in each row to indicate whether the instruction uses symbolic or absolute
addressing.
ADD 90
CMP found
STO 20
[2]
X 1 0 1 1 1 0 1 0
.......................................................................................................................................[1]
.......................................................................................................................................[1]
.......................................................................................................................................[1]
(d) The current contents of the main memory, Index Register (IX) and selected values from the
ASCII character set are provided with a copy of the instruction set.
Complete the trace table for the given assembly language program.
[8]
Direct addressing:
• 20 is the address of the data
Indirect addressing:
• 20 is an address which holds the address where the data is stored
ADD 90 9
CMP found 9
STO 20 9
4(c)(i) 186 1
4(c)(ii) BA 1
4(c)(iii) –70 1
Direct addressing
• The operand is the address where the data is stored
Indirect addressing
• The operand is an address, that address holds another address where
the data is stored
71 *
72 130
73 0
74 1
75 1
76 1
77 133
78
79
81 1
82
83
74 2
75 2
76 2
77 130
78
79
80 *
81 2
82
83
84
3 The following table shows assembly language instructions for a processor which has one general
purpose register, the Accumulator (ACC) and an Index Register (IX).
Instruction
Explanation
Op code Operand
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC.
LDX <address> Indexed addressing. Form the address from <address> + the contents of the
Index Register. Copy the contents of this calculated address to ACC.
LDR #n Immediate addressing. Load the number n to IX.
STO <address> Store contents of ACC at the given address.
ADD <address> Add the contents of the given address to ACC.
INC <register> Add 1 to the contents of the register (ACC or IX).
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
CMP <address> Compare contents of ACC with contents of <address>.
JPE <address> Following compare instruction, jump to <address> if the compare was True.
JPN <address> Following compare instruction, jump to <address> if the compare was False.
JMP <address> Jump to the given address.
OUT Output to the screen the character whose ASCII value is stored in ACC.
END Return control to the operating system.
(a) (i) State what is meant by absolute addressing and symbolic addressing.
...........................................................................................................................................
...........................................................................................................................................
[2]
(ii) Give an example of an ADD instruction using both absolute addressing and symbolic
addressing.
(b) (i) State what is meant by indexed addressing and immediate addressing.
...........................................................................................................................................
...........................................................................................................................................
[2]
X 1 1 0 0 0 0 0 1
...................................................................................................................................... [1]
...................................................................................................................................... [1]
...................................................................................................................................... [1]
(d) The current contents of the main memory, Index Register (IX) and selected values from the
ASCII character set are:
100 2
101 302
102 303
103 303
104 0
105 303
IX 1
Instruction
Explanation
Op code Operand
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC.
LDX <address> Indexed addressing. Form the address from <address> + the contents of the
Index Register. Copy the contents of this calculated address to ACC.
LDR #n Immediate addressing. Load the number n to IX.
STO <address> Store contents of ACC at the given address.
ADD <address> Add the contents of the given address to ACC.
INC <register> Add 1 to the contents of the register (ACC or IX).
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
CMP <address> Compare contents of ACC with contents of <address>.
JPE <address> Following a compare instruction, jump to <address> if the compare was True.
JPN <address> Following a compare instruction, jump to <address> if the compare was False.
JMP <address> Jump to the given address.
OUT Output to the screen the character whose ASCII value is stored in ACC.
END Return control to the operating system.
Complete the trace table for the given assembly language program.
[7]
4 A student has written the steps of the fetch stage of the fetch-execute (FE) cycle in register transfer
notation. The student has made some errors.
Line 2 PC PC + 1
Line 4 CIR PC
(a) Identify the line numbers of three errors that the student has made. Write the correct notation
for each error.
[3]
1 ........................................................................................................................................
2 ........................................................................................................................................
3 ........................................................................................................................................
[3]
(ii) Explain how interrupts are handled during the fetch-execute cycle.
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...................................................................................................................................... [5]
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11
Bus Description
Control bus
Unidirectional
(one direction)
Address bus
Bidirectional
(two directions)
Data bus
[2]
Indexed addressing:
• The address to be used is formed by:
operand + the contents of the Index Register (IX)
Immediate addressing:
• The operand is not an address // the operand is the actual value to be
loaded
3(c)(i) 193 1
3(c)(ii) C1 1
3(c)(iii) –63 1
41
43 302
44
45
47 2
48 1
49 1
50 2
51
41
42
43 303
44
45
46 +
47 1
48 0
49 0
50 3
51
41
54
1 MAR ← [PC]
3 MDR ← [ [MAR] ]
4 CIR ← [MDR]
2 PC ← [PC] + 1
For example:
• Hardware fault // Example of hardware fault
• I/O request // Example of I/O request
• Program/software error // Example of software error
• End of a time-slice
(a) The table contains some of the tasks performed by a two-pass assembler.
Tick (✓) one box in each row to indicate whether the task is performed at the first or second
pass. The first row has been completed for you.
(b) The processor’s instruction set can be grouped according to their function. For example, one
group is modes of addressing.
1 ................................................................................................................................................
...................................................................................................................................................
2 ................................................................................................................................................
...................................................................................................................................................
[2]
(c) The table shows assembly language instructions for a processor which has one general
purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Op code Operand
LDM #n Immediate addressing. Load the denary number n to ACC.
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC.
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
Index Register. Copy the contents of this calculated address to ACC.
LDR #n Immediate addressing. Load the denary number n to IX.
STO <address> Store contents of ACC at the given address.
ADD <address> Add the contents of the given address to ACC.
INC <register> Add 1 to the contents of the register (ACC or IX).
CMP #n Compare contents of ACC with denary number n.
JPE <address> Following a compare instruction, jump to <address> if the compare was True.
JPN <address> Following a compare instruction, jump to <address> if the compare was False.
JMP <address> Jump to the given address.
OUT Output to screen the character whose ASCII value is stored in ACC.
END Return control to the operating system.
The current contents of the main memory, Index Register (IX) and selected values from the
ASCII character set are:
IX 0
© UCLES 2019 9608/11/M/J/19
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11
Trace the program currently in memory using the following trace table. The first instruction
has been completed for you.
65 67 69 69 68 33 0
20 0
[8]
5(a) 1 mark for two correct ticks, 2 marks for three correct ticks 2
Expansion of macros ✓
Removal of comments ✓
• Data movement
• Input and output of data
• Arithmetic operations
• Jump instructions
• Compare instructions
Memory address
Instruction
IX OUTPUT
address ACC 100 101 102 103 104 300 301
65 67 69 69 68 33 0
20 0
21 0
22
23
28 65
29 A
30 0
31 1
32 1
33 1
34
35
22
24 67
25 100
26 d
27
30 1
31 2
32 2
33 2
34
36
01 MAR [PC]
02 PC [PC] - 1
03 MDR [MAR]
04 CIR [MAR]
Identify the line number of each error and give the correction.
Correction .................................................................................................................................
Correction .................................................................................................................................
Correction .................................................................................................................................
[3]
(b) A processor’s instruction set can be grouped according to their function. For example, one
group is the input and output of data.
1 ................................................................................................................................................
...................................................................................................................................................
2 ................................................................................................................................................
...................................................................................................................................................
[2]
(c) The following table shows assembly language instructions for a processor which has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Op code Operand
LDM #n Immediate addressing. Load the denary number n to ACC
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
Index Register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the denary number n to IX
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP #n Compare contents of ACC with denary number n
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
The current contents of the main memory, Index Register (IX) and selected values from the
ASCII character set are:
IX 0
© UCLES 2019 9608/12/M/J/19
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7
Trace the program currently in memory using the following trace table.
The first instruction has been completed for you.
2 5 0 4 64 0
50 0
[8]
• Data movement
• Arithmetic operations
• (Unconditional and conditional) jump instructions
• Compare instructions
• Modes of addressing
(a) The diagram has registers used in Von Neumann architecture on the left and descriptions on
the right.
Draw one line to match each register with its correct description.
Register Description
Program Counter
Stores the address of the next instruction to
be read
[4]
(b) Many components of the computer system transfer data between them using buses. One
example of a bus is an address bus.
(i) Name two other buses that exist within a computer and give the purpose of each.
Bus 1 .................................................................................................................................
Purpose .............................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
Bus 2 .................................................................................................................................
Purpose .............................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
[4]
(ii) State the benefit of increasing the address bus width from 16 bits to 32 bits.
...........................................................................................................................................
..................................................................................................................................... [1]
The processor’s instruction set can be put into several groups. One of these groups is
........................................................... .
[3]
Register Description
1(b)(i) 1 mark for naming, 1 mark for purpose for each bus 4
• Data bus
• Carries data between the processor and memory / carries data that is
currently being processed.
• Control bus
• Transmits signals between the control unit and the other components
The processor’s instruction set can be put into several groups. One of these
groups is data movement // input and output // arithmetic operations //
jump instructions // compare instructions // modes of addressing.
6 A processor has one general purpose register, the Accumulator (ACC), and an Index Register
(IX).
(a) The table gives three assembly language instructions for loading data into the ACC. It also
identifies the addressing mode used for each instruction.
(i) State the contents of the Accumulator after each of the instructions A, B and C are run.
A ........................................................................................................................................
...........................................................................................................................................
B ........................................................................................................................................
...........................................................................................................................................
C ........................................................................................................................................
...........................................................................................................................................
[3]
1 ........................................................................................................................................
2 ........................................................................................................................................
[2]
(b) The ACC is a general purpose register. The IX is a special purpose register.
Identify two other special purpose registers used in the fetch-execute cycle and describe
their role in the cycle.
Register 1 .................................................................................................................................
Role ..........................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
Register 2 .................................................................................................................................
Role ..........................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
[4]
© UCLES 2020 9608/11/M/J/20
Compiled By: Absar Moeen Page 147 of 187 of Worksheet
9608/11 Cambridge International AS & A Level – Mark Scheme May/June 2020
PUBLISHED
C: The data in the memory location found by adding the contents of the IX to
193
• Indirect
• Relative
6(b) 1 mark for correctly naming register, 1 mark for appropriate role 4
• Program counter // PC
• Stores the address of the next instruction to be fetched
The following three statements are used to complete the sequence of steps.
A If it is already in the symbol table, it checks to see if the absolute address is known
B When it meets a symbolic address, it checks to see if it is already in the symbol table
C If it is known, it is entered
Write one of the letters A, B or C in the appropriate step to complete the sequence.
2. .........................
4. .........................
5. .........................
The table shows the denary values for three assembler op codes.
(i) Convert the denary value for the op code LDD into 8‑bit binary.
[1]
(ii) Convert the denary value for the op code STO into hexadecimal.
..................................................................................................................................... [1]
(iii) State why the denary value for the op code ADD cannot be represented in 8‑bit two’s
complement form. Justify your answer.
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
..................................................................................................................................... [2]
(c) The table shows part of the instruction set for a processor. The processor has one general
purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Op code Operand
LDM #n Immediate addressing. Load the denary number n to ACC
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
Index Register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the denary number n to IX
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare contents of the address given with the contents of ACC
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
OUT Output to screen the character whose ASCII value is stored in ACC
END Return control to the operating system
Complete the trace table for the following assembly language program. The first instruction
has been completed for you.
23 LDD 100 20 0
24 ADD 101
25 STO 100
26 LDD 103
27 INC ACC
28 STO 103
29 JMP 20
30 END
100 1
101 2
102 3
103 0
[6]
© UCLES 2020 9608/12/M/J/20 [Turn over
Compiled By: Absar Moeen Page 152 of 187 of Worksheet
9608/12 Cambridge International AS & A Level – Mark Scheme May/June 2020
PUBLISHED
5(a) 1 mark for one letter in the correct place, 2 marks for all three correct 2
2 B
4 A
5 C
5(b)(i) 11000010 1
5(b)(ii) CD 1
• The maximum range for an 8-bit two's complement binary number is −128
to +127
• … 200 is outside of the maximum range
1 2 3 0
20 0
21
22
23 1
24 3
25 3
26 0
27 1
28 1
29
20 1
21
22
23 3
24 5
25 5
26 1
27 2
28 2
29
20 2
21
22
30
4 The following table shows assembly language instructions for a processor that has one general
purpose register, the Accumulator (ACC).
Instruction
Explanation
Op code Operand
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC.
LDM #n Immediate addressing. Load the denary number n to ACC.
Indirect addressing. The address to be used is at the given address. Load
LDI <address>
the contents of this second address to ACC.
CMP <address> Compare the contents of ACC with <address>.
SUB <address> Subtract the contents of the given address from the contents of ACC.
OUT Output to screen the character whose ASCII value is stored in ACC.
JPE <address> Following a compare instruction, jump to <address> if the compare was True.
Address Instruction
100 LDD 200
101 ADD 201
102 ADD 202
103 SUB 203
104 STO 204
105 END
200 10
201 20
202 5
203 6
204
205
Tick (✓) one box to indicate which one of the following statements is true after program
execution.
Address Instruction
100 LDM #120
101 ADD 121
102 SUB 122
103 STO 120
104 END
120 10
121 2
122 4
123 6
124 8
125 10
Tick (✓) one box to indicate which one of the following statements is true after program
execution.
Address Instruction
150 LDI 200
151 ADD 200
152 ADD 201
153 STO 205
154 END
200 202
201 203
202 201
203 200
204
205
Tick (✓) one box to indicate which one of the following statements is true after program
execution.
(d) Identify two modes of addressing that are not used in parts (a), (b) or (c).
1 ................................................................................................................................................
2 ................................................................................................................................................
[2]
Tick (✓) one box on each row to indicate the appropriate instruction group for each assembly
language instruction.
STO 120
JPE 200
ADD 3
LDD 20
INC ACC
OUT
[3]
• Indexed
• Relative
STO 120
JPE 200
ADD 3
LDD 20
INC ACC
OUT
The Von Neumann model for a computer system uses the ....................................... program
concept.
....................................... it.
The processor uses several ....................................... to store the data and instructions from
the program because they can be accessed faster than main memory.
[6]
(b) The following table shows assembly language instructions for a processor that has one
general purpose register, the Accumulator (ACC).
Instruction
Explanation
Op code Operand
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC.
LDM #n Immediate addressing. Load the denary number n to ACC.
Indirect addressing. The address to be used is at the given address. Load the
LDI <address>
contents of this second address to ACC.
STO <address> Store contents of ACC at the given address.
CMP <address> Compare the contents of ACC with the contents of <address>.
OUT Output to screen the character whose ASCII value is stored in ACC.
JPE <address> Following a compare instruction, jump to <address> if the compare was True.
Following a compare instruction, jump to <address> if the compare was
JPN <address>
False.
END Return control to the operating system.
80 10
81 2
82 0
Trace the program currently in memory using the following trace table.
The first instruction has been completed for you.
10 2 0
50 10
[5]
Tick (✓) one box in each column to identify the appropriate instruction group for each of
the three assembly language instructions.
Data movement
Arithmetic operations
Compare instructions
[3]
Stored
Memory
Fetches
Decodes
Executes
Registers
The processor fetches each instruction, decodes it and then executes it.
The processor uses several registers to store the data and instructions from
the program because they can be accessed faster than main memory.
Data movement
Arithmetic operations
Compare instructions
3 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Op code Operand
LDD <address> Direct addressing. Load the content of the location at the given
address to ACC.
LDI <address> Indirect addressing. The address to be used is at the given
address. Load the contents of this second address to ACC.
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
CMP <address> Compare the contents of ACC with the contents of <address>.
JMP <address> Jump to the given address.
JPE <address> Following a compare instruction, jump to <address> if the
compare was True.
STO <address> Store the contents of ACC at the given address.
END Return control to the operating system.
Address Instruction
100 LDD 200
101 CMP 201
102 JPE 106
103 DEC ACC
104 STO 200
105 JMP 101
106 END
200 2
201 0
202 200
(a) Trace the program currently in memory using the following trace table.
Memory address
Instruction
ACC
address
200 201 202
2 0 200
[3]
(b) The instruction in memory address 100 needs to be changed. It needs to use indirect
addressing to load the contents of memory address 200.
............................................................................................................................................. [1]
© UCLES 2021 9608/11/M/J/21 [Turn over
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8
(c) Each instruction in the assembly language program is encoded in 16 bits (8-bit op code
followed by an 8-bit operand).
[1]
(ii) State the maximum number of op codes that can be represented using eight bits.
..................................................................................................................................... [1]
Identify three condition flags that can be set in the status register.
1 ................................................................................................................................................
2 ................................................................................................................................................
3 ................................................................................................................................................
[3]
Memory Address
Instruction
ACC
Address
200 201 202
2 0 200
100 2
101
102
103 1
104 1
105
101
102
103 0
104 0
105
101
102
106
3(c)(ii) 256 1
e.g.
• Zero
• Carry
• Overflow
• Sign/negative
• Compare results
• Parity
2 The following diagram shows four register notations and seven descriptions.
Draw one line from each register notation to its most appropriate description.
3 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Op code Operand
Direct addressing. Load the contents of the location at the
LDD <address>
given address to ACC.
Indirect addressing. The address to be used is at the given
LDI <address>
address. Load the contents of this second address to ACC.
STO <address> Store the contents of ACC at the given address.
Address Instruction
50 LDI 103
51 CMP 101
52 JPE 59
53 ADD 102
54 STO 102
55 LDD 100
56 INC ACC
57 STO 100
58 JMP 51
59 ADD 102
60 STO 102
61 END
100 1
101 3
102 0
103 100
© UCLES 2021 9608/12/M/J/21
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5
(a) Trace the program currently in memory using the following trace table.
Memory address
Instruction
ACC
address 100 101 102 103
1 3 0 100
[5]
(b) The instruction in memory address 50 needs to be changed to use direct addressing to load
the contents of the memory location at address 100.
............................................................................................................................................. [1]
(c) Each instruction in the assembly language program is encoded in 16 bits (8-bit op code
followed by an 8-bit operand).
[1]
..................................................................................................................................... [1]
(d) The assembly language program uses direct and indirect addressing.
1 ................................................................................................................................................
2 ................................................................................................................................................
[2]
Memory Address
Instruction
ACC
Address 100 101 102 103
1 3 0 100
50 1
51
52
53 1
54 1
55 1
56 2
57 2
58
51
52
53 3
54 3
55 2
56 3
57 3
58
51
52
59 6
60 6
61
3(c)(ii) 3B 1
• Immediate
• Indexed
• Relative
6 (a) Complete the following sentences that describe parts of a processor in a Von Neumann
model for a computer system.
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
............................................................................................................................................. [5]
8 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Explanation
Op code Operand
ADD <address> Add the contents of the given address to the ACC
Address Instruction
150 13
151 23
152 11
153 0
160 150
[4]
The width of the address bus determines the number of directly accessible
memory locations.
The control unit sends signals on the control bus to direct the operation of
system components.
Instruction
ACC Memory address
address
150 151 152 153 160
13 23 11 0 150
130 13
131 13
132 13
133 150
134 151
135 151
136
130 23
131 36
132 36
133 151
134 152
135 152
136
4 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).
Instruction
Op Explanation
Operand
Code
SUB <address> Subtract the contents of the given address from the ACC
DEC <register> Subtract 1 from the contents of the register (ACC or IX)
(a) The instructions in the processor’s instruction set can be grouped according to their function.
(i) Identify three different instruction groups from the instructions given in the table.
1 ........................................................................................................................................
2 ........................................................................................................................................
3 ........................................................................................................................................
[3]
..................................................................................................................................... [1]
(b) The following are four special purpose registers used in the processor:
Describe the purpose of any three registers from the four given.
Register 1 .................................................................................................................................
Description ................................................................................................................................
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Register 2 .................................................................................................................................
Description ................................................................................................................................
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Register 3 .................................................................................................................................
Description ................................................................................................................................
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[6]
• Compare instructions
• Arithmetic operations
• Data movement
4(b) 1 mark per bullet point to max 2 per register, max 6 in total 6
Program Counter
• Points to the address ...
• ... of the next instruction to be fetched
• So the address can be transferred to/from the MAR