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vlsi verification testing

vlsi verification testing

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12 views

vlsi verification testing

vlsi verification testing

Uploaded by

abdulnayeemssmrvpu
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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M.Tech.

in VLSI Design and Embedded Systems

VLSI DESIGN VERIFICATION AND TESTING

Course Code: 19EC2205 L P C


3 0 3
Prerequisites: Digital Design through Verilog
Course Outcomes: At the end of the course the student will be able to
CO1: Outline the concepts of verification methodologies.
CO2: Explain the concepts of various data types
CO3: Develop test bench environment for Design under Test
CO4: Summarize the System Verilog assertions
CO5: Describe the applications of randomization techniques

UNIT-I 10 Lectures
Verification guidelines
Verification Process, Basic Test bench functionality, directed testing, Methodology basics,
Constrained-Random stimulus, Functional coverage, Test bench Components Layered test
bench, Building layered test bench, Simulation environment phases, Maximum code reuse,
Test bench performance.

Learning outcomes: At the end of this unit, the student will be able to
1. Discuss basic test bench functionality (L2)
2. Compare directed and random test cases (L5)
3. Analyze test-bench performance (L4)

UNIT-II 10 Lectures
Data types
Built-in data types, Fixed-size arrays, Dynamic arrays, Queues, Associative Arrays, Linked
lists, Array methods, choosing a storage type, creating new types with typedef, Creating
user-defined structures, Type conversion, Enumerated types, Constants, strings, expression
width.

Learning outcomes: At the end of this unit, the student will be able to
1. Describe array concepts (L2)
2. Discuss array methods (L2)
3. Interpret Enumerated data types (L2)

36
M.Tech. in VLSI Design and Embedded Systems

UNIT-III 10 Lectures
Procedural statements and routines
Procedural statements, tasks, functions and void Functions, Routine arguments, returning
from a routine, local data storage, Time values Connecting the test bench and design:
Separating the test bench and design, Interface constructs, Stimulus timing, Interface
driving and sampling, connecting it all together, Top-level scope, Program – Module
interactions.

Learning outcomes: At the end of this unit, the student will be able to
1. Differentiate task and functions (L2)
2. Develop test bench environment (L6)
3. Describe Top-level scopes (L2)

UNIT-IV 10 Lectures
System Verilog Assertions
Basic OOP: Introduction, first class, define a class, OOP terminology, Creating new
objects, Object de-allocation, Using objects, Static variables vs. Global variables, Class
routines, Defining routines, outside of the class, Scoping rules, Using one class inside
another, Understanding dynamic objects, Copying objects, Public vs. private, Straying off
course, building a test bench.

Learning outcomes: At the end of this unit, the student will be able to
1. Discuss basic OOP terminology (L2)
2. Illustrate concepts of class methods (L3)
3. Describe dynamic objects (L2)

UNIT-V 10 Lectures
Randomization
Introduction, randomization, Randomization in SystemVerilog, Constraint details, solution
probabilities, Controlling multiple constraint blocks, Valid constraints, In-line constraints,
The pre_randomize and post_randomize functions, Constraints tips and techniques,
common randomization problems.

Learning outcomes: At the end of this unit, the student will be able to
1. Summarize the concept of randomization (L2)
2. Illustrate Randomization in SystemVerilog (L3)
3. Differentiate pre and post randomization techniques (L2)

37
M.Tech. in VLSI Design and Embedded Systems

Text Books
Spear, Chris. SystemVerilog for verification: a guide to learning the testbench
language features, 2nd Edition Springer Science & Business Media, 2008.

References
1. IEEE 1800-2009 standard (IEEE Standard for SystemVerilog, Unified
Hardware Design, Specification, and Verification Language).
2. System Verilog website :www.systemverilog.org
3. OVM, UVM(on top of SV) www.verificationacademy.com

***

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