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Interrupts

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12 views

Interrupts

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aloneboysandeep17
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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The concept of interrupts

• When the processor is interrupted, it suspends its current activity


and executes the Interrupt service routine corresponding to the
interrupt request.

• After that, it resumes the previous activity.

• Interrupts can occur at any time.


Interrupts of 8086
 8086 has hardware interrupts, software interrupts and error generated
interrupts.

 For the three cases mentioned, the interrupting mechanism is different,


but the way the processor responds is similar.

 An interrupt is not very different from a CALL instruction in its


philosophy, but there are differences in the way it is handled and
processed.
Interrupt Response of 8086
 After every instruction cycle, the processor checks if any interrupt is
awaiting service.

 If, it finds an interrupt request, then decides to acknowledge and service it.

 The response is the following:


Interrupt response-steps
 i) The flag register is pushed on to the stack.
 ii) The interrupt flag is disabled/resets (IF = 0).
 iii) The trap flag is disabled/ resets (TF = 0).
 iv) The CS register is pushed on to the stack.
 v) The IP register is pushed on to the stack.
 vi) Control is transferred to the location in which the corresponding
‘Interrupt Service Routine’ (ISR) is stored. This in effect, would be a far
jump.
Interrupt response-steps..contd’
 vii) The program corresponding to the ISR is executed. The last
instruction in the ISR will be IRET.
 viii) Then IP is popped off the stack.
 ix) CS is popped off the stack.
 x) The Flag register is popped off the stack.
 xi) Control returns to the point at which it had left off .

 Steps i to vi constitute the actions before getting to the interrupt service


routine, and steps viii to xi occur on returning from the interrupt.
Steps in processing an interrupt request
Interrupt Service Routine and Interrupt Vector
 When an interrupt occurs, the processor suspends the execution of its
current task and takes on another task as required by the interrupting
source.

 This program, or routine as it may be called, is designated as an ‘interrupt


service routine’(ISR) or interrupt handler.

 The address of an ISR is called its ‘interrupt vector’.


Interrupt Vector Table
 The 8086 has 256 interrupt vectors and since each vector is specified by 4
bytes, it implies that 256 × 4 = 1024 bytes (1K) of memory are allocated to
store the interrupt vectors.

 These 256 vectors are stored in a table called the ‘Interrupt Vector Table’
(IVT) in system RAM from locations 00000 to 003FFH i.e., upto 0000: 03FF.
Interrupt vector table of 8086 A typical interrupt vector (4 bytes)
Example

 Find the address (in the IVT) of the interrupt vector of INT 61H. Find the
physical address of the ISR corresponding to this interrupt if the vector is
0F00:9872.
Example -solution
• The type number of the interrupt is 61H = 97 in decimal.
• The address of the interrupt vector is 97x4 = 388 = 184H.
• Thus, the interrupt vector is to be stored in the IVT in location 0000:0184 onwards.
• For the ISR, the CS value is 0F00H and the IP value is 9872H. The part of the interrupt vector
table which has these vectors stored is shown.
Dedicated Interrupt Types
INT 0 (Divide by Zero Error)
 The interrupt with type number 0 is dedicated to the ‘divide by zero’ error.
This interrupt is an ‘error generated’ interrupt (also an ‘exception’).

 On division, if the quotient register is not large enough to contain the


quotient, this interrupt is generated automatically.

 Dedicating Type 0 for this case means that the corresponding interrupt
vector in the interrupt vector table is available at 0000:0000.
INT 1 (Single Stepping)

 This type number is dedicated for ‘single stepping’ or ‘trace’.

 Single stepping is an important idea in debugging.

 During logical debugging of our programs, we would like to stop after the
execution of each instruction and check the contents of registers, memory
and so on.
 For this , the TRAP flag needs to be set.
INT 2 (Non Maskable Interrupt)

 This interrupt corresponds to the vector (pointer) of the hardware


interrupt NMI.

 When an interrupt is received on the pin NMI (Non Maskable Interrupt)


of the processor, a type 2 interrupt occurs – this means that the ISR for
NMI must be written in the address pointed by the corresponding IVT
content.
INT 3 (Breakpoint Interrupt)

 This is the breakpoint interrupt, which is useful for de-bugging.

 It need to set breakpoints (stop after executing a group of instructions)


and check the content of registers and memory after executing
instructions up to the breakpoint.

 The breakpoint interrupt is special in that it is a single byte instruction


with the code CCH.
INT 4/INTO (Overflow Interrupt)

 This interrupt corresponds to the overflow flag. If the overflow flag is set,
this interrupt occurs, but not automatically.

 An instruction INTO (interrupt on overflow) must be written after the


program segment which is likely to cause the overflow flag (OF) to be set.
Interrupt Vector Table Allocation
Hardware Interrupts
 Now we will examine the hardware interrupt pins of 8086.

 There are two pins on which interrupt requests can be received – they are
the INTR pin and the NMI pin.
NMI (Non Maskable Interrupt)
 This is a positive edge triggered interrupt, but it is also required to have a
duration in the high state of more than two clock cycles.

• This is a non maskable interrupt, in that t does not depend on the setting
of the interrupt flag (IF). It cannot be masked or prevented from being
activated.

 It is a Type 2 interrupt,
INTR

 This is the non-vectored interrupt pin of the 8086, which means that
when an interrupt request is received on this pin, it does not get
automatically directed towards any particular entry in the IVT.

 The interrupt flag (IF) is required to be set for an interrupt request on the
INTR line to be honored.

 INTR is a high level triggered interrupt.


Response to an INTR request
 The INTA line is lowered and an ‘Interrupt acknowledge machine cycle is
started .

 In the first machine cycle, the data bus is floated.

 During the first machine cycle, the interrupting device places the ‘type
number’ of the interrupt on the lower data lines (D0 to D7), which comes
out of the float condition.
Interrupt acknowledge machine cycle of the 8086
Can We Consider the Reset Pin as an
Interrupt Pin?
Priority of Interrupts

 When many interrupts occur at the same time, which source gets its
request honored first? The processor decides the priority. The order of
priority is set in the following manner:

 i) Type 0, INT (n), INT O – get the highest priority,


 ii) NMI,
 iii) INTR
 Iv) Type 1 – gets the lowest priority.
Software Interrupts

• When an interrupt is initiated by an instruction,


it is called a software interrupt. The format of this instruction is:
INT type number

• The type numbers can vary from 0 to 255.

 Thus, the user can write any procedure as an ISR, store it in some address
in memory and call it by using the instruction INT n.
Interrupt Vector Table Allocation
What Is the Size of an Interrupt
Instruction?
Thank you

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