Lab 3
Lab 3
Group No
Name Reg. No Viva / Lab Analysis of Modern Tool Ethics and Individual Total
Performance data in Lab Usage Safety and Team marks
Report Work Obtained
Prelab:
1. Design the practical circuits given in Task 1 and Task 2 by giving the truth table of the problems and
then giving the circuit (logic diagram) for the designs
Task No 1 (4)
5V
Logic Circuit
0 0 0 0 1
0 0 1 0 1
0 1 0 0 1
0 1 1 0 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0
Verilog Code
endmodule
module testAND3;
reg a, b, c;
initial
begin
end
endmodule
Simulation:
Proteus SS
Design a three-way switch for lighting a bulb. Suppose the Switch A is installed at the entrance of the room,
switch B is installed to the bedside table, Switch C is installed outside the room. Now three way switching
can facilitate the switching ON/OFF from any location. The mechanism is such that if a single switch is on
the bulb should be ON. Now if the second switch is turned on the bulb if switched on earlier is switched off.
If two switches are already on and third switch is turned on then it should switch on the bulb. Implement
with basic gates.
Truth Table
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Proteus SS
module
task1(out1,
in3;
output out1;
mod
ule
test
XO
R3;
reg
a, b,
c;
wire out11;
initial
begin
end
endmodule
Hardware Implementation
Task No 3 (2)
The system is a speed warning device. It receives, on two lines, an indication of the speed limit on the
highway. There are three possible values 45, 55, or 65 MPH. It receives from the automobile, on two other
lines, an indication of speed of the vehicle. There are four possible values under 45, between 46 and 55,
between 56 and 65, and over 65 MPH. It produces two outputs. The first f, indicates whether the car is going
above the speed limit. The second g, indicates that the car is driving at “dangerous speed” – defined as either
over 65 MPH or more than 10 MPH above the speed limit. Show how each of the inputs and outputs are
coded (in terms of binary values) and complete the truth table for the system.
Solution:
Speed limits:
Speed Ranges:
00 00 0 0
00 01 1 0
00 10 1 1
00 11 1 1
01 00 0 0
01 01 0 0
01 10 1 0
01 11 1 1
10 00 0 0
10 01 0 0
10 10 0 0
10 11 1 1
Conclusion:
We learned the practical uses of GATES in this lab and implemented them on hardware as well as simulated
them on software. We also wrote the verilog codes and made truth tables in all cases.