Department of Electrical Engineering

Faculty Member: Habeel Ahmad Dated: October 22, 2023

Semester: 3rd Section: BEE 14-A

Group No.:09

EE-221: Digital Logic Design

Lab 6: Binary to Gray and Gray to Binary Code Conversion

PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7

Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performance of data in Tool Usage Safety and Team marks
Lab Report Work Obtained

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

ABDULLAH 413132
MUNIR

AHMAD HUSSAIN 404302

RAYYAN NAEEM 414044

MUZAFFAR

AWAIS ASGHAR 427265

EE-221: Digital Logic Design Page 1

Lab6: Part (a): Binary to Gray and Gray to Binary Code Conversion

Lab6: Part (b): Gate-level Modeling in Verilog

This Lab has been divided into two parts:

In first part you are required to design and implement a binary to gray and gray to binary code
converter. You will be cascading these two converters thus implementing a binary to gray coder
and decoder (gray to binary).

The next part is the Verilog Modeling and Simulation of the Circuit you implemented in you first
lab.

Objectives:

✓ Understand steps involved in design of combinational circuits

✓ Understand binary codes for decimals and their hardware realization
✓ Write code for combinational circuits using Verilog Gate Level Modeling
✓ Design a circuit in Verilog by calling different modules

Lab Instructions

✓ This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
✓ The lab report will be uploaded on LMS three days before scheduled lab date. The students
will get hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit
it with teacher/lab engineer for necessary evaluation. Alternately each group to upload
completed lab report on LMS for grading.
✓ The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining functional
verification)
✓ Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit
will simplify trouble-shooting process.
✓ After the lab, students are expected to unwire the circuit and deposit back components before
leaving.
✓ The students will complete lab task and submit complete report to Lab Engineer before
leaving lab.
✓ The Total duration for the lab is 3 hrs. After lab duration, a deduction of 5 marks per
day will be done for late submission.
✓ A lab with in-complete lab tasks will not be accepted.
✓ There are related questions at the end of this activity. Give complete answers.

EE-221: Digital Logic Design Page 2

Pre-Lab Tasks: (To be done before coming to the lab) (2 marks)
1. What do you mean by binary codes for the decimal digits? Give some examples and codes
(tables) for the decimal digits.
Answer:
In the coding, when numbers, letters or words are represented by a specific group of symbols,
it is said that the number, letter or word is being encoded. The group of symbols is called as a
code. The digital data is represented, stored and transmitted as group of binary bits. This
group is also called as binary code. The binary code is represented by the number as well as
alphanumeric letter.

DECIMAL BCD BCD EXCESS-3

8421 2421
0 0000 0000 0011
1 0001 0001 0100
2 0010 0010 0101
3 0011 0011 0110
4 0100 0100 0111
5 0101 1011 1000
6 0110 1100 1001
7 0111 1101 1010
8 1000 1110 1011
9 1001 1111 1100

Binary Codes are different encoding techniques to convert numbers into a form that can be understood
by the computers in the form 0f 0’s and 1’s.

Examples are:

• BCD (Binary Coded Decimal)

• EBCDIC (Extended Binary coded Decimal Interchange Code)
• ASCII (American Standard Code for Information Interchange)

After k mapping and simplification, we arrive at following expressions.

W= A

X= A’B + AB’, or we can say X= A xor B

Y= B’C + BC’, or we can say Y= B xor C

Z= C’D + CD’, or we can say Z= C xor D

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Dec Binary Gray Dec Gray Binary

A B C D W X Y Z W X Y Z A B C D
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1 2 0 0 1 1 0 0 1 0
3 0 0 1 1 0 0 1 0 3 0 0 1 0 0 0 1 1
4 0 1 0 0 0 1 1 0 4 0 1 1 0 0 1 0 0
5 0 1 0 1 0 1 1 1 5 0 1 1 1 0 1 0 1
6 0 1 1 0 0 1 0 1 6 0 1 0 1 0 1 1 0
7 0 1 1 1 0 1 0 0 7 0 1 0 0 0 1 1 1
8 1 0 0 0 1 1 0 0 8 1 1 0 0 1 0 0 0
9 1 0 0 1 1 1 0 1 9 1 1 0 1 1 0 0 1
10 1 0 1 0 1 1 1 1 10 1 1 1 1 1 0 1 0
11 1 0 1 1 1 1 1 0 11 1 1 1 0 1 0 1 1
12 1 1 0 0 1 0 1 0 12 1 0 1 0 1 1 0 0
13 1 1 0 1 1 0 1 1 13 1 0 1 1 1 1 0 1
14 1 1 1 0 1 0 0 1 14 1 0 0 1 1 1 1 0
15 1 1 1 1 1 0 0 0 15 1 0 0 0 1 1 1 1

After k mapping and simplification, we arrive at following expressions

A= W

B= W’X + WX’ or B= W xor X

C= Y’B+YB’ or C= Y xor B

D= Z’C + Z’C or D= Z xor C

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A= W B=W’X+WX’

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C=W ⊕Y ⊕ X D= W⊕Y⊕X⊕Z

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 1. Draw the logic diagram for the Binary-to-Gray and Gray-to-Binary code converters using Exclusive-OR
gates in the space provided below.

A
W

B
X

C
Y

D
Z

Only the following gates are available to you for lab tasks.

EE-221: Digital Logic Design Page 7

Lab Tasks: (To be completed in the lab) (3 marks)
Lab Task 1:

Implement the Binary to Gray Code Converter using logic gates. Make the Schematic Diagram. Show the
results to your Teacher/Lab Engr. What and how many gates did you use? Do not dispatch your hardware.
You will need it in lab task 3.

Proteus Simulation: Hardware Implementation:

EE-221: Digital Logic Design Page 8

Lab Task 2:

Realize the Gray to Binary Code Converter using exclusive-OR gates. Make the Schematic Diagram. Show the
results to your Teacher/ Lab Engr. What and how many gates did you use? Do not dispatch your hardware.
You will need it in lab task 3.

Proteus Simulation: Hardware Implementation:

Lab Task 3:

Now cascade the two circuits in series by connecting the outputs of binary-to-gray converter to the inputs of the
gray-to-binary converter. You should be able to get the binary input at output as well. Show the results to your
Teacher/Lab Engr. Use LEDs to show input-output relationship.

Proteus Simulation: Hardware Implementation:

EE-221: Digital Logic Design Page 9

Lab Task 4:

Verilog Code:
module binaryToGray( a, b, c,d,w,x,y,z);

input a, b, c,d;

output w,x,y,z ;

assign w = a;

assign x= a^b;

assign y= b^c;

assign z=c^d;

endmodule

module grayToBinary( w, x, y, z, a, b, c, d);

output a, b, c,d;

input w,x,y,z ;

assign a = w;

assign b= w^x;

assign c= x^y;

assign d=y^z;

endmodule

module implementation(A,B,C,D,W,X,Y,Z);

input A, B, C, D;

wire w1,x1,y1,z1;

output W,X,Y,Z;

binaryToGray b1(A, B ,C, D, w1, x1, y1, z1);

brayToBinary g1(w1,x1,y1,z1,W,X,Y,Z);

endmodule
EE-221: Digital Logic Design Page 10
module FinalTest;

reg A,B,C,D;

wire o1,o2,o3,o4;

implementation i1(A,B,C,D,o1,o2,o3,o4);

initial

begin

#100 B=1'b0; C=1'b0; D=1'b0;A=1'b0;

#100 B=1'b0; C=1'b0; D=1'b1;A=1'b0;

#100 B=1'b0; C=1'b1; D=1'b0;A=1'b0;

#100 B=1'b0; C=1'b1; D=1'b1;A=1'b0;

#100 B=1'b1; C=1'b0; D=1'b0;A=1'b0;

#100 B=1'b1; C=1'b0; D=1'b1;A=1'b0;

#100 B=1'b1; C=1'b1; D=1'b0;A=1'b0;

#100 B=1'b1; C=1'b1; D=1'b1;A=1'b0;

#100 B=1'b0; C=1'b0; D=1'b0;A=1'b1;

#100 B=1'b0; C=1'b0; D=1'b1;A=1'b1;

#100 B=1'b0; C=1'b1; D=1'b0;A=1'b1;

#100 B=1'b0; C=1'b1; D=1'b1;A=1'b1;

#100 B=1'b1; C=1'b0; D=1'b0;A=1'b1;

#100 B=1'b1; C=1'b0; D=1'b1;A=1'b1;

#100 B=1'b1; C=1'b1; D=1'b0;A=1'b1;

#100 B=1'b1; C=1'b1; D=1'b1;A=1'b1;

end

endmodule

EE-221: Digital Logic Design Page 11

Waveform:

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