Lab 6
Lab 6
Group No.:09
ABDULLAH 413132
MUNIR
In first part you are required to design and implement a binary to gray and gray to binary code
converter. You will be cascading these two converters thus implementing a binary to gray coder
and decoder (gray to binary).
The next part is the Verilog Modeling and Simulation of the Circuit you implemented in you first
lab.
Objectives:
Lab Instructions
✓ This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
✓ The lab report will be uploaded on LMS three days before scheduled lab date. The students
will get hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit
it with teacher/lab engineer for necessary evaluation. Alternately each group to upload
completed lab report on LMS for grading.
✓ The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining functional
verification)
✓ Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit
will simplify trouble-shooting process.
✓ After the lab, students are expected to unwire the circuit and deposit back components before
leaving.
✓ The students will complete lab task and submit complete report to Lab Engineer before
leaving lab.
✓ The Total duration for the lab is 3 hrs. After lab duration, a deduction of 5 marks per
day will be done for late submission.
✓ A lab with in-complete lab tasks will not be accepted.
✓ There are related questions at the end of this activity. Give complete answers.
Binary Codes are different encoding techniques to convert numbers into a form that can be understood
by the computers in the form 0f 0’s and 1’s.
Examples are:
W= A
A B C D W X Y Z W X Y Z A B C D
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1 2 0 0 1 1 0 0 1 0
3 0 0 1 1 0 0 1 0 3 0 0 1 0 0 0 1 1
4 0 1 0 0 0 1 1 0 4 0 1 1 0 0 1 0 0
5 0 1 0 1 0 1 1 1 5 0 1 1 1 0 1 0 1
6 0 1 1 0 0 1 0 1 6 0 1 0 1 0 1 1 0
7 0 1 1 1 0 1 0 0 7 0 1 0 0 0 1 1 1
8 1 0 0 0 1 1 0 0 8 1 1 0 0 1 0 0 0
9 1 0 0 1 1 1 0 1 9 1 1 0 1 1 0 0 1
10 1 0 1 0 1 1 1 1 10 1 1 1 1 1 0 1 0
11 1 0 1 1 1 1 1 0 11 1 1 1 0 1 0 1 1
12 1 1 0 0 1 0 1 0 12 1 0 1 0 1 1 0 0
13 1 1 0 1 1 0 1 1 13 1 0 1 1 1 1 0 1
14 1 1 1 0 1 0 0 1 14 1 0 0 1 1 1 1 0
15 1 1 1 1 1 0 0 0 15 1 0 0 0 1 1 1 1
A= W
C= Y’B+YB’ or C= Y xor B
A
W
B
X
C
Y
D
Z
Only the following gates are available to you for lab tasks.
Implement the Binary to Gray Code Converter using logic gates. Make the Schematic Diagram. Show the
results to your Teacher/Lab Engr. What and how many gates did you use? Do not dispatch your hardware.
You will need it in lab task 3.
Realize the Gray to Binary Code Converter using exclusive-OR gates. Make the Schematic Diagram. Show the
results to your Teacher/ Lab Engr. What and how many gates did you use? Do not dispatch your hardware.
You will need it in lab task 3.
Lab Task 3:
Now cascade the two circuits in series by connecting the outputs of binary-to-gray converter to the inputs of the
gray-to-binary converter. You should be able to get the binary input at output as well. Show the results to your
Teacher/Lab Engr. Use LEDs to show input-output relationship.
Verilog Code:
module binaryToGray( a, b, c,d,w,x,y,z);
input a, b, c,d;
output w,x,y,z ;
assign w = a;
assign x= a^b;
assign y= b^c;
assign z=c^d;
endmodule
output a, b, c,d;
input w,x,y,z ;
assign a = w;
assign b= w^x;
assign c= x^y;
assign d=y^z;
endmodule
module implementation(A,B,C,D,W,X,Y,Z);
input A, B, C, D;
wire w1,x1,y1,z1;
output W,X,Y,Z;
brayToBinary g1(w1,x1,y1,z1,W,X,Y,Z);
endmodule
EE-221: Digital Logic Design Page 10
module FinalTest;
reg A,B,C,D;
wire o1,o2,o3,o4;
implementation i1(A,B,C,D,o1,o2,o3,o4);
initial
begin
end
endmodule