Integrated Circuit 2

ECE 430

Lecture 8: Semiconductor Memories

Dr. Emad Badry

❑ Semiconductor memory arrays can store a large quantity of digital information and are essential to all digital
systems. The amount of memory required in a particular system depends on the type of application, but, in general,
the number of transistors utilized for the information (data) storage function is much larger than the number of
transistors used in logic operations and for other purposes.
 Memory array organization

❑ The data storage structure, or core, consists of individual memory cells arranged in an array of horizontal rows and
vertical columns. Each cell can store one bit of binary information.

❑ The total number of memory cells in this array

is 2𝑀 x 2𝑁 .
❑ To access a particular memory cell, i.e., a particular data bit in this array, the corresponding bit line and the
corresponding word line must be selected. The row and column selection operations are done by row and column
decoders, respectively. The row decoder circuit chooses one out of 2𝑁 word lines according to an N-bit row address,
while the column decoder circuit selects one out of 2𝑀 bit lines based on an M-bit column address.
 Read-Only Memory (ROM) Circuits

❑ Read-Only Memory (ROM) cells can be realized with only one transistor per bit of storage.
❑ A ROM is a nonvolatile memory structure in that the state is retained indefinitely even without power.

❑ Commercial ROMs are normally dynamic, although pseudo-NMOS is simple and suffices for small structures.

❑ The word-line input must be low during pre-charge on

dynamic NOR gates.

❑ Only one word line is activated at a time by making its

voltage to VDD, while all other rows are at a low voltage
level.

❑ If an active transistor exists at the cross point of a column

and the selected row, the column voltage is pulled down to
the logic low level by that transistor. If no active transistor
exists at the cross point, the column voltage is pulled high by
the PMOS load device.
❑ In actual ROM layout, the array can be initially manufactured with NMOS transistors at every row-
column intersection. The "1-bits” are then realized by omitting the drain or source connection, or the gate
electrode of the corresponding NMOS transistors in the final metallization step.
 Design of Row and Column Decoders

❑ A row decoder designed to drive a NOR ROM array must, by definition, choose one of the 2𝑁 word lines by raising its
voltage to VOH.

❑ For 2-bit address decoder, a most straightforward implementation of this

decoder is another NOR array, consisting of 4 rows (outputs) and 4
columns (two address bits and their complements).
❑ The column decoder circuitry is designed to select one out of 2𝑀 bit lines (columns) of the ROM array according to an M-
bit column address, and to route the data content of the chosen bit line to the data output.

❑ In this arrangement, only one NMOS pass

transistor is turned on at a time, depending
on the column address bits applied to the
decoder inputs. The conducting pass
transistor routes the selected column signal
to the data output. Similarly, a number of
columns can be chosen at a time, and the
selected columns can be routed to a
parallel data output port.
 Programmable ROMs

❑ It is often desirable for the user to be able to program or reprogram a ROM after it is manufactured. Programming/writing
speeds are generally slower than read speeds for ROMs.

❑ Four types of nonvolatile memories include Programmable ROMs (PROMs), Erasable Programmable ROMs
(EPROMs), Electrically Erasable Programmable ROMs (EEPROMs), and Flash memories.

❑ PROMs use fuses while EPROMs, EEPROMs, and Flash use charge stored on a floating gate.

❑ Programmable ROMs can be fabricated as ordinary ROMs fully populated with pulldown transistors in every position.
Each transistor is placed in series with a fuse that can be burned out by applying a high current.
❑ The user typically configures the ROM in a specialized PROM programmer before putting it in the system.

❑ PROMs are also referred to as one-time programmable memories.

The Flash Memory

❑ Flash memories are high-density read/write memories that are nonvolatile.

❑ This high density is achieved in flash memories with a storage cell that consists of a single floating-gate
MOS transistor. A data bit is stored as charge or the absence of charge on the floating gate depending if a 0
or a 1 is stored.
Flash Memory Cell

❑ The stacked gate MOS transistor consists of a control gate and a floating gate in addition to the drain and source.

❑ The floating gate stores electrons (charge) if a

sufficient voltage applied to the control gate. A “0” is
stored when there is more charge and a “1” is stored
when there is less or no charge.

❑ The amount of charge present on the floating gate

determines if the transistor will turn on and conduct
current from the drain to the source when a control
voltage is applied during a read operation.
Basic Flash Memory Operation

Programming
❑ Initially, all cells are at the 1 state because charge was removed from each cell in a previous erase operation.

❑ Application of a sufficient positive voltage to the control gate with respect to the source during
programming attracts electrons to the floating gate. Once programmed, a cell can preserve the charge for up
to 100 years without any external power.
Read
❑ During a read operation, a positive voltage is applied to the control gate. The amount of charge present on the
floating gate of a cell determines whether or not the voltage applied to the control gate will activate the
transistor.
Erase

❑ During an erase operation, charge is removed from all the memory cells. A sufficient positive voltage is
applied to the transistor source with respect to the control gate.
Random Access Random (RAM)

Random Access Random (RAM)

Static RAM Dynamic RAM

 Static RAM

❑ The memory circuit is said to be static if the stored data can be retained indefinitely if a sufficient power supply voltage is
provided, without requiring a periodic refresh operation.

❑ The data storage cell, i.e., the 1-bit memory cell in static RAM arrays, invariably consists of a simple latch circuit with
two stable operating points (states).

❑ Depending on the preserved state of the two-inverter latch circuit, the data being held in the memory cell will be
interpreted either as a logic "0" or as a logic " 1".

❑ Usually, two complementary access switches consisting of NMOS pass transistors are implemented to connect the 1-bit
SRAM cell to the complementary bit lines (columns).
Full CMOS SRAM Cell
SRAM Write Circuitry
SRAM Read Circuitry

During the "data read" operation in the SRAM array, the voltage level on either one of
the columns decreases slightly after the pass transistors are turned on by the row address
decoder circuit. To reduce the read access time, the "read" circuitry must detect a very
small voltage difference between the two complementary columns and amplify this
difference to produce a valid logic output level. A simple source-coupled differential
amplifier can be used for this task
Here, the drain currents of the two complementary NMOS transistors are:

𝐾𝑛 2
𝐾𝑛 2
𝐼𝐷1 = 𝑉 − 𝑉𝑋 − 𝑉𝑡𝑛1 𝐼𝐷2 = 𝑉 ҧ − 𝑉𝑋 − 𝑉𝑡𝑛2
2 𝐶 2 𝐶

𝜕 𝑉𝑜1 − 𝑉𝑜2 𝜕𝐼𝐷

= −𝑅𝑔𝑚 𝑔𝑚 = = 2𝐾𝑛 𝐼𝐷
𝜕 𝑉𝐶 − 𝑉𝐶ҧ 𝜕𝑉𝐺𝑆
 Dynamic RAM

❑ Dynamic RAMs (DRAMs) store their contents as charge on a capacitor rather than in a feedback loop. Thus, the basic cell is
substantially smaller than SRAM, but the cell must be periodically read and refreshed so that its contents do not leak away.
DRAMs are built in specialized processes optimized for dense capacitor structures. A 1-transistor (1T) dynamic RAM cell
consists of a transistor and a capacitor

❑ As SRAM, the cell is accessed by asserting the word-line to

connect the capacitor to the bit-line. On a read, the bit-line
is initially pre-charged to VDD/2. When the word-line rises,
the capacitor shares its charge with the bit-line, causing a
voltage change 𝞓V that can be sensed.

❑ The read disturbs the cell contents at x, so the cell must be

rewritten after each read. On a write, the bit-line is driven
high or low and the voltage is forced onto the capacitor.
End of Lecture