Integrated Circuit 2

ECE 430

Lecture 2: MOSFET Review

Dr. Emad Badry

 The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Structure

The n-channel MOSFET transistor contains p type semiconductor substrate, two n+ type semiconductor, Silicon dioxide
(SIO2), and a polysilicon gate (G). The two n+ regions represent the Drain (D) and Source (S) terminals.
I/V Characteristics of MOSFET transistor

In the case of n-channel MOSFET

A positive voltage should be applied at the gate terminal in order to activate the transistor, the applied voltage must be
greater than a threshold voltage (Vt), otherwise, the current is zero value, and this mode of operation is called cutoff
region.

If VDS is smaller than (VGS-Vt), the transistor works in the triode region and 𝑰𝑫 can be defined as:

𝑾 𝟏
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮𝑺 − 𝑽𝒕 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝑳 𝟐

𝑊
Where 𝜇𝑛 and 𝐶𝑜𝑥 are the electron mobility and oxide capacitance, respectively. W is the channel width. is called the
𝐿
aspect ratio.
If 𝑽𝑫𝑺 << 𝟐 𝑽𝑮𝑺 − 𝑽𝒕 , we have

𝑾
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮𝑺 − 𝑽𝒕 𝑽𝑫𝑺
𝑳

The path between drain and source can be specifies as a linear resistor (𝑅𝐷𝑆 ) equal to:

𝟏
𝑹𝑫𝑺 =
𝑾
𝝁𝒏 𝑪𝒐𝒙 𝑳 𝑽𝑮𝑺 − 𝑽𝒕

If 𝑽𝑫𝑺 > 𝑽𝑮𝑺 − 𝑽𝒕 , the transistor operates in saturation region and 𝑰𝑫 can be defined as:

𝟏 𝑾 𝟐
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 𝑽 − 𝑽𝒕
𝟐 𝑳 𝑮𝑺
❑ There is a dependency on 𝑽𝑫𝑺 for 𝑰𝑫 current. The 𝑰𝑫 is not constant at the saturation region, and that because the
phenomena of Channel Length Modulation (CLM)

❑ At higher VDS values, the pinch off point moves from the original location X1 to a new location X2 toward source
region.

𝟏 𝑾
𝑰𝑫 = 𝟐 𝝁𝒏 𝑪𝒐𝒙 𝑳
𝑽𝑮𝑺 − 𝑽𝒕 𝟐 (1+λVDS)

Where λ is the channel length modulation coefficient

Symbol

Cut off region VGS<Vtn

I𝐷 = 0

Triode region VGD > Vtn , (VDS < VGS-Vtn) VGS>Vtn

𝑊 1
I𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ( 𝑉𝐺𝑆 − 𝑉𝑡 𝑉𝐷𝑆 − 𝑉𝐷𝑆 2 )
𝐿 2

Saturation region VGD < Vtn , (VDS > VGS-Vtn) VGS>Vtn

1 𝑊 2
I𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑡 (1+λVDS)
2 𝐿
P-channel MOSFET Symbol

Cut off region VSG < |Vtp|

I𝐷 = 0

Triode region VDG> |Vtp| , (VSD < VSG-|Vtp|) VSG < |Vtp|
𝑊 1
I𝐷 = 𝜇𝑝 𝐶𝑜𝑥 ( V𝑆𝐺 − |V𝑡𝑝 | 𝑉𝑆𝐷 − 𝑉𝑆𝐷 2 )
𝐿 2

Saturation region VDG < |Vtp|, (VSD > VSG-|Vtp|) VSG < |Vtp|

1 𝑊 2
I𝐷 = 𝜇𝑝 𝐶𝑜𝑥 V𝑆𝐺 − |V𝑡𝑝 | (1+|λ|𝑉𝑆𝐷 )
2 𝐿
 MOSFET Device Capacitance

The capacitances originate from the central MOS gate structure, the characteristics of the channel charge, and the pn
junction depletion regions. The channel and depletion capacitances vary with the applied voltage.

The first group due to the system itself (𝐶𝐺𝑆 and 𝐶𝐺𝐷 )while the second due to depletion regions (𝐶𝑆𝐵 and 𝐶𝐷𝐵 ).
 MOSFET based capacitance

𝐶𝐺 is defined as:
𝐶𝐺 = 𝐶𝑂𝑋 𝑊𝐿𝐷

Where 𝐶𝑂𝑋 and 𝐿𝐷 is the oxide capacitance and drawn channel length.
𝐶𝑂𝑋 and 𝐿𝐷 are defined as:

𝜀𝑂𝑋
𝐶𝑂𝑋 =
𝑡𝑂𝑋

𝐿𝐷 = 𝐿 + 2𝐿𝑂

𝜀𝑂𝑋 is permittivity of silicon dioxide, 𝑡𝑂𝑋 is the oxide thickness. 𝐿𝑂 is the gate overlap distance. Gate overlap is due to
lateral doping effects during the processing.
The 𝐶𝐺 it may be broken down into components by writing

𝐶𝐺 = 𝐶𝑔 + 2𝐶𝑂𝐿
Cut off region CGB = CG
where
𝐶𝑔 = 𝐶𝑂𝑋 𝑊𝐿 2
Saturation region CGS = CG
The overlap capacitance 𝐶𝑂𝐿 = 𝐶𝑂 𝑊 3

𝐶𝑂 = 𝐶𝑂𝑋 𝐿𝑂
Triode region CGS = O. 5CG CGD = O. 5CG
Depletion capacitance

Depletion capacitance originates from the depletion region that consists of ionized dopants in the vicinity a pn junction

Depletion capacitance is also a nonlinear parasitic that is defined by

𝜕𝑄𝑑
𝐶𝑗 =
𝜕𝑉
Where 𝑄𝑑 is the depletion charge density in units of 𝐶ൗ𝑐𝑚2 and V is the applied voltage

The derivative gives the zero-bias capacitance per unit area as

𝜀𝑠𝑖
𝐶𝑗𝑜 =
𝑥𝑑0

where the zero-bias depletion width

2𝜀𝑠𝑖 𝜙0 1 1
𝑥𝑑𝑜 = +𝑁
𝑞 𝑁𝑎 𝑑
 The built-in voltage is

𝐾𝑇 𝑁𝑎 𝑁𝑑
𝜙𝑜 = ln
𝑞 𝑛𝑖 2

The depletion widths increase with the reverse applied voltage 𝑉𝑅

𝑉𝑅
𝑥𝑑 𝑉𝑅 = 𝑥𝑑𝑜 1 +
𝜙𝑜

The junction capacitance is

𝜀𝑠𝑖
𝐶𝑗 𝑉𝑅 =
𝑥𝑑 𝑉𝑅

𝐶𝑗𝑜
𝑉
The junction 𝐶𝑗 capacitance decreases as 𝑉𝑅 increases. 1 + 𝜙𝑅
𝑜
 Depletion capacitances are found at the source and drain regions

𝐶𝑏𝑜𝑡 = 𝐶𝑗𝑜 WX
𝐶𝑗𝑠𝑤 = 𝐶𝑗𝑜𝑠𝑤 𝑥𝑗

As the sidewall capacitance per unit perimeter in units of F/cm. The total
sidewall capacitance is given by

𝐶𝑠𝑖𝑑𝑒 = 𝐶𝑗𝑠𝑤 𝑃

where P is the total perimeter length around the n+ region in units of centimeters
 𝑃 =2 𝑊+𝑋

The total zero-biased depletion capacitance is then given by

𝐶𝑛 = 𝐶𝑏𝑜𝑡 + 𝐶𝑠𝑖𝑑𝑒

= 𝐶𝑗𝑜 𝑊𝑋 + 𝐶𝑗𝑠𝑤 2 𝑊 + 𝑋
 𝐴𝑆 = 𝑊𝑌
𝑃𝑆 = 2 𝑊 + 𝑌

𝐶𝑆𝐵𝑜 = 𝐶𝑗𝑜 𝑊𝑌 + 2𝐶𝑗𝑠𝑤 (W+Y)

𝐴𝐷 = 𝑊𝑋

𝑃𝐷 = 2 𝑊 + 𝑋

𝐶𝐷𝐵𝑜 = 𝐶𝑗𝑜 𝑊𝑋 + 2𝐶𝑗𝑠𝑤 (W+X)

𝐶𝑗𝑜 𝑊𝑋 2𝐶𝑗𝑠𝑤 𝑊 + 𝑋
𝐶𝐷𝐵 𝑉𝐷 = +
𝑉 𝑉
1 + 𝜙𝐷 1+𝜙 𝐷
𝑂 𝑜𝑠𝑤

where 𝑉𝐷 is the drain voltage. 𝜙𝑜𝑠𝑤 is the built-in potential for the sidewall
The accurate model is
𝐶𝑗𝑜 𝐴 𝐶𝑗𝑠𝑤 𝑃
𝐶𝑑𝑒𝑝 𝑉𝑅 = +
𝑉 𝑉
1 + 𝜙𝑅 0.5 1 + 𝜙𝑅 0.33
𝑜 𝑜
Problem

Given:

𝑡𝑜𝑥 =6nm
L=0.24µm
W= 0.36µm
𝐿𝐷 = 𝐿𝑆 =0.625µm
𝐶𝑜 =3x10−10 F/m
𝐶𝑗𝑜 =2x10−3 F/𝑚2
𝐶𝑗𝑠𝑤 =2.75x10−10 F/m
𝜀𝑜𝑥 = 3.5 𝑥 10−11 F/m

Determine the zero-bias value of all relevant capacitances.