Integrated Circuit 2

ECE 430

Lecture 3: MOS Inverter ( Static characteristics)

Dr. Emad Badry

 Basic circuit

❑ In MOS inverter, both input terminal A and output terminal B are

represented by node voltage. The value of 1 and 0 can be presented by
VDD and 0, respectively.

VTC of ideal Inverter.

The general structure of NMOS inverter.

𝐼𝑑𝑟𝑖𝑣𝑒𝑟 𝑉𝑖𝑛 𝑉𝑜𝑢𝑡 = 𝐼𝑙𝑜𝑎𝑑 𝑉𝐿

For low Vin, the Vout is equal to the high value of 𝑉𝑂𝐻 . In this case, the NMOS is
cut-off and 𝐼𝑑𝑟𝑖𝑣𝑒𝑟 =0 and 𝑉𝐿 is very small

As the input voltage Vin increases, the driver transistor starts conducting a
certain drain current, and the output voltage decreases.
 Resistive-Load Inverter

For Vin < Vtn The transistor is off, Vout=VDD

For Vin > Vtn

Initially it operates in saturation since VDS=Vout is larger than Vin-Vtn, thus
𝐾𝑛
𝐼𝑅 = (𝑉𝑖𝑛 − 𝑉𝑡𝑛 )2
2

Vin > Vout+Vtn The driver transistor enters triode region.

𝐾𝑛
𝐼𝑅 = 2 𝑉𝑖𝑛 − 𝑉𝑡𝑛 . 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2
2 𝑊
𝐾𝑛 =𝜇𝑛 𝐶𝑜𝑥
𝐿

❑ For simplicity, the channel length modulation is neglected and VSB=0.

 Critical points estimation

Calculation of VOH

𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝑅𝐿 𝐼𝑅

When Vin < Vtn 𝐼𝐷 = 𝐼𝑅 = 0 𝑉𝑂𝐻 = 𝑉𝐷𝐷

Calculation of VOL

We assume that Vin=VOH so Vin-Vtn>Vout The driver transistor operates in triode region

𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 𝑉𝑖𝑛 = 𝑉𝐷𝐷

𝐼𝑅 =
𝑅𝐿
Using KCL, 𝐼𝐷 = 𝐼𝑅 𝑉𝑜𝑢𝑡 = 𝑉𝑂𝐿
𝑉𝐷𝐷 − 𝑉𝑂𝐿 𝐾𝑛
= 2 𝑉𝐷𝐷 − 𝑉𝑡𝑛 . 𝑉𝑂𝐿 − 𝑉𝑂𝐿 2
𝑅𝐿 2
 The equation yields a simple quadratic in 𝑉𝑂𝐿

1 2
𝑉𝑂𝐿 2 − 2. 𝑉𝐷𝐷 − 𝑉𝑡𝑛 + . 𝑉𝑂𝐿 + .𝑉 = 0
𝐾𝑛 𝑅𝐿 𝐾𝑛 𝑅𝐿 𝐷𝐷

The solution of this equation gives

2
1 1 2𝑉𝐷𝐷
𝑉𝑂𝐿 = 𝑉𝐷𝐷 − 𝑉𝑡𝑛 + ± 𝑉𝐷𝐷 − 𝑉𝑡𝑛 + −
𝐾𝑛 𝑅𝐿 𝐾𝑛 𝑅𝐿 𝐾𝑛 𝑅𝐿

Calculation of VIL
When Vin=VIL The Vout is slightly smaller than VOH Vout> Vin-Vtn

The driver transistor operates in saturation region.

 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 𝐾𝑛 2
= 𝑉 − 𝑉𝑡𝑛
𝑅𝐿 2 𝑖𝑛

1 𝑑𝑉𝑜𝑢𝑡
We differentiate both sides with respect to 𝑉𝑖𝑛 − . = 𝐾𝑛 𝑉𝑖𝑛 − 𝑉𝑡𝑛
𝑅𝐿 𝑑𝑉𝑖𝑛

1
We can substitute 𝑑𝑉𝑜𝑢𝑡 Τ𝑑𝑉𝑖𝑛 = - 1 − . −1 = 𝐾𝑛 𝑉𝐼𝐿 − 𝑉𝑡𝑛
𝑅𝐿

1
𝑉𝐼𝐿 = 𝑉𝑡𝑛 +
𝐾𝑛 𝑅𝐿

The Vout when input voltage is VIL can be estimated as follows:

2
𝐾𝑛 𝑅𝐿 1 1
𝑉𝑜𝑢𝑡 𝑉𝑖𝑛 = 𝑉𝐼𝐿 = 𝑉𝐷𝐷 − 𝑉𝑡𝑛 + − 𝑉𝑡𝑛 = 𝑉𝐷𝐷 −
2 𝐾𝑛 𝑅𝐿 2𝐾𝑛 𝑅𝐿
 Calculation of VIH

When (𝑉𝑖𝑛 = 𝑉𝐼𝐻 ) 𝑉𝑜𝑢𝑡 is only slightly greater than 𝑉𝑂𝐿 Vout< Vin-Vtn

The driver transistor operates in triode region.

𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 𝐾𝑛
= 2 𝑉𝑖𝑛 − 𝑉𝑡𝑛 . 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2
𝑅𝐿 2

1 𝑑𝑉𝑜𝑢𝑡 𝐾𝑛 𝑑𝑉𝑜𝑢𝑡 𝑑𝑉𝑜𝑢𝑡

We differentiate both sides with respect to 𝑉𝑖𝑛 − . = 2 𝑉𝑖𝑛 − 𝑉𝑡𝑛 . + 2𝑉𝑜𝑢𝑡 − 2𝑉𝑜𝑢𝑡 .
𝑅𝐿 𝑑𝑉𝑖𝑛 2 𝑑𝑉𝑖𝑛 𝑑𝑉𝑖𝑛

1
We can substitute 𝑑𝑉𝑜𝑢𝑡 Τ𝑑𝑉𝑖𝑛 = - 1, 𝑉𝑖𝑛 = 𝑉𝐼𝐻 − . −1 = 𝐾𝑛 . 𝑉𝐼𝐻 − 𝑉𝑡𝑛 . −1 + 2𝑉𝑜𝑢𝑡
𝑅𝐿
 1
𝑉𝐼𝐻 = 𝑉𝑡𝑛 + 2𝑉𝑜𝑢𝑡 −
𝐾𝑛 𝑅𝐿

We Substitute by 𝑉𝐼𝐻 value

𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 𝐾𝑛 1
= 2 𝑉𝑡𝑛 + 2𝑉𝑜𝑢𝑡 − − 𝑉𝑡𝑛 . 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2
𝑅𝐿 2 𝐾𝑛 𝑅𝐿

The positive solution of Vout when 𝑉𝑖𝑛 = 𝑉𝐼𝐻

2 𝑉𝐷𝐷
𝑉𝑜𝑢𝑡 𝑉𝑖𝑛 = 𝑉𝐼𝐻 =
3 𝐾𝑛 𝑅𝐿

8 𝑉𝐷𝐷 1
𝑉𝐼𝐻 = 𝑉𝑡𝑛 + −
3 𝐾𝑛 𝑅𝐿 𝐾𝑛 𝑅𝐿
 𝐾𝑛 𝑅𝐿 can be adjusted to change of VTC curve

For larger 𝐾𝑛 𝑅𝐿 values, the output low voltage 𝑉𝑂𝐿 becomes smaller. and
that the shape of the VTC approaches that of the ideal inverter

Power Consumption and Chip Area

When the input voltage is equal to VOL, the driver transistor is off. Consequently, there is no steady-state current flow in the
circuit (ID = IR = 0), and zero DC power dissipation.
When the input voltage is equal to 𝑉𝑂𝐻 on the other hand, both the driver MOSFET and the load resistor conduct a nonzero
current.

𝑉𝐷𝐷 − 𝑉𝑂𝐿 50% ON 𝑉𝐷𝐷 𝑉𝐷𝐷 − 𝑉𝑂𝐿

𝐼𝐷 = 𝐼𝑅 = 𝑃𝐷𝐶 𝑎𝑣𝑒𝑟𝑎𝑔𝑒 = .
𝑅𝐿 50 % OFF 2 𝑅𝐿
Summary of the four critical VTC points

VOH VDD
VOL 1 1 2
2𝑉𝐷𝐷
𝑉𝐷𝐷 − 𝑉𝑡𝑛 + − 𝑉𝐷𝐷 − 𝑉𝑡𝑛 + −
𝐾𝑛 𝑅𝐿 𝐾𝑛 𝑅𝐿 𝐾𝑛 𝑅𝐿
VIL 1
𝑉𝑡𝑛 +
𝐾𝑛 𝑅𝐿
VIH 8 𝑉𝐷𝐷 1
𝑉𝑡𝑛 + −
3 𝐾𝑛 𝑅𝐿 𝐾𝑛 𝑅𝐿
Example
Consider the following inverter design problem: Given VDD = 5 V, Kn' = 30 𝛍𝐀Τ𝐕 𝟐 , and Vtn= 1V, design a
𝐖
resistive-load inverter circuit with VOL= 0.2V. Specifically, determine the ( 𝐋 ) ratio of the driver transistor and
the value of the load resistor RL that achieve the required VOL

Kn ' is the process transconductance parameter=𝜇𝑛 𝐶𝑜𝑥

Note that the driver transistor is operating in the linear region when the output voltage is equal to VOL and the input
voltage is equal to VOH = VDD

𝑉𝐷𝐷 − 𝑉𝑂𝐿 Kn ′ 𝑊
= . 2 𝑉𝑂𝐻 − 𝑉𝑡𝑛 . 𝑉𝑂𝐿 − 𝑉𝑂𝐿 2
𝑅𝐿 2 𝐿

Assuming VOL = 0.2 V and using the given values for the power supply voltage, the driver threshold voltage and the
driver transconductance K 𝑛 ′, we obtain the following equation:

5 − 0.2 30x10−6 𝑊
= . 2 5 − 1 . 0.2 − 0.22
𝑅𝐿 2 𝐿
 𝑊
𝑅𝐿 = 2.05𝑥105 Ω
𝐿

𝑉𝐷𝐷 𝑉𝐷𝐷 − 𝑉𝑂𝐿

𝑃𝐷𝐶 𝑎𝑣𝑒𝑟𝑎𝑔𝑒 = .
2 𝑅𝐿

It is seen that the power consumption increases significantly as the value of the load resistor 𝑅𝐿 is decreased, and the
𝑊
( 𝐿 ) ratio is increased.
Example

𝐖
Consider a resistive-load inverter circuit with VDD= 5 V, Kn'= 20 𝛍𝐀Τ𝐕 𝟐 , Vtn= 0.8 V, RL = 200 k Ω, and = 2.
𝐋
Calculate the critical voltages (VOL, VOH, VIL, VIH) on the VTC and find the noise margins of the circuit.

𝑉𝑂𝐻 = 𝑉𝐷𝐷

Kn=20 x 2=40 𝜇𝐴Τ𝑉 2

1 1 2 2𝑉𝐷𝐷
VOL=𝑉𝐷𝐷 − 𝑉𝑡𝑛 + − 𝑉𝐷𝐷 − 𝑉𝑡𝑛 + 𝐾 𝑅 −𝐾
𝐾𝑛 𝑅𝐿 𝑛 𝐿 𝑛 𝑅𝐿
NMH=𝑉𝑂𝐻 − 𝑉𝐼𝐻 =5-1.97=3.03 V
1 1 2 10 NML=𝑉𝐼𝐿 − 𝑉𝑂𝐿 =0.93-0.15=0.78 V
=5 − 0.8 + − 5 − 0.8 +8 − =0.147 V
8 8

1 1
VIL=𝑉𝑡𝑛 + 𝐾 = 0.8 + 8 = 0.925 𝑉
𝑛 𝑅𝐿

8 𝑉𝐷𝐷 1 40 1
VIH=𝑉𝑡𝑛 + −𝐾 =0.8+ − = 1.97 𝑉
3 𝐾𝑛 𝑅𝐿 𝑛 𝑅𝐿 24 8
Complementary MOS (CMOS) Inverter

NMOS and PMOS transistor are fabricated on the same chip and this process is more complex. This process provides a n-
type for PMOS substrate and p-type substrate for NMOS, and that can be achieved by building n-well or p-well.
❑ The most important advantage of CMOS circuit is that the power dissipation is
negligible except a small power due to leakage current. The VTC of CMOS inverter
exhibit a full output voltage swing between 0 V and 𝑉𝐷𝐷 and VTC transition is
usually very sharp.

It consists of NMOS transistor as a driver transistor and PMOS transistor as a load

transistor.
Circuit operation of CMOS Inverter

𝑉𝑖𝑛 = 𝑉𝐺𝑆𝑛 𝑉𝑜𝑢𝑡 = 𝑉𝐷𝑆𝑛

𝑉𝑆𝐺𝑝 = 𝑉𝐷𝐷 − 𝑉𝑖𝑛 𝑉𝑆𝐷𝑝 = 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡

When 𝑉𝑖𝑛 < 𝑉𝑡𝑛 NMOS is off, PMOS operates in triode region but 𝑉𝑆𝐷𝑝 = 0

𝐼𝐷𝑛 = 𝐼𝐷𝑝 = 0 𝑉𝑜𝑢𝑡 = 𝑉𝑂𝐻 = 𝑉𝐷𝐷

When 𝑉𝑖𝑛 > 𝑉𝐷𝐷 + 𝑉𝑡𝑝 PMOS is off, NMOS operates in triode region, 𝑉𝐷𝑆𝑛 = 0.

𝑉𝑜𝑢𝑡 = 𝑉𝑂𝐿 = 0
 The regions of operations for the NMOS and PMOS transistors.

Region 𝑉𝑖𝑛 𝑉𝑜𝑢𝑡 NMOS PMOS

A <𝑉𝑡𝑛 VOH Cut-off Triode
B VIL ≈VOH Saturation Triode
C 𝑉𝑡ℎ 𝑉𝑡ℎ Saturation Saturation
D VIH ≈VOL Triode Saturation
E >(VDD+Vtp) VOL Triode Cut-off
Calculation of VIL
MMOS operates in saturation
𝑑𝑉𝑜𝑢𝑡 Τ𝑑𝑉𝑖𝑛 = - 1 when 𝑉𝑖𝑛 = 𝑉𝐼𝐿
PMOS operates in triode region
𝐼𝐷𝑛 = 𝐼𝐷𝑝

𝐾𝑛 𝐾𝑝
𝑉 − 𝑉𝑡𝑛 2 = 2. 𝑉𝐺𝑆𝑝 − 𝑉𝑡𝑝 . 𝑉𝐷𝑆𝑝 − 𝑉𝐷𝑆𝑝 2
2 𝐺𝑆𝑛 2

𝐾𝑛 2
𝐾𝑝 2
𝑉 − 𝑉𝑡𝑛 = 2. 𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 . 𝑉𝑜𝑢𝑡 − 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 − 𝑉𝐷𝐷
2 𝑖𝑛 2

We differentiate both sides with respect to Vin

𝑑𝑉𝑜𝑢𝑡 𝑑𝑉𝑜𝑢𝑡
𝐾𝑛 𝑉𝑖𝑛 − 𝑉𝑡𝑛 = 𝐾𝑝 𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 . + 𝑉𝑜𝑢𝑡 − 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 − 𝑉𝐷𝐷 .
𝑑𝑉𝑖𝑛 𝑑𝑉𝑖𝑛
Substituting 𝑉𝑖𝑛 = 𝑉𝐼𝐿 and 𝑑𝑉𝑜𝑢𝑡 Τ𝑑𝑉𝑖𝑛 = - 1

𝐾𝑛 𝑉𝐼𝐿 − 𝑉𝑡𝑛 = 𝐾𝑝 2𝑉𝑜𝑢𝑡 − 𝑉𝐼𝐿 + 𝑉𝑡𝑝 − 𝑉𝐷𝐷

2𝑉𝑜𝑢𝑡 + 𝑉𝑡𝑝 − 𝑉𝐷𝐷 + 𝐾𝑅 𝑉𝑡𝑛 𝐾𝑛

𝑉𝐼𝐿 = 𝐾𝑅 =
1 + 𝐾𝑅 𝐾𝑝

Calculation of VIH
when 𝑉𝑖𝑛 = 𝑉𝐼𝐻 , 𝐼𝐷𝑛 = 𝐼𝐷𝑝
PMOS operates in saturation
𝐾𝑛 2 𝐾𝑝 2
2. 𝑉𝐺𝑆𝑛 − 𝑉𝑡𝑛 . 𝑉𝐷𝑆𝑛 − 𝑉𝐷𝑆𝑛 = 𝑉 − 𝑉𝑡𝑝
2 2 𝐺𝑆𝑝 NMOS operates in triode region

𝐾𝑛 2 𝐾𝑝 2
2. 𝑉𝑖𝑛 − 𝑉𝑡𝑛 . 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 = 𝑉 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝
2 2 𝑖𝑛
We differentiate both sides with respect to Vin

𝑑𝑉𝑜𝑢𝑡 𝑑𝑉𝑜𝑢𝑡
𝐾𝑛 𝑉𝑖𝑛 − 𝑉𝑡𝑛 . + 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 . = 𝐾𝑃 𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝
𝑑𝑉𝑖𝑛 𝑑𝑉𝑖𝑛

Substituting 𝑉𝑖𝑛 = 𝑉𝐼𝐻 and 𝑑𝑉𝑜𝑢𝑡 Τ𝑑𝑉𝑖𝑛 = - 1

𝐾𝑛 −𝑉𝐼𝐻 + 𝑉𝑡𝑛 + 2𝑉𝑜𝑢𝑡 = 𝐾𝑃 𝑉𝐼𝐻 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝

𝑉𝐷𝐷 + 𝑉𝑡𝑝 + 𝐾𝑅 2𝑉𝑜𝑢𝑡 + 𝑉𝑡𝑛

𝑉𝐼𝐻 =
1 + 𝐾𝑅
Calculation of Vth
PMOS operates in saturation
𝑉𝑖𝑛 = 𝑉𝑜𝑢𝑡 = 𝑉𝑡ℎ
NMOS operates in saturation

𝐾𝑛 2
𝐾𝑝 2
𝑉𝐺𝑆𝑛 − 𝑉𝑡𝑛 = 𝑉𝐺𝑆𝑝 − 𝑉𝑡𝑝
2 2
Replacing 𝑉𝐺𝑆𝑛 = 𝑉𝑖𝑛 and 𝑉𝐺𝑆𝑝 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷

𝐾𝑛 2
𝐾𝑝 2
𝑉𝑖𝑛 − 𝑉𝑡𝑛 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝
2 2

1
𝑉𝑡𝑛 + 𝑉 + 𝑉𝑡𝑝
𝐾𝑝 𝐾𝑃 𝐾𝑅 𝐷𝐷
𝑉𝑖𝑛 1+ = 𝑉𝑡𝑛 + 𝑉𝐷𝐷 + 𝑉𝑡𝑝 𝑉𝑡ℎ =
𝐾𝑛 𝐾𝑛 1
1+
𝐾𝑅
Design of CMOS Inverter

At given VDD
1 (𝑉𝑡ℎ −𝑉𝑡𝑛 )
=
𝐾𝑅 𝑉𝐷𝐷 + 𝑉𝑡𝑝 − 𝑉𝑡ℎ

Solving for 𝐾𝑅
2
𝐾𝑛 𝑉𝐷𝐷 + 𝑉𝑡𝑝 − 𝑉𝑡ℎ
𝐾𝑅 = =
𝐾𝑃 𝑉𝑡ℎ − 𝑉𝑡𝑛

Recall that the switching threshold voltage of an ideal inverter is defined as

1
𝑉𝑡ℎ,𝑖𝑑𝑒𝑎𝑙 = 𝑉𝐷𝐷
2
 2
𝐾𝑛 0.5𝑉𝐷𝐷 + 𝑉𝑡𝑝
=
𝐾𝑃 𝑖𝑑𝑒𝑎𝑙
0.5𝑉𝐷𝐷 − 𝑉𝑡𝑛

If 𝑉𝑡 = 𝑉𝑡𝑛 = |𝑉𝑡𝑝 |
𝐾𝑛
=1
𝐾𝑃 𝑠𝑦𝑚𝑚𝑒𝑡𝑟𝑐

Note that 𝐾𝑅 is defined as 𝑊 𝑊

𝐾𝑛 𝜇 𝐶
𝑛 𝑜𝑥 𝐿 𝜇𝑛 𝐿
𝑛 𝑛
= =
𝐾𝑝 𝜇 𝐶 𝑊 𝑊
𝑝 𝑜𝑥 𝐿 𝜇𝑝 𝐿
𝑝 𝑝

For ideal symmetric inverter

𝑊 Hence,
𝐿 𝜇𝑝 230 𝑐𝑚2 Τ𝑉. 𝑠
𝑛
= ≈ 𝑊 𝑊
𝑊 𝜇𝑛 580 𝑐𝑚2 Τ𝑉. 𝑠 ( )𝑝 ≈ 2.5 ( )𝑛
𝐿 𝑝
𝐿 𝐿
For symmetric CMOS inverter Vtn=|Vtp| and 𝐾𝑅 = 1

1
𝑉𝐼𝐿 = (3𝑉𝐷𝐷 + 2𝑉𝑡𝑛 )
8
1
𝑉𝐼𝐻 = (5𝑉𝐷𝐷 − 2𝑉𝑡𝑛 )
8
𝑉𝐼𝐿 + 𝑉𝐼𝐻 = 𝑉𝐷𝐷

𝑁𝑀𝐿 = 𝑉𝐼𝐿 − 𝑉𝑂𝐿 = 𝑉𝐼𝐿

𝑁𝑀𝐻 = 𝑉𝑂𝐻 − 𝑉𝐼𝐻 = 𝑉𝐷𝐷 − 𝑉𝐼𝐻

𝑁𝑀𝐿 = 𝑁𝑀𝐻 = 𝑉𝐼𝐿

Example

Consider a CMOS inverter circuit with the following parameters: VDD =3.3 V, Vtn= 0.6 V, Vtp=-0.7 V, Kn = 200
𝛍𝐀Τ𝐕 𝟐 , and Kp= 80 𝛍𝐀Τ𝐕 𝟐 . Calculate the noise margins of the circuit.

VOL=0 V, VOH=VDD=3.3 V

2𝑉𝑜𝑢𝑡 + 𝑉𝑡𝑝 − 𝑉𝐷𝐷 + 𝐾𝑅 𝑉𝑡𝑛

𝑉𝐼𝐿 =
1 + 𝐾𝑅

2𝑉𝑜𝑢𝑡 − 0.7 − 3.3 + 1.5

𝑉𝐼𝐿 = = 0.5𝑉𝑜𝑢𝑡 − 0.71
1 + 2.5

Now substitute this expression into the KCL equation

𝐾𝑛 𝐾𝑝
(𝑉𝐼𝐿 − 𝑉𝑡𝑛 )2 = (2. 𝑉𝐼𝐿 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 . (𝑉𝑜𝑢𝑡 − 𝑉𝐷𝐷 ) − (𝑉𝑜𝑢𝑡 − 𝑉𝐷𝐷 )2 )
2 2

2.5(0.5𝑉𝑜𝑢𝑡 − 0.71 − 0.6)2 = (2. 0.5𝑉𝑜𝑢𝑡 − 0.71 − 3.3 + 0.7 . (𝑉𝑜𝑢𝑡 − 3.3) − (𝑉𝑜𝑢𝑡 − 3.3)2 )
 0.66𝑉𝑜𝑢𝑡 2 + 0.05𝑉𝑜𝑢𝑡 − 6.65 = 0
𝑉𝑜𝑢𝑡 = 3.14 𝑉, VIL=1.08 V
To calculate VIH

𝑉𝐷𝐷 + 𝑉𝑡𝑝 + 𝐾𝑅 (2𝑉𝑜𝑢𝑡 + 𝑉𝑡𝑛 )

𝑉𝐼𝐻 =
1 + 𝐾𝑅
3.3 − 0.7 + 2.5(2𝑉𝑜𝑢𝑡 + 0.6)
𝑉𝐼𝐻 = = 1.43𝑉𝑜𝑢𝑡 + 1.17
1 + 2.5

Now substitute this expression into the KCL equation

2.61𝑉𝑜𝑢𝑡 2 + 6.94𝑉𝑜𝑢𝑡 − 2.04 = 0
𝐾𝑛 𝐾𝑝 𝑉𝑜𝑢𝑡 = 0.27 𝑉, VIH=1.55 V
2. 𝑉𝐼𝐻 − 𝑉𝑡𝑛 . 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2 = (𝑉𝐼𝐻 − 𝑉𝐷𝐷 − 𝑉𝑡𝑝 )2
2 2
NMH=𝑉𝑂𝐻 − 𝑉𝐼𝐻 =1.75 V
2.5 2. 1.43𝑉𝑜𝑢𝑡 + 1.17 − 0.6 . 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2
𝐾𝑝 NML=𝑉𝐼𝐿 − 𝑉𝑂𝐿 =1.08 V
= (1.43𝑉𝑜𝑢𝑡 + 1.17 − 3.3 + 0.7)2
2
End of Lecture